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WO2024148565A1 - 像素电路、驱动控制方法、显示基板和显示装置 - Google Patents

像素电路、驱动控制方法、显示基板和显示装置 Download PDF

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Publication number
WO2024148565A1
WO2024148565A1 PCT/CN2023/071907 CN2023071907W WO2024148565A1 WO 2024148565 A1 WO2024148565 A1 WO 2024148565A1 CN 2023071907 W CN2023071907 W CN 2023071907W WO 2024148565 A1 WO2024148565 A1 WO 2024148565A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
electrically connected
line
electrode
orthographic projection
Prior art date
Application number
PCT/CN2023/071907
Other languages
English (en)
French (fr)
Inventor
袁粲
李永谦
袁志东
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2023/071907 priority Critical patent/WO2024148565A1/zh
Priority to CN202380008168.4A priority patent/CN118742946A/zh
Publication of WO2024148565A1 publication Critical patent/WO2024148565A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving control method, a display substrate and a display device.
  • a top-emitting light-emitting device requires a transparent cathode sputtering process, which is prone to generate particles between the anode and cathode of the top-emitting light-emitting device, thereby causing a high incidence of dark spots in the display product.
  • an embodiment of the present disclosure provides a pixel circuit, including a driving circuit, a control circuit, and a light emitting unit;
  • the first end of the driving circuit is electrically connected to the power supply voltage line
  • the second end of the driving circuit is electrically connected to the first end of the light-emitting unit
  • the driving circuit is used to generate a driving current to drive the light-emitting unit under the control of the potential of its control end;
  • the control circuit is electrically connected to the first scan line, the power supply voltage line and the second end of the drive circuit respectively, and is used to control the power supply voltage line to be connected to the second end of the drive circuit under the control of the first scan signal provided by the first scan line;
  • the second end of the light emitting unit is electrically connected to the cathode voltage line.
  • a width-to-length ratio of a transistor included in the control circuit is greater than a width-to-length ratio of a transistor included in the drive circuit.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes an energy storage circuit and a data writing circuit;
  • the first end of the energy storage circuit is electrically connected to the control end of the driving circuit, and the second end of the energy storage circuit is electrically connected to the first end of the light-emitting unit; the energy storage circuit is used to store electrical energy;
  • the data writing circuit is electrically connected to the second scan line, the data line and the control end of the driving circuit respectively, and is used to write the data line under the control of the second scan signal provided by the second scan line.
  • the data voltage provided by the line is written into the control terminal of the driving circuit.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes an external compensation control circuit
  • the external compensation control circuit is electrically connected to the second scan line, the external compensation line and the second end of the drive circuit respectively, and is used to control the connection between the external compensation line and the second end of the drive circuit under the control of the second scan signal.
  • the light-emitting unit includes at least two light-emitting elements; or, the light-emitting unit includes one light-emitting element;
  • the anode of the light emitting element is electrically connected to the first end of the light emitting unit, and the cathode of the light emitting element is electrically connected to a cathode voltage line.
  • the driving circuit includes a driving transistor, and the control circuit includes a first transistor;
  • the gate of the driving transistor is electrically connected to the control terminal of the driving circuit, the first electrode of the driving transistor is electrically connected to the power supply voltage line, and the second electrode of the driving transistor is electrically connected to the first terminal of the light emitting unit;
  • a gate of the first transistor is electrically connected to a first scan line, a first electrode of the first transistor is electrically connected to the power supply voltage line, and a second electrode of the first transistor is electrically connected to a second end of the driving circuit.
  • the energy storage circuit includes a storage capacitor
  • the external control circuit includes a second transistor
  • the data writing circuit includes a third transistor
  • the first plate of the storage capacitor is electrically connected to the first end of the light emitting unit, and the second plate of the storage capacitor is electrically connected to the control end of the driving circuit;
  • the gate of the second transistor is electrically connected to the second scan line, the first electrode of the second transistor is electrically connected to the external compensation line, and the second electrode of the second transistor is electrically connected to the second end of the driving circuit;
  • a gate of the third transistor is electrically connected to the second scan line, a first electrode of the third transistor is electrically connected to the data line, and a second electrode of the third transistor is electrically connected to the control end of the driving circuit.
  • an embodiment of the present disclosure provides a drive control method, which is applied to the above-mentioned pixel circuit, and the drive control method includes:
  • the cathode voltage line provides a high voltage signal, and the power voltage line provides a low voltage signal; or, the cathode The voltage line provides a low voltage signal, and the power voltage line provides a high voltage signal;
  • the data writing circuit writes the data voltage provided by the data line into the control end of the driving circuit to control the driving circuit to disconnect the connection between its first end and the second end. Thereafter, the control circuit controls the power supply voltage line to be connected to the second end of the driving circuit under the control of the first scanning signal.
  • an embodiment of the present disclosure provides a display substrate, including a base substrate and a plurality of rows and columns of the above-mentioned pixel circuits arranged on the base substrate.
  • the pixel circuit includes a driving transistor, a first transistor, a second transistor and a third transistor;
  • the active layer pattern of the driving transistor, the active layer pattern of the first transistor, the active layer pattern of the second transistor and the active layer pattern of the third transistor are arranged in the same layer;
  • the active layer pattern of the third transistor and the active layer pattern of the driving transistor are arranged along a first direction;
  • the active layer pattern of the second transistor and the active layer pattern of the first transistor are arranged along a first direction;
  • the active layer pattern of the driving transistor and the active layer pattern of the first transistor are arranged along a second direction;
  • the first direction and the second direction intersect.
  • the pixel circuit includes a storage capacitor
  • the first electrode plate of the storage capacitor includes a first electrode plate portion and a second electrode plate portion;
  • the first plate portion, the second plate of the storage capacitor and the second plate portion are sequentially stacked in a direction away from the substrate plate, and the first plate portion is electrically connected to the second plate portion;
  • the orthographic projection of the first electrode portion on the base substrate, the orthographic projection of the second electrode portion on the base substrate, and the orthographic projection of the second electrode portion on the base substrate at least partially overlap.
  • the display substrate described in at least one embodiment of the present disclosure further includes an auxiliary cathode electrode line, and the pixel circuit includes a light-emitting element; the auxiliary cathode electrode line is arranged on a first side of the pixel circuit;
  • the auxiliary cathode electrode line extends along a third direction, and the third direction intersects with the first direction;
  • the auxiliary cathode electrode line is electrically connected to the cathode of the light emitting element.
  • the auxiliary cathode electrode line is electrically connected to an auxiliary connection pattern, and the auxiliary connection pattern and the auxiliary cathode electrode line are arranged in different layers.
  • the auxiliary cathode electrode line is electrically connected to the first connection pattern
  • the first connection pattern is electrically connected to the second connection pattern, and the first connection pattern and the second connection pattern are located in different layers; the second connection pattern is arranged in the same layer as the anode of the light-emitting element;
  • the second connection pattern is electrically connected to the third connection pattern, and the third connection pattern is arranged on a side of the second connection pattern away from the base substrate;
  • the third connection pattern is electrically connected to the cathode of the light emitting element, and the cathode of the light emitting element is arranged on a side of the third connection pattern away from the base substrate.
  • the orthographic projection of the third connection pattern on the base substrate is within the orthographic projection of the second connection pattern on the base substrate.
  • the pixel circuit includes a light-emitting element; the display substrate further includes a reflective electrode;
  • the reflective electrode is disposed between the anode of the light-emitting element and the cathode of the light-emitting element;
  • the orthographic projection of the reflective electrode on the base substrate at least partially overlaps with the orthographic projection of the anode of the light-emitting element on the base substrate; the reflective electrode is opaque, and the reflective electrode is electrically connected to the anode of the light-emitting element.
  • the display substrate described in at least one embodiment of the present disclosure further includes a light shielding pattern, at least a portion of which is disposed between the active layer pattern of the driving transistor and the base substrate, and the active layer pattern of the driving transistor is disposed in the same layer as the active layer pattern of the first transistor;
  • the orthographic projection of the active layer pattern of the driving transistor on the base substrate at least partially overlaps with the orthographic projection of the light shielding pattern on the base substrate;
  • An orthographic projection of the active layer pattern of the first transistor on the base substrate at least partially overlaps with an orthographic projection of the light shielding pattern on the base substrate.
  • the display substrate described in at least one embodiment of the present disclosure further includes a power voltage line and a data line;
  • the power supply voltage line is arranged on the second side of the pixel circuit; the data line is arranged on the first side of the pixel circuit;
  • the first side and the second side are opposite sides.
  • an embodiment of the present disclosure provides a display device, comprising the above-mentioned display substrate.
  • the display substrate comprises a plurality of columns of auxiliary cathode electrode lines and a plurality of rows and columns of minimum repeating units arranged on the base substrate;
  • the minimum repeating unit includes at least three pixel circuits
  • the at least three pixel circuits are electrically connected to different data lines respectively, and the at least three pixel circuits are electrically connected to a power supply voltage line and an external compensation line; the at least three pixel circuits are electrically connected to a first scan line and a second scan line;
  • the auxiliary cathode electrode lines, the data lines, the power supply voltage lines and the external compensation lines extend along a third direction, and portions of the first scan lines and the second scan lines extend along a first direction intersecting the third direction.
  • the display substrate includes a pixel circuit area and a transparent area; the minimum repeating unit is arranged in the pixel circuit area;
  • the transparent area is arranged on a first side of the pixel circuit area and a second side of the pixel circuit area;
  • the second scanning line is disposed on a third side of the transparent area, and the first scanning line is disposed on a fourth side of the transparent area; the third side and the fourth side are opposite sides.
  • the first scan line includes at least two first scan line portions extending along the first direction, and at least two second scan line portions extending along the first direction;
  • the second scan line includes at least two third scan line portions extending along the first direction, and at least two fourth scan line portions extending along the first direction;
  • the orthographic projection of the first scan line portion on the base substrate overlaps with the orthographic projection of the auxiliary cathode electrode line on the base substrate, the orthographic projection of the first scan line portion on the base substrate overlaps with the orthographic projection of the data line on the base substrate, and the orthographic projection of the first scan line portion on the base substrate overlaps with the orthographic projection of the external compensation line on the base substrate;
  • the orthographic projection of the second scanning line portion on the base substrate overlaps with the orthographic projection of the power supply voltage line on the base substrate;
  • the orthographic projection of the third scanning line portion on the base substrate is parallel to the auxiliary cathode electrode line.
  • the orthographic projections on the base substrate partially overlap, the orthographic projections of the first scan line portion on the base substrate partially overlap with the orthographic projections of the data line on the base substrate, and the orthographic projections of the third scan line portion on the base substrate partially overlap with the orthographic projections of the external compensation line on the base substrate;
  • An orthographic projection of the fourth scan line portion on the base substrate partially overlaps with an orthographic projection of the power supply voltage line on the base substrate.
  • FIG1 is a structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG4 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG5 is a schematic diagram of a working state of at least one embodiment of the pixel circuit shown in FIG4 of the present disclosure
  • FIG6 is a schematic diagram of a working state of at least one embodiment of the pixel circuit shown in FIG4 of the present disclosure
  • FIG7 is a circuit diagram showing at least one embodiment of a minimum repeating unit included in a substrate
  • FIG8 is a layout diagram of a portion of at least one embodiment of the pixel circuit shown in FIG4 of the present disclosure.
  • FIG9 is a layout diagram of the light shielding layer in FIG8.
  • FIG. 10 and 11 are layout diagrams of the semiconductor layer in FIG. 8;
  • FIG12 is a layout diagram of the gate metal layer in FIG8;
  • FIG13 is a layout diagram of the source/drain metal layer in FIG8 ;
  • FIG14 is a stacking diagram of the light shielding layer and the semiconductor layer in FIG8;
  • FIG15 is a stacking diagram of the semiconductor layer and the gate metal layer in FIG8;
  • FIG16 is a stacking diagram of the gate metal layer and the source/drain metal layer in FIG14 ;
  • FIG17 is a schematic diagram of adding vias penetrating the interlayer dielectric layer in the stack diagram of the light shielding layer, the semiconductor layer and the gate metal layer in FIG8;
  • FIG18 is a layout diagram of at least one embodiment of the minimum repeating unit shown in FIG7;
  • FIG19 is a layout diagram of the light shielding layer in FIG18.
  • FIG20 is a layout diagram of the semiconductor layer in FIG18.
  • FIG21 is a layout diagram of the gate metal layer in FIG18.
  • FIG22 is a layout diagram of the source/drain metal layer in FIG18 ;
  • Fig. 23 is the solid line frame in Fig. 18;
  • FIG24 is a layout diagram of the anode layer in FIG18.
  • FIG25 is a layout diagram of the electrode layer in FIG18.
  • Fig. 26 is the dotted box in Fig. 18;
  • FIG27 is a stacking diagram of the light shielding layer and the semiconductor layer in FIG18
  • FIG28 is a stacking diagram of the light shielding layer, the semiconductor layer and the gate metal layer in FIG18;
  • FIG29 is a schematic diagram of additionally providing via holes penetrating the interlayer dielectric layer on the basis of FIG28.
  • the icons with multiplication signs inside the boxes are via holes penetrating the interlayer dielectric layer;
  • FIG30 is a stacked diagram of the light shielding layer, the semiconductor layer, the gate metal layer and the source-drain metal layer in FIG18;
  • FIG31 is a schematic diagram showing a solid line frame added to FIG30;
  • FIG32 is a schematic diagram showing a via hole penetrating the passivation layer based on FIG31;
  • FIG33 is a stacking diagram showing an additional anode layer based on FIG32;
  • FIG34 is a stacking diagram showing an additional electrode layer based on FIG33;
  • FIG35 is a schematic diagram of the stacking of the anode layer and the electrode layer in FIG18;
  • FIG36 is a schematic diagram of the stacking of the source/drain metal layer and the anode layer in FIG18 ;
  • FIG37 is a cross-sectional view taken along line A-A’ in FIG18 .
  • FIG38 is a schematic diagram showing a configuration in which a light-emitting material layer and a cathode layer are provided on the basis of FIG37 .
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the electrodes is called the first electrode and the other is called the second electrode.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, The second electrode may be a drain electrode.
  • the pixel circuit described in the embodiment of the present disclosure includes a driving circuit 11 , a control circuit 12 and a light emitting unit 10 ;
  • the first end of the driving circuit 11 is electrically connected to the power supply voltage line VDD, and the second end of the driving circuit 11 is electrically connected to the first end of the light emitting unit 10.
  • the driving circuit 11 is used to generate a driving current to drive the light emitting unit 10 under the control of the potential of its control end;
  • the control circuit 12 is electrically connected to the first scan line G1, the power supply voltage line VDD and the second end of the drive circuit 11 respectively, and is used to control the power supply voltage line VDD to be connected to the second end of the drive circuit 11 under the control of the first scan signal provided by the first scan line G1;
  • the second end of the light emitting unit 10 is electrically connected to the cathode voltage line VS.
  • the pixel circuit described in the embodiment of the present disclosure adds a control circuit 12 to increase the branch current by increasing the forward voltage and the reverse voltage, thereby burning out the particles (foreign matter) at the dark spots, turning the dark spots into normal pixels, and improving product yield and display quality.
  • the width-to-length ratio of the transistor included in the control circuit 12 is greater than the width-to-length ratio of the transistor included in the drive circuit 11 .
  • the transistor included in the control circuit 12 can be a channel enhancement TFT (thin film transistor), which has a larger width-to-length ratio and can improve the current limiting on the TFT branch, thereby increasing the branch current by increasing the forward voltage and the reverse voltage, thereby burning out the particles at the dark spot.
  • TFT thin film transistor
  • the pixel circuit described in at least one embodiment of the present disclosure further includes an energy storage circuit and a data writing circuit;
  • the first end of the energy storage circuit is electrically connected to the control end of the driving circuit, and the second end of the energy storage circuit is electrically connected to the first end of the light-emitting unit; the energy storage circuit is used to store electrical energy;
  • the data writing circuit is electrically connected to the second scan line, the data line and the control end of the driving circuit respectively, and is used to write the data voltage provided by the data line into the control end of the driving circuit under the control of the second scan signal provided by the second scan line.
  • the pixel circuit may further include an energy storage circuit and a data writing circuit.
  • the data writing circuit writes the data voltage provided by the data line into the control terminal of the driving circuit under the control of the second scanning signal.
  • the pixel circuit further includes an external compensation control circuit
  • the external compensation control circuit is electrically connected to the second scan line, the external compensation line and the second end of the drive circuit respectively, and is used to control the connection between the external compensation line and the second end of the drive circuit under the control of the second scan signal.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include an external compensation control circuit, which controls the connection between the external compensation line and the second end of the driving circuit under the control of the second scanning signal.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a storage circuit 21 , a data writing circuit 22 and an external compensation control circuit 23 ;
  • the first end of the energy storage circuit 21 is electrically connected to the control end of the driving circuit 11, and the second end of the energy storage circuit 21 is electrically connected to the first end of the light emitting unit 10; the energy storage circuit 21 is used to store electrical energy;
  • the data writing circuit 22 is electrically connected to the second scanning line G2, the data line Da and the control terminal of the driving circuit 11 respectively, and is used to write the data voltage provided by the data line Da into the control terminal of the driving circuit 11 under the control of the second scanning signal provided by the second scanning line G2;
  • the external compensation control circuit 23 is electrically connected to the second scan line G2, the external compensation line Sn and the second end of the drive circuit 11 respectively, and is used to control the connection between the external compensation line Sn and the second end of the drive circuit 11 under the control of the second scan signal.
  • At least one embodiment of the driving circuit shown in FIG. 2 of the present disclosure is in operation.
  • the cathode voltage line provides a high voltage signal, and the power voltage line provides a low voltage signal;
  • the data writing circuit writes the data voltage provided by the data line into the control end of the driving circuit to control the driving circuit to disconnect the connection between the first end and the second end.
  • the control circuit controls the connection between the power supply voltage line and the second end of the driving circuit under the control of the first scanning signal to apply a reverse voltage to the light-emitting element included in the light-emitting unit 10 to burn out the Particle at the light-emitting element.
  • At least one embodiment of the driving circuit shown in FIG. 2 of the present disclosure is in operation.
  • the cathode voltage line provides a low voltage signal, and the power voltage line provides a high voltage signal
  • the data writing circuit writes the data voltage provided by the data line into the control end of the driving circuit under the control of the second scanning signal, so as to control the driving circuit to disconnect the connection between the first end and the second end.
  • the control circuit controls the power supply voltage line to be connected to the second end of the driving circuit under the control of the first scanning signal, so as to apply a forward voltage to the light-emitting element included in the light-emitting unit 10, so as to burn out the Particle at the light-emitting element.
  • the light-emitting unit includes at least two light-emitting elements; or, the light-emitting unit includes one light-emitting element;
  • the anode of the light emitting element is electrically connected to the first end of the light emitting unit, and the cathode of the light emitting element is electrically connected to a cathode voltage line.
  • the light emitting element may be a top emitting light emitting element, but is not limited thereto.
  • the light emitting element may be an organic light emitting diode, but is not limited thereto.
  • the light emitting unit includes a first organic light emitting diode O1 and a second organic light emitting diode O2 ;
  • An anode of the first organic light emitting diode O1 is electrically connected to the second end of the driving circuit 11, and a cathode of the first organic light emitting diode O1 is electrically connected to a cathode voltage line VS;
  • An anode of the second organic light emitting diode O2 is electrically connected to the second end of the driving circuit 11 , and a cathode of the second organic light emitting diode O2 is electrically connected to the cathode voltage line VS.
  • the driving circuit includes a driving transistor, and the control circuit includes a first transistor;
  • the gate of the driving transistor is electrically connected to the control terminal of the driving circuit, the first electrode of the driving transistor is electrically connected to the power supply voltage line, and the second electrode of the driving transistor is electrically connected to the first terminal of the light emitting unit;
  • a gate of the first transistor is electrically connected to a first scan line, a first electrode of the first transistor is electrically connected to the power supply voltage line, and a second electrode of the first transistor is electrically connected to a second end of the driving circuit.
  • a width-to-length ratio of the first transistor is greater than a width-to-length ratio of the driving transistor.
  • the energy storage circuit includes a storage capacitor
  • the external control circuit includes a second transistor
  • the data writing circuit includes a third transistor
  • the first plate of the storage capacitor is electrically connected to the first end of the light emitting unit, and the second plate of the storage capacitor is electrically connected to the control end of the driving circuit;
  • the gate of the second transistor is electrically connected to the second scan line, the first electrode of the second transistor is electrically connected to the external compensation line, and the second electrode of the second transistor is electrically connected to the second end of the driving circuit;
  • a gate of the third transistor is electrically connected to the second scan line, a first electrode of the third transistor is electrically connected to the data line, and a second electrode of the third transistor is electrically connected to the control end of the driving circuit.
  • the driving circuit includes a driving transistor Td, and the control circuit includes a first transistor T1;
  • the first electrode of the driving transistor Td is electrically connected to the power supply voltage line VDD, and the second electrode of the driving transistor Td is electrically connected to the anode of the first organic light emitting diode O1 and the anode of the second organic light emitting diode O2 respectively;
  • the gate of the first transistor T1 is electrically connected to the first scan line G1, the first electrode of the first transistor T1 is electrically connected to the power supply voltage line VDD, and the second electrode of the first transistor T1 is electrically connected to the second electrode of the driving transistor Td;
  • the energy storage circuit includes a storage capacitor C1, the external control circuit includes a second transistor T2, and the data writing circuit includes a third transistor T3;
  • the first electrode plate of the storage capacitor C1 is electrically connected to the anode of the first organic light emitting diode O1 and the anode of the second organic light emitting diode O2 respectively, and the second electrode plate of the storage capacitor C1 is electrically connected to the gate of the driving transistor Td;
  • the gate of the second transistor T2 is electrically connected to the second scan line G2, the first electrode of the second transistor T2 is electrically connected to the external compensation line Sn, and the second electrode of the second transistor T2 is electrically connected to the second electrode of the driving transistor Td;
  • a gate electrode of the third transistor T3 is electrically connected to the second scan line G2 , a first electrode of the third transistor T3 is electrically connected to the data line Da, and a second electrode of the third transistor T3 is electrically connected to the gate electrode of the driving transistor Td.
  • the width-to-length ratio of T1 may be greater than the width-to-length ratio of Td.
  • all transistors are n-type transistors, but the present invention is not limited thereto.
  • O1 and O2 may be reversely pressurized, that is, VS provides a high voltage signal and VDD provides a low voltage signal;
  • G1 provides a high voltage signal
  • G2 provides a high voltage signal
  • T1, T2 and T3 are all turned on
  • Da provides a low voltage signal to the gate of Td
  • Td is turned off;
  • G1 provides a high voltage signal
  • G2 provides a low voltage signal
  • T1 is turned on
  • T1 is a channel enhancement TFT.
  • the current flows from the cathode of O1 to the anode of O1, and the current flows from the cathode of O2 to the anode of O2, and the Particle at the organic light emitting diode is burned out by reverse voltage.
  • O1 and O2 may be positively pressurized, that is, VS provides a low voltage signal and VDD provides a high voltage signal;
  • G1 provides a high voltage signal
  • G2 provides a high voltage signal
  • T1, T2 and T3 are all turned on
  • Da provides a low voltage signal to the gate of Td
  • Td is turned off;
  • G1 provides a high voltage signal
  • G2 provides a low voltage signal
  • T1 is turned on
  • T1 is a channel enhancement TFT.
  • the current flows from the anode of O1 to the cathode of O1, and the current flows from the anode of O2 to the cathode of O2, and the particle at the organic light emitting diode is burned out by positive pressure.
  • the pixel circuit does not include the first transistor T1. Since the aspect ratios of Td, T2 and T3 are relatively small, the current limiting is serious, and a large current cannot be provided, and the current carrying capacity is weak. Based on this, at least one embodiment of the present disclosure adds a first transistor T1.
  • the first transistor T1 is a channel enhancement TFT, which can increase the branch current and turn the dark spot into a normal spot, thereby protecting the organic light emitting diode from damage, ensuring the yield of the display product, and improving the picture quality.
  • FIG. 7 is a circuit diagram of at least one embodiment of a minimal repeating unit included in a display substrate.
  • the display substrate may include multiple rows and columns of the minimal repeating unit.
  • At least one embodiment of the minimum repeating unit may include a first pixel circuit, a second pixel circuit, a third pixel circuit, and a fourth pixel circuit;
  • the first pixel circuit includes a first driving transistor Td1, a first first transistor T11, a first second transistor T12, a first third transistor T13, a first storage capacitor C11, a first white organic light emitting diode O11 and a second white organic light emitting diode O12;
  • a first electrode of the first driving transistor Td1 is electrically connected to the power supply voltage line VDD, and a second electrode of the first driving transistor Td1 is electrically connected to an anode of the first white organic light emitting diode O11 and an anode of the second white organic light emitting diode O12 respectively;
  • the gate of the first first transistor T11 is electrically connected to the first scan line G1, the first electrode of the first first transistor T11 is electrically connected to the power supply voltage line VDD, and the second electrode of the first first transistor T11 is electrically connected to the second electrode of the first driving transistor Td1;
  • the second electrode plate of the first storage capacitor C11 is electrically connected to the gate of the first driving transistor Td1, and the first electrode plate of the first storage capacitor C11 is electrically connected to the anode of the first white organic light emitting diode O11 and the anode of the second white organic light emitting diode O12 respectively;
  • the gate of the first second transistor T12 is electrically connected to the second scan line G2, the first electrode of the first second transistor T12 is electrically connected to the external compensation line Sn, and the second electrode of the first second transistor T12 is electrically connected to the second electrode of the first driving transistor Td1;
  • the gate of the first third transistor T13 is electrically connected to the second scan line G2, the first electrode of the first third transistor T13 is electrically connected to the white data line Da_w, and the second electrode of the first third transistor T13 is electrically connected to the gate of the first driving transistor Td1;
  • the second pixel circuit includes a second driving transistor Td2, a second first transistor T21, a second second transistor T22, a second third transistor T23, a second storage capacitor C12, a first green organic light emitting diode O21 and a second green organic light emitting diode O22;
  • a first electrode of the second driving transistor Td2 is electrically connected to the power voltage line VDD, and a second electrode of the second driving transistor Td2 is electrically connected to an anode of the first green organic light emitting diode O21 and an anode of the second green organic light emitting diode O22 respectively;
  • the gate of the second first transistor T21 is electrically connected to the first scan line G1, the first electrode of the second first transistor T21 is electrically connected to the power supply voltage line VDD, and the second electrode of the second first transistor T21 is electrically connected to the second electrode of the second driving transistor Td2;
  • the second electrode plate of the second storage capacitor C12 is electrically connected to the gate of the second driving transistor Td2, and the first electrode plate of the second storage capacitor C12 is electrically connected to the anode of the first green organic light emitting diode O21 and the anode of the second green organic light emitting diode O22 respectively;
  • the gate of the second second transistor T22 is electrically connected to the second scan line G2, the first electrode of the second second transistor T22 is electrically connected to the external compensation line Sn, and the second electrode of the second second transistor T22 is electrically connected to the second electrode of the second driving transistor Td2;
  • the gate electrode of the second third transistor T23 is electrically connected to the second scan line G2, the first electrode of the second third transistor T23 is electrically connected to the green data line Da_g, and the second A second electrode of the third transistor T23 is electrically connected to the gate of the second driving transistor Td2;
  • the third pixel circuit includes a third driving transistor Td3, a third first transistor T31, a third second transistor T32, a third third transistor T33, a third storage capacitor C13, a first red organic light emitting diode O31 and a second red organic light emitting diode O32;
  • a first electrode of the third driving transistor Td3 is electrically connected to the power voltage line VDD, and a second electrode of the third driving transistor Td3 is electrically connected to an anode of the first red organic light emitting diode O31 and an anode of the second red organic light emitting diode O32 respectively;
  • the gate of the third first transistor T31 is electrically connected to the first scan line G1, the first electrode of the third first transistor T31 is electrically connected to the power supply voltage line VDD, and the second electrode of the third first transistor T31 is electrically connected to the second electrode of the third driving transistor Td3;
  • the second electrode plate of the third storage capacitor C13 is electrically connected to the gate of the third driving transistor Td3, and the first electrode plate of the third storage capacitor C13 is electrically connected to the anode of the first red organic light emitting diode O31 and the anode of the second red organic light emitting diode O32 respectively;
  • the gate of the third second transistor T32 is electrically connected to the second scan line G2, the first electrode of the third second transistor T32 is electrically connected to the external compensation line Sn, and the second electrode of the third second transistor T32 is electrically connected to the second electrode of the third driving transistor Td3;
  • the gate of the third third transistor T33 is electrically connected to the second scan line G2, the first electrode of the third third transistor T33 is electrically connected to the red data line Da_r, and the second electrode of the third third transistor T33 is electrically connected to the gate of the third driving transistor Td3;
  • the fourth pixel circuit includes a fourth driving transistor Td4, a fourth first transistor T41, a fourth second transistor T42, a fourth third transistor T43, a fourth storage capacitor C14, a first blue organic light emitting diode O41 and a second blue organic light emitting diode O42;
  • a first electrode of the fourth driving transistor Td4 is electrically connected to the power voltage line VDD, and a second electrode of the fourth driving transistor Td4 is electrically connected to an anode of the first blue organic light emitting diode O41 and an anode of the second blue organic light emitting diode O42 respectively;
  • the gate of the fourth first transistor T41 is electrically connected to the first scan line G1, the first electrode of the fourth first transistor T41 is electrically connected to the power supply voltage line VDD, and the second electrode of the fourth first transistor T41 is electrically connected to the second electrode of the fourth driving transistor Td4;
  • the second electrode plate of the fourth storage capacitor C14 is connected to the gate electrode of the fourth driving transistor Td4.
  • the first electrode plate of the fourth storage capacitor C14 is electrically connected to the anode of the first blue organic light emitting diode O41 and the anode of the second blue organic light emitting diode O42 respectively;
  • the gate of the fourth third transistor T43 is electrically connected to the second scan line G2, the first electrode of the fourth third transistor T43 is electrically connected to the blue data line Da_b, and the second electrode of the fourth third transistor T43 is electrically connected to the gate of the fourth driving transistor Td4;
  • all transistors are n-type transistors, but the present invention is not limited thereto.
  • the external compensation line Sn, the white data line Da_w, the green data line Da_g, the red data line Da_r, and the blue data line Da_b are all disposed on the left side of each pixel circuit, and the external compensation line Sn, the white data line Da_w, the green data line Da_g, the red data line Da_r, and the blue data line Da_b are all extended in the vertical direction;
  • the power supply voltage line VDD extends in a vertical direction, and the power supply voltage line VDD may be arranged on the right side of each pixel circuit;
  • the first scan line G1 is disposed below each pixel circuit, and most of the first scan line G1 extends in the horizontal direction;
  • the second scan line G2 is disposed above each pixel circuit, and most of the second scan line G2 extends in the horizontal direction;
  • the auxiliary cathode electrode line Ax extends in a vertical direction, and the auxiliary cathode electrode line Ax may be disposed on the left side of each pixel circuit.
  • a white pixel circuit, a green pixel circuit, a red pixel circuit, and a blue pixel circuit are arranged in sequence along a vertical direction.
  • the minimum repeating unit may include at least three pixel circuits, and the at least three pixel circuits are pixel circuits with different colors;
  • the minimum repeating unit when the minimum repeating unit includes a first pixel circuit, a second pixel circuit, a third pixel circuit and a fourth pixel circuit, the first pixel circuit, the second pixel circuit, the third pixel circuit and the fourth pixel circuit can be arranged in sequence along the vertical direction, and the first pixel circuit can be a red pixel circuit.
  • the second pixel circuit may be one of a red pixel circuit, a green pixel circuit, a blue pixel circuit, and a white pixel circuit
  • the third pixel circuit may be one of a red pixel circuit, a green pixel circuit, a blue pixel circuit, and a white pixel circuit
  • the fourth pixel circuit may be one of a red pixel circuit, a green pixel circuit, a blue pixel circuit, and a white pixel circuit
  • the color corresponding to the first pixel circuit, the color corresponding to the second pixel circuit, the color corresponding to the third pixel circuit, and the color corresponding to the fourth pixel circuit are different from each other;
  • the first pixel circuit, the second pixel circuit, and the third pixel circuit can be arranged in sequence along the vertical direction
  • the first pixel circuit can be one of a red pixel circuit, a green pixel circuit, and a blue pixel circuit
  • the second pixel circuit can be one of a red pixel circuit, a green pixel circuit, and a blue pixel circuit
  • the third pixel circuit can be one of a red pixel circuit, a green pixel circuit, and a blue pixel circuit
  • the color corresponding to the first pixel circuit, the color corresponding to the second pixel circuit, and the color corresponding to the third pixel circuit are different from each other.
  • the driving control method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the driving control method includes:
  • the cathode voltage line provides a high voltage signal, and the power supply voltage line provides a low voltage signal; or, the cathode voltage line provides a low voltage signal, and the power supply voltage line provides a high voltage signal;
  • the data writing circuit writes the first voltage signal provided by the data line into the control end of the driving circuit to control the driving circuit to disconnect the connection between its first end and the second end. Thereafter, the control circuit controls the power supply voltage line to be connected to the second end of the driving circuit under the control of the first scanning signal.
  • the display substrate described in the embodiment of the present disclosure includes a base substrate and a plurality of rows and columns of the above-mentioned pixel circuits arranged on the base substrate.
  • the pixel circuit includes a driving transistor, a first transistor, a second transistor and a third transistor;
  • the active layer pattern of the driving transistor, the active layer pattern of the first transistor, the active layer pattern of the second transistor and the active layer pattern of the third transistor are arranged in the same layer;
  • the active layer pattern of the second transistor and the active layer pattern of the first transistor are arranged along a first direction;
  • the active layer pattern of the driving transistor and the active layer pattern of the first transistor are arranged along a second direction;
  • the first direction and the second direction intersect.
  • Figure 8 is a partial layout diagram of at least one embodiment of the pixel circuit shown in Figure 4 of the present disclosure
  • Figure 9 is a layout diagram of the light shielding layer in Figure 8
  • Figures 10 and 11 are layout diagrams of the semiconductor layer in Figure 8
  • Figure 12 is a layout diagram of the gate metal layer in Figure 8
  • Figure 13 is a layout diagram of the source and drain metal layer in Figure 8.
  • the driving transistor is labeled Td
  • the first transistor is labeled T1
  • the second transistor is labeled T2
  • the third transistor is labeled T3
  • the auxiliary cathode electrode line is labeled Ax
  • the data line is labeled Da
  • the external compensation line is labeled Sn
  • the power supply voltage line is labeled VDD.
  • FIG. 14 is a stacking diagram of the light shielding layer and the semiconductor layer in FIG. 8
  • FIG. 15 is a stacking diagram of the semiconductor layer and the gate metal layer in FIG. 8
  • FIG. 16 is a stacking diagram of the gate metal layer and the source/drain metal layer in FIG. 14 ;
  • FIG. 17 is a schematic diagram of adding vias penetrating the interlayer dielectric layer in the stack diagram of the light shielding layer, the semiconductor layer and the gate metal layer in FIG. 8 .
  • the icons with a multiplication sign inside the boxes are vias penetrating the interlayer dielectric layer.
  • the light-shielding pattern formed on the light-shielding layer needs to be electrically connected to the pattern formed on the source-drain metal layer, and the thickness of the insulating layer between the light-shielding layer and the source-drain metal layer is relatively large. Therefore, holes can be punched in the form of sleeve holes, and the punching method can be used twice to form a via hole for electrically connecting the light-shielding pattern on the light-shielding layer with the pattern formed on the source-drain metal layer.
  • Ad is an active layer pattern of the driving transistor Td
  • A1 is an active layer pattern of the first transistor T1
  • A2 is an active layer pattern of the second transistor T2
  • A3 is an active layer pattern of the third transistor T3.
  • the active layer pattern Ad of the driving transistor Td, the active layer pattern A1 of the first transistor T1, the active layer pattern A2 of the second transistor T2 and the active layer pattern A3 of the third transistor T3 are arranged in the same layer;
  • A3 and Ad are arranged in the horizontal direction;
  • A2 and A1 are arranged in the horizontal direction;
  • Ad and A1 are arranged in the vertical direction.
  • the first direction may be a horizontal direction
  • the second direction may be a vertical direction, but the present invention is not limited thereto.
  • the pixel circuit includes a storage capacitor
  • the first electrode plate of the storage capacitor includes a first electrode plate portion and a second electrode plate portion;
  • the first plate portion, the second plate of the storage capacitor and the second plate portion are stacked in sequence in a direction away from the substrate plate, and the first plate portion is electrically connected to the second plate portion;
  • the orthographic projection of the first electrode portion on the base substrate, the orthographic projection of the second electrode portion on the base substrate, and the orthographic projection of the second electrode portion on the base substrate at least partially overlap.
  • the first electrode plate of the storage capacitor includes a first electrode plate portion and a second electrode plate portion which are electrically connected to each other.
  • the first electrode plate portion, the second electrode plate of the storage capacitor and the second electrode plate portion are stacked in sequence along a direction away from the substrate electrode plate.
  • the orthographic projection of the first electrode plate portion on the substrate substrate, the orthographic projection of the second electrode plate portion on the substrate substrate and the orthographic projection of the second electrode plate on the substrate substrate at least partially overlap, so as to increase the capacitance value of the storage capacitor.
  • the first plate portion of the first plate of the storage capacitor is labeled C1a1
  • the second plate of the storage capacitor is labeled C1b ;
  • C1a2 is a second plate portion included in the first plate of the storage capacitor.
  • the orthographic projection of C1a1 on the substrate substrate, the orthographic projection of C1b on the substrate substrate, and the orthographic projection of C1a2 on the substrate substrate at least partially overlap;
  • C1a1 is electrically connected to C1b1 through a via.
  • the first electrode of Td is labeled Dd
  • the second electrode of Td is labeled Sd;
  • Dd is electrically connected to the power supply voltage line VDD through a via hole
  • Sd is electrically connected to C1b through a via hole
  • C1a1 is electrically connected to the second electrode Sd of Td.
  • the first plate of the storage capacitor includes a first plate portion C1a1 formed on the light shielding layer
  • the second plate C1b of the storage capacitor is formed on the semiconductor layer
  • the first plate of the storage capacitor includes a second plate portion C1a2 formed on the source-drain metal layer
  • at least a portion of C1b is disposed between C1a1 and C1a2
  • C1a1 is electrically connected to C1b1 to increase the capacitance value of the storage capacitor.
  • the display substrate further includes an auxiliary cathode electrode line, the pixel circuit includes a light-emitting element; the auxiliary cathode electrode line is arranged on a first side of the pixel circuit;
  • the auxiliary cathode electrode line extends along a third direction, and the third direction intersects with the first direction;
  • the auxiliary cathode electrode line is electrically connected to the cathode of the light emitting element.
  • the first direction may be a horizontal direction
  • the third direction may be a vertical direction, but is not limited thereto.
  • the auxiliary cathode electrode line Ax extends in a vertical direction and is disposed on the left side of a pixel circuit.
  • the pixel circuit includes a driving transistor Td, a first transistor T1 , a second transistor T2 , a third transistor T3 and a storage capacitor.
  • the first side is the left side.
  • the auxiliary cathode electrode line is electrically connected to an auxiliary connection pattern, and the auxiliary connection pattern and the auxiliary cathode electrode line are arranged in different layers.
  • the auxiliary cathode electrode line Ax can be formed in the source and drain metal layer.
  • the auxiliary connection pattern Lx is formed in the gate metal layer.
  • the auxiliary cathode electrode line Ax and the auxiliary connection pattern Lx are electrically connected through a via to reduce the resistance of the auxiliary cathode electrode line Ax.
  • the auxiliary cathode electrode line Ax is electrically connected to a cathode layer, and the cathode of the light emitting element is formed on the cathode layer.
  • the light-emitting element can be a top-emitting light-emitting element
  • the cathode of the light-emitting element is a transparent cathode. Since the resistance of the transparent cathode is relatively large, in order to reduce the resistance of the cathode of the light-emitting element, at least one embodiment of the present disclosure sets the cathode layer to be electrically connected to the auxiliary cathode electrode line Ax, and sets the auxiliary cathode electrode line Ax to be electrically connected to the auxiliary connection pattern Lx to reduce the resistance of the cathode of the light-emitting element.
  • the display substrate described in at least one embodiment of the present disclosure further includes a light shielding pattern, at least a portion of which is disposed between the active layer pattern of the driving transistor and the base substrate, and the active layer pattern of the driving transistor is disposed in the same layer as the active layer pattern of the first transistor;
  • the orthographic projection of the active layer pattern of the driving transistor on the base substrate at least partially overlaps with the orthographic projection of the light shielding pattern on the base substrate;
  • An orthographic projection of the active layer pattern of the first transistor on the base substrate at least partially overlaps with an orthographic projection of the light shielding pattern on the base substrate.
  • C1a1 is multiplexed as the first light-shielding pattern, and the pattern labeled Z2 is the second light-shielding pattern.
  • the active layer pattern Ad of the driving transistor and the active layer pattern A1 of the first transistor T1 are both formed in the semiconductor layer.
  • the orthographic projection of the active layer pattern Ad of the driving transistor on the substrate at least partially overlaps with the orthographic projection of C1a1 on the substrate to reduce the light exposure of the active layer pattern Ad of the driving transistor and improve the threshold voltage drift phenomenon of the driving transistor.
  • the orthographic projection of the active layer pattern A1 of the first transistor on the substrate at least partially overlaps with the orthographic projection of Z2 on the substrate to reduce the light exposure of the active layer pattern A1 of the first transistor and improve the threshold voltage drift phenomenon of the first transistor.
  • the light shielding layer may be a metal layer.
  • the light shielding layer may be made of Mo (molybdenum), but is not limited thereto.
  • the display substrate may further include a power voltage line and a data line;
  • the power supply voltage line is arranged on the second side of the pixel circuit; the data line is arranged on the first side of the pixel circuit;
  • the first side and the second side are opposite sides.
  • the line labeled VDD is a power supply voltage line
  • the line labeled Da is a data line
  • the power voltage line VDD is arranged on the right side of the pixel circuit, and the data line Da is arranged on the left side of the pixel circuit.
  • the first side may be the left side
  • the second side may be the right side.
  • G1 is the gate of T1
  • G2 is the gate of T2
  • G3 is the gate of T3
  • Gd is the gate of Td.
  • the first electrode of T1 is labeled D1
  • the second electrode of T1 is labeled S1 .
  • FIG. 18 is a layout diagram of at least one embodiment of the minimal repeating unit shown in FIG. 7 .
  • a pixel defining layer is disposed outside the dotted line frame, and a first insulating layer is disposed outside the solid line frame.
  • the first insulating layer may be, for example, a resin layer.
  • FIG. 19 is a layout diagram of the light shielding layer in FIG. 18
  • FIG. 20 is a layout diagram of the semiconductor layer in FIG. 18
  • FIG. 21 is a layout diagram of the gate metal layer in FIG. 18
  • FIG. 22 is a layout diagram of the source/drain metal layer in FIG. 18 ,
  • FIG23 is a solid-line frame in FIG18 , outside the solid-line frame, a first insulating layer is provided, and inside the solid-line frame, the first insulating layer is not provided;
  • FIG24 is a layout diagram of the anode layer in FIG18;
  • FIG25 is a layout diagram of the electrode layer in FIG18;
  • FIG26 is the dotted frame in FIG18 , wherein a pixel defining layer is provided outside the dotted frame, and no pixel defining layer is provided inside the dotted frame.
  • a light shielding layer, a semiconductor layer, a gate metal layer, a source-drain metal layer, an anode layer, an electrode layer and a pixel defining layer are sequentially stacked on a base substrate;
  • An interlayer dielectric layer is provided between the gate metal layer and the source/drain metal layer;
  • a first insulating layer and a passivation layer are arranged between the source-drain metal layer and the anode layer.
  • the first insulating layer is arranged between the source-drain metal layer and the passivation layer, and the passivation layer is arranged between the first insulating layer and the anode layer.
  • the first insulating layer may be, for example, a resin layer.
  • the anode layer may be made of ITO (indium tin oxide), but is not limited thereto.
  • FIG27 is a stacking diagram of the light shielding layer and the semiconductor layer in FIG18
  • FIG28 is a stacking diagram of the light shielding layer, the semiconductor layer and the gate metal layer in FIG18;
  • FIG29 is a schematic diagram of additionally providing via holes penetrating the interlayer dielectric layer on the basis of FIG28.
  • the icons with multiplication signs inside the boxes are via holes penetrating the interlayer dielectric layer;
  • FIG30 is a stacked diagram of the light shielding layer, the semiconductor layer, the gate metal layer and the source-drain metal layer in FIG18;
  • FIG31 is a schematic diagram of FIG30 with a solid line frame added thereto; in FIG31 , a first insulating layer is provided outside the solid line frame, and no first insulating layer is provided inside the solid line frame;
  • FIG32 is a schematic diagram showing a via hole penetrating the passivation layer based on FIG31 ; in FIG32 , a black solid block indicates a via hole penetrating the passivation layer;
  • FIG33 is a stacking diagram showing an additional anode layer based on FIG32;
  • FIG34 is a stacking diagram showing an additional electrode layer based on FIG33;
  • FIG35 is a schematic diagram of the stacking of the anode layer and the electrode layer in FIG18;
  • FIG36 is a schematic diagram of the stacking of the source/drain metal layer and the anode layer in FIG18 .
  • the auxiliary cathode electrode line is labeled Ax
  • the white digital line is labeled Da_w.
  • Data lines the one labeled Da_g is a green data line
  • the one labeled Da_r is a red data line
  • the one labeled Da_b is a blue data line
  • the one labeled Sn is an external compensation line
  • the one labeled VDD is a power supply voltage line;
  • the first transistor is labeled T11
  • the first second transistor is labeled T12
  • the first third transistor is labeled T13
  • the first driving transistor is labeled Td1;
  • the transistor labeled T21 is the second first transistor
  • the transistor labeled T22 is the second second transistor
  • the transistor labeled T23 is the second third transistor
  • the transistor labeled Td2 is the second driving transistor
  • the transistor labeled T31 is the third first transistor
  • the transistor labeled T32 is the third second transistor
  • the transistor labeled T33 is the third third transistor
  • the transistor labeled Td3 is the third driving transistor
  • the fourth first transistor is labeled T41
  • the fourth second transistor is labeled T42
  • the fourth third transistor is labeled T43
  • the fourth driving transistor is labeled Td4.
  • C11a1 is the first electrode portion of the first electrode plate of C11
  • C12a1 is the first electrode portion of the first electrode plate of C12
  • C13a1 is the first electrode portion of the first electrode plate of C13
  • C14a1 is the first electrode portion of the first electrode plate of C14;
  • the first second light-shielding pattern is labeled Z12
  • the second second light-shielding pattern is labeled Z22
  • the third second light-shielding pattern is labeled Z32
  • the fourth second light-shielding pattern is labeled Z42;
  • C11a1 is electrically connected to the first connection portion L1
  • C12a1 is electrically connected to the second connection portion L2
  • C13a1 is electrically connected to the third connection portion L3
  • C14a1 is electrically connected to the fourth connection portion L5.
  • the anode labeled An11 is the anode of O11
  • the anode labeled An12 is the anode of O12
  • the anode labeled An21 is the anode of O21
  • the anode labeled An22 is the anode of O22
  • the anode labeled An31 is the anode of O31
  • the anode labeled An32 is the anode of O32
  • the anode labeled An41 is the anode of O41
  • the anode labeled An42 is the anode of O42.
  • L1 is electrically connected to An11 and An12 through vias, so that C11a1 is electrically connected to An11 and An12;
  • L2 is electrically connected to An21 and An22 through vias, so that C12a1 is electrically connected to An21 and An22;
  • L3 is electrically connected to An31 and An32 through vias, so that C13a1 is electrically connected to An31 and An32. connect;
  • L4 is electrically connected to An41 and An42 through a via hole, so that C14a1 is electrically connected to An41 and An42.
  • C11b is the second electrode plate of C11
  • C12b is the second electrode plate of C12
  • C13b is the second electrode plate of C13
  • C14b is the second electrode plate of C14.
  • the auxiliary cathode electrode line is electrically connected to the first connection pattern
  • the first connection pattern is electrically connected to the second connection pattern, and the first connection pattern and the second connection pattern are located in different layers; the second connection pattern is arranged in the same layer as the anode of the light-emitting element;
  • the second connection pattern is electrically connected to the third connection pattern, and the third connection pattern is arranged on a side of the second connection pattern away from the base substrate;
  • the third connection pattern is electrically connected to the cathode of the light emitting element, and the cathode of the light emitting element is arranged on a side of the third connection pattern away from the base substrate.
  • the first connection pattern may be formed in a source-drain metal layer
  • the second connection pattern may be formed in an anode layer
  • the third connection pattern may be formed in an electrode layer, but the present invention is not limited thereto.
  • the auxiliary cathode electrode line is labeled Ax
  • the external compensation line is labeled Sn
  • the power supply voltage line is labeled VDD
  • the white data line is labeled Da_w
  • the green data line is labeled Da_g
  • the red data line is labeled Da_r
  • the blue data line is labeled Da_b.
  • the auxiliary cathode electrode line Ax is electrically connected to the first first connection pattern L11 and the second first connection pattern L21 .
  • the second electrode plate portion labeled C11a2 is included in the first electrode plate of C11
  • the second electrode plate portion labeled C12a2 is included in the first electrode plate of C12
  • the second electrode plate portion labeled C13a2 is included in the first electrode plate of C13
  • the second electrode plate portion labeled C14a2 is included in the first electrode plate of C14.
  • the first second connection pattern is labeled L12
  • the second second connection pattern is labeled L22;
  • the first third connection pattern is labeled L13
  • the second third connection pattern is labeled L23.
  • a third connection graph is
  • L11 , L12 and L13 are electrically connected, and L21 , L22 and L23 are electrically connected.
  • L13 is electrically connected to the cathode layer, and L23 is electrically connected to the cathode layer, so that the auxiliary cathode electrode line Ax is electrically connected to the cathode of the organic light emitting diode in each pixel circuit;
  • the cathode of the organic light emitting diode in each pixel circuit is formed on the cathode layer, and the cathode layer is arranged on a side of the electrode layer away from the base substrate.
  • the orthographic projection of the third connection pattern on the base substrate is within the orthographic projection of the second connection pattern on the base substrate.
  • the orthographic projection of L13 on the base substrate is within the orthographic projection of L12 on the base substrate
  • the orthographic projection of L23 on the base substrate is within the orthographic projection of L22 on the base substrate.
  • the first second connection pattern L12 formed on the anode layer and the first third connection pattern L13 formed on the electrode layer form a RIB structure, which acts as an auxiliary electrode
  • the second second connection pattern L22 formed on the anode layer and the second third connection pattern L23 formed on the electrode layer form a RIB structure, which acts as an auxiliary electrode
  • the area of the first third connection pattern L13 is smaller than the area of the first second connection pattern L12
  • the area of the second third connection pattern L23 is smaller than the area of the second second connection pattern L22
  • the orthographic projection of the first third connection pattern L13 on the substrate is within the orthographic projection of the first second connection pattern L12 on the substrate
  • the orthographic projection of the second third connection pattern L23 on the substrate is within the orthographic projection of the second second connection pattern L22 on the substrate
  • the first third connection pattern L13 and the second third connection pattern L23 can be inverted trapezoidal connection patterns.
  • a connection pattern is formed in the electrode layer to form an I-shaped gap, a light-emitting material layer is arranged on the side of the electrode layer away from the base substrate, the light-emitting material layer will be cut off in the I-shaped gap, and then a cathode layer is arranged on the side of the light-emitting material layer away from the base substrate, the cathode layer will be electrically connected to the first second connection pattern L12 and the second second connection pattern L22, so that the auxiliary cathode electrode line Ax is electrically connected to the cathode layer to reduce the resistance of the cathode layer and reduce the cathode IR Drop (IR drop, IR drop refers to a phenomenon in which the voltage drops or rises on the power supply and ground networks in an integrated circuit).
  • the pixel circuit includes a light-emitting element; the display substrate further includes a reflective electrode;
  • the reflective electrode is disposed between the anode of the light-emitting element and the cathode of the light-emitting element;
  • the orthographic projection of the reflective electrode on the base substrate at least partially overlaps with the orthographic projection of the anode of the light-emitting element on the base substrate; the reflective electrode is opaque;
  • the reflective electrode is electrically connected to the anode of the light emitting element.
  • an electrode layer may be provided between the anode layer and the pixel defining layer;
  • an electrode layer is arranged between the anode layer and the pixel defining layer.
  • the electrode layer may include a stacked metal layer and a conductive layer.
  • the metal layer may be, for example, a Cu (copper) layer, a Mo (molybdenum) layer or an alloy layer.
  • the conductive layer may be made of ITO, but is not limited to this.
  • the metal layer is arranged between the conductive layer and the anode, and the electrode layer may be subjected to a patterning process to form a plurality of reflective electrodes.
  • F1 is a first reflective electrode
  • F2 is a second reflective electrode
  • F3 is a third reflective electrode
  • F4 is a fourth reflective electrode
  • F5 is a fifth reflective electrode
  • F6 is a sixth reflective electrode
  • F7 is a seventh reflective electrode
  • F8 is an eighth reflective electrode
  • F1, F2, F3, F4, F5, F6, F7 and F8 are opaque;
  • the orthographic projection of F1 on the substrate substrate at least partially overlaps with the orthographic projection of An11 on the substrate substrate
  • the orthographic projection of F2 on the substrate substrate at least partially overlaps with the orthographic projection of An12 on the substrate substrate
  • the orthographic projection of F3 on the substrate substrate at least partially overlaps with the orthographic projection of An21 on the substrate substrate
  • the orthographic projection of F4 on the substrate substrate at least partially overlaps with the orthographic projection of An22 on the substrate substrate
  • the orthographic projection of F5 on the substrate substrate at least partially overlaps with the orthographic projection of An31 on the substrate substrate
  • the orthographic projection of F6 on the substrate substrate at least partially overlaps with the orthographic projection of An32 on the substrate substrate
  • the orthographic projection of F7 on the substrate substrate at least partially overlaps with the orthographic projection of An41 on the substrate substrate
  • the orthographic projection of F8 on the substrate substrate at least partially overlaps with the orthographic projection of An42 on the substrate substrate;
  • F1 is electrically connected to An11
  • F2 is electrically connected to An12
  • F3 is electrically connected to An21
  • F4 is electrically connected to An22
  • F5 is electrically connected to An31
  • F6 is electrically connected to An32
  • F7 is electrically connected to An41
  • F8 is electrically connected to An42.
  • Da_w, Da_g, Da_r, Da_b and Sn may all extend in the vertical direction, Ax extends in the vertical direction, and VDD extends in the vertical direction;
  • Ax, Da_w, Da_g, Da_r, Da_b and Sn are arranged on the left side of each pixel circuit, and VDD is arranged on the right side of each pixel circuit.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned display substrate.
  • the display substrate includes a plurality of columns of auxiliary cathode electrode lines and a plurality of rows and columns of minimum repeating units disposed on a base substrate;
  • the minimum repeating unit includes at least three pixel circuits
  • the at least three pixel circuits are electrically connected to different data lines respectively, and the at least three pixel circuits are electrically connected to a power supply voltage line and an external compensation line; the at least three pixel circuits are electrically connected to a first scan line and a second scan line;
  • the auxiliary cathode electrode lines, the data lines, the power supply voltage lines and the external compensation lines extend along a third direction, and portions of the first scan lines and the second scan lines extend along a first direction intersecting the third direction.
  • the first direction may be a horizontal direction
  • the third direction may be a vertical direction
  • Ax is an auxiliary cathode electrode line
  • Da_w is a white data line
  • Da_g is a green data line
  • Da_r is a red data line
  • Da_b is a blue data line
  • Sn is an external compensation line
  • VDD is a power supply voltage line
  • G2 is a second scan line
  • G1 is a first scan line
  • the portion of G2 and the portion of G1 extend in the horizontal direction;
  • Ax, Da_w, Da_g, Da_r, Da_b, Sn and VDD all extend in the vertical direction.
  • the display substrate includes a pixel circuit region and a transparent region; the minimum repeating unit is disposed in the pixel circuit region;
  • the transparent area is arranged on a first side of the pixel circuit area and a second side of the pixel circuit area;
  • the second scanning line is disposed on a third side of the transparent area, and the first scanning line is disposed on a fourth side of the transparent area; the third side and the fourth side are opposite sides.
  • the first side may be a left side
  • the second side may be a right side
  • the third side may be an upper side
  • the fourth side may be a lower side, but is not limited thereto.
  • the pixel circuit area is labeled A0, the first transparent area is labeled A11, and the second transparent area is labeled A12;
  • the first insulating layer and the metal layer are not provided.
  • the pixel definition layer may be transparent.
  • A11 is disposed on the left side of the pixel circuit region A0
  • A12 is disposed on the right side of the pixel circuit region A0 ;
  • the second scan line G2 is disposed on the upper side of the pixel circuit region A0
  • the first scan line G1 is disposed on the lower side of the pixel circuit region A0 .
  • the first scan line includes at least two first scan line portions extending along the first direction, and at least two second scan line portions extending along the first direction;
  • the second scan line includes at least two third scan line portions extending along the first direction, and at least two fourth scan line portions extending along the first direction;
  • the orthographic projection of the first scan line portion on the base substrate overlaps with the orthographic projection of the auxiliary cathode electrode line on the base substrate, the orthographic projection of the first scan line portion on the base substrate overlaps with the orthographic projection of the data line on the base substrate, and the orthographic projection of the first scan line portion on the base substrate overlaps with the orthographic projection of the external compensation line on the base substrate;
  • the orthographic projection of the second scanning line portion on the base substrate overlaps with the orthographic projection of the power supply voltage line on the base substrate;
  • the orthographic projection of the third scan line portion on the base substrate overlaps with the orthographic projection of the auxiliary cathode electrode line on the base substrate, the orthographic projection of the first scan line portion on the base substrate overlaps with the orthographic projection of the data line on the base substrate, and the orthographic projection of the third scan line portion on the base substrate overlaps with the orthographic projection of the external compensation line on the base substrate;
  • An orthographic projection of the fourth scan line portion on the base substrate partially overlaps with an orthographic projection of the power supply voltage line on the base substrate.
  • At least two orthogonal projections of the first scan line portions on the substrate overlap with the orthogonal projections of the auxiliary cathode electrode line on the substrate, at least two orthogonal projections of the first scan line portions on the substrate overlap with the orthogonal projections of the data line on the substrate, and at least two orthogonal projections of the first scan line portions on the substrate overlap with the external compensation line.
  • the orthographic projections of the lines on the base substrate overlap, so that when a first scan line portion is short-circuited with at least one of the auxiliary cathode electrode line, the data line and the external compensation line, the first scan line portion can be cut off by laser, and the first scan line can still transmit the first scan signal;
  • Orthographic projections of at least two second scan line portions on the substrate overlap with the orthographic projections of the power supply voltage line on the substrate, so that when one second scan line portion is short-circuited with the power supply voltage line, the second scan line portion can be cut off by laser, and the first scan line can still transmit the first scan signal;
  • the orthographic projections of at least two third scan line portions on the base substrate overlap with the orthographic projections of the auxiliary cathode electrode line on the base substrate, the orthographic projections of at least two third scan line portions on the base substrate overlap with the orthographic projections of the data line on the base substrate, and the orthographic projections of at least two third scan line portions on the base substrate overlap with the orthographic projections of the external compensation line on the base substrate, so that when a third scan line portion is short-circuited with at least one of the auxiliary cathode electrode line, the data line and the external compensation line, the third scan line portion can be cut off by laser, and the second scan line can still transmit the second scan signal;
  • the orthographic projections of at least two fourth scan line portions on the substrate overlap with the orthographic projections of the power supply voltage line on the substrate, so that when a fourth scan line portion is short-circuited with the power supply voltage line, the fourth scan line portion can be cut off by laser, and the second scan line can still transmit the second scan signal.
  • the first first scanning line portion is labeled G11
  • the second first scanning line portion is labeled G21
  • the first second scanning line portion is labeled G12
  • the second second scanning line portion is labeled G22;
  • the first third scanning line portion is labeled G13
  • the second third scanning line portion is labeled G23
  • the first fourth scanning line portion is labeled G14
  • the second fourth scanning line portion is labeled G24.
  • the orthographic projection of G11 on the substrate partially overlaps with the orthographic projection of Ax on the substrate
  • the orthographic projection of G21 on the substrate partially overlaps with the orthographic projection of Ax on the substrate
  • the orthographic projection of G11 on the substrate partially overlaps with the orthographic projection of Da_w on the substrate
  • the orthographic projection of G21 on the substrate partially overlaps with the orthographic projection of Da_w on the substrate
  • the orthographic projection of G11 on the substrate partially overlaps with the orthographic projection of Da_g on the substrate
  • G21 on the substrate partially overlaps with the orthographic projection of Da_w on the substrate.
  • the orthographic projection on the substrate substrate partially overlaps with the orthographic projection of Da_g on the substrate substrate, the orthographic projection of G11 on the substrate substrate partially overlaps with the orthographic projection of Da_r on the substrate substrate, the orthographic projection of G21 on the substrate substrate partially overlaps with the orthographic projection of Da_r on the substrate substrate, the orthographic projection of G11 on the substrate substrate partially overlaps with the orthographic projection of Da_b on the substrate substrate, the orthographic projection of G21 on the substrate substrate partially overlaps with the orthographic projection of Da_b on the substrate substrate substrate, the orthographic projection of G11 on the substrate substrate partially overlaps with the orthographic projection of Sn on the substrate substrate, and the orthographic projection of G21 on the substrate partially overlaps with the orthographic projection of Sn on the substrate substrate, so that when G11 or G21 is disconnected, G1 can still normally provide the first scanning signal;
  • the orthographic projection of G12 on the substrate partially overlaps with the orthographic projection of VDD on the substrate, and the orthographic projection of G22 on the substrate partially overlaps with the orthographic projection of VDD on the substrate, so that when G12 or G22 is disconnected, G1 can still normally provide the first scanning signal;
  • the orthographic projection of G13 on the substrate partially overlaps with the orthographic projection of Ax on the substrate, the orthographic projection of G23 on the substrate partially overlaps with the orthographic projection of Ax on the substrate, the orthographic projection of G13 on the substrate partially overlaps with the orthographic projection of Da_w on the substrate, the orthographic projection of G23 on the substrate partially overlaps with the orthographic projection of Da_w on the substrate, the orthographic projection of G13 on the substrate partially overlaps with the orthographic projection of Da_g on the substrate, the orthographic projection of G23 on the substrate partially overlaps with the orthographic projection of Da_g on the substrate, the orthographic projection of G13 on the substrate partially overlaps with the orthographic projection of D
  • the orthographic projection of a_r on the substrate substrate partially overlaps, the orthographic projection of G23 on the substrate substrate partially overlaps with the orthographic projection of Da_r on the substrate substrate, the orthographic projection of G13 on the substrate substrate partially overlaps with the orthographic projection of Da_b on the substrate substrate, the orthographic projection of
  • the orthographic projection of G14 on the substrate partially overlaps with the orthographic projection of VDD on the substrate, and the orthographic projection of G24 on the substrate partially overlaps with the orthographic projection of VDD on the substrate, so that when G14 or G24 is disconnected, G2 can still provide the second scanning signal normally.
  • FIG37 is a cross-sectional view taken along line A-A’ in FIG18 .
  • reference numeral 30 is a base substrate, and the base substrate 30 may be a glass substrate, but is not limited thereto;
  • the number 31 is a light shielding layer
  • the number 32 is a buffer layer
  • the number 33 is a gate insulating layer
  • the number 34 is a gate metal layer
  • the number 35 is an interlayer dielectric layer
  • the number 36 is a source-drain metal layer
  • the number 37 is a passivation layer
  • the number 38 is a first insulating layer
  • the number 39 is an anode layer
  • the number 310 is a metal layer
  • the number 311 is a conductive layer
  • the number 312 is a pixel defining layer
  • the metal layer 310 and the conductive layer 311 form an electrode layer;
  • the first insulating layer 38 may be a resin layer
  • the metal layer 310 may be made of Cu, Mo or an alloy
  • the conductive layer 311 may be made of ITO.
  • the leftmost side is a transparent area.
  • the anode layer 39 is electrically connected to the connecting portion formed on the light-shielding layer 31 by forming a source-drain metal layer 36, and the connecting portion is electrically connected to the second electrode of the driving transistor to introduce the anode signal into the light-emitting area; in the transparent area, the first insulating layer is dug up to increase the transmittance.
  • a light-emitting material layer and a cathode layer are provided on the basis of FIG37 .
  • reference numeral 313 is a light emitting material layer
  • reference numeral 314 is a cathode layer.
  • the display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

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Abstract

一种像素电路、驱动控制方法、显示基板和显示装置。像素电路包括驱动电路(11)、控制电路(12)和发光单元(10)；驱动电路(11)用于在其控制端的电位的控制下，产生驱动发光单元(10)的驱动电流；控制电路(12)分别与第一扫描线(G1)、电源电压线(VDD)和驱动电路(11)的第二端电连接，用于在第一扫描信号的控制下，控制电源电压线(VDD)与驱动电路(11)的第二端之间连通；发光单元(10)的第二端与阴极电压线(VS)电连接。通过增设控制电路(12)，以能够通过增加正向电压及反向电压的方式，增加支路电流，进而将暗点处的异物烧断，将暗点变为正常点像素，提升产品良率及显示品质。

Description

像素电路、驱动控制方法、显示基板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路、驱动控制方法、显示基板和显示装置。
背景技术
在相关技术中，顶发射发光器件需要透明阴极Sputter(溅射)工艺，此工艺易在顶发射发光器件的阳极和顶发射发光器件的阴极之间产生Particle(异物)，从而导致显示产品暗点高发。
发明内容
在一个方面中，本公开实施例提供一种像素电路，包括驱动电路、控制电路和发光单元；
所述驱动电路的第一端与电源电压线电连接，所述驱动电路的第二端与所述发光单元的第一端电连接，所述驱动电路用于在其控制端的电位的控制下，产生驱动所述发光单元的驱动电流；
所述控制电路分别与第一扫描线、电源电压线和所述驱动电路的第二端电连接，用于在所述第一扫描线提供的第一扫描信号的控制下，控制所述电源电压线与所述驱动电路的第二端之间连通；
所述发光单元的第二端与阴极电压线电连接。
可选的，所述控制电路包括的晶体管的宽长比大于所述驱动电路包括的晶体管的宽长比。
可选的，本公开至少一实施例所述的像素电路还包括储能电路和数据写入电路；
所述储能电路的第一端与所述驱动电路的控制端电连接，所述储能电路的第二端与所述发光单元的第一端电连接；所述储能电路用于储存电能；
所述数据写入电路分别与第二扫描线、数据线和所述驱动电路的控制端电连接，用于在所述第二扫描线提供的第二扫描信号的控制下，将所述数据 线提供的数据电压写入所述驱动电路的控制端。
可选的，本公开至少一实施例所述的像素电路还包括外部补偿控制电路；
所述外部补偿控制电路分别与所述第二扫描线、外部补偿线和所述驱动电路的第二端电连接，用于在所述第二扫描信号的控制下，控制所述外部补偿线与所述驱动电路的第二端之间连通。
可选的，所述发光单元包括至少两个发光元件；或者，所述发光单元包括一个发光元件；
所述发光元件的阳极与所述发光单元的第一端电连接，所述发光元件的阴极与阴极电压线电连接。
可选的，所述驱动电路包括驱动晶体管，所述控制电路包括第一晶体管；
所述驱动晶体管的栅极与所述驱动电路的控制端电连接，所述驱动晶体管的第一电极与所述电源电压线电连接，所述驱动晶体管的第二电极与所述发光单元的第一端电连接；
所述第一晶体管的栅极与第一扫描线电连接，所述第一晶体管的第一电极与所述电源电压线电连接，所述第一晶体管的第二电极与所述驱动电路的第二端电连接。
可选的，所述储能电路包括存储电容，所述外部控制电路包括第二晶体管，所述数据写入电路包括第三晶体管；
所述存储电容的第一极板与所述发光单元的第一端电连接，所述存储电容的第二极板与所述驱动电路的控制端电连接；
所述第二晶体管的栅极与第二扫描线电连接，所述第二晶体管的第一电极与外部补偿线电连接，所述第二晶体管的第二电极与所述驱动电路的第二端电连接；
所述第三晶体管的栅极与所述第二扫描线电连接，所述第三晶体管的第一电极与所述数据线电连接，所述第三晶体管的第二电极与所述驱动电路的控制端电连接。
在第二个方面中，本公开实施例提供一种驱动控制方法，应用于上述的像素电路，所述驱动控制方法包括：
阴极电压线提供高电压信号，电源电压线提供低电压信号；或者，阴极 电压线提供低电压信号，电源电压线提供高电压信号；
数据写入电路在第二扫描信号的控制下，将数据线提供的数据电压写入所述驱动电路的控制端，以控制所述驱动电路断开其第一端和第二端之间的连接，之后，控制电路在第一扫描信号的控制下，控制电源电压线与驱动电路的第二端之间连通。
在第三个方面中，本公开实施例提供一种显示基板，包括衬底基板和设置于衬底基板上的多行多列上述的像素电路。
可选的，所述像素电路包括驱动晶体管、第一晶体管、第二晶体管和第三晶体管；
所述驱动晶体管的有源层图形、所述第一晶体管的有源层图形、所述第二晶体管的有源层图形和所述第三晶体管的有源层图形同层设置；
所述第三晶体管的有源层图形和所述驱动晶体管的有源层图形沿第一方向排列；
所述第二晶体管的有源层图形和所述第一晶体管的有源层图形沿第一方向排列；
所述驱动晶体管的有源层图形和所述第一晶体管的有源层图形沿第二方向排列；
所述第一方向和所述第二方向相交。
可选的，所述像素电路包括存储电容；
所述存储电容的第一极板包括第一极板部和第二极板部；
所述第一极板部、所述存储电容的第二极板和所述第二极板部沿着远离所述衬底极板的方向依次层叠设置，所述第一极板部与所述第二极板部电连接；
所述第一极板部在所述衬底基板上的正投影、所述第二极板部在所述衬底基板上的正投影和所述第二极板在所述衬底基板上的正投影至少部分交叠。
可选的，本公开至少一实施例所述的显示基板还包括辅助阴极电极线，所述像素电路包括发光元件；所述辅助阴极电极线设置于所述像素电路的第一侧；
所述辅助阴极电极线沿第三方向延伸，所述第三方向与第一方向相交；
所述辅助阴极电极线与所述发光元件的阴极电连接。
可选的，所述辅助阴极电极线与辅助连接图形电连接，所述辅助连接图形与所述辅助阴极电极线设置于不同层。
可选的，所述辅助阴极电极线与第一连接图形电连接；
所述第一连接图形与第二连接图形电连接，所述第一连接图形与所述第二连接图形位于不同层；所述第二连接图形与所述发光元件的阳极同层设置；
所述第二连接图形与第三连接图形电连接，所述第三连接图形设置于所述第二连接图形远离所述衬底基板的一侧；
所述第三连接图形与所述发光元件的阴极电连接，所述发光元件的阴极设置于所述第三连接图形远离所述衬底基板的一侧。
可选的，所述第三连接图形在所述衬底基板上的正投影在所述第二连接图形在所述衬底基板上的正投影之内。
可选的，所述像素电路包括发光元件；所述显示基板还包括反射电极；
所述反射电极设置于所述发光元件的阳极与所述发光元件的阴极之间；
所述反射电极在所述衬底基板上的正投影与所述发光元件的阳极在所述衬底基板上的正投影至少部分交叠；所述反射电极不透明，所述反射电极与所述发光元件的阳极电连接。
可选的，本公开至少一实施例所述的显示基板还包括遮光图形，所述遮光图形的至少部分设置于所述驱动晶体管的有源层图形与衬底基板之间，所述驱动晶体管的有源层图形与所述第一晶体管的有源层图形同层设置；
所述驱动晶体管的有源层图形在所述衬底基板上的正投影与所述遮光图形在所述衬底基板上的正投影至少部分交叠；
所述第一晶体管的有源层图形在所述衬底基板上的正投影与所述遮光图形在所述衬底基板上的正投影至少部分交叠。
可选的，本公开至少一实施例所述的显示基板还包括电源电压线和数据线；
所述电源电压线设置于所述像素电路的第二侧；所述数据线设置于所述像素电路的第一侧；
第一侧和第二侧为相对的两侧。
在第四个方面中，本公开实施例提供一种显示装置，包括上述的显示基板。
可选的，所述显示基板包括设置于衬底基板上的多列辅助阴极电极线和多行多列最小重复单元；
所述最小重复单元包括至少三个像素电路；
所述至少三个像素电路分别与不同的数据线电连接，所述至少三个像素电路都与电源电压线和外部补偿线电连接；所述至少三个像素电路都与第一扫描线和第二扫描线电连接；
所述辅助阴极电极线、所述数据线、所述电源电压线和所述外部补偿线沿第三方向延伸，所述第一扫描线的部分和所述第二扫描线的部分沿第一方向延伸，所述第一方向与所述第三方向相交。
可选的，所述显示基板包括像素电路区域和透明区域；所述最小重复单元设置于像素电路区域；
所述透明区域设置于所述像素电路区域的第一侧和所述像素电路区域的第二侧；
所述第二扫描线设置于所述透明区域的第三侧，所述第一扫描线设置于所述透明区域的第四侧；所述第三侧与所述第四侧为相对的两侧。
可选的，所述第一扫描线包括沿第一方向延伸的至少两个第一扫描线部，以及，沿第一方向延伸的至少两个第二扫描线部；
所述第二扫描线包括沿第一方向延伸的至少两个第三扫描线部，以及，沿第一方向延伸的至少两个第四扫描线部；
所述第一扫描线部在所述衬底基板上的正投影与所述辅助阴极电极线在所述衬底基板上的正投影部分交叠，所述第一扫描线部在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影部分交叠，所述第一扫描线部在所述衬底基板上的正投影与所述外部补偿线在所述衬底基板上的正投影部分交叠；
所述第二扫描线部在衬底基板上的正投影与所述电源电压线在所述衬底基板上的正投影部分交叠；
所述第三扫描线部在所述衬底基板上的正投影与所述辅助阴极电极线在 所述衬底基板上的正投影部分交叠，所述第上扫描线部在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影部分交叠，所述第三扫描线部在所述衬底基板上的正投影与所述外部补偿线在所述衬底基板上的正投影部分交叠；
所述第四扫描线部在衬底基板上的正投影与所述电源电压线在所述衬底基板上的正投影部分交叠。
附图说明
图1是本公开实施例所述的像素电路的结构图；
图2是本公开至少一实施例所述的像素电路的结构图；
图3是本公开至少一实施例所述的像素电路的结构图；
图4是本公开至少一实施例所述的像素电路的电路图；
图5是本公开图4所示的像素电路的至少一实施例的工作状态示意图；
图6是本公开图4所示的像素电路的至少一实施例的工作状态示意图；
图7是显示基板包括的最小重复单元的至少一实施例的电路图；
图8是本公开图4所示的像素电路的至少一实施例的部分的布局图；
图9是图8中的遮光层的布局图；
图10和图11是图8中的半导体层的布局图；
图12是图8中的栅金属层的布局图；
图13是图8中的源漏金属层的布局图；
图14是图8中的遮光层与半导体层的叠层图；
图15是图8中的半导体层与栅金属层的叠层图；
图16是图14中的栅金属层与源漏金属层的叠层图；
图17是在图8中的遮光层、半导体层和栅金属层的叠层图中增设贯穿层间介质层的过孔的示意图；
图18是图7所示的最小重复单元的至少一实施例的布局图；
图19是图18中的遮光层的布局图；
图20是图18中的半导体层的布局图；
图21是图18中的栅金属层的布局图；
图22是图18中的源漏金属层的布局图；
图23是图18中的实线框；
图24是图18中的阳极层的布局图；
图25是图18中的电极层的布局图；
图26是图18中的虚线框；
图27是图18中的遮光层与半导体层的叠层图，图28是图18中的遮光层、半导体层与栅金属层的叠层图；
图29是在图28的基础上增设贯穿层间介质层的过孔的示意图，在图29中，方框内部带乘号的图标为贯穿层间介质层的过孔；
图30是图18中的遮光层、半导体层、栅金属层和源漏金属层的叠层图；
图31是在图30的基础上增设实线框的示意图；
图32是在图31的基础上示出贯穿钝化层的过孔的示意图；
图33是在图32的基础上增设阳极层的叠层图；
图34是在图33的基础上增设电极层的叠层图；
图35是图18中的阳极层与电极层的叠层示意图；
图36是图18中的源漏金属层与阳极层的叠层示意图；
图37是图18中的A-A’截面图。
图38是在图37的基础上设置了发光材料层和阴极层的示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一电极，另一极称为第二电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一电极可以为漏极，所述第二电极可以为源极；或者，所述第一电极可以为源极， 所述第二电极可以为漏极。
如图1所示，本公开实施例所述的像素电路包括驱动电路11、控制电路12和发光单元10；
所述驱动电路11的第一端与电源电压线VDD电连接，所述驱动电路11的第二端与所述发光单元10的第一端电连接，所述驱动电路11用于在其控制端的电位的控制下，产生驱动所述发光单元10的驱动电流；
所述控制电路12分别与第一扫描线G1、电源电压线VDD和所述驱动电路11的第二端电连接，用于在所述第一扫描线G1提供的第一扫描信号的控制下，控制所述电源电压线VDD与所述驱动电路11的第二端之间连通；
所述发光单元10的第二端与阴极电压线VS电连接。
本公开实施例所述的像素电路通过增设控制电路12，以能够通过增加正向电压及反向电压的方式，增加支路电流，进而将暗点处的Particle(异物)烧断，将暗点变为正常点像素，提升产品良率及显示品质。
可选的，所述控制电路12包括的晶体管的宽长比大于所述驱动电路11包括的晶体管的宽长比。
在本公开至少一实施例中，所述控制电路12包括的晶体管可以为沟道增强TFT(薄膜晶体管)，其宽长比设计较大，可以提升TFT支路上的限流，从而通过增加正向电压及反向电压的方式，增加支路电流，进而将暗点处的Particle烧断。
本公开至少一实施例所述的像素电路还包括储能电路和数据写入电路；
所述储能电路的第一端与所述驱动电路的控制端电连接，所述储能电路的第二端与所述发光单元的第一端电连接；所述储能电路用于储存电能；
所述数据写入电路分别与第二扫描线、数据线和所述驱动电路的控制端电连接，用于在所述第二扫描线提供的第二扫描信号的控制下，将所述数据线提供的数据电压写入所述驱动电路的控制端。
在具体实施时，所述像素电路还可以包括储能电路和数据写入电路，数据写入电路在第二扫描信号的控制下，将数据线提供的数据电压写入驱动电路的控制端。
可选的，所述像素电路还包括外部补偿控制电路；
所述外部补偿控制电路分别与所述第二扫描线、外部补偿线和所述驱动电路的第二端电连接，用于在所述第二扫描信号的控制下，控制所述外部补偿线与所述驱动电路的第二端之间连通。
在具体实施时，本公开至少一实施例所述的像素电路还可以包括外部补偿控制电路，外部补偿控制电路在所述第二扫描信号的控制下，控制所述外部补偿线与所述驱动电路的第二端之间连通。
如图2所示，在图1所示的驱动电路的实施例的基础上，本公开至少一实施例所述的驱动电路还包括储能电路21、数据写入电路22和外部补偿控制电路23；
所述储能电路21的第一端与所述驱动电路11的控制端电连接，所述储能电路21的第二端与所述发光单元10的第一端电连接；所述储能电路21用于储存电能；
所述数据写入电路22分别与第二扫描线G2、数据线Da和所述驱动电路11的控制端电连接，用于在所述第二扫描线G2提供的第二扫描信号的控制下，将所述数据线Da提供的数据电压写入所述驱动电路11的控制端电连接；
所述外部补偿控制电路23分别与所述第二扫描线G2、外部补偿线Sn和所述驱动电路11的第二端电连接，用于在所述第二扫描信号的控制下，控制所述外部补偿线Sn与所述驱动电路11的第二端之间连通。
本公开图2所示的驱动电路的至少一实施例在工作时，
阴极电压线提供高电压信号，电源电压线提供低电压信号；
数据写入电路在第二扫描信号的控制下，将数据线提供的数据电压写入所述驱动电路的控制端，以控制所述驱动电路断开其第一端和第二端之间的连接，之后，控制电路在第一扫描信号的控制下，控制电源电压线与驱动电路的第二端之间连通，以对所述发光单元10包括的发光元件施加反向电压，以将所述发光元件处的Particle烧断。
本公开图2所示的驱动电路的至少一实施例在工作时，
阴极电压线提供低电压信号，电源电压线提供高电压信号；
数据写入电路在第二扫描信号的控制下，将数据线提供的数据电压写入所述驱动电路的控制端，以控制所述驱动电路断开其第一端和第二端之间的 连接，之后，控制电路在第一扫描信号的控制下，控制电源电压线与驱动电路的第二端之间连通，以对所述发光单元10包括的发光元件施加正向电压，以将所述发光元件处的Particle烧断。
可选的，所述发光单元包括至少两个发光元件；或者，所述发光单元包括一个发光元件；
所述发光元件的阳极与所述发光单元的第一端电连接，所述发光元件的阴极与阴极电压线电连接。
在本公开至少一实施例中，所述发光元件可以为顶发射发光元件，但不以此为限。
在具体实施时，所述发光元件可以为有机发光二极管，但不以此为限。
如图3所示，在图2所示的像素电路的至少一实施例的基础上，所述发光单元包括第一有机发光二极管O1和第二有机发光二极管O2；
第一有机发光二极管O1的阳极与所述驱动电路11的第二端电连接，第一有机发光二极管O1的阴极与阴极电压线VS电连接；
第二有机发光二极管O2的阳极与所述驱动电路11的第二端电连接，第二有机发光二极管O2的阴极与阴极电压线VS电连接。
可选的，所述驱动电路包括驱动晶体管，所述控制电路包括第一晶体管；
所述驱动晶体管的栅极与所述驱动电路的控制端电连接，所述驱动晶体管的第一电极与所述电源电压线电连接，所述驱动晶体管的第二电极与所述发光单元的第一端电连接；
所述第一晶体管的栅极与第一扫描线电连接，所述第一晶体管的第一电极与所述电源电压线电连接，所述第一晶体管的第二电极与所述驱动电路的第二端电连接。
在本公开至少一实施例中，所述第一晶体管的宽长比大于所述驱动晶体管的宽长比。
可选的，所述储能电路包括存储电容，所述外部控制电路包括第二晶体管，所述数据写入电路包括第三晶体管；
所述存储电容的第一极板与所述发光单元的第一端电连接，所述存储电容的第二极板与所述驱动电路的控制端电连接；
所述第二晶体管的栅极与第二扫描线电连接，所述第二晶体管的第一电极与外部补偿线电连接，所述第二晶体管的第二电极与所述驱动电路的第二端电连接；
所述第三晶体管的栅极与所述第二扫描线电连接，所述第三晶体管的第一电极与所述数据线电连接，所述第三晶体管的第二电极与所述驱动电路的控制端电连接。
如图4所示，在图3所示的像素电路的至少一实施例的基础上，所述驱动电路包括驱动晶体管Td，所述控制电路包括第一晶体管T1；
所述驱动晶体管Td的第一电极与所述电源电压线VDD电连接，所述驱动晶体管Td的第二电极分别与所述第一有机发光二极管O1的阳极和所述第二有机发光二极管O2的阳极电连接；
所述第一晶体管T1的栅极与第一扫描线G1电连接，所述第一晶体管T1的第一电极与所述电源电压线VDD电连接，所述第一晶体管T1的第二电极与所述驱动晶体管Td的第二电极电连接；
所述储能电路包括存储电容C1，所述外部控制电路包括第二晶体管T2，所述数据写入电路包括第三晶体管T3；
所述存储电容C1的第一极板分别与所述第一有机发光二极管O1的阳极和所述第二有机发光二极管O2的阳极电连接，所述存储电容C1的第二极板与所述驱动晶体管Td的栅极电连接；
所述第二晶体管T2的栅极与第二扫描线G2电连接，所述第二晶体管T2的第一电极与外部补偿线Sn电连接，所述第二晶体管T2的第二电极与所述驱动晶体管Td的第二电极电连接；
所述第三晶体管T3的栅极与所述第二扫描线G2电连接，所述第三晶体管T3的第一电极与所述数据线Da电连接，所述第三晶体管T3的第二电极与所述驱动晶体管Td的栅极电连接。
在图4所示的像素电路的至少一实施例中，T1的宽长比可以大于Td的宽长比。
在图4所示的像素电路的至少一实施例中，所有晶体管都为n型晶体管，但不以此为限。
在具体实施时，可以对O1和O2进行反向加压，也即，VS提供高电压信号，VDD提供低电压信号；
首先，G1提供高电压信号，G2提供高电压信号，T1、T2和T3都打开，Da提供低电压信号至Td的栅极，Td关断；
之后，G1提供高电压信号，G2提供低电压信号，T1打开，T1为沟道增强TFT，如图5所示，电流由O1的阴极流向O1的阳极，电流由O2的阴极流向O2的阳极，通过反向加压将有机发光二极管处的Particle烧断。
在具体实施时，可以对O1和O2进行正向加压，也即，VS提供低电压信号，VDD提供高电压信号；
首先，G1提供高电压信号，G2提供高电压信号，T1、T2和T3都打开，Da提供低电压信号至Td的栅极，Td关断；
之后，G1提供高电压信号，G2提供低电压信号，T1打开，T1为沟道增强TFT，如图6所示，电流由O1的阳极流向O1的阴极，电流由O2的一昂及流向O2的阴极，通过正向加压将有机发光二极管处的Particle烧断。
在相关技术中，所述像素电路不包括第一晶体管T1，由于Td的宽长比、T2的宽长比和T3的宽长比较小，限流严重，无法提供较大电流，且耐流能力较弱，基于此，本公开至少一实施例增设第一晶体管T1，所述第一晶体管T1为沟道增强TFT，可以增加支路电流，将暗点变为正常点，能保护有机发光二极管不受损害，保证了显示产品的良率，并提升画质。
图7是显示基板包括的最小重复单元的至少一实施例的电路图，所述显示基板可以包括多行多列所述最小重复单元。
如图7所示，所述最小重复单元的至少一实施例可以包括第一像素电路、第二像素电路、第三像素电路和第四像素电路；
所述第一像素电路包括第一驱动晶体管Td1、第一个第一晶体管T11、第一个第二晶体管T12、第一个第三晶体管T13、第一存储电容C11、第一白色有机发光二极管O11和第二白色有机发光二极管O12；
所述第一驱动晶体管Td1的第一电极与所述电源电压线VDD电连接，所述第一驱动晶体管Td1的第二电极分别与所述第一白色有机发光二极管O11的阳极和所述第二白色有机发光二极管O12的阳极电连接；
所述第一个第一晶体管T11的栅极与第一扫描线G1电连接，所述第一个第一晶体管T11的第一电极与所述电源电压线VDD电连接，所述第一个第一晶体管T11的第二电极与所述第一驱动晶体管Td1的第二电极电连接；
所述第一存储电容C11的第二极板与所述第一驱动晶体管Td1的栅极电连接，所述第一存储电容C11的第一极板分别与所述第一白色有机发光二极管O11的阳极和所述第二白色有机发光二极管O12的阳极电连接；
所述第一个第二晶体管T12的栅极与第二扫描线G2电连接，所述第一个第二晶体管T12的第一电极与外部补偿线Sn电连接，所述第一个第二晶体管T12的第二电极与所述第一驱动晶体管Td1的第二电极电连接；
所述第一个第三晶体管T13的栅极与所述第二扫描线G2电连接，所述第一个第三晶体管T13的第一电极与白色数据线Da_w电连接，所述第一个第三晶体管T13的第二电极与所述第一驱动晶体管Td1的栅极电连接；
所述第二像素电路包括第二驱动晶体管Td2、第二个第一晶体管T21、第二个第二晶体管T22、第二个第三晶体管T23、第二存储电容C12、第一绿色有机发光二极管O21和第二绿色有机发光二极管O22；
所述第二驱动晶体管Td2的第一电极与所述电源电压线VDD电连接，所述第二驱动晶体管Td2的第二电极分别与所述第一绿色有机发光二极管O21的阳极和所述第二绿色有机发光二极管O22的阳极电连接；
所述第二个第一晶体管T21的栅极与第一扫描线G1电连接，所述第二个第一晶体管T21的第一电极与所述电源电压线VDD电连接，所述第二个第一晶体管T21的第二电极与所述第二驱动晶体管Td2的第二电极电连接；
所述第二存储电容C12的第二极板与所述第二驱动晶体管Td2的栅极电连接，所述第二存储电容C12的第一极板分别与所述第一绿色有机发光二极管O21的阳极和所述第二绿色有机发光二极管O22的阳极电连接；
所述第二个第二晶体管T22的栅极与第二扫描线G2电连接，所述第二个第二晶体管T22的第一电极与外部补偿线Sn电连接，所述第二个第二晶体管T22的第二电极与所述第二驱动晶体管Td2的第二电极电连接；
所述第二个第三晶体管T23的栅极与所述第二扫描线G2电连接，所述第二个第三晶体管T23的第一电极与绿色数据线Da_g电连接，所述第二个 第三晶体管T23的第二电极与所述第二驱动晶体管Td2的栅极电连接；
所述第三像素电路包括第三驱动晶体管Td3、第三个第一晶体管T31、第三个第二晶体管T32、第三个第三晶体管T33、第三存储电容C13、第一红色有机发光二极管O31和第二红色有机发光二极管O32；
所述第三驱动晶体管Td3的第一电极与所述电源电压线VDD电连接，所述第三驱动晶体管Td3的第二电极分别与所述第一红色有机发光二极管O31的阳极和所述第二红色有机发光二极管O32的阳极电连接；
所述第三个第一晶体管T31的栅极与第一扫描线G1电连接，所述第三个第一晶体管T31的第一电极与所述电源电压线VDD电连接，所述第三个第一晶体管T31的第二电极与所述第三驱动晶体管Td3的第二电极电连接；
所述第三存储电容C13的第二极板与所述第三驱动晶体管Td3的栅极电连接，所述第三存储电容C13的第一极板分别与所述第一红色有机发光二极管O31的阳极和所述第二红色有机发光二极管O32的阳极电连接；
所述第三个第二晶体管T32的栅极与第二扫描线G2电连接，所述第三个第二晶体管T32的第一电极与外部补偿线Sn电连接，所述第三个第二晶体管T32的第二电极与所述第三驱动晶体管Td3的第二电极电连接；
所述第三个第三晶体管T33的栅极与所述第二扫描线G2电连接，所述第三个第三晶体管T33的第一电极与红色数据线Da_r电连接，所述第三个第三晶体管T33的第二电极与所述第三驱动晶体管Td3的栅极电连接；
所述第四像素电路包括第四驱动晶体管Td4、第四个第一晶体管T41、第四个第二晶体管T42、第四个第三晶体管T43、第四存储电容C14、第一蓝色有机发光二极管O41和第二蓝色有机发光二极管O42；
所述第四驱动晶体管Td4的第一电极与所述电源电压线VDD电连接，所述第四驱动晶体管Td4的第二电极分别与所述第一蓝色有机发光二极管O41的阳极和所述第二蓝色有机发光二极管O42的阳极电连接；
所述第四个第一晶体管T41的栅极与第一扫描线G1电连接，所述第四个第一晶体管T41的第一电极与所述电源电压线VDD电连接，所述第四个第一晶体管T41的第二电极与所述第四驱动晶体管Td4的第二电极电连接；
所述第四存储电容C14的第二极板与所述第四驱动晶体管Td4的栅极电 连接，所述第四存储电容C14的第一极板分别与所述第一蓝色有机发光二极管O41的阳极和所述第二蓝色有机发光二极管O42的阳极电连接；
所述第四个第二晶体管T42的栅极与第二扫描线G2电连接，所述第四个第二晶体管T42的第一电极与外部补偿线Sn电连接，所述第四个第二晶体管T42的第二电极与所述第四驱动晶体管Td4的第二电极电连接；
所述第四个第三晶体管T43的栅极与所述第二扫描线G2电连接，所述第四个第三晶体管T43的第一电极与蓝色数据线Da_b电连接，所述第四个第三晶体管T43的第二电极与所述第四驱动晶体管Td4的栅极电连接；
在图7所示的至少一实施例中，所有晶体管都为n型晶体管，但不以此为限。
在图7所示的至少一实施例中，外部补偿线Sn、白色数据线Da_w、绿色数据线Da_g、红色数据线Da_r和蓝色数据线Da_b都设置于各像素电路左侧，外部补偿线Sn、白色数据线Da_w、绿色数据线Da_g、红色数据线Da_r和蓝色数据线Da_b都沿竖直方向延伸；
电源电压线VDD沿竖直方向延伸，电源电压线VDD可以设置于各像素电路右侧；
第一扫描线G1设置于各像素电路下方，第一扫描线G1的大部分沿水平方向延伸；
第二扫描线G2设置于各像素电路上方，第二扫描线G2的大部分沿水平方向延伸；
辅助阴极电极线Ax沿竖直方向延伸，辅助阴极电极线Ax可以设置于各像素电路左侧。
在图7所示的至少一实施例中，白色像素电路、绿色像素电路、红色像素电路和蓝色像素电路沿竖直方向依次排列。
在本公开至少一实施例中，最小重复单元可以包括至少三个像素电路，所述至少三个像素电路为具有不同颜色的像素电路；
在具体实施时，当最小重复单元包括第一像素电路、第二像素电路、第三像素电路和第四像素电路时，第一像素电路、第二像素电路、第三像素电路和第四像素电路可以沿竖直方向依次排列，第一像素电路可以为红色像素 电路、绿色像素电路、蓝色像素电路、白色像素电路中之一，第二像素电路可以为红色像素电路、绿色像素电路、蓝色像素电路、白色像素电路中之一，第三像素电路可以为红色像素电路、绿色像素电路、蓝色像素电路、白色像素电路中之一，第四像素电路可以为红色像素电路、绿色像素电路、蓝色像素电路、白色像素电路中之一，第一像素电路对应的颜色、第二像素电路对应的颜色、第三像素电路对应的颜色和第四像素电路对应的颜色互不相同；
当最小重复单元包括第一像素电路、第二像素电路和第三像素电路时，第一像素电路、第二像素电路和第三像素电路可以沿竖直方向依次排列，第一像素电路可以为红色像素电路、绿色像素电路、蓝色像素电路中之一，第二像素电路可以为红色像素电路、绿色像素电路、蓝色像素电路中之一，第三像素电路可以为红色像素电路、绿色像素电路、蓝色像素电路中之一，第一像素电路对应的颜色、第二像素电路对应的颜色和第三像素电路对应的颜色互不相同。
本公开实施例所述的驱动控制方法，应用于上述的像素电路，所述驱动控制方法包括：
阴极电压线提供高电压信号，电源电压线提供低电压信号；或者，阴极电压线提供低电压信号，电源电压线提供高电压信号；
数据写入电路在第二扫描信号的控制下，将数据线提供的第一电压信号写入所述驱动电路的控制端，以控制所述驱动电路断开其第一端和第二端之间的连接，之后，控制电路在第一扫描信号的控制下，控制电源电压线与驱动电路的第二端之间连通。
本公开实施例所述的显示基板包括衬底基板和设置于衬底基板上的多行多列上述的像素电路。
可选的，所述像素电路包括驱动晶体管、第一晶体管、第二晶体管和第三晶体管；
所述驱动晶体管的有源层图形、所述第一晶体管的有源层图形、所述第二晶体管的有源层图形和所述第三晶体管的有源层图形同层设置；
所述第三晶体管的有源层图形和所述驱动晶体管的有源层图形沿第一方向排列；
所述第二晶体管的有源层图形和所述第一晶体管的有源层图形沿第一方向排列；
所述驱动晶体管的有源层图形和所述第一晶体管的有源层图形沿第二方向排列；
所述第一方向和所述第二方向相交。
图8是本公开图4所示的像素电路的至少一实施例的部分的布局图，图9是图8中的遮光层的布局图，图10和图11是图8中的半导体层的布局图，图12是图8中的栅金属层的布局图，图13是图8中的源漏金属层的布局图。
在图8中，标号为Td的为驱动晶体管，标号为T1的为第一晶体管，标号为T2的为第二晶体管，标号为T3的为第三晶体管，标号为Ax的为辅助阴极电极线，标号为Da的为数据线，标号为Sn的为外部补偿线，标号为VDD的为电源电压线。
图14是图8中的遮光层与半导体层的叠层图，图15是图8中的半导体层与栅金属层的叠层图，图16是图14中的栅金属层与源漏金属层的叠层图；
图17是在图8中的遮光层、半导体层和栅金属层的叠层图中增设贯穿层间介质层的过孔的示意图，在图17中，方框内部带乘号的图标为贯穿层间介质层的过孔。
在具体实施时，形成于遮光层上的遮光图形需要与形成于源漏金属层的图形电连接，而遮光层与源漏金属层之间的绝缘层厚度较大，因此可以采用套孔的形式打孔，可以采用两次打孔的方式，以形成用于电连接遮光层上的遮光图形需要与形成于源漏金属层的图形的过孔。
在图10中，标号为Ad的为驱动晶体管Td的有源层图形，标号为A1的为第一晶体管T1的有源层图形，标号为A2的为第二晶体管T2的有源层图形，标号为A3的为第三晶体管T3的有源层图形。
如图10所示，所述驱动晶体管Td的有源层图形Ad、所述第一晶体管T1的有源层图形A1、所述第二晶体管T2的有源层图形A2和所述第三晶体管T3的有源层图形A3同层设置；
A3和Ad沿水平方向排列；
A2和A1沿水平方向排列；
Ad和A1沿竖直方向排列。
在本公开至少一实施例中，所述第一方向可以为水平方向，所述第二方向可以为竖直方向，但不以此为限。
在本公开至少一实施例中，所述像素电路包括存储电容；
所述存储电容的第一极板包括第一极板部和第二极板部；
所述第一极板部、所述存储电容的第二极板和所述第二极板部沿着远离所述衬底极板的方向依次层叠设置，所述第一极板部与所述第二极板部电连接；
所述第一极板部在所述衬底基板上的正投影、所述第二极板部在所述衬底基板上的正投影和所述第二极板在所述衬底基板上的正投影至少部分交叠。
在具体实施时，存储电容的第一极板包括相互电连接的第一极板部和第二极板部，第一极板部、所述存储电容的第二极板和所述第二极板部沿着远离所述衬底极板的方向依次层叠设置，所述第一极板部在所述衬底基板上的正投影、所述第二极板部在所述衬底基板上的正投影和所述第二极板在所述衬底基板上的正投影至少部分交叠，以能提升存储电容的电容值。
在图9中，标号为C1a1的为存储电容的第一极板包括的第一极板部，在图11中，标号为C1b的为存储电容叠的第二极板；
在图13中，标号为C1a2的为存储电容的第一极板包括的第二极板部。
如图8所示，C1a1在衬底基板上的正投影、C1b在衬底基板上的正投影和C1a2在衬底基板上的正投影至少部分交叠；
如图8-图17所示，C1a1通过过孔与C1b1电连接。
在图11中，标号为Dd的为Td的第一电极，标号为Sd的为Td的第二电极；
如图8-图17所示，Dd通过过孔与电源电压线VDD电连接，Sd通过过孔与C1b电连接，C1a1与Td的第二电极Sd电连接。
在图8所示的至少一实施例中，存储电容的第一极板包括的第一极板部C1a1形成于遮光层，存储电容的第二极板C1b形成于半导体层，存储电容的第一极板包括的第二极板部C1a2形成于源漏金属层，C1b的至少部分设置于C1a1与C1a2之间，C1a1与C1b1电连接，以能提升存储电容的电容值。
本公开至少一实施例所述的显示基板还包括辅助阴极电极线，所述像素电路包括发光元件；所述辅助阴极电极线设置于所述像素电路的第一侧；
所述辅助阴极电极线沿第三方向延伸，所述第三方向与第一方向相交；
所述辅助阴极电极线与所述发光元件的阴极电连接。
可选的，所述第一方向可以为水平方向，所述第三方向可以为竖直方向，但不以此为限。
如图8所示，辅助阴极电极线Ax沿竖直方向延伸，辅助阴极电极线Ax设置于像素电路左侧，所述像素电路包括驱动晶体管Td、第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容。
在图8所示的至少一实施例中，第一侧为左侧。
在本公开至少一实施例中，所述辅助阴极电极线与辅助连接图形电连接，所述辅助连接图形与所述辅助阴极电极线设置于不同层。
如图13所示，所述辅助阴极电极线Ax可以形成于源漏金属层，如图12所示，辅助连接图形Lx形成于栅金属层，辅助阴极电极线Ax和辅助连接图形Lx通过过孔电连接，以降低辅助阴极电极线Ax的电阻。
在本公开至少一实施例中，所述辅助阴极电极线Ax与阴极层电连接，所述发光元件的阴极形成于所述阴极层。
在具体实施时，所述发光元件可以为顶发射发光元件，所述发光元件的阴极为透明阴极，由于透明阴极的电阻较大，因此，为了减小所述发光元件的阴极的电阻，本公开至少一实施例将所述阴极层设置为与辅助阴极电极线Ax电连接，将辅助阴极电极线Ax设置为与辅助连接图形Lx电连接，以降低所述发光元件的阴极的电阻。
本公开至少一实施例所述的显示基板还包括遮光图形，所述遮光图形的至少部分设置于所述驱动晶体管的有源层图形与衬底基板之间，所述驱动晶体管的有源层图形与所述第一晶体管的有源层图形同层设置；
所述驱动晶体管的有源层图形在所述衬底基板上的正投影与所述遮光图形在所述衬底基板上的正投影至少部分交叠；
所述第一晶体管的有源层图形在所述衬底基板上的正投影与所述遮光图形在所述衬底基板上的正投影至少部分交叠。
如图9所示，C1a1复用为第一遮光图形，标号为Z2的为第二遮光图形。
如图10所示，驱动晶体管的有源层图形Ad与第一晶体管T1的有源层图形A1都形成于半导体层。
如图8-图17所示，所述驱动晶体管的有源层图形Ad在所述衬底基板上的正投影与C1a1在衬底基板上的正投影至少部分重叠，以减少驱动晶体管的有源层图形Ad受到的光照，改善驱动晶体管的阈值电压漂移现象。
如图8-图17所示，所述第一晶体管的有源层图形A1在所述衬底基板上的正投影与Z2在衬底基板上的正投影之内至少部分重叠，以减少第一晶体管的有源层图形A1受到的光照，改善第一晶体管的阈值电压漂移现象。
可选的，所述遮光层可以为金属层，例如，所述遮光层可以由Mo(钼)制成，但不以此为限。
在本公开至少一实施例中，所述显示基板还可以包括电源电压线和数据线；
所述电源电压线设置于所述像素电路的第二侧；所述数据线设置于所述像素电路的第一侧；
第一侧和第二侧为相对的两侧。
如图8和图13所示，标号为VDD的为电源电压线，标号为Da的为数据线；
电源电压线VDD设置于像素电路右侧，数据线Da设置于像素电路左侧。
在图8所示的至少一实施例中，第一侧可以为左侧，第二侧都可以为右侧。
在图12中，标号为G1的为T1的栅极，标号为G2的为T2的栅极，标号为G3的为T3的栅极，标号为Gd的为Td的栅极。
在图13中，标号为D1的为T1的第一电极，标号为S1的为T1的第二电极。
图18是图7所示的最小重复单元的至少一实施例的布局图。
在图18中，在虚线框外，设置有像素界定层，在实线框外，设置有第一绝缘层，所述第一绝缘层例如可以为树脂层(Resin)。
图19是图18中的遮光层的布局图，图20是图18中的半导体层的布局 图，图21是图18中的栅金属层的布局图，图22是图18中的源漏金属层的布局图，
图23是图18中的实线框，在实线框外，设置有第一绝缘层，在实线框内，不设置有第一绝缘层；
图24是图18中的阳极层的布局图；图25是图18中的电极层的布局图；
图26是图18中的虚线框，在虚线框外设置有像素界定层，在虚线框内不设置像素界定层。
在本公开至少一实施例中，在衬底基板上，依次层叠设置有遮光层、半导体层、栅金属层、源漏金属层、阳极层、电极层和像素界定层；
在栅金属层和源漏金属层之间设置有层间介质层；
在源漏金属层和阳极层之间设置有第一绝缘层和钝化层，第一绝缘层设置于源漏金属层和钝化层之间，钝化层设置于第一绝缘层与阳极层之间；所述第一绝缘层例如可以为树脂层。
在具体实施时，所述阳极层可以由ITO(氧化铟锡)制成，但不以此为限。
图27是图18中的遮光层与半导体层的叠层图，图28是图18中的遮光层、半导体层与栅金属层的叠层图；
图29是在图28的基础上增设贯穿层间介质层的过孔的示意图，在图29中，方框内部带乘号的图标为贯穿层间介质层的过孔；
图30是图18中的遮光层、半导体层、栅金属层和源漏金属层的叠层图；
图31是在图30的基础上增设实线框的示意图；在图31中，在实线框外，设置有第一绝缘层，在实线框内，不设置有第一绝缘层；
图32是在图31的基础上示出贯穿钝化层的过孔的示意图；在图32中，黑色实心块标示的为贯穿钝化层的过孔；
图33是在图32的基础上增设阳极层的叠层图；
图34是在图33的基础上增设电极层的叠层图；
图35是图18中的阳极层与电极层的叠层示意图；
图36是图18中的源漏金属层与阳极层的叠层示意图。
在图30中，标号为Ax的为辅助阴极电极线，标号为Da_w的为白色数 据线，标号为Da_g的为绿色数据线，标号为Da_r的为红色数据线，标号为Da_b的为蓝色数据线，标号为Sn的为外部补偿线，标号为VDD的为电源电压线；
标号为T11的为第一个第一晶体管，标号为T12的为第一个第二晶体管，标号为T13的为第一个第三晶体管，标号为Td1的为第一驱动晶体管；
标号为T21的为第二个第一晶体管，标号为T22的为第二个第二晶体管，标号为T23的为第二个第三晶体管，标号为Td2的为第二驱动晶体管；
标号为T31的为第三个第一晶体管，标号为T32的为第三个第二晶体管，标号为T33的为第三个第三晶体管，标号为Td3的为第三驱动晶体管；
标号为T41的为第四个第一晶体管，标号为T42的为第四个第二晶体管，标号为T43的为第四个第三晶体管，标号为Td4的为第四驱动晶体管。
在图19中，标号为C11a1的为C11的第一极板包括的第一极板部，标号为C12a1的为C12的第一极板包括的第一极板部，标号为C13a1的为C13的第一极板包括的第一极板部，标号为C14a1的为C14的第一极板包括的第一极板部；
标号为Z12的为第一个第二遮光图形，标号为Z22的为第二个第二遮光图形，标号为Z32的为第三个第二遮光图形，标号为Z42的为第四个第二遮光图形；
C11a1与第一连接部L1电连接，C12a1与第二连接部L2电连接，C13a1与第三连接部L3电连接，C14a1与第四连接部L5电连接。
在图24中，标号为An11的为O11的阳极，标号为An12的为O12的阳极，标号为An21的为O21的阳极，标号为An22的为O22的阳极，标号为An31的为O31的阳极，标号为An32的为O32的阳极，标号为An41的为O41的阳极，标号为An42的为O42的阳极。
如图18-图36所示，L1通过过孔与An11和An12电连接，以使得C11a1与An11和An12电连接；
L2通过过孔与An21和An22电连接，以使得C12a1与An21和An22电连接；
L3通过过孔与An31和An32电连接，以使得C13a1与An31和An32电 连接；
L4通过过孔与An41和An42电连接，以使得C14a1与An41和An42电连接。
在图20中，标号为C11b的为C11的第二极板，标号为C12b的为C12的第二极板，标号为C13b的为C13的第二极板，标号为C14b的为C14的第二极板。
在本公开至少一实施例中，所述辅助阴极电极线与第一连接图形电连接；
所述第一连接图形与第二连接图形电连接，所述第一连接图形与所述第二连接图形位于不同层；所述第二连接图形与所述发光元件的阳极同层设置；
所述第二连接图形与第三连接图形电连接，所述第三连接图形设置于所述第二连接图形远离所述衬底基板的一侧；
所述第三连接图形与所述发光元件的阴极电连接，所述发光元件的阴极设置于所述第三连接图形远离所述衬底基板的一侧。
在具体实施时，所述第一连接图形可以形成于源漏金属层，所述第二连接图形可以形成于阳极层，所述第三连接图形可以形成于电极层，但不以此为限。
在图22中，标号为Ax的为辅助阴极电极线，标号为Sn的为外部补偿线，标号为VDD的为电源电压线，标号为Da_w的为白色数据线，标号为Da_g的为绿色数据线，标号为Da_r的为红色数据线，标号为Da_b的为蓝色数据线。
如图22所示，辅助阴极电极线Ax与第一个第一连接图形L11和第二个第一连接图形L21电连接。
在图22中，标号为C11a2的为C11的第一极板包括的第二极板部，标号为C12a2的为C12的第一极板包括的第二极板部，标号为C13a2的为C13的第一极板包括的第二极板部，标号为C14a2的为C14的第一极板包括的第二极板部。
在图24中，标号为L12的为第一个第二连接图形，标号为L22的为第二个第二连接图形；
在图25中，标号为L13的为第一个第三连接图形，标号为L23的为第二 个第三连接图形。
如图18-图36所示，L11、L12和L13电连接，L21、L22和L23电连接。
在本公开至少一实施例中，L13与阴极层电连接，L23与阴极层电连接，以使得辅助阴极电极线Ax与各像素电路中的有机发光二极管的阴极电连接；
各像素电路中的有机发光二极管的阴极形成于所述阴极层，所述阴极层设置于所述电极层远离所述衬底基板的一侧。
可选的，所述第三连接图形在所述衬底基板上的正投影在所述第二连接图形在所述衬底基板上的正投影之内。
如图35所示，L13在衬底基板的正投影在L12在衬底基板的正投影之内，L23在衬底基板的正投影在L22在衬底基板的正投影之内。
在本公开至少一实施例中，形成于阳极层的第一个第二连接图形L12和形成于电极层的第一个第三连接图形L13形成RIB结构，起着辅助电极的作用，形成于阳极层的第二个第二连接图形L22和形成于电极层的第二个第三连接图形L23形成RIB结构，起着辅助电极的作用.
在具体实施时，第一个第三连接图形L13的面积小于第一个第二连接图形L12的面积，第二个第三连接图形L23的面积小于第二个第二连接图形L22的面积，第一个第三连接图形L13在衬底基板的正投影在第一个第二连接图形L12在衬底基板的正投影之内，第二个第三连接图形L23在衬底基板的正投影在第二个第二连接图形L22在衬底基板的正投影之内，则第一个第三连接图形L13和第二个第三连接图形L23可以为倒梯形连接图形，在电极层，形成工字型空隙，在电极层远离衬底基板的一侧设置发光材料层，在工字型的空隙中，发光材料层会被切断，之后在发光材料层远离衬底基板的一侧设置阴极层，阴极层会与第一个第二连接图形L12和第二个第二连接图形L22电连接，从而使得辅助阴极电极线Ax与阴极层电连接，以降低所述阴极层的电阻，减小阴极IR Drop(IR压降，IR压降是指出现在集成电路中电源和地网络上电压下降或升高的一种现象)。
在本公开至少一实施例中，所述像素电路包括发光元件；所述显示基板还包括反射电极；
所述反射电极设置于所述发光元件的阳极与所述发光元件的阴极之间；
所述反射电极在所述衬底基板上的正投影与所述发光元件的阳极在所述衬底基板上的正投影至少部分交叠；所述反射电极不透明；
所述反射电极与所述发光元件的阳极电连接。
在具体实施时，在阳极层和像素界定层之间可以设置有电极层；
由于所述发光元件可以为顶发射发光元件，顶发射发光元件的阳极需要为反射阳极，因此，本公开至少一实施例在阳极层和像素界定层之间设置电极层，所述电极层可以包括层叠设置的金属层和导电层，所述金属层例如可以为Cu(铜)层、Mo(钼)层或合金层，所述导电层可以由ITO制成，但不以此为限；所述金属层设置于所述导电层与所述阳极之间，可以对所述电极层进行构图工艺，制成多个反射电极。
在图25中，标号为F1的为第一反射电极，标号为F2的为第二反射电极，标号为F3的为第三反射电极，标号为F4的为第四反射电极，标号为F5的为第五反射电极，标号为F6的为第六反射电极，标号为F7的为第七反射电极，标号为F8的为第八反射电极；
F1、F2、F3、F4、F5、F6、F7和F8不透明；
如图18-图36所示，F1在衬底基板上的正投影与An11在衬底基板上的正投影至少部分交叠，F2在衬底基板上的正投影与An12在衬底基板上的正投影至少部分交叠，F3在衬底基板上的正投影与An21在衬底基板上的正投影至少部分交叠，F4在衬底基板上的正投影与An22在衬底基板上的正投影至少部分交叠，F5在衬底基板上的正投影与An31在衬底基板上的正投影至少部分交叠，F6在衬底基板上的正投影与An32在衬底基板上的正投影至少部分交叠，F7在衬底基板上的正投影与An41在衬底基板上的正投影至少部分交叠，F8在衬底基板上的正投影与An42在衬底基板上的正投影至少部分交叠；
F1与An11电连接，F2与An12电连接，F3与An21电连接，F4与An22电连接，F5与An31电连接，F6与An32电连接，F7与An41电连接，F8与An42电连接。
如图18-图36所示，Da_w、Da_g、Da_r、Da_b和Sn可以都沿竖直方向延伸，Ax沿竖直方向延伸，VDD沿竖直方向延伸；
Ax、Da_w、Da_g、Da_r、Da_b和Sn设置于各像素电路左侧，VDD设置于各像素电路右侧。
本公开实施例所述的显示装置包括上述的显示基板。
在本公开至少一实施例中，所述显示基板包括设置于衬底基板上的多列辅助阴极电极线和多行多列最小重复单元；
所述最小重复单元包括至少三个像素电路；
所述至少三个像素电路分别与不同的数据线电连接，所述至少三个像素电路都与电源电压线和外部补偿线电连接；所述至少三个像素电路都与第一扫描线和第二扫描线电连接；
所述辅助阴极电极线、所述数据线、所述电源电压线和所述外部补偿线沿第三方向延伸，所述第一扫描线的部分和所述第二扫描线的部分沿第一方向延伸，所述第一方向与所述第三方向相交。
可选的，所述第一方向可以为水平方向，所述第三方向可以为竖直方向。
如图18所示，标号为Ax的为辅助阴极电极线，标号为Da_w的为白色数据线，标号为Da_g的为绿色数据线，标号为Da_r的为红色数据线，标号为Da_b的为蓝色数据线，标号为Sn的为外部补偿线，标号为VDD的为电源电压线，标号为G2的为第二扫描线，标号为G1的为第一扫描线；
G2的部分和G1的部分沿水平方向延伸；
Ax、Da_w、Da_g、Da_r、Da_b、Sn和VDD都沿竖直方向延伸。
在本公开至少一实施例中，所述显示基板包括像素电路区域和透明区域；所述最小重复单元设置于像素电路区域；
所述透明区域设置于所述像素电路区域的第一侧和所述像素电路区域的第二侧；
所述第二扫描线设置于所述透明区域的第三侧，所述第一扫描线设置于所述透明区域的第四侧；所述第三侧与所述第四侧为相对的两侧。
可选的，所述第一侧可以为左侧，所述第二侧可以为右侧，所述第三侧可以为上侧，所述第四侧可以为下侧，但不以此为限。
在图34中，标号为A0的为像素电路区域，标号为A11的为第一透明区域，标号为A12的为第二透明区域；
在第一透明区域A11和第二透明区域A12内，不设置有第一绝缘层和金属层。
在具体实施时，像素界定层可以是透明的。
如图34所示，A11设置于像素电路区域A0左侧，A12设置于像素电路区域A0右侧；
第二扫描线G2设置于像素电路区域A0上侧，第一扫描线G1设置于像素电路区域A0下侧。
在本公开至少一实施例中，所述第一扫描线包括沿第一方向延伸的至少两个第一扫描线部，以及，沿第一方向延伸的至少两个第二扫描线部；
所述第二扫描线包括沿第一方向延伸的至少两个第三扫描线部，以及，沿第一方向延伸的至少两个第四扫描线部；
所述第一扫描线部在所述衬底基板上的正投影与所述辅助阴极电极线在所述衬底基板上的正投影部分交叠，所述第一扫描线部在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影部分交叠，所述第一扫描线部在所述衬底基板上的正投影与所述外部补偿线在所述衬底基板上的正投影部分交叠；
所述第二扫描线部在衬底基板上的正投影与所述电源电压线在所述衬底基板上的正投影部分交叠；
所述第三扫描线部在所述衬底基板上的正投影与所述辅助阴极电极线在所述衬底基板上的正投影部分交叠，所述第上扫描线部在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影部分交叠，所述第三扫描线部在所述衬底基板上的正投影与所述外部补偿线在所述衬底基板上的正投影部分交叠；
所述第四扫描线部在衬底基板上的正投影与所述电源电压线在所述衬底基板上的正投影部分交叠。
在具体实施时，至少两个第一扫描线部在所述衬底基板上的正投影与所述辅助阴极电极线在所述衬底基板上的正投影部分交叠，至少两个第一扫描线部在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影部分交叠，至少两个第一扫描线部在所述衬底基板上的正投影与所述外部补偿 线在所述衬底基板上的正投影部分交叠，以使得当一第一扫描线部与辅助阴极电极线、数据线和外部补偿线中至少之一短路时，可以通过激光切断该第一扫描线部，所述第一扫描线仍然能够传递第一扫描信号；
至少两个第二扫描线部在衬底基板上的正投影与所述电源电压线在所述衬底基板上的正投影部分交叠，以使得当一个第二扫描线部与所述电源电压线短路时，可以通过激光切断该第二扫描线部，所述第一扫描线仍然能够传递第一扫描信号；
至少两个第三扫描线部在所述衬底基板上的正投影与所述辅助阴极电极线在所述衬底基板上的正投影部分交叠，至少两个第三扫描线部在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影部分交叠，至少两个第三扫描线部在所述衬底基板上的正投影与所述外部补偿线在所述衬底基板上的正投影部分交叠，以使得当一第三扫描线部与辅助阴极电极线、数据线和外部补偿线中至少之一短路时，可以通过激光切断该第三扫描线部，所述第二扫描线仍然能够传递第二扫描信号；
至少两个第四扫描线部在衬底基板上的正投影与所述电源电压线在所述衬底基板上的正投影部分交叠，以使得当一个第四扫描线部与所述电源电压线短路时，可以通过激光切断该第四扫描线部，所述第二扫描线仍然能够传递第二扫描信号。
如图21所示，标号为G11的为第一个第一扫描线部，标号为G21的为第二个第一扫描线部，标号为G12的为第一个第二扫描线部，标号为G22的为第二个第二扫描线部；
标号为G13的为第一个第三扫描线部，标号为G23的为第二个第三扫描线部，标号为G14的为第一个第四扫描线部，标号为G24的为第二个第四扫描线部。
如图21和图30所示，G11在衬底基板上的正投影与Ax在衬底基板上的正投影部分重叠，G21在衬底基板上的正投影与Ax在衬底基板上的正投影部分重叠，G11在衬底基板上的正投影与Da_w在衬底基板上的正投影部分重叠，G21在衬底基板上的正投影与Da_w在衬底基板上的正投影部分重叠，G11在衬底基板上的正投影与Da_g在衬底基板上的正投影部分重叠，G21在 衬底基板上的正投影与Da_g在衬底基板上的正投影部分重叠，G11在衬底基板上的正投影与Da_r在衬底基板上的正投影部分重叠，G21在衬底基板上的正投影与Da_r在衬底基板上的正投影部分重叠，G11在衬底基板上的正投影与Da_b在衬底基板上的正投影部分重叠，G21在衬底基板上的正投影与Da_b在衬底基板上的正投影部分重叠，G11在衬底基板上的正投影与Sn在衬底基板上的正投影部分重叠，G21在衬底基板上的正投影与Sn在衬底基板上的正投影部分重叠，以使得当G11或G21断开时，G1仍能够正常提供第一扫描信号；
G12在衬底基板上的正投影与VDD在衬底基板上的正投影部分重叠，G22在衬底基板上的正投影与VDD在衬底基板上的正投影部分重叠，以使得当G12或G22断开时，G1仍能够正常提供第一扫描信号；
G13在衬底基板上的正投影与Ax在衬底基板上的正投影部分重叠，G23在衬底基板上的正投影与Ax在衬底基板上的正投影部分重叠，G13在衬底基板上的正投影与Da_w在衬底基板上的正投影部分重叠，G23在衬底基板上的正投影与Da_w在衬底基板上的正投影部分重叠，G13在衬底基板上的正投影与Da_g在衬底基板上的正投影部分重叠，G23在衬底基板上的正投影与Da_g在衬底基板上的正投影部分重叠，G13在衬底基板上的正投影与Da_r在衬底基板上的正投影部分重叠，G23在衬底基板上的正投影与Da_r在衬底基板上的正投影部分重叠，G13在衬底基板上的正投影与Da_b在衬底基板上的正投影部分重叠，G23在衬底基板上的正投影与Da_b在衬底基板上的正投影部分重叠，G13在衬底基板上的正投影与Sn在衬底基板上的正投影部分重叠，G23在衬底基板上的正投影与Sn在衬底基板上的正投影部分重叠，以使得当G13或G23断开时，G2仍能够正常提供第二扫描信号；
G14在衬底基板上的正投影与VDD在衬底基板上的正投影部分重叠，G24在衬底基板上的正投影与VDD在衬底基板上的正投影部分重叠，以使得当G14或G24断开时，G2仍能够正常提供第二扫描信号。
图37是图18中的A-A’截面图。
在图37中，标号为30的为衬底基板，衬底基板30可以为玻璃基板，但不以此为限；
标号为31的为遮光层，标号为32的为缓冲层，标号为33的为栅绝缘层，标号为34的为栅金属层，标号为35的为层间介质层，标号为36的为源漏金属层，标号为37的为钝化层，标号为38的为第一绝缘层，标号为39的为阳极层，标号为310的为金属层，标号为311的为导电层，标号为312的为像素界定层；金属层310和导电层311形成电极层；
第一绝缘层38可以为树脂层，金属层310可以由Cu、Mo或合金制成，导电层311可以由ITO制成。
由图37所示，最左侧为透明区域，在透明区域，阳极层39通过形成源漏金属层36与形成于遮光层31的连接部电连接，并该连接部与驱动晶体管的第二电极电连接，以将阳极信号引入发光区域；在透明区域，将第一绝缘层挖开，增加透过率。
如图38所示，在图37的基础上设置了发光材料层和阴极层。
在图38中，标号为313的为发光材料层，标号为314的为阴极层。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (22)

  1. 一种像素电路，包括驱动电路、控制电路和发光单元；
    所述驱动电路的第一端与电源电压线电连接，所述驱动电路的第二端与所述发光单元的第一端电连接，所述驱动电路用于在其控制端的电位的控制下，产生驱动所述发光单元的驱动电流；
    所述控制电路分别与第一扫描线、电源电压线和所述驱动电路的第二端电连接，用于在所述第一扫描线提供的第一扫描信号的控制下，控制所述电源电压线与所述驱动电路的第二端之间连通；
    所述发光单元的第二端与阴极电压线电连接。
  2. 如权利要求1所述的像素电路，其中，所述控制电路包括的晶体管的宽长比大于所述驱动电路包括的晶体管的宽长比。
  3. 如权利要求1所述的像素电路，其中，还包括储能电路和数据写入电路；
    所述储能电路的第一端与所述驱动电路的控制端电连接，所述储能电路的第二端与所述发光单元的第一端电连接；所述储能电路用于储存电能；
    所述数据写入电路分别与第二扫描线、数据线和所述驱动电路的控制端电连接，用于在所述第二扫描线提供的第二扫描信号的控制下，将所述数据线提供的数据电压写入所述驱动电路的控制端。
  4. 如权利要求3所述的像素电路，其中，还包括外部补偿控制电路；
    所述外部补偿控制电路分别与所述第二扫描线、外部补偿线和所述驱动电路的第二端电连接，用于在所述第二扫描信号的控制下，控制所述外部补偿线与所述驱动电路的第二端之间连通。
  5. 如权利要求3所述的像素电路，其中，所述发光单元包括至少两个发光元件；或者，所述发光单元包括一个发光元件；
    所述发光元件的阳极与所述发光单元的第一端电连接，所述发光元件的阴极与阴极电压线电连接。
  6. 如权利要求1至5中任一权利要求所述的像素电路，其中，所述驱动电路包括驱动晶体管，所述控制电路包括第一晶体管；
    所述驱动晶体管的栅极与所述驱动电路的控制端电连接，所述驱动晶体管的第一电极与所述电源电压线电连接，所述驱动晶体管的第二电极与所述发光单元的第一端电连接；
    所述第一晶体管的栅极与第一扫描线电连接，所述第一晶体管的第一电极与所述电源电压线电连接，所述第一晶体管的第二电极与所述驱动电路的第二端电连接。
  7. 如权利要求4所述的像素电路，其中，所述储能电路包括存储电容，所述外部控制电路包括第二晶体管，所述数据写入电路包括第三晶体管；
    所述存储电容的第一极板与所述发光单元的第一端电连接，所述存储电容的第二极板与所述驱动电路的控制端电连接；
    所述第二晶体管的栅极与第二扫描线电连接，所述第二晶体管的第一电极与外部补偿线电连接，所述第二晶体管的第二电极与所述驱动电路的第二端电连接；
    所述第三晶体管的栅极与所述第二扫描线电连接，所述第三晶体管的第一电极与所述数据线电连接，所述第三晶体管的第二电极与所述驱动电路的控制端电连接。
  8. 一种驱动控制方法，应用于如权利要求3至7中任一权利要求所述的像素电路，所述驱动控制方法包括：
    阴极电压线提供高电压信号，电源电压线提供低电压信号；或者，阴极电压线提供低电压信号，电源电压线提供高电压信号；
    数据写入电路在第二扫描信号的控制下，将数据线提供的数据电压写入所述驱动电路的控制端，以控制所述驱动电路断开其第一端和第二端之间的连接，之后，控制电路在第一扫描信号的控制下，控制电源电压线与驱动电路的第二端之间连通。
  9. 一种显示基板，包括衬底基板和设置于衬底基板上的多行多列如权利要求1至7中任一权利要求所述的像素电路。
  10. 如权利要求9所述的显示基板，其中，所述像素电路包括驱动晶体管、第一晶体管、第二晶体管和第三晶体管；
    所述驱动晶体管的有源层图形、所述第一晶体管的有源层图形、所述第 二晶体管的有源层图形和所述第三晶体管的有源层图形同层设置；
    所述第三晶体管的有源层图形和所述驱动晶体管的有源层图形沿第一方向排列；
    所述第二晶体管的有源层图形和所述第一晶体管的有源层图形沿第一方向排列；
    所述驱动晶体管的有源层图形和所述第一晶体管的有源层图形沿第二方向排列；
    所述第一方向和所述第二方向相交。
  11. 如权利要求9所述的显示基板，其中，所述像素电路包括存储电容；
    所述存储电容的第一极板包括第一极板部和第二极板部；
    所述第一极板部、所述存储电容的第二极板和所述第二极板部沿着远离所述衬底极板的方向依次层叠设置，所述第一极板部与所述第二极板部电连接；
    所述第一极板部在所述衬底基板上的正投影、所述第二极板部在所述衬底基板上的正投影和所述第二极板在所述衬底基板上的正投影至少部分交叠。
  12. 如权利要求9所述的显示基板，其中，还包括辅助阴极电极线，所述像素电路包括发光元件；所述辅助阴极电极线设置于所述像素电路的第一侧；
    所述辅助阴极电极线沿第三方向延伸，所述第三方向与第一方向相交；
    所述辅助阴极电极线与所述发光元件的阴极电连接。
  13. 如权利要求12所述的显示基板，其中，所述辅助阴极电极线与辅助连接图形电连接，所述辅助连接图形与所述辅助阴极电极线设置于不同层。
  14. 如权利要求13所述的显示基板，其中，所述辅助阴极电极线与第一连接图形电连接；
    所述第一连接图形与第二连接图形电连接，所述第一连接图形与所述第二连接图形位于不同层；所述第二连接图形与所述发光元件的阳极同层设置；
    所述第二连接图形与第三连接图形电连接，所述第三连接图形设置于所述第二连接图形远离所述衬底基板的一侧；
    所述第三连接图形与所述发光元件的阴极电连接，所述发光元件的阴极 设置于所述第三连接图形远离所述衬底基板的一侧。
  15. 如权利要求14所述的显示基板，其中，所述第三连接图形在所述衬底基板上的正投影在所述第二连接图形在所述衬底基板上的正投影之内。
  16. 如权利要求9所述的显示基板，其中，所述像素电路包括发光元件；所述显示基板还包括反射电极；
    所述反射电极设置于所述发光元件的阳极与所述发光元件的阴极之间；
    所述反射电极在所述衬底基板上的正投影与所述发光元件的阳极在所述衬底基板上的正投影至少部分交叠；所述反射电极不透明，所述反射电极与所述发光元件的阳极电连接。
  17. 如权利要求10所述的显示基板，其中，还包括遮光图形，所述遮光图形的至少部分设置于所述驱动晶体管的有源层图形与衬底基板之间，所述驱动晶体管的有源层图形与所述第一晶体管的有源层图形同层设置；
    所述驱动晶体管的有源层图形在所述衬底基板上的正投影与所述遮光图形在所述衬底基板上的正投影至少部分交叠；
    所述第一晶体管的有源层图形在所述衬底基板上的正投影与所述遮光图形在所述衬底基板上的正投影至少部分交叠。
  18. 如权利要求12至15中任一权利要求所述的显示基板，其中，还包括电源电压线和数据线；
    所述电源电压线设置于所述像素电路的第二侧；所述数据线设置于所述像素电路的第一侧；
    第一侧和第二侧为相对的两侧。
  19. 一种显示装置，包括如权利要求9至18中任一权利要求所述的显示基板。
  20. 如权利要求19所述的显示装置，其中，所述显示基板包括设置于衬底基板上的多列辅助阴极电极线和多行多列最小重复单元；
    所述最小重复单元包括至少三个像素电路；
    所述至少三个像素电路分别与不同的数据线电连接，所述至少三个像素电路都与电源电压线和外部补偿线电连接；所述至少三个像素电路都与第一扫描线和第二扫描线电连接；
    所述辅助阴极电极线、所述数据线、所述电源电压线和所述外部补偿线沿第三方向延伸，所述第一扫描线的部分和所述第二扫描线的部分沿第一方向延伸，所述第一方向与所述第三方向相交。
  21. 如权利要求20所述的显示装置，其中，所述显示基板包括像素电路区域和透明区域；所述最小重复单元设置于像素电路区域；
    所述透明区域设置于所述像素电路区域的第一侧和所述像素电路区域的第二侧；
    所述第二扫描线设置于所述透明区域的第三侧，所述第一扫描线设置于所述透明区域的第四侧；所述第三侧与所述第四侧为相对的两侧。
  22. 如权利要求20所述的显示装置，其中，所述第一扫描线包括沿第一方向延伸的至少两个第一扫描线部，以及，沿第一方向延伸的至少两个第二扫描线部；
    所述第二扫描线包括沿第一方向延伸的至少两个第三扫描线部，以及，沿第一方向延伸的至少两个第四扫描线部；
    所述第一扫描线部在所述衬底基板上的正投影与所述辅助阴极电极线在所述衬底基板上的正投影部分交叠，所述第一扫描线部在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影部分交叠，所述第一扫描线部在所述衬底基板上的正投影与所述外部补偿线在所述衬底基板上的正投影部分交叠；
    所述第二扫描线部在衬底基板上的正投影与所述电源电压线在所述衬底基板上的正投影部分交叠；
    所述第三扫描线部在所述衬底基板上的正投影与所述辅助阴极电极线在所述衬底基板上的正投影部分交叠，所述第上扫描线部在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影部分交叠，所述第三扫描线部在所述衬底基板上的正投影与所述外部补偿线在所述衬底基板上的正投影部分交叠；
    所述第四扫描线部在衬底基板上的正投影与所述电源电压线在所述衬底基板上的正投影部分交叠。
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WO2007111202A1 (ja) * 2006-03-28 2007-10-04 Pioneer Corporation 電流制御型発光素子の駆動装置
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JP2003051384A (ja) * 2001-06-01 2003-02-21 Semiconductor Energy Lab Co Ltd 発光装置の修理方法および作製方法
JP2006011391A (ja) * 2004-05-21 2006-01-12 Semiconductor Energy Lab Co Ltd 表示装置
WO2007111202A1 (ja) * 2006-03-28 2007-10-04 Pioneer Corporation 電流制御型発光素子の駆動装置
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