WO2024146136A1

WO2024146136A1 - Semiconductor structure and method for manufacturing same

Info

Publication number: WO2024146136A1
Application number: PCT/CN2023/111098
Authority: WO
Inventors: 陈小璇
Original assignee: 长鑫存储技术有限公司
Priority date: 2023-01-05
Filing date: 2023-08-03
Publication date: 2024-07-11
Also published as: WO2024146136A9; CN118338667A

Abstract

Provided are a semiconductor structure and a method for manufacturing same. The semiconductor structure comprises a substrate and a contact plug. A word line trench is formed in the substrate. A first word line conductive layer and a second word line conductive layer which are stacked are provided in the word line trench. The second word line conductive layer comprises a first conductive portion and a second conductive portion. The first conductive portion is internally provided with doping ions, and the resistivity of the first conductive portion is less than that of the second conductive portion. At least part of the side wall of the first conductive portion and the inner wall of the word line trench are arranged at an interval. The second conductive portion is in contact with the inner wall of the word line trench. The contact plug is electrically connected to the first conductive portion.

Description

Semiconductor structure and method for manufacturing semiconductor structure

cross reference

The present disclosure claims priority to Chinese invention patent application numbered 202310014535.3 filed on January 5, 2023, entitled “Semiconductor Structure and Method for Manufacturing Semiconductor Structure”, the entire contents of which are incorporated herein by reference in their entirety.

Technical Field

The present disclosure belongs to the field of semiconductors, and in particular relates to a semiconductor structure and a method for manufacturing the semiconductor structure.

Background technique

Dynamic Random Access Memory (DRAM) in semiconductor structure is a semiconductor memory widely used in computer systems. The main working principle of DRAM is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

The buried word line can be set in the substrate, which is beneficial to improve the integration of DRAM and increase the channel length to improve the short channel effect. However, the performance of DRAM using the buried word line structure needs to be further improved.

Summary of the invention

The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the semiconductor structure, which are at least beneficial to improving the performance of a DRAM using a buried word line structure.

According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor structure, the semiconductor structure comprising: a substrate, wherein the substrate has a word line groove; the word line groove has a first word line conductive layer and a second word line conductive layer stacked in a stacked manner; the second word line conductive layer comprises a first conductive portion and a second conductive portion, the first conductive portion has doped ions, and the resistivity of the first conductive portion is less than the resistivity of the second conductive portion; at least a portion of the sidewalls of the first conductive portion are spaced apart from the inner wall of the word line groove; the second conductive portion is in contact with the inner wall of the word line groove; and a contact plug, the contact plug being electrically connected to the first conductive portion.

According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method for manufacturing a semiconductor structure comprising: providing a substrate, forming a word line groove in the substrate; forming a first word line conductive layer and a second word line conductive layer stacked in the word line groove; the second word line conductive layer comprises a first conductive part and a second conductive part, the first conductive part has doped ions, and the resistivity of the first conductive part is less than the resistivity of the second conductive part; at least a portion of the sidewalls of the first conductive part are spaced apart from the inner wall of the word line groove; the second conductive part is in contact with the inner wall of the word line groove; and a contact plug is formed, the contact plug being connected to the first conductive part.

The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

The second word line conductive layer includes a first conductive part and a second conductive part, wherein the first conductive part has doped ions and has a resistivity lower than that of the second conductive part; at least a portion of the sidewall of the first conductive part is spaced from the inner wall of the word line groove. That is, compared with the second conductive part, the first conductive part has a smaller contact area with the sidewall of the word line groove or has no contact relationship, thereby reducing the overlapping area between the first conductive part and the active area, thereby reducing the GIDL current (gate-induced drain leakage). The contact plug is electrically connected to the first conductive part, and since the first conductive part has a smaller resistivity, the contact resistance between the two is smaller, which is beneficial to improving the operating speed of the semiconductor structure.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

1-2 are different top views of an array region of a semiconductor structure provided by an embodiment of the present disclosure;

FIG3 is a different cross-sectional view of the semiconductor structure shown in FIG1 or FIG2 along the A-A1 direction;

FIG4 is a different cross-sectional view of the semiconductor structure shown in FIG1 or FIG2 along the B-B1 direction;

FIG5 is a different cross-sectional view of the semiconductor structure shown in FIG1 or FIG2 along the C-C1 direction;

6 to 9 are different cross-sectional views of the semiconductor structure shown in FIG. 1 or FIG. 2 along the D-D1 direction;

FIG10 is a cross-sectional view of a peripheral region of a semiconductor structure provided by an embodiment of the present disclosure;

11 to 19 are schematic structural diagrams corresponding to each step in a method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure.

Detailed ways

As can be seen from the background technology, the performance of DRAM using an embedded word line structure needs to be further improved. After analysis, it was found that the main reason is that there is an overlapping area between the word line and the active area in the substrate, and gate induced drain leakage current, i.e., GIDL current, may be generated in the overlapping area. GIDL current will have a great impact on the reliability of the semiconductor structure. Therefore, the word line can be composed of a first word line conductive layer and a second word line conductive layer stacked, and the second word line conductive layer can be made of a material with a smaller work function to reduce the GIDL current, but the conductivity of these materials is usually poor. If the thickness of the second word line conductive layer is to be increased, the total resistance of the word line may be too large, thereby aggravating the RC delay effect and reducing the operating speed of the semiconductor structure.

In the disclosed embodiment, the second word line conductive layer includes a first conductive part and a second conductive part, the first conductive part has doped ions, and the resistivity of the first conductive part is less than the resistivity of the second conductive part; at least part of the sidewall of the first conductive part is spaced apart from the inner wall of the word line groove; the second conductive part is in contact with the inner wall of the word line groove. That is, the first conductive part with a smaller resistivity has a smaller contact area with the inner wall of the word line groove or has no contact relationship, thereby reducing the overlapping area between the first conductive part and the active area, thereby reducing the GIDL current. The contact plug is electrically connected to the first conductive part, thereby reducing the contact resistance between the two, thereby improving the operating speed of the semiconductor structure.

The semiconductor structure will be described in detail below with reference to the accompanying drawings.

As shown in Figures 1 to 10, an embodiment of the present disclosure provides a semiconductor structure. It should be noted that Figures 1 to 10 are partial schematic diagrams of the semiconductor structure. The semiconductor structure includes: a substrate 1, in which a word line groove 30 is provided; in the word line groove 30, a first word line conductive layer 31 and a second word line conductive layer 32 are stacked; the second word line conductive layer 32 includes a first conductive portion 321 and a second conductive portion 322, the first conductive portion 321 has doped ions, and the resistivity of the first conductive portion 321 is less than the resistivity of the second conductive portion 322; at least part of the sidewall of the first conductive portion 321 is spaced from the inner wall of the word line groove 30; the second conductive portion 322 is in contact with the inner wall of the word line groove 30; a contact plug 81, and the contact plug 81 is electrically connected to the first conductive portion 321. It is worth noting that the inner wall of the word line groove 30 also has a thin gate dielectric layer 2, therefore, “contacting the inner wall of the word line groove 30” in the disclosed embodiment can be understood as “contacting the gate dielectric layer 2 on the inner wall of the word line groove 30”.

Such a design has at least the following advantages:

First, doping ions can adjust the resistivity of the first conductive portion 321, so that the resistivity of the first conductive portion 321 is lower than that of the second conductive portion 322. Compared with the second conductive portion 322, at least a portion of the sidewall of the first conductive portion 321 is spaced apart from the word line trench 30, that is, the first conductive portion 321 and the active area 11 in the substrate 1 can be spaced apart or have less overlapping area, thereby reducing the GIDL current.

Second, the first conductive portion 321 with a lower resistivity is electrically connected to the contact plug 81, thereby reducing the contact In other words, since the first conductive portion 321 has a relatively small resistance, the contact plug 81 can directly contact the first conductive portion 321 without penetrating the second word line conductive layer 32 to contact the first word line conductive layer 31. In this way, the formation process of the contact plug 81 can be simplified.

Specifically, referring to FIG. 1-FIG. 2, for a more intuitive view, FIG. 1 and FIG. 2 only show a part of the structure in the semiconductor structure. The semiconductor structure includes a first direction X and a second direction Y. The first direction X is the arrangement direction of the plurality of word line grooves 30, that is, a direction perpendicular to the sidewalls of the word line grooves 30, and the second direction Y is the extension direction of the word line grooves 30. The second direction Y is perpendicular to the first direction X, and both are parallel to the upper surface of the substrate 1.

Continuing to refer to FIG. 1-FIG. 2, the substrate 1 includes an array region 1ab, wherein the array region 1ab includes a storage region 1a and a contact region 1b. The word line 3 can be formed in the storage region 1a and the contact region 1b, and the contact plug 81 can be formed in the contact region 1b. For example, the contact region 1b and the storage region 1a are arranged in the second direction Y. There can be two contact regions 1b, and the two contact regions 1b are respectively located on opposite sides of the storage region 1a. The total area of the two contact regions 1b is larger than the area of one contact region 1b, which can provide more sufficient space for the contact plug 81 to reduce the parasitic capacitance between multiple contact plugs 81. For example, the contact plugs 81 connected to adjacent word lines 3 can be located in different contact regions 1b. Therefore, a word line 3 can be spaced between adjacent contact plugs 81 in the same contact region 1b, thereby increasing the spacing between adjacent contact plugs 81, and then reducing the parasitic capacitance between adjacent contact plugs 81 to improve the operating speed of the semiconductor structure.

In addition, adjacent contact plugs 81 in the same contact region 1b may be staggered, that is, the two are not directly opposite in the first direction X. It can be understood that the smaller the directly opposite area, the smaller the parasitic capacitance. In this way, the width of the contact plug 81 in the second direction Y can be appropriately increased, thereby increasing the contact area between the contact plug 81 and the second word line conductive layer 32. In other words, even if the width of the contact plug 81 in the second direction Y is large, since the spacing between adjacent contact plugs 81 is large and the directly opposite area is small, a large parasitic capacitance will not be generated between adjacent contact plugs 81.

In some other embodiments, there may be only one contact region 1 b , and the storage region 1 a and the one contact region 1 b are also arranged in the second direction Y.

Referring to Figures 1 to 5, Figure 3 is a cross-sectional view of the semiconductor structure shown in Figure 1 or Figure 2 in the A-A1 direction, Figure 4 is a cross-sectional view of the semiconductor structure shown in Figure 1 or Figure 2 in the B-B1 direction, Figure 5 is a cross-sectional view of the semiconductor structure shown in Figure 1 or Figure 2 in the C-C1 direction, and Figure 3 only shows one contact area 1b. The array area 1ab has a first insulating structure 12, a second insulating structure 13, and a plurality of mutually separate active areas 11. By way of example, the material of the first insulating structure 12 may be silicon oxide, and the material of the second insulating structure 13 may be silicon nitride. The material of the active area 11 may be silicon or germanium.

4, the active region 11 may include a source-drain region 111 and a channel region 112, the source-drain region 111 is located above the channel region 112, and the source-drain region 111 is located on both sides of the top of the word line trench 30, and the channel region 112 is located below the source-drain region 111. The source-drain region 111 includes a source S and a drain D, and the source S and the drain D are respectively located on different sides of the word line trench 30. The source-drain region 111 and the channel region 112 may have opposite types of doped ions, for example, the channel region 112 has P-type doped ions, and the source-drain region 111 has N-type doped ions. For example, the source S is used to connect the capacitor and the drain D is used to connect the bit line.

1 to 9 , the first word line conductive layer 31 and the second word line conductive layer 32 together constitute a word line 3 , which will be described in detail below.

1 to 3, the first word line conductive layer 31 is located in the storage area 1a and the contact area 1b, and extends along the second direction Y, that is, the first word line conductive layer 31 extends in the extension direction of the word line trench 30. In some embodiments, the first word line conductive layer 31 can be a single-layer structure, and the material of the single-layer structure can include metal, metal nitride, such as tungsten, titanium, tantalum, titanium nitride, tantalum nitride or tungsten nitride. In other embodiments, the first word line conductive layer 31 can be a multi-layer structure, for example, the first word line conductive layer 31 includes a barrier layer and a metal layer, the material of the barrier layer can include metal nitride, such as titanium nitride, tantalum nitride or tungsten nitride, and the material of the metal layer can include low-resistance metals such as tungsten, titanium, tantalum, nickel, etc.

For example, the barrier layer may include a first barrier layer and a second barrier layer, wherein the first barrier layer is located on the inner wall of the word line groove 30, the first barrier layer is in contact with the gate dielectric layer 2 on the inner wall of the word line groove 30 and is located between the gate dielectric layer 2 and the word line 3 or between the gate dielectric layer 2 and the first word line conductive layer 31, and the first barrier layer can block the metal atoms of the metal layer from diffusing into the gate dielectric layer 2, thereby ensuring the isolation performance of the gate dielectric layer 2 and avoiding leakage current between the channel region 112 and the word line 3. The second barrier layer may be located on the upper surface of the first word line conductive layer 31 and in contact with the second word line conductive layer 32, and the second barrier layer can prevent the metal atoms of the first word line conductive layer 31 from diffusing toward the second word line conductive layer 32, thereby avoiding increasing the GIDL current. In other embodiments, the barrier layer may include only one of the first barrier layer and the second barrier layer.

The first word line conductive layer 31 may have a high work function, thereby increasing the work function difference between the first word line conductive layer 31 and the channel region 112. This work function difference can form an electric field between the first word line conductive layer 31 and the channel region 112, and the electric field can enhance the effect of the threshold voltage of the word line 3, that is, improve the utilization rate of the voltage of the word line 3. In other words, the electric field can make the threshold voltage of the word line 3 lower, thereby reducing power consumption.

It is worth noting that, referring to FIG4 , in some embodiments, the first word line conductive layer 31 does not overlap with the source and drain regions 111, that is, the top surface of the first word line conductive layer 31 may be flush with or lower than the bottom surface of the source and drain regions 111. Thus, the first word line conductive layer 31 may be prevented from increasing the GIDL current.

Since the second word line conductive layer 32 and the source and drain regions 111 have an overlapping area in a direction perpendicular to the surface of the substrate 1, the second word line conductive layer 32 can be made of a material with a lower work function to reduce the GIDL current, thereby avoiding affecting the retention time and write recovery time of the DRAM, thereby improving the performance of the semiconductor structure. For example, the material of the second word line conductive layer 32 may include a non-metallic conductive material such as polysilicon or polycrystalline germanium.

In some embodiments, the type of doping ions of the first conductive portion 321 is N-type. At the same doping concentration, the resistance of the first conductive portion 321 with N-type doping ions is lower than that of the second conductive portion 322 with P-type doping ions, and it is easier to form an ohmic contact with the contact plug 81, which is beneficial to reduce the contact resistance. In other embodiments, the doping ions of the first conductive portion 321 may also be P-type. In addition, the concentration of P-type doping ions can be increased to ensure the formation of ohmic contact. N-type doping ions may include one or more of phosphorus and arsenic, and P-type doping ions may include one or more of boron, aluminum, and indium.

For example, the doping concentration of the first conductive portion 321 is greater than or equal to 1E23/μm ³ . The doping concentration within the above range can ensure that the first conductive portion 321 has a lower resistance and can ensure that the first conductive portion 321 forms an ohmic contact with the contact plug 81 , thereby facilitating the improvement of the operating speed of the semiconductor structure.

In some embodiments, in the direction from the first word line conductive layer 31 to the second word line conductive layer 32, that is, in the direction from bottom to top, the doping concentration in the first conductive portion 321 can be in an increasing trend, that is, the doping concentration of the first conductive portion 321 in contact with the contact plug 81 can be greater than the doping concentration of the first conductive portion 321 in contact with the first word line conductive layer 31, thereby reducing the contact resistance difference caused by the contact area between the first conductive portion 321 and the two.

In some embodiments, the second conductive portion 322 does not have doping ions, which is beneficial to reducing the GIDL current. In other embodiments, the second conductive portion 322 has doping ions, thereby more flexibly adjusting the work function of the word line 3, thereby adjusting the threshold voltage of the transistor. When the second conductive portion 322 has doping ions, the doping concentration of the second conductive portion 322 is less than the doping concentration of the first conductive portion 321, so as to reduce the GIDL current.

4 to 9 , the ratio of the width of the first conductive portion 321 in the first direction X to the width of the second word line conductive layer 32 in the first direction X can be 0.5 to 0.75, for example, 0.6, 0.63 or 0.7. When the widths of the two are within the above range, the contact area between the first conductive portion 321 and the contact plug 81 can be effectively increased while avoiding the generation of GIDL current, thereby reducing the contact resistance.

The positional relationship between the first conductive portion 321 and other structures will be described in detail below.

1 , the first word line conductive layer 31 and the second conductive portion 322 are located in the storage area 1a and the contact area 1b. And both extend in the extension direction of the word line groove 30; the first conductive part 321 is located in the contact area 1b. That is, the first conductive part 321 is a block structure, and the contact area between the first conductive part 321 and the second conductive part 322 is small, which can prevent more doped ions in the first conductive part 321 from diffusing into the second conductive part 322, thereby helping to reduce the GIDL current. For example, the first conductive part 321 located in the contact area 1b is surrounded by the second conductive part 322, and at this time, all side walls of the first conductive part 321 are spaced from the inner wall of the word line groove 30.

In some other embodiments, referring to FIG. 2 , the first conductive portion 321 extends in the extension direction of the word line trench 30. That is, the first conductive portion 321 is a strip structure, and the first conductive portion 321 can be located in the contact area 1b and the storage area 1a at the same time. This is conducive to reducing the overall resistance of the word line 3, thereby improving the operating speed of the semiconductor structure.

Referring to FIG. 6-FIG. 8, FIG. 6-FIG. 8 are different cross-sectional views of the semiconductor structure shown in FIG. 1 or FIG. 2 in the D-D1 direction. In some embodiments, the first conductive portion 321 and the second conductive portion 322 are in contact with the first word line conductive layer 31. That is, the peripheral signal can be applied to the first word line conductive layer 31 through the contact plug 81 and the first conductive portion 321 in sequence. Since the resistance of the first conductive portion 321 is smaller than that of the second conductive portion 322, the first conductive portion 321 is directly in contact with the first word line conductive layer 31, which is conducive to improving the transmission rate of the signal.

In other embodiments, referring to FIG. 9 , FIG. 9 is another cross-sectional view of the semiconductor structure shown in FIG. 1 and FIG. 2 in the D-D1 direction, the second conductive portion 322 is in contact with the first word line conductive layer 31, and the first conductive portion 321 is spaced apart from the top surface of the first word line conductive layer 31. That is, the second conductive portion 322 covers the bottom surface of the first conductive portion 321, and the signal provided by the peripheral device can be applied to the first word line conductive layer 31 through the contact plug 81, the first conductive portion 321, and the second conductive portion 322 in sequence.

3-6, in some embodiments, the top surface of the first conductive part 321 is flush with the top surface of the second conductive part 322. That is, the top surface of the first conductive part 321 and the top surface of the second conductive part 322 are both planes and are at the same height, which is conducive to simplifying the manufacturing process.

In other embodiments, referring to FIG. 7 , the top surface of the first conductive portion 321 is higher than the top surface of the second conductive portion 322, thereby increasing the surface area of the first conductive portion 321 exposed by the second conductive portion 322, thereby facilitating increasing the contact area between the contact plug 81 and the second conductive portion 322, thereby reducing the contact resistance. For example, the top surface of the first conductive portion 321 may be an arc surface; or the top surface of the first conductive portion 321 may be a plane, and part of the side wall of the first conductive portion 321 is also exposed by the second conductive portion 322.

In other embodiments, referring to FIG. 8 , the top surface of at least a portion of the first conductive portion 321 in contact with the contact plug 81 is lower than the top surface of the second conductive portion 322, the contact plug 81 is spaced apart from the inner wall of the word line trench 30, the width of the contact plug 81 in the first direction is greater than the width of the first conductive portion 321 in the first direction, and the contact plug 81 has a protrusion 810, and the protrusion 810 is at least located on two opposite sides of the first conductive portion 321. That is, the contact plug 81 not only contacts the top surface of the first conductive portion 321, but also contacts a portion of the sidewall of the first conductive portion 321, thereby increasing the contact area between the first conductive portion 321 and the contact plug 81 to reduce the contact resistance. In addition, the protrusion 810 can also play a role in stabilizing the contact plug 81.

It should be noted that when the first conductive portion 321 is only located in the contact area 1b, that is, when the first conductive portion 321 is a block structure, the protrusion 810 of the contact plug 81 can surround the first conductive portion 321, thereby increasing the contact area between the contact plug 81 and the first conductive portion 321. When the first conductive portion 321 is located in the contact area 1b and the storage area 1a, that is, when the first conductive portion 321 is a strip structure, the protrusion 810 can be located only on two opposite sides of the first conductive portion 321.

In some embodiments, referring to FIG. 4 , part of the sidewall of the first conductive portion 321 may contact the inner wall of the word line trench 30. In this case, the sidewall of the first conductive portion 321 contacting the word line trench 30 may face the source region S, but not the drain region D. That is, the first conductive portion 321 at least does not have an overlapping region with the drain region D, but may have an overlapping region with the source region S. This is because GIDL leakage is generated in the overlapping region of the drain region D and the gate (word line 3).

In some embodiments, referring to FIGS. 1-3 and 5 - 9 , all sidewalls of the first conductive portion 321 are spaced apart from the inner wall of the word line trench 30 , and the second conductive portion 322 is in contact with two opposite inner walls of the word line trench 30 . Such a structure has higher symmetry, which is conducive to simplifying the manufacturing process of the semiconductor structure.

For example, the first conductive portion 321 is at the same distance from two opposite inner walls of the word line trench 30. In this way, the uniformity of the semiconductor structure is better and the manufacturing process is simpler. Alternatively, the first conductive portion 321 is farther away from the inner wall of the word line trench 30 facing the drain region D and closer to the inner wall of the word line trench 30 facing the source region S, which is conducive to reducing the risk of generating GIDL current.

1 to 9 , the word line trench 30 also has a protection layer 6 covering the word line 3. The contact plug 81 also penetrates the protection layer 6. The protection layer 6 may be a single-layer structure, and its material may be an insulating material such as silicon nitride or silicon oxynitride layer.

The peripheral region 1c will be described in detail below.

10 , the peripheral region 1 c has a peripheral device and a peripheral plug 82 ; the peripheral device includes an active layer 14 , and the peripheral plug 82 is electrically connected to the active layer 14 . In addition, the peripheral device may further include a gate structure 15 , and the gate structure 15 is located on the active layer 14 .

The peripheral plug 82 can also be electrically connected to the contact plug 81. For example, the peripheral plug 82 and the contact plug 81 can be electrically connected through a wiring layer (not shown in the figure). That is, the peripheral device can provide a peripheral signal to the word line 3 through the peripheral plug 82, the wiring layer and the contact plug 81. Since the contact plug 81 forms an ohmic contact with the first conductive portion 321, the transmission speed of the peripheral signal is faster.

In addition, the peripheral region 1c also has an isolation layer 64 covering the peripheral device, and the isolation layer 64 is penetrated by the peripheral plug 82. By way of example, the isolation layer 64 can be a multi-layer structure, for example, the isolation layer 64 includes a first isolation layer 61, a second isolation layer 62, and a third isolation layer 63 that are stacked. The material of the first isolation layer 61 and the third isolation layer 63 is the same, and is different from the material of the second isolation layer 62. By way of example, the material of the first isolation layer 61 and the third isolation layer 63 can be silicon nitride, and the material of the second isolation layer 62 can be silicon oxide.

In summary, the second word line conductive layer 32 is designed as a composite structure in the embodiment of the present disclosure, and at least part of the sidewall of the first conductive portion 321 with a smaller resistance in the second word line conductive layer 32 is spaced from the inner wall of the word line trench 30, thereby facilitating the reduction of the overlap area between the first conductive portion 321 and the active area 11, thereby facilitating the reduction of the GIDL current. The contact plug 81 contacts the first conductive portion 321 with a smaller resistance, thereby facilitating the reduction of the contact resistance and improving the RC delay effect.

As shown in Figures 11 to 19, another embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, which can be used to manufacture the semiconductor structure provided by the aforementioned embodiment. For detailed descriptions of the semiconductor structure, reference can be made to the aforementioned embodiment and will not be repeated here. The method for manufacturing the semiconductor structure will be described in detail below in conjunction with the accompanying drawings. It should be noted that Figures 11 to 19 are partial schematic diagrams of the semiconductor structure.

Referring to FIG11 , a substrate 1 is provided, a word line groove 30 is formed on the substrate 1, and a word line 3 filling the word line groove 30 is formed. It should be noted that before forming the word line 3, a thin gate dielectric layer 2 is also formed on the inner wall of the word line groove 30. Therefore, the “contacting the inner wall of the word line groove 30” in the embodiment of the present disclosure can be understood as contacting the gate dielectric layer 2 on the inner wall of the word line groove 30.

Specifically, the substrate 1 in the storage area 1 a and the contact area 1 b is etched to form a plurality of word line trenches 30 extending along the second direction and arranged in the first direction.

Continuing to refer to FIG. 11 , a first word line conductive layer 31 is formed in the word line groove 30. For example, a low-resistance metal such as titanium, tungsten or molybdenum is deposited on the word line groove 30 and the upper surface of the substrate 1 by a chemical vapor deposition process as an initial first word line conductive layer. The initial first word line conductive layer is planarized and etched back to remove the initial first word line conductive layer on the upper surface of the substrate 1 and part of the initial first word line conductive layer in the word line groove 30, and the remaining initial first word line conductive layer is used as the first word line conductive layer 31. That is, the first word line conductive layer 31 is located in the storage area 1a and the contact area 1b, and the first word line conductive layer 31 extends in the extension direction of the word line groove 30.

Continuing to refer to FIG. 11 , an initial second word line conductive layer 320 is formed on the first word line conductive layer 31. For example, polysilicon is deposited on the upper surface of the substrate 1 and in the word line trench 30 by chemical vapor deposition process to form The initial second word line conductive film is planarized and etched back to remove the initial second word line conductive film on the upper surface of the substrate 1 and a portion of the initial second word line conductive film in the word line groove 30, and the remaining initial second word line conductive film is used as the initial second word line conductive layer 320. That is, the initial second word line conductive layer 320 is located in the storage area 1a and the contact area 1b, and the initial second word line conductive layer 320 extends in the extension direction of the word line groove 30.

In some embodiments, during the chemical vapor deposition process, a doping gas may be introduced into the reaction chamber so that the initial second word line conductive layer 320 has doping ions. That is, an in-situ doping process is used to form the doped initial second word line conductive layer 320. In other embodiments, the doping gas may not be introduced to form a pure initial second word line conductive layer 320.

12-15 , a mask layer 5 is formed, which is at least located on the inner wall of the word line trench 30 and covers a portion of the initial second word line conductive layer 320. For example, the mask layer 5 may be a hard mask layer, and its material may include silicon nitride or silicon oxynitride.

Specifically, referring to FIG12 , an atomic layer deposition process is used to form the initial mask layer 50, and the atomic layer deposition process deposits the material in the form of a single atomic layer, so that the initial mask layer 50 can have a uniform thickness. In some embodiments, the initial mask layer 50 can be a conformal covering film layer, that is, the initial mask layer 50 is located on the inner wall of the word line groove 30, the upper surface of the substrate 1, and the upper surface of the initial second word line conductive layer 320, but does not fill the word line groove 30. In other embodiments, the initial mask layer 50 can also fill the word line groove 30.

13-15, FIG. 14-15 are different top views of the semiconductor structure shown in FIG. 13, and the initial mask layer 50 is patterned to form a mask layer 5, that is, a portion of the initial mask layer 50 on the upper surface of the initial second word line conductive layer 320 is removed, and the remaining initial mask layer 50 serves as the mask layer 5. The mask layer 5 has an opening 51, and the opening 51 at least exposes a portion of the initial second word line conductive layer 320 of the contact area 1b.

In some embodiments, referring to FIG. 13 , the graphical processing can remove a portion of the initial mask layer 50 located on the upper surface of the initial second word line conductive layer 320 in the storage area 1a and the contact area 1b, that is, the mask layer 5 simultaneously exposes a portion of the upper surface of the initial second word line conductive layer 320 in the storage area 1a and the contact area 1b, and the orthographic projection of the opening 51 on the substrate 1 is a long strip and extends along the second direction Y.

In other embodiments, referring to FIG. 15 , the patterning process can remove part of the initial mask layer 50 in the word line groove 30 of the contact area 1b. That is, the mask layer 5 fills the word line groove 30 of the storage area 1a, and the mask layer 5 is also located on the inner wall of the word line groove 30 of the contact area 1b, and exposes part of the initial second word line conductive layer 320 of the contact area 1b. That is, the orthographic projection of the opening 51 on the substrate 1 is block-shaped and is only located in the contact area 1b. In the second direction Y, the length of the opening 51 can be equal to or less than the length of the initial second word line conductive layer 320 of the contact area 1b. It is worth noting that, since the contact area 1b has no active area 11, the length of the opening 51 in the second direction Y can also be greater than the width of the initial second word line conductive layer 320 located in the contact area 1b, that is, the opening 51 can also expose the first insulating structure 12 of the contact area 1b, and the shape of the mask layer 5 is similar to a comb.

It should be noted that the mask layer 5 can be located on two opposite inner walls of the word line groove 30 at the same time, or it can be located only on one of the two opposite inner walls of the word line groove 30. For example, part of the initial mask layer 50 near the source region S is removed, and the initial mask layer 50 near the drain region D can be used as the mask layer 5.

16 , the portion of the initial second word line conductive layer 320 exposed by the mask layer 5 is doped to form a second word line conductive layer 32 , the doped portion of the second word line conductive layer 32 serves as a first conductive portion 321 , and the portion of the second word line conductive layer 32 covered by the mask layer 5 serves as a second conductive portion 322 .

For example, ion implantation can be used for doping. During the process of implanting doping ions, heavy atoms, such as arsenic atoms or indium atoms, can also be implanted into the semiconductor structure. Heavy atoms can reduce the degree of scattering to reduce the doping atoms scattered to the second conductive portion 322, thereby avoiding affecting the electrical properties of the second conductive portion 322.

At this point, based on the steps shown in FIG. 10 to FIG. 16 , a word line 3 can be formed in the word line trench 30, and the word line 3 includes a first word line conductive layer 31 and a second word line conductive layer 32 stacked; the second word line conductive layer 32 includes a first conductive portion 321 and a second conductive portion 322, the first conductive portion 321 has doped ions, and the first conductive portion 322 has a first conductive portion 321 and a second conductive portion 322. The resistivity of the first conductive portion 321 is less than that of the second conductive portion 322; at least part of the sidewall of the first conductive portion 321 is spaced apart from the inner wall of the word line groove 30; the second conductive portion 322 is in contact with the inner wall of the word line groove 30. It should be noted that the aforementioned steps of forming the second word line conductive layer 32 are exemplary, and in other embodiments, the steps of forming the second word line conductive layer 32 may be adjusted. For example, after forming the mask layer 5, the initial second word line conductive layer 320 exposed by the mask layer 5 may be removed, and the remaining initial second word line conductive layer 320 is used as the second conductive portion 322, and then a chemical vapor deposition process and an in-situ doping process are used to form the first conductive portion 321.

17 , the mask layer 5 is removed, and a protection layer 6 is formed to cover the word line 3. For example, an insulating material such as silicon nitride is deposited in the word line trench 30 and on the upper surface of the substrate 1 as the protection layer 6 by chemical vapor deposition.

18 and 6, a contact plug 81 is formed, and the contact plug 81 is connected to the first conductive portion 321. Specifically, referring to FIG18, the protective layer 6 is etched to form a first through hole 71 penetrating the protective layer 6, and the first through hole 71 at least exposes the first conductive portion 321. Referring to FIG18, a metal such as copper, tungsten, or molybdenum is deposited in the first through hole 71 as the contact plug 81. The contact plug 81 is spaced apart from the inner wall of the word line trench 30 to avoid leakage.

It should be noted that, in some embodiments, during the process of forming the first through hole 71, only the protection layer 6 may be etched so that the top surfaces of the first conductive portion 321 and the second conductive portion 322 remain flush. In other embodiments, a portion of the first conductive portion 321 may be etched so that the top surface of the first conductive portion 321 is lower than the top surface of the second conductive portion 322, and the bottom of the contact plug 81 formed subsequently may be embedded in the second word line conductive layer 32. Alternatively, part of the second conductive part 322 may be etched while etching the first conductive part 321. For example, the etching rate of the first conductive part 321 may be the same as the etching rate of the second conductive part 322, that is, the contact plug 81 formed subsequently has a relatively flat bottom surface. The etching rate of the first conductive part 321 may also be lower than the etching rate of the second conductive part 322, that is, the first through hole 71 may also expose part of the side wall of the first conductive part 321. The contact plug 81 formed subsequently has a protrusion 810 (see FIG. 8 ). The protrusion 810 is located on part of the side wall of the first conductive part 321. The protrusion 810 may increase the contact area between the contact plug 81 and the first conductive part 321, and may also stabilize the contact plug 81.

19 , a peripheral device is formed in the peripheral region 1c, and the peripheral device includes an active layer 14. By way of example, the peripheral device may further include a gate structure 15, and the gate structure 15 and the active layer 14 constitute a transistor.

19, an isolation layer 64 covering the peripheral device is formed. For example, multiple chemical vapor deposition processes are used to form a stacked first isolation layer 61, a second isolation layer 62 and a third isolation layer 63 to serve as the isolation layer 64 of the peripheral area 1c. The first isolation layer 61 can be formed in the same process step as the protective layer 6.

19 and 10 , while the contact plug 81 is formed, a peripheral plug 82 is formed in the protective layer 6 , and the peripheral plug 82 is electrically connected to the active layer 14 .

19, the isolation layer 64 is etched to form a second through hole 72 penetrating the isolation layer 64. The first through hole 71 and the second through hole 72 may be formed in the same process step.

10 , metal is deposited in the second through hole 72 to serve as the peripheral plug 82. It should be noted that metal can be deposited in the first through hole 71 and the second through hole 72 at the same time, so that the peripheral plug 82 and the contact plug 81 are formed in the same process step, thereby simplifying the production process.

It should be noted that if the second word line conductive layer 32 does not have the first conductive portion 321, that is, the resistivity of the entire second word line conductive layer 32 is relatively large, in order to avoid affecting the operating rate of the semiconductor structure, the contact plug 81 needs to penetrate the second word line conductive layer 32 so as to be directly connected to the first word line conductive layer 31. However, compared with the active layer 14 of the peripheral area 1c, the first word line conductive layer 31 is deeper in the substrate 1. If the first through hole 71 and the second through hole 72 are formed at the same time, the active layer 14 will be over-etched, or the first word line conductive layer 31 cannot be exposed. Therefore, the first through hole 71 and the second through hole 72 are usually formed in different process steps, and the production cost is relatively high. In the embodiment of the present disclosure, a first conductive portion 321 with a relatively small resistivity is formed in the second word line conductive layer 32, so that the contact plug 81 directly contacts the first conductive portion 321 to meet the requirement of relatively small contact resistance. The second word line conductive layer 32 does not need to be etched through. Compared with the first word line conductive layer 31, the depth of the second word line conductive layer 32 in the substrate 1 is closer to the depth of the active layer 14 in the substrate 1. Therefore, the first through hole 71 and the second through hole 72 can be formed in the same process step, thereby reducing the production cost.

The manufacturing method further includes: forming a wiring layer (not shown in the figure), and the peripheral plug 82 is electrically connected to the contact plug 81 through the wiring layer. For example, an insulating layer is formed on the protective layer 6, the insulating layer is etched to form a wiring filling groove in the insulating layer, and the wiring layer is formed in the wiring filling groove.

In summary, the doping of ions in the first conductive portion 321 ensures high conductivity and is conducive to reducing contact resistance. At least part of the sidewall of the first conductive portion 321 is spaced from the inner wall of the trench to reduce the overlap area between the first conductive portion 321 and the active area 11, thereby reducing the GIDL current and ensuring the operating speed of the semiconductor structure.

In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and cannot be construed as limitations on the present disclosure. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and specification of the present disclosure shall fall within the scope of the patent of the present disclosure.

Claims

A semiconductor structure, comprising:

A substrate (1), wherein the substrate (1) has a word line groove (30);

The word line groove (30) has a first word line conductive layer (31) and a second word line conductive layer (32) stacked in a stack;

The second word line conductive layer (32) comprises a first conductive portion (321) and a second conductive portion (322), wherein the first conductive portion (321) has doped ions, and the resistivity of the first conductive portion (321) is smaller than the resistivity of the second conductive portion (322); at least a portion of the sidewall of the first conductive portion (321) is spaced from the inner wall of the word line groove (30); and the second conductive portion (322) is in contact with the inner wall of the word line groove (30);

A contact plug (81), the contact plug (81) being electrically connected to the first conductive portion (321).
The semiconductor structure according to claim 1, characterized in that the first conductive portion (321) and the second conductive portion (322) are in contact with the first word line conductive layer (31); or

The second conductive portion (322) is in contact with the first word line conductive layer (31), and the first conductive portion (321) is spaced apart from a top surface of the first word line conductive layer (31).
The semiconductor structure according to claim 1 or 2, characterized in that the top surface of the first conductive part (321) is flush with or higher than the top surface of the second conductive part (322).
The semiconductor structure according to any one of claims 1 to 3, characterized in that the first conductive portion (321) extends in an extension direction of the word line trench (30).
The semiconductor structure according to any one of claims 1 to 4, characterized in that all side walls of the first conductive portion (321) are spaced apart from the inner wall of the word line trench (30), and the second conductive portion (322) is in contact with two opposite inner walls of the word line trench (30).
The semiconductor structure according to any one of claims 1 to 3 or 5, characterized in that the substrate (1) comprises a storage area (1a) and a contact area (1b);

The first word line conductive layer (31) and the second conductive portion (322) are located in the storage area (1a) and the contact area (1b), and both extend in the extension direction of the word line groove (30);

The first conductive portion (321) is located in the contact area (1b) and is surrounded by the second conductive portion (322).
The semiconductor structure according to any one of claims 1 to 2 or any one of claims 4 to 6, characterized in that a top surface of at least a portion of the first conductive portion (321) in contact with the contact plug (81) is lower than a top surface of the second conductive portion (322), the contact plug (81) is spaced apart from an inner wall of the word line groove (30), a width of the contact plug (81) in a first direction (X) is greater than a width of the first conductive portion (321) in the first direction (X), and the contact plug (81) has a protrusion (810), and the protrusion (810) is located at least on two opposite sides of the first conductive portion (321); the first direction (X) is perpendicular to an extension direction of the word line groove (30) and parallel to an upper surface of the substrate (1).
The semiconductor structure according to any one of claims 1 to 7, characterized in that the type of doping ions in the first conductive portion (321) is N-type.
The semiconductor structure according to any one of claims 1 to 8 is characterized in that the second conductive portion (322) does not contain doping ions; or the second conductive portion (322) contains doping ions, and the doping concentration of the second conductive portion (322) is less than the doping concentration of the first conductive portion (321).
The semiconductor structure according to any one of claims 1 to 9, characterized in that the doping concentration of the first conductive portion (321) is greater than or equal to 1E23/μm 3 .
The semiconductor structure according to any one of claims 1 to 10, characterized in that the substrate (1) further comprises a peripheral region (1c);

The peripheral area (1c) has peripheral devices and peripheral plugs (82);

The peripheral device includes an active layer (14), and the peripheral plug (82) is electrically connected to the active layer (14) and the contact plug (82).
A method for manufacturing a semiconductor structure, comprising:

Providing a substrate (1), and forming a word line groove (30) in the substrate (1);

forming a first word line conductive layer (31) and a second word line conductive layer (32) which are stacked in the word line groove (30);

The second word line conductive layer (32) comprises a first conductive portion (321) and a second conductive portion (322), wherein the first conductive portion (321) has doped ions, and the resistivity of the first conductive portion (321) is smaller than the resistivity of the second conductive portion (322); at least a portion of the sidewall of the first conductive portion (321) is spaced from the inner wall of the word line groove (30); and the second conductive portion (322) is in contact with the inner wall of the word line groove (30);

A contact plug (81) is formed, wherein the contact plug (81) is connected to the first conductive portion (321).
The method for manufacturing a semiconductor structure according to claim 12, characterized in that the step of forming the second word line conductive layer (32) comprises:

forming an initial second word line conductive layer (320) on the first word line conductive layer (31);

forming a mask layer (5), wherein the mask layer (5) is at least located on the inner wall of the word line trench (30) and covers a portion of the initial second word line conductive layer (320);

The portion of the initial second word line conductive layer (320) exposed by the mask layer (5) is doped to form a second word line conductive layer (32), the doped portion of the second word line conductive layer (32) serving as the first conductive portion (321), and the portion of the second word line conductive layer (32) covered by the mask layer serving as the second conductive portion (322).
The method for manufacturing a semiconductor structure according to claim 13, characterized in that the substrate (1) comprises a storage area (1a) and a contact area (1b), the first word line conductive layer (31) and the initial second word line conductive layer (320) are both located in the storage area (1a) and the contact area (1b), and both extend in the extension direction of the word line trench (30);

The mask layer (5) completely fills the word line groove (30) of the storage area (1a); the mask layer (5) is also located on the inner wall of the word line groove (30) of the contact area (1b), and exposes a portion of the initial second word line conductive layer (320) of the contact area (1b);

A doping process is performed on the portion of the initial second word line conductive layer (320) exposed by the mask layer (5) to form the first conductive portion (321) in the contact area (1b).
The method for manufacturing a semiconductor structure according to any one of claims 12 to 14, characterized in that the substrate further comprises a peripheral region (1c), and the peripheral region (1c) has an active layer (14); the manufacturing method further comprises:

A peripheral device is formed in the peripheral area (1c); the peripheral device includes an active layer (14);

forming an isolation layer (64) covering the peripheral device;

While forming the contact plug (81), a peripheral plug (82) is formed in the isolation layer (64), wherein the peripheral plug (82) is electrically connected to the active layer (14);

A wiring layer is formed, and the peripheral plug (82) is electrically connected to the contact plug (81) through the wiring layer.