WO2024144020A1

WO2024144020A1 - Sar-adc having capacitor correction function, and digital conversion method for analog signal using same

Info

Publication number: WO2024144020A1
Application number: PCT/KR2023/020643
Authority: WO
Inventors: 고재간; 이봉준
Original assignee: 주식회사 램쉽
Priority date: 2022-12-29
Filing date: 2023-12-14
Publication date: 2024-07-04
Also published as: KR20240106168A

Abstract

This SAR-ADC having a capacitor correction function applies a voltage corresponding to a difference from a known reference voltage to one end of a capacitor (measurement target capacitor) to be measured among capacitors constituting a capacitor array, and measures a voltage applied to be equivalent to a weight of the measurement target capacitor by using a basic operation of the corresponding SAR-ADC, thereby measuring a weight of the capacitor to be corrected, and calculating an output value of the SAR-ADC by using the measured values to correct an error of the capacitor.

Description

SAR-ADC with capacitor compensation function and digital conversion method of analog signal using it

The present invention relates to a technology that can correct capacitor error in SAR-ADC.

The structure of the SAR (Successive-Approximation Register) ADC is introduced in Patent Document 1, etc. The SAR ADC can convert the input signal into a digital code corresponding to the input by measuring it repeatedly several times while changing the reference value (Vdac). The resolution increases as the number of repetitions, and it can be operated with only a 1-bit comparator. , It is an ADC suitable for low-power, high-resolution performance.

The method of determining the amount of movement of the reference voltage compared to the input voltage according to the operation of one cycle is the traditional binary search method, and the redundant search method that takes margin for comparator error in each cycle. It can be shared.

When performing a binary search method for 5-bit resolution, depending on the result of determining whether the input size is 16 or more, the next cycle determines whether it is 24 or more or 8 or more [16, 8, 4, 2. , 1], the size of the reference voltage is changed and compared. However, this binary search method has the disadvantage of not being able to restore the original value when an error occurs in a certain cycle due to comparator offset or temperature noise. To overcome this, a redundant search method was proposed. It has been done.

Redundancy secured in the redundant search method has the disadvantage of requiring an increase in the number of cycles required compared to the binary search method. However, by using the secured margin, it is possible to move on to the next cycle before the DAC output value is completely stabilized, thereby ensuring full conversion. Time can have a reducing effect. On the other hand, the binary search method requires sufficient time to be allocated to each cycle so that the DAC's output value can be stabilized to less than 1/2 LSB.

The binary search method and the redundant search method are generally implemented including CDAC.

Regardless of how it is implemented, the weights of the capacitors included in the CDAC must be accurate for the final output value to be accurate. Here, the weights of the capacitors are elaborately designed using unit capacitors, but they differ from the designed values due to process errors that inevitably occur during the chip manufacturing process, so there is a need to reduce the weight errors of these capacitors. there is.

Meanwhile, a technology related to capacitor mismatch correction that measures the weight of each capacitor using an external input Vin is introduced in Patent Document 1. However, the correction method using external input has limitations in terms of cost and practicality in actually implementing the correction process, so technology that can self-correct for the effects of capacitor mismatch and parasitic capacitors is required.

<Patent Document 1> KR 10-1586407 B1

<Non-patent document 1> InProceedings (4746011), Ogawa, Tomohiko / Kobayashi, Haruo / Hotta, Masao / Takahashi, Yosuke / San, Hao / Takai, Nobukazu “SAR ADC algorithm with redundancy” APCCAS, 2008 IEEE Asia Pacific Conference on Circuits and Systems, p. 268-271

<Non-patent Document 2> InProceedings (4523149), Agnes, Andrea / Bonizzoni, Edoardo / Malcovati, Piero / Maloberti, Franco, A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator, 2008 IEEE International Solid- State Circuits Conference - Digest of Technical Papers, p. 246-610

One aspect of the present invention can provide a SAR-ADC equipped with a capacitor correction function that can correct capacitor error using already prepared capacitors.

One aspect of the present invention can provide a method of digital conversion of an analog signal with improved precision by correcting capacitor error using already prepared capacitors.

A SAR-ADC equipped with a capacitor correction function according to an embodiment of the present invention, which was created to achieve the above problem, is a capacitor to be measured ( The weight of the capacitor to be corrected is actually measured by applying a voltage equal to the weight of the measurement target capacitor to the other end of the measurement target capacitor and measuring the applied voltage using the basic operation of the relevant SAR-ADC, and using the actually measured values to measure the SAR -By calculating the output value of the ADC, the error of the capacitor can be corrected.

The digital conversion method of an analog signal according to an embodiment of the present invention applies a voltage corresponding to the difference between a known reference voltage to the other end of the capacitor to be measured, and applies a voltage equal to the weight of the capacitor to be measured to the SAR-ADC. By measuring using the basic operation of , the weight of the capacitor to be corrected can be actually measured, and the output value of the SAR-ADC can be calculated using the actually measured values to correct the error of the capacitor.

A SAR-ADC equipped with a capacitor compensation function according to an embodiment of the present invention outputs an input voltage, which is an analog signal, with n-bit resolution, and includes a main switch; 1st to n-1th capacitors whose upper plates are connected to the other end of the main switch; first to n-1th switches, one end of which is connected to a lower plate of each of the first to n-1th capacitors; A comparator including a first terminal to which the other end of the main switch is connected, a second terminal to which the first reference voltage is applied, and a third terminal that outputs a result of comparing the voltages of the first terminal and the second terminal; a switch controller that controls the main switch and the first to n-1th switches; an operator that performs calculations using the output of the third terminal; and a control unit that applies a control command to the switch controller using the operation result of the operator, wherein at least one of the first to n-1 switches is operated according to a command of the switch controller. -1 One of the first reference voltage, a second reference voltage greater than the first reference voltage, and a third reference voltage less than the first reference voltage may be selectively applied to the lower plate of the capacitor or may be opened.

At this time, the design weights of the first to n-1th capacitors are defined as Pd(1) to Pd(n-1), respectively, and the actual weights of the first to n-1th capacitors are defined as Pr(1) to Pd(n-1), respectively. It is defined as Pr(n-1), and the control unit generates a control command so that the switch controller operates in one mode selected from normal mode and compensation mode, and the output of the third terminal in the normal mode is D(k ), and in the normal mode, the output terminal of the calculator is defined as ADC_out, and at least one of the Pr(1) to Pr(n-1) is determined in the correction mode, and the normal mode is in progress. The calculator can calculate the ADC_out by applying the actual weight obtained in the correction mode.

In addition, Pr(x), one of Pr(1) to Pr(n-1), is derived by calculating the equation below,

The d(k) is a value defined as 1 when the comparator output in the correction mode is high, and -1 when the comparator output is low.

In addition, the actual weight may be applied to the P(k) for capacitors for which the actual weight has already been derived, and the design weight may be applied to the capacitor for which the actual weight has not been derived.

In addition, the ADC_out is derived by calculating the equation below,

Pr(k) is preferentially applied to the PP(k), and if Pr(k) is not present, Pd(k) may be applied.

In addition, m is an integer greater than 1 and less than n-1, and PP(k) can be defined as Pr(k) when k is greater than m, and Pd(k) when k is less than m. there is.

In the digital conversion method of an analog signal according to an embodiment of the present invention, in the correction mode, a process of calculating the actual weight Pr(x) of the capacitor to be measured is performed, wherein the other end of the first to n-1th switches and the Step A0 in which the first reference voltage is applied to the first terminal; Step A1 of applying the second reference voltage to the lower plate of the capacitor to be measured and storing the output of the comparator after the voltage of the first terminal is stabilized; A2 step of changing the reference voltage applied to the lower plate of the capacitor with the largest design weight in the set of capacitors to be applied and storing the comparator output after the comparator is stabilized; Step A3 of excluding the capacitor for which step A2 has been performed from the set of capacitors subject to application; and step A4 of feeding back the applied capacitor set in step A3 to step A2. However, the reference voltage in step A2 is changed to the third reference voltage when the comparator output is high. If the comparator output is low, it is changed to the second reference voltage, and the set of capacitors to be applied in the A2 stage is composed of capacitors whose design weight or actual weight is smaller than the capacitor to be measured, By sequentially performing steps A2 to A4 for capacitors included in the set of capacitors to be applied, the actual weight of the capacitor to be measured can be derived.

At this time, the actual weight Pr(x) of the capacitor to be measured is derived by calculating the equation below,

The x is an integer greater than or equal to 1 and less than or equal to n-1, and the d(k) is set to 1 when the operator receives one of the comparator output stored in step A1 and the comparator output stored while repeatedly performing step A2. After conversion, the row can be the value converted to -1.

In addition, the P(k) may have an actual weight applied to a capacitor for which an actual weight has already been derived, and a design weight may be applied to a capacitor for which an actual weight has not been derived.

In addition, the actual weight Pr(x) of the capacitor to be measured is derived by calculating the equation below,

The x is an integer greater than m and less than or equal to n-1, the m is an integer greater than 1 and less than n-1, and d(k) is the comparator output stored in step A1 and stored while the step A2 is repeatedly performed. The operator may receive any one of the comparator outputs and convert high to 1 and low to -1.

In addition, the ADC_out is derived by calculating the equation below,

The PP(k) may be defined as Pr(k) when k is greater than m, and as Pd(k) when k is less than m.

According to an embodiment of the present invention, capacitor errors can be corrected using already prepared capacitors, and the precision of digital conversion of analog signals can be improved by using the error correction results.

1 is a diagram schematically illustrating a SAR-ADC equipped with a capacitor compensation function according to an embodiment of the present invention;

Figure 2 is a diagram schematically illustrating a modification of Figure 1,

Figure 3 is a diagram for explaining a SAR-ADC equipped with a capacitor compensation function according to another embodiment of the present invention;

Figure 4 (a) is a diagram schematically illustrating a general capacitor array, and Figure 4 (b) is a diagram schematically illustrating a capacitor array to which a split deck structure is applied.

Figure 5 is a diagram for explaining the normal mode driving method of the SAR-ADC equipped with a capacitor compensation function according to an embodiment of the present invention;

Figure 6 is a diagram for explaining a compensation mode driving method of a SAR-ADC equipped with a capacitor compensation function according to an embodiment of the present invention.

Figure 1 is a diagram schematically illustrating a SAR-ADC 100 equipped with a capacitor correction function according to an embodiment of the present invention, Figure 2 is a diagram schematically illustrating a modification of Figure 1, and Figure 3 is a diagram schematically illustrating a modification of Figure 1. This is a diagram for explaining the SAR-ADC 100 equipped with a capacitor compensation function according to another embodiment of the present invention. Figure 4 (a) is a diagram schematically illustrating a general capacitor array, and Figure 4 (b) is a diagram schematically illustrating a general capacitor array. ) is a diagram schematically illustrating a capacitor array to which a split deck structure is applied, and Figure 5 is a diagram illustrating the normal mode driving method of the SAR-ADC (100) equipped with a capacitor compensation function according to an embodiment of the present invention. 6 is a diagram for explaining the compensation mode driving method of the SAR-ADC 100 equipped with a capacitor compensation function according to an embodiment of the present invention.

Referring to the drawing, the SAR-ADC 100 equipped with a capacitor correction function according to an embodiment of the present invention can correct errors in capacitors included in a capacitor array (also referred to as CDAC) in a general SAR-ADC. there is. Additionally, the output accuracy of the SAR-ADC can be improved by reflecting the correction results.

The SAR-ADC (100) equipped with a capacitor correction function according to an embodiment of the present invention can output the input voltage (Vin), which is an analog signal, with n-bit resolution. In one embodiment, the SAR-ADC (100) equipped with a capacitor compensation function includes a main switch (SWc), first to n-1th capacitors (C(1) to C(n-1)), and first to n-th capacitors (C(1) to C(n-1)). It includes an n-1 switch (SW(1) to SW(n-1)), a comparator 110, a switch controller 130, an operator 140, and a control unit 150. Here, the default capacitor C(0) of FIGS. 1 and 2 may be included to set the conversion gain of the ADC to 1.

The other end of the main switch (SWc) and the top plates of the first to n-1th capacitors may be connected to the first terminal 111 of the comparator 110. In one embodiment, the first reference voltage (Vcm) may be selectively connected to one end of the main switch (SWc).

A first reference voltage (Vcm) may be applied to the second terminal 112 of the comparator 110, and a comparison result may be output to the third terminal 113 of the comparator 110. The comparator 110 compares the value input to the first terminal 111 with the value input to the second terminal 112 and sends a high signal to the third terminal if the value input to the first terminal 111 is large. It can be output to (113), and vice versa, low can be output to the third terminal (113). In one embodiment, high may match a digital value of 1 and low may match a digital value of 0.

First to n-1th switches may be connected to the lower plates of the first to n-1th capacitors.

In one embodiment, capacitors included in the capacitor array 120 may have a design weight and an actual weight. Here, the design weights of the first to n-1th capacitors are defined as Pd(1) to Pd(n-1), respectively, and the actual weights of the first to n-1th capacitors are defined as Pr(1) to Pr( It can be defined as n-1). Due to the above-described errors in the manufacturing process, a difference occurs between the design weight Pd and the actual weight Pr, and the actual weight Pr can be derived in the SAR-ADC (100) equipped with a capacitor compensation function according to an embodiment of the present invention. there is. Additionally, the conversion can be performed more precisely by performing analog-to-digital conversion using the derived actual weights.

In one embodiment, the other end of the main switch (SWc) may be connected to the first reference voltage (Vcm) or may be open.

In one embodiment, the input voltage Vin may be applied to one end of the main switch SWc, as illustrated in FIG. 1, so that the input voltage Vin sampling process of the ADC may be performed. In another embodiment, the input voltage Vin may be applied to the first to n-1th switches, as illustrated in FIG. 2, so that the input voltage Vin sampling process of the ADC is performed.

Through the first to n-1th switches, the first reference voltage (Vcm), the second reference voltage (Vrefp), and the third reference voltage (Vrefm) can be selectively applied to the first to n-1th switch capacitors. there is.

The switch controller 130 receives the output of the comparator 110, generates a control signal that varies depending on the output of the comparator 110, and determines the connection position of at least one of the first to n-1 switches and the main switch (SWc). can be controlled. In one embodiment, the switch controller 130 may provide a clock signal (ck) to the comparator 110 to adjust the timing at which the comparator 110 outputs a comparison result.

In one embodiment, the second reference voltage (Vrefp) may have a higher value than the first reference voltage (Vcm), and the third reference voltage (Vrefm) may have a lower value than the first reference voltage (Vcm). Additionally, the first reference voltage (Vcm) may be determined as an intermediate value between the second reference voltage (Vrefp) and the third reference voltage (Vrefm). For example, the first reference voltage (Vcm) may be determined to be 0, the second reference voltage (Vrefp) may be determined to be 1, and the third reference voltage (Vrefm) may be determined to be -1.

The calculator 140 can perform a calculation process using the value output from the third terminal 113 of the comparator 110. Additionally, the calculator 140 can convert the input voltage Vin, which is an analog signal, into a digital value and output the value through the output terminal 141.

The control unit 150 can control the operation method of the switch controller 130 by generating a control command using the operation result of the operator 140 and applying the control command to the switch controller 130. Here, the operation method may include a normal mode operation method and a correction mode operation method. By performing the correction mode, the actual weight of the capacitors included in the capacitor array can be derived, and by performing the normal mode, the input voltage ( Vin) can be converted to a digital value and output.

In one embodiment, the output of the third terminal 113 in the normal mode may be defined as D(k), and the output of the output terminal 141 of the calculator 140 may be defined as ADC_out in the normal mode. Additionally, at least one of Pr(1) to Pr(n) may be determined in correction mode. Additionally, during the normal mode process, the calculator 140 can calculate ADC_out by applying the actual weight determined in the correction mode.

In one embodiment, the actual weight Pr(x) of the xth capacitor included in the capacitor array can be derived by calculating Equation 1, where d(k) is the output of the comparator 110 in compensation mode. If this value is high, it is defined as 1, and if the output of the comparator 110 is low, it is defined as -1.

In one embodiment, the actual weight may be applied to P(k) in Equation 1 for capacitors for which the actual weight has already been derived, and the design weight may be applied to the capacitor for which the actual weight has not been derived.

In one embodiment, ADC_out can be derived by calculating Equation 2. In Equation 2, Pr(k) is first applied to PP(k), and if Pr(k) is not present, Pd(k) is applied. You can.

A split-deck structured capacitor array is advantageous compared to a general capacitor array in reducing the area of the capacitor array under the same conditions.

Meanwhile, errors in the manufacturing process commonly occur in the two types of capacitor arrays illustrated in FIG. 4, but in the case of an ADC containing a split-deck capacitor array, in addition to errors in the manufacturing process, weight errors due to parasitic capacitors increase. . Therefore, when an embodiment of the present invention is reflected in an ADC including a capacitor array of a split deck structure, problems caused by weight errors can be more effectively improved.

On the other hand, if the actual weight is larger than the design weight due to an error, rather than performing error correction in an ADC using a traditional binary search method, redundancy is used to allow for the error of the comparator 110 in each cycle. It may be efficient to perform error correction in an ADC using a redundant search method.

In one embodiment, the size of the capacitor from which the actual weight is derived can be determined by taking into account errors expected by the designer in the manufacturing process or errors due to parasitic capacitance.

In one embodiment, the capacitors included in the capacitor array may be arranged so that the design weight increases as the number increases. For example, the design weight of the second capacitor may be designed to be greater than or equal to the design weight of the first capacitor, and the design weight of the n-1th capacitor may be designed to be greater than or equal to the design weight of the n-2th capacitor.

Since capacitors with a large design weight are used to determine the most significant bit (MSB) during analog-to-digital conversion, the error of a capacitor with a large design weight can greatly affect the effective resolution of the ADC compared to the error of a capacitor with a small design weight. there is. Therefore, the larger the design weight of the capacitor, the greater the need to derive the actual weight.

Meanwhile, in order to obtain the actual weight of a capacitor with a small design weight, a capacitor with a design weight small enough to correspond to the error rate is needed. Therefore, it is impossible to derive the actual weight for all capacitors included in the capacitor array, or the actual gain is small. There are cases where it is inefficient. Considering this, in the SAR-ADC (100) equipped with a capacitor correction function according to an embodiment of the present invention, the design weight of the capacitor that derives the actual weight can be set, and for this purpose, the m value can be defined. .

In one embodiment, x in Equation 1 can be an integer greater than m and less than n-1 (m is an integer greater than 1 and less than n-1). Here, the m value can be determined by considering errors expected by the designer in the manufacturing process or errors due to parasitic capacitance. For example, if the expected error rate is 2%, the error will be 10fF for a capacitor with a design capacity of 500fF. Only if there is a capacitor with a capacity smaller than this error of 10fF, the actual weight of the capacitor with a design capacity of 500fF is used. Since it can be derived, the value of m can be determined by taking these matters into consideration.

Meanwhile, the capacitor array for analog-to-digital conversion does not include a capacitor with a sufficiently small design weight, but it may be necessary to obtain an actual weight for a capacitor with a small design weight. For this case, an embodiment of the present invention The SAR-ADC (100) equipped with a capacitor compensation function according to suggests a method of utilizing an auxiliary capacitor with a sufficiently small design weight.

Referring to Figure 3, between the main switch (SWc) and the first terminal 111, auxiliary capacitors (C(-1), C(-2),...) and auxiliary switches (SW(-1), SW(- 2), … ), it is possible to perform compensation mode and derive actual weights even for capacitors with smaller design weights.

In one embodiment, a first compensation mode auxiliary switch (CSW1) is provided between the top plate of the auxiliary capacitor and the first terminal 111, so that the auxiliary capacitor is connected to the capacitor array only in the compensation mode. Accordingly, while improving the precision of capacitor compensation, unnecessary energy loss or malfunction of the analog-digital conversion process can be prevented.

In another embodiment, taking into account the mismatch of the capacitor that may occur or the quantization error that occurs when performing the correction mode using the capacitor in charge of the lower bit, an appropriate m is selected, starting from P(m). Correction mode can be performed by calculating the actual weight.

At this time, P(-1), P(-2), etc. are implemented with a capacitor (the aforementioned auxiliary capacitor) smaller than the unit capacitor, or by subdividing the size of the reference voltage applied to the unit capacitor and connecting it. can do.

In one embodiment, a second compensation mode auxiliary switch (CSW2) that selectively connects or disconnects between at least one of the first to n-1th capacitors and the first terminal 111 may be further provided. The second compensation mode auxiliary switch (CSW2) can be used to separate the corresponding capacitor from the capacitor array in compensation mode. If a correction mode for a capacitor with a small weight is performed while a capacitor with a large weight is connected to the capacitor array, the judgment accuracy of the comparator 110 may be reduced. In this case, at least one of the capacitors with a larger weight than the capacitor to be measured By separating the capacitor from the capacitor array, the accuracy of the comparator 110 judgment can be improved.

The digital conversion method of an analog signal according to an embodiment of the present invention can be implemented by utilizing the SAR-ADC (100) equipped with the capacitor correction function described above.

In one embodiment, a process of calculating the actual weight Pr(x) of the capacitor to be measured may be performed in the correction mode.

First, a first reference voltage (Vcm) may be applied to the other terminal of the first to n-1th switches and the first terminal 111 (step A0).

Next, the second reference voltage (Vrefp) is applied to the lower plate of the capacitor to be measured, and after the voltage at the first terminal 111 is stabilized, the output of the comparator 110 can be stored (step A1).

Next, the reference voltage applied to the lower plate of the capacitor with the largest design weight in the set of capacitors to be applied can be changed and the output of the comparator 110 can be stored after the comparator 110 is stabilized (step A2). Here, the set of capacitors to be applied means a set of capacitors whose design weight or actual weight is smaller than the capacitor to be measured.

Next, the capacitor that has undergone step A2 is excluded from the set of capacitors subject to approval (step A3).

Next, the set of applied capacitors for which step A3 was performed is fed back to step A2 (step A4).

The reference voltage is changed in stage A2. If the output of the comparator 110 is high, it is changed to the third reference voltage (Vrefm), and if the output of the comparator 110 in stage A2 is low, it is changed to the second reference voltage ( Vrefp).

By sequentially performing steps A2, A3, and A4 described above for the capacitors included in the set of capacitors to be applied, the actual weight of the capacitor to be measured can be derived.

Meanwhile, since the second reference voltage was applied to the lower plate of the capacitor to be measured in step A1, when step A2 is first performed for the set of capacitors to be recognized, the comparator output can be changed to the third reference voltage even if it is not judged. In other words, since the second reference voltage is applied in the A1 stage, the comparator output naturally becomes high, and the reference voltage change first applied to the A2 stage is not the second reference voltage applied to the bottom plate of the capacitor to be measured in the A1 stage. 3 All that needs to be done is to change to the standard voltage.

Referring to FIG. 6, looking at the principle of deriving the actual weight P(n-2) of the n-2th capacitor (C(n-2)), during the T(1) period and the first to n-1th switches A first reference voltage (Vcm) is applied to the other end and the first terminal 111. In the drawing, Vbot(n-1) refers to the voltage of the bottom plate of the n-1th capacitor (see FIG. 5).

Next, the second reference voltage (Vrefp) is applied to the lower plate of the n-2th capacitor (C(n-2)), which is the capacitor to be measured, in the T(2) section, and as a result, the voltage of the first terminal 111 It rises by a predetermined gain (e.g., (Vrefp-Vcm)*P(n-2)/sum(P)). Here, the comparator 110 outputs the result of comparing the increased voltage of the first terminal 111 with the voltage of the second terminal 112 and is stored as D(n-3). In one embodiment, the comparison result is high, so D(n-3) is 1, and d(n-3) may also be 1. Meanwhile, the output timing of the comparator 110 can be adjusted by the clock signal ck in such a way that the result output of the comparator 110 is performed at the rising edge of the clock signal ck. Meanwhile, in the drawing, a synchronous type is illustrated in which the clock signal and the operation cycle of the ADC are identical, but it can be implemented asynchronously if necessary. Here, the asynchronous method is a method in which the timing of the next operation varies considering the completion time of the previous operation, and the operation cycle is not constant and can vary.

Next, the sequential progress of steps A2, A3, and A4 is repeated for the capacitors included in the set of capacitors subject to application in the T(3) section. In the situation illustrated in Figure 6, the capacitor set to be applied includes C(n-3), C(n-4), C(n-5),... C(1), C(0), C(-1), C(-2), etc. may be included.

First, since D(n-3) is 1 (High), the n-3th switch is controlled so that the third reference voltage (Vrefm) is applied to the lower plate of C(n-3), and as a result, Vbot(n-3) The first reference voltage (Vcm) is changed to the third reference voltage (Vrefm), and accordingly, the voltage of the first terminal 111 also changes to a predetermined gain (e.g., (Vcm-Vrefm)*P(n-3)/ Descend by sum(P)). Here, the comparator 110 outputs the result of comparing the lowered voltage of the first terminal 111 with the first reference voltage (Vcm), which is the voltage of the second terminal 112, and is stored as D(n-4). . In one embodiment, the comparison result is high, so D(n-4) may be 1, and d(n-4) may be 1. This is the process of performing step A2 for C(n-3). Step A3 is performed to exclude C(n-3) from the set of capacitors to be recognized, and step A4 is performed to select a renewed set of capacitors to be recognized. Feedback to step A2.

Next, since D(n-4) is 1 (High), the n-4th switch is set so that the third reference voltage (Vrefm) is applied to the lower plate of C(n-4), which has the largest design weight in the set of capacitors to be recognized. control, and as a result, Vbot (n-4) changes from the first reference voltage (Vcm) to the third reference voltage (Vrefm), and accordingly, the voltage of the first terminal 111 also changes to a predetermined gain (for example, (Vcm) -Vrefm)*P(n-4)/sum(P)) descends. Here, the comparator 110 outputs the result of comparing the lowered voltage of the first terminal 111 with the first reference voltage (Vcm), which is the voltage of the second terminal 112, and is stored as D(n-5). . In one embodiment, the comparison result is low, so D(n-5) may be 0 and d(n-5) may be -1. This is the process of performing step A2 for C(n-4). Step A3 is performed to exclude C(n-4) from the set of capacitors to be recognized, and step A4 is performed to select a renewed set of capacitors to be recognized. Feedback to step A2.

Next, since D(n-5) is 1 (Low), the n-5th switch is controlled so that the second reference voltage (Vrefp) is applied to the lower plate of C(n-5), and as a result, Vbot(n-5 ) is changed from the first reference voltage (Vcm) to the second reference voltage (Vrefp), and as a result, the voltage of the first terminal 111 also changes to a predetermined gain (e.g., (Vrefp-Vcm)*P(n-5)/ It rises by sum(P)). Here, the comparator 110 outputs the result of comparing the raised voltage of the first terminal 111 with the first reference voltage (Vcm), which is the voltage of the second terminal 112, and is stored as D(n-6). . In one embodiment, the comparison result is high, so D(n-6) may be 1, and d(n-6) may be 1. This is the process of performing step A2 for C(n-5). Step A3 is performed to exclude C(n-5) from the set of capacitors to be recognized, and step A4 is performed to select a renewed set of capacitors to be recognized. Feedback to step A2.

If you repeat the process of sequentially performing steps A2, A3, and A4 as above and proceed with step A2 for C1, D(0) can be obtained. D(0), D(1), … derived in this way. D(n-3) and the already known P(0), P(1), … Pr(n-2) can be derived by applying Equation 1 using P(n-3).

Meanwhile, C(0) is the default capacitor, so D(0) can be obtained without changing the reference voltage for C(0). In addition, the DC voltage can be maintained connected to the bottom of the default capacitor, and by providing this default capacitor, the conversion gain of the ADC can be set to 1. However, if the conversion gain of the ADC is less than 1, the default capacitor can be omitted. However, if the design weight of the capacitor to be measured is sufficiently small, the actual weight may need to be derived by changing Vbot(0), Vbot(-1), and Vbot(-2) using the default capacitor or even an auxiliary capacitor. .

As above, the actual measurement process for capacitors with large design weights is carried out using capacitors with small design weights, so the actual measurement process for capacitors with small design weights is started first, and the actual measurement weights are applied to the capacitors for which actual measurements have been completed and the actual measurements for other capacitors are performed. It is desirable to allow the process to proceed. In other words, if m is 4, use Pd(0), Pd(1), Pd(2), Pd(3), Pr(4), Pr(5), Pr(6), and Pr(7) to obtain Pr It is desirable to derive (8), and it is desirable to derive Pr(4) and then obtain the actual weights in the order of Pr(5), Pr(6), and Pr(7).

Referring to FIG. 5, looking at the principle of converting the input voltage (Vin) and outputting ADC_out, first, the input voltage (Vin) is applied to the first terminal 111 and the comparator 110 is stabilized, and then the comparison result is It is output, and the output comparison result is stored as D(n-1).

In one embodiment, the comparison result is high, so D(n-1) is 1, and d(n-1) may also be 1. At this time, since D(n-1) is 1 (High), the n-1th switch is controlled so that the third reference voltage (Vrefm) is applied to the lower plate of C(n-1), and as a result, Vbot(n-1) The first reference voltage (Vcm) is changed to the third reference voltage (Vrefm), and accordingly, the voltage of the first terminal 111 also changes to a predetermined gain (e.g., (Vcm-Vrefm)*P(n-1)/ Descend by sum(P)). Here, the comparator 110 outputs the result of comparing the lowered voltage of the first terminal 111 with the first reference voltage (Vcm), which is the voltage of the second terminal 112, and is stored as D(n-2). . In one embodiment, the comparison result is low, so D(n-2) may be 0 and d(n-2) may be -1.

Next, since D(n-2) is 0 (Low), the n-2th switch is controlled so that the second reference voltage (Vrefp) is applied to the lower plate of C(n-2), and as a result, Vbot(n-2 ) is changed from the first reference voltage (Vcm) to the second reference voltage (Vrefp), and accordingly, the voltage of the first terminal 111 also changes to a predetermined gain (e.g., (Vrefp-Vcm)*P(n-2) It rises by /sum(P)). Here, the comparator 110 outputs the result of comparing the raised voltage of the first terminal 111 with the first reference voltage (Vcm), which is the voltage of the second terminal 112, and is stored as D(n-3). . In one embodiment, the comparison result is high, so D(n-3) may be 1, and d(n-3) may be 1.

By repeating the above process, D(0) can be obtained. D(0), D(1), … derived in this way. D(n-1) and the already known P(0), P(1), … ADC_out can be derived by applying Equation 2 using P(n-1). In Equation 2, for PP(k), the actual weight may be applied to the capacitor for which the actual weight has already been derived, and the design weight may be applied to the capacitor for which the actual weight has not been derived. That is, Pr(k) is first applied to PP(k), and if Pr(k) is not present, Pd(k) can be applied.

Additionally, PP(k) can be defined as Pr(k) when k is greater than m and as Pd(k) when k is less than m.

Although not shown, the present invention can be applied in the same way to not only single mode ADC but also differential mode ADC. For example, in the case of differential mode, a capacitor array of the same configuration may also be connected to the second terminal 112 of the comparator 110.

According to an embodiment of the present invention configured as described above, large weights on the upper bit side can be corrected using already prepared capacitors without a separate external circuit for error correction, and considering a mismatch of several percent, A high-resolution ADC circuit can effectively eliminate the effects of cap mismatch and parasitic cap (especially in the case of split dac) by accurately extracting the upper weights using its own components.

100: SAR-ADC with capacitor compensation function, 110: comparator, 111: first terminal, 112: second terminal, 113: third terminal, 120: capacitor array, 121: input terminal, C(0): default Capacitor, C(1) ~ C(n-1): 1st to n-1th capacitor, C(-1), C(-2): Auxiliary capacitor, SWc: Main switch, SW(0): Default switch , SW(1) ~ SW(n-1): 1st to n-1th switch, SW(-1), SW(-2): auxiliary switch, CSW1: 1st compensation mode auxiliary switch, CSW2: 2nd Compensation mode auxiliary switch, Vin: input voltage, Vcm: first reference voltage, Vrefp: second reference voltage, Vrefm: third reference voltage, 130: switch controller, 140: operator, 141: output terminal, 150: control unit

A SAR-ADC equipped with a capacitor correction function according to an embodiment of the present invention can be used to implement an analog-to-digital converter, and the analog-to-digital converter can be used in all electronic devices such as various transmission and reception devices and display devices. there is. In addition, an embodiment of the present invention can solve problems caused by process errors occurring during the chip manufacturing process and is advantageous in reducing power consumption and increasing high resolution of the data transmission and reception interface. Accordingly, it can be used in the next-generation automobile industry, such as high-speed transmission and reception of large-capacity data between sensors and processors for autonomous vehicles, and in the wired communication industry for ultra-high-speed and large-capacity video data.

Claims

In a SAR-ADC that outputs an input voltage, which is an analog signal, with n-bit resolution,

main switch;

1st to n-1th capacitors whose upper plates are connected to the other end of the main switch;

first to n-1th switches, one end of which is connected to a lower plate of each of the first to n-1th capacitors;

A comparator including a first terminal to which the other end of the main switch is connected, a second terminal to which the first reference voltage is applied, and a third terminal that outputs a result of comparing the voltages of the first terminal and the second terminal;

a switch controller that controls the main switch and the first to n-1th switches;

an operator that performs calculations using the output of the third terminal; and

A control unit that applies a control command to the switch controller using the operation result of the operator,

At least one of the first to n-1th switches is applied to the lower plate of the first to n-1th capacitor according to a command of the switch controller, and applies the first reference voltage and a second reference voltage greater than the first reference voltage. and SAR-ADC with a capacitor compensation function, characterized in that one of the third reference voltages smaller than the first reference voltage is selectively applied or opened.
According to paragraph 1,

The design weights of the first to n-1th capacitors are defined as Pd(1) to Pd(n-1), respectively,

The actual weights of the first to n-1th capacitors are defined as Pr(1) to Pr(n-1), respectively,

The control unit generates a control command so that the switch controller operates in one mode selected from normal mode and compensation mode,

In the normal mode, the output of the third terminal is defined as D(k),

In the normal mode, the output terminal of the calculator is defined as ADC_out,

In the correction mode, at least one of Pr(1) to Pr(n-1) is determined,

A SAR-ADC with a capacitor correction function, wherein while the normal mode is in progress, the calculator calculates the ADC_out by applying the actual weight obtained in the correction mode.
According to paragraph 2,

Pr(x), one of Pr(1) to Pr(n-1), is derived by calculating the equation below,

The d(k) is a value defined as 1 when the comparator output in the correction mode is high, and is defined as -1 when the comparator output is low. SAR-ADC.
According to clause 3,

A SAR-ADC with a capacitor correction function, wherein the actual weight is applied to the P(k) for capacitors for which the actual weight has already been derived, and the design weight is applied to the capacitor for which the actual weight has not been derived.
According to clause 3,

The ADC_out is derived by calculating the equation below,

A SAR-ADC with a capacitor compensation function, characterized in that Pr(k) is first applied to the PP(k), and when there is no Pr(k), Pd(k) is applied.
According to clause 5,

where m is an integer greater than 1 and less than n-1,

The PP(k) is defined as Pr(k) when k is greater than m, and is defined as Pd(k) when k is less than m.
In the method of digital conversion of an analog signal using a SAR-ADC equipped with a capacitor correction function according to any one of claims 2 to 6,

In the correction mode, the process of calculating the actual weight Pr(x) of the capacitor to be measured is performed,

Step A0 in which the first reference voltage is applied to the other terminal and the first terminal of the first to n-1th switches;

Step A1 of applying the second reference voltage to the lower plate of the capacitor to be measured and storing the output of the comparator after the voltage of the first terminal is stabilized;

A2 step of changing the reference voltage applied to the lower plate of the capacitor with the largest design weight in the set of capacitors to be applied and storing the comparator output after the comparator is stabilized;

Step A3 of excluding the capacitor for which step A2 has been performed from the set of capacitors subject to application; and

Step A4 of feeding back the set of applied capacitors on which step A3 was performed to step A2,

The reference voltage change in step A2 is,

If the comparator output is high, it is changed to the third reference voltage, and if the comparator output is low, it is changed to the second reference voltage, and so on.

The set of capacitors to be applied in step A2 is composed of capacitors whose design weight or actual weight is smaller than the capacitor to be measured,

A digital conversion method of an analog signal, characterized in that steps A2 to A4 are sequentially performed on capacitors included in the set of capacitors to be applied to derive the actual weight of the capacitor to be measured.
In clause 7,

The actual weight Pr(x) of the capacitor to be measured is derived by calculating the equation below,

where x is an integer greater than or equal to 1 and less than or equal to n-1,

The d(k) is characterized in that the operator receives one of the comparator output stored in step A1 and the comparator output stored while repeatedly performing step A2, and converts high to 1 and low to -1. A method of digital conversion of analog signals.
According to clause 8,

The P(k) is a digital conversion method of an analog signal, characterized in that the actual weight is applied to the capacitor for which the actual weight has already been derived, and the design weight is applied to the capacitor for which the actual weight has not been derived.
In clause 7,

The actual weight Pr(x) of the capacitor to be measured is derived by calculating the equation below,

where x is an integer greater than m and less than or equal to n-1, and m is an integer greater than 1 and less than n-1,

The d(k) is characterized in that the operator receives one of the comparator output stored in step A1 and the comparator output stored while repeatedly performing step A2, and converts high to 1 and low to -1. A method of digital conversion of analog signals.
According to clause 10,

The ADC_out is derived by calculating the equation below,

The PP(k) is defined as Pr(k) when the k is greater than the m, and is defined as Pd(k) when the k is less than the m.
In the SAR-ADC, which includes a SAR-ADC and is equipped with a capacitor compensation function that converts the input voltage, which is an analog signal, into a digital value and outputs it,

The SAR-ADC includes a capacitor array,

The capacitor to be measured is a capacitor to be measured among the capacitors constituting the capacitor array,

A voltage corresponding to the difference between the known reference voltages is applied to the other end of the capacitor to be measured, and the voltage applied as the weight of the capacitor to be measured is measured using the basic operation of the SAR-ADC, so that the weight of the capacitor to be corrected is determined. A SAR-ADC equipped with a capacitor correction function, which calculates the output value of the SAR-ADC using the actually measured values and corrects the error of the capacitor.
In a method of digital conversion of an analog signal using a SAR-ADC including a capacitor array,

The capacitor to be measured is a capacitor to be measured among the capacitors constituting the capacitor array,

A voltage corresponding to the difference between the known reference voltages is applied to the other end of the capacitor to be measured, and the voltage applied as the weight of the capacitor to be measured is measured using the basic operation of the SAR-ADC, so that the weight of the capacitor to be corrected is determined. A digital conversion method of an analog signal, characterized in that the output value of the SAR-ADC is calculated using the actually measured values and the error of the capacitor is corrected.