WO2024016725A1 - Analog front-end chip, analog front-end circuit, and signal processing device - Google Patents

Abstract

Embodiments of the present application provide an analog front-end chip, an analog front-end circuit, and a signal processing device. The analog front-end chip comprises: a first operational amplifier module, configured to perform amplitude adjustment on an electric signal on a path connected to a first input impedance network; and a second operational amplifier module, configured to perform amplitude adjustment on an electric signal on a path connected to a second input impedance network, wherein the impedance of the second input impedance network is different from that of the first input impedance network, and the first operational amplifier module and the second operational amplifier module are integrated in a same chip.

Description

Analog front-end chips, analog front-end circuits and signal processing devices

Related applications

This application claims priority to the Chinese patent application filed on July 20, 2022, with application number 202210853150.1 and titled "Analog Front-end Chip, Analog Front-end Circuit and Signal Processing Device", the full text of which is hereby incorporated by reference.

Technical field

The present invention relates to the technical field of testing and measurement, and in particular to an analog front-end chip, an analog front-end circuit and a signal processing device.

Background technique

Currently, various signal processing devices, such as oscilloscopes and data acquisition cards, can process and analyze the signals they receive. Usually the signal processing device includes an analog front-end circuit. The main function of the analog front-end circuit is to adjust the amplitude of the input analog signal, that is, to adjust the signal within a large dynamic input range to a fixed output range signal for the next stage. Circuitry used, for example, by an analog-to-digital converter (ADC) located at the back end. Analog front-end circuits generally need to have technical indicators such as high stability, large bandwidth, and in-band flatness. In addition, they also need to have the following two obvious characteristics: 1) The gain is variable in a wide range and stable within the full gain range; 2) The input impedance is variable, supporting high input impedance and low input impedance. If you consider the simplicity and convenience of system implementation, it is best to reduce the use of peripheral devices as much as possible when building the system for analog front-end circuits.

However, there are many devices in the analog front-end circuit, and signals are propagated step by step in the circuit in the form of voltage, which places high requirements on the signal propagation path and the performance of each device. The signal transmission line is long, the parasitic resistance and parasitic capacitance are very sensitive, and process deviations and other reasons will affect the bandwidth of the signal transmission path; the temperature characteristics of each chip are inconsistent, which will lead to poor overall temperature drift characteristics of the system.

Contents of the invention

In view of this, embodiments of the present application provide an analog front-end chip, an analog front-end circuit, and a signal processing device to solve at least one problem existing in the background technology.

In the first aspect, an embodiment of the present application provides an analog front-end chip, including:

The first operational amplifier module is configured to adjust the amplitude of the electrical signal on the path connected to the first input impedance network;

The second operational amplifier module is configured to adjust the amplitude of the electrical signal on the path connected to the second input impedance network; the impedance of the second input impedance network is different from that of the first input impedance network;

Wherein, the first operational amplifier module and the second operational amplifier module are integrated into the same chip.

In conjunction with the first aspect of the present application, in an optional implementation, a multiplexer is further included, wherein,

The multiplexer includes a first input terminal, a second input terminal and an output terminal. The first input terminal is connected to the output terminal of the first operational amplifier module, and the second input terminal is connected to the first operational amplifier module. The output terminals of the two operational amplifier modules are connected;

The multiplexer is configured to select between outputting an electrical signal received through the first input terminal and an electrical signal received through the second input terminal, and pass the selected electrical signal through the output terminal output;

The multiplexer, the first operational amplifier module and the second operational amplifier module are integrated into the same chip.

In conjunction with the first aspect of the present application, in an optional implementation, a third operational amplifier module is further included, wherein,

The input end of the third operational amplifier module is connected to the output end of the multiplexer, and the third operational amplifier module is configured to amplitude the electrical signal received from the output end of the multiplexer. value adjustment;

The third operational amplifier module, the first operational amplifier module and the second operational amplifier module are integrated into the same chip.

In conjunction with the first aspect of the present application, in an optional implementation, the first operational amplifier module includes an input buffer, a first amplifier and a second amplifier; wherein,

The input end of the input buffer is configured to receive a path connected to the first input impedance network. electrical signal;

The first amplifier and the second amplifier are connected in parallel between the output terminal of the input buffer and the output terminal of the first operational amplifier module.

In conjunction with the first aspect of the present application, in an optional implementation, the second operational amplifier module includes a variable gain amplifier; wherein,

The variable gain amplifier is connected between the output end of the second input impedance network and the output end of the second operational amplifier module.

In conjunction with the first aspect of the present application, in an optional implementation, it further includes a first input impedance network part and/or a third input impedance network part integrated in the same chip as the first operational amplifier module and the second operational amplifier module. Two input impedance network parts, where,

The first input impedance network portion is a part of the first input impedance network, and the second input impedance network portion is a part of the second input impedance network;

The input terminal of the first operational amplifier module is connected to the output terminal of the first input impedance network part, and the input terminal of the second operational amplifier module is connected to the output terminal of the second input impedance network part.

In conjunction with the first aspect of the present application, the impedance of the first input impedance network is lower than the impedance of the second input impedance network; the first input impedance network is provided outside the analog front-end chip;

The analog front-end chip also includes a second input impedance network part integrated in the same chip as the second operational amplifier module; the second input impedance network part is a part of the second input impedance network; the second input impedance network part is The input terminals of the two operational amplifier modules are connected to the output terminals of the second input impedance network part.

In a second aspect, embodiments of the present application provide an analog front-end circuit, including: the analog front-end chip described in any one of the above-mentioned first aspects.

Combined with the second aspect of the present application, in an optional implementation, a relay is also included, wherein,

The relay is located at the front end of the first input impedance network and the second input impedance network, and is configured to selectively access a path connected to the first input impedance network or connected to the third input impedance network. Two input impedance network paths.

In a third aspect, embodiments of the present application provide a signal processing device, including: an analog front-end circuit as described in any one of the above second aspects.

The analog front-end chip, analog front-end circuit and signal processing device provided by the embodiment of the present application include: a first operational amplifier module configured to adjust the amplitude of the electrical signal on the path connected to the first input impedance network; second The operational amplifier module is configured to adjust the amplitude of the electrical signal on the path connected to the second input impedance network; the impedances of the second input impedance network and the first input impedance network are different; wherein, the first operational amplifier module and the second input impedance network have different impedances. The operational amplifier module is integrated into the same chip; thus, the problem of sensitivity to parasitic capacitance and parasitic resistance caused by the external wiring of the chip is solved; the first operational amplifier module and the second operational amplifier module are formed under the same process conditions, avoiding process deviations, etc. The reason affects the bandwidth of the signal transmission path, making it easy to achieve high-bandwidth performance of the analog front-end circuit; at the same time, the key signal paths are all in one chip, the temperature characteristics are consistent, and the system temperature drift is small.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Description of drawings

The drawings described here are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the attached picture:

Figure 1 is a schematic structural diagram of an oscilloscope;

Figure 2 is a schematic structural diagram of an analog front-end chip in an embodiment of the present application;

Figure 3 is a schematic structural diagram of an analog front-end chip in another embodiment of the present application;

Figure 4 is a schematic structural diagram of an analog front-end chip in yet another embodiment of the present application;

Figure 5 is a schematic structural diagram of an analog front-end chip in yet another embodiment of the present application;

Figure 6 is a schematic structural diagram of an analog front-end circuit in a specific example of this application;

FIG. 7 is a schematic structural diagram of an analog front-end circuit in another specific example of the present application.

Detailed ways

In order to make the technical solutions and beneficial effects of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present application are clearly and completely described below by enumerating specific embodiments. Obviously, the described embodiments are only for the purpose of this application. Apply for some of the embodiments, not all of them. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the description of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

It will be understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first resistor may be referred to as a second resistor, and similarly, the second resistor may be referred to as a first resistor, without departing from the scope of the present application. The first resistor and the second resistor are both resistors, but they are not the same resistor. When a "first" is described, it does not mean that there must be a "second"; and when a "second" is discussed, it does not mean that there must be a first element, component, region, layer or section in the present application. As used herein, the singular forms "a," "an," and "the" may also be intended to include the plural forms as well, unless the context clearly dictates otherwise. "Plural" means more than two, unless otherwise clearly and specifically limited. It will also be understood that the term "comprising", when used in this specification, identifies the presence of stated features but does not exclude the presence or addition of one or more other features. When used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the present invention provide an analog front-end chip. The analog front-end chip can perform different degrees of gain adjustment on input signals. The analog front-end chip can be used in analog front-end circuits. The analog front-end circuit can be integrated into a signal processing device. . The signal processing device includes but is not limited to an oscilloscope. The oscilloscope is specifically, for example, a digital oscilloscope.

Next, taking an oscilloscope as an example, we will introduce the application of analog front-end circuits in signal processing devices. Please refer to Figure 1, which is a schematic structural diagram of an oscilloscope. Oscilloscopes generally include multiple analog front-end circuits, such as analog front-end circuit 1, analog front-end circuit 2...analog front-end circuit n in the figure; analog front-end circuit The terminal circuit is responsible for conditioning the input signal data to a suitable size and then sending it to the acquisition module. The acquisition module mainly includes an analog-to-digital conversion chip and a clock module that provides a sampling clock (not shown in the figure). The acquisition module converts the input analog signal The data is converted into digital signal data. The digital signal data is output to the data processing module for processing and then the waveform is restored and displayed on the display. The communication interface is responsible for communicating with the outside world, such as USB, network port, serial port, etc.

Next, please refer to Figure 2. An embodiment of the present application provides an analog front-end chip, including: a first operational amplifier module, used to adjust the amplitude of an electrical signal on a path connected to a first input impedance network; a second operational amplifier module, used to The amplitude of the electrical signal on the path connected to the second input impedance network is adjusted; the impedances of the second input impedance network and the first input impedance network are different; wherein, the first operational amplifier module and the second operational amplifier module are integrated in the same within the chip.

It can be understood that the specific implementation manner of the first operational amplifier module and the second operational amplifier module is related to the functions they themselves want to achieve. Those skilled in the art can set them according to the actual situation, and are not specifically limited here. The first operational amplifier module and the second operational amplifier module are integrated into the same chip. As one possibility, the chip is an analog front-end chip. As another possibility, the analog front-end chip may include an integrated first operational amplifier module and a second operational amplifier module. The chip of the amplification module also includes other components.

In order to achieve variable input impedance, analog front-end circuits usually have two input resistance modes, low-impedance input (generally 50Ω or 75Ω) and high-impedance input (generally 1MΩ). The two input resistance modes require the design of two input impedance networks with different impedances and switching through off-chip relays. In order to achieve a wide range of variable gain and system stability within the full gain range, the general solution will use two operational amplifier modules (hereinafter referred to as "AOP1 group" and "AOP2 group" respectively), and specifically use multiple AOPs chip (amplifier chip) to achieve a large variation range of gain. In other words, AOP1 group and AOP2 group are actually a general term. They may be multiple AOP chips connected in series, or multiple VGA chips (variable gain amplifiers) connected in series, or even multiple AOP chips and multiple VGA chips are connected in series and parallel. The reason why a single general-purpose op amp chip or a single VGA chip cannot be used is because it is difficult for a single chip to achieve a wide range of gain changes; in general applications, the oscilloscope analog front end can It can require a large dynamic range of continuously adjustable gain from 0.005 to 400 times. Secondly, it is difficult for a single chip to maintain stability within such a large range of gain changes. Such a design will make the system more complex. Finally, since multiple discrete chips are used and set to different gain stages to achieve gain, the temperature characteristics of each chip are inconsistent, which will lead to poor overall temperature drift characteristics of the system. In addition, the signal path constantly passes from inside the chip to outside the chip, and is easily affected by parasitic resistance and capacitance on the chip package and PCB, making it difficult to achieve high bandwidth.

In this embodiment, the first operational amplifier module and the second operational amplifier module are integrated into the same chip to form an analog front-end chip, which not only meets the gain requirements required by the analog front-end circuit, but also solves the problem of parasitics caused by the external wiring of the chip. Capacitance and parasitic resistance are sensitive issues; the first operational amplifier module and the second operational amplifier module are formed under the same process conditions, which avoids the impact of process deviations and other reasons on the bandwidth of the signal transmission path, making it easy to achieve high-bandwidth performance of the analog front-end circuit; At the same time, the key signal paths are all in one chip, the temperature characteristics are consistent, and the system temperature drift is small.

Here, the impedances of the second input impedance network and the first input impedance network are different. Specifically, one of the two input impedance networks may be a high input impedance network, and the other may be a low input impedance network. For a high input impedance network, a specific example is a 1MΩ input impedance network; for a low input impedance network, a specific example is a 50Ω or 75Ω input impedance network (the following will take a 50Ω input impedance network as an example).

As an optional implementation manner, the analog front-end chip may also include a multiplexer. Please refer to Figure 3. The multiplexer includes a first input terminal I31, a second input terminal I32 and an output terminal O3. The first input terminal I31 is connected to the output terminal O1 of the first operational amplifier module, and the second input terminal I32 is connected to the output terminal O1 of the first operational amplifier module. The output terminal O2 of the second operational amplifier module is connected; the multiplexer is used to select between outputting the electrical signal received through the first input terminal and the electrical signal received through the second input terminal, and passing the selected electrical signal through The output terminal O3 outputs; the multiplexer, the first operational amplifier module and the second operational amplifier module are integrated in the same chip.

It is understandable that for analog front-end circuits using discrete chips, it is difficult to make the 1MΩ input impedance network channel output and the 50Ω input impedance network channel output in parallel, and then use a multiplexer to select the output. This is because the output impedance of discrete devices is often different, and if their Connecting the output terminal to the input terminal of the multiplexer will cause the input impedance received by the multiplexer to be different, and it is difficult for the multiplexer to perfectly match the inputs of various different devices, making it difficult to ensure the requirements of the analog front-end. High-speed and high-precision performance, easy to produce signal distortion. Therefore, a relay is generally installed at the rear end of the first operational amplifier module and the second operational amplifier module, or between the first operational amplifier module and the second operational amplifier module, to achieve switching between the two paths. However, in such a setting, the relay is in the middle of the critical path for signal transmission in the entire chip. The relay needs to have the characteristics of high speed and low leakage, otherwise it will have an adverse impact on signal transmission, which undoubtedly puts higher requirements on the selection of relays. requirements, resulting in increased costs.

In this embodiment, since the first operational amplifier module and the second operational amplifier module are integrated in the same chip in parallel, a multiplexer can be further integrated in the chip. The signal enters the multiplexer, and after being selected by the multiplexer, it continues to be output to the downstream stage, so that the parasitic capacitance, parasitic inductance and parasitic resistance caused by the wiring are relatively small, making it easy to achieve high-bandwidth performance of the analog front-end.

As an optional implementation manner, the analog front-end chip may also include a third operational amplifier module. Please refer to Figure 4. The input terminal I41 of the third operational amplifier module is connected to the output terminal O3 of the multiplexer, and is used to adjust the amplitude of the electrical signal received from the output terminal O3 of the multiplexer; the third The operational amplifier module, the first operational amplifier module and the second operational amplifier module are integrated into the same chip. The third operational amplifier module may be referred to as "AOP3 group" in the following.

In this way, the input signal passes through the AOP1 group or AOP2 group to achieve the first level of amplitude conditioning; after that, the two input signals enter the multiplexer, and after selection by the multiplexer, enter the AOP3 group for the second level of amplitude conditioning. Conditioning. Through at least two levels of amplitude adjustment, the problems of continuously adjustable gain over a wide range, system stability within the full gain range, and poor system temperature characteristics are better solved. Moreover, by setting up at least two levels of operational amplifier modules (the first level is the AOP1 group and the AOP2 group connected to each input impedance network, and the second level is the AOP3 group), it is conducive to flexibly designing each gain in the chip according to the actual gain requirements. stages, so that the gain stage reuse rate is maximized; and the gain distribution of each input impedance network does not affect each other; finally, the gain of each gain stage can be flexibly implemented by AOP and VGA, and the gain combination is not affected by the stability of the isolated chip, achieving While the gain is variable in a wide range, it can also ensure stable performance at each level. Certainly. The solution provided by this embodiment can theoretically achieve the maximum gain adjustable range using a single signal path.

It should be understood that the solution of the present application is not limited to this, and of course, multi-stage variable gain operational amplifiers can also be integrated on the same chip. And, after the last stage of amplitude adjustment, the signal is output from the analog front-end chip.

By integrating each gain stage into the same chip, the connection between each gain stage is short, and at the same time integrating a multiplexer on the chip, the parasitic capacitance, parasitic inductance and parasitic resistance caused by the connection are relatively small and easy to Achieve high-bandwidth performance of the analog front-end and better frequency response.

The specific implementation forms of the first operational amplifier module, the second operational amplifier module and the third operational amplifier module are related to their own functions, and those skilled in the art can flexibly set them according to actual conditions. As shown in Figure 6, the first operational amplifier module, the second operational amplifier module and the third operational amplifier module can be multiple AOP chips connected in series, or multiple VGA chips connected in series (VGA1, VGA2...VGAn in the figure) , it can also be at least one AOP and at least one VGA chip connected in series and parallel. Of course, at least one of the first operational amplifier module, the second operational amplifier module and the third operational amplifier module may also include an AOP chip or a VGA chip. Therefore, it can be a single stage or a multi-stage gain combination. The specific structures of the first operational amplifier module, the second operational amplifier module and the third operational amplifier module may be the same or different.

The structures of the first operational amplifier module, the second operational amplifier module and the third operational amplifier module are illustratively described below for typical examples.

Please refer to Figure 7. As shown in the figure, the first operational amplifier module includes an input buffer, a first amplifier and a second amplifier.

Among them, please refer to AOP1_1 in the figure for the input buffer, and AOP1_1 as an input buffer mainly cooperates with the first off-chip input impedance network. Specifically, the input end of the input buffer is used to receive the electrical signal on the path connected to the first input impedance network.

For the first amplifier, please refer to AOP1_2 in the figure, and for the second amplifier, please refer to AOP1_3 in the figure; it can be seen that AOP1_2 and AOP1_3 are connected in parallel between the output end of the input buffer and the output end of the first operational amplifier module. Specifically, the input terminal of AOP1_2 and the input terminal of AOP1_3 are connected at Together, they are jointly connected to the output terminal of the input buffer; the output terminals of AOP1_2 and the output terminals of AOP1_3 are connected together, and jointly connected to the input terminal of the multiplexer (MUX).

Further, the first amplifier and the second amplifier respectively achieve two different gains. Both the first amplifier and the second amplifier are selected through the enable signal, and only one amplifier works at a time to achieve variable gain.

Please continue to refer to Figure 7. The second operational amplifier module may include a variable gain amplifier. For variable gain amplifier, please refer to VGA2_1 in the figure. Wherein, the variable gain amplifier is connected between the output end of the second input impedance network and the output end of the second operational amplifier module, specifically connected between the second input impedance network and the multiplexer. When the second operational amplifier module only includes a variable gain amplifier, the output of the variable gain amplifier serves as the output of the second operational amplifier module.

Optionally, the second operational amplifier module may only include a variable gain amplifier, and the variable gain amplifier itself may provide a gain variable function, so that the second operational amplifier module can achieve local gain adjustment.

As shown in Figure 7, the analog front-end chip can also include an impedance calibration network integrated inside the chip. For details, please refer to the 1MΩ impedance calibration network in the figure. The second operational amplifier module can be connected to the impedance calibration network. One input end of the variable gain amplifier is connected to the impedance calibration network, and the other input end is used to connect to the first input impedance network; the impedance calibration network is used to calibrate the second input impedance network. The impedance calibration network will be further explained below when describing the second input impedance network.

Please continue to refer to Figure 7. The third operational amplifier module may include a third amplifier and an output buffer. Among them, please refer to VGA3_1 in the figure for the third amplifier. Specifically, a variable gain amplifier can be selected; through the third amplifier, the second stage gain can be variable. For the output buffer, please refer to AOP3_2 in the figure, and AOP3_2 is used as an output buffer to improve the front-end drive capability.

For example, the gains of VGA2_1 and VGA3_1 are adjustable in 3 levels, and AOP1_2, AOP1_3 and AOP3_1 can each achieve one gain; then, the analog front-end chip can achieve 6 gain combinations of the first input impedance network path, and Nine gain combinations for two-input impedance network paths. increase Rich combination of benefits to meet the needs of analog front-end circuits.

Next, please refer to Figure 5. As an optional implementation, the analog front-end chip may also include a first input impedance network part and/or a second input impedance network part integrated in the same chip as the first operational amplifier module and the second operational amplifier module, wherein , the first input impedance network part is part of the first input impedance network, and the second input impedance network part is part of the second input impedance network; the input end of the first operational amplifier module is connected to the output end of the first input impedance network part , the input terminal of the second operational amplifier module is connected to the output terminal of the second input impedance network part.

It is easy to understand that in this embodiment, part of the first input impedance network is integrated inside the chip and part is set outside the chip, while the second input impedance network is set outside the chip; or, part of the second input impedance network is integrated inside the chip. The first input impedance network and the second input impedance network are both partially integrated inside the chip and partially arranged outside the chip. In this way, optimal performance can be achieved more flexibly. In practical applications, the input impedance network part integrated inside the chip can mainly integrate various programmable resistors and capacitor arrays, thereby calibrating the impedance of the entire network; the input impedance calibration is achieved by configuring the register, with higher accuracy.

Optionally, in each input impedance network, the device value of the part of the device set outside the chip is greater than the device value of the part of the device set inside the chip; specifically, for example, the device with a larger device value is designed outside the chip, and Devices with relatively small device values are designed inside the chip. Here, devices with large device values include, for example, large capacitors, large resistors, large inductors, etc.; specifically, for example, resistors with a resistance value of MΩ level and above, capacitors with a resistance value of hundreds of pF and above, and inductors with a resistance value of tens of nH and above. This compares to the devices described here with smaller device values.

Optionally, in each input impedance network, the absolute temperature drift of the parts of the device arranged outside the chip is smaller than the absolute temperature drift of the parts of the device arranged inside the chip; specifically, for example, the device with a smaller absolute temperature drift is designed on the chip. Externally, the device with relatively large absolute temperature drift is designed inside the chip. Devices located outside the chip have higher requirements for device value accuracy than devices located inside the chip. In this way, the device installed outside the chip has small absolute temperature drift and accurate absolute value of the device. Features include diverse packages and a wide range of device values to choose from.

Optionally, in each input impedance network, some devices arranged inside the chip are devices that need to form feedback with the operational amplifier to function. Specific examples include devices closely related to high-frequency performance. In this way, the connection between the device and the operational amplifier has small parasitics and good high-frequency performance.

Optionally, in each input impedance network, some of the devices arranged inside the chip are devices whose own temperature drift needs to be consistent with the temperature drift of the op amp. In this way, the temperature drift of the device is consistent with the temperature drift of the chip, and the temperature characteristics are good.

Optionally, in each input impedance network, some devices arranged inside the chip are adjustable devices. In this way, the device can be implemented through programmable technology and is easy to adjust.

As a specific implementation manner, the impedance of the first input impedance network is lower than the impedance of the second input impedance network; the first input impedance network is arranged outside the analog front-end chip; the analog front-end chip also includes a second operational amplifier module integrated with The second input impedance network part is in the same chip; the second input impedance network part is a part of the second input impedance network; the input end of the second operational amplifier module is connected to the output end of the second input impedance network part. In other words, the low input impedance network is disposed outside the analog front-end chip, while the high input impedance network is partly disposed outside the analog front-end chip and partly disposed inside the analog front-end chip.

Taking the low-impedance input as 50Ω and the high-impedance input as 1MΩ as an example, the 50Ω resistor is placed outside the chip mainly because the 50Ω resistor can be selected accurately and with small errors; while the 1MΩ resistor is divided into two parts, one of which is set at Outside the film, part of it is set inside the film. This is mainly due to the fact that the accuracy of a resistor is calculated in percentage. For the same accuracy, the error of a 1MΩ resistor will be much higher than that of a 50Ω resistor. Therefore, assume that the 1MΩ resistor is divided into two parts, 500KΩ is set outside the chip, and 500KΩ is set inside the chip; and the 500KΩ inside the chip is programmable, and its true range is adjustable from 500KΩ to 600KΩ. Then, it can be guaranteed that in multiple PCB application solutions, or in multi-batch PCB application solutions, the final overall input impedance is very close to 1MΩ, and the accuracy is fully guaranteed. In addition, since the 1MΩ signal transmission network requires matching and calibration, as shown in Figure 7, the 1MΩ input impedance calibration network can be built on-chip.

Based on the same inventive concept, an embodiment of the present application also provides an analog front-end circuit, including: Such as the analog front-end chip in the previous embodiment. Therefore, the analog front-end circuit provided by this embodiment includes the technical features of the analog front-end chip provided by the previous embodiment, and can achieve the technical effects of the analog front-end chip provided by the previous embodiment. For similarities, refer to the above simulation provided by the previous embodiment. The description of the front-end chip will not be repeated here.

Next, please refer to Figure 6. As an optional implementation, the analog front-end circuit may also include a relay, wherein the relay is located at the front end of the first input impedance network and the second input impedance network and is used to selectively access the path connected to the first input impedance network. Or a path connected to a second input impedance network.

It is understandable that for the implementation of discrete devices, if the relay is set between the AOP1 group chip and the AOP2 group chip, the relay will be in the middle of the critical path of the entire chip signal transmission. The relay needs to have the characteristics of high speed, low leakage, etc. Choose a more expensive relay. In this embodiment, the relay responsible for impedance selection is set at the voltage signal input end. The leakage characteristics and parasitic parameters of the relay have little impact on the entire input impedance and the simulation performance of the entire signal path; when necessary, it can also be configured in AOP1 The corresponding compensation network is set up in the group and AOP2 group to further offset the non-ideal factors introduced by the relay. Therefore, the technical solution of this embodiment has lower requirements for off-chip relays, the design is simpler, and the cost is reduced.

Based on the same inventive concept, an embodiment of the present application also provides a signal processing device, including: an analog front-end circuit as in the previous embodiment. Therefore, the signal processing device provided by this embodiment includes the technical features of the analog front-end circuit and the analog front-end chip provided by the previous embodiment, and can achieve the technical effects of the analog front-end chip provided by the previous embodiment. For similarities, refer to the above-mentioned implementation. The description of the analog front-end chip provided in the example will not be repeated here.

The technical features of the above embodiments can be combined in any way. To simplify the description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, All should be considered to be within the scope of this manual.

The above-mentioned embodiments only express several implementation modes of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention. It should be noted that, for general knowledge in this field For those skilled in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the scope of protection of the patent of the present invention should be determined by the appended claims.

Claims (10)

1. An analog front-end chip, including:

   The first operational amplifier module is configured to adjust the amplitude of the electrical signal on the path connected to the first input impedance network;

   The second operational amplifier module is configured to adjust the amplitude of the electrical signal on the path connected to the second input impedance network; the impedance of the second input impedance network is different from that of the first input impedance network;

   Wherein, the first operational amplifier module and the second operational amplifier module are integrated into the same chip.
2. The analog front-end chip according to claim 1, wherein the analog front-end chip further includes a multiplexer, wherein,

   The multiplexer includes a first input terminal, a second input terminal and an output terminal. The first input terminal is connected to the output terminal of the first operational amplifier module, and the second input terminal is connected to the first operational amplifier module. The output terminals of the two operational amplifier modules are connected;

   The multiplexer is configured to select between outputting an electrical signal received through the first input terminal and an electrical signal received through the second input terminal, and pass the selected electrical signal through the output terminal output;

   The multiplexer, the first operational amplifier module and the second operational amplifier module are integrated into the same chip.
3. The analog front-end chip according to claim 2, wherein the analog front-end chip further includes a third operational amplifier module, wherein,

   The input end of the third operational amplifier module is connected to the output end of the multiplexer, and the third operational amplifier module is configured to amplitude the electrical signal received from the output end of the multiplexer. value adjustment;

   The third operational amplifier module, the first operational amplifier module and the second operational amplifier module are integrated into the same chip.
4. The analog front-end chip according to claim 1, wherein the first operational amplifier The module includes an input buffer, a first amplifier and a second amplifier; wherein,

   The input end of the input buffer is configured to receive an electrical signal on a path connected to the first input impedance network;

   The first amplifier and the second amplifier are connected in parallel between the output terminal of the input buffer and the output terminal of the first operational amplifier module.
5. The analog front-end chip according to claim 1 or 4, wherein the second operational amplifier module includes a variable gain amplifier; wherein,

   The variable gain amplifier is connected between the output end of the second input impedance network and the output end of the second operational amplifier module.
6. The analog front-end chip according to claim 1, wherein the analog front-end chip further includes a first input impedance network part and/or a first input impedance network part integrated in the same chip as the first operational amplifier module and the second operational amplifier module. or the second input impedance network section, where,

   The first input impedance network portion is a part of the first input impedance network, and the second input impedance network portion is a part of the second input impedance network;

   The input terminal of the first operational amplifier module is connected to the output terminal of the first input impedance network part, and the input terminal of the second operational amplifier module is connected to the output terminal of the second input impedance network part.
7. The analog front-end chip according to claim 1, wherein the impedance of the first input impedance network is lower than the impedance of the second input impedance network; the first input impedance network is disposed outside the analog front-end chip ;

   The analog front-end chip also includes a second input impedance network part integrated in the same chip as the second operational amplifier module; the second input impedance network part is a part of the second input impedance network; the second input impedance network part is The input terminals of the two operational amplifier modules are connected to the output terminals of the second input impedance network part.
8. An analog front-end circuit, including: the analog front-end chip according to any one of claims 1-7.
9. The analog front-end circuit according to claim 8, wherein the analog front-end circuit further includes a relay, wherein,

   The relay is located at the front end of the first input impedance network and the second input impedance network, and is configured to selectively access a path connected to the first input impedance network or a path connected to the second input impedance network. path.
10. A signal processing device comprising: the analog front-end circuit as claimed in claim 8 or 9.