WO2024016414A1

WO2024016414A1 - Time sequence test method and apparatus, computer device, and storage medium

Info

Publication number: WO2024016414A1
Application number: PCT/CN2022/112676
Authority: WO
Inventors: 第五天昊
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-07-20
Filing date: 2022-08-16
Publication date: 2024-01-25
Also published as: CN115145775A

Abstract

A time sequence test method and apparatus, a computer device, a storage medium, and a computer program product. The method comprises: acquiring an initial value of read data of a target register, the target register being a register in a tested chip (S200); according to the initial value of the read data, performing data configuration of a data channel on the target register (S400); reading an actual value of the target register (S600); and, according to the actual value and the initial value of the read data, determining whether the tested chip has a time sequence offset (S800). The method can effectively test a time sequence of a chip, thereby improving the product quality.

Description

Timing test methods, devices, computer equipment, storage media

Cross-references to related applications

This disclosure claims priority to the Chinese patent application filed with the China Patent Office on July 20, 2022, with application number 2022108581337 and the invention title "Timing Test Method, Device, Computer Equipment, Storage Medium", the entire content of which is incorporated by reference. in this disclosure.

Technical field

The present disclosure relates to the technical field of timing testing, and in particular, to a timing testing method, device, computer equipment, storage medium and computer program product.

Background technique

When a memory chip reads data according to a storage instruction, it usually reads multi-bit data from multiple storage units specified in the storage instruction. One bit of data is stored in each memory unit. At this time, the memory unit is prone to timing deviation, causing data reading failure.

Based on this, effective timing testing of memory chips is required.

Contents of the invention

According to various embodiments of the present disclosure, a timing testing method, apparatus, computer equipment, computer-readable storage medium, and computer program product are provided.

According to various embodiments of the present disclosure, a timing testing method is provided, which method includes:

Obtain the initial value of the read data of the target register, which is a register in the chip under test;

According to the initial value of the read data, perform data configuration of the data channel on the target register;

Read the actual value of the target register;

According to the actual value and the initial value of the read data, it is determined whether there is a timing offset in the chip under test.

In some embodiments, before obtaining the initial value of the read data of the target register, the method further includes:

Enable the target register function.

In some embodiments, enabling the target register function includes:

Configuration mode register value;

The target register is called based on the value of the mode register.

In some embodiments, the target register is a multi-function register including multiple sub-registers, and the initial read data values include multiple sets of read initial values corresponding to each sub-register,

The data configuration of the data channel for the target register according to the initial value of the read data includes:

According to the read initial value of each group, the data configuration of the data channel is performed for each of the sub-registers.

In some embodiments, configuring data in each data channel of each of the sub-registers according to each group of read initial values includes:

Read the initial value according to each group's instructions, configure the value of the data register and the data value mode;

According to the value of the data register and the data value mode, the data configuration of the data channel is performed for each of the sub-registers.

In some embodiments, reading the actual value of the target register includes:

According to the parallel mode, the actual value of each of the sub-registers is read.

In some embodiments, reading the actual value of the target register includes:

According to the serial mode, the actual value of each said sub-register is read.

In some embodiments, determining whether there is a timing offset in the target register based on the actual value and the initial value of the read data includes:

Determine whether there is a timing offset in the chip under test based on the actual value of each sub-register and its read initial value;

When the actual value of any of the sub-registers is different from its read initial value, it is determined that the chip under test has a parallel timing offset or a serial timing offset.

In some embodiments, determining whether there is a timing offset in the target register based on the actual value and the initial value of the read data further includes:

When the actual value of each sub-register and its read initial value are the same, it is determined that there is no timing offset in the chip under test.

According to various embodiments of the present disclosure, a timing testing device is also provided, and the device includes:

The acquisition module is used to obtain the initial value of the read data of the target register, which is a register in the chip under test;

A configuration module configured to perform data configuration of the data channel on the target register according to the initial value of the read data;

A reading module, used to read the actual value of the target register;

A judgment module is used to judge whether there is a timing offset in the chip under test based on the actual value and the initial value of the read data.

In some embodiments, the device further includes:

A function enabling module is used to enable the target register function.

In some embodiments, the function enabling module includes a mode register, and the configuration module is also used to configure the value of the mode register and call the target register according to the value of the mode register.

In some embodiments,

The target register is a multi-function register including multiple sub-registers, and the initial read data value includes multiple sets of read initial values corresponding to each sub-register,

The configuration module also includes a data register. The data register is used to configure the value of the data register and the data value mode according to the read initial value of each group, and configure the value of the data register and the data value mode according to the value of the data register and the data value. mode, perform data configuration of the data channel for each of the sub-registers.

According to various embodiments of the present disclosure, a computer device is also provided, including a memory and a processor. The memory stores a computer program. When the processor executes the computer program, it implements any of the above methods. step.

According to various embodiments of the present disclosure, there is also provided a computer-readable storage medium on which a computer program is stored, which implements the steps of any of the above methods when executed by a processor.

According to various embodiments of the present disclosure, a computer program product is also provided, including a computer program that implements the steps of any of the above methods when executed by a processor.

Embodiments of the present disclosure may/at least have the following advantages:

The timing test method, device, computer equipment, storage medium and computer program product in the embodiment of the present disclosure can configure the data channel of the target register and read it, so that according to the data reading situation of the target register, Effectively reflects whether there is timing offset in the chip under test, thereby improving product quality.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will become apparent from the description, drawings, and claims.

Description of drawings

In order to more clearly explain the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings needed to be used in the description of the embodiments or the traditional technology will be briefly introduced below. Obviously, the drawings in the following description are only for the purpose of explaining the embodiments or the technical solutions of the traditional technology. For some disclosed embodiments, those of ordinary skill in the art can also obtain other drawings based on these drawings without exerting creative efforts.

Figure 1 is a schematic flow chart of a timing testing method in an embodiment;

Figure 2 is a schematic flow chart of a timing testing method in another embodiment;

Figure 3 is a schematic flow chart of a timing testing method in yet another embodiment;

Figure 4 is a schematic diagram of the data configuration of the data channel in the sub-register MPR0 according to the read initial value of MPR0 in one embodiment;

Figure 5 is a schematic diagram of data configuration of the data channel in the sub-register MPR0 according to the read initial value of MPR0 in another embodiment;

Figure 6 is a structural block diagram of a timing test device in an embodiment;

Figure 7 is a structural block diagram of a timing test device in another embodiment;

Figure 8 is an internal structure diagram of a computer device in one embodiment.

To better describe and illustrate embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the figures should not be construed as limiting the scope of any of the disclosed inventions, the embodiments and/or examples presently described, and the best modes currently understood of these inventions.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present disclosure more clear, the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present disclosure and are not intended to limit the present disclosure.

As mentioned in the background art, when a memory chip reads data according to a storage instruction, its memory unit is prone to timing deviation, resulting in data reading failure.

Specifically, for example, when a DIMM (dual in-line memory module) reads 8-bit byte data in 8 storage units specified in the storage instruction according to the STRB instruction (byte data storage instruction), because each storage unit The data channel (DQ) is usually arranged in series, and the data of each storage unit needs to be read out in sequence. Therefore, timing offset is easily generated when reading data, leading to data read errors.

Based on this, embodiments of the present disclosure propose a timing testing method, device, computer equipment, storage medium and computer program product, which can effectively test chip timing, thereby improving product quality. The embodiments of the present disclosure can, but are not limited to, test the STRB timing of the DIMM.

In the following, this method is used to test the STRB timing of a DIMM as an example.

In one embodiment, please refer to Figure 1. A timing method is provided. The method is applied to the terminal in Figure 1 as an example to illustrate, including the following steps:

Step S200, obtain the initial value of the read data of the target register, which is a register in the chip under test;

Step S400, configure the data channel of the target register according to the initial value of the read data;

Step S600, read the actual value of the target register;

Step S800: Determine whether there is a timing offset in the chip under test based on the actual value and the initial value of the read data.

Among them, in step S200, the target register is a register in the chip under test. The initial value of the read data of the target register can be its default initial value, or it can be a value that is reset as needed. There is no restriction on this.

The chip under test can include multiple banks and peripheral logic circuits. Each bank can contain multiple data channels. Each data channel can include multiple sets of memory cells. And each data channel can include multiple bit lines. And each group of memory cells can correspond to multiple word lines. Each word line runs through each data channel.

The following takes the chip under test (DRAM chip) as having a burst length of 8 and having 8 DQ terminals as an example to specifically describe the testing process of the present disclosure.

In step S400, after data configuration, the target register can correspond to multiple data channels, so that it can be read and written in parallel mode. The destination register can also correspond to a data channel and thus be read and written in serial mode.

At the same time, the target register can be a multi-function register including multiple sub-registers, or it can only include one register.

After configuring the data channel of the target register, relevant data can be stored in the storage units in each data channel of the target register according to the configured data.

It should be noted that "deposit" here does not necessarily mean writing through the test device. Specifically, it can be written through the register in the DRAM chip (chip under test).

In step S600, after storing relevant data in the storage units in each data channel of the target register, the target memory can be read.

In step S800, when the actual value is different from the initial value of the read data, it can be determined that there is a timing offset in the chip under test. When the actual value is the same as the initial value of the read data, it can be determined that there is no timing offset in the chip under test.

When there is a timing offset in the chip under test, the chip under test can be adjusted so that the memory cells in each data channel of the chip under test can be effectively read and written after adjustment.

In this embodiment, the target register can be configured with data channel data and read, so that whether there is a timing offset in the chip under test can be effectively reflected based on the data reading of the target register, thereby improving product quality.

In one embodiment, before step S200, it also includes:

Step S100, enable the target register function.

The default initial value of the target register can be saved in the test machine. After the target register function is turned on, step S200 may call the default initial value of the target register as the initial value for obtaining the read data of the target register.

At this point, the default initial value of the target register can be obtained simply and effectively.

Of course, in other embodiments, the initial value of the read data of the target register can also be set as needed, and this is not limited here.

In one embodiment, referring to Figure 2, step S100 includes:

Step S110, configure the value of the mode register;

Step S120: Call the target register according to the value of the mode register.

The mode register can be a register in the test machine.

At this time, the target register function can be easily turned on by calling the target register according to the register in the test machine.

In one embodiment, the target register is a multi-function register including multiple sub-registers, and the initial value of the read data includes multiple sets of initial read values corresponding to each sub-register.

At the same time, step S400 includes:

Step S410: Configure the data channel of each sub-register according to the initial value read by each group.

At this time, after the data configuration in step S400, each sub-register can correspond to multiple data channels (such as corresponding to 8 data channels), so that each sub-register can be read and written in parallel. Alternatively, each sub-register can also correspond to a data channel, so that each sub-register can be read and written in a serial manner. Of course, the data channel corresponding modes of each sub-register can also be different, and there is no restriction on this here.

As an example, the target register may be MRS3, which may include four sub-registers MPR0, MPR1, MPR2, and MPR3.

Among them, the initial read value of sub-register MPR0 can be: 01010101. The initial read value of sub-register MPR1 can be: 00110011. The initial read value of sub-register MPR2 can be: 00001111. The initial read value of sub-register MPR3 can be: 00000000.

At this time, you can configure the data channel data for sub-register MPR0 according to "01010101"; configure the data channel for sub-register MPR1 according to "00110011"; configure the data channel for sub-register MPR2 according to "00001111"; "00000000" configures the data channel of the sub-register MPR3.

Thereafter, in step S600, the actual value of each sub-register can be read. The actual value of each sub-register can be read according to the parallel mode, or the actual value of each sub-register can be read according to the serial mode. The specific method can be determined according to the specific way of configuring the data channel of each sub-register. Moreover, in step S800, it can be determined whether there is a timing offset in the chip under test based on the actual value of each sub-register and its read initial value.

In this embodiment, by setting the target register to be a multi-function register including multiple sub-registers, the timing of the chip under test can be repeatedly and comprehensively detected, thereby improving detection reliability. Of course, in other embodiments, the target register may also include only one register, and there is no limitation on this here.

In one embodiment, referring to Figure 3, step S410 includes:

Step S411, configure the value of the data register and the data value mode according to the initial value read by each group;

Step S412: Configure data channel data for each sub-register according to the value of the data register and the data value mode.

In step S411, the data register may be a register in the test machine (such as a topology register).

The value of the configured data register can eventually be converted into binary data. Each bit of binary data can be configured into a data channel according to the data value mode.

In step S412, the value of the data register may be converted into binary data. Then, each bit in the binary data is configured into each data channel of the corresponding sub-register according to the data value mode (specifically, configured into the storage unit in each data channel).

As an example, the target register may be MRS3, which may include four sub-registers MPR0, MPR1, MPR2, and MPR3. As an example, the initial values of the four sub-registers MPR0, MPR1, MPR2, and MPR3 can be set according to JEDEC regulations. Among them, the initial read value of sub-register MPR0 can be: 01010101.

At this time, please refer to Figure 4. You can read the initial value "01010101" according to the sub-register MPR0, the value of the configuration data register is "AAAA" in hexadecimal, and the configuration data value mode is: one bit and two The data generates eight-bit storage data in the same data channel (each bit of storage data is stored in one storage unit), and for the same binary data, each bit of the eight-bit storage data has a true value.

Then convert hexadecimal "AAAA" into binary data "1010 1010 1010 1010". When converting hexadecimal to binary, conversion is performed from right to left. The binary data corresponding to a hexadecimal A is "1010", and the binary data is also arranged from right to left.

Then, according to the data reading mode, configure the right 8 bits of the binary data "1010 1010 1010 1010" into the eight data channels DQ0 to DQ7, that is, 0, 1, 0, 1, 0, 1, 0, 1 Configure them in sequence into the data channels DQ0 to DQ7 of the chip under test.

Furthermore, in DQ0, from the first memory cell to the eighth memory cell in the first column of memory cells, data "0" that takes a true value for the first digit "0" from the right is arranged. In DQ1, from the first memory cell to the eighth memory cell in the first column of memory cells, data "1" that takes a true value for the second digit "1" from the right is arranged. By analogy, in DQ7, from the first memory cell to the eighth memory cell in the first column of memory cells, data "1" that takes the true value of the eighth bit "1" from the right is configured.

At this time, correspondingly, in step S600, the actual value of the sub-register MPR0 is read through the parallel mode. When reading, read the data in the first storage unit in DQ0 to DQ7 in order to obtain the actual value of sub-register MPR0. Then, the actual value of sub-register MPR0 can be compared with the corresponding bit data of the read initial value of sub-register MPR0 to obtain the comparison result. If there is no problem in the data reading process, the data in the first storage unit in DQ0 to DQ7 should be 0, 1, 0, 1, 0, 1, 0, 1 in sequence. At this time, read the actual value of sub-register MPR0 The value is 01010101, which is the same as the read initial value 01010101 of sub-register MPR0.

For sub-registers MPR1, MPR2, and MPR3, the data configuration process can be similar to that of sub-register MPR0.

For example, the initial read value of sub-register MPR1 can be: 00110011.

At this time, you can read the initial value "00110011" according to the sub-register MPR1, the value of the configuration data register is "CCCC" in hexadecimal, and the configuration data value mode is: data generation by one bit and two for the same data channel The eight-bit stored data (each bit of stored data is stored in one storage unit), and each bit of the eight-bit stored data takes a true value for the binary data.

Then convert the hexadecimal "CCCC" into binary data "0011 0011 0011 0011". When converting hexadecimal to binary, conversion is performed from right to left. The binary data corresponding to a hexadecimal C is "0011", and the binary data is also arranged from right to left.

Then, according to the data reading mode, configure the right 8 bits of the binary data "0011 0011 0011 0011" into the eight data channels DQ0 to DQ7, that is, 1, 1, 0, 0, 1, 1, 0, 0 Configure them in sequence into the data channels DQ0 to DQ7 of the chip under test.

In DQ0, from the first memory cell to the eighth memory cell in the first column of memory cells, data "1" that takes a true value for the first bit "1" from the right is arranged. In DQ1, from the first memory cell to the eighth memory cell in the first column of memory cells, data "1" that takes a true value for the second digit "1" from the right is arranged. By analogy, in DQ7, from the first memory cell to the eighth memory cell in the first column of memory cells, data "0" that takes the true value of the eighth bit "0" from the right is configured.

For sub-register MPR2, its initial read value can be: 00001111. At this time, you can read the initial value "00001111" according to the sub-register MPR2, the value of the configuration data register is "F0F0" in hexadecimal, and the configuration data value mode is: data is generated by one bit and two in the same data channel The eight-bit stored data (each bit of stored data is stored in one storage unit), and for the same binary data, each bit of the eight-bit stored data has a true value.

For sub-register MPR3, its initial read value can be: 00000000. At this time, you can read the initial value "00000000" according to the sub-register MPR3, the value of the configuration data register is "0000" in hexadecimal, and the configuration data value mode is: data is generated by one bit and two in the same data channel The eight-bit stored data (each bit of stored data is stored in one storage unit), and for the same binary data, each bit of the eight-bit stored data takes a true value.

At this time, correspondingly, in step S600, the actual values of the sub-registers MPR1, MPR2, and MPR3 are read through the parallel mode. When reading, read the data in the first memory unit in DQ0 to DQ7 in sequence.

It can be understood that in this embodiment, after step S412 configures the data channel of each sub-register according to the value of the data register and the data value mode, the data of each sub-register can be stored one by one in each of the chips under test. in the storage unit in the data channel. After the data of a sub-register is stored according to the configuration data, it can be read in step S600. Then, according to the configuration data, the data of another sub-register is stored, and then read in step S600. By analogy, the reading of the real value of each sub-register is completed.

As another example, the target register may be MRS3, which may include four sub-registers MPR0, MPR1, MPR2, and MPR3. Among them, the initial read value of sub-register MPR0 can be: 01010101.

At this time, please refer to Figure 5. You can read the initial value "01010101" according to the sub-register MPR0, the value of the configuration data register is "0000" in hexadecimal, and the configuration data value mode is: generated by one-bit binary data Eight-bit stored data in the same data channel (each bit of stored data is stored in one storage unit), and for the same binary data, every odd bit in the eight-bit stored data has a true value, and each of the eight-bit stored data has a true value. Even-numbered bits are inverted.

Then convert hexadecimal "0000" into binary data "0000 0000 0000 0000". When converting hexadecimal to binary, conversion is performed from right to left. The binary data corresponding to a hexadecimal 0 is "0000", and the binary data is also arranged from right to left.

Then, according to the data reading mode, configure the right 8 bits of the binary data "0000 0000 0000 0000" into the eight data channels DQ0 to DQ7, that is, 0, 0, 0, 0, 0, 0, 0, 0 Configure them in sequence into the data channels DQ0 to DQ7 of the chip under test.

Moreover, in DQ0, from the first memory cell to the eighth memory cell in the first column of memory cells, the eight-bit result data of alternately taking the true value and the inverse value of the first "0" from the right is arranged. , specifically, configure 0, 1, 0, 1, 0, 1, 0, 1 in sequence.

In DQ1, from the first storage unit to the eighth storage unit in the first column of storage units, the eight-bit result data of the second digit "0" from the right alternately taking the true value and the negative value is configured in sequence. Specifically, , configure 0, 1, 0, 1, 0, 1, 0, 1 in sequence.

By analogy, in DQ7, from the first memory unit to the eighth memory unit in the first column of memory units, the eight-bit result of alternately taking the true value and the negative value of the eighth bit "0" from the right is configured. Data, specifically, is configured with 0, 1, 0, 1, 0, 1, 0, 1 in sequence.

At this time, correspondingly, in step S600, the actual values of the sub-registers MPR0, MPR1, MPR2, and MPR3 are read through the serial mode. When reading, the data in the first to eighth memory cells in the first column of memory cells in the same data channel (such as DQ0) are read sequentially. The data channel being read is the data channel of each sub-register of the target register.

For example, when reading MPR0, read the data in the first to eighth memory cells in the first column of memory cells in the same data channel (such as DQ0) in order to obtain the actual value of sub-register MPR0. Then, the actual value of sub-register MPR0 can be compared with the corresponding bit data of the read initial value of sub-register MPR0 to obtain the comparison result. If there is no problem in the data reading process, the data in the first to eighth memory cells in the first column of memory cells in the same data channel of MPR0 (such as DQ0) should be 0, 1, 0, 1 in sequence. , 0, 1, 0, 1. At this time, the actual value read from the sub-register MPR0 is 01010101, which is the same as the initial value 01010101 read from the sub-register MPR0.

In some embodiments, after going through step S411 and step S412 once, and then reading the actual value of each sub-register in parallel mode, return to step S411 again, and reconfigure the data register according to the initial value read for each group. value and data value mode. After that, read the actual value of each sub-register in serial mode.

At this time, testing the timing in both parallel and serial situations can effectively improve the test coverage, thereby further improving product reliability.

In one embodiment, step S800 includes: determining whether there is a timing offset in the chip under test based on the actual value of each sub-register and its read initial value;

When the actual value of any sub-register is different from the initial read value, it is determined that the chip under test has a parallel timing offset or a serial timing offset.

Specifically, after step S400 configures the data channel of each sub-register according to the initial value read by each group, step S600 reads the actual value of each sub-register in parallel mode. At this time, when the actual value of any sub-register is different from the initial read value, it is determined that the chip under test has a parallel timing offset.

After step S400 configures the data channel of each sub-register based on the initial value read from each group, step S600 reads the actual value of each sub-register through the serial mode. At this time, when the actual value of any sub-register is different from the initial read value, it is determined that the chip under test has a serial timing offset.

In one embodiment, when the actual value of each sub-register and its read initial value are the same, it is determined that there is no timing offset in the chip under test.

Specifically, it may be that step S400 configures the data channel of each sub-register according to the initial value read by each group, and then step S600 reads the actual value of each sub-register in parallel mode, and the actual value of each sub-register is the same as the read value. The initial values are all the same. At this time, it is determined that there is no timing offset in the chip under test.

It can also be that after step S400 configures the data channel of each sub-register according to the initial value read by each group, step S600 reads the actual value of each sub-register through the serial mode. The actual value of each sub-register is different from the read initial value. If the values are all the same, it is determined that there is no timing offset in the chip under test.

It can also be that after step S400 configures the data channel of each sub-register according to the initial value read by each group, step S600 reads the actual value of each sub-register in parallel mode, and the actual value of each sub-register is different from the read initial value. All are the same. Then, step S400 re-configures the data channel of each sub-register according to the initial value read by each group, and then step S600 reads the actual value of each sub-register through the serial mode. The actual value of each sub-register is different from the initial read value. The values are all the same. At this time, it is determined that there is no timing offset in the chip under test.

That is, whether there is a timing offset in the chip under test, you can only judge whether there is an offset in the parallel case, or you can only judge whether there is an offset in the serial case, or you can also judge whether there is an offset in the parallel case and the serial case at the same time. When the two Only when neither of them deviates can it be judged that there is no timing skew in the chip under test. Otherwise, there may be parallel timing skew and/or serial timing skew.

It should be understood that although the steps in the flowcharts of Figures 1, 2 and 3 are shown in sequence as indicated by arrows, these steps are not necessarily executed in the order indicated by arrows. Unless explicitly stated in this article, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in Figures 1, 2 and 3 may include multiple steps or stages. These steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution order of the steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

In one embodiment, please refer to Figure 6, a timing test device is provided, including: an acquisition module 100, a configuration module 200, a reading module 300 and a judgment module 400, wherein:

The acquisition module 100 is used to acquire the initial value of the read data of the target register, which is a register in the chip under test.

The configuration module 200 is used to configure the data channel of the target register according to the initial value of the read data.

The reading module 300 is used to read the actual value of the target register.

The judgment module 400 is used to judge whether there is a timing offset in the chip under test based on the actual value and the initial value of the read data.

In one embodiment, please refer to FIG. 7 , the timing test device further includes a function enabling module 500 . The function enabling module 500 is used to enable the target register function.

In one embodiment, referring to FIG. 7 , the function enabling module 500 includes a mode register 510 . The configuration module 200 is also used to configure the value of the mode register 510 and call the target register according to the value of the mode register 510.

The configuration module 200 is used to configure the data channel of each sub-register according to the initial value read by each group.

In one embodiment, referring to FIG. 7 , the configuration module 200 includes a data register 210 . The data register 210 may be a topology register, for example.

The data register 210 is used to configure the value of the data register and the data value mode according to the initial value read by each group, and configure the data channel of each sub-register according to the value of the data register and the data value mode.

In one embodiment, the reading module 300 is used to read the actual value of each sub-register according to the parallel mode.

In one embodiment, the reading module 300 is used to read the actual value of each sub-register according to the serial mode.

In one embodiment, the determination module 400 determines whether there is a timing offset in the chip under test based on the actual value of each sub-register and its read initial value. When the actual value of any sub-register is different from its read initial value, the determination module 400 determines that there is a parallel timing offset or a serial timing offset in the chip under test.

In one embodiment, when the actual value of each sub-register and its read initial value are the same, the determination module 400 determines that there is no timing offset in the chip under test.

Regarding the specific limitations on the timing test device, please refer to the limitations on the timing test method mentioned above, which will not be described again here. Each module in the above timing test device can be implemented in whole or in part by software, hardware and combinations thereof. Each of the above modules may be embedded in or independent of the processor of the computer device in the form of hardware, or may be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. 8 . The computer device includes a processor, memory, communication interface, display screen and input device connected through a system bus. Wherein, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes non-volatile storage media and internal memory. The non-volatile storage medium stores operating systems and computer programs. This internal memory provides an environment for the execution of operating systems and computer programs in non-volatile storage media. The communication interface of the computer device is used for wired or wireless communication with external terminals. The wireless mode can be implemented through WIFI, mobile cellular network, NFC (Near Field Communication) or other technologies. The computer program implements a timing testing method when executed by a processor. The display screen of the computer device may be a liquid crystal display or an electronic ink display. The input device of the computer device may be a touch layer covered on the display screen, or may be a button, trackball or touch pad provided on the computer device shell. , it can also be an external keyboard, trackpad or mouse, etc.

Those skilled in the art can understand that the structure shown in Figure 8 is only a block diagram of a partial structure related to the disclosed solution, and does not constitute a limitation on the computer equipment to which the disclosed solution is applied. The specific computer device can May include more or fewer parts than shown, or combine certain parts, or have a different arrangement of parts.

In one embodiment, a computer device is also provided, including a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, it implements the steps in the above method embodiments.

In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above method embodiments are implemented.

In one embodiment, a computer program product is provided, including a computer program that implements the steps in each of the above method embodiments when executed by a processor.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage. In the media, when executed, the computer program may include the processes of the above method embodiments. Any reference to memory, storage, database or other media used in various embodiments provided by the present disclosure may include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in many forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM).

The technical features of the above embodiments can be combined in any way. To simplify the description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, all possible combinations should be used. It is considered to be within the scope of this manual.

The above-described embodiments only express several implementation modes of the present disclosure, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, and these all fall within the protection scope of the present disclosure. Therefore, the protection scope of the patent disclosed should be determined by the appended claims.

Claims

A timing testing method, the method includes:

Obtain the initial value of the read data of the target register, which is a register in the chip under test;

According to the initial value of the read data, perform data configuration of the data channel on the target register;

Read the actual value of the target register;

According to the actual value and the initial value of the read data, it is determined whether there is a timing offset in the chip under test.
The timing testing method according to claim 1, wherein before obtaining the initial value of the read data of the target register, it further includes:

Enable the target register function.
The timing testing method according to claim 2, wherein turning on the target register function includes:

Configuration mode register value;

The target register is called based on the value of the mode register.
The timing test method according to claim 1, wherein the target register is a multi-function register including a plurality of sub-registers, and the read data initial value includes multiple sets of read initial values corresponding to each sub-register,

The data configuration of the data channel for the target register according to the initial value of the read data includes:

According to the read initial value of each group, the data configuration of the data channel is performed for each of the sub-registers.
The timing test method according to claim 4, wherein said configuring data in each data channel of each said sub-register according to each group of said read initial values includes:

Read the initial value according to each group's instructions, configure the value of the data register and the data value mode;

According to the value of the data register and the data value mode, the data configuration of the data channel is performed for each of the sub-registers.
The timing testing method according to claim 4, wherein reading the actual value of the target register includes:

According to the parallel mode, the actual value of each of the sub-registers is read.
The timing testing method according to claim 4, wherein reading the actual value of the target register includes:

According to the serial mode, the actual value of each said sub-register is read.
The timing test method according to claim 6 or 7, wherein determining whether there is a timing offset in the target register based on the actual value and the initial value of the read data includes:

Determine whether there is a timing offset in the chip under test based on the actual value of each sub-register and its read initial value;

When the actual value of any of the sub-registers is different from its read initial value, it is determined that the chip under test has a parallel timing offset or a serial timing offset.
The timing testing method according to claim 8, wherein determining whether there is a timing offset in the target register based on the actual value and the initial value of the read data further includes:

When the actual value of each sub-register and its read initial value are the same, it is determined that there is no timing offset in the chip under test.
A timing test device, the device includes:

The acquisition module is used to obtain the initial value of the read data of the target register, which is a register in the chip under test;

A configuration module configured to perform data configuration of the data channel on the target register according to the initial value of the read data;

A reading module, used to read the actual value of the target register;

A judgment module is used to judge whether there is a timing offset in the chip under test based on the actual value and the initial value of the read data.
The timing test device according to claim 10, wherein the device further includes:

A function enabling module is used to enable the target register function.
The timing test device according to claim 11, wherein the function enabling module includes a mode register, and the configuration module is also used to configure the value of the mode register and call the target register according to the value of the mode register.
The timing test device according to claim 10, wherein,

The target register is a multi-function register including multiple sub-registers, and the initial read data value includes multiple sets of read initial values corresponding to each sub-register,

The configuration module also includes a data register. The data register is used to configure the value of the data register and the data value mode according to the read initial value of each group, and configure the value of the data register and the data value mode according to the value of the data register and the data value. mode, perform data configuration of the data channel for each of the sub-registers.
A computer device includes a memory and a processor. The memory stores a computer program. When the processor executes the computer program, it implements the steps of the timing testing method according to any one of claims 1 to 9.
A computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the timing testing method of any one of claims 1 to 9 are implemented.
A computer program product, including a computer program, which implements the steps of the timing testing method according to any one of claims 1 to 9 when executed by a processor.