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WO2024016350A1 - 像素驱动电路及其驱动方法、显示面板、显示装置 - Google Patents

像素驱动电路及其驱动方法、显示面板、显示装置 Download PDF

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Publication number
WO2024016350A1
WO2024016350A1 PCT/CN2022/107495 CN2022107495W WO2024016350A1 WO 2024016350 A1 WO2024016350 A1 WO 2024016350A1 CN 2022107495 W CN2022107495 W CN 2022107495W WO 2024016350 A1 WO2024016350 A1 WO 2024016350A1
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WO
WIPO (PCT)
Prior art keywords
signal terminal
terminal
circuit
signal
driving circuit
Prior art date
Application number
PCT/CN2022/107495
Other languages
English (en)
French (fr)
Inventor
王灿
曲燕
张粲
玄明花
陈小川
丛宁
牛晋飞
张晶晶
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280002323.7A priority Critical patent/CN117769736A/zh
Priority to PCT/CN2022/107495 priority patent/WO2024016350A1/zh
Publication of WO2024016350A1 publication Critical patent/WO2024016350A1/zh
Priority to US18/642,994 priority patent/US12283234B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel driving circuit and a driving method thereof, a display panel, and a display device.
  • the pixel driving circuit generally provides driving current to the light-emitting unit according to the voltage of the data signal, that is, the pixel driving circuit controls the gray scale of the sub-pixel unit through the voltage of the data signal.
  • the pixel driving circuit of this architecture has problems such as high power consumption and low gray-scale adjustment accuracy.
  • a pixel driving circuit is provided, wherein the pixel driving circuit is used to drive a light-emitting unit to emit light, and the pixel driving circuit includes: a driving circuit, a first lighting control circuit, a first digital circuit, and a driving circuit.
  • the circuit is connected to the first power terminal, the first node, and the light-emitting unit, and is used to use the first power terminal to provide driving current to the light-emitting unit according to the voltage of the first node;
  • the first light-emitting control circuit is connected to the first digital signal terminal, and is connected in series with the driving circuit between the first power terminal and the light-emitting unit, and is used to turn on or turn off the first power terminal in response to the first digital signal of the first digital signal terminal.
  • the first digital circuit includes a first signal conversion circuit, the first signal conversion circuit is connected to the first analog signal terminal and the first digital signal terminal, and is used according to the The first analog signal of the first analog signal terminal inputs the first digital signal to the first digital signal terminal.
  • the first digital circuit further includes: a first switch unit, the first switch unit is connected between the first signal conversion circuit and the first analog signal terminal for The first signal conversion circuit and the first analog signal terminal are connected in response to a signal at the first data writing signal terminal.
  • the first digital circuit further includes: a first detection circuit, the first detection circuit is connected to the first digital signal terminal, the first analog signal terminal, and the first data reading signal terminal. , used to respond to the signal of the first data reading signal terminal to transmit the signal of the first digital signal terminal to the first analog signal terminal.
  • the first signal conversion circuit includes: a first inverter and a second inverter.
  • the input end of the first inverter is connected to the first analog signal end, and the output end is connected to the first analog signal end.
  • Connect the first digital signal terminal; the input terminal of the second inverter is connected to the first digital signal terminal, and the output terminal is connected to the input terminal of the first inverter.
  • the driving circuit includes: a driving transistor, a first electrode of the driving transistor is connected to the first power terminal, a second electrode is connected to the second node, and a gate electrode is connected to the first node.
  • the first light-emitting control circuit includes: a first transistor, a first electrode of the first transistor is connected to the second node, a second electrode is connected to the light-emitting unit, and a gate electrode is connected to the first digital signal terminal.
  • the first switch unit includes: a second transistor, a first pole of the second transistor is connected to the first analog signal terminal, and a second pole is connected to the first signal conversion circuit, The gate is connected to the first data writing signal terminal.
  • the first signal conversion circuit includes: a first inverter, an input terminal of the first inverter is connected to the first analog signal terminal, and an output terminal is connected to the first digital signal terminal. signal terminal; the first detection circuit is also used to invert the signal transmitted from the first digital signal terminal to the first analog signal terminal.
  • the first detection circuit includes: a third inverter and a third transistor, the input terminal of the third inverter is connected to the first digital signal terminal; One pole is connected to the first analog signal terminal, the second pole is connected to the output terminal of the third inverter, and the gate is connected to the first data reading signal terminal.
  • the pixel driving circuit further includes: a first data writing circuit connected to the first node, the data signal terminal, and the first gate driving signal terminal, and for transmitting the signal at the data signal terminal to the first node in response to the signal at the first gate drive signal terminal.
  • the pixel driving circuit further includes: a second data writing circuit connected to the first node, the data signal terminal, and the second gate driving signal terminal, for transmitting the signal of the data signal terminal to the first node in response to the signal of the second gate drive signal terminal; the conduction level of the first data writing circuit and the second data writing circuit Opposite polarity.
  • the first data writing circuit includes: a fourth transistor, a first electrode of the fourth transistor is connected to the data signal terminal, and a second electrode is connected to the first node, The gate is connected to the first gate drive signal terminal;
  • the second data writing circuit includes: a fifth transistor, a first electrode of the fifth transistor is connected to the data signal terminal, and a second electrode is connected to the third One node, the gate electrode is connected to the second gate drive signal terminal; among the fourth transistor and the fifth transistor, one transistor is an N-type transistor, and the other transistor is a P-type transistor.
  • the pixel driving circuit further includes: a second light-emitting control circuit and a second digital circuit.
  • the second light-emitting control circuit is connected to the second digital signal terminal and is connected in series with the driving circuit. between the first power terminal and the light-emitting unit, for responding to the second digital signal of the second digital signal terminal to turn on or off the current path between the first power terminal and the light-emitting unit;
  • the second digital circuit includes a second signal conversion circuit, the second signal conversion circuit is connected to a second analog signal terminal and the second digital signal terminal, and is used to transmit the signal to the second analog signal terminal according to the second analog signal of the second analog signal terminal.
  • the second digital signal terminal inputs the second digital signal.
  • the second digital circuit further includes: a second switch unit and a second detection circuit.
  • the second switch unit is connected to the second signal conversion circuit and the second analog signal terminal. between the second signal conversion circuit and the second analog signal terminal in response to the signal of the second data writing signal terminal; the second detection circuit is connected to the second digital signal terminal and the second analog signal terminal.
  • a second data reading signal terminal used to respond to the signal of the second data reading signal terminal to transmit the signal of the second digital signal terminal to the second analog signal terminal.
  • the second signal conversion circuit includes: a fourth inverter and a fifth inverter.
  • the input end of the fourth inverter is connected to the second analog signal end, and the output end is connected to the second analog signal end.
  • the second light-emitting control circuit includes: a sixth transistor, a first electrode of the sixth transistor is connected to the first light-emitting control circuit, a second electrode is connected to the light-emitting unit, and a gate electrode is connected to the second digital signal terminal.
  • the second detection circuit is also used to invert the signal transmitted from the second digital signal terminal to the second analog signal terminal;
  • the second detection circuit includes: a sixth inverter and a seventh transistor,
  • the input terminal of the sixth inverter is connected to the second digital signal terminal;
  • the first pole of the seventh transistor is connected to the second analog signal terminal,
  • the second pole is connected to the output terminal of the sixth inverter, and the gate electrode Connect the second data read signal terminal.
  • the light-emitting unit is a micro-light emitting diode.
  • a pixel driving circuit driving method is provided, wherein the driving method is used to drive the above-mentioned pixel driving circuit, and the driving method includes:
  • the first signal conversion circuit is used to input the first digital signal to the first digital signal terminal according to the first analog signal of the first analog signal terminal;
  • the duty cycle of the effective level in the first digital signal is used to adjust the gray scale of the sub-pixel where the pixel driving circuit is located.
  • the driving method includes:
  • the duty cycle of the effective level in the first digital signal is used to adjust the gray level of the sub-pixel where the pixel driving circuit is located.
  • the driving method further includes:
  • the first detection circuit is used to transmit the signal of the first digital signal terminal to the first analog signal terminal.
  • the driving method when the pixel driving circuit includes a second light emitting control circuit and a second digital circuit, the driving method further includes:
  • the duty cycle of the overlap period of the effective level in the first digital signal and the effective level in the second digital signal is used to adjust the gray scale of the sub-pixel where the pixel driving circuit is located.
  • a display panel which includes the above-mentioned pixel driving circuit.
  • a display device which includes the above-mentioned display panel.
  • Figure 1 is a schematic structural diagram of an exemplary embodiment of a pixel driving circuit of the present disclosure
  • Figure 2 is a schematic structural diagram of the inverter in Figure 1;
  • Figure 3 is a timing diagram of each control signal in a driving method of the pixel driving circuit shown in Figure 1;
  • Figure 4 is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure.
  • Figure 5 is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure.
  • Figure 6 is a timing diagram of some control signals in a driving method of the pixel driving circuit shown in Figure 5;
  • FIG. 7 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments. To those skilled in the art.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • FIG. 1 is a schematic structural diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure.
  • the pixel driving circuit is used to drive the light emitting unit L to emit light.
  • the pixel driving circuit may include: a driving circuit 1, a first light emitting control circuit 21, and a first digital circuit 41.
  • the driving circuit 1 is connected to the first power terminal VDD, the first node N1, and the light-emitting unit L, and is used to use the first power terminal VDD to provide a driving current to the light-emitting unit L according to the voltage of the first node N1.
  • the light-emitting unit The other electrode of L can be connected to the second power terminal VSS;
  • the first light-emitting control circuit 21 is connected to the first digital signal terminal DS1, and is connected in series with the driving circuit 1 between the first power terminal VDD and the light-emitting unit L. time, for responding to the first digital signal of the first digital signal terminal DS1 to turn on or off the current path between the first power supply terminal VDD and the light-emitting unit L;
  • the first digital circuit 41 It includes a first signal conversion circuit 51.
  • the first signal conversion circuit 51 is connected to the first analog signal terminal BL1 and the first digital signal terminal DS1, and is used to transmit the signal to the first analog signal terminal BL1 according to the first analog signal of the first analog signal terminal BL1.
  • the first digital signal terminal DS1 inputs the first digital signal.
  • a data signal can be input to the first node N1; in the light-emitting stage: the driving circuit 1 can use the first power terminal VDD to input a data signal to the light-emitting unit L according to the data signal of the first node N1.
  • Driving current at the same time, a first analog signal can be input to the first analog signal terminal BL1.
  • the first analog signal can include an active level and an inactive level that are alternately output.
  • the first digital signal can include an active level and an inactive level that are alternately output. level.
  • the first lighting control circuit 21 conducts the current path between the first power supply terminal VDD and the light-emitting unit L.
  • the first lighting control circuit 21 21 When the first digital signal is at an inactive level, the first lighting control circuit 21 21. Turn off the current path between the first power terminal VDD and the light-emitting unit L.
  • the greater the duty cycle of the effective level in the first digital signal the greater the brightness of the light-emitting unit L.
  • the smaller the duty cycle of the effective level in the first digital signal the smaller the brightness of the light-emitting unit L.
  • the pixel driving circuit can adjust the gray scale of the sub-pixel where the pixel driving circuit is located by controlling the duty cycle of the effective level in the first digital signal.
  • the effective level refers to the level that can drive the target circuit to turn on
  • the invalid level refers to the level that can drive the target circuit to turn off.
  • the valid level is high level and the invalid level is low level.
  • the pixel driving circuit can only use the data signal of the first node to control the gray level of the sub-pixel at a high gray level, and the duty cycle of the effective level in the first digital signal can be 100%; At low gray levels, the gray level of the sub-pixel can be controlled only by using the duty cycle of the effective level in the first digital signal, and the voltage of the first node N1 can remain unchanged in the low gray level range.
  • This setting can keep the output current of the driving circuit 1 at a higher value. Since the light-emitting unit L has higher luminous efficiency at a higher driving current, this setting can improve the luminous efficiency of the light-emitting unit L and reduce the pixel count. Power consumption of the driver circuit.
  • the low gray level can be from 0 gray level to 40 gray level.
  • the low gray level can be 0 gray level, 20 gray level, and 40 gray level;
  • the high gray level can be 41 gray level.
  • Level - 255 gray level for example, the high gray level can be 41 gray level, 100 gray level, 150 gray level, 200 gray level, 255 gray level.
  • the pixel driving circuit may also have other driving methods.
  • the pixel driving circuit may utilize the data signal of the first node and the first digital signal at each gray level.
  • the duty cycle of the active level also controls the gray scale of the sub-pixel. By adjusting the duty cycle of the effective level in the first digital signal, the gray scale corresponding to the original data signal can be further subdivided, so that the driving method can improve the control accuracy of the gray scale.
  • the first digital circuit 41 can convert the first analog signal into a first digital signal.
  • Both the logic 1 and the logic 0 of the first digital signal are stable potentials, so that this setting can improve the efficiency of gray scale adjustment. stability.
  • the first digital circuit 41 may further include: a first switch unit 61 , and the first switch unit 61 is connected to the first signal conversion circuit 51 and the first Between the analog signal terminals BL1, the first signal conversion circuit 51 and the first analog signal terminal BL1 are connected in response to the signal of the first data writing signal terminal Wdw1.
  • the first digital circuit 41 may also include: a first detection circuit 71, the first detection circuit 71 is connected to the first digital signal terminal DS1, the first analog signal terminal BL1.
  • the first data reading signal terminal Wdr1 is used to respond to the signal of the first data reading signal terminal Wdr1 and transmit the signal of the first digital signal terminal DS1 to the first analog signal terminal BL1.
  • the first signal conversion circuit 51 may include: a first inverter I1 and a second inverter I2.
  • the input end of the first inverter I1 is connected to the The first analog signal terminal BL1 has an output terminal connected to the first digital signal terminal DS1; the input terminal of the second inverter I2 is connected to the first digital signal terminal DS1 and the output terminal is connected to the first inverter I1.
  • input terminal may also have other structures.
  • the first signal conversion circuit 51 may be an analog-to-digital converter.
  • the first signal conversion circuit 51 may also be an analog-to-digital converter. Only the first inverter I1 may be included.
  • the driving circuit 1 may include: a driving transistor DT, the first pole of the driving transistor DT is connected to the first power supply terminal VDD, and the second pole is connected to the second node N2, The gate is connected to the first node N1.
  • the first light emitting control circuit 21 includes: a first transistor T1, a first electrode of the first transistor T1 is connected to the second node N2, a second electrode is connected to the light emitting unit L, and a gate electrode is connected to the first digital signal. Terminal DS1. It should be understood that the first lighting control circuit 21 can also be connected between the first power terminal VDD and the driving circuit 1 .
  • the first switch unit 61 may include: a second transistor T2 , the first electrode of the second transistor T2 is connected to the first analog signal terminal BL1 , and the second electrode of the second transistor T2 is connected to the first analog signal terminal BL1 .
  • the gate of the first signal conversion circuit 51 is connected to the first data writing signal terminal Wdw1.
  • the first detection circuit 71 is also used to invert the signal transmitted from the first digital signal terminal DS1 to the first analog signal terminal BL1.
  • the first detection circuit 71 may include: a third inverter I3 and a third transistor T3.
  • the input terminal of the third inverter I3 is connected to the first digital signal terminal DS1; the first pole of the third transistor T3 is connected to
  • the first analog signal terminal BL1 has a second electrode connected to the output terminal of the third inverter I3 and a gate connected to the first data reading signal terminal Wdr1.
  • the pixel driving circuit further includes: a first data writing circuit 81, which is connected to the first node N1, the data signal terminal Da, and the first data writing circuit 81.
  • a gate drive signal terminal G1 is used to transmit the signal of the data signal terminal Da to the first node N1 in response to the signal of the first gate drive signal terminal G1.
  • the first data writing circuit 81 may include: a fourth transistor T4, a first electrode of the fourth transistor T4 is connected to the data signal terminal Da, a second electrode is connected to the first node N1, and a gate electrode is connected to the data signal terminal Da.
  • the pixel driving circuit may further include a capacitor C, and the capacitor C is connected between the first node N1 and the second node N2.
  • the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may be N-type transistors, and the first power supply terminal VDD may be a high-level power supply terminal.
  • the second power supply terminal VSS can be a low-level power supply terminal. It should be understood that in other exemplary embodiments, the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may also be P-type transistors.
  • each inverter may include an N-type transistor NT and a P-type transistor PT.
  • the first pole of the N-type transistor NT is connected to the low-level signal terminal VGL
  • the second pole is connected to the output terminal OUT of the inverter
  • the gate is connected to the input terminal IN of the inverter
  • the first pole of the P-type transistor PT is connected to the high-level signal terminal VGL.
  • the flat signal terminal VGH, the second pole is connected to the output terminal OUT of the inverter, and the gate is connected to the input terminal IN of the inverter.
  • FIG. 3 it is a timing diagram of each control signal in a driving method of the pixel driving circuit shown in Figure 1.
  • G1 represents the timing diagram of the signal on the first gate drive signal terminal
  • Wdw1 represents the timing diagram of the signal on the first data writing signal terminal
  • BL1 represents the timing diagram of the signal on the first analog signal terminal
  • Wdr1 represents the first data Timing diagram of the signal on the read signal terminal.
  • the pixel driving circuit driving method may include three stages: data writing stage t1, light emitting stage t2, and detection stage t3. Among them, during the data writing stage t1, the first gate drive signal terminal G1 outputs a high-level signal, the fourth transistor T4 is turned on, and the data signal terminal Da inputs a data signal to the first node N1. In the light-emitting phase t2, the data signal on the first node N1 drives the driving transistor DT to input a driving current to the second node N2. At the same time, the first data writing signal terminal Wdw1 outputs a high-level signal, the second transistor T2 is turned on, and the first analog signal terminal BL1 inputs a first analog signal to the first signal conversion circuit 51.
  • the first analog signal includes alternately output high level and low level.
  • the first inverter I1 converts the first analog signal into a low level digital signal and transmits it to the first digital signal terminal DS1.
  • the first inverter I1 converts the first analog signal into a high level digital signal and transmits it to the first digital signal terminal DS1.
  • the second inverter I2 can invert the first digital signal at the first digital signal terminal DS1 and transmit it to the input terminal of the first inverter I1.
  • the second inverter I2 and the first inverter I1 can form a latch structure, and the latch structure can improve the stability of the signal at the input end of the first inverter I1.
  • the first digital signal on the first digital signal terminal DS1 can control the first transistor T1 to turn on or off, thereby controlling the gray scale of the sub-pixel.
  • the detection phase t3 the first data reading signal terminal Wdr1 outputs a high level, the third transistor T3 is turned on, and the third inverter I3 inverts the signal of the first digital signal terminal DS1 and transmits it to the first analog signal terminal BL1, so that the voltage on the first analog signal terminal BL1 can be detected through an external detection circuit to detect whether the logic signal on the first digital signal terminal DS1 is correct.
  • the detection stage t3 may be located in a blank stage between frames. As shown in Figure 3, during the light-emitting phase t2, the first data writing signal terminal Wdw1 can continue to output a high-level signal. It should be understood that in other exemplary embodiments, the detection phase t3 may also be located in other time periods. In addition, in other exemplary embodiments, during the light-emitting phase t2, the first data writing signal terminal Wdw1 can also output multiple high-level pulse signals.
  • the high-level pulse signals output by the first data writing signal terminal Wdw1 and The low-level pulse signal output by the first analog signal terminal BL1 corresponds to one-to-one, and the high-level pulse signal output by the first data writing signal terminal Wdw1 and the corresponding low-level pulse signal output by the first analog signal terminal BL1 At least partially overlap in the output period.
  • the gate-source voltage difference of the fourth transistor T4 is small, wherein the gate-source voltage difference of the fourth transistor T4 It is equal to the voltage difference between the first gate drive signal terminal G1 and the first node N1.
  • a small gate-source voltage difference may fail to turn on the fourth transistor T4. That is, the data signal terminal Da cannot write the required data signal voltage to the first node N1.
  • FIG. 4 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit of the present disclosure.
  • the pixel driving circuit may further include: a second data writing circuit 82.
  • the second data writing circuit 82 is connected to the first node N1, the data signal terminal Da, and the second gate driving signal.
  • Terminal G2 is used to transmit the signal of the data signal terminal Da to the first node N1 in response to the signal of the second gate drive signal terminal G2; the first data writing circuit 81 and the second The on-level polarity of the data writing circuit 82 is reversed.
  • the second data writing circuit 82 may include: a fifth transistor T5, a first electrode of the fifth transistor T5 is connected to the data signal terminal Da, a second electrode is connected to the first node N1, and a gate electrode is connected to the data signal terminal Da.
  • the second gate driving signal terminal G2 and the fifth transistor T5 may be P-type transistors.
  • the fifth transistor T5 can be turned on through the second gate drive signal terminal G2. Since the fifth transistor T5 is a P-type transistor, the fifth transistor T5 The smaller the gate-source voltage difference of the transistor T5 is, the more fully the fifth transistor T5 is turned on.
  • the gate-source voltage difference of the fifth transistor T5 is equal to the voltage difference between the second gate drive signal terminal G2 and the data signal terminal Da. Therefore, the data signal terminal Da can input a larger voltage to the first node N1 through the fifth transistor T5. That is, this setting increases the setting range of the data signal voltage.
  • the fourth transistor T4 and the fifth transistor T5 may be turned on at the same time. It should be understood that in other exemplary embodiments, the fifth transistor T5 may be turned on when the data signal voltage is relatively high, and the fourth transistor T5 may be turned on when the data signal voltage is relatively small. Furthermore, in other exemplary embodiments, the fourth transistor T4 may be a P-type transistor, and the fifth transistor T5 may be an N-type transistor.
  • the first analog signal terminal BL1 in order to prevent the light-emitting unit L from flickering, the first analog signal terminal BL1 needs to output a higher frequency low-level pulse signal.
  • the pulse duration of the low-level pulse signal output by the first analog signal terminal BL1 in the high-frequency output state will not be too small.
  • the high-level duty cycle on the first digital signal terminal DS1 cannot be too small, that is, the adjustment range of the high-level duty cycle on the first digital signal terminal DS1 is limited.
  • the pixel driving circuit may further include: a second light emitting control circuit 22 and a second digital circuit 42 .
  • the second light emitting control circuit 22 is connected to the second digital signal terminal DS2 and is connected to the driving circuit 1 is connected in series between the first power terminal VDD and the light-emitting unit L, and is used to turn on or turn off the first power terminal VDD and the light-emitting unit L in response to the second digital signal of the second digital signal terminal DS2.
  • the current path between the light-emitting units L; the second digital circuit 42 includes a second signal conversion circuit 52, the second signal conversion circuit 52 is connected to the second analog signal terminal BL2 and the second digital signal terminal DS2.
  • the second digital signal is input to the second digital signal terminal DS2 according to the second analog signal of the second analog signal terminal BL2.
  • the second digital circuit 42 further includes: a second switch unit 62 and a second detection circuit 72 .
  • the second switch unit 62 is connected to the second signal conversion circuit 52 and the second analog signal terminal BL2, for responding to the signal of the second data writing signal terminal Wdw2 to connect the second signal conversion circuit 52 and the second analog signal terminal BL2; the second detection circuit 72 Connect the second digital signal terminal DS2, the second analog signal terminal BL2, and the second data read signal terminal Wdr2 for responding to the signal of the second data read signal terminal Wdr2 to change the second digital signal terminal
  • the signal of DS2 is transmitted to the second analog signal terminal BL2.
  • the second signal conversion circuit 52 may include: a fourth inverter I4 and a fifth inverter I5.
  • the input end of the fourth inverter I4 is connected to the The second analog signal terminal BL2 has an output terminal connected to the second digital signal terminal DS2; the input terminal of the fifth inverter I5 is connected to the second digital signal terminal DS2, and the output terminal is connected to the fourth inverter I4. input terminal.
  • the second light emitting control circuit 22 may include: a sixth transistor T6, a first electrode of the sixth transistor T6 is connected to the first light emitting control circuit 21, a second electrode is connected to the light emitting unit L, and a gate electrode is connected to the first light emitting control circuit 21.
  • the second detection circuit 72 is also used to invert the signal transmitted from the second digital signal terminal DS2 to the second analog signal terminal BL2; the second detection circuit 72 may include: a sixth inversion signal.
  • the output terminal of the sixth inverter I6 has a gate connected to the second data read signal terminal Wdr2.
  • FIG 6 it is a timing diagram of some control signals in a driving method of the pixel driving circuit shown in Figure 5, where Wdw1 represents the timing diagram of the signal on the first data writing signal terminal, and Wdw2 represents the second data writing The timing diagram of the signal on the signal terminal, DS1 represents the timing of the signal on the first digital signal terminal, and DS2 represents the timing of the signal on the second digital signal terminal.
  • the first analog signal on the first analog signal terminal BL1 and the second analog signal on the second analog signal terminal BL2 may have different timings, so that the first digital signal on the first digital signal terminal DS1 and the second digital signal on the second digital signal terminal DS2 have different timings.
  • the high-level period of the first digital signal and the high-level period of the second digital signal may partially overlap.
  • the first transistor T1 and the sixth transistor T6 are turned on at the same time, and the light-emitting unit L emits light. It can be seen from Figure 6 that when the lighting frequency of the light-emitting unit L remains unchanged, the pixel driving circuit shown in Figure 6 can achieve a shorter single lighting time of the light-emitting unit L, thereby achieving smaller gray scale adjustment.
  • the first digital circuit 41 is combined in the pixel driving circuit architecture of 3T1C; as shown in Figure 5, the first digital circuit 41 and the second digital circuit 42 are combined in the pixel of 5T1C. in the driver circuit architecture.
  • the first digital circuit 41 and/or the second digital circuit 42 may also be incorporated into pixel driving circuits of other architectures.
  • FIG. 7 it is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit of the present disclosure.
  • the first digital circuit 41 and the second digital circuit 42 may be integrated into the pixel driving circuit architecture of the 7T1C.
  • the pixel driving circuit may also include: a driving transistor M3, a first transistor M1, a second transistor M2, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. , seventh transistor M7, capacitor C.
  • the first electrode of the fourth transistor M4 is connected to the data signal terminal Da
  • the second electrode of the fourth transistor M4 is connected to the first electrode of the driving transistor M3, and the gate electrode of the fourth transistor M4 is connected to the first gate driving signal terminal G1
  • the first electrode of the fifth transistor M5 is connected to the first power terminal VDD
  • the second electrode of the fifth transistor M5 is connected to the first electrode of the driving transistor M3, and the gate electrode of the fifth transistor M5 is connected to the first digital signal terminal DS1
  • the driving transistor M3 The gate of the second transistor M2 is connected to the node N
  • the first electrode of the second transistor M2 is connected to the node N
  • the second electrode of the second transistor M2 is connected to the second electrode of the driving transistor M3, and the gate of the second transistor M2 is connected to the second gate driving signal.
  • the first electrode of the sixth transistor M6 is connected to the second electrode of the driving transistor M3, the second electrode of the sixth transistor M6 is connected to the second electrode of the seventh transistor M7, and the gate electrode of the sixth transistor M6 is connected to the second digital signal terminal DS2.
  • the first electrode of the seventh transistor M7 is connected to the second initial signal terminal ViniM2, and the gate electrode of the seventh transistor M7 is connected to the second reset signal terminal Re2;
  • the second electrode of the first transistor M1 is connected to the node N, and the second electrode of the first transistor M1 is connected to the node N.
  • the pixel driving circuit can be connected to a light-emitting unit L.
  • the pixel driving circuit is used to drive the light-emitting unit L to emit light.
  • the first electrode of the light-emitting unit L can be connected to the second electrode of the sixth transistor M6, and the second electrode of the light-emitting unit can be connected to The second power terminal VSS.
  • the first transistor M1 and the second transistor M2 may be N-type transistors, and the driving transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 may be P-type transistors.
  • the light-emitting unit L may be a micro light-emitting diode (Micro Light Emitting Diode, referred to as Micro LED), a sub-millimeter light-emitting diode (Mini Light Emitting Diode, referred to as Mini LED), etc.
  • the size of the sub-millimeter light-emitting diode is approximately 100-300 ⁇ m; the size of micro light-emitting diodes is below 100 ⁇ m.
  • the pixel driving circuit may be a CMOS pixel driving circuit integrated on a silicon base.
  • the backplane in the display panel may include silicon elements, such as polysilicon or monocrystalline silicon, and the backplane may be called a silicon substrate or a silicon-based backplane.
  • the transistors in the pixel drive circuit are formed in the silicon substrate through a CMOS process.
  • the silicon-based transistor formed in the silicon substrate includes a silicon substrate.
  • the silicon-based transistor may have the following advantages: 1. The size of the silicon-based transistor is tens to hundreds of nanometers. , the size of glass-based thin film transistors is several microns to tens of microns, and the size of silicon-based transistors is small. 2.
  • the conduction time of silicon-based transistors is tens of picoseconds, and the conduction time of glass-based thin film transistors is between tens and hundreds of nanoseconds (nanoseconds).
  • the conduction time of silicon-based transistors is faster. 3.
  • the stability of silicon-based transistors is higher than that of transistors prepared on glass substrates.
  • the pixel driving circuit composed of glass-based transistors does not need to compensate for the threshold voltage. It should be understood that in other exemplary embodiments, the light-emitting unit may also be other types of light-emitting diodes.
  • This exemplary embodiment also provides a pixel driving circuit driving method, wherein the driving method is used to drive the above-mentioned pixel driving circuit, and the driving method includes:
  • the first signal conversion circuit is used to input the first digital signal to the first digital signal terminal according to the first analog signal of the first analog signal terminal;
  • the duty cycle of the effective level in the first digital signal is used to adjust the gray scale of the sub-pixel where the pixel driving circuit is located.
  • the driving method includes:
  • the duty cycle of the effective level in the first digital signal is used to adjust the gray level of the sub-pixel where the pixel driving circuit is located.
  • the driving method when the first digital circuit includes a first detection circuit, the driving method further includes:
  • the first detection circuit is used to transmit the signal of the first digital signal terminal to the first analog signal terminal.
  • the driving method when the pixel driving circuit includes a second light emitting control circuit and a second digital circuit, the driving method further includes:
  • the duty cycle of the overlap period of the effective level in the first digital signal and the effective level in the second digital signal is used to adjust the gray scale of the sub-pixel where the pixel driving circuit is located.
  • This exemplary embodiment also provides a display panel, wherein the display panel may include the above-mentioned pixel driving circuit.
  • This exemplary embodiment also provides a display device, wherein the display device includes the above-mentioned display panel.
  • the display device can be a display device such as VR (Virtual Reality, virtual reality), AR (Augmented Reality, augmented reality), mobile phone, tablet computer, etc.

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Abstract

一种像素驱动电路及其驱动方法、显示面板、显示装置，像素驱动电路用于驱动发光单元(L)发光，像素驱动电路包括：驱动电路(1)、第一发光控制电路(21)、第一数字电路(41)。驱动电路(1)连接第一电源端(VDD)、第一节点(N1)、发光单元(L)，用于根据第一节点(N1)的电压利用第一电源端(VDD)向发光单元(L)提供驱动电流；第一发光控制电路(21)连接第一数字信号端(DS1)，且与驱动电路(1)串联于第一电源端(VDD)和发光单元(L)之间，用于响应第一数字信号端(DS1)的第一数字信号以导通或关断第一电源端(VDD)和发光单元(L)之间的电流通路；第一数字电路(41)包括第一信号转换电路(51)，第一信号转换电路(51)连接第一模拟信号端(BL1)、第一数字信号端(DS1)，用于根据第一模拟信号端(BL1)的第一模拟信号向第一数字信号端(DS1)输入第一数字信号。像素驱动电路具有较低的功耗和较好的稳定性。

Description

像素驱动电路及其驱动方法、显示面板、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路及其驱动方法、显示面板、显示装置。
背景技术
相关技术中，像素驱动电路一般根据数据信号的电压向发光单元提供驱动电流，即像素驱动电路通过数据信号的电压控制子像素单元的灰阶。然而，该架构的像素驱动电路存在功耗高、灰阶调节精度低等问题。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的一个方面，提供一种像素驱动电路，其中，所述像素驱动电路用于驱动发光单元发光，所述像素驱动电路包括：驱动电路、第一发光控制电路、第一数字电路，驱动电路连接第一电源端、第一节点、发光单元，用于根据所述第一节点的电压利用所述第一电源端向所述发光单元提供驱动电流；第一发光控制电路连接第一数字信号端，且与所述驱动电路串联于所述第一电源端和所述发光单元之间，用于响应所述第一数字信号端的第一数字信号以导通或关断所述第一电源端和所述发光单元之间的电流通路；所述第一数字电路包括第一信号转换电路，所述第一信号转换电路连接第一模拟信号端、所述第一数字信号端，用于根据所述第一模拟信号端的第一模拟信号向所述第一数字信号端输入所述第一数字信号。
本公开一种示例性实施例中，所述第一数字电路还包括：第一开关单元，第一开关单元连接于所述第一信号转换电路和所述第一模拟信号端之间，用于响应第一数据写入信号端的信号以连接所述第一信号转换电路和 所述第一模拟信号端。
本公开一种示例性实施例中，所述第一数字电路还包括：第一检测电路，第一检测电路连接所述第一数字信号端、第一模拟信号端、第一数据读取信号端，用于响应所述第一数据读取信号端的信号以将所述第一数字信号端的信号传输到所述第一模拟信号端。
本公开一种示例性实施例中，所述第一信号转换电路包括：第一反相器、第二反相器，第一反相器的输入端连接所述第一模拟信号端，输出端连接所述第一数字信号端；第二反相器的输入端连接所述第一数字信号端，输出端连接所述第一反相器的输入端。
本公开一种示例性实施例中，所述驱动电路包括：驱动晶体管，驱动晶体管的第一极连接所述第一电源端，第二极连接第二节点，栅极连接所述第一节点。所述第一发光控制电路包括：第一晶体管，第一晶体管的第一极连接所述第二节点，第二极连接所述发光单元，栅极连接所述第一数字信号端。
本公开一种示例性实施例中，所述第一开关单元包括：第二晶体管，第二晶体管的第一极连接所述第一模拟信号端，第二极连接所述第一信号转换电路，栅极连接所述第一数据写入信号端。
本公开一种示例性实施例中，所述第一信号转换电路包括：第一反相器，第一反相器的输入端连接所述第一模拟信号端，输出端连接所述第一数字信号端；所述第一检测电路还用于将从所述第一数字信号端传输到所述第一模拟信号端的信号进行反相。
本公开一种示例性实施例中，所述第一检测电路包括：第三反相器、第三晶体管，第三反相器的输入端连接所述第一数字信号端；第三晶体管的第一极连接所述第一模拟信号端，第二极连接所述第三反相器的输出端，栅极连接所述第一数据读取信号端。
本公开一种示例性实施例中，所述像素驱动电路还包括：第一数据写入电路，第一数据写入电路连接所述第一节点、数据信号端、第一栅极驱动信号端，用于响应所述第一栅极驱动信号端的信号将所述数据信号端的信号传输到所述第一节点。
本公开一种示例性实施例中，所述像素驱动电路还包括：第二数据写 入电路，第二数据写入电路连接所述第一节点、数据信号端、第二栅极驱动信号端，用于响应所述第二栅极驱动信号端的信号将所述数据信号端的信号传输到所述第一节点；所述第一数据写入电路和所述第二数据写入电路的导通电平极性相反。
本公开一种示例性实施例中，所述第一数据写入电路包括：第四晶体管，所述第四晶体管的第一极连接所述数据信号端，第二极连接所述第一节点，栅极连接所述第一栅极驱动信号端；所述第二数据写入电路包括：第五晶体管，所述第五晶体管的第一极连接所述数据信号端，第二极连接所述第一节点，栅极连接所述第二栅极驱动信号端；在所述第四晶体管和所述第五晶体管中，一个晶体管为N型晶体管，另一晶体管为P型晶体管。
本公开一种示例性实施例中，所述像素驱动电路还包括：第二发光控制电路、第二数字电路，第二发光控制电路连接第二数字信号端，且与所述驱动电路串联于所述第一电源端和所述发光单元之间，用于响应所述第二数字信号端的第二数字信号以导通或关断所述第一电源端和所述发光单元之间的电流通路；所述第二数字电路包括第二信号转换电路，所述第二信号转换电路连接第二模拟信号端、所述第二数字信号端，用于根据所述第二模拟信号端的第二模拟信号向所述第二数字信号端输入所述第二数字信号。
本公开一种示例性实施例中，所述第二数字电路还包括：第二开关单元、第二检测电路，第二开关单元连接于所述第二信号转换电路和所述第二模拟信号端之间，用于响应第二数据写入信号端的信号以连接所述第二信号转换电路和所述第二模拟信号端；第二检测电路连接所述第二数字信号端、第二模拟信号端、第二数据读取信号端，用于响应所述第二数据读取信号端的信号以将所述第二数字信号端的信号传输到所述第二模拟信号端。
本公开一种示例性实施例中，所述第二信号转换电路包括：第四反相器、第五反相器，第四反相器的输入端连接所述第二模拟信号端，输出端连接所述第二数字信号端；第五反相器的输入端连接所述第二数字信号端，输出端连接所述第四反相器的输入端。所述第二发光控制电路包括：第六晶体管，第六晶体管的第一极连接所述第一发光控制电路，第二极连接所 述发光单元，栅极连接所述第二数字信号端。所述第二检测电路还用于将从所述第二数字信号端传输到所述第二模拟信号端的信号进行反相；所述第二检测电路包括：第六反相器、第七晶体管，第六反相器的输入端连接所述第二数字信号端；第七晶体管的第一极连接所述第二模拟信号端，第二极连接所述第六反相器的输出端，栅极连接所述第二数据读取信号端。
本公开一种示例性实施例中，所述发光单元为微发光二极管。
根据本公开的一个方面，提供一种像素驱动电路驱动方法，其中，所述驱动方法用于驱动上述的像素驱动电路，所述驱动方法包括：
在数据写入阶段，向所述第一节点输入数据信号；
在发光阶段，利用所述第一信号转换电路根据所述第一模拟信号端的第一模拟信号向所述第一数字信号端输入所述第一数字信号；
其中，在至少部分灰阶下，利用所述第一数字信号中有效电平的占空比调节所述像素驱动电路所在子像素的灰阶。
本公开一种示例性实施例中，所述驱动方法包括：
在高灰阶下，利用所述第一节点的电压调节所述像素驱动电路所在子像素的灰阶；
在低灰阶下，利用所述第一数字信号中有效电平的占空比调节所述像素驱动电路所在子像素的灰阶。
本公开一种示例性实施例中，当所述第一数字电路还包括第一检测电路时，所述驱动方法还包括：
在检测阶段，利用所述第一检测电路将所述第一数字信号端的信号传输到所述第一模拟信号端。
本公开一种示例性实施例中，当所述像素驱动电路包括第二发光控制电路和第二数字电路时，所述驱动方法还包括：
在至少部分灰阶下，利用所述第一数字信号中有效电平和第二数字信号中有效电平交叠时段的占空比调节所述像素驱动电路所在子像素的灰阶。
根据本公开的一个方面，提供一种显示面板，其中，包括上述的像素驱动电路。
根据本公开的一个方面，提供一种显示装置，其中，包括上述的显示 面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开像素驱动电路一种示例性实施例的结构示意图；
图2为图1中反相器的结构示意图；
图3为图1所示像素驱动电路一种驱动方法中各个控制信号的时序图；
图4为本公开像素驱动电路另一种示例性实施例的结构示意图；
图5为本公开像素驱动电路另一种示例性实施例的结构示意图；
图6为图5所示像素驱动电路一种驱动方法中部分控制信号的时序图；
图7为本公开像素驱动电路另一种示例性实施例的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
本示例性实施例首先提供一种像素驱动电路，如图1所示，为本公开像素驱动电路一种示例性实施例的结构示意图。其中，所述像素驱动电路用于驱动发光单元L发光。所述像素驱动电路可以包括：驱动电路1、第一发光控制电路21、第一数字电路41。驱动电路1连接第一电源端VDD、 第一节点N1、发光单元L，用于根据所述第一节点N1的电压利用所述第一电源端VDD向所述发光单元L提供驱动电流，发光单元L的另一电极可以连接第二电源端VSS；第一发光控制电路21连接第一数字信号端DS1，且与所述驱动电路1串联于所述第一电源端VDD和所述发光单元L之间，用于响应所述第一数字信号端DS1的第一数字信号以导通或关断所述第一电源端VDD和所述发光单元L之间的电流通路；所述第一数字电路41包括第一信号转换电路51，所述第一信号转换电路51连接第一模拟信号端BL1、所述第一数字信号端DS1，用于根据所述第一模拟信号端BL1的第一模拟信号向所述第一数字信号端DS1输入所述第一数字信号。
本示例性实施例中，在数据写入阶段：可以向第一节点N1输入数据信号；在发光阶段：驱动电路1可以根据第一节点N1的数据信号利用第一电源端VDD向发光单元L输入驱动电流；同时可以向第一模拟信号端BL1输入第一模拟信号，第一模拟信号可以包括交替输出的有效电平和无效电平，相应的，第一数字信号可以包括交替输出的有效电平和无效电平。当第一数字信号为有效电平时，第一发光控制电路21导通第一电源端VDD和所述发光单元L之间的电流通路，当第一数字信号为无效电平时，第一发光控制电路21关断第一电源端VDD和所述发光单元L之间的电流通路。第一数字信号中有效电平的占空比越大，发光单元L的亮度越大，相应的，第一数字信号中有效电平的占空比越小，发光单元L的亮度越小，从而该像素驱动电路可以通过控制第一数字信号中有效电平的占空比调节该像素驱动电路所在子像素的灰阶。
需要说明的是，有效电平是指能够驱动目标电路导通的电平，无效电平是指能够驱动目标电路关断的电平。例如，当目标电路为N型晶体管时，有效电平为高电平，无效电平为低电平。
本示例性实施例中，该像素驱动电路在高灰阶下，可以仅利用第一节点的数据信号控制子像素的灰阶，第一数字信号中有效电平的占空比可以为100％；在低灰阶下，可以仅利用第一数字信号中有效电平的占空比控制子像素的灰阶，第一节点N1在低灰阶范围内电压可以不变。该设置可以使得驱动电路1的输出电流保持在一个较高的值，由于发光单元L在较高的驱动电流下具有较高的发光效率，从而该设置可以提高发光单元L的发 光效率，降低像素驱动电路的功耗。在最大灰阶为255的显示面板中，低灰阶可以为0灰阶-40灰阶，例如，低灰阶可以为0灰阶、20灰阶、40灰阶；高灰阶可以为41灰阶-255灰阶，例如，高灰阶可以为41灰阶、100灰阶、150灰阶、200灰阶、255灰阶。
应该理解的是，在其他示例性实施例中，该像素驱动电路还可以有其他驱动方法，例如，该像素驱动电路可以在每一灰阶下利用第一节点的数据信号和第一数字信号中有效电平的占空比同时控制子像素的灰阶。通过调节第一数字信号中有效电平的占空比可以对原本数据信号对应的灰阶进行进一步细分，从而该驱动方法可以提高灰阶的控制精度。
本示例性实施例中，第一数字电路41可以将第一模拟信号转换为第一数字信号，第一数字信号的逻辑1和逻辑0均为稳定的电位，从而该设置可以提高灰阶调节的稳定性。
本示例性实施例中，如图1所示，所述第一数字电路41还可以包括：第一开关单元61，第一开关单元61连接于所述第一信号转换电路51和所述第一模拟信号端BL1之间，用于响应第一数据写入信号端Wdw1的信号以连接所述第一信号转换电路51和所述第一模拟信号端BL1。
本示例性实施例中，如图1所示，所述第一数字电路41还可以包括：第一检测电路71，第一检测电路71连接所述第一数字信号端DS1、第一模拟信号端BL1、第一数据读取信号端Wdr1，用于响应所述第一数据读取信号端Wdr1的信号以将所述第一数字信号端DS1的信号传输到所述第一模拟信号端BL1。
本示例性实施例中，如图1所示，所述第一信号转换电路51可以包括：第一反相器I1、第二反相器I2，第一反相器I1的输入端连接所述第一模拟信号端BL1，输出端连接所述第一数字信号端DS1；第二反相器I2的输入端连接所述第一数字信号端DS1，输出端连接所述第一反相器I1的输入端。应该理解的是，在其他示例性实施例中，第一信号转换电路51还可以为其他结构，例如，第一信号转换电路51可以为模数转换器，再例如，第一信号转换电路51还可以仅包括第一反相器I1。
本示例性实施例中，如图1所示，所述驱动电路1可以包括：驱动晶体管DT，驱动晶体管DT的第一极连接所述第一电源端VDD，第二极连接 第二节点N2，栅极连接所述第一节点N1。所述第一发光控制电路21包括：第一晶体管T1，第一晶体管T1的第一极连接所述第二节点N2，第二极连接所述发光单元L，栅极连接所述第一数字信号端DS1。应该理解的是，第一发光控制电路21还可以连接于第一电源端VDD和驱动电路1之间。
本示例性实施例中，如图1所示，所述第一开关单元61可以包括：第二晶体管T2，第二晶体管T2的第一极连接所述第一模拟信号端BL1，第二极连接所述第一信号转换电路51，栅极连接所述第一数据写入信号端Wdw1。
本示例性实施例中，如图1所示，所述第一检测电路71还用于将从所述第一数字信号端DS1传输到所述第一模拟信号端BL1的信号进行反相。所述第一检测电路71可以包括：第三反相器I3、第三晶体管T3，第三反相器I3的输入端连接所述第一数字信号端DS1；第三晶体管T3的第一极连接所述第一模拟信号端BL1，第二极连接所述第三反相器I3的输出端，栅极连接所述第一数据读取信号端Wdr1。
本示例性实施例中，如图1所示，所述像素驱动电路还包括：第一数据写入电路81，第一数据写入电路81连接所述第一节点N1、数据信号端Da、第一栅极驱动信号端G1，用于响应所述第一栅极驱动信号端G1的信号将所述数据信号端Da的信号传输到所述第一节点N1。所述第一数据写入电路81可以包括：第四晶体管T4，所述第四晶体管T4的第一极连接所述数据信号端Da，第二极连接所述第一节点N1，栅极连接所述第一栅极驱动信号端G1。
本示例性实施例中，如图1所示，该像素驱动电路还可以包括电容C，电容C连接于第一节点N1和第二节点N2之间。
本示例性实施例中，驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4可以为N型晶体管，第一电源端VDD可以为高电平电源端，第二电源端VSS可以为低电平电源端。应该理解的是，在其他示例性实施例中，驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4也可以为P型晶体管。
如图2所示，为图1中反相器的结构示意图。本示例性实施例中，各个反相器可以包括N型晶体管NT、P型晶体管PT。N型晶体管NT的第一 极连接低电平信号端VGL，第二极连接反相器的输出端OUT，栅极连接反相器的输入端IN；P型晶体管PT的第一极连接高电平信号端VGH，第二极连接反相器的输出端OUT，栅极连接反相器的输入端IN。
如图3所示，为图1所示像素驱动电路一种驱动方法中各个控制信号的时序图。其中，G1表示第一栅极驱动信号端上信号的时序图，Wdw1表示第一数据写入信号端上信号的时序图，BL1表示第一模拟信号端上信号的时序图，Wdr1表示第一数据读取信号端上信号的时序图。
该像素驱动电路驱动方法可以包括三个阶段：数据写入阶段t1、发光阶段t2、检测阶段t3。其中，在数据写入阶段t1，第一栅极驱动信号端G1输出高电平信号，第四晶体管T4导通，数据信号端Da向第一节点N1输入数据信号。在发光阶段t2，第一节点N1上的数据信号驱动驱动晶体管DT向第二节点N2输入驱动电流。同时，第一数据写入信号端Wdw1输出高电平信号，第二晶体管T2导通，第一模拟信号端BL1向第一信号转换电路51输入第一模拟信号，第一模拟信号包括交替输出的高电平和低电平，当第一模拟信号为高电平时，第一反相器I1将第一模拟信号转换为低电平的数字信号并传输到第一数字信号端DS1，当第一模拟信号为低电平时，第一反相器I1将第一模拟信号转换为高电平的数字信号并传输到第一数字信号端DS1。第二反相器I2可以将第一数字信号端DS1的第一数字信号再进行反相并传输到第一反相器I1的输入端。第二反相器I2和第一反相器I1可以形成一锁存器结构，该锁存器结构可以提高第一反相器I1输入端信号的稳定性。第一数字信号端DS1上的第一数字信号可以控制第一晶体管T1导通或关断，从而控制子像素的灰阶。在检测阶段t3：第一数据读取信号端Wdr1输出高电平，第三晶体管T3导通，第三反相器I3对第一数字信号端DS1的信号进行反相并传输到第一模拟信号端BL1，从而可以通过外部检测电路检测第一模拟信号端BL1上的电压，以检测第一数字信号端DS1上的逻辑信号是否正确。
本示例性实施例中，检测阶段t3可以位于帧与帧之间的空白阶段。如图3所示，在发光阶段t2，第一数据写入信号端Wdw1可以持续输出高电平信号。应该理解的是，在其他示例性实施例中，检测阶段t3还可以位于其他时段。此外，在其他示例性实施例中，在发光阶段t2，第一数据 写入信号端Wdw1还可以输出多个高电平脉冲信号，第一数据写入信号端Wdw1输出的高电平脉冲信号和第一模拟信号端BL1输出的低电平脉冲信号一一对应，且第一数据写入信号端Wdw1输出的高电平脉冲信号和与其对应的第一模拟信号端BL1输出的低电平脉冲信号在输出时段上至少部分交叠。
如图1所示，当数据信号端Da需要向第一节点N1写入的数据信号电压较大时，第四晶体管T4的栅源电压差较小，其中，第四晶体管T4的栅源电压差等于第一栅极驱动信号端G1和第一节点N1的电压差。较小的栅源电压差可能无法导通第四晶体管T4。即数据信号端Da无法向第一节点N1写入所需的数据信号电压。
基于此，如图4所示，为本公开像素驱动电路另一种示例性实施例的结构示意图。本示例性实施例中，所述像素驱动电路还可以包括：第二数据写入电路82，第二数据写入电路82连接所述第一节点N1、数据信号端Da、第二栅极驱动信号端G2，用于响应所述第二栅极驱动信号端G2的信号将所述数据信号端Da的信号传输到所述第一节点N1；所述第一数据写入电路81和所述第二数据写入电路82的导通电平极性相反。所述第二数据写入电路82可以包括：第五晶体管T5，所述第五晶体管T5的第一极连接所述数据信号端Da，第二极连接所述第一节点N1，栅极连接所述第二栅极驱动信号端G2，第五晶体管T5可以为P型晶体管。当数据信号端Da需要向第一节点N1写入的数据信号电压较大时，可以通过第二栅极驱动信号端G2导通第五晶体管T5，由于第五晶体管T5为P型晶体管，第五晶体管T5的栅源电压差越小第五晶体管T5导通越充分，其中，第五晶体管T5的栅源电压差等于第二栅极驱动信号端G2和数据信号端Da的电压差。从而，数据信号端Da可以通过第五晶体管T5向第一节点N1输入较大的电压。即该设置提高了数据信号电压的设置范围。
本示例性实施例中，在数据写入阶段，第四晶体管T4和第五晶体管T5可以同时导通。应该理解的是，在其他示例性实施例中，也可以在数据信号电压较大时，导通第五晶体管T5，在数据信号电压较小时，导通第四晶体管。此外，在其他示例性实施例中，第四晶体管T4可以为P型晶体管，第五晶体管T5可以为N型晶体管。
本示例性实施例中，为了避免发光单元L出现闪烁现象，第一模拟信号端BL1需要输出较高频率的低电平脉冲信号。然而，限于向第一模拟信号端BL1提供第一模拟信号的电路的驱动能力，第一模拟信号端BL1在高频输出状态下，其输出的低电平脉冲信号的脉冲时长不会过小。从而导致第一数字信号端DS1上高电平的占空比不能过小，即第一数字信号端DS1上高电平的占空比调节范围有限。
基于此，如图5所示，为本公开像素驱动电路另一种示例性实施例的结构示意图。本示例性实施例中，所述像素驱动电路还可以包括：第二发光控制电路22、第二数字电路42，第二发光控制电路22连接第二数字信号端DS2，且与所述驱动电路1串联于所述第一电源端VDD和所述发光单元L之间，用于响应所述第二数字信号端DS2的第二数字信号以导通或关断所述第一电源端VDD和所述发光单元L之间的电流通路；所述第二数字电路42包括第二信号转换电路52，所述第二信号转换电路52连接第二模拟信号端BL2、所述第二数字信号端DS2，用于根据所述第二模拟信号端BL2的第二模拟信号向所述第二数字信号端DS2输入所述第二数字信号。
本示例性实施例中，如图5所示，所述第二数字电路42还包括：第二开关单元62、第二检测电路72，第二开关单元62连接于所述第二信号转换电路52和所述第二模拟信号端BL2之间，用于响应第二数据写入信号端Wdw2的信号以连接所述第二信号转换电路52和所述第二模拟信号端BL2；第二检测电路72连接所述第二数字信号端DS2、第二模拟信号端BL2、第二数据读取信号端Wdr2，用于响应所述第二数据读取信号端Wdr2的信号以将所述第二数字信号端DS2的信号传输到所述第二模拟信号端BL2。
本示例性实施例中，如图5所示，所述第二信号转换电路52可以包括：第四反相器I4、第五反相器I5，第四反相器I4的输入端连接所述第二模拟信号端BL2，输出端连接所述第二数字信号端DS2；第五反相器I5的输入端连接所述第二数字信号端DS2，输出端连接所述第四反相器I4的输入端。所述第二发光控制电路22可以包括：第六晶体管T6，第六晶体管T6的第一极连接所述第一发光控制电路21，第二极连接所述发光单元L，栅极连接所述第二数字信号端DS2。所述第二检测电路72还用于将从所述第二数字信号端DS2传输到所述第二模拟信号端BL2的信号进行反 相；所述第二检测电路72可以包括：第六反相器I6、第七晶体管T7，第六反相器I6的输入端连接所述第二数字信号端DS2；第七晶体管T7的第一极连接所述第二模拟信号端BL2，第二极连接所述第六反相器I6的输出端，栅极连接所述第二数据读取信号端Wdr2。
如图6所示，为图5所示像素驱动电路一种驱动方法中部分控制信号的时序图，其中，Wdw1表示第一数据写入信号端上信号的时序图，Wdw2表示第二数据写入信号端上信号的时序图，DS1表示第一数字信号端上信号的时序，DS2表示第二数字信号端上信号的时序。
在发光阶段t2，第一模拟信号端BL1上的第一模拟信号和第二模拟信号端BL2上的第二模拟信号可以具有不同的时序，以使得第一数字信号端DS1上的第一数字信号和第二数字信号端DS2上的第二数字信号具有不同的时序。其中，第一数字信号的高电平时段和第二数字信号的高电平时段可以部分交叠。如图6所示，在第一数字信号和第二数字信号的高电平交叠时段t，第一晶体管T1和第六晶体管T6同时导通，发光单元L发光。根据图6可以看出，在发光单元L点亮频率不变的情况下，图6所示像素驱动电路可以实现发光单元L更短的单次点亮时长，从而实现更小的灰阶调节。
本示例性实施例中，如图1所示，第一数字电路41结合于3T1C的像素驱动电路架构中；如图5所示，第一数字电路41和第二数字电路42结合于5T1C的像素驱动电路架构中。应该理解的是，在其他示例性实施例中，第一数字电路41和/或第二数字电路42还可以结合到其他架构的像素驱动电路中。例如，如图7所示，为本公开像素驱动电路另一种示例性实施例的结构示意图。第一数字电路41和第二数字电路42可以结合到7T1C的像素驱动电路架构中。该像素驱动电路除了包括第一数字电路41和第二数字电路42以外还可以包括：驱动晶体管M3、第一晶体管M1、第二晶体管M2、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、电容C。其中，第四晶体管M4的第一极连接数据信号端Da，第四晶体管M4的第二极连接驱动晶体管M3的第一极，第四晶体管M4的栅极连接第一栅极驱动信号端G1；第五晶体管M5的第一极连接第一电源端VDD，第五晶体管M5的第二极连接驱动晶体管M3的第一极，第五晶体管M5的 栅极连接第一数字信号端DS1；驱动晶体管M3的栅极连接节点N；第二晶体管M2的第一极连接节点N，第二晶体管M2的第二极连接驱动晶体管M3的第二极，第二晶体管M2的栅极连接第二栅极驱动信号端G2；第六晶体管M6的第一极连接驱动晶体管M3的第二极，第六晶体管M6第二极连接第七晶体管M7的第二极，第六晶体管M6栅极连接第二数字信号端DS2，第七晶体管M7的第一极连接第二初始信号端ViniM2，第七晶体管M7的栅极连接第二复位信号端Re2；第一晶体管M1的第二极连接节点N，第一晶体管M1的第一极连接第一初始信号端ViniM1，第一晶体管M1的栅极连接第一复位信号端Re1；电容C的第一电极连接节点N，电容C的第二电极连接第一电源端VDD。该像素驱动电路可以连接一发光单元L，像素驱动电路用于驱动该发光单元L发光，发光单元L的第一电极可以连接于第六晶体管M6的第二极，发光单元的第二电极可以连接第二电源端VSS。其中，第一晶体管M1和第二晶体管M2可以为N型晶体管，驱动晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7可以为P型晶体管。
本示例性实施例中，发光单元L可以为微型发光二极管(Micro Light Emitting Diode，简称Micro LED)、次毫米发光二极管(Mini Light Emitting Diode，简称Mini LED)等，次毫米发光二极管的尺寸约为100-300μm；微型发光二极管的尺寸为100μm以下。像素驱动电路可以为集成于硅基的CMOS像素驱动电路。即显示面板中的背板可以包括硅元素，例如多晶硅或单晶硅，背板可以被称为硅基板或硅基背板。像素驱动电路中的晶体管通过CMOS工艺形成于硅基板中。在一些实施例中，形成于硅基板中的硅基晶体管包括硅基底，硅基晶体管相较于玻璃基的薄膜晶体管可以具有以下优点：一、硅基晶体管的尺寸为几十纳米-几百纳米，玻璃基的薄膜晶体管尺寸为几微米-几十微米，硅基晶体管的体积小。二、硅基晶体管的导通时间为几十皮秒(picosecond)，玻璃基的薄膜晶体管导通时间是几十至几百纳秒(nanosecond)之间，硅基晶体管导通时间较快。三、硅基晶体管的稳定性高于玻璃基上制备的晶体管，玻璃基晶体管组成的像素驱动电路不需要进行对阈值电压进行补偿。应该理解的是，在其他示例性实施例中，发光单元也可以为其他类型发光二极管。
本示例性实施例还提供一种像素驱动电路驱动方法，其中，所述驱动方法用于驱动上述的像素驱动电路，所述驱动方法包括：
在数据写入阶段，向所述第一节点输入数据信号；
在发光阶段，利用所述第一信号转换电路根据所述第一模拟信号端的第一模拟信号向所述第一数字信号端输入所述第一数字信号；
其中，在至少部分灰阶下，利用所述第一数字信号中有效电平的占空比调节所述像素驱动电路所在子像素的灰阶。
本示例性实施例中，所述驱动方法包括：
在高灰阶下，利用所述第一节点的电压调节所述像素驱动电路所在子像素的灰阶；
在低灰阶下，利用所述第一数字信号中有效电平的占空比调节所述像素驱动电路所在子像素的灰阶。
本示例性实施例中，当所述第一数字电路包括第一检测电路时，所述驱动方法还包括：
在检测阶段，利用所述第一检测电路将所述第一数字信号端的信号传输到所述第一模拟信号端。
本示例性实施例中，当所述像素驱动电路包括第二发光控制电路和第二数字电路时，所述驱动方法还包括：
在至少部分灰阶下，利用所述第一数字信号中有效电平和第二数字信号中有效电平交叠时段的占空比调节所述像素驱动电路所在子像素的灰阶。
本示例性实施例还提供一种显示面板，其中，显示面板可以包括上述的像素驱动电路。
本示例性实施例还提供一种显示装置，其中，该显示装置包括上述的显示面板。该显示装置可以为VR(Virtual Reality，虚拟现实)、AR(Augmented Reality，增强现实)、手机、平板电脑等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施 例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (21)

  1. 一种像素驱动电路，其中，所述像素驱动电路用于驱动发光单元发光，所述像素驱动电路包括：
    驱动电路，连接第一电源端、第一节点、发光单元，用于根据所述第一节点的电压利用所述第一电源端向所述发光单元提供驱动电流；
    第一发光控制电路，连接第一数字信号端，且与所述驱动电路串联于所述第一电源端和所述发光单元之间，用于响应所述第一数字信号端的第一数字信号以导通或关断所述第一电源端和所述发光单元之间的电流通路；
    第一数字电路，所述第一数字电路包括第一信号转换电路，所述第一信号转换电路连接第一模拟信号端、所述第一数字信号端，用于根据所述第一模拟信号端的第一模拟信号向所述第一数字信号端输入所述第一数字信号。
  2. 根据权利要求1所述的像素驱动电路，其中，所述第一数字电路还包括：
    第一开关单元，连接于所述第一信号转换电路和所述第一模拟信号端之间，用于响应第一数据写入信号端的信号以连接所述第一信号转换电路和所述第一模拟信号端。
  3. 根据权利要求1所述的像素驱动电路，其中，所述第一数字电路还包括：
    第一检测电路，连接所述第一数字信号端、第一模拟信号端、第一数据读取信号端，用于响应所述第一数据读取信号端的信号以将所述第一数字信号端的信号传输到所述第一模拟信号端。
  4. 根据权利要求1所述的像素驱动电路，其中，所述第一信号转换电路包括：
    第一反相器，输入端连接所述第一模拟信号端，输出端连接所述第一数字信号端；
    第二反相器，输入端连接所述第一数字信号端，输出端连接所述第一反相器的输入端。
  5. 根据权利要求1所述的像素驱动电路，其中，所述驱动电路包括：
    驱动晶体管，第一极连接所述第一电源端，第二极连接第二节点，栅极连接所述第一节点；
    所述第一发光控制电路包括：
    第一晶体管，第一极连接所述第二节点，第二极连接所述发光单元，栅极连接所述第一数字信号端。
  6. 根据权利要求2所述的像素驱动电路，其中，所述第一开关单元包括：
    第二晶体管，第一极连接所述第一模拟信号端，第二极连接所述第一信号转换电路，栅极连接所述第一数据写入信号端。
  7. 根据权利要求3所述的像素驱动电路，其中，所述第一信号转换电路包括：
    第一反相器，输入端连接所述第一模拟信号端，输出端连接所述第一数字信号端；
    所述第一检测电路还用于将从所述第一数字信号端传输到所述第一模拟信号端的信号进行反相。
  8. 根据权利要求7所述的像素驱动电路，其中，所述第一检测电路包括：
    第三反相器，输入端连接所述第一数字信号端；
    第三晶体管，第一极连接所述第一模拟信号端，第二极连接所述第三反相器的输出端，栅极连接所述第一数据读取信号端。
  9. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括：
    第一数据写入电路，连接所述第一节点、数据信号端、第一栅极驱动信号端，用于响应所述第一栅极驱动信号端的信号将所述数据信号端的信号传输到所述第一节点。
  10. 根据权利要求9所述的像素驱动电路，其中，所述像素驱动电路还包括：
    第二数据写入电路，连接所述第一节点、数据信号端、第二栅极驱动信号端，用于响应所述第二栅极驱动信号端的信号将所述数据信号端的信号传输到所述第一节点；
    所述第一数据写入电路和所述第二数据写入电路的导通电平极性相反。
  11. 根据权利要求10所述的像素驱动电路，其中，所述第一数据写入电路包括：
    第四晶体管，所述第四晶体管的第一极连接所述数据信号端，第二极连接所述第一节点，栅极连接所述第一栅极驱动信号端；
    所述第二数据写入电路包括：
    第五晶体管，所述第五晶体管的第一极连接所述数据信号端，第二极连接所述第一节点，栅极连接所述第二栅极驱动信号端；
    在所述第四晶体管和所述第五晶体管中，一个晶体管为N型晶体管，另一晶体管为P型晶体管。
  12. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括：
    第二发光控制电路，连接第二数字信号端，且与所述驱动电路串联于所述第一电源端和所述发光单元之间，用于响应所述第二数字信号端的第二数字信号以导通或关断所述第一电源端和所述发光单元之间的电流通路；
    第二数字电路，所述第二数字电路包括第二信号转换电路，所述第二信号转换电路连接第二模拟信号端、所述第二数字信号端，用于根据所述第二模拟信号端的第二模拟信号向所述第二数字信号端输入所述第二数字信号。
  13. 根据权利要求12所述的像素驱动电路，其中，所述第二数字电路还包括：
    第二开关单元，连接于所述第二信号转换电路和所述第二模拟信号端之间，用于响应第二数据写入信号端的信号以连接所述第二信号转换电路和所述第二模拟信号端；
    第二检测电路，连接所述第二数字信号端、第二模拟信号端、第二数据读取信号端，用于响应所述第二数据读取信号端的信号以将所述第二数字信号端的信号传输到所述第二模拟信号端。
  14. 根据权利要求13所述的像素驱动电路，其中，所述第二信号转 换电路包括：
    第四反相器，输入端连接所述第二模拟信号端，输出端连接所述第二数字信号端；
    第五反相器，输入端连接所述第二数字信号端，输出端连接所述第四反相器的输入端；
    所述第二发光控制电路包括：
    第六晶体管，第一极连接所述第一发光控制电路，第二极连接所述发光单元，栅极连接所述第二数字信号端；
    所述第二检测电路还用于将从所述第二数字信号端传输到所述第二模拟信号端的信号进行反相；
    所述第二检测电路包括：
    第六反相器，输入端连接所述第二数字信号端；
    第七晶体管，第一极连接所述第二模拟信号端，第二极连接所述第六反相器的输出端，栅极连接所述第二数据读取信号端。
  15. 根据权利要求1所述的像素驱动电路，其中，所述发光单元为微发光二极管。
  16. 一种像素驱动电路驱动方法，其中，所述驱动方法用于驱动权利要求1-15任一项所述的像素驱动电路，所述驱动方法包括：
    在数据写入阶段，向所述第一节点输入数据信号；
    在发光阶段，利用所述第一信号转换电路根据所述第一模拟信号端的第一模拟信号向所述第一数字信号端输入所述第一数字信号；
    其中，在至少部分灰阶下，利用所述第一数字信号中有效电平的占空比调节所述像素驱动电路所在子像素的灰阶。
  17. 根据权利要求16所述的像素驱动电路驱动方法，其中，所述驱动方法包括：
    在高灰阶下，利用所述第一节点的电压调节所述像素驱动电路所在子像素的灰阶；
    在低灰阶下，利用所述第一数字信号中有效电平的占空比调节所述像素驱动电路所在子像素的灰阶。
  18. 根据权利要求16所述的像素驱动电路驱动方法，其中，当所述 第一数字电路还包括第一检测电路时，所述驱动方法还包括：
    在检测阶段，利用所述第一检测电路将所述第一数字信号端的信号传输到所述第一模拟信号端。
  19. 根据权利要求16所述的像素驱动电路驱动方法，其中，当所述像素驱动电路包括第二发光控制电路和第二数字电路时，所述驱动方法还包括：
    在至少部分灰阶下，利用所述第一数字信号中有效电平和第二数字信号中有效电平交叠时段的占空比调节所述像素驱动电路所在子像素的灰阶。
  20. 一种显示面板，其中，包括权利要求1-15任一项所述的像素驱动电路。
  21. 一种显示装置，其中，包括权利要求20所述的显示面板。
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