WO2024013872A1 - Power supply control ic and method for diagnosing power supply control ic - Google Patents

Abstract

Provided is a power supply control IC that is mounted on an ECU, that has a function capable of reactivating through a process of an internal circuit or an external circuit, and that can perform highly accurate failure predictive diagnosis. This power supply control IC is characterized by comprising: a power supply circuit that generates at least one voltage from a power supply voltage; an activation pin for activating the power supply circuit; and an activation circuit that performs a reactivation process for the power supply circuit on the basis of a reactivation signal when a prescribed voltage is applied to the activation pin.

Description

Power control IC, diagnosis method of power control IC

The present invention relates to the configuration of a semiconductor device and its control, and particularly to a technique that is effective when applied to a power control IC installed in an on-vehicle ECU that requires high reliability.

With car sharing and fully automated driving, the operating hours of cars per day will increase, and the operating hours of in-vehicle semiconductor components will also increase accordingly. Furthermore, when autonomous driving level 4 or above is put into practical use, all driving operations will be handled by the automatic driving system installed in the car, and the CPU installed in the ECU (Electronic Control Unit), which is responsible for controlling automatic driving, will It is expected that the processing amount in the central processing unit (Central Processing Unit) will increase and the loss in the power supply control IC (Integrated Circuit) will increase accordingly.

As background technology in this technical field, there is, for example, a technology such as Patent Document 1. Patent Document 1 discloses a technique for cooling electronic devices by flowing a refrigerant circulating inside an automobile into an ECU housing for the purpose of suppressing heat generation in the electronic devices.

Additionally, Patent Document 2 discloses a power control IC that has a diagnostic function that performs diagnosis when the power control IC is activated when the vehicle is in a stopped state.

Additionally, Patent Document 3 describes a diagnostic method that determines a failure only when an abnormality is detected multiple times in a row in a power supply control IC, in order to avoid erroneous diagnosis due to environmental factors such as electromagnetic noise during vehicle operation. Disclosed.

JP2014-121228A Japanese Patent Application Publication No. 2013-81349 JP 2021-154993 Publication

In general, the higher the junction temperature (operating temperature) of a semiconductor component, the faster it will lead to wear-out failure (life span), and depending on the characteristics, the characteristics may change from their initial values over the operating time (hereinafter referred to as characteristics change over time). ) may be accelerated. As described above, when the operating time of the power control IC installed in the ECU becomes longer and the junction temperature of the power control IC increases due to the increase in loss, the life of the power control IC, that is, the time at which it will fail, becomes earlier.

In such cases, when the life of the power control IC approaches the end of its life, the car can be continued to be used by replacing the ECU equipped with the power control IC. When using a vehicle, including ECU replacement, it is desirable to be able to reduce the frequency of replacement, and to achieve this, it is necessary to extend the operating time of the power supply control IC itself.

By using the technology disclosed in Patent Document 1, it is possible to suppress the rise in the junction temperature of the power supply control IC, and by slowing down the change in characteristics over time, the operating time of the power supply control IC is extended compared to the case without cooling. can. However, it is necessary to provide a path for the refrigerant to flow through the ECU casing, and an ECU casing with high heat dissipation properties is expensive.

On the other hand, if the power control IC fails, the ECU equipped with the power control IC may stop functioning, and if the ECU stops functioning while the car is running, it may lead to an accident. Therefore, it is desirable to be able to detect and notify a pre-failure sign when the power supply control IC is activated while the vehicle is in a stopped state. In particular, failures caused by changes in characteristics over time are characterized by the fact that abnormalities begin to be detected as the failure time approaches, and the probability of abnormality occurrence increases as the failure time approaches. When detecting as a sign of a failure, it is necessary to detect it in a state where the probability of detecting an abnormality is low, which is before the failure.

In the technique described in Patent Document 2, the probability of occurrence of an abnormality is low at the time when a sign of a failure is predicted, so it is difficult to detect a sign of a failure with a single diagnosis at startup. Furthermore, there is a possibility of misdiagnosis due to environmental factors, and if a misdiagnosis is made, the car will not be able to start, and in order to start it again, the user will have to turn off the ignition switch (hereinafter referred to as IG-SW) and then turn it on again. In addition to this, the detected abnormality is cleared by user operation, so even if the system is restarted, it is not possible to identify the abnormality due to startup failure. If there is a startup failure of unknown cause, there is a possibility that the ECU will be replaced even though there is plenty of operating time before the power control IC fails.

The technology described in Patent Document 3 can distinguish between a failure and a misdiagnosis due to environmental factors, depending on whether or not abnormalities are detected continuously. However, since the probability of occurrence of an abnormality is low and a sign of a failure cannot be detected, there is a possibility that the ECU will not be replaced until a failure occurs.

Given the above, it is important to provide a low-cost method to extend the operating time of the power control IC, which has severe usage conditions in terms of IC life in an ECU, and to provide a method that can detect signs of failure. becomes.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a power control IC installed in an ECU that has a function of restarting according to the processing of an internal circuit or an external circuit, and that enables more accurate predictive failure diagnosis. Our goal is to provide the following.

In order to solve the above problems, the present invention provides a power supply circuit that generates at least one voltage from a power supply voltage, a starting pin for starting the power supply circuit, and a predetermined voltage input to the starting pin. At times, the power supply circuit is characterized by comprising a startup circuit that performs restart processing of the power supply circuit based on a restart signal.

The present invention also provides the following steps: (a) inputting a startup signal for the power supply control IC; (b) counting up the number of times of diagnosis by one and storing it in memory; and (c) diagnosing the startup of the power supply control IC. (d) if an abnormality is detected in step (c), incrementing the number of abnormality detections by one and storing it in the memory; (e) counting the number of times of diagnosis and abnormality detection from the memory; and (f) comparing the abnormality detection frequency calculated in step (e) with a predetermined threshold. If the detection frequency is less than the predetermined threshold, it is determined to be normal and a restart signal for the power supply control IC is output, and if the abnormality detection frequency is greater than or equal to the predetermined threshold, it is determined to be a sign of a failure and the failure occurs. It is characterized by outputting a notification of a sign of.

According to the present invention, a power supply control IC installed in an ECU has a function of restarting according to the processing of internal circuits or external circuits, and is capable of more accurate failure symptom diagnosis. can do.

As a result, the operating time of the power supply control IC and the ECU equipped with it can be extended while suppressing cost increases.

Problems, configurations, and effects other than those described above will be made clear by the description of the embodiments below.

1 is a diagram showing a schematic configuration of an ECU according to Example 1 of the present invention. 2 is a block diagram showing a configuration example of a power supply control IC 100 in FIG. 1. FIG. 3 is a diagram illustrating a configuration example of a startup circuit 20 in FIG. 2. FIG. 3 is a diagram showing a configuration example of the power supply circuit 10 of FIG. 2. FIG. 3 is a diagram showing an example of the configuration of a startup diagnostic circuit 31 in FIG. 2. FIG. 3 is a flowchart schematically showing a startup process of the power control IC 100 of FIG. 2. FIG. FIG. 2 is a block diagram showing the configuration of a power supply control IC 100 according to a second embodiment of the present invention. 8 is a diagram showing a configuration example of the counter circuit 40 of FIG. 7. FIG. 8 is a flowchart schematically showing a startup process of the power control IC 100 of FIG. 7. FIG. 12 is a flowchart schematically showing a startup process of a power supply control IC according to a third embodiment of the present invention. FIG. 3 is a block diagram showing the configuration of a power supply control IC 100 according to a fourth embodiment of the present invention. 12 is a block diagram showing a configuration example of a characteristic control circuit 60 in FIG. 11. FIG. 12 is a timing chart schematically showing a correction operation of the characteristic control circuit 60 of FIG. 11. FIG. 12 is a flowchart schematically showing startup processing of the power control IC 100 of FIG. 11. FIG. 7 is a block diagram showing the configuration of a power supply control IC 100 according to Example 5 of the present invention. 16 is a flowchart schematically showing startup processing of the power control IC 100 of FIG. 15. FIG. 7 is a block diagram showing the configuration of a power supply control IC 100 according to a sixth embodiment of the present invention. 18 is a flowchart schematically showing startup processing of the power supply control IC 100 of FIG. 17. 7 is a block diagram showing the configuration of a power supply control IC 100 according to Example 7 of the present invention. FIG. 20 is a block diagram showing a configuration example of the restart setting circuit 50 of FIG. 19. FIG. 20 is a flowchart schematically showing startup processing of the power control IC 100 of FIG. 19.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that since the drawings are simplified, the technical scope of the present invention should not be interpreted narrowly based on the descriptions in the drawings. In addition, the same elements are given the same reference numerals, and redundant explanations will be omitted.

With reference to FIGS. 1 to 6, a power supply control IC and its diagnosis method according to a first embodiment of the present invention will be described.

In this embodiment, a process is performed in which the power control IC is stopped according to a predetermined process (hereinafter referred to as internal process) executed within the power control IC, and then the start process is restarted (hereinafter referred to as restart process). The configuration and operation of the power supply control IC, which is characterized by executing the following steps) and can be restarted by restart processing when a temporary abnormality occurs in the power supply control IC due to noise or the like, will be described.

FIG. 1 shows an example of the configuration of an ECU 1 equipped with a power supply control IC 100. The ECU 1 includes a CPU 200 that performs control and a power control IC 100 that supplies power to the CPU 200. When the IG-SW 2 is turned on by a user operation, the power supply control IC 100 performs a startup process and supplies power to the CPU 200 by generating an output voltage Voutput from the power supply voltage Vpower.

FIG. 2 is a block diagram showing a configuration example of the power supply control IC 100 of FIG. 1. The power supply control IC 100 shown in FIG. 2 includes a power supply circuit 10 that generates at least one voltage from the power supply voltage Vpower, an internal processing section 30 that performs internal processing and outputs a restart signal Srepup as necessary, and a restart signal Srepup. It is comprised of a startup circuit 20 that executes restart processing of the power supply control IC 100 when a startup signal Srepup is input.

The startup circuit 20 performs startup processing of the power supply control IC 100 when the startup signal Spup is input, and performs a shutdown processing of the power supply control IC 100 when the stop signal Spdown is input. Further, when the restart signal Srepup is input while the activation signal line 102 is high, restart processing is executed.

The power supply circuit 10 includes a startup pin (not shown) for starting the power supply circuit 10, and when a predetermined voltage is input to the startup pin, the startup circuit 20 starts the power supply circuit based on a restart signal. 10 restart processing is performed.

To give an example of the starting circuit 20 in this embodiment, a circuit configuration as shown in FIG. 3 can be considered. The startup circuit 20 shown in FIG. 3 includes a startup signal detection section 21 that detects the startup signal Spup, a diagnostic signal generation section 22 that outputs the diagnostic signal Sdiag during the diagnostic time Tdiag after detecting the startup signal Spup, and a diagnostic signal generation section 22 that outputs the diagnostic signal Sdiag during the diagnostic time Tdiag after detecting the startup signal Spup. If the restart signal Srepup is not input later, the control signal generation unit 23 outputs a logical high level (hereinafter referred to as High) to the control signal line 104, and if the restart signal Srepup is input, the control signal generation unit 23 keeps the startup signal Spup constant. It is comprised of a switch element 24 which sets the starting circuit 20 to an initial state by shutting it off for a time and then connecting it again. Further, the delay circuit 26a and the delay circuit 26b are configured to be initialized when the restart signal Srepup is input.

The initial state of the startup circuit 20 is a state in which a logical low level (hereinafter referred to as "Low") is output to the diagnostic signal line 105 and the control signal line 104. Further, since the restart signal line 101 is Low, the switch element 24 is connected, and when High is input to the startup signal line 102 as the startup signal Spup, the startup signal detection unit 21 compares it with the startup signal determination threshold voltage Vth_pup. However, if it is larger than the activation signal determination threshold voltage Vth_pup, it is determined that the activation signal Spup is present and outputs High to the diagnostic signal generation section 22.

When the diagnostic signal generating section 22 receives a High signal from the activation signal detecting section 21, it outputs a High signal to the diagnostic signal line 105 as a diagnostic signal Sdiag. The delay time of the delay circuit 26a becomes the diagnosis time Tdiag, and after the diagnosis is completed and Tdiag has elapsed, it outputs Low. By setting the delay time of the delay circuit 26b in the control signal generation unit 23 to be longer than Tdiag, it is determined whether the power supply circuit 10 is disabled or enabled depending on whether there is a restart signal Srepup after Tdiag. . Since it is known that the delay circuit can be easily realized by a plurality of NOT circuits, a description of the configuration and operation will be omitted.

If there is no restart signal Srepup after the diagnostic time Tdiag, High is output to the control signal line 104, and the power supply circuit 10 starts operating. If there is a restart signal Srepup after Tdiag, the switch element 24 is disconnected and the startup circuit 20 is initialized while outputting Low to the control signal line 104. Further, when Low is input to the activation signal line 102, the activation signal detection unit 21 determines that the stop signal Spdown is smaller than the activation signal determination threshold voltage Vth_pup, and outputs Low to the diagnostic signal generation unit 22. As a stop process, the startup circuit 20 enters an initial state in which it outputs Low to the diagnostic signal line 105 and the control signal line 104.

The power supply circuit 10 has a function (function A) of supplying power necessary for startup to internal circuits when a power supply voltage Vpower is input to a power supply line 103, and a function (function A) that supplies power necessary for starting up the internal circuit when a power supply voltage Vpower is input to a power supply line 103, and a voltage level of a control signal line 104. When the control signal Power_en that changes from Low to High is input, at least one output voltage is generated from the power supply voltage Vpower, and the function (Function B) of supplying the power necessary for ECU operation to the internal circuit or external circuit is performed. Be prepared.

Possible circuits that implement these functions include switching regulators, linear regulators, bandgap references, etc., and a configuration that includes one or more of them, or a configuration that combines them may also be used.

To give an example of the power supply circuit 10 in this embodiment, a circuit configuration as shown in FIG. 4 can be considered. The former function (function A) is configured by a linear regulator 12b, the latter function (function B) is configured by a linear regulator 12a, and is configured by a switch element 11 that disconnects or connects the power line 103 and the linear regulator 12a.

An example of the configuration of the linear regulator 12a includes a feedback resistor 16 and a feedback resistor 17 that divide the output voltage Voutput to generate a feedback voltage Vfb, and a reference voltage generator 13 that generates a reference voltage Vref that is a reference for the output voltage Voutput. and an error amplifier 15 that outputs the difference between the voltage values of the feedback voltage Vfb and the reference voltage Vref as a difference signal Sdiff, and generates an output voltage Voutput from the power supply voltage Vpower by controlling the resistance value according to the difference signal Sdiff. An example configured with MOSFET 14 is given.

The switch element 11 electrically connects the power supply voltage Vpower and the MOSFET 14 while a high level is input to the control signal line 104, and electrically connects the power supply voltage Vpower and the MOSFET 14 while a low level is input to the control signal line 104. cut the target.

It is known that the reference voltage generation unit 13 can be easily realized using a bandgap reference circuit or the like, and outputs a reference voltage Vref whose voltage value does not change due to changes in the surrounding environment such as input voltage and temperature.

By performing control so that the difference between the voltage values of the feedback voltage Vfb and the reference voltage Vref becomes small with respect to changes in the output voltage Voutput, the output voltage line 108 of the linear regulator 12a has a reference value as shown in equation (1). The output voltage Voutput determined by the voltage Vref and the feedback resistance values Rfbu and Rfbd is stably output.

Voutput=Vref×(Rfbu+Rfbd)÷Rfbd (1)
Note that since the linear regulator 12b is the same as the linear regulator 12a, explanations of the configuration and operation will be omitted.

The internal processing unit 30 outputs a restart signal Srepup when a predetermined characteristic (hereinafter referred to as an internal characteristic) within the power supply control IC 100 satisfies a predetermined condition. Here, the internal characteristics refer to physical quantities (voltage value, current value, frequency, etc.) possessed by the waveform.

As an example of the circuit installed in the internal processing section 30 in this embodiment, a circuit configuration as shown in FIG. 5 can be considered. The startup diagnostic circuit 31 shown in FIG. 5 compares the internal characteristics with the abnormality determination threshold voltage Vth_diag and outputs the restart signal Srepup. The startup diagnostic circuit 31 can detect abnormalities in the internal characteristics by monitoring the internal characteristics using the signal line 111 to be diagnosed.

As shown in FIG. 5, the startup diagnostic circuit 31 has an abnormality determination unit 32 that compares the internal characteristics monitored by the diagnosed signal line 111 with the abnormality determination threshold voltage Vth_diag, and a high level is input to the diagnostic signal line 105. It is comprised of a diagnostic control unit 33 that outputs the diagnostic results for a period, and a filter circuit 34 that determines an abnormality only when High is output during the abnormality determination filter time Tfilter. The delay amount of the delay circuit 26c determines the filter time Tfilter.

The startup diagnostic circuit 31 diagnoses whether there is an abnormality in the internal characteristics by comparing the internal characteristics with the abnormality determination threshold voltage Vth_diag when the voltage level of the diagnostic signal line 105 is High from the startup circuit 20. If the internal characteristic is larger than the abnormality determination threshold voltage Vth_diag, it is determined to be normal, and a Low signal is output to the restart signal line 101. On the other hand, if the internal characteristic is less than or equal to the abnormality determination threshold voltage Vth_diag, it is determined that the internal characteristic is abnormal, and a High signal is output to the restart signal line 101.

As an example of a startup process for restarting the power supply control IC 100 in this embodiment by internal processing, FIG. This will be explained using a flowchart.

First, when the power supply voltage Vpower is applied to the power supply line 103 (START), a voltage level High is inputted to the startup signal line 102 as the startup signal Spup in step S1. The starting circuit 20 outputs a High signal to the diagnostic signal line 105 as a diagnostic signal, and the process proceeds to step S2.

Next, in step S2, the startup diagnostic circuit 31 compares the internal characteristics and the abnormality determination threshold voltage Vth_diag. If the internal characteristic is larger than the abnormality determination threshold voltage Vth_diag, it is determined that the internal characteristic is normal (OK), and the process proceeds to step S3. If the internal characteristic is less than or equal to the abnormality determination threshold voltage Vth_diag, it is determined that the internal characteristic is abnormal (NG), and the process proceeds to step S5.

In step S3, the startup circuit 20 outputs High to the control signal line 104. The power supply circuit 10 starts operating and proceeds to step S4.

Subsequently, in step S4, the power supply circuit 10 generates an output voltage Voutput from the power supply voltage Vpower. The output voltage Voutput is supplied to the load, the load starts operating, and the startup process ends (END).

On the other hand, in step S5, the startup diagnostic circuit 31 outputs High to the restart signal line 101 as the restart signal Srepup, and the process proceeds to step S6.

In step S6, the starting circuit 20 enters the initial state as a stop process, and returns to step S2. Then, when an abnormality occurs after the last startup, the restart is repeated until no abnormality is detected. Note that the restart process may be set to be executed a predetermined number of times.

Here, the startup process refers to the process from a state in which the power supply voltage Vpower is applied to the power supply line 103 (START) to a state in which the circuit to which power is supplied to the power supply control IC 100 operates (END). Further, the restart process is a process of restarting the start process in the middle of the start process, and refers to the process from step S5 to step S6.

Although this embodiment shows a configuration example in which restart processing is performed by internal processing of the power supply control IC 100, by electrically connecting the startup circuit 20 of the power supply control IC 100 and external elements of the power supply control IC 100, It is also possible to perform restart processing of the power supply control IC 100 by processing in an external element (hereinafter referred to as external processing).

The diagnosis by the startup diagnosis circuit 31 in this embodiment is merely an example described from the perspective of comparing voltage values, and similar diagnosis can be realized in various other forms. For example, the abnormality determination unit 32, which is a comparison circuit, may be a current input type comparator circuit for comparing current values, or a circuit such as a digital counter or a phase comparator for comparing frequencies.

As explained above, the power supply control IC 100 of this embodiment is characterized by executing restart processing according to internal processing, and restarts when a temporary abnormality occurs in the power supply control IC 100 due to noise or the like. It can be restarted using the startup process.

A power supply control IC and its diagnosis method according to a second embodiment of the present invention will be described with reference to FIGS. 7 to 9.

In this embodiment, in addition to the configuration of Embodiment 1, the frequency of abnormality detection is determined by detecting the number of times of diagnosis and the number of times of abnormality detection, and when the frequency of abnormality detection is equal to or higher than a predetermined threshold value, it is determined that it is a sign of failure. The configuration and operation of the power supply control IC will be explained. Note that the following description focuses on the points that are different from the first embodiment.

FIG. 7 is a block diagram showing the configuration of the power supply control IC 100 of this embodiment. Focusing on the difference from Example 1 (FIG. 2), the power supply control IC 100 of this example includes a counter circuit 40 that counts the number of diagnoses Ndiag performed at startup and the number of abnormality detections Ndet_err; A stop signal line 110 connected to the counter circuit 40 is provided.

When the voltage level of the stop signal line 110 changes from Low to High, the startup circuit 20 enters the initial state as a stop process. A diagnostic signal line 105 and a diagnostic result signal line 106 are connected to the counter circuit 40, and each time a high level is input to the diagnostic signal line 105 as a diagnostic signal, the number of times of diagnosis Ndiag is counted up, and the diagnostic result is determined as an abnormality. Every time High is input to the signal line 106, the number of abnormality detections Ndet_err is counted up.

The abnormality detection frequency Rdet_err obtained from the number of diagnoses Ndiag and the number of abnormality detections Ndet_err is compared with the predictive judgment threshold Rth_preerr, and if the abnormality detection frequency Rdet_err is less than the predictive judgment threshold Rth_preerr, the voltage level of the restart signal line 101 is changed from Low to High. If the abnormality detection frequency Rdet_err is equal to or higher than the predictive judgment threshold Rth_preerr, the number of diagnosis times Ndiag and the number of abnormality detections Ndet_err in the counter circuit memory 47 of the counter circuit 40, which will be described later in FIG. 8, are cleared to initial values, and the stop signal line The voltage level of 110 is changed from Low to High.

Furthermore, the counter circuit 40 has a configuration or means that can hold the number of diagnoses Ndiag and the number of abnormality detections Ndet_err even if the power supply circuit 10 stops.

Note that the abnormality detection frequency Rdet_err can be calculated using the following equation (2).

Rdet_err=Ndet_err/Ndiag (2)
Considering accuracy, it is desirable to calculate the abnormality detection frequency Rdet_err from the number of activations of three or more times.

To give an example of the counter circuit 40 in this embodiment, a configuration as shown in FIG. 8 can be considered. The counter circuit 40 shown in FIG. 8 includes a diagnostic result edge detection unit 41 that detects the rising edge of the voltage level of the diagnostic result signal line 106 from Low to High, and a diagnostic result edge detection unit 41 that detects the rising edge of the voltage level of the diagnostic signal line 105 from Low to High. A diagnostic signal edge detection unit 42 that detects an edge, an abnormality detection counter circuit 44 that counts up the number of abnormality detections Ndet_err every time a rising edge is detected by the diagnostic result edge detection unit 41, and a diagnostic signal edge detection unit 42 that detects a rising edge. A diagnostic counter circuit 45 that counts up the number of diagnoses Ndiag every time an edge is detected, a counter circuit memory 47 that stores the number of abnormality detections Ndet_err, and calculates the abnormality detection frequency Rdet_err and determines the abnormality detection frequency Rdet_err and the sign. It also includes an abnormality detection frequency determination unit 46 that determines whether to start by comparing a threshold value Rth_preerr.

The abnormality detection frequency determination unit 46 calculates the abnormality detection frequency Rdet_err, which is the ratio of the number of abnormality detections Ndet_err to the number of diagnoses Ndiag, and compares the abnormality detection frequency Rdet_err with the premonition determination threshold Rth_preerr, so that the abnormality detection frequency Rdet_err becomes the predetermined threshold. If it is less than Rth_preerr, it is determined to be normal, and the voltage level of the restart signal line 101 is changed from Low to High. On the other hand, if the abnormality detection frequency Rdet_err is equal to or higher than the sign determination threshold Rth_preerr, it is determined that it is a sign of failure, and the abnormality detection frequency Ndet_err in the counter circuit memory 47 is cleared to the initial value, and the voltage level of the stop signal line 110 is changed from Low to Low. Set it to High.

Furthermore, the abnormality detection frequency determination unit 46 can also notify the user via an external element by outputting High to the communication signal line 109 when a sign of a failure is detected.

An example of the startup process of determining a sign of failure based on the abnormality detection frequency Rdet_err at startup in this embodiment will be described using the flowchart in FIG.

The flowchart shown in FIG. 9 shows that when the power supply control IC 100 detects an abnormality in the startup diagnosis, it restarts the startup by performing a restart process, calculates the abnormality detection frequency Rdet_err every time an abnormality is detected in the startup diagnosis, This is a process flow in which it is determined that it is a sign of failure when the abnormality detection frequency Rdet_err is equal to or greater than the sign determination threshold Rth_preerr, and the load is notified of the failure sign, and then the power supply control IC 100 is not activated.

Note that the following description will focus on the points that are different from the processing in Example 1 (FIG. 6).

First, when the power supply voltage Vpower is applied to the power supply line 103 (START), in step S1, the voltage level High is inputted to the startup signal line 102 as the startup signal Spup, similarly to the first embodiment (FIG. 6). The starting circuit 20 outputs a High signal to the diagnostic signal line 105 as a diagnostic signal, and the process proceeds to step S2.

In step S2, the number of diagnoses Ndiag is counted up by one, stored in the counter circuit memory 47, and the process proceeds to step S3.

In step S3, the startup diagnostic circuit 31 compares the internal characteristics and the abnormality determination threshold voltage Vth_diag. If the internal characteristics are larger than the abnormality determination threshold voltage Vth_diag and it is determined that the internal characteristics are normal (OK), steps S4 and S5 corresponding to steps S3 and S4 of the first embodiment (FIG. 6) are executed. , ends the startup process (END).

On the other hand, in step S3, if the internal characteristic is equal to or lower than the abnormality determination threshold voltage Vth_diag, it is determined that the internal characteristic is abnormal (NG), and the process proceeds to step S6.

In step S6, by detecting the rising edge of the voltage level of the diagnostic result signal line 106 from Low to High by the diagnostic result edge detection unit 41, the number of abnormality detections Ndet_err is counted up by one and stored in the counter circuit memory 47. The process then proceeds to step S7.

Next, in step S7, the number of diagnoses Ndiag and the number of abnormality detections Ndet_err are read from the counter circuit memory 47, and the abnormality detection frequency Rdet_err is calculated. If the abnormality detection frequency Rdet_err is less than the sign determination threshold Rth_preerr (<Rth_preerr), it is determined to be normal, and the process proceeds to step S8. If the abnormality detection frequency Rdet_err is greater than or equal to the sign determination threshold Rth_preerr (≧Rth_preerr), it is determined that it is a sign of failure, and the process proceeds to step S10.

In step S10, the power supply circuit 10 is temporarily enabled, and the process proceeds to step S11.

Subsequently, in step S11, power is temporarily supplied to the load, and the load is notified that there is a sign of failure.

Next, in step S12, the number of diagnoses Ndiag and the number of abnormality detections Ndet_err (that is, the abnormality detection frequency Rdet_err) in the counter circuit memory 47 are cleared to initial values, and the process proceeds to step S13.

In step S13, after the power control IC 100 is stopped, the process returns to step S1 and the processes from step S1 onwards are repeated.

On the other hand, in step S7, if the abnormality detection frequency Rdet_err is less than the sign determination threshold Rth_preerr (<Rth_preerr) and is determined to be normal, the processing in steps S8 and S9 corresponding to steps S5 and S6 in the first embodiment (FIG. 6) is executed, the process returns to step S2, and the processes from step S2 onwards are repeated.

In this embodiment, the abnormality detection frequency is cleared every time the stop signal is input, but the abnormality detection frequency obtained by inputting the start signal multiple times may be used. Judgments can be made based on the abnormality detection frequency obtained over a longer period of time.

Further, in this embodiment, when it is determined that there is a sign of failure, a flow is shown in which the failure sign is only notified and normal operation is not performed, but a flow may be adopted in which normal operation is performed after notifying the failure sign.

As explained above, the power supply control IC 100 of this embodiment determines the abnormality detection frequency by detecting the number of times of diagnosis and the number of times of abnormality detection, and determines that it is a sign of failure when the abnormality detection frequency is equal to or higher than a predetermined threshold. be able to.

With reference to FIGS. 8 to 10, a power supply control IC and its diagnosis method according to a third embodiment of the present invention will be described.

In this embodiment, as a modification of the power supply control IC 100 of the second embodiment, a configuration and an operation example will be described in which restarting is performed a fixed number of times at startup. Note that the following description will focus on the points that are different from the second embodiment.

Focusing on the difference from the counter circuit 40 of the second embodiment, in this embodiment, the counter circuit memory 47 in the counter circuit 40 further stores the number of startups Npup, which is the number of startups including restarts after inputting the startup signal Spup. It is characterized by storing the maximum number of activations Nmax_pup, which is the number of times the activation is performed in response to one input of the activation signal Spup.

Furthermore, when the number of activations Npup reaches the maximum number of activations Nmax_pup, the counter circuit 40 compares the abnormality detection frequency Rdet_err, which is the ratio of the number of abnormality detections Ndet_err to the number of diagnoses Ndiag, with the predictive judgment threshold Rth_preerr, and determines the abnormality detection frequency Rdet_err. If it is less than the premonitory determination threshold Rth_preerr, it is determined to be normal and the voltage level of the restart signal line 101 is changed from Low to High. If the abnormality detection frequency Rdet_err is equal to or higher than the sign determination threshold Rth_preerr, it is determined to be a sign of a failure, and the load is notified that it is a sign of a failure, and the abnormality detection frequency Ndet_err in the counter circuit memory 47 is cleared to the initial value. to change the voltage level of the stop signal line 110 from Low to High.

Here, in the counter circuit 40, even if the power supply control IC 100 is stopped, the number of activations Npup, the maximum number of restarts Nmax_pup, and the omen determination threshold Rth_preerr stored in the counter circuit memory 47 are retained. In particular, the maximum number of restarts Nmax_pup and the predictive sign determination threshold Rth_preerr can be changed as appropriate by external processing if they can be rewritten from an external element via a communication signal line or the like.

In addition, since the maximum number of restarts Nmax_pup and the predictive sign determination threshold Rth_preerr only need to be able to hold their values even if the power supply control IC 100 stops, A configuration in which the value is held in memory (memory) may also be used.

Further, by storing the maximum number of restarts Nmax_pup and the predictive sign determination threshold Rth_preerr in a non-volatile memory, the values may be written in advance during manufacturing, and the values may be fixed during use.

An example of the startup process in which the process is divided according to the abnormality detection frequency in this embodiment will be explained using the flowchart in FIG. 10.

The flowchart shown in FIG. 10 is a flow of a startup process in which restarting is performed a predetermined number of times at startup, and a sign of failure can be determined from the abnormality detection frequency.

Note that the following description will focus on the points that are different from the processing in Example 2 (FIG. 9).

The processing from START to step S3 is the same as in the second embodiment (FIG. 9).

In step S3, if it is determined that the internal characteristic is larger than the abnormality determination threshold voltage Vth_diag and the internal characteristic is normal (OK), the process proceeds to step S4.

In step S4, the number of activations Npup stored in the counter circuit memory 47 is read and compared with the maximum number of activations Nmax_pup. If the number of activations Npup is less than the maximum number of activations Nmax_pup (<Nmax_pup), the process advances to step S5. If the number of activations Npup has reached the maximum number of activations Nmax_pup (=Nmax_pup), the process advances to step S9.

In step S5, the number of diagnoses Ndiag and the number of abnormality detections Ndet_err stored in the counter circuit memory 47 are read out, and the abnormality detection frequency Rdet_err is calculated. If the abnormality detection frequency Rdet_err is less than the sign determination threshold Rth_preerr (<Rth_preerr), the process advances to step S6. The processing from step S6 to END is similar to the processing from step S4 to END in the second embodiment (FIG. 9).

If the abnormality detection frequency Rdet_err is greater than or equal to the sign determination threshold Rth_preerr (≧Rth_preerr), the process advances to step S8. The processing from step S8 to step S13 is similar to the processing from step S10 to step S11 in the second embodiment (FIG. 9).

In step S14, the number of activations Npup, the number of abnormality detections Ndet_err, and the number of diagnoses Ndiag stored in the counter circuit memory 47 are cleared to their initial values, and the process proceeds to step S15.

In step S15, after the power control IC 100 is stopped, the process returns to step S1 and the processes from step S1 onwards are repeated.

In step S3, if the internal characteristic is less than or equal to the abnormality determination threshold voltage Vth_diag, it is determined that the internal characteristic is abnormal (NG), and the process proceeds to step S10.

In step S10, the diagnostic result edge detection unit 41 detects the rising edge of the voltage level of the diagnostic result signal line 106 from Low to High, thereby incrementing the number of abnormality detections Ndet_err by one, and storing it in the counter circuit memory 47. The process then proceeds to step S4.

In step S9, the number of activations Npup stored in the counter circuit memory 47 is counted up, and the process proceeds to step S11. The processing in step S11 and step S12 is similar to the processing in step S8 and step S9 of the second embodiment (FIG. 9).

As explained above, the power supply control IC 100 of this embodiment determines the abnormality detection frequency by restarting a fixed number of times at startup, and determines that it is a sign of failure when the abnormality detection frequency is equal to or higher than the sign determination threshold. be able to.

With reference to FIGS. 11 to 14, a power supply control IC and its diagnosis method according to a fourth embodiment of the present invention will be described.

In this embodiment, a characteristic in which an abnormality has been detected is corrected according to the abnormality detection frequency, and whether or not the corrected characteristic has been improved is detected based on the abnormality detection frequency, and furthermore, when the characteristic variation over time is equal to or greater than a predetermined value. A configuration and an operation example that can set a flag when this occurs will be described. Note that the following description will focus on the points that are different from the second embodiment.

FIG. 11 is a block diagram showing the configuration of the power supply control IC 100 of this embodiment. Focusing on the difference from Example 2 (FIG. 7), the power supply control IC 100 of this example further includes a characteristic control circuit 60 that controls the characteristic value of the internal characteristic based on the abnormality detection frequency Rdet_err.

To give an example of the characteristic control circuit 60 in this embodiment, a configuration as shown in FIG. 12 can be considered. The characteristic control circuit 60 shown in FIG. 12 includes a characteristic adjustment circuit 61 that determines the correction amount of the internal characteristic based on the abnormality detection frequency Rdet_err, and a characteristic value of the internal characteristic that is fixed based on the correction signal output from the characteristic adjustment circuit 61. It includes a correction circuit 63 that can perform correction with correction resolution, and a characteristic control circuit memory 62 that stores the correction signal calculated by the characteristic adjustment circuit 61. An example of a circuit installed in the characteristic adjustment circuit 61 is an up/down counter circuit.

The up/down counter circuit counts up when the voltage level of the correction request signal line 116 transitions from Low to High while High is input to the correction polarity signal line 117, and when Low is input to the correction polarity signal line 117. When the voltage level of the correction request signal line 116 changes from Low to High in this state, it counts down and outputs the count value to the characteristic control circuit memory 62 as a correction amount. The correction circuit 63 reads the correction amount stored in the characteristic control circuit memory 62 at startup, and performs correction according to the correction amount.

Here, FIG. 13 shows the operation of correcting the characteristic value of the output voltage of the power supply circuit 10 based on the abnormality detection frequency Rdet_err. It is assumed that the correction circuit 63 can perform correction with a correction resolution Dcomp.

At time t1, when the voltage value approaches the low voltage threshold due to changes in characteristics over time, the abnormality detection frequency Rdet_err increases, and when it exceeds the sign determination threshold, the counter circuit 40 determines that it is a sign of failure.

Since the abnormality diagnosed as a sign of failure is a low voltage abnormality in the output voltage, the counter circuit 40 outputs High to the correction polarity signal line 117 and High to the correction request signal line 116, and the characteristic adjustment circuit 61 outputs the correction amount. is counted up, and the correction amount is set to 1 and stored in the characteristic control circuit memory 62. The correction circuit 63 reads the correction amount 1 from the characteristic control circuit memory 62 and applies the correction resolution Dcomp.

At time t2, when the counter circuit 40 determines that there is a sign of a failure, the characteristic adjustment circuit 61 counts up the correction amount and stores the correction amount as 2 in the characteristic control circuit memory 62. The correction circuit 63 reads the correction amount 2 from the characteristic control circuit memory 62 and applies 2 (correction amount)×correction resolution Dcomp.

Further, when the already-corrected amount reaches the maximum correction value Dmax_comp, the characteristic control circuit 60 sets the voltage level of the maximum correction signal line 112 to High, and the counter circuit memory 47 sets the voltage level of the maximum correction signal line 112 (High). or Low).

Furthermore, if a mechanism is provided in which any part in the ECU detects that High is output to the maximum correction signal line 112, the power supply control IC 100 and the parts equipped with the power supply control IC 100 in the vehicle will need to be replaced. It is possible to notify the car user, etc. of this fact.

Although FIG. 13 shows an example of a low voltage abnormality, if the abnormality diagnosed as a sign of failure is an overvoltage abnormality, the counter circuit 40 outputs Low to the correction polarity signal line 117 and High to the correction request signal line 116. The characteristic adjustment circuit 61 operates to count down the amount of correction, and performs correction to lower the output voltage.

An example of the startup process of the power control IC 100 of this embodiment (FIG. 11) will be described using the flowchart of FIG. 14.

The flowchart shown in FIG. 14 shows that the power supply circuit 10 is restarted after correcting the internal characteristics determined to be a sign of failure in the start-up process, and the power supply circuit 10 is restarted unless the abnormality detection frequency Rdet_err is improved to less than the sign judgment threshold Rth_preerr. This is a flow of a startup process in which the maximum correction signal is set to High when the correction amount Dcomp reaches the maximum correction value Dmax_comp without being made effective.

Note that the following description will focus on the differences from the processing in Example 3 (FIG. 10).

In step S2, the correction amount Dcomp in the characteristic control circuit memory 62 is applied, and the process proceeds to step S3.

The processing from step S3, step S5, and step S7 to END is the same as the processing from step S3 to END in the third embodiment (FIG. 10).

Furthermore, the processes in steps S6, S4, S16, and S17 are similar to the processes in steps S9 to S12 of the third embodiment (FIG. 10).

In step S10, a correction amount Dcomp to be applied at the next restart is calculated for the characteristic for which an abnormality was detected in the startup diagnosis, and the process proceeds to step S11.

In step S11, the correction amount Dcomp is stored in the characteristic control circuit memory 62, and the process proceeds to step S12.

In step S12, the correction amount Dcomp and the maximum correction value Dmax_comp are compared. If the correction amount Dcomp has reached the maximum correction value Dmax_comp (=Dmax_comp), the process advances to step S13. If the correction amount Dcomp has not reached the maximum correction value Dmax_comp (<Dmax_comp), the process advances to step S16.

In step S13, the voltage level of the maximum correction signal line 112 is switched from Low to High. The counter circuit memory 47 stores the maximum correction signal at the rise of the voltage level of the maximum correction signal line 112, and the process proceeds to step S14.

In step S14, the power supply circuit 10 is enabled, and the process proceeds to step S15.

In step S15, the user is notified of the maximum correction signal and the presence of a sign of failure, and the process proceeds to step S18.

In step S18, after the power control IC 100 is stopped, the process returns to step S1 and the processes from step S1 onwards are repeated.

As described above, the power supply control IC 100 of the present embodiment corrects the characteristics in which an abnormality has been detected according to the abnormality detection frequency, and detects whether or not the corrected characteristics have been improved based on the abnormality detection frequency. Further, a flag is set if the amount of variation in characteristics over time exceeds a predetermined value.

With reference to FIGS. 15 and 16, a power supply control IC and its diagnosis method according to a fifth embodiment of the present invention will be described.

In this embodiment, startup diagnosis is performed after controlling the internal characteristics of the power supply control IC during startup diagnosis, and after the startup diagnosis, the internal characteristics are returned to the state before startup diagnosis, compared to a case where no control is performed during startup diagnosis. A configuration and operation example that can make it easier to detect an abnormality before a failure of the power supply control IC will be described. Note that the following description will focus on the points that are different from the fourth embodiment.

FIG. 15 is a block diagram showing the configuration of the power supply control IC 100 of this embodiment. Focusing on the difference from the fourth embodiment (FIG. 11), the characteristic control circuit 60 has a configuration in which the correction request signal line 116 is connected to the diagnostic signal line 105, and further controls the internal characteristics so as to approach the diagnostic threshold during the diagnostic period. A characteristic control circuit 60 is provided.

To give an example of the configuration of the characteristic control circuit 60 in this embodiment, in the configuration based on FIG. A conceivable configuration includes a correction circuit 63 that performs control so as to approach the diagnostic threshold according to a control amount within the range, and a characteristic control circuit memory 62 that stores the control amount.

An example of the startup process of the power supply control IC 100 of this embodiment (FIG. 15) will be described using the flowchart of FIG. 16.

The flowchart shown in FIG. 16 is a flow of a startup process in which the internal characteristics are controlled to be close to the diagnostic threshold only during the startup diagnosis period, thereby making it easier to detect abnormalities compared to a case where no control is performed.

Note that the following description will focus on the differences from the processing in Example 4 (FIG. 14).

In step S2, the internal characteristics inside the power supply control IC 100 are controlled to approach the diagnostic threshold before startup diagnosis, and the process proceeds to step S3.

In step S3, the startup diagnostic circuit 31 compares the internal characteristics and the abnormality determination threshold voltage Vth_diag. If the internal characteristics are larger than the abnormality determination threshold voltage Vth_diag and it is determined that the internal characteristics are normal (OK), the process proceeds to step S4.

In step S4, the characteristics controlled after startup diagnosis are returned to the characteristics before control, and the process proceeds to step S5.

The processing from step S5 to END is similar to the processing from step S7 to END in the fourth embodiment (FIG. 14).

On the other hand, in step S3, if the internal characteristic is equal to or lower than the abnormality determination threshold voltage Vth_diag, it is determined that the internal characteristic is abnormal (NG), and the process proceeds to step S8.

In step S8, the characteristics controlled after the start-up diagnosis are returned to the characteristics before the control, and the process proceeds to step S9.

In step S9, by detecting the rising edge of the voltage level of the diagnostic result signal line 106 from Low to High by the diagnostic result edge detection unit 41, the number of abnormality detections Ndet_err is incremented by one and stored in the counter circuit memory 47. The process then proceeds to step S10.

The processing in step S10 and step S11 is similar to the processing in step S16 and step S17 of the fourth embodiment (FIG. 14).

In step S5, if the abnormality detection frequency Rdet_err is greater than or equal to the sign determination threshold Rth_preerr (≧Rth_preerr), the process proceeds to step S12.

In step S12, after the power control IC 100 is stopped, the process returns to step S1 and the processes from step S1 onwards are repeated.

As explained above, the power supply control IC 100 of this embodiment performs the startup diagnosis after controlling the internal characteristics to approach the diagnosis threshold only during the startup diagnosis period, so that an abnormality occurs before the power supply control IC fails during the startup diagnosis. By making it easier to detect and returning the internal characteristics to the state before the control after the startup diagnosis, it is possible to operate with a margin for the control amount relative to the diagnostic threshold.

With reference to FIGS. 17 and 18, a power supply control IC and its diagnosis method according to a sixth embodiment of the present invention will be described.

In this embodiment, setting information of past setting terminals is saved in memory, and by comparing the setting terminal settings detected at startup with the settings of the past setting terminals, the validity of the terminal settings detected at startup is determined. A configuration and operation example that can distinguish between misdiagnosis due to an accidental abnormality caused by the environment and intentionally changed settings by rereading the setting information by restarting the system if the judgment results do not match. I will explain about it. Note that the following description will focus on the points that are different from Example 2 (FIG. 7).

FIG. 17 is a block diagram showing the configuration of the power supply control IC 100 of this embodiment. Focusing on the difference from Example 2 (FIG. 7), the power control IC 100 of this example further adjusts the predetermined settings (hereinafter referred to as , an internal setting), and a memory 70 for storing past terminal settings Dpre_set set at past startups, and a comparison circuit 32 in the startup diagnostic circuit 31 detects the settings detected at startup. It is characterized by comparing the terminal setting Dset and the past terminal setting Dpre_set.

The comparison circuit 32 compares the past terminal setting Dpre_set and the setting terminal Dset read in the startup process, and if they match, reflects the contents of the terminal setting Dset in the internal settings. If they do not match, the number of abnormality detections Ndet_err is counted up, and the startup diagnostic circuit 31 outputs High to the restart signal line 101. When the number of abnormality detections Ndet_err reaches the startup determination threshold number Nth_pup, it is determined that there is no misdiagnosis due to environmental factors, and the terminal setting Dset is reflected in the power supply control IC 100.

An example of the startup process of the power supply control IC 100 of this embodiment (FIG. 17) will be described using the flowchart of FIG. 18.

The flowchart shown in FIG. 18 is a flow of a startup process in which an abnormality in the terminal setting Dset is detected during startup diagnosis and restart is performed.

Note that the following description will focus on the points that are different from the processing in Example 2 (FIG. 9).

In step S2, the terminal setting Dset is detected from the potential of the setting terminal 115, and the process proceeds to step S3.

In step S3, the number of abnormality detections Ndet_err is read from the memory 70. If the number of abnormality detections Ndet_err is less than the activation determination threshold number Nth_pup (<Nth_pup), the process advances to step S4. When the number of abnormality detections Ndet_err reaches the activation determination threshold number Nth_pup (=Nth_pup), the process advances to step S5.

In step S4, the comparison circuit 32 compares the terminal setting Dset and the past terminal setting Dpre_set. If they match, the process advances to step S5. If they do not match, the process advances to step S7.

The processing from step S5 to END is the same as the processing from step S4 to END in the second embodiment (FIG. 9).

In step S7, the number of abnormality detections Ndet_err is counted up and stored in the memory 70, and the process proceeds to step S8.

The processing in step S8 and step S9 is similar to the processing in step S8 and step S9 of the second embodiment (FIG. 9).

In this embodiment, the past terminal setting Dpre_set is saved in the memory 70, and the validity of the detected setting terminal is checked by comparing the terminal setting Dset detected at startup with the past terminal setting Dpre_set in the memory 70. Although an example in which the determination can be made has been shown, configurations other than this configuration are also possible. For example, a configuration may be considered in which the value of the nonvolatile memory is used as a comparison target, and the validity of the detected setting terminal is determined by comparing it with the expected value of the setting terminal written in advance at the time of manufacturing.

As explained above, the power supply control IC 100 of this embodiment stores past terminal settings in memory and determines the validity of the terminal settings by comparing the terminal settings detected at startup with the past terminal settings. If the judgment results do not match, the configuration information can be reread through restart processing, and if the startup judgment thresholds do not match, it is determined that the terminal settings have been intentionally changed and the terminal settings are controlled by the power source. It can be reflected on the IC.

With reference to FIGS. 19 to 21, a power supply control IC and its diagnosis method according to a seventh embodiment of the present invention will be described.

In this embodiment, the configuration and operation example are such that the process to be executed and the number of times to be executed can be selected when executing the reboot process, so that an optimal reboot can be carried out while suppressing the time required for the reboot process. I will explain about it. Note that the following description will focus on the points that are different from Example 6 (FIG. 17).

FIG. 19 is a block diagram showing the configuration of the power supply control IC 100 of this embodiment. Focusing on the differences from Example 6 (FIG. 17), the power supply control IC 100 of this example further includes a setting pin readout process and a diagnostic process that are performed in the restart process, and a restart process that can set the number of times each is performed. A setting circuit 50 is provided.

The restart setting circuit 50 is connected to the diagnosis result signal line 106 of the startup diagnosis circuit 31, and sets the startup process and stop process to be performed at the time of restart according to the diagnosis result. Furthermore, by connecting the restart setting circuit 50 to the startup circuit 20 through the re-diagnosis signal line 113 and the re-setting pin readout signal line 114, it is possible to control the process to be re-implemented.

The counter circuit 40 stores the number of readings of the setting terminal and the number of diagnostics in a memory, and outputs them to the restart setting circuit 50 at startup. Note that the process can be set not to be executed by setting the number of times of execution to 0.

To give an example of the restart setting circuit 50 in this embodiment, a configuration as shown in FIG. 20 can be considered. The restart setting circuit 50 shown in FIG. 20 includes a restart setting circuit memory 51 in which a target number of diagnosis Ndiag_target and a target terminal setting read number Npinread_target are stored, a number of times of diagnosis Ndiag output from the counter circuit 40, and a counter circuit A comparison circuit 52a that compares the target diagnosis number Ndiag_target stored in the memory 47 compares the terminal setting read number Npinread outputted from the counter circuit 40 and the target terminal setting read number Npinread_target stored in the counter circuit memory 47. and a comparison circuit 52b.

An example of the restart process of the power supply control IC 100 of this embodiment (FIG. 19) will be described using the flowchart of FIG. 21.

The flowchart shown in FIG. 21 is a flowchart of a startup process in which only the flow for which an abnormality is detected by reading the setting terminal 115 and startup diagnosis at startup is re-implemented.

Note that the following description will focus on the points that are different from the processing in Example 6 (FIG. 18).

In step S4, the terminal setting read count Npinread is counted up. The terminal setting Dset and the past terminal setting Dpre_set are compared, and if they match, the process advances to step S6. If they do not match, the process advances to step S5.

In step S5, the number of abnormality detections Ndet_err is counted up and stored in the memory 70, and the process proceeds to step S6.

In step S6, the number of times of diagnosis Ndiag and the target number of times of diagnosis Ndiag_target are read and compared. If the number of diagnoses Ndiag is less than the target number of diagnoses Ndiag_target (<Ndiag_target), the process advances to step S7. If the number of diagnoses Ndiag has reached the target number of diagnoses Ndiag_target (=Ndiag_target), the process advances to step S9.

In step S7, the startup diagnostic circuit 31 compares the internal characteristics and the abnormality determination threshold voltage Vth_diag. If the internal characteristics are larger than the abnormality determination threshold voltage Vth_diag and it is determined that the internal characteristics are normal (OK), the process proceeds to step S9. If the internal characteristic is less than or equal to the abnormality determination threshold voltage Vth_diag, it is determined that the internal characteristic is abnormal (NG), and the process proceeds to step S8.

In step S8, by detecting the rising edge of the voltage level of the diagnostic result signal line 106 from Low to High by the diagnostic result edge detection unit 41, the number of abnormality detections Ndet_err is counted up by one and stored in the counter circuit memory 47. The process then proceeds to step S9.

In step S9, if the number of times of diagnosis Ndiag is less than the target number of times of diagnosis Ndiag_target, High is output to the re-diagnosis signal line 113, and if the number of terminal setting read times Npinread is less than the target number of terminal setting read times Npinread_target, a reset pin read signal is output. High is output to the line 114, and the process advances to step S14. On the other hand, if the number of times of diagnosis Ndiag has reached the target number of times of diagnosis Ndiag_target and the number of terminal setting read times Npinread has reached the target number of terminal setting read times Npinread_target, the process advances to step S10.

In step S14, the terminal setting read count Npinread and the target terminal setting read count Npinread_target are read and compared. If the terminal setting readout count Npinread is less than the target terminal setting readout count Npinread_target (<Npinread_target), the process advances to step S3. On the other hand, if the terminal setting readout number Npinread has reached the target terminal setting readout number Npinread_target (=Npinread_target), the process advances to step S6.

In step S10, if the number of abnormality detections Ndet_err is less than the activation determination threshold number Nth_pup (<Nth_pup), the process advances to step S11. When the number of abnormality detections Ndet_err reaches the activation determination threshold number Nth_pup (=Nth_pup), the process advances to step S15.

The processing from step S11 to END is the same as the processing from step S5 to END in the sixth embodiment (FIG. 18).

The process in step S15 is similar to the process in step S9 of the sixth embodiment (FIG. 18).

In this embodiment, a restart setting circuit is installed inside the power supply control IC 100, and by inputting the diagnosis result of the diagnostic circuit, it is possible to set the startup process and stop process to be executed at restart according to the startup diagnosis result. Although a possible example has been shown, configurations other than this configuration are also possible.

For example, if the configuration is such that restart settings are input via a communication interface circuit, subsequent restart processing can be set in response to an abnormality detected during operation of a circuit (for example, a CPU) outside the power supply control IC 100. can. Alternatively, the restart setting may be set in advance at the time of manufacturing by storing the process to be executed in the restart process and the number of execution times of the process in a non-volatile memory.

As explained above, the power supply control IC 100 of the present embodiment allows the user to select the process to be executed and the number of times it is executed when executing the reboot process, thereby reducing the time required for the reboot process and optimizing the reboot process. can be carried out.

As explained in each embodiment, by using the power control IC according to the present invention, it is possible to notify the user in the form of a parts replacement notification or the like before the power control IC fails, and it is possible to notify the user before the failure of the power control IC. In comparison, it can be used for almost the same lifespan. Further, since the power control IC can be used for a long time by detecting signs without using an ECU housing with high heat dissipation as in Patent Document 1, the operating time of the ECU housing can be extended and costs can be reduced. Furthermore, by combining an ECU housing with high heat dissipation and predictive detection, the operating time can be further extended. In addition, by installing a mechanism to correct for characteristics where the frequency of abnormality detection has increased, it is possible to further extend the period until parts are replaced, and it is also possible to reduce costs by reducing the number of replacements and inspection frequency. .

Note that the present invention is not limited to the above-described embodiments, and includes various modifications. For example, the embodiments described above are described in detail to explain the present invention in an easy-to-understand manner, and the present invention is not necessarily limited to having all the configurations described. Furthermore, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Further, it is possible to add, delete, or replace a part of the configuration of each embodiment with other configurations.

DESCRIPTION OF SYMBOLS 1... ECU, 2... Ignition switch (IG-SW), 10... Power supply circuit, 11, 24... Switch element, 12a, 12b... Linear regulator, 13... Reference voltage generation part, 14... MOSFET, 15... Error amplifier, 16 , 17... feedback resistor, 20... starting circuit, 21... starting signal detection section, 22... diagnostic signal generation section, 23... control signal generation section, 25a, 25b, 25c... NOT circuit, 26a, 26b, 26c... delay circuit, 27a, 27b...AND circuit, 30...Internal processing unit, 31...Start-up diagnostic circuit, 32...Abnormality determination unit (comparison circuit), 33...Diagnostic control unit, 34...Filter circuit, 40...Counter circuit, 41...Diagnosis result edge Detection unit, 42...Diagnostic signal edge detection unit, 44...Abnormality detection counter circuit, 45...Diagnostic counter circuit, 46...Abnormality detection frequency determination unit, 47...Memory for counter circuit, 50...Restart setting circuit, 51...Restart Setting circuit memory, 52a, 52b...comparison circuit, 60...characteristic control circuit, 61...characteristic adjustment circuit, 62...characteristic control circuit memory, 63...correction circuit, 70...memory, 100...power supply control IC, 101...return Start signal line, 102...Start signal line, 103...Power supply line, 104...Control signal line, 105...Diagnosis signal line, 106...Diagnosis result signal line, 107...Internal voltage line, 108...Output voltage line, 109...Communication signal Line, 110... Stop signal line, 111... Signal line to be diagnosed, 112... Maximum correction signal line, 113... Re-diagnosis signal line, 114... Resetting pin read signal line, 115... Setting terminal, 116... Correction request signal line, 117...Correction polarity signal line, 118...Diagnosis count signal line, 119...Terminal setting readout count signal line, 200...CPU, Vpower...Power supply voltage, Vth_pup...Start signal determination threshold voltage, Voperate_min...Minimum operating voltage, Voutput...Output voltage , Vref...Reference voltage, Vfb...Feedback voltage, Internal...Internal voltage, Vth_diag...Low voltage abnormality determination threshold voltage, Srepup...Restart signal, Spup...Start signal, Spdown...Stop signal, Spower_en...Control signal, Sdiff...Difference signal , Sdiag...Diagnosis signal, Smax_comp...Maximum correction signal, Ndiag...Number of diagnosis, Ndet_err...Number of abnormality detection, Nth_pup...Number of startup judgment thresholds, Npup...Number of startups, Nmax_pup...Maximum number of startups, Nerr_set...Number of abnormal terminal settings, Npinread... Number of terminal settings read, Ndiag_target...Target number of diagnosis, Npinread_target...Target number of terminal settings read, Rdet_err...Abnormality detection frequency, Rth_pup...Startup judgment threshold frequency, Rth_preerr...Predictive judgment threshold, Dset...Terminal setting, Dpre_set...Past terminal setting, Dcomp ...Correction resolution (correction amount), Dmax_comp...Maximum correction value.

Claims (12)

1. a power supply circuit that generates at least one voltage from a power supply voltage;
   a start pin for starting the power supply circuit;
   a startup circuit that performs restart processing of the power supply circuit based on a restart signal when a predetermined voltage is input to the startup pin;
   A power supply control IC.
2. The power supply control IC according to claim 1,
   comprising a diagnostic circuit that performs a self-diagnosis of the power supply control IC when the power supply circuit starts up;
   A power supply control IC that transmits a restart signal to the startup circuit when detecting a startup abnormality in the power supply circuit or an abnormality detected by the diagnostic circuit.
3. The power supply control IC according to claim 2,
   comprising a counter circuit that counts the number of abnormality detections in the diagnostic circuit,
   The counter circuit calculates an abnormality detection frequency that is a ratio of the number of abnormality detections to the number of diagnoses,
   retaining the number of times of diagnosis and the number of times of abnormality detection regardless of the operation of the power supply circuit;
   A power supply control IC that determines a sign of failure or a failure when the abnormality detection frequency is greater than a predetermined value.
4. The power supply control IC according to claim 3,
   A power supply control IC that repeatedly restarts when an abnormality occurs after the last startup until the abnormality is no longer detected.
5. The power supply control IC according to claim 1,
   A power supply control IC that performs the restart process a predetermined number of times.
6. The power supply control IC according to claim 3,
   The counter circuit is a power supply control IC that calculates the abnormality detection frequency from the number of activations of three or more times.
7. The power supply control IC according to claim 3,
   A power supply control IC having a notification function for notifying an external device when any of the restart signal, the startup abnormality, the abnormality detected by the diagnostic circuit, the sign of failure, or the failure is detected.
8. The power supply control IC according to claim 3,
   a characteristic control circuit that calculates a correction amount when the abnormality detection frequency exceeds the predetermined value;
   a storage unit that stores the correction amount;
   a correction circuit that corrects a characteristic value in which an abnormality has been detected according to the correction amount,
   The counter circuit determines that the characteristic value in which the abnormality is detected has been corrected when the abnormality detection frequency after applying the correction amount is smaller than the abnormality detection frequency before applying the correction amount. I.C.
9. The power supply control IC according to claim 3,
   Equipped with a control circuit that controls predetermined characteristic values,
   The control circuit is a power supply control IC that controls the predetermined characteristic value during a start-up diagnosis period so that abnormalities are more likely to occur.
10. The power supply control IC according to claim 3,
    a setting terminal that determines a predetermined setting value according to the voltage value input at startup;
    a memory for storing past setting values of the setting terminal;
    a comparison circuit that compares the predetermined set value and the past set value,
    The memory retains the stored value regardless of the operation of the power supply circuit,
    The diagnostic circuit is a power supply control IC that sends a restart signal to the startup circuit according to the comparison result of the comparison circuit.
11. The power supply control IC according to claim 1,
    comprising a restart setting circuit that can set the number of executions for each process of the restart process,
    A power supply control IC that executes a process the set number of times set for each process when executing the restart process.
12. (a) inputting a startup signal for the power supply control IC;
    (b) counting up the number of diagnosis by one and storing it in memory;
    (c) performing a startup diagnosis of the power supply control IC;
    (d) in the step (c), when an abnormality is detected, counting up the number of abnormality detections by one and storing it in the memory;
    (e) reading the number of diagnoses and the number of abnormality detections from the memory and calculating the frequency of abnormality detection;
    (f) comparing the abnormality detection frequency calculated in step (e) with a predetermined threshold;
    has
    In step (f), if the abnormality detection frequency is less than the predetermined threshold, it is determined to be normal and a restart signal for the power supply control IC is output, and if the abnormality detection frequency is greater than or equal to the predetermined threshold, A method for diagnosing a power supply control IC that determines that it is a sign of failure and outputs a notification of the sign of failure.

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