WO2024092503A1

WO2024092503A1 - Imaging device and imaging system

Info

Publication number: WO2024092503A1
Application number: PCT/CN2022/128974
Authority: WO
Inventors: Takafumi Kishi
Original assignee: Guangdong Oppo Mobile Telecommunications Corp., Ltd.
Priority date: 2022-11-01
Filing date: 2022-11-01
Publication date: 2024-05-10

Abstract

An imaging device (2,2a) includes: a pixel array (PA) in which plural pixels are arrayed to form plural rows and plural columns, the pixel array (PA) including a first pixel group (PG1) and a second pixel group (PG2), the first pixel group (PG1) including two or more pixels each corresponding to a first color among the plural pixels, the second pixel group (PG2) including two or more pixels each corresponding to a second color among the plural pixels; and a control circuit (CC) configured to perform a readout scan to, while selecting the plural rows sequentially, read out a pixel signal from a pixel of each column included in a selected row. The control circuit (CC) performs a first readout scan to read out pixel signals from pixels of the first pixel group (PG1) and a second readout scan to read out pixel signals from pixels of the first pixel group (PG1) and the second pixel group (PG2) in a one-frame period.

Description

IMAGING DEVICE AND IMAGING SYSTEM

[Technical Field]

The present invention relates to an imaging device and an imaging system.

[Background Art]

In an imaging device including a pixel array, plural pixels are arranged to configure plural rows and plural columns in the pixel array. In the imaging device, each of the pixels generates a pixel signal corresponding to an object image formed by the pixel array, and a control circuit performs readout scan for reading out pixel signals in units of row while sequentially selecting plural rows.

[Disclosure of Invention]

[Problem to be Solved by the Invention]

In the imaging device, in a case in which plural pixels in the pixel array correspond to plural colors, an easiness of saturation of the pixel signal tends to be different among the pixels of plural colors. On the other hand, by performing plural times of readout scan for a pixel of a color that can be easily saturated while performing one time of readout scan for a pixel of a color that is hardly saturated in one frame period, a dynamic range of a pixel signal of each color can be expanded. When a time for the readout scan is kept constant in plural times of readout scan, an operational time for the readout scan in one frame period is prolonged, and power consumption of the control circuit tends to be increased.

The present invention has been made in view of such a situation, and provides an imaging device and an imaging system that can reduce power consumption.

Solution to Problem

[Means for Solving Problem]

To solve the problem described above and achieve an aim of the present disclosure, an imaging device according to one aspect of the present disclosure includes a pixel array in which plural pixels are arrayed to form plural rows and plural columns, the pixel array including a first pixel group and a second pixel group, the first pixel group including two or more pixels each corresponding to a first color among the plural pixels, and the second pixel group including two or more pixels each corresponding to a second color among the plural pixels; and a control circuit configured to perform a readout scan to, while selecting the plural rows sequentially, read out a pixel signal from a pixel of each column included in a selected row, wherein the control circuit performs a first readout scan to read out pixel signals from pixels of the first pixel group and performs a second readout scan to read out pixel signals from pixels of the first pixel group and the second pixel group in a one-frame period.

[Effect of the Invention]

According to one aspect of the present invention, power consumption can be reduced.

[Brief Description of Drawings]

FIG. 1 is a block diagram illustrating a configuration of an imaging system including an imaging device according to an embodiment.

FIG. 2 is a circuit diagram illustrating a configuration of an image sensor according to the embodiment.

FIG. 3 is a timing chart illustrating an operation of a control circuit according to the embodiment.

FIG. 4 is a circuit diagram illustrating a configuration of a pixel according to the embodiment.

FIG. 5 is a waveform diagram illustrating an operation of the pixel according to the embodiment.

FIG. 6 is a cross-sectional view illustrating a configuration of the pixel according to the embodiment.

FIG. 7 is a diagram illustrating a transmission characteristic of a color filter according to the embodiment.

FIG. 8 is a timing chart illustrating a configuration of a pixel array and an operation of the control circuit according to the embodiment.

FIG. 9 is a timing chart illustrating a configuration of a pixel array and an operation of a control circuit according to a first modification of the embodiment.

FIG. 10 is a timing chart illustrating a configuration of a pixel array and an operation of a control circuit according to a second modification of the embodiment.

FIG. 11 is a timing chart illustrating a configuration of a pixel array and an operation of a control circuit according to a third modification of the embodiment.

FIG. 12 is a timing chart illustrating a configuration of a pixel array and an operation of a control circuit according to a fourth modification of the embodiment.

FIG. 13 is a circuit diagram illustrating a configuration of a pixel unit according to the fourth modification of the embodiment.

FIG. 14 is a waveform diagram illustrating an operation of the pixel unit according to the fourth modification of the embodiment.

FIG. 15 is a timing chart illustrating a configuration of a pixel array and an operation of a control circuit according to a fifth modification of the embodiment.

FIG. 16 is a timing chart illustrating a configuration of a pixel array and an operation of a control circuit according to a sixth modification of the embodiment.

FIG. 17 is a timing chart illustrating an operation of a control circuit according to a seventh modification of the embodiment.

FIG. 18 is a diagram illustrating processing of determining pixel saturation according to the seventh modification of the embodiment.

FIG. 19 is a circuit diagram illustrating a configuration of a pixel according to the seventh modification of the embodiment.

FIG. 20 is a diagram illustrating a configuration of a frame image according to an eighth modification of the embodiment.

FIG. 21 is a diagram illustrating an operation of an imaging device according to a ninth modification of the embodiment.

[Embodiment (s) of Carrying Out the Invention]

Hereinafter, an imaging device according to embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(Embodiment)

The imaging device according to the embodiment includes a pixel array in which plural pixels are arranged to configure plural rows and plural columns, and a control circuit performs readout scan for reading out pixel signals in units of row while sequentially selecting plural rows. The imaging device is contrived to reduce power consumption for the readout scan.

For example, an imaging system 1 including an imaging device 2 may be configured as illustrated in FIG. 1. FIG. 1 is a block diagram illustrating a configuration of the imaging system 1 including the imaging device 2. FIG. 1 exemplifies the configuration in a case in which the imaging system 1 includes an imaging device 2a in addition to the imaging device 2. The imaging system 1 may be a portable electronic device. The portable electronic device may be, for example, a smartphone, a tablet, a video camera, or an electronic still camera.

The imaging device 2 includes an optical system 21, an image sensor 22, a signal processing unit 23, and a controller 24. The optical system 21 is disposed on an optical axis PX of the image sensor 22, and forms an object image on an imaging surface of the image sensor 22. The image sensor 22 generates an image signal corresponding to the object image to be supplied to the signal processing unit 23. The signal processing unit 23 performs predetermined image processing on the image signal to generate image data, and supplies the image data to the controller 24. The controller 24 performs predetermined processing using the image data.

Similarly, the imaging device 2a includes an optical system 21a, an image sensor 22a, a signal processing unit 23a, and a controller 24a. The optical system 21a is disposed on an optical axis PXa of the image sensor 22a, and forms an object image on an imaging surface of the image sensor 22a. The image sensor 22a generates an image signal corresponding to the object image to be supplied to the signal processing unit 23a. The signal processing unit 23a performs predetermined image processing on the image signal to generate image data, and supplies the image data to the controller 24a. The controller 24a performs predetermined processing using the image data.

In the imaging devices 2 and 2a, configurations of the

optical systems

21 and 21a may be different from each other. An angle of view of the optical system 21a may be wider than an angle of view of the optical system 21. For example, the optical system 21 may be an optical system for standard. The optical system 21a may be an optical system for wide field of view (for example, a wide type or an ultra-wide type) .

In the imaging devices 2 and 2a, each of the

image sensors

22 and 22a, each of the

signal processing units

23 and 23a, and each of the

controllers

24 and 24a may have similar configuration.

As illustrated in FIG. 2, the

image sensors

22 and 22a each include a pixel array PA and a control circuit CC. FIG. 2 is a circuit diagram illustrating the configuration of the image sensor 22. FIG. 2 exemplifies the configuration of the image sensor 22, but the image sensor 22a also has similar configuration.

The pixel array PA is disposed on the imaging surface of the image sensor 22. In the pixel array PA, plural pixels P (1, 1) to P (8, 8) may be two-dimensionally arranged. The pixels P (1, 1) to P (8, 8) may also be arranged to configure plural rows and plural columns. FIG. 2 exemplifies a configuration in which 8 rows and 8 columns of the pixels P (1, 1) to P (8, 8) are arranged in the pixel array PA. Hereinafter, a direction along the row is referred to as a row direction, and a direction along the column is referred to as a column direction.

The pixel array PA corresponds to plural colors. The pixel array PA includes a pixel group PG1 and a pixel group PG2. The pixel group PG1 includes two or more pixels P1 corresponding to a first color among the pixels P (1, 1) to P (8, 8) . The pixel group PG2 includes two or more pixels P2 corresponding to a second color among the pixels P (1, 1) to P (8, 8) . The second color is a color different from the first color.

In the pixel array PA, a first column and a second column are alternatively arranged along a row direction. Here, the first column may be defined as odd-numbered column when being counted from left side in FIG. 2. The second column may be defined as even-numbered column when being counted from left side in FIG. 2. In the first column, a pixel of the pixel group PG2 and a pixel of the pixel group PG1 are alternatively arranged along a column direction. In the second column, the pixels of the pixel group PG2 are arranged along the column direction.

An easiness of saturation of the pixel signal tends to be different between the pixel group PG1 and the pixel group PG2. An easiness of light of the first color to saturate a pixel of the pixel group PG1 is larger than an easiness of light of the second color to saturate a pixel of the pixel group PG2.

The first color corresponds to light in a first wavelength band. The second color corresponds to light in a second wavelength band. The first wavelength band may include the second wavelength band. Each of the pixels P1 in the pixel group PG1 includes a first color filter. Each of the pixel P2 in the pixel group PG2 includes a second color filter. The first color filer is transmittable with more amount of light than the second color filter.

For example, a transmission wavelength band of the first color filter may include a transmission wavelength band of the second color filter. With this property, amount of light transmitted by the first color filter may be more than that transmitted by the second color filter. The first color may be white. The second color may be any of red, green, and blue.

Hereinafter, in a case in which the pixel P1 in the pixel group PG1 and the pixel P2 in the pixel group PG2 are not distinguished from each other, they are each simply referred to as a pixel P in some cases.

In a case in which the image sensor 22 performs imaging with plural colors using the pixel array PA, it is preferable that the pixels P1 in the pixel group PG1 be uniformly distributed in the pixel array PA, and the pixels P2 in the pixel group PG2 be uniformly distributed in the pixel array PA. As illustrated in FIG. 2 by hatching with oblique lines, the pixels P1 are disposed in part of the rows and part of the columns. The pixels P2 are disposed at positions other than those of the pixels P1 in the pixel array PA. In the example of FIG. 2, the pixel group PG1 includes the pixels P1 disposed at positions of even-numbered rows and odd-numbered columns, and the pixel group PG2 includes the pixels P2 disposed at the other positions.

Each of the pixels P performs photoelectric conversion, and performs a charge storage operation for storing electric charge corresponding to light. The electric charge of each of the pixels P is reset. When the reset is canceled, each of the pixels P starts the charge storage operation. A pixel signal corresponding to a stored charge amount is read out from each of the pixels P. The electric charge of each of the pixels P is reset again, and when the reset is canceled, each pixel P starts the charge storage operation. In each of the pixels P, a period from a timing when the reset is canceled to a timing when readout is performed is a charge storage period. In the charge storage period, the charge storage operation is performed.

The control circuit CC controls the pixel array PA so that pixel signals are read out from the pixel array PA for each frame period. The control circuit CC includes a row scanning circuit 4, a timing control circuit 5, plural column processing circuits 6-1 to 6-8, and a column scanning circuit 7. The row scanning circuit 4 controls the pixel array PA in units of row. The column scanning circuit 7 controls the pixel array PA in units of column. The timing control circuit 5 controls an operation timing of the row scanning circuit 4 and the column scanning circuit 7.

The timing control circuit 5 receives a clock signal from the controller 24 (refer to FIG. 1) , and generates a first timing signal and a second timing signal corresponding to the clock signal. The timing control circuit 5 supplies the first timing signal to the row scanning circuit 4, and supplies the second timing signal to the column scanning circuit 7.

The row scanning circuit 4 is disposed to be adjacent to the pixel array PA in the row direction. The row scanning circuit 4 is connected to plural rows of the pixels P (1, 1) to P (8, 8) via plural control line groups CL-1 to CL-8. The control line groups CL-1 to CL-8 correspond to plural rows. Each of the control line groups CL extends in the row direction. Each of the control line groups CL is connected to each pixel P of a corresponding row. The row scanning circuit 4 can perform selective scan on the pixel array PA in units of row in accordance with the first timing signal.

For example, the row scanning circuit 4 performs reset scan for sequentially selecting plural rows in the pixel array PA while resetting each pixel of the selected rows for each frame period. The row scanning circuit 4 performs reset-cancel scan for sequentially selecting plural rows in the pixel array PA while canceling reset of each pixel in the selected rows for each frame period. The row scanning circuit 4 performs readout scan for, while sequentially selecting plural rows in the pixel array PA, reading out a pixel signal from the pixel in each column included in the selected rows for each frame period.

The column processing circuits 6-1 to 6-8 are disposed to be adjacent to the pixel array PA in the column direction. The column processing circuits 6-1 to 6-8 are connected to plural columns of signal lines SL-1 to SL-8. The columns of signal lines SL-1 to SL-8 correspond to plural columns. Each of the signal lines SL extends in a direction along the column. Each of the signal lines SL is connected to each pixel P of a corresponding column. The column processing circuits 6-1 to 6-8 correspond to the columns of the signal lines SL-1 to SL-8.

For each frame period, the pixel signal is read out from the pixel P into each of the column processing circuits 6 via the signal line SL of the corresponding column by readout scan. Each of the column processing circuits 6 may convert the read-out pixel signal (analog signal) into a pixel signal (digital signal) . The column processing circuit 6 holds the converted pixel signal.

The column scanning circuit 7 is disposed in the column direction with respect to the pixel array PA. The column scanning circuit 7 is disposed on the opposite side of the pixel array PA with respect to the column processing circuits 6-1 to 6-8. The column scanning circuit 7 is connected to the column processing circuits 6-1 to 6-8.

For each frame period, the column scanning circuit 7 can sequentially perform selective scan on the column processing circuits 6-1 to 6-8 in accordance with the second timing signal. Due to this, the column scanning circuit 7 can perform selective scan on the pixel array PA in units of column. The column scanning circuit 7 supplies the pixel signal held by the selected column processing circuit 6 to the signal processing unit 23 (refer to FIG. 1) .

In each of the pixels P in the pixel array PA, a charge amount stored by the charge storage operation may be saturated to exceed a tolerable amount of the pixel P for each frame period. There is a demand for preventing saturation of the pixel P, and securing a wide dynamic range.

For example, in a case of acquiring a moving image by the imaging device 2, when a frame rate is increased n times (n is an integral number equal to or larger than 2) , a signal amount per frame is decreased by 1/n, and the pixel P is hardly saturated. For example, in a case of acquiring a moving image at 30 fps (frames per second) by the imaging device 2, when the frame rate is increased two times (to 60 fps) , the signal amount per frame is decreased by 1/2, and the pixel P is hardly saturated. By adding up the pixel signals of n frames, the imaging device 2 can acquire pixel signals corresponding to an original one frame, and secure a wide dynamic range of the signal.

However, if an operational frequency of the control circuit CC is increased to perform readout at high speed, power consumption may be increased. In a case in which the imaging system 1 to which the imaging devices 2 and 2a are applied is an electronic device of a portable type such as a smartphone, it is preferable to reduce power consumption while securing a wide dynamic range of the signal.

On the other hand, the imaging devices 2 and 2a can operate as illustrated in FIG. 3. FIG. 3 is a timing chart illustrating an operation of the imaging device 2. FIG. 3 exemplifies the operation of the imaging device 2, but the imaging device 2a can also operate in similar manner. In an upper diagram of FIG. 3, a vertical axis indicates a row position of the pixel P1, and a horizontal axis indicates a time. In a lower diagram of FIG. 3, a vertical axis indicates a row position of the pixel P2, and a horizontal axis indicates a time.

In a case in which the pixels P1 of the pixel group PG1 in the pixel array PA are easily saturated as compared with the pixels P2 of the pixel group PG2, the imaging device 2 performs one time of reset-cancel scan RC for all the pixels P, performs multiple times of readout scan RD-1 and RD-2 dividedly for the pixels P1 of the pixel group PG1, and performs one time of readout scan RD-2 for the pixels P2 of the pixel group PG2 in one frame period FT.

The imaging device 2 can acquire pixel signals of the pixels P1 corresponding to one frame by adding up the pixel signals that are read out by dividedly performing readout scan RD-1 and RD-2, and can acquire pixel signals of the pixels P2 corresponding to one frame that are read out by collectively performing the readout scan RD-2. Due to this, the pixel signals corresponding to one frame can be acquired without increasing the frame rate, and power consumption can be reduced while securing a wide dynamic range of the signal.

At this point, the readout scan RD-1 is performed on the pixels P1 of the pixel group PG1, and the readout scan RD-2 is performed on the pixels P1 and P2 of the pixel groups PG1 and PG2. The number of pixels of the readout scan RD-1 is smaller than the number of pixels of the readout scan RD-2. For example, in the pixel array PA, the pixels P1 of the pixel group PG1 illustrated by hatching in FIG. 2 are arranged in part of the rows, and the pixels P2 of the pixel group PG2 illustrated without hatching are arranged in all of the rows. The number of pixel rows of the readout scan RD-1 is smaller than the number of pixel rows of the readout scan RD-2. The imaging device 2 can perform the readout scan RD-1 as down-sampled scan, and perform the readout scan RD-2 as all-row scan. The down-sampled scan means to perform a scan down-sampled by thinning out part of the rows.

Accordingly, as illustrated in FIG. 3, time RT-1 for the readout scan RD-1 is shorter than time RT-2 for the readout scan RD-2. Due to this, the operational time of the control circuit CC in the readout scan RD-1 can be shortened as compared with the operational time of the control circuit CC in the readout scan RD-2 without increasing the operational frequency of the control circuit CC. As a result, power consumption of the control circuit CC can be reduced as compared with an operation in a case in which the time for the readout scan RD is uniform. That is, power consumption can be reduced while securing the dynamic range of the signal.

The reset-cancel scan RC is performed on the pixels P1 and P2 of the pixel groups PG1 and PG2, and the readout scan RD-2 is performed on the pixels P1 and P2 of the pixel groups PG1 and PG2. The number of pixels of the reset-cancel scan RC is substantially equal to the number of pixels of the readout scan RD-2. The number of pixel rows of the reset-cancel scan RC is substantially equal to the number of pixel rows of the readout scan RD-2. The imaging device 2 can perform the reset-cancel scan RC as all-row scan, and perform the readout scan RD-2 as all-row scan. Accordingly, time CT for the reset-cancel scan RC is substantially equal to the time RT-2 for the readout scan RD-2.

As illustrated in FIG. 3, the pixels P1 of the pixel group PG1 dividedly perform the charge storage operation in the one frame period FT, and the pixel signals are dividedly read out. The one frame period FT is substantially equal to the sum total of plural charge accumulation times. FIG. 3 exemplifies an operation in which the pixel P1 of the pixel group PG1 divides the charge storage operation into two operations to be performed in the one frame period FT. The charge accumulation times at the first time of the pixels P1 in the second row, the fourth row, the sixth row, and the eighth row (the pixels P illustrated by hatching in FIG. 2) are assumed to be ST1_2, ST1_4, ST1_6, and ST1_8, respectively. The charge accumulation times at the second time of the pixels P1 in the second row, the fourth row, the sixth row, and the eighth row are assumed to be ST2_2, ST2_4, ST2_6, and ST2_8, respectively. In this case, the following expression 1 is established.

FT = ST1_2 + ST2_2 = ST1_4 + ST2_4 = ST1_6 + ST2_6 = ST1_8 + ST2_8 ... Expression 1

In accordance with the fact that the time RT-1 for the readout scan RD-1 is shorter than the time RT-2 for the readout scan RD-2, the charge accumulation times at the first time of the pixels P of the pixel group PG1 are different among the second row, the fourth row, the sixth row, and the eighth row, and the charge accumulation time is sequentially shortened as represented by the following Expression 2.

ST1_2 > ST1_4 > ST1_6 > ST1_8 ... Expression 2

In accordance with the fact that the time RT-1 for the readout scan RD-1 is shorter than the time RT-2 for the readout scan RD-2, the charge accumulation times at the second time of the pixels P of the pixel group PG1 are different among the second row, the fourth row, the sixth row, and the eighth row, and the charge accumulation time is sequentially increased as represented by the following Expression 3.

ST2_2 < ST2_4 < ST2_6 < ST2_8 ... Expression 3

The pixels P2 of the pixel group PG2 collectively perform the charge storage operation in the one frame period FT, and the pixel signals are collectively read out. The one frame period FT is equal to the charge accumulation time. The charge accumulation times of the pixels P2 in the first row to the eighth row (the pixels P illustrated without hatching in FIG. 2) are substantially equal to each other, and this charge accumulation time is assumed to be ST3. In this case, the following Expression 4 is established.

FT = ST3 ... Expression 4

Next, the following describes a circuit configuration of the pixel P with reference to FIG. 4. FIG. 4 is a circuit diagram illustrating a configuration of the pixel P. FIG. 4 (a) illustrates a configuration of each pixel P1 of the pixel group PG1, and FIG. 4 (b) illustrates a configuration of each pixel P2 of the pixel group PG2.

As illustrated in FIG. 4 (a) , for example, each pixel P1 includes a photoelectric conversion unit PD, a transfer unit TX, a charge-voltage conversion unit FD, a reset unit RES, an amplification unit AM, and a selection unit SEL. The control line group CL includes a power supply line VDD, a control line

acontrol line

and a control line

The power supply line VDD supplies a power supply potential VDD. The control line

supplies a control signal

The control line

supplies a control signal

The control line

supplies a control signal

The control line

supplies a control signal

The photoelectric conversion unit PD performs photoelectric conversion, and generates electric charge corresponding to received light to be stored. The photoelectric conversion unit PD includes a photodiode, for example.

The transfer unit TX transfers the electric charge of the photoelectric conversion unit PD to the charge-voltage conversion unit FD in an activated state, and does not transfer the electric charge of the photoelectric conversion unit PD to the charge-voltage conversion unit FD in a non-activated state. In a case of receiving the control signal

of an active level from the row scanning circuit 4, the transfer unit TX transfers the electric charge of the photoelectric conversion unit PD to the charge-voltage conversion unit FD. In a case of receiving the control signal

of a non-active level from the row scanning circuit 4, the transfer unit TX does not transfer the electric charge of the photoelectric conversion unit PD to the charge-voltage conversion unit FD. For example, the transfer unit TX includes a transfer transistor functioning as a transfer gate. In a case in which the gate thereof receives the control signal

of an active level, the transfer unit TX turns on the transfer transistor to transfer the electric charge of the photoelectric conversion unit PD to the charge-voltage conversion unit FD, and in a case in which the gate thereof receives the control signal

of a non-active level, the transfer unit TX turns off the transfer transistor not to transfer the electric charge of the photoelectric conversion unit PD to the charge-voltage conversion unit FD.

The charge-voltage conversion unit FD converts the transferred electric charge into a voltage using parasitic capacitance C _FD thereof. The charge-voltage conversion unit FD includes floating diffusion, for example.

In a case of receiving the control signal

of an active level from the row scanning circuit 4, the reset unit RES resets an electric potential of the charge-voltage conversion unit FD to a predetermined electric potential (for example, VDD) . For example, the reset unit RES includes a reset transistor, and in a case in which the gate thereof receives the control signal

of an active level, the reset unit RES turns on the reset transistor to reset the electric potential of the charge-voltage conversion unit FD to the predetermined electric potential (for example, VDD) .

When the pixel P1 is caused to be in a selected state, the amplification unit AM outputs a signal based on a voltage of the charge-voltage conversion unit FD to the signal line SL. For example, the amplification unit AM includes an amplifier transistor. When the pixel P1 is caused to be in the selected state, the amplification unit AM outputs a signal corresponding to the voltage of the charge-voltage conversion unit FD to the column processing circuit 6 via the signal line SL by performing a source-follower operation together with a load current source CS connected via the signal line SL. The load current source CS includes a load transistor.

The selection unit SEL causes the pixel P to be in the selected state in a case of receiving the control signal

of an active level from the row scanning circuit 4, and causes the pixel P1 to be in a non-selected state in a case of receiving the control signal

of a non-active level from the row scanning circuit 4. For example, the selection unit SEL includes a selection transistor. When the gate thereof receives the control signal

of an active level, the selection unit SEL turns on the selection transistor to cause the pixel P1 to be in the selected state, and when the gate thereof receives the control signal

of a non-active level, the selection unit SEL turns off the selection transistor to cause the pixel P1 to be in the non-selected state.

The pixel P1 may have a configuration from which the selection unit SEL is omitted. In this case, the reset unit RES may perform an operation for causing the pixel P1 to be in the selected state/non-selected state. For example, the reset unit RES may cause the pixel P1 to be in the selected state by resetting the electric potential of the charge-voltage conversion unit FD to a first electric potential (for example, a VDD level) , and may cause the pixel P1 to be in the non-selected state by resetting the electric potential of the charge-voltage conversion unit FD to a second electric potential (an electric potential at which the amplification unit AM (amplifier transistor) is turned off, for example, a GND level) .

As illustrated in FIG. 4 (b) , each pixel P2 includes the photoelectric conversion unit PD, the transfer unit TX, the charge-voltage conversion unit FD, the reset unit RES, the amplification unit AM, and the selection unit SEL. Configurations and functions of the respective units in each pixel P2 are basically similar to those of each pixel P1, but different in the following points.

The transfer unit TX of the pixel P2 receives the control signal

instead of the control signal

from the row scanning circuit 4. In a case of receiving the control signal

The following describes a specific operation of each pixel P with reference to FIG. 5. FIG. 5 is a waveform diagram illustrating an operation of the pixel P. FIG. 5 exemplifies operations of the pixels P in the first to the fourth rows, but similar operations are applied to the pixels P in the rows subsequent to the fourth row.

Immediately before timing t1, the control circuit CC causes the control signals

to be an active level for the first row. Due to this, the control circuit CC resets each pixel P2 in the first row. At the same time, the control circuit CC causes the control signal

to be a non-active level. Due to this, the control circuit CC causes each pixel P2 in the first row to be in the non-selected state.

At the timing t1, the control circuit CC causes the control signals

of an active level to be a non-active level for the first row. Due to this, the control circuit CC cancels the reset of each pixel P in the first row, and starts the charge storage operation. In parallel to this, the control circuit CC causes the control signal

of a non-active level to be an active level. Due to this, the control circuit CC causes each pixel P2 in the first row to be in the selected state.

Similarly, at timing t2, the control circuit CC causes the control signals

of an active level to be a non-active level for the second row, cancels the reset of each of the pixels P1 and P2 in the second row, and starts the charge storage operation.

At timing t3, the control circuit CC causes the control signals

of an active level to be a non-active level for the third row, cancels the reset of each pixel P2 in the third row, and starts the charge storage operation.

At timing t4, the control circuit CC causes the control signals

of an active level to be a non-active level for the fourth row, cancels the reset of each of the pixels P1 and P2 in the fourth row, and starts the charge storage operation.

In this way, the control circuit CC performs the reset-cancel scan RC on the first row to the fourth row in order. The control circuit CC performs the reset-cancel scan RC on the rows subsequent to the fourth row in order.

At timing t5, the control circuit CC causes the control signal

of a non-active level to be an active level for the second row. Due to this, the control circuit CC reads out the pixel signal corresponding to a stored electric charge in the pixel P1 in the second row to the column processing circuit 6 via the signal line SL.

At timing t6, the control circuit CC causes the control signal

of a non-active level to be an active level for the second row. Due to this, the control circuit CC completes readout of the pixel signal from the pixel P1 in the second row, and resets the pixel P1 in the second row.

At timing t7, the control circuit CC causes the control signals

and

of an active level to be a non-active level for the second row. Due to this, the control circuit CC cancels the reset of each pixel P1 in the second row, and starts the charge storage operation again.

At timing t8, the control circuit CC causes the control signal

of a non-active level to be an active level for the fourth row. Due to this, the control circuit CC reads out the pixel signal corresponding to a stored electric charge in the pixel P1 in the fourth row to the column processing circuit 6 via the signal line SL.

At timing t9, the control circuit CC causes the control signal

of a non-active level to be an active level for the fourth row. Due to this, the control circuit CC completes readout of the pixel signal from the pixel P1 in the fourth row, and resets the pixel P1 in the fourth row.

At timing t10, the control circuit CC causes the control signals

of an active level to be a non-active level for the fourth row. Due to this, the control circuit CC cancels the reset of each pixel P1 in the fourth row, and starts the charge storage operation again.

In this way, the control circuit CC performs the readout scan RD-1 on the second row and the fourth row in order. That is, the control circuit CC performs the readout scan RD-1 as down-sampled scan on the second row and the fourth row among the first row to the fourth row. The control circuit CC similarly performs the readout scan RD-1 as down-sampled scan on the rows subsequent to the fourth row.

At timing t11, the control circuit CC causes the control signals

of a non-active level to be an active level for the first row. Due to this, the control circuit CC reads out the pixel signals corresponding to stored electric charge of the pixels P2 in the first row to the column processing circuit 6 via the signal line SL.

At timing t12, the control circuit CC causes the control signals

of an active level to be a non-active level for the first row. Due to this, the control circuit CC completes readout of the pixel signals from the pixels P2 in the first row.

At timing t13, the control circuit CC causes the control signals

of a non-active level to be an active level for the second row. Due to this, the control circuit CC reads out the pixel signals corresponding to the stored electric charge of the pixels P1 and P2 in the second row to the column processing circuit 6 via the signal line SL.

At timing t14, the control circuit CC causes the control signals

of an active level to be a non-active level for the second row. Due to this, the control circuit CC completes readout of the pixel signals from the pixels P1 and P2 in the second row.

At timing t15, the control circuit CC causes the control signals

of a non-active level to be an active level for the third row. Due to this, the control circuit CC reads out the pixel signals corresponding to the stored electric charge of the pixels P2 in the third row to the column processing circuit 6 via the signal line SL.

At timing t16, the control circuit CC causes the control signals

of an active level to be a non-active level for the third row. Due to this, the control circuit CC completes readout of the pixel signals from the pixels P2 in the third row.

At timing t17, the control circuit CC causes the control signals

of a non-active level to be an active level for the fourth row. Due to this, the control circuit CC reads out the pixel signals corresponding to the stored electric charge of the pixels P1 and P2 in the fourth row to the column processing circuit 6 via the signal line SL.

At timing t18, the control circuit CC causes the control signals

of an active level to be a non-active level for the fourth row. Due to this, the control circuit CC completes readout of the pixel signals from the pixels P1 and P2 in the fourth row.

In this way, the control circuit CC performs the readout scan RD-2 on the first row to the fourth row in order. The control circuit CC similarly performs the readout scan RD-2 on the rows subsequent to the fourth row in order.

As illustrated in FIG. 6, a color filter CF may be disposed in each pixel P, the color filter CF for selectively guiding light in a specific wavelength region of light incident from the optical system 21 to the photoelectric conversion unit PD. FIG. 6 is a cross-sectional view illustrating a configuration of the pixel P of the image sensor 22. FIG. 6 exemplifies the configuration of the pixel P of the image sensor 22, but the pixel P of the image sensor 22a also has similar configurations. FIG. 6 exemplifies a configuration related to the photoelectric conversion unit PD in the pixel P. For the sake of simplification, configurations related to the transfer unit TX, the charge-voltage conversion unit FD, the reset unit RES, the amplification unit AM, and the selection unit SEL in the pixel P are not illustrated in FIG. 6.

The pixel P1 of the pixel group PG1 may correspond to white (W) , for example, and may be configured as illustrated in FIG. 6 (a) . The pixel P1 may include a color filter CFw and a microlens MLw in addition to a photoelectric conversion unit PDw. The photoelectric conversion unit PDw includes a charge storage region SRw. The charge storage region SRw is disposed in the vicinity of a surface of a substrate SB. The substrate SB includes a semiconductor region including first conductivity-type impurities in the vicinity of the charge storage region SRw. The charge storage region SRw may be formed of a semiconductor region including second conductivity-type impurities. The second conductivity type is an opposite conductivity type of the first conductivity type. The color filter CFw is disposed on an upper side of the charge storage region SRw via an interlayer insulating film DFw. The color filter CFw has a transmission wavelength band corresponding to white (W) . The microlens MLw is disposed above the color filter CFw. Due to this, white (W) light is selectively guided to the charge storage region SRw via the microlens MLw and the color filter CFw. Accordingly, photoelectric conversion is performed in the vicinity of an interface between the charge storage region SRw and the substrate SB, and the electric charge is stored in the charge storage region SRw. The pixel P1 corresponding to white (W) may also be called a W pixel.

The pixel P2 of the pixel group PG2 may correspond to red (R) , for example, and may be configured as illustrated in FIG. 6 (b) . The pixel P2 may include a color filter CFr and a microlens MLr in addition to a photoelectric conversion unit PDr. The photoelectric conversion unit PDr includes a charge storage region SRr. The charge storage region SRr is disposed in the vicinity of the surface of the substrate SB. The substrate SB includes a semiconductor region including first conductivity-type impurities in the vicinity of the charge storage region SRr. The charge storage region SRr may be formed of a semiconductor region including second conductivity-type impurities. The color filter CFr is disposed on an upper side of the charge storage region SRr via an interlayer insulating film DFr. The color filter CFr has a transmission wavelength band corresponding to red (R) . The microlens MLr is disposed above the color filter CFr. Due to this, red (R) light is selectively guided to the charge storage region SRr via the microlens MLr and the color filter CFr. Accordingly, photoelectric conversion is performed in the vicinity of an interface between the charge storage region SRr and the substrate SB, and the electric charge is stored in the charge storage region SRr. The pixel P2 corresponding to red (R) may also be called an R pixel.

The pixel P2 of the pixel group PG2 may correspond to green (G) , for example, and may be configured as illustrated in FIG. 6 (c) . The pixel P2 may include a color filter CFg and a microlens MLg in addition to a photoelectric conversion unit PDg. The photoelectric conversion unit PDg includes a charge storage region SRg. The charge storage region SRg is disposed in the vicinity of the surface of the substrate SB. The substrate SB includes a semiconductor region including first conductivity-type impurities in the vicinity of the charge storage region SRg. The charge storage region SRg may be formed of a semiconductor region including second conductivity-type impurities. The color filter CFg is disposed on an upper side of the charge storage region SRg via an interlayer insulating film DFg. The color filter CFg has a transmission wavelength band corresponding to green (G) . The microlens MLg is disposed above the color filter CFg. Due to this, green (G) light is selectively guided to the charge storage region SRg via the microlens MLg and the color filter CFg. Accordingly, photoelectric conversion is performed in the vicinity of an interface between the charge storage region SRg and the substrate SB, and the electric charge is stored in the charge storage region SRg. The pixel P2 corresponding to green (G) may also be called a G pixel.

The pixel P2 of the pixel group PG2 may correspond to blue (B) , for example, and may be configured as illustrated in FIG. 6 (d) . The pixel P2 may include a color filter CFb and a microlens MLb in addition to a photoelectric conversion unit PDb. The photoelectric conversion unit PDb includes a charge storage region SRb. The charge storage region SRb is disposed in the vicinity of the surface of the substrate SB. The substrate SB includes a semiconductor region including first conductivity-type impurities in the vicinity of the charge storage region SRb. The charge storage region SRb may be formed of a semiconductor region including second conductivity-type impurities. The color filter CFb is disposed on an upper side of the charge storage region SRb via an interlayer insulating film DFb. The color filter CFb has a transmission wavelength band corresponding to blue (B) . The microlens MLb is disposed above the color filter CFb. Due to this, blue (B) light is selectively guided to the charge storage region SRb via the microlens MLb and the color filter CFb. Accordingly, photoelectric conversion is performed in the vicinity of an interface between the charge storage region SRb and the substrate SB, and the electric charge is stored in the charge storage region SRb. The pixel P2 corresponding to blue (B) may also be called a B pixel.

Transmission characteristics of respective color filters CFw, CFr, CFg, and CFb may be characteristics as illustrated in FIG. 7. FIG. 7 is a diagram illustrating the transmission characteristics of the color filters CFw, CFr, CFg, and CFb. The color filter CFw has a transmission characteristic WFw. The transmission characteristic WFw has a transmission wavelength band corresponding to white (W) . The transmission wavelength band is assumed to be a wavelength band in which transmittance is equal to or higher than required transmittance TRth. The color filter CFr has a transmission characteristic WFr corresponding to red (R) . The transmission characteristic WFr has a transmission wavelength band corresponding to red (R) . The color filter CFg has a transmission characteristic WFg corresponding to green (G) . The transmission characteristic WFg has a transmission wavelength band corresponding to green (G) . The color filter CFb has a transmission characteristic WFb corresponding to blue (B) . The transmission characteristic WFb has a transmission wavelength band corresponding to blue (B) .

As illustrated in FIG. 7, the transmission wavelength band of the color filter CFw includes the transmission wavelength band of the color filter CFr. The transmission wavelength band of the color filter CFw includes the transmission wavelength band of the color filter CFg. The transmission wavelength band of the color filter CFw includes the transmission wavelength band of the color filter WFb.

Further as illustrated in FIG. 7, maximum transmittance of the color filter CFw is higher than maximum transmittance of the color filter CFr. The maximum transmittance of the color filter CFw is higher than maximum transmittance of the color filter CFg. The maximum transmittance of the color filter CFw is higher than maximum transmittance of the color filter WFb.

Due to this, in a case of storing the electric charge with charge accumulation times substantially equal to each other, the electric charge may be easily saturated in the charge storage region SRw of the photoelectric conversion unit PDw as compared with the charge storage region SRr of the photoelectric conversion unit PDr. The electric charge may be easily saturated in the charge storage region SRw of the photoelectric conversion unit PDw as compared with the charge storage region SRg of the photoelectric conversion unit PDg. The electric charge may be easily saturated in the charge storage region SRw of the photoelectric conversion unit PDw as compared with the charge storage region SRb of the photoelectric conversion unit PDb.

For example, in a case in which the pixel array PA is configured as a two-dimensional array of unit arrays UA illustrated in FIG. 8 (a) , the control circuit CC may perform control illustrated in FIG. 8 (b) . FIG. 8 (a) is a diagram illustrating a configuration of the pixel array PA. FIG. 8 (b) is a timing chart illustrating an operation of the control circuit CC.

In the pixel array PA, the unit arrays UA are repeatedly arranged in the row direction and the column direction. The unit array UA includes two rows and two columns of the pixels P. The unit array UA can be obtained by replacing one G pixel of a Bayer array including the R pixel, the B pixel, and two G pixels with the W pixel. In the unit array UA, the R pixel and the B pixel are arranged to be diagonally opposite to each other, and the G pixel and the W pixel are arranged to be diagonally opposite to each other. In the unit array UA, the W pixel corresponds to the pixel P1 of the pixel group PG1 (the pixel P illustrated by hatching in FIG. 2) , and the R pixel, the B pixel, and the G pixel correspond to the pixel P2 of the pixel group PG2 (the pixel P illustrated without hatching in FIG. 2) .

In the one frame period FT illustrated in FIG. 8 (b) , the control circuit CC performs the reset-cancel scan RC as all-row scan on the pixels P in the respective rows of the pixel array PA. The control circuit CC performs a reset cancellation operation on the R pixel and the G pixel in the first row. The control circuit CC performs the reset cancellation operation on the W pixel and the B pixel in the second row. The control circuit CC performs the reset cancellation operation on the R pixel and the G pixel in the third row. The control circuit CC performs the reset cancellation operation on the W pixel and the B pixel in the fourth row. The control circuit CC performs the reset cancellation operation on the R pixel and the G pixel in the fifth row. The control circuit CC performs the reset cancellation operation on the W pixel and the B pixel in the sixth row. The control circuit CC performs the reset cancellation operation on the R pixel and the G pixel in the seventh row. The control circuit CC performs the reset cancellation operation on the W pixel and the B pixel in the eighth row. Accordingly, the pixels P in the respective rows (the W pixel, the R pixel, the B pixel, and the G pixel) start the charge storage operation.

The control circuit CC performs the readout scan RD-1 as down-sampled scan on the pixels P1 of the pixel group PG1 (the pixels P illustrated by hatching in FIG. 2) . The control circuit CC performs a readout operation on the W pixel in the second row. The control circuit CC performs the readout operation on the W pixel in the fourth row. The control circuit CC performs the readout operation on the W pixel in the sixth row. The control circuit CC performs the readout operation on the W pixel in the eighth row. Due to this, the pixels P1 (W pixels) complete the first charge storage operation, and the pixel signals corresponding to the electric charge stored in the first charge storage operation are read out from the pixels P1 (W pixels) to the control circuit CC. The control circuit CC transfers the read-out pixel signals to the signal processing unit 23. In parallel to this, the pixels P1 (W pixels) start the second charge storage operation. At this point, the pixels P2 (the R pixel, the B pixel, and the G pixel) are continuously performing the charge storage operation.

The control circuit CC performs the readout scan RD-2 as all-row scan on the pixels P in each row of the pixel array PA. The control circuit CC performs the readout operation on the R pixel and the G pixel in the first row. The control circuit CC performs the readout operation on the W pixel and the B pixel in the second row. The control circuit CC performs the readout operation on the R pixel and the G pixel in the third row. The control circuit CC performs the readout operation on the W pixel and the B pixel in the fourth row. The control circuit CC performs the readout operation on the R pixel and the G pixel in the fifth row. The control circuit CC performs the readout operation on the W pixel and the B pixel in the sixth row. The control circuit CC performs the readout operation on the R pixel and the G pixel in the seventh row. The control circuit CC performs the readout operation on the W pixel and the B pixel in the eighth row. Due to this, the pixels P1 (W pixels) complete the second charge storage operation, and the pixels P2 (the R pixel, the B pixel, and the G pixel) complete the charge storage operation. The pixel signals corresponding to the electric charge stored in the second charge storage operation are read out from the pixels P1 (W pixels) to the control circuit CC (column processing circuit 6) . The control circuit CC transfers the read-out pixel signals to the signal processing unit 23. The pixel signals corresponding to the electric charge stored in the charge storage operation are read out from the pixels P2 (the R pixel, the B pixel, and the G pixel) to the control circuit CC (column processing circuit 6) . The control circuit CC transfers the read-out pixel signals to the signal processing unit 23.

The signal processing unit 23 generates pixel signals corresponding to one frame by adding up the pixel signals read out by the readout scan RD-1 and the pixel signals read out by the readout scan RD-2 for the pixel P1. The signal processing unit 23 assumes the pixel signals read out by the readout scan RD-2 as pixel signals corresponding to one frame for the pixel P2. The signal processing unit 23 performs predetermined signal processing on each pixel signal, and configures the pixel signals two dimensionally to generate image data. The signal processing unit 23 supplies the image data to the controller 24. Due to this, the controller 24 can cause an image (for example, a moving image or a static image) to be displayed on a display screen (not illustrated) in accordance with the image data.

As described above, in the imaging device 2 according to the present embodiment, the control circuit CC performs, in one frame period FT, readout scan RD-1 to read out pixel signals from the pixels P1 of the pixel group PG1, and performs readout scan RD-2 to read out pixel signals from the pixels P1 of the pixel group PG1 and the pixel P2 of the pixel group PG2. With this operation, the time RT-1 for the readout scan RD-1 may be shorter than the time RT-2 for the readout scan RD-2. Due to this, the operational time of the control circuit CC in the readout scan RD-1 can be shortened as compared with the operational time of the control circuit CC in the readout scan RD-2 without increasing the operational frequency of the control circuit CC. As a result, power consumption of the control circuit CC can be reduced as compared with an operation in a case in which the time for the readout scan RD is uniform. That is, power consumption can be reduced while securing the dynamic range of the signal.

Note that, in a first modification of the embodiment, the pixel array PA may have the pixels P2 of the pixel group PG2 and the pixels P1 of the pixel group PG1 that are arrayed in the column direction alternately row by row, as illustrated in FIG. 9 (a) . In this case, the control circuit CC may perform control as illustrated in FIG. 9 (b) . FIG. 9 (a) is a diagram illustrating configuration of the pixel array PA according to the first modification of the embodiment. FIG. 9 (b) is a timing chart illustrating operations of the control circuit CC according to the first modification of the embodiment.

In the pixel array PA, a first column and a second column are alternatively arranged along the row direction. Here, the first column may be defined as odd-numbered column when being counted from left side in FIG. 9. The second column may be defined as even-numbered column when being counted from left side in FIG. 9. In the first column, a pixel of the pixel group PG2 and a pixel of the pixel group PG1 are alternatively arranged along the row direction. In the second column, a pixel of the pixel group PG2 and a pixel of the pixel group PG1 are alternatively arranged along the row direction. A row position of the pixel group PG1 in the first column corresponds to a row position of the pixel group PG2 in the second column. A row position of the pixel group PG1 in the first column corresponds to a row position of the pixel group PG1 in the second column.

The pixel array PA corresponds to plural colors. The pixel group PG1 corresponds to the first color. The pixel group PG2 corresponds to the second color. In the case of FIG. 9, the first color is any of white or blue, and the second color is any of red or green. In other words, the pixel group PG1 includes W pixels and B pixels, and the pixel group PG2 includes R pixels and G pixels.

In the pixel array PA, for B pixels of any even-numbered rows, the configuration of the pixel P2 (see FIG. 4 (b) ) is replaced with the configuration of the pixel P1 (see FIG. 4 (a) ) . The control line group CL of any odd-numbered rows is replaced with the control line group CL2, and the control line group CL of any even-numbered rows is replaced with the control line group CL1. In the control line group CL2, the control line

is omitted from the control line group CL. In the control line group CL1, the control line

is omitted from the control line group CL. This makes it possible to reduce the number of control lines and secure a wide light-receiving area of the photoelectric conversion unit PD.

In the one-frame period FT as illustrated in FIG. 9 (b) , the control circuit CC performs the reset-cancel scan RC for the pixels P of each row in the pixel array PA as all-row scan. The control circuit CC performs reset-cancel operation for the R pixels and the G pixels of the first row. The control circuit CC performs reset-cancel operation for the W pixels and the B pixels of the second row. The control circuit CC performs reset-cancel operation for the R pixels and the G pixels of the third row. The control circuit CC performs reset-cancel operation for the W pixels and the B pixels of the fourth row. The control circuit CC performs reset-cancel operation for the R pixels and the G pixels of the fifth row. The control circuit CC performs reset-cancel operation for the W pixels and the B pixels of the sixth row. The control circuit CC performs reset-cancel operation for the R pixels and the G pixels of the seventh row. The control circuit CC performs reset-cancel operation for the W pixels and the B pixels of the eighth row. Thus, the pixels P (W pixels, R pixels, B pixels, and G pixels) of each row start charge storage operation.

The control circuit CC performs, as down-sampled scan, a readout scan RD-1 for the pixels P1 (W pixels and B pixels) of the pixel group PG1. The control circuit CC performs readout operation for the W pixels and the B pixels of the second row. The control circuit CC performs readout operation for the W pixels and the B pixels of the fourth row. The control circuit CC performs readout operation for the W pixels and the B pixels of the sixth row. The control circuit CC performs readout operation for the W pixels and the B pixels of the eighth row. Thus, the pixels P1 (W pixels and B pixels) completes the first charge storage operation, and pixel signals corresponding to the charge stored by the first charge storage operation are read-out from the pixels P1 (W pixels and B pixels) to the control circuit CC. The control circuit CC transfers the read-out pixel signals to the signal processing unit 23. Along with that, the pixels P1 (W pixels and B pixels) start second charge storage operation. At this moment, the pixels P2 (R pixels and G pixels) continues the charge storage operation.

The control circuit CC performs, as all-row scan, a readout scan RD-2 for the pixels P of each row in the pixel array PA. The control circuit CC performs readout operation for the R pixels and the G pixels of the first row. The control circuit CC performs readout operation for the W pixels and the B pixels of the second row. The control circuit CC performs readout operation for the R pixels and the G pixels of the third row. The control circuit CC performs readout operation for the W pixels and the B pixels of the fourth row. The control circuit CC performs readout operation for the R pixels and the G pixels of the fifth row. The control circuit CC performs readout operation for the W pixels and the B pixels of the sixth row. The control circuit CC performs readout operation for the R pixels and the G pixels of the seventh row. The control circuit CC performs readout operation for the W pixels and the B pixels of the eighth row. Thus, the pixels P1 (W pixels and B pixels) complete the second charge storage operation, and the pixels P2 (R pixels and G pixels) complete the charge storage operation. Pixel signals corresponding to the charge stored by the second charge storage operation are read-out from the pixels P1 (W pixels and B pixels) to the control circuit CC (column processing circuit 6) . The control circuit CC forwards the read-out pixel signals to the signal processing unit 23. Pixel signals corresponding to the charge stored by the charge storage operation are read out from the pixels P2 (R pixels and G pixels) to the control circuit CC (column processing circuit 6) . The control circuit CC transfers the read-out pixel signals to the signal processing unit 23.

The signal processing unit 23 adds, for the pixels P1, the pixel signals read-out at the readout scan RD-1 and the pixel signals read-out at the readout scan RD-2 to generate pixel signals for one frame. The signal processing unit 23 uses, for the pixels P2, the pixel signals read-out at the readout scan RD-2 as pixel signals for one frame. The signal processing unit 23 performs predetermined signal processing for each pixel signal and form them two-dimensionally, thereby generating image data. The signal processing unit 23 supplies the image data to the controller 24. The controller 24 thus can display an image (for example, a moving image or a still image) on a display screen (not shown) in accordance with the image data.

With the imaging device 2 as described above, the time RT-1 of the readout scan RD-1 is still shorter than the time RT-2 of the readout scan RD-2. Therefore, without increasing the operational frequency of the control circuit CC, the operational time of the control circuit CC for the readout scan RD-1 can be shortened than the operational time of the control circuit CC for the readout scan RD-2. As a result, it is possible to reduce the power consumed by the control circuit CC, as compared to operations in which the times for the readout scans RD are uniformly equal. In other words, it is possible to reduce the power consumed, while securing the dynamic range of the signals.

In a second modification of the embodiment, the pixel array PA may have configuration in which the W pixels are omitted, as illustrated in FIG. 10 (a) . In this case, the control circuit CC may perform control as illustrated in FIG. 10 (b) . FIG. 10 (a) is a diagram illustrating the configuration of the pixel array PA according to the second modification of the embodiment. FIG. 10 (b) is a timing chart illustrating operations of the control circuit CC according to the second modification of the embodiment.

The pixel array PA corresponds to plural colors. The pixel group PG1 corresponds to the first color. The pixel group PG2 corresponds to the second color. In the case of FIG. 10, the first color is green, and the second color is any of red, green or blue. In other words, the pixel group PG1 includes course-dot-hatched G pixels, and the pixel group PG2 includes R pixels, fine-dot-hatched G pixels and B pixels.

The unit array UA is formed by a Bayer array including an R pixel, a B pixel, and two G pixels. As illustrated in FIG. 7, the maximum transmittance of the color filter CFg is higher than the maximum transmittance of the color filter CFr. The maximum transmittance of the color filter CFg is higher than the maximum transmittance of the color filter CFb. With this configuration, when charge is accumulated in a mutually-equal charge accumulation time, the charge storage region SRg of the photoelectric conversion unit PDg is saturated with charge more easily than the charge storage region SRr of the photoelectric conversion unit PDr. The charge storage region SRg of the photoelectric conversion unit PDg is saturated with charge more easily than the charge storage region SRb of the photoelectric conversion unit PDb. Thus, in the unit array UA, one of the two G pixels that is on an even-numbered row has the configuration of the pixel P1 (see FIG. 4 (a) ) , and the other G pixel on an odd-numbered row has the configuration of the pixel P2 (see FIG. 4 (b) ) .

In the one-frame period FT as illustrated in FIG. 10 (b) , the control circuit CC performs, as all-row scan, the reset-cancel scan RC for the pixels P of each row in the pixel array PA. The control circuit CC performs reset-cancel operation for the R pixels and the G pixels of the first row. The control circuit CC performs reset-cancel operation for the G pixels and the B pixels of the second row. The control circuit CC performs reset-cancel operation for the R pixels and the G pixels of the third row. The control circuit CC performs reset-cancel operation for the G pixels and the B pixels of the fourth row. The control circuit CC performs reset-cancel operation for the R pixels and the G pixels of the fifth row. The control circuit CC performs reset-cancel operation for the G pixels and the B pixels of the sixth row. The control circuit CC performs reset-cancel operation for the R pixels and the G pixels of the seventh row. The control circuit CC performs reset-cancel operation for the G pixels and the B pixels of the eighth row. Thus, the pixels P (G pixels, R pixels, B pixels, and G pixels) of each row start charge storage operation.

The control circuit CC performs, as down-sampled scan, the readout scan RD-1 for the pixels P1 (hatched pixels P as illustrated in FIG. 2) of the pixel group PG1. The control circuit CC performs readout operation for the G pixels of the second row. The control circuit CC performs readout operation for the G pixels of the fourth row. The control circuit CC performs readout operation for the G pixels of the sixth row. The control circuit CC performs readout operation for the G pixels of the eighth row. Thus, the pixels P1 (G pixels) completes the first charge storage operation, and pixel signals corresponding to the charge stored by the first charge storage operation are read-out from the pixels P1 (G pixels) to the control circuit CC. The control circuit CC forwards the read-out pixel signals to the signal processing unit 23. Along with that, the pixels P1 (G pixels) start second charge storage operation. At this moment, the pixels P2 (R pixels, B pixels, and G pixels) continue the charge storage operation.

The control circuit CC performs, as all-row scan, the readout scan RD-2 for the pixels P of each row in the pixel array PA. The control circuit CC performs readout operation for the R pixels and the G pixels of the first row. The control circuit CC performs readout operation for the G pixels and the B pixels of the second row. The control circuit CC performs readout operation for the R pixels and the G pixels of the third row. The control circuit CC performs readout operation for the G pixels and the B pixels of the fourth row. The control circuit CC performs readout operation for the R pixels and the G pixels of the fifth row. The control circuit CC performs readout operation for the G pixels and the B pixels of the sixth row. The control circuit CC performs readout operation for the R pixels and the G pixels of the seventh row. The control circuit CC performs readout operation for the G pixels and the B pixels of the eighth row. Thus, the pixels P1 (G pixels) complete the second charge storage operation, and the pixels P2 (R pixels, B pixels, and G pixels) complete the charge storage operation. Pixel signals corresponding to the charge stored by the second charge storage operation are read-out from the pixels P1 (G pixels) to the control circuit CC (column processing circuit 6) . The control circuit CC forwards the read-out pixel signals to the signal processing unit 23. Pixel signals corresponding to the charge stored by the charge storage operation are read-out from the pixels P2 (R pixels, B pixels, and G pixels) to the control circuit CC (column processing circuit 6) . The control circuit CC transfers the read-out pixel signals to the signal processing unit 23.

With the imaging device 2 as described above, the time RT-1 of the readout scan RD-1 is still shorter than the time RT-2 of the readout scan RD-2. Therefore, without increasing the operational frequency of the control circuit CC, the operational time of the control circuit CC for the readout scan RD-1 can be shortened than the operational time of the control circuit CC for the readout scan RD-2. As a result, it is possible to reduce the power consumed by the control circuit CC, as compared to operations in which the times for the readout scans RD are uniformly equal. In other words, it is possible to reduce the power consumed, while maintaining the dynamic range of the signals.

In a third modification of the embodiment, the pixel array PA may have configuration in which the W pixels are omitted and in which the pixels P2 of the pixel group PG2 and the pixels P1 of the pixel group PG1 are arrayed in the column direction alternately row by row, as illustrated in FIG. 11 (a) . In this case, the control circuit CC may perform control as illustrated in FIG. 11 (b) . FIG. 11 (a) is a diagram illustrating the configuration of the pixel array PA according to the third modification of the embodiment. FIG. 11 (b) is a timing chart illustrating operations of the control circuit CC according to the third modification of the embodiment.

In the pixel array PA, a first column and a second column are alternatively arranged along the row direction. Here, the first column may be defined as odd-numbered column when being counted from left side in FIG. 11. The second column may be defined as even-numbered column when being counted from left side in FIG. 11. In the first column, a pixel of the pixel group PG2 and a pixel of the pixel group PG1 are alternatively arranged along the row direction. In the second column, a pixel of the pixel group PG2 and a pixel of the pixel group PG1 are alternatively arranged along the row direction. A row position of the pixel group PG1 in the first column corresponds to a row position of the pixel group PG2 in the second column. A row position of the pixel group PG1 in the first column corresponds to a row position of the pixel group PG1 in the second column.

The pixel array PA corresponds to plural colors. The pixel group PG1 corresponds to the first color. The pixel group PG2 corresponds to the second color. In the case of FIG. 11, the first color is any of green or blue, and the second color is any of red or green. In other words, the pixel group PG1 includes course-dot-hatched G pixels and B pixels, and the pixel group PG2 includes R pixels and fine-dot-hatched G pixels.

The pixel array PA as illustrated in FIG. 11 (a) is made by modifying the pixel array PA as illustrated in FIG. 10 (a) such that, for B pixels in any even-numbered rows, the configuration of the pixel P2 (see FIG. 4 (b) ) is replaced with the configuration of the pixel P1 (see FIG. 4 (a) ) . The control line group CL in any odd-numbered rows is replaced with the control line group CL2, and the control line group CL in any even-numbered rows is replaced with the control line group CL1. In the control line group CL2, the control line

In the one-frame period FT as illustrated in FIG. 11 (b) , the control circuit CC performs, as all-row scan, the reset-cancel scan RC for the pixels P of each row in the pixel array PA. The control circuit CC performs reset-cancel operation for the R pixels and the G pixels of the first row. The control circuit CC performs reset-cancel operation for the G pixels and the B pixels of the second row. The control circuit CC performs reset-cancel operation for the R pixels and the G pixels of the third row. The control circuit CC performs reset-cancel operation for the G pixels and the B pixels of the fourth row. The control circuit CC performs reset-cancel operation for the R pixels and the G pixels of the fifth row. The control circuit CC performs reset-cancel operation for the G pixels and the B pixels of the sixth row. The control circuit CC performs reset-cancel operation for the R pixels and the G pixels of the seventh row. The control circuit CC performs reset-cancel operation for the G pixels and the B pixels of the eighth row. Thus, the pixels P (G pixels, R pixels, B pixels, and G pixels) of each row start charge storage operation.

The control circuit CC performs, as down-sampled scan, the readout scan RD-1 for the pixels P1 (G pixels and B pixels) of the pixel group PG1. The control circuit CC performs readout operation for the G pixels and the B pixels of the second row. The control circuit CC performs readout operation for the G pixels and the B pixels of the fourth row. The control circuit CC performs readout operation for the G pixels and the B pixels of the sixth row. The control circuit CC performs readout operation for the G pixels and the B pixels of the eighth row. Thus, the pixels P1 (G pixels and B pixels) complete the first charge storage operation, and pixel signals corresponding to the charge stored by the first charge storage operation are read-out from the pixels P1 (G pixels and B pixels) to the control circuit CC. The control circuit CC forwards the read-out pixel signals to the signal processing unit 23. Along with that, the pixels P1 (G pixel and B pixel) start second charge storage operation. At this moment, the pixels P2 (R pixels and G pixels) continue the charge storage operation.

The control circuit CC performs, as all-row scan, the readout scan RD-2 for the pixels P of each row in the pixel array PA. The control circuit CC performs readout operation for the R pixels and the G pixels of the first row. The control circuit CC performs readout operation for the G pixels and the B pixels of the second row. The control circuit CC performs readout operation for the R pixels and the G pixels of the third row. The control circuit CC performs readout operation for the G pixels and the B pixels of the fourth row. The control circuit CC performs readout operation for the R pixels and the G pixels of the fifth row. The control circuit CC performs readout operation for the G pixels and the B pixels of the sixth row. The control circuit CC performs readout operation for the R pixels and the G pixels of the seventh row. The control circuit CC performs readout operation for the G pixels and the B pixels of the eighth row. Thus, the pixels P1 (G pixels and B pixels) complete the second charge storage operation, and the pixels P2 (R pixels and G pixels) complete the charge storage operation. Pixel signals corresponding to the charge stored by the second charge storage operation are read-out from the pixels P1 (G pixels and B pixels) to the control circuit CC (column processing circuit 6) . The control circuit CC forwards the read-out pixel signals to the signal processing unit 23. Pixel signals corresponding to the charge stored by the charge storage operation are read-out from the pixels P2 (R pixels and G pixels) to the control circuit CC (column processing circuit 6) . The control circuit CC forwards the read-out pixel signals to the signal processing unit 23.

In a fourth modification of the embodiment, the pixel array PA may have configuration that enables charge addition of two or more pixels, as illustrated in FIG. 12 (a) . In this case, the control circuit CC may perform control as illustrated in FIG. 12 (b) . FIG. 12 (a) is a diagram illustrating the configuration of the pixel array PA according to the fourth modification of the embodiment. FIG. 12 (b) is a timing chart illustrating operations of the control circuit CC according to the fourth modification of the embodiment.

In the pixel array PA, a first column and a second column are alternatively arranged along a row direction. Here, the first column may be defined as odd-numbered column when being counted from left side in FIG. 12. The second column may be defined as even-numbered column when being counted from left side in FIG. 12. In the first column, a pixel of the pixel group PG2 and a pixel of the pixel group PG1 are alternatively arranged along a column direction. In the second column, a pixel of the pixel group PG1 and a pixel of the pixel group PG2 are alternatively arranged along the column direction. A row position of the pixel group PG2 in the first column corresponds to a row position of the pixel group PG1 in the second column. A row position of the pixel group PG1 in the first column corresponds to a row position of the pixel group PG2 in the second column.

The pixel array PA corresponds to plural colors. The pixel group PG1 corresponds to the first color. The pixel group PG2 corresponds to the second color. In the case of FIG. 12, the first color is white, and the second color is any of red, green or blue. In other words, the pixel group PG1 includes W pixels, and the pixel group PG2 includes R pixels and G pixels and B pixels.

The pixel array PA has unit arrays UA as illustrated in FIG. 12 (a) arranged two-dimensionally. The unit array UA includes pixel units PU each having two rows and two columns. Each pixel unit PU includes four pixels P. The unit array UA corresponds to a Bayer array, and it includes an R pixel unit PUr, a B pixel unit PUb, and two G pixel units PUg. The R pixel unit PUr has two R pixels arranged in a diagonal direction and two W pixels arranged in the other diagonal direction. The B pixel unit PUb has two B pixels arranged in a diagonal direction and two W pixels arranged in the other diagonal direction. The G pixel unit PUg has two G pixels arranged in a diagonal direction and two W pixels arranged in the other diagonal direction.

Each pixel unit PU may be configured as illustrated in FIG. 13. FIG. 13 is a circuit diagram illustrating configuration of the pixel unit PU according to the fourth modification of the embodiment.

In the R pixel unit PUr, the charge-voltage conversion unit FD, the reset unit RES, the amplification unit AM, and the selection unit SEL are shared by the four pixels P, and the photoelectric conversion unit PD and the transfer unit TX are provided at each of the four pixels P. The photoelectric conversion units PDr and the transfer units TXr correspond to the R pixels, and the photoelectric conversion units PDw and the transfer units TXw correspond to the W pixels. In the R pixel unit PUr, the two photoelectric conversion units PDr and the two transfer units TXr are arranged in a diagonal direction, and the two photoelectric conversion units PDw and the two transfer units TXw are arranged in the other diagonal direction.

In the B pixel unit PUb, the charge-voltage conversion unit FD, the reset unit RES, the amplification unit AM, and the selection unit SEL are shared by the four pixels P, and the photoelectric conversion unit PD and the transfer unit TX are provided at each of the four pixels P. The photoelectric conversion units PDb and the transfer units TXb correspond to the B pixels, and the photoelectric conversion units PDw and the transfer units TXw correspond to the W pixels. In the B pixel unit PUb, the two photoelectric conversion units PDb and the two transfer units TXb are arranged in a diagonal direction, and the two photoelectric conversion units PDw and the two transfer units TXw are arranged in the other diagonal direction.

In the G pixel unit PUg, the charge-voltage conversion unit FD, the reset unit RES, the amplification unit AM, and the selection unit SEL are shared by the four pixels P, and the photoelectric conversion unit PD and the transfer unit TX are provided at each of the four pixels P. The photoelectric conversion units PDg and the transfer units TXg correspond to the G pixels, and the photoelectric conversion units PDw and the transfer units TXw correspond to the W pixels. In the G pixel unit PUg, the two photoelectric conversion units PDg and the two transfer units TXg are arranged in a diagonal direction, and the two photoelectric conversion units PDw and the two transfer units TXw are arranged in the other diagonal direction.

In the one-frame period FT as illustrated in FIG. 12 (b) , the control circuit CC performs, as all-row scan, the reset-cancel scan RC for the pixels P of each row in the pixel array PA. The control circuit CC performs reset-cancel operation for each pixel P in the R pixel unit PUr and each pixel P in the G pixel unit PUg of the first row. The control circuit CC performs reset-cancel operation for each pixel P in the G pixel unit PUg and each pixel P in the B pixel unit PUb of the second row. The control circuit CC performs reset-cancel operation for each pixel P in the R pixel unit PUr and each pixel P in the G pixel unit PUg of the third row. The control circuit CC performs reset-cancel operation for each pixel P in the G pixel unit PUg and each pixel P in the B pixel unit PUb of the fourth row. Thus, each pixel P (W pixels, R pixels, B pixels, and G pixels) in the pixel units PU of each row starts charge storage operation.

The control circuit CC performs the readout scan RD-1 for the pixels P1 (W pixels) of the pixel group PG1 as substantially down-sampled scan. The control circuit CC performs readout operation by performing charge addition of the respective W pixels in the R pixel unit PUr and the respective W pixels of the G pixel unit PUg of the first row.

At a timing t21 as illustrated in FIG. 14, for example, the control circuit CC sets the control signal

from a non-active level to an active level. FIG. 14 is a waveform chart illustrating operation of the pixel unit PU according to the fourth modification of the embodiment. The control circuit CC thus transfers the charges of the two photoelectric conversion units PDw in the R pixel unit PUr of the first row and causes the charge-voltage conversion unit FD to add them together, and transfers the charges of the two photoelectric conversion units PDw in the G pixel unit PUg of the first row and causes the charge-voltage conversion unit FD to add them together. The control circuit CC thereby reads out pixel signals for W corresponding to the charge addition results of the R pixel unit PUr and the G pixel unit PUg of the first row, respectively, to the column processing circuit 6 via the signal line SL.

At a timing t22, the control circuit CC sets the control signal

from the non-active level to the active level. Thus, the control circuit CC completes the reading-out of the pixel signals from the W pixels (photoelectric conversion units PDw) in the R pixel unit PUr and the G pixel unit PUg of the first row and resets those W pixels (photoelectric conversion units PDw) .

At a timing t23, the control circuit CC sets the control signals

from the active level to the non-active level. Thus, the control circuit CC cancels the reset of the W pixels in the R pixel unit PUr and the G pixel unit PUg (photoelectric conversion units PDw) of the first row and re-starts the charge storage operation.

As described above, in the readout scan RD-1, operation relating to the R pixels in the R pixel unit PUr of the first row is skipped, and operation relating to the G pixels in the G pixel unit PUg of the first row is skipped.

Returning to FIG. 12, the control circuit CC performs readout operation by performing charge addition of the respective W pixels in the G pixel unit PUg and the respective W pixels of the B pixel unit PUb of the second row. The control circuit CC performs readout operation by performing charge addition of the respective W pixels in the R pixel unit PUr and the respective W pixels of the G pixel unit PUg of the third row. The control circuit CC performs readout operation by performing charge addition of the respective W pixels in the G pixel unit PUg and the respective W pixels of the B pixel unit PUb of the fourth row. Thus, the W pixels of the pixel unit PU (photoelectric conversion units PDw) complete the first charge storage operation, and pixel signals corresponding to the charge stored by the first charge storage operation are read out from the pixel unit PU to the control circuit CC. The control circuit CC transfers the read-out pixel signals to the signal processing unit 23. Along with that, the W pixels (photoelectric conversion units PDw) start second charge storage operation. At this moment, the R pixels, the G pixels, and the B pixels (photoelectric conversion units PDr, PDg, and PDb) of the pixel units PU continue the charge storage operation.

The control circuit CC performs, as all-row scan, the readout scan RD-2 for the pixels P of each row in the pixel array PA. The control circuit CC performs readout operation by performing charge addition of the respective W pixels in the R pixel unit PUr and the respective W pixels of the G pixel unit PUg of the first row. The control circuit CC performs readout operation by performing charge addition of the respective R pixels in the R pixel unit PUr and the respective G pixels of the G pixel unit PUg of the first row.

At a timing t24 as illustrated in FIG. 14, for example, the control circuit CC sets the control signal

from the non-active level to the active level for the first row. The control circuit CC thus transfers the charges of the two photoelectric conversion units PDw in the R pixel unit PUr of the first row and causes the charge-voltage conversion unit FD to add them together, and transfers the charges of the two photoelectric conversion units PDw in the G pixel unit PUg of the first row and causes the charge-voltage conversion unit FD to add them together. The control circuit CC thereby reads out pixel signals for W corresponding to the charge addition results of the R pixel unit PUr and the G pixel unit PUg of the first row, respectively, to the column processing circuit 6 via the signal line SL.

At a timing t25, the control circuit CC sets the control signal

from the non-active level to the active level and sets the control signal

from the active level to the non-active level. Thus, the control circuit CC completes the reading-out of the pixel signals from the W pixels (photoelectric conversion units PDw) in the R pixel unit PUr and the G pixel unit PUg of the first row and resets the charge-voltage conversion unit FD.

At a timing t26, the control circuit CC sets the control signal

from the active level to the non-active level, and sets the control signal

from the non-active level to the active level. Thus, the control circuit CC transfers the charges of the two photoelectric conversion units PDr in the R pixel unit PUr of the first row and causes the charge-voltage conversion unit FD to add them together, and transfers the charges of the two photoelectric conversion units PDg in the G pixel unit PUg of the first row and causes the charge-voltage conversion unit FD to add them together. The control circuit CC thereby reads out pixel signals for R and G corresponding to the charge addition results of the R pixel unit PUr and the G pixel unit PUg of the first row, respectively, to the column processing circuit 6 via the signal line SL.

At a timing t27, the control circuit CC sets the control signal

from the active level to the non-active level. Thus, the control circuit CC completes the reading-out of the pixel signals from the R pixels (photoelectric conversion units PDr) in the R pixel unit PUr and the G pixels (photoelectric conversion units PDg) and the G pixel unit PUg of the first row.

Returning to FIG. 12, the control circuit CC performs readout operation by performing charge addition of the respective W pixels in the G pixel unit PUg and the respective W pixels of the B pixel unit PUb of the second row. The control circuit CC performs readout operation by performing charge addition of the respective G pixels in the G pixel unit PUg and the respective B pixels of the B pixel unit PUb of the second row. The control circuit CC performs readout operation by performing charge addition of the respective W pixels in the R pixel unit PUr and the respective W pixels of the G pixel unit PUg of the third row. The control circuit CC performs readout operation by performing charge addition of the respective R pixels in the R pixel unit PUr and the respective G pixels of the G pixel unit PUg of the third row. The control circuit CC performs readout operation by performing charge addition of the respective W pixels in the G pixel unit PUg and the respective W pixels of the B pixel unit PUb of the fourth row. The control circuit CC performs readout operation by performing charge addition of the respective G pixels in the G pixel unit PUg and the respective B pixels of the B pixel unit PUb of the fourth row. Thus, the pixels P1 (W pixels) complete the second charge storage operation, and the pixels P2 (R pixels, G pixels, and B pixels) complete the charge storage operation. Pixel signals for W corresponding to the charge stored by the second charge storage operation are read out from the pixel unit PU to the control circuit CC (column processing circuit 6) . The control circuit CC forwards the read-out pixel signals to the signal processing unit 23.

The signal processing unit 23 adds, for the pixels P1, the pixel signals for W read-out at the readout scan RD-1 and the pixel signals for W read-out at the readout scan RD-2 to generate pixel signals for W for one frame. The signal processing unit 23 uses, for the pixels P2, the pixel signals read-out at the readout scan RD-2 as pixel signals for R, G, and B for one frame. The signal processing unit 23 performs predetermined signal processing for each pixel signal and form them two-dimensionally, thereby generating image data. The signal processing unit 23 supplies the image data to the controller 24. The controller 24 thus can display an image (for example, a moving image or a still image) on a display screen (not shown) in accordance with the image data.

In a fifth modification of the embodiment, the imaging devices 2 and 2a may be able to perform readout scan in a multiple step manner.

The pixel array PA includes a pixel group PG3 in addition of the pixel group PG1 and the pixel group PG2. The pixel group PG1 includes two or more pixels P1 corresponding to a first color. The pixel group PG2 includes two or more pixels P2 corresponding to a second color. The second color is a color different from the first color. The pixel group PG3 includes two or more pixels P3 corresponding to a third color. The third color is a color different from the first color and different from the second color.

The first color corresponds to light of a first wavelength band. The second color corresponds to light of a second wavelength band. The third color corresponds to light of a third wavelength band. The first wavelength band may include the second wavelength band. The first wavelength band may include the third wavelength band. Each pixel P1 of the pixel group PG1 includes a first color filter. Each pixel P2 of the pixel group PG2 includes a second color filter. Each pixel P3 of the pixel group PG3 includes a third color filter. A transmission wavelength band of the first color filter may include a transmission wavelength band of the second color filter. The transmission wavelength band of the first color filter may include a transmission wavelength band of the third color filter. The first color may be white. The second color may be either red or blue. The third color may be green.

When the order of easiness of saturation for pixels in the pixel array PA are pixel P1 > pixel P3 > pixel P2, with the imaging device 2, the control circuit CC may change the number of readout scans between the pixel P1, the pixel P3, and the pixel P2, step by step, as illustrated in FIG. 15. In the one-frame period FT, the control circuit CC performs one reset-cancel scan RC for all the pixels P; performs readout scan for the pixels P1 divisionally by performing three readout scans, i.e., readout scans RD-1, RD-3, and RD-2; performs readout scan for the pixels P3 divisionally by performing two readout scans, i.e., readout scans RD-3 and RD-2; and performs one readout scan RD-2 for the pixels P2 of the pixel group PG2. The control circuit CC supplies pixel signals read-out at each of the readout scans to the signal processing unit 23.

With the imaging device 2, the signal processing unit 23 can obtain, for the pixels P1, pixel signals for one frame by adding pixel signals read-out by the divisional execution of the readout scans RD-1, RD-3, and RD-2. The signal processing unit 23 can obtain, for the pixels P3, pixel signals for one frame by adding pixel signals read-out by the divisional execution of the readout scans RD-3 and RD-2. The signal processing unit 23 can obtain, for the pixels P2, pixel signals for one frame that are read-out by the batch execution of the readout scan RD-2. With this configuration, it is possible to obtain pixel signals for one frame without increasing the frame rate, and it is possible to reduce the power consumed, while securing a wide dynamic range of the signals.

In this case, the readout scan RD-1 is performed for the pixels P1, the readout scan RD-3 is performed for the pixels P1 and the pixels P3, and the readout scan RD-2 is performed for the pixels P1, the pixels P3, and the pixels P2. The number of pixels for the readout scan RD-1 is smaller than the number of pixels for the readout scan RD-3. The number of pixels for the readout scan RD-3 is smaller than the number of pixels for readout scan RD-2. The imaging device 2 can perform the readout scan RD-1 as substantially down-sampled scan, perform the readout scan RD-3 as substantially down-sampled scan, and perform the readout scan RD-3 as all-row scan. The down-sampled scan indicates a scan down-sampled by thinning out some rows from plural rows. The down-sampling rate of the readout scan RD-1 may be higher than the down-sampling rate of the readout scan RD-3.

Accordingly, as illustrated in FIG. 15, the time RT-1 of the readout scan RD-1 is shorter than the time RT-3 of the readout scan RD-3. The time RT-3 of the readout scan RD-3 is shorter than the time RT-2 of the readout scan RD-2. Therefore, without increasing the operational frequency of the control circuit CC, the operational time of the control circuit CC for the readout scan RD can be shortened in a multiple step manner. The operational time of the control circuit CC for the readout scan RD-1 can be shortened than the operational time of the control circuit CC for the readout scan RD-3. The operational time of the control circuit CC for the readout scan RD-3 can be shortened than the operational time of the control circuit CC for the readout scan RD-2. As a result, it is possible to reduce the power consumed by the control circuit CC, as compared to operations in which the times for the readout scans RD are uniformly equal. In other words, it is possible to reduce the power consumed, while securing the dynamic range of the signals.

In a sixth modification of the embodiment, the pixel array PA may have configuration that enables charge addition of two or more pixels, as illustrated in FIG. 16 (a) , and the control circuit CC may be able to perform readout scan in a multiple step manner, as illustrated in FIG. 16 (b) .

In the pixel array PA, a first column and a second column are alternatively arranged along a row direction. Here, the first column may be defined as odd-numbered column when being counted from left side in FIG. 16. The second column may be defined as even-numbered column when being counted from left side in FIG. 16. In the first column, a pixel of the pixel group PG2 or PG3 and a pixel of the pixel group PG1 are alternatively arranged along a column direction. In the second column, a pixel of the pixel group PG1 and a pixel of the pixel group PG2 or PG3 are alternatively arranged along the column direction. A row position of the pixel group PG2 or PG3 in the first column corresponds to a row position of the pixel group PG1 in the second column. A row position of the pixel group PG1 in the first column corresponds to a row position of the pixel group PG2 or PG3 in the second column.

The pixel array PA corresponds to plural colors. The pixel group PG1 corresponds to the first color. The pixel group PG2 corresponds to the second color. The pixel group PG3 corresponds to the third color. In the case of FIG. 16, the first color is white, and the second color is any of red or blue. The third color is green. In other words, the pixel group PG1 includes W pixels, the pixel group PG2 includes R pixels and B pixels, and the pixel group PG3 includes G pixels.

The pixel array PA as illustrated in FIG. 16 (a) is similar to the pixel array PA as illustrated in FIG. 12 (a) . The unit array UA corresponds to a Bayer array, and it includes an R pixel unit PUr, a B pixel unit PUb, and two G pixel units PUg. The configuration of each pixel unit PU is similar to the configuration as illustrated in FIG. 13.

In the one-frame period FT as illustrated in FIG. 16 (b) , the control circuit CC performs, as all-row scan, the reset-cancel scan RC for the pixels P of each row in the pixel array PA. Thus, each pixel P (W pixels, R pixels, B pixels, and G pixels) in the pixel units PU of each row starts charge storage operation.

The control circuit CC performs the readout scan RD-1 for the pixels P1 (W pixels) as substantially down-sampled scan. The control circuit CC performs readout operation by performing charge addition of the respective W pixels in the R pixel unit PUr and the respective W pixels of the G pixel unit PUg of the first row. The control circuit CC performs readout operation by performing charge addition of the respective W pixels in the G pixel unit PUg and the respective W pixels of the B pixel unit PUb of the second row. The control circuit CC performs readout operation by performing charge addition of the respective W pixels in the R pixel unit PUr and the respective W pixels of the G pixel unit PUg of the third row. The control circuit CC performs readout operation by performing charge addition of the respective W pixels in the G pixel unit PUg and the respective W pixels of the B pixel unit PUb of the fourth row. Thus, the W pixels (photoelectric conversion units PDw) of the pixel units PU complete the first charge storage operation, and pixel signals corresponding to the charge stored by the first charge storage operation are read out from the pixel units PU to the control circuit CC. The control circuit CC transfers the read-out pixel signals to the signal processing unit 23. Along with that, the W pixels (photoelectric conversion units PDw) start second charge storage operation. At this moment, the R pixels, the G pixels, and the B pixels (photoelectric conversion units PDr, PDg, and PDb) of the pixel units PU continue the charge storage operation.

The control circuit CC performs the readout scan RD-3 for the pixels P1 (W pixels) and the pixels P3 (G pixels) as substantively down-sampled scan. The control circuit CC performs readout operation by performing charge addition of the respective W pixels in the R pixel unit PUr and the respective W pixels of the G pixel unit PUg of the first row. The control circuit CC performs readout operation by performing charge addition of the respective G pixels of the G pixel unit PUg of the first row. The control circuit CC performs readout operation by performing charge addition of the respective W pixels in the G pixel unit PUg and the respective W pixels of the B pixel unit PUb of the second row. The control circuit CC performs readout operation by performing charge addition of the respective G pixels in the G pixel unit PUg of the second row. The control circuit CC performs readout operation by performing charge addition of the respective W pixels in the R pixel unit PUr and the respective W pixels of the G pixel unit PUg of the third row. The control circuit CC performs readout operation by performing charge addition of the respective G pixels of the G pixel unit PUg of the third row. The control circuit CC performs readout operation by performing charge addition of the respective W pixels in the G pixel unit PUg and the respective W pixels of the B pixel unit PUb of the fourth row. The control circuit CC performs readout operation by performing charge addition of the respective G pixels in the G pixel unit PUg of the fourth row.

Thus, the W pixels (photoelectric conversion units PDw) of the pixel units PU complete the second charge storage operation, and pixel signals corresponding to the charge stored by the second charge storage operation are read out from the pixel units PU to the control circuit CC. The G pixels (photoelectric conversion units PDg) of the pixel units PU complete the first charge storage operation, and pixels signal corresponding to the charge stored by the first charge storage operation are read out from the pixel units PU to the control circuit CC. The control circuit CC forwards the read-out pixel signals to the signal processing unit 23. Along with that, the W pixels (photoelectric conversion units PDw) start third charge storage operation. The G pixels (photoelectric conversion units PDg) start second charge storage operation. At this moment, the R pixels and the B pixels (photoelectric conversion units PDr and PDb) of the pixel units PU continue the charge storage operation.

The control circuit CC performs the readout scan RD-2 for the pixels P of each row of the pixel array PA as all-row scan. The control circuit CC performs readout operation by performing charge addition of the respective W pixels in the R pixel unit PUr and the respective W pixels of the G pixel unit PUg of the first row. The control circuit CC performs readout operation by performing charge addition of the respective R pixels in the R pixel unit PUr and the respective G pixels of the G pixel unit PUg of the first row. The control circuit CC performs readout operation by performing charge addition of the respective W pixels in the G pixel unit PUg and the respective W pixels of the B pixel unit PUb of the second row. The control circuit CC performs readout operation by performing charge addition of the respective G pixels in the G pixel unit PUg and the respective B pixels of the B pixel unit PUb of the second row. The control circuit CC performs readout operation by performing charge addition of the respective W pixels in the R pixel unit PUr and the respective W pixels of the G pixel unit PUg of the third row. The control circuit CC performs readout operation by performing charge addition of the respective R pixels in the R pixel unit PUr and the respective G pixels of the G pixel unit PUg of the third row. The control circuit CC performs readout operation by performing charge addition of the respective W pixels in the G pixel unit PUg and the respective W pixels of the B pixel unit PUb of the fourth row. The control circuit CC performs readout operation by performing charge addition of the respective G pixels in the G pixel unit PUg and the respective B pixels of the B pixel unit PUb of the fourth row.

Thus, the pixels P1 (W pixels) complete the third charge storage operation, the pixels P3 (G pixels) complete the second charge storage operation, and the pixels P2 (R pixels and B pixels) complete the charge storage operation. Pixel signals for W corresponding to the charge stored by the third charge storage operation are read out from the pixel units PU to the control circuit CC (column processing circuit 6) . Pixel signals for G corresponding to the charge stored by the second charge storage operation are read out from the pixel units PU to the control circuit CC (column processing circuit 6) . Pixel signals for R and B corresponding to the charge stored by the charge storage operation are read out from the pixel units PU to the control circuit CC (column processing circuit 6) . The control circuit CC forwards the read-out pixel signals to the signal processing unit 23.

The signal processing unit 23 adds, for the pixels P1 (W pixels) , the pixel signals for W read-out at the readout scan RD-1, the pixel signals for W read-out at the readout scan RD-3, and the pixel signals for W read-out at the readout scan RD-2 to generate pixel signals for W for one frame. The signal processing unit 23 adds, for the pixels P3 (G pixels) , the pixel signals for G read-out at the readout scan RD-3 and the pixel signals for G read-out at the readout scan RD-2 to generate pixel signals for G for one frame. The signal processing unit 23 uses, for the pixels P2, the pixel signals read-out at the readout scan RD-2 as pixel signals for R and B for one frame. The signal processing unit 23 performs predetermined signal processing for each pixel signal and form them two-dimensionally, thereby generating image data. The signal processing unit 23 supplies the image data to the controller 24. The controller 24 thus can display an image (for example, a moving image or a still image) on a display screen (not shown) in accordance with the image data.

With the imaging device 2 as described above, the time RT-1 of the readout scan RD-1 is shorter than the time RT-3 of the readout scan RD-3. The time RT-3 of the readout scan RD-3 is shorter than the time RT-2 of the readout scan RD-2. Therefore, without increasing the operational frequency of the control circuit CC, the operational time of the control circuit CC for the readout scan RD can be shortened step by step. The operational time of the control circuit CC for the readout scan RD-1 can be shortened than the operational time of the control circuit CC for the readout scan RD-3. The operational time of the control circuit CC for the readout scan RD-3 can be shortened than the operational time of the control circuit CC for the readout scan RD-2. As a result, it is possible to reduce the power consumed by the control circuit CC, as compared to operations in which the times for the readout scans RD are uniformly equal. In other words, it is possible to reduce the power consumed, while securing the dynamic range of the signals.

In a seventh modification of the embodiment, it may be changeable in the pixel array PA between pixels P that are divisionally read-out and pixels P that are read-out in one batch. For example, operations may be performed as illustrated in FIG. 17 and FIG. 18. FIG. 17 is a timing chart illustrating operations of the control circuit according to the seventh modification of the embodiment. FIG. 18 is a diagram illustrating a process of determining pixel saturation according to the seventh modification of the embodiment.

In a frame period FT1, the control circuit CC performs the reset-cancel scan RC for the pixels P of each row of the pixel array PA as all-row scan. The control circuit CC performs the readout scan RD for the pixels P of each row of the pixel array PA as all-row scan. The control circuit CC forwards the read-out pixel signals to the signal processing unit 23. No divisional reading is performed in the frame period FT1.

The signal processing unit 23 determines, in accordance with color-based pixel signals that are read-out in the frame period FT1, whether the color-based pixel signals should be read-out divisionally or in one batch, as illustrated in FIG. 18.

For example, the signal processing unit 23 averages R pixel signals of all the R pixels, thereby calculating an R-pixel-signal amount. The signal processing unit 23 averages G pixel signals of all the G pixels, thereby calculating a G-pixel-signal amount. The signal processing unit 23 averages B pixel signals of all the B pixels, thereby calculating a B-pixel-signal amount. The signal processing unit 23 averages W pixel signals of all the W pixels, thereby calculating a W-pixel-signal amount. The signal processing unit 23 compares each of the R-pixel-signal amount, the G-pixel-signal amount, the B-pixel-signal amount, and the W-pixel-signal amount to a signal-amount threshold Ath.

When the pixel array PA includes W pixels, determination is performed as illustrated in FIG. 18 (a) to FIG. 18 (d) .

In a case of FIG. 18 (a) , the W-pixel-signal amount is above the signal-amount threshold Ath, and each of the R-pixel-signal amount, the G-pixel-signal amount, and the B-pixel-signal amount is below the signal-amount threshold Ath; therefore, the signal processing unit 23 determines that the W pixel is a saturated pixel and the R, G, and B pixels are non-saturated pixels. The saturated pixel is a pixel whose signal should be read-out divisionally. The non-saturated pixel is a pixel whose signal should be read-out in one batch.

In a case of FIG. 18 (b) , the R-pixel-signal amount is above the signal-amount threshold Ath, and each of the G-pixel-signal amount, the B-pixel-signal amount, and the W-pixel-signal amount is below the signal-amount threshold Ath; therefore, the signal processing unit 23 determines that the R pixel is a saturated pixel and the G, B, and W pixels are non-saturated pixels.

In a case of FIG. 18 (c) , the G-pixel-signal amount is above the signal-amount threshold Ath, and each of the R-pixel-signal amount, the B-pixel-signal amount, and the W-pixel-signal amount is below the signal-amount threshold Ath; therefore, the signal processing unit 23 determines that the G pixel is a saturated pixel and the R, B, and W pixels are non-saturated pixels.

In a case of FIG. 18 (d) , the B-pixel-signal amount is above the signal-amount threshold Ath, and each of the R-pixel-signal amount, the G-pixel-signal amount, and the W-pixel-signal amount is below the signal-amount threshold Ath; therefore, the signal processing unit 23 determines that the B pixel is a saturated pixel and the R, G, and W pixels are non-saturated pixels.

When the pixel array PA includes no W pixels, determination is performed as illustrated in FIG. 18 (e) to FIG. 18 (g) .

In a case of FIG. 18 (e) , the R-pixel-signal amount is above the signal-amount threshold Ath, and each of the G-pixel-signal amount and the B-pixel-signal amount is below the signal-amount threshold Ath; therefore, the signal processing unit 23 determines that the R pixel is a saturated pixel and the G and B pixels are non-saturated pixels.

In a case of FIG. 18 (f) , the G-pixel-signal amount is above the signal-amount threshold Ath, and each of the R-pixel-signal amount and the B-pixel-signal amount is below the signal-amount threshold Ath; therefore, the signal processing unit 23 determines that the G pixel is a saturated pixel and the R and B pixels are non-saturated pixels.

In a case of FIG. 18 (g) , the B-pixel-signal amount is above the signal-amount threshold Ath, and each of the R-pixel-signal amount and the G-pixel-signal amount is below the signal-amount threshold Ath; therefore, the signal processing unit 23 determines that the B pixel is a saturated pixel and the R and G pixels are non-saturated pixels.

The signal processing unit 23 generates a control signal in accordance with a determination result and supplies the control signal to the control circuit CC. The control circuit CC performs, among the color-based pixels in the pixel array PA, signal divisional-reading for pixels of a color determined to be the saturated pixels and signal batch-reading for pixels of colors determined to be the non-saturated pixels in accordance with the control signal.

For example, each pixel P may be designed to be switchable between the saturated pixel and the non-saturated pixel, as illustrated in FIG. 19. FIG. 19 is a circuit diagram illustrating configuration of the pixel P according to the seventh modification of the embodiment.

The control line group CL may further include a control line

The control line

supplies a control signal

Each pixel P1 further has a switching unit SW. When receiving the control signal

being at the active level from the row scanning circuit 4, the switching unit SW switches to the state as indicated by the solid lines such that the control signal

can be supplied to the transfer unit TX. Thus, the switching unit SW allows the pixel P to be operate as the saturated pixel. When receiving the control signal

being at the non-active level from the row scanning circuit 4, the switching unit SW switches to the state as indicated by the dotted lines such that the control signal

can be supplied to the transfer unit TX. Thus, the switching unit SW allows the pixel P to be operate as the non-saturated pixel.

Immediately before the frame period FT2 as illustrated in FIG. 17, the control circuit CC switches each pixel P to the saturated pixel or the non-saturated pixel in accordance with the control signal.

In the frame period FT2, the control circuit CC performs the reset-cancel scan RC for the saturated pixels P and the non-saturated pixels P as all-row scan. Thus, the saturated pixels P and the non-saturated pixels P each start charge storage operation.

The control circuit CC performs the readout scan RD-1 for the saturated pixels P as down-sampled scan. Thus, the saturated pixels P complete the first charge storage operation, and pixel signals corresponding to the charge stored by the first charge storage operation are read out from the saturated pixels P to the control circuit CC. The control circuit CC transfers the read-out pixel signals to the signal processing unit 23. Along with that, the saturated pixels P start second charge storage operation. At this moment, the non-saturated pixels P continue the charge storage operation.

The control circuit CC performs the readout scan RD-2 for the saturated pixels P and the non-saturated pixels P as all-row scan. Thus, the saturated pixels P complete the second charge storage operation, and the non-saturated pixels P complete the charge storage operation. Pixel signals corresponding to the charge stored by the second charge storage operation are read out from the saturated pixels P to the control circuit CC (column processing circuit 6) . The control circuit CC transfers the read-out pixel signals to the signal processing unit 23. Pixel signals corresponding to the charge stored by the charge storage operation are read out from the non-saturated pixels P to the control circuit CC (column processing circuit 6) . The control circuit CC transfers the read-out pixel signals to the signal processing unit 23.

The signal processing unit 23 adds, for the saturated pixels P, the pixel signals read-out at the readout scan RD-1 and the pixel signals read-out at the readout scan RD-2 to generate pixel signals for one frame. The signal processing unit 23 uses, for the non-saturated pixels P, the pixel signals read-out at the readout scan RD-2 as pixel signals for one frame. The signal processing unit 23 performs predetermined signal processing for each pixel signal and form them two-dimensionally, thereby generating image data. The signal processing unit 23 supplies the image data to the controller 24. The controller 24 thus can display an image (for example, a moving image or a still image) on a display screen (not shown) in accordance with the image data.

The same operation is performed also in a frame period FT3, as performed in the frame period FT2

In an eighth modification of the embodiment, it may be changeable for each partial region in the pixel array PA between pixels P that are divisionally read-out and pixels P that are read-out in one batch.

For example, when a frame image FI captured by the imaging device 2 includes plural partial images PI-1 to PI-4 as illustrated in FIG. 20, with the imaging device 2, it may be changeable for each of the partial images PI-1 to PI-4 between pixels P that are divisionally read-out and pixels P that are read-out in one batch. FIG. 20 is a diagram illustrating configuration of the frame image FI according to the eighth modification of the embodiment.

The pixel array PA includes plural partial pixel regions PR-1 to PR-4, as illustrated in FIG. 2 those surrounded by the dotted lines. The plural partial pixel regions PR-1 to PR-4 corresponds to the plural partial images PI-1 to PI-4.

At this moment, similar operations to those illustrated in FIGS. 17 and 18 may be performed for each of the partial pixel regions PR-1 to PR-4.

In the frame period FT1, the control circuit CC performs the reset-cancel scan RC for the pixels P of each row in the pixel array PA as all-row scan. The control circuit CC performs the readout scan RD for the pixels P of each row in the pixel array PA as all-row scan. The control circuit CC forwards the read-out pixel signals to the signal processing unit 23. No divisional reading is performed in the frame period FT1.

The signal processing unit 23 calculates, for each partial pixel region PR, an amount of color-based pixel signals that are read-out in the frame period FT1, as illustrated in FIG. 18. The signal processing unit 23 determines, for each partial pixel region PR, whether the color-based pixel signals should be read-out divisionally or in one batch in accordance with the amount of color-based pixel signals.

When the partial pixel region PR-1 includes W pixels, determination is performed as illustrated in FIG. 18 (a) to FIG. 18 (d) . When the partial pixel region PR-1 includes no W pixels, determination is performed as illustrated in FIG. 18 (e) to FIG. 18 (g) .

When the partial pixel region PR-4 includes W pixels, determination is performed as illustrated in FIG. 18 (a) to FIG. 18 (d) . When the partial pixel region PR-4 includes no W pixels, determination is performed as illustrated in FIG. 18 (e) to FIG. 18 (g) .

For example, in each of the partial pixel regions PR-1 to PR-4, each pixel P may be designed to be switchable between the saturated pixel and the non-saturated pixel, as illustrated in FIG. 19. In such a case, for each pixel P in each of the partial pixel regions PR-1 to PR-4, the switching unit SW may be connected to a control line

different from a control line connected to another partial pixel region PR so that the switching unit SW can be controlled independently from another switching unit SW of the another partial pixel region PR.

Immediately before the frame period FT2 as illustrated in FIG. 17, the control circuit CC switches, for each partial pixel region PR, each pixel P to the saturated pixel or the non-saturated pixel in accordance with the control signal. The control circuit CC switches each pixel P of the partial pixel region PR-1 to the saturated pixel or the non- saturated pixel in accordance with the control signal. The control circuit CC switches each pixel P of the partial pixel region PR-4 to the saturated pixel or the non-saturated pixel in accordance with the control signal.

The operations subsequent to the frame period FT2 are similar to those in the seventh modification of the embodiment.

In a ninth modification of the embodiment, it may be changeable in the pixel array PA between pixels P that are divisionally read-out and pixels P that are read-out in one batch by means of cooperation between plural imaging devices, e.g., the imaging devices 2 and 2a.

When, for example, the angle of view of the optical system 21a of the imaging device 2a is wider than the angle of view of the optical system 21 of the imaging device 2, the imaging device 2a acquires a frame FIa as illustrated in FIG. 21 (a) , and the imaging device 2 acquires a frame FI as illustrated in FIG. 21 (b) . The frame image FIa includes a partial image PIa that corresponds to the frame image FI. Due to this, the controller 24 of the imaging device 2 as illustrated in FIG. 1 acquires data of the frame image FIa from the controller 24a of the imaging device 2a and cuts the partial image PIa out from the frame image FIa. The controller 24 supplies the partial image PIa to the signal processing unit 23. The signal processing unit 23 determines whether the color-based pixel signals should be read-out divisionally or in one batch in accordance with the amount of signals of color-based pixels in the partial image PIa.

At this moment, similar operations to those illustrated in FIGS. 17 and 18 may be performed.

In the frame period FT1, in the imaging device 2a, the control circuit CC performs the reset-cancel scan RC for the pixels P of each row in the pixel array PA as all-row scan. The control circuit CC performs the readout scan RD for the pixels P of each row in the pixel array PA as all-row scan. The control circuit CC transfers the read-out pixel signals to the signal processing unit 23. No divisional reading is performed in the frame period FT1.

In the imaging device 2a, the signal processing unit 23a performs predetermined signal processing for the pixel signal of each pixel P and form them two-dimensionally, thereby generating data of the frame image FIa, and then supplies the data to the controller 24a. The controller 24a supplies the data of the frame image FIa to the controller 24 of the imaging device 2. The controller 24 cuts out the partial image PIa out from the frame image FIa. The controller 24 supplies the partial image PIa to the signal processing unit 23.

In the imaging device 2, the signal processing unit 23 may calculate an amount of color-based pixel signals in the partial image PIa, as illustrated in FIG. 18. The signal processing unit 23 may determine whether the color-based pixel signals should be read-out divisionally or in one batch in accordance with the amount of color-based pixel signals.

When the pixel array PA includes W pixels, determination is performed as illustrated in FIG. 18 (a) to FIG. 18 (d) . When the pixel array PA includes no W pixels, determination is performed as illustrated in FIG. 18 (e) to FIG. 18 (g) .

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

[Explanations of Letters or Numerals]

1 imaging system

2, 2a imaging device

21, 21a optical system

22, 22a image sensor

23, 23a signal processing unit

24, 24a controller

CC control circuit

P, P (1, 1) to P (8, 8) pixel

PA pixel array

PG1, PG2, PG3 pixel group

PR, PR-1 to PR-4 partial pixel region

Claims

An imaging device comprising:

a pixel array in which plural pixels are arrayed to form plural rows and plural columns, the pixel array including a first pixel group and a second pixel group, the first pixel group including two or more pixels each corresponding to a first color among the plural pixels, and the second pixel group including two or more pixels each corresponding to a second color among the plural pixels; and

a control circuit configured to perform a readout scan to, while selecting the plural rows sequentially, read out a pixel signal from a pixel of each column included in a selected row, wherein

the control circuit performs a first readout scan to read out pixel signals from pixels of the first pixel group and performs a second readout scan to read out pixel signals from pixels of the first pixel group and the second pixel group in a one-frame period.
The imaging device according to claim 1, wherein

the number of the pixels for the first readout scan is smaller than the number of the pixels for the second readout scan.
The imaging device according to claim 1, wherein

in the pixel array, a first column and a second column are alternatively arranged along a row direction,

in the first column, a pixel of the second pixel group and a pixel of the first pixel group are alternatively arranged along a column direction, and

in the second column, the pixels of the second pixel group are arranged along the column direction.
The imaging device according to claim 1, wherein

in the pixel array, a first column and a second column are alternatively arranged along a row direction,

in the first column, a pixel of the second pixel group and a pixel of the first pixel group are alternatively arranged along a row direction, and

in the second column, a pixel of the second pixel group and a pixel of the first pixel group are alternatively arranged along the row direction,

a row position of the second pixel group in the first column corresponds to a row position of the second pixel group in the second column,

a row position of the first pixel group in the first column corresponds to a row position of the first pixel group in the second column.
The imaging device according to claim 1, wherein

in the pixel array, a first column and a second column are alternatively arranged along a row direction,

in the first column, a pixel of the second pixel group and a pixel of the first pixel group are alternatively arranged along a column direction, and

in the second column, a pixel of the first pixel group and a pixel of the second pixel group are alternatively arranged along the column direction

a row position of the second pixel group in the first column corresponds to a row position of the first pixel group in the second column,

a row position of the first pixel group in the first column corresponds to a row position of the second pixel group in the second column.
The imaging device according to claim 1, wherein

the control circuit further performs, before the first readout scan and the second readout scan, a reset cancel scan to cancel of the pixels of the first pixel group and the second pixel group in the one-frame period.
The imaging device according to claim 6, wherein

the number of the pixels for the first readout scan is smaller than the number of the pixels for the reset cancel scan.
The imaging device according to claim 6, wherein

the number of rows where the pixels for the first readout scan are arranged is smaller than the number of rows where the pixels for the reset cancel scan are arranged.
The imaging device according to claim 1, wherein

an easiness of light of the first color to saturate a pixel of the first pixel group is larger than an easiness of light of the second color to saturate a pixel of the second pixel group.
The imaging device according to claim 1, wherein

each pixel of the first pixel group includes a first color filter,

each pixel of the second pixel group includes a second color filter, and

the first color filer is transmittable with more amount of light than the second color filter.
The imaging device according to claim 9, wherein

the first color corresponds to light of a first wavelength band,

the second color corresponds to light of a second wavelength band, and

the first wavelength band includes the second wavelength band.
The imaging device according to claim 11, wherein

the first color is white, and

the second color is any of red, green, or blue.
The imaging device according to claim 10, wherein

each pixel of the first pixel group includes a first color filter,

each pixel of the second pixel group includes a second color filter, and

a maximum transmittance of the first color filter is higher than a maximum transmittance of the second color filter.
The imaging device according to claim 13, wherein

the first color is white, and

the second color is any of red, green, or blue.
The imaging device according to claim 13, wherein

the first color is green, and

the second color is either red or blue.
The imaging device according to claim 1, wherein

the imaging device determines whether the pixel signals of the first pixel group is to be read-out either divisionally or in one batch in accordance with an amount of pixel signals of the first pixel group that have been read-out in a first frame period,

when the pixel signals of the first pixel group are determined to be read-out divisionally, the control circuit reads out the pixel signals of the first pixel group in a second frame period divisionally by performing the first readout scan and the second readout scan, and

when the pixel signals of the first pixel group are determined to be read-out in one batch, the control circuit reads out the pixel signals of the first pixel group in the second frame period in one batch by performing the second readout scan.
The imaging device according to claim 1, wherein

the pixel array is divided into plural regions,

the imaging device determines, for each of the plural regions, whether the pixel signals of the first pixel group is to be read-out either divisionally or in one batch in accordance with an amount of pixel signals of the first pixel group that have been read-out in a first frame period, and

the control circuit reads out the pixel signals of the first pixel group in a second frame period,

for a region determined to be read-out divisionally, divisionally by performing the first readout scan and the second readout scan, and

for a region determined to be read-out in one batch, in one batch by performing the second readout scan.
The imaging device according to claim 1, wherein

the imaging device determines whether the pixel signals of the first pixel group is to be read-out either divisionally or in one batch in accordance with an amount of pixel signals of a fourth pixel group that have been read-out from a second imaging device in a first frame period,

wherein the second imaging device includes a pixel array including the fourth pixel group and a fifth pixel group, the fourth pixel group corresponding to the first pixel group, and the fifth pixel group corresponding to the second pixel group,

when the pixel signals of the first pixel group are determined to be read-out divisionally, the control circuit reads out the pixel signals of the first pixel group in a second frame period divisionally by performing the first readout scan and the second readout scan, and

when the pixel signals of the first pixel group are determined to be read-out in one batch, the control circuit reads out the pixel signals of the first pixel group in the second frame period in one batch by performing the second readout scan.
An imaging system comprising:

a first imaging device that is the imaging device according to claim 1;

a first optical system configured to form an object image on an imaging surface of the first imaging device;

a second imaging device; and

a second optical system configured to form an object image on an imaging surface of the second imaging device, wherein

the first imaging device includes a pixel array in which plural pixels are arrayed to form plural rows and plural columns, the pixel array including a first pixel group and a second pixel group, the first pixel group including two or more pixels each corresponding to a first color among the plural pixels, and the second pixel group including two or more pixels each corresponding to a second color among the plural pixels,

the second imaging device includes a pixel array including a fourth pixel group and a fifth pixel group, the fourth pixel group corresponding to the first pixel group, and the fifth pixel group corresponding to the second pixel group,

the first imaging device determines whether pixel signals of the first pixel group is to be read-out either divisionally or in one batch in accordance with an amount of pixel signals of the fourth pixel group that have been read-out from the pixel array of the second imaging device in a first frame period, and

the first imaging device further includes a control circuit configured to

when the pixel signals of the first pixel group are determined to be read-out divisionally, read out the pixel signals of the first pixel group in a second frame period divisionally by performing the first readout scan and the second readout scan, and

when the pixel signals of the first pixel group are determined to be read-out in one batch, read out the pixel signals of the first pixel group in the second frame period in one batch by performing the second readout scan.
The imaging system according to claim 19, wherein

an angle of view of the second optical system is wider than an angle of view of the first optical system, and

the first imaging device determines whether the pixel signals of the first pixel group is to be read-out either divisionally or in one batch in accordance with an amount of pixel signals of the fourth pixel group that have been read-out from a region of the pixel array of the second imaging device in the first frame period, the region corresponding to the angle of view of the first optical system.