WO2024092550A1

WO2024092550A1 - Quality improvement method and apparatus for semiconductor device, and high-energy particle beam photolithography device

Info

Publication number: WO2024092550A1
Application number: PCT/CN2022/129218
Authority: WO
Inventors: 张洁; 张启华; 简维廷; 洪流; 袁元; 张勇为; 蒋军浩; 汪俊亮
Original assignee: 东华大学; 洪启集成电路(珠海)有限公司
Priority date: 2022-11-02
Filing date: 2022-11-02
Publication date: 2024-05-10
Also published as: CN117397002A

Abstract

The present invention relates to a quality improvement method and apparatus for a semiconductor device, and a high-energy particle beam photolithography device. The method comprises: acquiring connected regions consisting of target pixel points in grayscale images and the width of each connected region; according to a width interval where the width of each connected region is located and a correspondence between the width interval and a high-energy particle beam spot size, acquiring a target high-energy particle beam spot value when a high-energy particle beam photolithography device engraves a pattern corresponding to each connected region; and according to a correspondence between a preset high-energy particle beam processing parameter corresponding to the target high-energy particle beam spot value and a grayscale value, acquiring high-energy particle beam processing parameters corresponding to pixel points in each connected region. In this way, a larger high-energy particle beam spot is used when the high-energy particle beam photolithography device engraves a connected region having a larger width, and a smaller high-energy particle beam spot is used when the high-energy particle beam photolithography device engraves a connected region having a smaller width. Compared with the prior art, the method ensures the processing efficiency while improving the processing precision of the semiconductor device.

Description

Semiconductor device quality improvement method, device and high-energy particle beam lithography equipment

Technical Field

The embodiments of the present application relate to the field of semiconductor processing technology, and in particular, to a method and device for improving the quality of semiconductor devices and a high-energy particle beam lithography device.

Background technique

In the field of traditional semiconductor processing technology, it is often based on the combination of integrated circuit mask and photolithography technology to achieve the transfer of integrated circuit layout to silicon substrate, thereby completing the manufacture of semiconductor devices.

However, as the requirements for the size of semiconductor devices become increasingly higher, the manufacture of light source systems that support lithography technology (such as EUV lithography machines) and the production of integrated circuit masks have become increasingly difficult. The use of integrated circuit masks will also make the manufacturing cost of semiconductor devices huge. Moreover, if the integrated circuit layout is modified or fine-tuned, the mask needs to be remade, resulting in low processing efficiency.

The high-energy particle beam in this application can be an ion beam, electron beam, laser beam, X-ray, etc., among which the experiment uses a high-energy focused ion beam. High-energy particle beams have a smaller wavelength than ordinary optical systems, which can improve the resolution of layout transfer and are suitable for making smaller devices. For example, due to wavelength limitations, DUV lithography machines are only suitable for making devices with feature sizes greater than 7nm; for the production of devices below 7nm, EUV must be introduced. High-energy particle beams have a smaller wavelength than EUV.

Summary of the invention

The embodiment of the present application provides a method and device for improving the quality of semiconductor devices and a high-energy particle beam lithography device, which can complete the processing of semiconductor devices without making integrated circuit masks and improve the processing accuracy. The technical solution is as follows:

In a first aspect, an embodiment of the present application provides a method for improving the quality of a semiconductor device, comprising:

Acquire an integrated circuit layout corresponding to the target semiconductor device; wherein the integrated circuit layout includes several layers of integrated circuit sub-layouts, and each layer of the integrated circuit sub-layout corresponds to a pattern of one or more material layers of the target semiconductor device;

Converting the integrated circuit sub-layouts of the plurality of layers into grayscale images of a preset format respectively;

Obtaining each connected region composed of target pixel points in the grayscale image and the width of each connected region; wherein the grayscale value of the target pixel point in each connected region is within the same preset grayscale value range;

According to the width interval where the width of each of the connected areas is located and the correspondence between the preset width interval and the beam spot size of the high-energy particle beam, a target high-energy particle beam spot value is obtained when the high-energy particle beam lithography device carves a pattern corresponding to each of the connected areas;

According to the correspondence between the preset high-energy particle beam processing parameters corresponding to the target high-energy particle beam spot value and the grayscale value, the high-energy particle beam processing parameters corresponding to the pixel points in each connected area in the grayscale image are obtained;

Each corresponding material layer is sequentially manufactured on the target substrate, and the electromagnetic lens in the high-energy particle beam lithography equipment is adjusted to control the size of the high-energy particle beam spot according to the target high-energy particle beam spot value corresponding to each connected area in the grayscale image of each layer, so that the spot value of the high-energy particle beam for engraving the connected area is the target high-energy particle beam spot value, and then according to the high-energy particle beam processing parameters corresponding to each pixel point in the connected area, the high-energy particle beam lithography equipment is controlled to emit the high-energy particle beam and act on the position corresponding to the connected area in the corresponding material layer, and the pattern corresponding to each connected area in the grayscale image of each layer is engraved to the corresponding material layer to obtain the target semiconductor device.

In a second aspect, an embodiment of the present application provides a semiconductor device quality improvement device, comprising:

A layout acquisition unit, used to acquire an integrated circuit layout corresponding to a target semiconductor device; wherein the integrated circuit layout includes a plurality of layers of integrated circuit sub-layouts, each layer of the integrated circuit sub-layout corresponds to a pattern of one or more material layers of the target semiconductor device;

A layout conversion unit, used to convert the integrated circuit sub-layouts of several layers into grayscale images of a preset format respectively;

A connected region acquisition unit, used to acquire each connected region composed of target pixel points in the grayscale image and the width of each connected region; wherein the grayscale value of the target pixel point in each connected region is within the same preset grayscale value range;

A beam spot value acquisition unit, used for acquiring a target high-energy particle beam spot value when the high-energy particle beam lithography device engraves a pattern corresponding to each of the connected areas according to a width interval in which the width of each of the connected areas is located and a correspondence between a preset width interval and a beam spot size of the high-energy particle beam;

a processing parameter acquisition unit, configured to acquire the high-energy particle beam processing parameter corresponding to each pixel point in the connected area in the grayscale image according to a correspondence between a preset high-energy particle beam processing parameter corresponding to the target high-energy particle beam spot value and a grayscale value;

A processing control unit is used to sequentially manufacture each corresponding material layer on a target substrate, and adjust an electromagnetic lens in a high-energy particle beam lithography device to control the size of a high-energy particle beam spot according to target high-energy particle beam spot values corresponding to each connected area in the grayscale image of each layer, so that the spot value of the high-energy particle beam for engraving the connected area is the target high-energy particle beam spot value, and then control the high-energy particle beam lithography device to emit a high-energy particle beam and act on a position corresponding to the connected area in a corresponding material layer according to high-energy particle beam processing parameters corresponding to each pixel point in the connected area, and engrave patterns corresponding to each connected area in the grayscale image of each layer to the corresponding material layer to obtain the target semiconductor device.

In a third aspect, an embodiment of the present application provides a high-energy particle beam lithography device, comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the steps of the semiconductor device quality improvement method as described in the first aspect are implemented.

In the embodiment of the present application, the integrated circuit sub-layout is converted into several layers of grayscale images, each connected area composed of target pixel points in the grayscale image and the width of each connected area are obtained, and according to the width interval where the width of each connected area is located and the correspondence between the preset width interval and the high-energy particle beam spot size, the target high-energy particle beam spot value when the high-energy particle beam lithography device engraves the pattern corresponding to each connected area is obtained, and then according to the correspondence between the preset high-energy particle beam processing parameters corresponding to the target high-energy particle beam spot value and the grayscale value, the high-energy particle beam processing parameters corresponding to the pixel points in each connected area in the grayscale image are obtained. After that, each corresponding material layer is sequentially manufactured on the target substrate, and the electromagnetic lens in the high-energy particle beam lithography equipment is adjusted to control the size of the high-energy particle beam spot value according to the target high-energy particle beam spot value corresponding to each connected area in the grayscale image of each layer, so that the spot value of the high-energy particle beam in the engraved connected area is the target high-energy particle beam spot value, and then according to the high-energy particle beam processing parameters corresponding to each pixel point in the connected area, the high-energy particle beam lithography equipment is controlled to emit the high-energy particle beam and act on the corresponding position of the connected area in the corresponding material layer, and the pattern corresponding to each connected area in the grayscale image of each layer is engraved to the corresponding material layer to obtain the target semiconductor device. This method for improving the quality of semiconductor devices not only does not require the production of masks, thus saving production costs, but can also flexibly modify the integrated circuit layout and improve the processing efficiency of semiconductor devices. In addition, by obtaining the width of the connected area in each layer of grayscale images, the size of the high-energy particle beam spot during engraving is adjusted, so that when the high-energy particle beam equipment is engraving a connected area with a larger width, a larger high-energy particle beam spot will be used, thereby shortening the processing time, and when engraving a connected area with a smaller width, a smaller high-energy particle beam spot will be used, thereby further improving the device processing accuracy.

For better understanding and implementation, the technical solution of the present application is described in detail below with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic flow chart of a method for improving the quality of a semiconductor device provided by an embodiment of the present application;

FIG. 2 is a schematic diagram of a flow chart of S103 in a method for improving the quality of a semiconductor device provided by an embodiment of the present application;

FIG3 is a schematic flow chart of S103 in a method for improving the quality of a semiconductor device provided by another embodiment of the present application;

FIG. 4 is a schematic diagram of a flow chart of S104 in a method for improving the quality of a semiconductor device provided by an embodiment of the present application;

FIG. 5 is a schematic diagram of a flow chart of S106 in a method for improving the quality of a semiconductor device provided by an embodiment of the present application;

FIG6 is a schematic structural diagram of a semiconductor device quality improvement device provided by an embodiment of the present application;

FIG. 7 is a schematic diagram of the structure of a high-energy particle beam lithography device provided in one embodiment of the present application.

Detailed ways

Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and/or" used in this article refers to and includes any or all possible combinations of one or more associated listed items.

It should be understood that, although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if"/"if" as used herein may be interpreted as "at the time of" or "when" or "in response to determination".

Please refer to FIG. 1 , which is a flow chart of a method for improving the quality of a semiconductor device provided by an embodiment of the present application. The method comprises the following steps:

S101: Obtain an integrated circuit layout corresponding to a target semiconductor device; wherein the integrated circuit layout includes several layers of integrated circuit sub-layouts, and each layer of the integrated circuit sub-layout corresponds to a pattern of one or more material layers of the target semiconductor device.

In an optional embodiment, the executor of the semiconductor device quality improvement method may be a high-energy particle beam lithography device, or a component in the high-energy particle beam lithography device, such as a processor or microprocessor inside the device; in another optional embodiment, the executor of the semiconductor device quality improvement method may be an external device that establishes a data connection with the high-energy particle beam lithography device, or a component in the external device.

In an embodiment of the present application, the execution body of the semiconductor device quality improvement method is a high-energy particle beam lithography device.

Specifically, the high-energy particle beam lithography equipment obtains the integrated circuit layout corresponding to the target semiconductor device.

The target semiconductor device may be any type of semiconductor device, and its specific type is not limited herein.

The integrated circuit layout refers to mapping the circuit design circuit diagram or circuit description language to the physical description level. The integrated circuit layout includes relevant physical information such as the device type, device size, relative position between devices, and connection relationship between each device of the integrated circuit.

The integrated circuit layout includes several layers of integrated circuit sub-layouts, and each layer of the integrated circuit sub-layout corresponds to the pattern of a material layer of the target semiconductor device.

In the embodiment of the present application, the material layer includes but is not limited to an active layer, an insulating layer, a polysilicon gate layer, a metal layer, and the like.

S102: Converting the integrated circuit sub-layouts of the plurality of layers into grayscale images of a preset format respectively.

The high-energy particle beam lithography equipment converts several layers of the integrated circuit sub-layouts into grayscale images in a preset format.

In an optional embodiment, the preset format is a TIF format. In other optional embodiments, the preset format may be other image formats that can be recognized and processed by a high-energy particle beam lithography device.

The grayscale value of the pixel in the grayscale image is 0 to 255, where a grayscale value of 0 indicates that the pixel has a lower brightness, and the human body subjectively perceives it as black, and a grayscale value of 255 indicates that the pixel has a higher brightness, and the human body subjectively perceives it as white.

S103: Obtain each connected area composed of target pixels in the grayscale image and the width of each connected area; wherein the grayscale values of the target pixels in each connected area are within the same preset grayscale value range.

In the field of image processing, connected regions include two types, one is an eight-connected region and the other is a four-connected region. In the embodiment of the present application, the connected region obtained is a four-connected region, that is, when determining whether it is connected, only whether there are connected pixels in the four directions of up, down, left and right of the pixel point is determined.

In an optional embodiment, when obtaining the four-connected area in a picture, it can be first determined whether the first adjacent pixel points (pixels directly adjacent in position) of a certain pixel point in the four directions of up, down, left and right are connected. If so, the connected first adjacent pixel point is added to the connected area of the pixel point, and then it is determined whether the second adjacent pixel points (pixels indirectly adjacent in position) of the first adjacent pixel point in the four directions of up, down, left and right are connected. If so, the connected second adjacent pixel point is added to the connected area of the pixel point, and then it is determined whether the third adjacent pixel points in the four directions of up, down, left and right of the second adjacent pixel point are connected, and so on, until no adjacent pixel points can be added to the connected area of the pixel point.

Afterwards, a pixel point is randomly selected again from the pixel points outside the above connected area, and the above steps are repeated to obtain the connected area of the pixel point until all the pixel points have been added to each connected area, and each four-connected area in the image is obtained.

It should be noted that the above detailed steps of obtaining the four-connected regions in a picture are only an example and have no limiting effect.

In the embodiment of the present application, the criterion for determining whether connectivity is possible is whether the grayscale values of the pixels are within the same preset grayscale value range.

The preset gray value interval is pre-set in the high-energy particle beam lithography device, and only the pixel points with gray values in the same gray value interval can be divided into the same connected area.

In an optional embodiment, to obtain each connected area composed of target pixels in the grayscale image, please refer to FIG. 2 , step S103 includes step S1031, which is as follows:

S1031: According to the grayscale value of each pixel point of the grayscale image and the position of each pixel point in the grayscale image, target pixel points that are adjacent in position and whose grayscale values are in the same preset grayscale value range are divided into one of the connected areas; wherein the adjacent positions include directly adjacent positions and indirectly adjacent positions.

The high-energy particle beam lithography equipment first obtains the grayscale value of each pixel in the image and the position of each pixel in the grayscale image, and then divides the target pixel points with adjacent positions and grayscale values in the same preset grayscale value range into one of the connected areas according to the preset four-connected area acquisition algorithm, and finally obtains each connected area in the grayscale image.

The preset four-connected region acquisition algorithm may be the algorithm provided in an optional embodiment described above, or may be other feasible algorithms, which are not limited here.

In an optional embodiment, to accurately obtain the width of the connected area, please refer to FIG. 3 , step S103 includes steps S1032 to S1034, which are as follows:

S1032: Obtain the number of target pixels in each row in the connected area.

The high-energy particle beam lithography equipment obtains the number of target pixel points located in the same row according to the positions of the target pixel points in the connected area.

S1033: Obtain the width of each row in the connected area according to the number of target pixel points in each row and the width of each target pixel point.

The high-energy particle beam lithography equipment multiplies the width of each target pixel by the number of target pixels in each row to obtain the width of each row in the connected area.

S1034: Obtain the width of the connected area according to the average value of the width of each row in the connected area.

The widths of the rows in the connected region are averaged, and the obtained average is used as the width of the connected region.

The smaller the width of the connected region is, the higher the precision required by the high-energy particle beam lithography equipment when engraving the pattern in the connected region is.

S104: According to the width interval of each of the connected regions and the correspondence between the preset width interval and the high-energy particle beam spot size, a target high-energy particle beam spot value is obtained when the high-energy particle beam lithography device engraves a pattern corresponding to each of the connected regions.

In the high-energy particle beam lithography equipment, a number of width intervals and a corresponding relationship between each width interval and the size of the high-energy particle beam spot are preset.

The high-energy particle beam lithography equipment obtains the target high-energy particle beam spot value when the high-energy particle beam lithography equipment engraves the pattern corresponding to each of the connected areas according to the width interval of the width of each of the connected areas and the correspondence between the preset width interval and the high-energy particle beam spot size.

Specifically, referring to FIG. 4 , step S104 includes steps S1041 to S1042, which are specifically as follows:

S1041: When the endpoint value of the width interval where the width of the connected area is located is larger, the target high-energy particle beam spot value when the high-energy particle beam lithography device carves a pattern corresponding to the connected area is larger.

S1042: When the endpoint value of the width interval in which the width of the connected area is located is smaller, the target high-energy particle beam spot value when the high-energy particle beam lithography device carves a pattern corresponding to the connected area is smaller.

The interval endpoint value may be the left endpoint value of the width interval or the right endpoint value of the width interval.

S105: According to the correspondence between the preset high-energy particle beam processing parameters corresponding to the target high-energy particle beam spot value and the grayscale value, the high-energy particle beam processing parameters corresponding to the pixel points in each connected area in the grayscale image are obtained.

In an optional embodiment, the correspondence between the preset high-energy particle beam processing parameters and the grayscale values can be preset and stored in the high-energy particle beam lithography equipment. In another optional embodiment, the correspondence between the preset high-energy particle beam processing parameters and the grayscale values can be preset and stored in the cloud or host computer, and then downloaded to the high-energy particle beam lithography equipment when used.

As the beam spot of the high-energy particle beam is smaller and other control conditions remain unchanged, it will take longer for the high-energy particle beam to carve away the same amount of material. Therefore, it is necessary to set different corresponding relationships between high-energy particle beam processing parameters and grayscale values according to different values of the beam spot of the high-energy particle beam.

Specifically, the correspondence between the preset high-energy particle beam processing parameters and the grayscale values can be stored in the high-energy particle beam lithography equipment, the cloud or the host computer, and the high-energy particle beam lithography equipment can search for the correspondence between the corresponding high-energy particle beam processing parameters and the grayscale values according to the target high-energy particle beam spot value.

In an optional embodiment, the high-energy particle beam processing parameters include high-energy particle beam acceleration voltage and/or high-energy particle beam action time.

In order to process semiconductor devices more accurately, the high-energy particle beam lithography equipment obtains the high-energy particle beam processing parameters corresponding to each pixel point in each connected area in the grayscale image according to the corresponding relationship between the preset high-energy particle beam processing parameters corresponding to the target high-energy particle beam spot value and the grayscale value, as follows:

The high-energy particle beam lithography device obtains the high-energy particle beam acceleration voltage corresponding to each pixel point in each connected area in the grayscale image according to the grayscale value of the pixel point in each connected area in the grayscale image. When the grayscale value of the pixel point in each connected area in the grayscale image is smaller, the high-energy particle beam acceleration voltage of the high-energy particle beam lithography device is higher; when the grayscale value of the pixel point in each connected area in the grayscale image is larger, the high-energy particle beam acceleration voltage of the high-energy particle beam lithography device is lower.

Alternatively, the high-energy particle beam lithography device obtains the high-energy particle beam action time corresponding to each pixel point in each connected area in the grayscale image according to the grayscale value of the pixel point in each connected area in the grayscale image. When the grayscale value of the pixel point in each connected area in the grayscale image is smaller, the high-energy particle beam action time of the high-energy particle beam lithography device is longer; when the grayscale value of the pixel point in each connected area in the grayscale image is larger, the high-energy particle beam action time of the high-energy particle beam lithography device is shorter.

Alternatively, the high-energy particle beam lithography device obtains the grayscale mean value of all pixels in each of the connected areas in the grayscale image. When the grayscale mean value is smaller, the high-energy particle beam acceleration voltage of the high-energy particle beam lithography device is made higher, and according to the grayscale values of the pixels in each of the connected areas in the grayscale image, the high-energy particle beam action time corresponding to each pixel in each of the connected areas in the grayscale image is obtained when the high-energy particle beam acceleration voltage remains unchanged. When the grayscale value of the pixel in each of the connected areas in the grayscale image is smaller, the high-energy particle beam action time of the high-energy particle beam lithography device is made longer; when the grayscale value of the pixel in each of the connected areas in the grayscale image is larger, the high-energy particle beam action time of the high-energy particle beam lithography device is made shorter.

S106: According to the correspondence between the preset high-energy particle beam processing parameters corresponding to the target high-energy particle beam spot value and the grayscale value, the high-energy particle beam processing parameters corresponding to the pixel points in each connected area in the grayscale image are obtained; each corresponding material layer is sequentially manufactured on the target substrate, and according to the target high-energy particle beam spot value corresponding to each connected area in the grayscale image of each layer, the electromagnetic lens in the high-energy particle beam lithography equipment is adjusted to control the size of the high-energy particle beam spot, so that the spot value of the high-energy particle beam engraved in the connected area is the target high-energy particle beam spot value, and then according to the high-energy particle beam processing parameters corresponding to each pixel point in the connected area, the high-energy particle beam lithography equipment is controlled to emit the high-energy particle beam and act on the position corresponding to the connected area in the corresponding material layer, and the pattern corresponding to each connected area in the grayscale image of each layer is engraved to the corresponding material layer to obtain the target semiconductor device.

In steps S103 to S105, each connected area and the width of the connected area in each layer of the grayscale image are obtained, and according to the width interval of the connected area width, the target high-energy particle beam spot value when engraving the pattern corresponding to each connected area is obtained.

Therefore, before the high-energy particle beam lithography device carves the pattern corresponding to each connected area in each layer of grayscale image to the corresponding material layer, it is necessary to adjust the electromagnetic lens in the high-energy particle beam lithography device to control the size of the high-energy particle beam spot according to the target high-energy particle beam spot value corresponding to each connected area, so that the spot value of the high-energy particle beam engraved in the connected area is the target high-energy particle beam spot value, and then, according to the high-energy particle beam processing parameters corresponding to each pixel point in the connected area, control the high-energy particle beam lithography device to emit the high-energy particle beam and act on the position corresponding to the connected area in the corresponding material layer to perform pattern engraving. In this way, the high-energy particle beam lithography device can use a larger high-energy particle beam spot when engraving a connected area with a larger width, shorten the engraving processing time, and use a smaller high-energy particle beam spot when engraving a connected area with a smaller width, improve the processing accuracy, so that the processing efficiency of the semiconductor device can be guaranteed while improving the processing effect of the semiconductor device.

In an optional embodiment, the material layers are pre-processed material layers, and the high-energy particle beam lithography equipment sequentially places each corresponding material layer on the target substrate by controlling the mechanical equipment.

In another optional embodiment, the material layer is a material layer deposited by controlling a high-energy particle beam lithography device. Specifically, referring to FIG. 5 , the step of sequentially manufacturing each corresponding material layer on the target substrate includes steps S1061 to S1062 as follows:

S1061: Acquire the material gas corresponding to the material layer and the deposition area corresponding to the material layer on the target substrate.

The material gas may be one gas or multiple gases, which may be different according to the differences of the material layers.

In some embodiments, in order to enable the high-energy particle beam to engrave better graphics effects on the material layer, each material layer includes multiple materials. For example, a layer of silicon oxide is first plated on the surface of single crystal silicon, and then a layer of tantalum is plated on the surface of the silicon oxide. Accordingly, multiple material gases are also required when preparing such material layers.

S1062: Control the high-energy particle beam lithography equipment to spray the material gas in the deposition area, so that the material gas is decomposed and deposited in the deposition area, thereby completing the production of the material layer.

Since high-energy particle beams can decompose metal vapor or gas-phase insulating materials, etc., the material gas is sprayed in the deposition area through the gas injection device in the high-energy particle beam lithography equipment, and the high-energy particle beam is emitted to decompose the material gas at the same time, so that the decomposed material gas is deposited in the deposition area to complete the production of the material layer.

The above method can complete the laying of material layers and the engraving of graphics by controlling a high-energy particle beam lithography device, thereby realizing the processing of semiconductor devices, which can not only reduce costs but also have a higher degree of automation.

In an optional embodiment, after each layer of the material is produced on the target substrate, the high-energy particle beam lithography equipment can also control the high-energy particle beam to polish the material layer according to a preset optimized thickness range and/or a preset optimized flatness range, so that the current thickness and/or current flatness of the material layer are respectively within the preset optimized thickness range and the preset optimized flatness range, thereby further improving the subsequent engraving effect and optimizing the processing of semiconductor devices.

Optionally, the preset optimized thickness range is 1 nm to 500 nm, and the preset optimized flatness range is 0.5 nm to 5 nm.

Please refer to FIG6 , which is a schematic diagram of the structure of a semiconductor device quality improvement device provided by an embodiment of the present application. The device can be implemented as all or part of a high-energy particle beam lithography device through software, hardware, or a combination of both. The device 6 includes:

A layout acquisition unit 61 is used to acquire an integrated circuit layout corresponding to a target semiconductor device; wherein the integrated circuit layout includes a plurality of layers of integrated circuit sub-layouts, each layer of the integrated circuit sub-layout corresponds to a pattern of one or more material layers of the target semiconductor device;

A layout conversion unit 62, used to convert the integrated circuit sub-layouts of several layers into grayscale images of a preset format;

A connected region acquisition unit 63 is used to acquire each connected region composed of target pixels in the grayscale image and the width of each connected region; wherein the grayscale value of the target pixel in each connected region is within the same preset grayscale value range;

A beam spot value acquisition unit 64 is used to acquire a target high-energy particle beam spot value when the high-energy particle beam lithography device engraves a pattern corresponding to each of the connected areas according to the width interval of each of the connected areas and the correspondence between the preset width interval and the beam spot size of the high-energy particle beam;

A processing parameter acquisition unit 65 is used to acquire the high-energy particle beam processing parameter corresponding to each pixel point in the connected area in the grayscale image according to the corresponding relationship between the preset high-energy particle beam processing parameter corresponding to the target high-energy particle beam spot value and the grayscale value;

The processing control unit 66 is used to sequentially manufacture each corresponding material layer on the target substrate, and adjust the electromagnetic lens in the high-energy particle beam lithography equipment to control the size of the high-energy particle beam spot according to the target high-energy particle beam spot value corresponding to each connected area in the grayscale image of each layer, so that the spot value of the high-energy particle beam for engraving the connected area is the target high-energy particle beam spot value, and then control the high-energy particle beam lithography equipment to emit the high-energy particle beam and act on the position corresponding to the connected area in the corresponding material layer according to the high-energy particle beam processing parameters corresponding to each pixel point in the connected area, and engrave the pattern corresponding to each connected area in the grayscale image of each layer to the corresponding material layer to obtain the target semiconductor device.

It should be noted that the semiconductor device quality improvement device provided in the above embodiment only uses the division of the above functional modules as an example when executing the semiconductor device quality improvement method. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the semiconductor device quality improvement device provided in the above embodiment and the semiconductor device quality improvement method belong to the same concept, and the implementation process thereof is detailed in the method embodiment, which will not be repeated here.

Please refer to Figure 7, which is a schematic diagram of the structure of a high-energy particle beam lithography device provided by an embodiment of the present application. As shown in Figure 7, the high-energy particle beam lithography device 7 may include: a processor 70, a memory 71, and a computer program 72 stored in the memory 71 and executable on the processor 70, such as a semiconductor device processing control program; when the processor 70 executes the computer program 72, the steps in the above-mentioned method embodiments are implemented, such as steps S101 to S106 shown in Figure 1.

The processor 70 may include one or more processing cores. The processor 70 uses various interfaces and lines to connect various parts in the high-energy particle beam lithography device 7, and executes various functions and processes data of the high-energy particle beam lithography device 7 by running or executing instructions, programs, code sets or instruction sets stored in the memory 71, and calling the data in the memory 71. Optionally, the processor 70 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 70 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing the content to be displayed on the touch display screen; and the modem is used to process wireless communication. It can be understood that the above-mentioned modem may not be integrated into the processor 70, but implemented by a single chip.

The memory 71 may include a random access memory (RAM) or a read-only memory (ROM). Optionally, the memory 71 includes a non-transitory computer-readable storage medium. The memory 71 may be used to store instructions, programs, codes, code sets or instruction sets. The memory 71 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch instructions, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area may store data involved in the above-mentioned various method embodiments, etc. The memory 71 may also be optionally at least one storage device located away from the aforementioned processor 70.

In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

The present invention is not limited to the above-mentioned embodiments. If various changes or modifications to the present invention do not depart from the spirit and scope of the present invention, and if these changes and modifications fall within the scope of the claims and equivalent technologies of the present invention, the present invention is also intended to include these changes and modifications.

Claims

A method for improving the quality of a semiconductor device, characterized in that it comprises the steps of:

Acquire an integrated circuit layout corresponding to the target semiconductor device; wherein the integrated circuit layout includes several layers of integrated circuit sub-layouts, and each layer of the integrated circuit sub-layout corresponds to a pattern of one or more material layers of the target semiconductor device;

Converting the integrated circuit sub-layouts of the plurality of layers into grayscale images of a preset format respectively;

Obtaining each connected region composed of target pixel points in the grayscale image and the width of each connected region; wherein the grayscale value of the target pixel point in each connected region is within the same preset grayscale value range;

According to the width interval of the width of each of the connected areas and the correspondence between the preset width interval and the spot size of the high-energy particle beam, a target high-energy particle beam spot value is obtained when the high-energy particle beam lithography device carves a pattern corresponding to each of the connected areas;

According to the correspondence between the preset high-energy particle beam processing parameters corresponding to the target high-energy particle beam spot value and the grayscale value, the high-energy particle beam processing parameters corresponding to the pixel points in each connected area in the grayscale image are obtained;

Each corresponding material layer is sequentially manufactured on the target substrate, and the electromagnetic lens in the high-energy particle beam lithography equipment is adjusted to control the size of the high-energy particle beam spot according to the target high-energy particle beam spot value corresponding to each connected area in the grayscale image of each layer, so that the spot value of the high-energy particle beam for engraving the connected area is the target high-energy particle beam spot value, and then according to the high-energy particle beam processing parameters corresponding to each pixel point in the connected area, the high-energy particle beam lithography equipment is controlled to emit the high-energy particle beam and act on the position corresponding to the connected area in the corresponding material layer, and the pattern corresponding to each connected area in the grayscale image of each layer is engraved to the corresponding material layer to obtain the target semiconductor device.
The method for improving the quality of semiconductor devices according to claim 1, characterized in that the step of obtaining each connected area composed of target pixels in the grayscale image comprises the steps of:

According to the grayscale value of each pixel point of the grayscale image and the position of each pixel point in the grayscale image, target pixel points with adjacent positions and grayscale values in the same preset grayscale value range are divided into one of the connected areas; wherein, the adjacent positions include direct adjacent positions and indirect adjacent positions.
The method for improving the quality of a semiconductor device according to claim 1, wherein obtaining the width of each of the connected regions comprises the steps of:

Obtain the number of target pixels in each row of the connected area;

Obtaining the width of each row in the connected area according to the number of target pixels in each row and the width of each target pixel;

The width of the connected region is obtained according to the average value of the width of each row in the connected region.
The method for improving the quality of semiconductor devices according to claim 1 is characterized in that, according to the width interval in which the width of each of the connected regions is located and the correspondence between the preset width interval and the beam spot size of the high-energy particle beam, obtaining the target high-energy particle beam spot value when the high-energy particle beam lithography equipment engraves the pattern corresponding to each of the connected regions, comprises the steps of:

When the endpoint value of the width interval where the width of the connected area is located is larger, the target high-energy particle beam spot value when the high-energy particle beam lithography device carves the pattern corresponding to the connected area is larger;

When the endpoint value of the width interval where the width of the connected area is located is smaller, the target high-energy particle beam spot value when the high-energy particle beam lithography device carves the pattern corresponding to the connected area is smaller.
The method for improving the quality of a semiconductor device according to claim 1, wherein:

The high-energy particle beam processing parameters include the high-energy particle beam acceleration voltage and/or the high-energy particle beam action time.

The step of obtaining the high-energy particle beam processing parameters corresponding to each pixel point in each connected area in the grayscale image according to the corresponding relationship between the preset high-energy particle beam processing parameters corresponding to the target high-energy particle beam spot value and the grayscale value comprises the following steps:

According to the grayscale values of the pixels in each of the connected areas in the grayscale image, the high-energy particle beam acceleration voltage corresponding to each pixel in each of the connected areas in the grayscale image is obtained, and when the grayscale value of the pixels in each of the connected areas in the grayscale image is smaller, the high-energy particle beam acceleration voltage of the high-energy particle beam lithography device is higher, and when the grayscale value of the pixels in each of the connected areas in the grayscale image is larger, the high-energy particle beam acceleration voltage of the high-energy particle beam lithography device is lower;

or,

According to the grayscale values of the pixels in each of the connected areas in the grayscale image, the high-energy particle beam action time corresponding to each pixel in each of the connected areas in the grayscale image is obtained, and when the grayscale value of the pixel in each of the connected areas in the grayscale image is smaller, the high-energy particle beam action time of the high-energy particle beam lithography device is longer, and when the grayscale value of the pixel in each of the connected areas in the grayscale image is larger, the high-energy particle beam action time of the high-energy particle beam lithography device is shorter;

or,

The grayscale mean of all pixels in each of the connected areas in the grayscale image is obtained. When the grayscale mean is smaller, the high-energy particle beam acceleration voltage of the high-energy particle beam lithography device is made higher. According to the grayscale values of the pixels in each of the connected areas in the grayscale image, the high-energy particle beam action time corresponding to each pixel in each of the connected areas in the grayscale image is obtained when the high-energy particle beam acceleration voltage remains unchanged. When the grayscale value of the pixel in each of the connected areas in the grayscale image is smaller, the high-energy particle beam action time of the high-energy particle beam lithography device is made longer. When the grayscale value of the pixel in each of the connected areas in the grayscale image is larger, the high-energy particle beam action time of the high-energy particle beam lithography device is made shorter.
The method for improving the quality of semiconductor devices according to claim 1, characterized in that the step of sequentially manufacturing each corresponding material layer on the target substrate comprises the steps of:

Acquire a material gas corresponding to the material layer and a deposition area corresponding to the material layer on the target substrate;

The high-energy particle beam lithography equipment is controlled to spray the material gas in the deposition area, so that the material gas is decomposed and deposited in the deposition area, thereby completing the production of the material layer.
The method for improving the quality of semiconductor devices according to claim 1, characterized in that the step of sequentially manufacturing each corresponding material layer on the target substrate comprises the steps of:

According to a preset optimized thickness range and/or a preset optimized flatness range, the high-energy particle beam is controlled to polish the material layer so that the current thickness and/or the current flatness of the material layer are respectively within the preset optimized thickness range and the preset optimized flatness range.
The method for improving the quality of semiconductor devices according to claim 6 is characterized in that: the preset optimized thickness range is between 1 nm and 500 nm, and the preset optimized flatness range is between 0.5 nm and 5 nm.
A semiconductor device quality improvement device, comprising:

A layout acquisition unit, used to acquire an integrated circuit layout corresponding to a target semiconductor device; wherein the integrated circuit layout includes a plurality of layers of integrated circuit sub-layouts, each layer of the integrated circuit sub-layout corresponds to a pattern of one or more material layers of the target semiconductor device;

A layout conversion unit, used to convert the integrated circuit sub-layouts of several layers into grayscale images of a preset format;

A connected region acquisition unit, used to acquire each connected region composed of target pixel points in the grayscale image and the width of each connected region; wherein the grayscale value of the target pixel point in each connected region is within the same preset grayscale value range;

A beam spot value acquisition unit, used for acquiring a target high-energy particle beam spot value when the high-energy particle beam lithography device engraves a pattern corresponding to each of the connected areas according to a width interval in which the width of each of the connected areas is located and a correspondence between a preset width interval and a beam spot size of the high-energy particle beam;

A processing parameter acquisition unit, configured to acquire the high-energy particle beam processing parameter corresponding to each pixel point in the connected area in the grayscale image according to a correspondence between a preset high-energy particle beam processing parameter corresponding to the target high-energy particle beam spot value and a grayscale value;

A processing control unit is used to sequentially manufacture each corresponding material layer on a target substrate, and adjust an electromagnetic lens in a high-energy particle beam lithography device to control the size of a high-energy particle beam spot according to target high-energy particle beam spot values corresponding to each connected area in the grayscale image of each layer, so that the spot value of the high-energy particle beam for engraving the connected area is the target high-energy particle beam spot value, and then control the high-energy particle beam lithography device to emit a high-energy particle beam and act on a position corresponding to the connected area in the corresponding material layer according to high-energy particle beam processing parameters corresponding to each pixel point in the connected area, and engrave patterns corresponding to each connected area in the grayscale image of each layer to the corresponding material layer to obtain the target semiconductor device.
A high-energy particle beam lithography device, characterized in that it includes: a processor, a memory, and a computer program stored in the memory and executable on the processor, characterized in that when the processor executes the computer program, the steps of the method as described in any one of claims 1 to 8 are implemented.