WO2024092544A1

WO2024092544A1 - Nitride-based semiconductor device and method for manufacturing thereof

Info

Publication number: WO2024092544A1
Application number: PCT/CN2022/129175
Authority: WO
Inventors: Sichao LI; Hui Yan; Chunhua Zhou
Original assignee: Innoscience (Zhuhai) Technology Co., Ltd.
Priority date: 2022-11-02
Filing date: 2022-11-02
Publication date: 2024-05-10
Also published as: CN118696415A

Abstract

A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a depletion mode device, and an enhancement mode device. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The depletion mode device includes a first III-V semiconductor layer disposed over the second nitride-based semiconductor layer. The enhancement mode device includes a second III-V semiconductor layer disposed over the second nitride-based semiconductor layer. The first III-V semiconductor layer and the second III-V semiconductor layer have the same thickness, and the second III-V semiconductor layer is doped to have a conductivity type different than that of the first III-V semiconductor layer.

Description

NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Inventors: Sichao LI; Hui YAN; Chunhua ZHOU

Field of the Disclosure:

The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having D mode and E mode devices which integrated to the same wafer.

Background of the Disclosure:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Summary of the Disclosure:

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a depletion mode device, and an enhancement mode device. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The depletion mode device includes a first source electrode and a first drain electrode disposed over the second nitride-based semiconductor layer. The depletion mode device includes a first gate electrode and a first III-V semiconductor layer. The first gate electrode is disposed over the second nitride-based semiconductor layer. The first III-V semiconductor layer is disposed between the second nitride-based semiconductor layer and the first gate electrode. The enhancement mode device includes a second source electrode and a second drain electrode disposed over the second nitride-based semiconductor layer. The enhancement mode device includes a second gate electrode and a second III-V semiconductor layer. The second gate electrode is disposed over the second nitride-based semiconductor layer. The second III-V semiconductor layer is disposed between the second nitride-based semiconductor layer and the second gate electrode. The second III-V semiconductor layer is doped to have a conductivity type different than that of the first III-V semiconductor layer.

In accordance with one aspect of the present disclosure, a method for manufacturing a nitride-based semiconductor device is provided. The method has steps as follows; forming a first nitride-based semiconductor layer on a substrate; forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer; forming a III-V semiconductor layer over the second nitride-based semiconductor layer; performing a first doping process to a first portion of the III-V semiconductor layer such that the first portion of the III-V semiconductor layer has a conductivity type different than that of a second portion of the III-V semiconductor layer; forming an enhancement mode device by using the first portion of the III-V semiconductor layer; and forming a depletion mode device by using the second portion of the III-V semiconductor layer.

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a depletion mode device, and an enhancement mode device. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The depletion mode device includes a first III-V semiconductor layer disposed over the second nitride-based semiconductor layer. The enhancement mode device includes a second III-V semiconductor layer disposed over the second nitride-based semiconductor layer. The first III-V semiconductor layer and the second III-V semiconductor layer have the same thickness, and the second III-V semiconductor layer is doped to have a conductivity type different than that of the first III-V semiconductor layer.

By the above configuration, a gate dielectric layer for a D-mode device can be formed by using a semiconductor compound so as to achieve integration of D-mode and E-mode devices into the same wafer during their processes.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1 is a vertical cross-sectional view of a depletion mode device 1A according to some embodiments of the present disclosure;

FIG. 2 is a vertical cross-sectional view of a nitride-based semiconductor device 2A according to some embodiments of the present disclosure;

FIG. 3 shows a flowchart of a method for manufacturing a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device 2B according to some embodiments of the present disclosure;

FIG. 5 is a vertical cross-sectional view of a depletion mode device 1B according to some embodiments of the present disclosure; and

FIG. 6 is a vertical cross-sectional view of a nitride-based semiconductor device 2C according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

In the present disclosure, a doping portion can have a conductive type expressed as a combination of a doping type and a plus/minus sign. For example, with respect to n-type dopant, there are three conductive types, including “n ⁺” , “n ^-” , and “n” . An n ⁺ doping portion has a doping concentration higher/heavier than an n-doping portion; and an n-doping portion has a doping concentration than higher an n ^--doping portion. Doping portions of the same symbol may have different absolute doping concentrations. For example, two different n ⁺ doping portions may have the same or different absolute doping concentrations. The definition can be applied to the p-type doping. In some embodiments, the n-type dopant can include, but are not limited to, silicon (Si) , carbon (C) , germanium (Ge) , Selenium (Se) , tellurium (Te) , or the like. In some embodiments, the p-type dopant can include, but are not limited to, magnesium (Mg) , beryllium (Be) , zinc (Zn) , or the like. In the exemplary illustrations of the present disclosure, although the element is illustrated as a single layer, it can include multiple layers therein.

For depletion mode devices, a gate dielectric layer is applied to the structure. Such the gate dielectric layer is not necessary for enhancement mode device, so these two mode devices are hard to get integrated into the same wafer during their processes. In the present disclosure, a gate dielectric layer is formed by using a semiconductor compound so as to achieve integration of these two mode devices into the same wafer during their processes.

FIG. 1 is a vertical cross-sectional view of a depletion mode device 1A according to some embodiments of the present disclosure. The depletion mode device 1A may be a depletion mode (D-mode) high-electron-mobility transistor (HEMT) . The depletion mode device 1A includes a substrate 10, nitride-based semiconductor layers 12, 14,

electrodes

20 and 22, a III-V semiconductor layer 30, and a gate electrode 32.

The substrate 10 may be a semiconductor substrate. The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

In some embodiments, the depletion mode device 1A may further include a buffer layer (not illustrated) . The buffer layer is disposed between the substrate 10 and the nitride-based semiconductor layer 12. The buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 12, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown) . The nucleation layer may be formed between the substrate 10 and a buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The nitride-based semiconductor layer 12 can be disposed on/over/above the buffer layer. The nitride-based semiconductor layer 14 can be disposed on/over/above the nitride-based semiconductor layer 12. The exemplary materials of the nitride-based semiconductor layer 12 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _xGa _(1–x) N where x ≤ 1. The exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layers 12 and 14 are selected such that the nitride-based semiconductor layer 14 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 12, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 12 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 14 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers 12 and 14 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to or along the heterojunction. Accordingly, the semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

The

electrodes

20 and 22 are disposed over the nitride-based semiconductor layer 14. Each of the

electrodes

20 and 22 can serve as a source electrode or a drain electrode. For example, the electrode 20 is a source electrode and the electrode 22 is the drain electrode. In some embodiments, the

electrodes

20 and 22 can be called ohmic electrodes.

In some embodiments, the

electrodes

20 and 22 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the

electrodes

20 and 22 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. The

electrodes

20 and 22 may be a single layer, or plural layers of the same or different composition. In some embodiments, the

electrodes

20 and 22 can form ohmic contact with the nitride-based semiconductor layer 14. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the

electrodes

20 and 22.

In some embodiments, each of the

electrodes

20 and 22 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

The III-V semiconductor layer 30 and the gate electrode 32 are disposed over the nitride-based semiconductor layer 14. The III-V semiconductor layer 30 and the gate electrode 32 are located between

electrodes

20 and 22. The III-V semiconductor layer 30 is in contact with the nitride-based semiconductor layer 14. The gate electrode 32 is disposed over the III-V semiconductor layer 30. The gate electrode 32 is in contact with the III-V semiconductor layer 30. The III-V semiconductor layer 30 is located between the nitride-based semiconductor layer 14 and the gate electrode 32. The III-V semiconductor layer 30 and the gate electrode 32 have the same width.

The III-V semiconductor layer 30 can serve as a gate dielectric layer for the D-mode device 1A. In some embodiments, the III-V semiconductor layer 30 is made of GaN. The reason for such the configuration is that the D-mode device 1A can be integrated into the same wafer with at least one enhancement mode (E-mode) device. A doped GaN layer can be applied to the E-mode device. The III-V semiconductor layer 30 can be modulated so it can serve as a gate dielectric layer and the compound thereof is further applicable for the E-mode device.

In some embodiments, the III-V semiconductor layer 30 is a GaN layer. In some embodiments, the III-V semiconductor layer 30 is a Al _xGa _(1–x) N layer, where x ≤ 1 layer. In some embodiments, the III-V semiconductor layer 30 is intrinsic. In some embodiments, the III-V semiconductor layer 30 is n-type doped. In some embodiments, the III-V semiconductor layer 30 has a varied n-type donor concentration along a vertical direction (i.e., the vertical direction of FIG. 1) . In some embodiments, the III-V semiconductor layer 30 has a n-type donor concentration in a range from about 10 ¹⁵ cm ^-3 to about 10 ¹⁷ cm ^-3. In some embodiments, the III-V semiconductor layer 30 has a thickness in a range from about 10 nm to about 50 nm. The character and the value range of the III-V semiconductor layer 30 as above is made for the purpose that the III-V semiconductor layer 30 can serve as a gate dielectric layer and that the compound thereof is applicable for the E-mode.

The gate electrode 32 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds. The

electrodes

20, 22, and the gate electrode 32 can constitute a depletion mode HEMT with the III-V semiconductor layer 30.

FIG. 2 is a vertical cross-sectional view of a nitride-based semiconductor device 2A according to some embodiments of the present disclosure. The nitride-based semiconductor device 3A includes a substrate 40, nitride-based semiconductor layers 42, 44, a D-mode device 50, and a E-mode device 60.

The configuration or characters of the substrate 40 and the nitride-based semiconductor layers 42, 44 can be identical with or similar to the substrate 10 and the nitride-based semiconductor layers 12, 14 as afore described. Accordingly, 2DEG along an interface between the nitride-based semiconductor layers 42 and 44 is formed.

The D-mode device 50 and the E-mode device 60 are disposed over the nitride-based semiconductor layers 42 and 44. The D-mode device 50 and the E-mode device 60 can share the 2DEG. That is, the D-mode device 50 and the E-mode device 60 can be integrated into the same wafer so they can be formed over the same epitaxy base and thus share the same 2DEG of the epitaxy base.

The D-mode device 50 includes

electrodes

52 and 54, a III-V semiconductor layer 56, and a gate electrode 58 disposed over the nitride-based semiconductor layers 42, 44. The configuration of the D-mode device 50 can be identical with or similar to the D-mode device as afore described in FIG. 1.

The E-mode device 60 is an enhancement mode (E-mode) HEMT. The E-mode device 60 includes

electrodes

62 and 64, a III-V semiconductor layer 66, and a gate electrode 68 disposed over the nitride-based semiconductor layers 42, 44. The configuration of the E-mode device 60 regarding the

electrodes

62 and 64 and the gate electrode 68 can be identical with or similar to those of the D-mode device 50. The

electrodes

52 and 54 of the D-mode device 50 and the

electrodes

62 and 64 of the E-mode device 60 can be formed in the same processes. The gate electrode 56 of the D-mode device 50 and the gate electrode 66 of the E-mode device 60 can be formed in the same processes.

The III-V semiconductor layer 66 is in contact with the nitride-based semiconductor layer 44 The III-V semiconductor layer 66 and the gate electrode 68 have the same width. The III-V semiconductor layer 66 of the E-mode device 60 has at least one character different than the III-V semiconductor layer 56 of the D-mode device 50.

The III-V semiconductor layer 66 is p-type doped, so as to achieve the E-mode. The III-V semiconductor layer 56 of the D-mode device 50 and the III-V semiconductor layer 66 of the E-mode device 60 can be formed from the same III-V semiconductor layer but doped at different processes. In some embodiments, after formation of an intrinsic III-V semiconductor layer, p-type donors are doped into the III-V semiconductor layer 66 of the E-mode device 60 while the III-V semiconductor layer 56 of the D-mode device 50 is protected by a mask layer so as to get free from the doping. In some embodiments, after the p-type donors are doped into the III-V semiconductor layer 66 of the E-mode device 60, the III-V semiconductor layer 66 of the E-mode device 60 is protected by a mask layer and n-type donors are doped into the III-V semiconductor layer 56 of the D-mode device 50.

In some embodiments, different degrees or conditions of the doping can be achieved by adjusting atmosphere composition, gas flow, and temperature during the process. The different degrees or conditions can be made to modulate the device threshold voltage.

After the process, the III-V semiconductor layer may have different portions serving as based for D-mode and E-mode devices. Accordingly, the III-V semiconductor layer 66 of the E-mode device 60 can has a conductivity type different than that of the III-V semiconductor layer 56 of the D-mode device 50. Accordingly, the D-mode device 50 and the E-mode device 60 can be integrated into the same wafer.

In some embodiments, the III-V semiconductor layer 56 of the D-mode device 50 and the III-V semiconductor layer 66 of the E-mode device 60 have the same III-V compound, such as AlGaN, GaN, or combinations thereof. In some embodiments, the III-V semiconductor layer 56 of the D-mode device 50 and the III-V semiconductor layer 66 of the E-mode device 60 have the same thickness, such as a thickness in a range from 10 nm to 50 nm.

FIG. 3 shows a flowchart of a method for manufacturing a nitride-based semiconductor device according to some embodiments of the present disclosure. The method includes steps S10, S20, S30, S40, and S50. In the step S10, a channel layer can be formed a substrate. In the step S20, a barrier layer can be formed on the channel layer. In the step S30, a III-V semiconductor layer can be formed over the barrier layer. In the step S40, at least one doping process is performed. In some embodiments, the doping process includes a p-type donor doping for a E-mode device as described. In some embodiments, the doping process further includes n-type donor doping for a D-mode device as described. In the step S50, at least one enhancement mode device and at least one depletion mode device are formed. The step S50 includes formation of source electrodes, drain electrodes, and gate electrodes. In some embodiments, the enhancement mode device and the depletion mode device can be formed simultaneously.

FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device 2B according to some embodiments of the present disclosure. The nitride-based semiconductor device 2B is similar to the nitride-based semiconductor device 2A as described and illustrated with reference to FIG. 2, except that the nitride-based semiconductor device 2B further includes an isolation structure 70. The isolation structure 70 is are formed to isolate the D-mode device 50B and the E-mode device 60B. In some embodiments, an implant isolation process may be used. Nitrogen, oxygen, fluorine or the like is implanted in the structure so as to form the isolation structure 70 blocking 2DEG.

FIG. 5 is a vertical cross-sectional view of a depletion mode device 1B according to some embodiments of the present disclosure. The depletion mode device 1B is similar to depletion mode device 1A as described and illustrated with reference to FIG. 1, except that the III-V semiconductor layer 30B is wider than the gate electrode 32B. The III-V semiconductor layer 30B can have an isolation property. The III-V semiconductor layer 30B can be further formed to abut against the

electrodes

20 and 22. As such, at least one etching stage to the III-V semiconductor layer 30B can be omitted, so as to improve the device yield rate and the device reliability.

FIG. 6 is a vertical cross-sectional view of a nitride-based semiconductor device 2C according to some embodiments of the present disclosure. The nitride-based semiconductor device 2C is similar to the nitride-based semiconductor device 2A as described and illustrated with reference to FIG. 2, except that the nitride-based semiconductor device 2B further applies the structure illustrated in FIG. 5.

A III-V semiconductor layer 80 located between the

electrodes

52C and 54C of the D-mode device 50C can be intrinsic or n-type doped. Nitride-based semiconductor layers 82 and 84 located between the electrode 54C of the D-mode device 50C and the electrode 62C of the E-mode device 60C can be intrinsic. A III-V semiconductor layer 86 located between the

electrodes

62C and 64C of the E-mode device 60C can be p-type doped. In some embodiment, a center portion of the III-V semiconductor layer 80 (e.g., which is directly beneath a gate electrode) is n-type doped and rest of the III-V semiconductor layer 80 is intrinsic. In some embodiment, a center portion of the III-V semiconductor layer 86 (e.g., which is directly beneath a gate electrode) is p-type doped and rest of the III-V semiconductor layer 86 is intrinsic. Those different doped types can be achieved via more than one doping process with using mask layers. In some embodiments, the III-V semiconductor layers 80, 82, 84, 86 have the same III-V compound, such as AlGaN, GaN, or combinations thereof. In some embodiments, the III-V semiconductor layers 80, 82, 84, 86 have the same thickness, such as a thickness in a range from 10 nm to 50 nm.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A nitride-based semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;

a depletion mode device comprising:

a first source electrode and a first drain electrode disposed over the second nitride-based semiconductor layer;

a first gate electrode disposed over the second nitride-based semiconductor layer; and

a first III-V semiconductor layer disposed between the second nitride-based semiconductor layer and the first gate electrode; and

an enhancement mode device comprising:

a second source electrode and a second drain electrode disposed over the second nitride-based semiconductor layer;

a second gate electrode disposed over the second nitride-based semiconductor layer; and

a second III-V semiconductor layer disposed between the second nitride-based semiconductor layer and the second gate electrode, wherein the second III-V semiconductor layer is doped to have a conductivity type different than that of the first III-V semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first nitride-based semiconductor layer and the second nitride-based semiconductor layer are configured to form two-dimensional electron gas (2DEG) along an interface between the first nitride-based semiconductor layer and the second nitride-based semiconductor layer, and the depletion mode device and the enhancement mode device share the 2DEG.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first III-V semiconductor layer is in contact with the second nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the second III-V semiconductor layer is in contact with the second nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first III-V semiconductor layer and the second III-V semiconductor layer have the same thickness.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first III-V semiconductor layer and the second III-V semiconductor layer have the same III-V compound.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first III-V semiconductor layer is intrinsic, and the second III-V semiconductor layer is p-type doped.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first III-V semiconductor layer is n-type doped, and the second III-V semiconductor layer is p-type doped.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first III-V semiconductor layer has a varied n-type donor concentration along a vertical direction.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first III-V semiconductor layer and the first gate electrode have the same width.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first III-V semiconductor layer is wider than the gate electrode.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first III-V semiconductor layer abuts against the first source electrode and the first drain electrode.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first III-V semiconductor layer has a thickness in a range from 10 nm to 50 nm.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first III-V semiconductor layer has a donor concentration in a range from 1015 cm-3 to 1017 cm-3.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first III-V semiconductor layer and the second III-V semiconductor layer are made of GaN.
A method for manufacturing a nitride-based semiconductor device, comprising:

forming a first nitride-based semiconductor layer on a substrate;

forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer;

forming a III-V semiconductor layer over the second nitride-based semiconductor layer;

performing a first doping process to a first portion of the III-V semiconductor layer such that the first portion of the III-V semiconductor layer has a conductivity type different than that of a second portion of the III-V semiconductor layer;

forming an enhancement mode device by using the first portion of the III-V semiconductor layer; and

forming a depletion mode device by using the second portion of the III-V semiconductor layer.
The method of any one of the preceding claims, wherein the III-V semiconductor layer in contact with the second nitride-based semiconductor layer.
The method of any one of the preceding claims, wherein the first portion of the III-V semiconductor layer is p-type doped, and the second portion of the III-V semiconductor layer is intrinsic.
The method of any one of the preceding claims, wherein the first portion of the III-V semiconductor layer is p-type doped, and the second portion of the III-V semiconductor layer is n-type doped.
The method of any one of the preceding claims, wherein the second portion of the III-V semiconductor layer has a varied n-type donor concentration along a vertical direction.
A nitride-based semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;

a depletion mode device comprising a first III-V semiconductor layer disposed over the second nitride-based semiconductor layer; and

an enhancement mode device comprising a second III-V semiconductor layer disposed over the second nitride-based semiconductor layer, wherein the first III-V semiconductor layer and the second III-V semiconductor layer have the same thickness, and the second III-V semiconductor layer is doped to have a conductivity type different than that of the first III-V semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first nitride-based semiconductor layer and the second nitride-based semiconductor layer are configured to form two-dimensional electron gas (2DEG) along an interface between the first nitride-based semiconductor layer and the second nitride-based semiconductor layer, and the depletion mode device and the enhancement mode device share the 2DEG.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first III-V semiconductor layer is in contact with the second nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the second III-V semiconductor layer is in contact with the second nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first III-V semiconductor layer and the second III-V semiconductor layer have the same III-V compound.