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WO2024085098A1 - Gsr element manufacturing method - Google Patents

Gsr element manufacturing method Download PDF

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Publication number
WO2024085098A1
WO2024085098A1 PCT/JP2023/037313 JP2023037313W WO2024085098A1 WO 2024085098 A1 WO2024085098 A1 WO 2024085098A1 JP 2023037313 W JP2023037313 W JP 2023037313W WO 2024085098 A1 WO2024085098 A1 WO 2024085098A1
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WO
WIPO (PCT)
Prior art keywords
groove
forming
resin film
magnetic wire
asic
Prior art date
Application number
PCT/JP2023/037313
Other languages
French (fr)
Japanese (ja)
Inventor
工藤一恵
田辺淳一
本蔵義信
本蔵晋平
菊池永喜
Original Assignee
マグネデザイン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2022166553A external-priority patent/JP7207676B1/en
Priority claimed from JP2022166551A external-priority patent/JP7203400B1/en
Priority claimed from JP2022197538A external-priority patent/JP7329782B1/en
Application filed by マグネデザイン株式会社 filed Critical マグネデザイン株式会社
Publication of WO2024085098A1 publication Critical patent/WO2024085098A1/en

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00Arrangements or instruments for measuring magnetic variables
    • G01R33/02Measuring direction or magnitude of magnetic fields or magnetic flux
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00Galvanomagnetic devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00Galvanomagnetic devices
    • H10N50/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00Galvanomagnetic devices
    • H10N50/80Constructional details

Definitions

  • the present invention relates to a method for manufacturing a GSR element through an integration process of a magnetic field detection element and an application specific integrated circuit (hereinafter referred to as ASIC).
  • ASIC application specific integrated circuit
  • High-sensitivity magnetic sensors include Hall sensors, GMR sensors, TMR sensors, high-frequency carrier sensors, FG sensors, MI sensors, GSR sensors, etc.
  • Hall sensors, GMR sensors, TMR sensors, and carrier sensors have been made smaller and thinner by integrating the element with an ASIC, but improving detection sensitivity remains an issue.
  • FG sensors, MI sensors, and GSR sensors have high sensitivity, but the element and ASIC are arranged separately and joined by wire bonding, making it difficult to reduce the thickness and size of the sensors.
  • Patent Document 1 discloses a thin, highly sensitive magnetic sensor in which an insulating resist is applied to the ASIC surface, a groove is formed therein in which a magnetic wire is disposed, and a GSR element consisting of a magnetic wire, a detection coil surrounding the magnetic wire, and electrodes is integrally formed on the ASIC surface.
  • a GSR element consisting of a magnetic wire, a detection coil surrounding the magnetic wire, and electrodes is integrally formed on the ASIC surface.
  • alignment marks are formed on a SiO2 film made on a flat portion, so there are no problems with visibility.
  • Methods for forming alignment marks are also disclosed in Patent Documents 2, 3, and 4, but none of them form alignment marks on photosensitive resin.
  • Another issue is to investigate technology for forming highly visible alignment marks on photosensitive resin.
  • the first problem is how to form the inverted trapezoidal groove.
  • an insulating film such as SiO2
  • a groove is created by RIE
  • the shape of the groove will be rectangular, so we investigated using resist to form the groove only through the photolithography process.
  • epoxy-based negative type resists hereinafter referred to as negative resists
  • the characteristic of negative resists is that the edges after patterning are steep, and even after the curing heat treatment to leave the structure, the groove remains rectangular, with no change in shape. Therefore, we found that it is difficult to form a lower coil along the groove using negative resist.
  • the second problem is the method of forming the alignment marks.
  • it is necessary to reduce the coil pitch to 5 ⁇ m or less and increase the number of turns of the coil, but the finer the coil pitch, the more accurately it is required to align the position of the ASIC board and the positions of the multiple masks. Therefore, the inventors came up with the idea of forming alignment marks and grooves at the same time.
  • alignment marks are formed on SiO2, a substrate protective film, but to form them simultaneously with grooves, they must be formed on a resin coating.
  • the surface of an ASIC substrate may have unevenness of 2 to 3 ⁇ m caused by the integrated circuit. In this case, even if a resin coating of the thickness required for groove formation (approximately 5 to 15 ⁇ m) is applied, the unevenness is transferred to the surface, making it difficult to obtain the flat surface required for alignment mark formation, as on SiO2.
  • the finer the coil pitch the more accurate alignment of the upper and lower coils is required, necessitating an auto-alignment mechanism with advanced alignment functions.
  • the auto-alignment mechanism depends on the contrast of the alignment mark image. As mentioned above, if there are irregularities on the surface of the ASIC board, the signal will be disturbed and the contrast of the mark image will be distorted, as shown in Figure 43. Therefore, if the mark is misrecognized and an attempt is made to form a fine coil with a coil pitch of 5 ⁇ m or less, the connection positions of the two will be misaligned when forming the upper coil after forming the lower coil, resulting in a problem of poor coil connection.
  • the third problem is that the grooves become asymmetrical when a process for forming an inverted trapezoid groove is examined using a positive resist resin film instead of a negative resist.
  • the ASIC substrate already has integrated circuit wiring and the layout of the electrode extraction openings and the like is already determined, so there is a limit to the location where linear grooves 431 for arranging the magnetic wires can be formed, as shown in Fig. 4(a).
  • the electrode extraction portions 421 of the ASIC substrate near the location where the linear grooves for arranging the wires are formed become asymmetrical with respect to the groove.
  • the shape of the upper part of the groove becomes asymmetrical as shown in FIG. 4B.
  • the asymmetrical shape of the upper part of the groove means that the height of the resist forming the groove is different on the left and right sides of the groove.
  • the difference 43H in resist height between the resist 433 on the side close to the electrode extraction opening 432 of the ASIC substrate and the resist 434 on the other side is large, resulting in an asymmetrical groove shape.
  • a common method for flattening the protruding parts of the resist is to use CMP (Chemical-Mechanical Polishing), but because the grooves for placing the magnetic wires are 20 ⁇ m wide or less and 5 to 15 ⁇ m deep, there is a concern that foreign matter may remain in the grooves, making this method difficult to apply.
  • CMP Chemical-Mechanical Polishing
  • the present invention solves these problems by integrating a magnetic field detection element with an application specific integrated circuit (hereinafter referred to as ASIC), 1) First, an inverted trapezoid groove for arranging wires and an alignment mark are simultaneously formed on a resin film on an ASIC substrate. 2) Next, alignment marks with excellent contrast are formed simultaneously with the grooves in order to accommodate the irregularities on the surface of the ASIC substrate and to accommodate further miniaturization. 3) And, the symmetry of the groove shape is improved in correspondence with the electrode extraction opening of the ASIC substrate.
  • the present invention provides a manufacturing method for integrally forming a GSR element having a detection coil formed with a fine coil pitch on an ASIC substrate.
  • a positive resist resin film is applied to the entire surface of the ASIC substrate, and then exposed to light through a mask material and developed, thereby simultaneously forming grooves and recesses for alignment marks. At this time, the groove has a rectangular parallelepiped shape.
  • a curing heat treatment is performed. When the curing heat treatment is performed, the groove changes from a rectangular parallelepiped shape to an inverted trapezoid shape due to the stress generated during the heat treatment. This is the effect of using a positive resist resin coating instead of a SiO2 coating or a negative resist resin coating.
  • the alignment mark recess also becomes inverted trapezoidal, reducing the visibility of the mark.
  • this problem can be solved by protecting the area other than the alignment mark with resist, and using the inverted trapezoid alignment mark itself as a mask to perform RIE processing and dig into the SiO2 on the ASIC surface, thereby making the edges of the digged alignment mark steeper.
  • a negative resist type resin film is applied, exposed to light, and developed to leave the resin film only in the grooves, and a curing heat treatment is performed to form an R shape in the bottom of the groove.
  • a metal film is formed on the entire surface of the ASIC substrate on which the inverted trapezoid groove and the alignment mark recess are formed.
  • the alignment mark recess is covered with the metal film, and this film functions as a reflective film, which further improves the visibility of the alignment mark.
  • This metal film is formed along the inverted trapezoid groove, and by applying a resist thereto and exposing and developing using the alignment mark, the pattern of the lower coil can be formed along the inverted trapezoid groove.
  • the resist is removed and the metal film other than the coil and electrode parts is wetted to form a lower coil with a thickness of 0.2 to 1.0 ⁇ m in the groove.
  • An R part is formed at the bottom of the groove, and the lower coil can be formed without breaking even with fine wiring with a line width of 0.5 to 2 ⁇ m.
  • FIGS. 6A shows the unevenness of the surface of the ASIC substrate 60.
  • FIG. 6B shows that the surface state after applying resist 61 to the areas where the grooves and alignment marks are to be formed and curing is performed has the unevenness of the ASIC substrate surface transferred as is. In this state, as shown in FIG. 3, the alignment mark is obstructed by the uneven mark, making it difficult to align the lower coil and the upper coil.
  • the two-layer resin coating method in Figure 7 involves polishing to remove the irregularities transferred to the first layer of resin 71g, flattening it, and then applying a second layer of resin 72g onto the flat surface and curing it to form grooves 74Gg and alignment marks 74Ag.
  • the first step is to form a first layer by applying a first resin film (negative resist) onto the ASIC substrate with irregularities, then place a flattened first base made of hard resin underneath where the inverted trapezoid groove and alignment mark will be placed, and remove the irregularities that occur in the first resin film.
  • the irregularities on the other parts of the ASIC surface, where the first base is not placed, are left as they will be used as electrode wiring.
  • the second step is to apply a second resin film (positive resist) thicker than the depth of the groove onto the first pedestal to form a second layer, which becomes the second pedestal, and then simultaneously form an inverted trapezoid groove and a recess for an alignment mark in this second pedestal (the second resin film of the second layer), and then deposit a metal film on top of that.
  • a second resin film positive resist
  • the first resin coating layer in the first step is preferably a polyimide-based negative resist because it is preferable to ensure that the top of the base is flat and that the edges of the base have a steep shape.
  • a positive resist can also be used.
  • the second resin coating film, which is the second layer in the second step is applied onto the planarized first pedestal, and it is necessary to use a positive resist in order to form an inverted trapezoidal groove after a curing heat treatment.
  • the alignment mark portion is formed at the same time as the groove portion, so it has an inverted trapezoid shape like the groove portion. Therefore, by using the inverted trapezoid second pedestal itself as a mask and digging into the first pedestal by RIE, the steepness of the alignment mark recess is increased. Furthermore, by using a metal film as a reflective film, it is possible to improve the visibility of the alignment mark. In this way, by adopting a two-layer resin coating, it is possible to remove unevenness that cannot be achieved with a one-layer structure.
  • a first resin film is applied onto the uneven surface of the ASIC substrate to form first pedestals in the groove formation portion and the alignment mark formation portion, but unevenness occurs. Since unevenness remains on the surface of the first pedestal even after the curing heat treatment, it is necessary to flatten the upper surface of the hardened first pedestal by a polishing method such as CMP (Chemical-Mechanical Polishing). This CMP may damage the electrodes of the ASIC, so it is preferable to apply a resist to the entire surface of the ASIC before CMP to protect the ASIC surface other than the pedestal, and then remove the resist with a resist remover after CMP to achieve flattening.
  • CMP Chemical-Mechanical Polishing
  • the groove and alignment mark recess are exposed to light using a mask, developed, and then cured with heat, the groove changes from a rectangular shape to an inverted trapezoid, and the alignment mark recess also changes from a rectangular shape to an inverted trapezoid.
  • This is the effect of using a positive resist resin coating instead of a SiO2 coating. Because the first base has already been flattened, the groove surface and alignment mark portion itself are smooth.
  • the shape of the alignment mark recess also becomes an inverted trapezoid, so in order to make the edges of the alignment mark steeper, the area other than the alignment mark is protected with resist, and the alignment mark area is etched by RIE using the inverted trapezoid second pedestal itself as a mask to engrave the first pedestal.
  • the second pedestal is also a resin coating, the etching selectivity of the RIE is roughly the same. Therefore, the amount of engraving is preferably 0.5 to 1.5 ⁇ m. Below 0.5 ⁇ m, the effect of steepening is small and no improvement in visibility is observed. Above 1.5 ⁇ m, the film loss of the second pedestal is large, affecting visibility.
  • the unevenness on the ASIC board is visible through the first resin and the second resin, making it impossible to ensure the high visibility contrast required for alignment. Therefore, by forming a metal film on the alignment mark to enhance the reflection function, the visibility of the alignment mark can be improved. If the first pedestal is not flattened, the unevenness of the ASIC substrate cannot be eliminated even if a metal film is formed, and sufficient visibility of the alignment mark cannot be ensured. In other words, flattening the pedestal and forming a metal film to enhance the reflection function are essential.
  • a metal film needs to be formed to form the lower coil in the inverted trapezoidal groove, it is desirable to use the same metal film for the alignment mark portion, which enhances the reflective function, and for the lower coil.
  • a negative resist resin film is applied to the groove portion, exposed to light, and developed to leave the resin film only in the groove portion, and an R-shape is formed at the bottom of the groove by a curing heat treatment, thereby preventing breakage of the metal film.
  • the two-layer resin coating method makes it possible to simultaneously form grooves and alignment marks, and to form highly visible alignment marks on the resin coating.
  • the thickness of the first resin film forming the first pedestal of the first layer is preferably three times or more the irregularities (usually about 2 ⁇ m to 3 ⁇ m) of the ASIC surface in order to perform CMP.
  • the film thickness of the second resin in the second layer must be thicker than the minimum groove depth in order to enable groove formation (groove depth of about 5 ⁇ m to 10 ⁇ m).
  • the rectangular parallelepiped groove shape obtained after exposure and development through a mask material becomes asymmetrical at the top of the inverted trapezoid groove formed after curing heat treatment, making it difficult to form a coil, it was thought that this was because, when forming the groove in the positive resist resin film, the electrode extraction portions of the ASIC board are opened at the same time, resulting in a difference in volume of the positive resist resin film on the left and right sides of the groove, and the way they shrink during the curing heat treatment differs.
  • a protective film 62 is formed on the surface of an ASIC substrate 81 .
  • a positive resist resin film 83 is applied to the entire surface of the ASIC substrate 81, and then exposed and developed through a mask material, thereby forming a groove 831, a recess for an alignment mark (not shown), and an opening 832 for extracting electrodes from the ASIC substrate in the resin film 83. If a curing heat treatment is performed in this state, the shape of the groove will be an inverted trapezoid as shown in Figure 8(b), but the upper part of the groove will be asymmetric. Therefore, only the groove portion is subjected to additional exposure once more.
  • the groove 831 becomes an inverted trapezoid as shown in Fig. 8(b), and since additional exposure has been performed, the shape of the upper portion of the groove becomes symmetrical on both sides regardless of the position of the opening in the ASIC substrate.
  • the resist height of the groove resist 833 on the side close to the electrode extraction opening 832 of the ASIC substrate and the resist height of the other groove resist 834 are almost the same, with the difference in resist height on the left and right sides of the groove being 0.2 ⁇ m or less.
  • Figure 9 shows the relationship between the asymmetry of the upper part of the groove (difference in resist height between the left and right sides of the groove: hereafter referred to as left-right difference) when the first exposure dose is 1500 mJ/ cm2 , the groove depth is 8 ⁇ m, and the distance between the groove and the opening for electrode extraction on the ASIC substrate is 50 ⁇ m. Without additional exposure, the difference between the left and right sides was 0.6 ⁇ m. However, with additional exposure, the difference between the left and right sides was minimized at 40 mJ/cm 2 , and with an exposure amount higher than this, the top of the groove on the opposite side became higher.
  • the left-right difference is preferably 0.2 ⁇ m or less, and in this case, the additional exposure amount is in the range of 20 to 60 mJ/ cm2 and the left-right difference is 0.2 ⁇ m or less. In other words, the additional exposure amount is preferably 1 to 4% of the first exposure amount. If it is lower than 1%, the left-right difference at the top of the groove is 0.2 ⁇ m or more, and if it exceeds 4%, the initial left-right difference is reversed, resulting in a left-right difference of 0.2 ⁇ m or more, and the shape of the groove will change.
  • the groove produced by solving the above problems is used to form the coil.
  • a metal film is formed in a groove with an R-shaped bottom, and the entire surface of the substrate is coated with resist, exposed, and developed into a pattern. After plating, the resist is removed and the base film other than the coil pattern is removed to form the lower coil.
  • the magnetic wire is placed in the groove that forms the lower coil with a tension of 30 to 100 kg/mm2, and both ends of the wire are temporarily fixed with adhesive, tape, etc.
  • the magnetic wire is then fixed inside the groove by applying resin, exposing it to light, developing it, and curing it with heat. At this point, both ends of the magnetic wire remain fixed, and by performing the curing heat treatment while maintaining the tension, it is possible to improve the GSR characteristics.
  • the magnetic wire fixed inside the groove is covered with insulating glass, part of the insulating glass covering the magnetic wire is removed to provide wire terminals (both ends of the magnetic wire).
  • hydrofluoric acid treatment is known, but it causes significant damage around the wire terminals and has a significant impact on element formation.
  • glass can be removed by RIE using CF4 gas, and henceforth, glass removal will be performed by RIE.
  • a positive resist resin film is applied to the entire surface of the ASIC board, exposed to light, and developed so that the positive resist resin film remains only in the groove and the magnetic wire, and a curing heat treatment is performed to smooth out the step between the groove and the magnetic wire.
  • negative-type resists are known as resists that are left as structures, but because negative-type resists have sharp edges, the metal film for the upper coil does not adhere well in the next process, raising the risk of breakage. Therefore, we investigated a positive resist resin coating, which is not generally used as a resist that is left as a structure because its shape changes after the curing heat treatment. As a result, the positive resist resin coating can improve the edge shape gently after the curing heat treatment, and can eliminate steps without the risk of disconnection.
  • the upper coil is formed on the magnetic wire and the electrode pattern (including wire terminals and wiring) is formed on the substrate through resist coating, exposure, and development processes. After plating and wet plating, the resist is removed to form the upper coil.
  • the connection part with the lower coil has a gentle shape, and the upper coil can be formed without disconnection, resulting in a detection coil that goes around the magnetic wire.
  • the alignment precision is improved, and the upper coil can be formed without misalignment with the lower coil even with a fine coil pitch.
  • the present invention devisees three new technologies to invent a method for forming elements directly on an ASIC substrate: a method for forming an inverted trapezoidal groove using a positive resist coating, a two-layer resin coating method for forming highly accurate alignment marks on a resin coating, and an additional exposure method for ensuring symmetry in the height of both sides of the groove.
  • the present invention makes it possible to simultaneously form an inverted trapezoidal groove for arranging a magnetic wire with a symmetrical upper shape and a highly visible alignment mark on a photosensitive resin coating without damaging the ASIC substrate, and also improves the symmetry of the groove, making it possible to integrally form a GSR element with a fine coil pitch of 5 ⁇ m or less on the ASIC substrate.
  • FIG. 1 is a diagram showing a groove formed by RIE in a SiO 2 insulating film on an ASIC substrate.
  • FIG. 2 is a diagram showing projections and recesses on the surface of an ASIC board; This figure shows the alignment marks on the surface of an ASIC substrate before the metal film is deposited, and the marks and unevenness signals on the A1-A2 line.
  • 1A is a plan view of an element after an electrode extraction opening and a wire placement groove of an ASIC substrate have been exposed to and developed using a positive resist resin coating
  • FIG. 1B is an A-A' cross-sectional view of the element.
  • 1A shows the shape of a wire placement groove formed in a positive resist resin coating on an ASIC board after exposure and development
  • FIG. 1B shows the groove after a curing heat treatment to form an inverted trapezoid shape.
  • 1A is a cross-sectional view of the uneven state of the ASIC substrate surface
  • FIG. 1B is a cross-sectional view of the state in which the uneven state has been transferred to the resin surface after resin has been applied and cured.
  • This is a cross-sectional view of the grooves and alignment marks after a metal film is formed on an ASIC substrate by the two-layer resin method.
  • 13 shows the shape (a) of a wire placement groove and an opening for electrode extraction of the ASIC substrate after exposure and development of a positive resist resin coating on the ASIC substrate, and a diagram showing the shape (b) of the wire placement groove and the opening for electrode extraction of the ASIC substrate after additional exposure and curing heat treatment of only the wire placement groove portion after exposure and development.
  • 13 is a graph showing the relationship between the amount of additional exposure and the difference between the left and right sides when a positive resist resin film is exposed to light for forming electrode extraction openings and wire placement grooves on an ASIC board, and then developed, and the additional exposure is applied only to the grooves.
  • 1 is a cross-sectional view showing a GSR element fabricated in an inverted trapezoidal groove having an R-shaped bottom on an ASIC substrate.
  • FIG. 1A is a plan view of a groove formation portion and an alignment mark formation portion on an ASIC substrate
  • FIG. 1B is a cross-sectional view taken along line A1-A2.
  • 1 is a cross-sectional view of a GSR element and an alignment mark formed on an ASIC substrate by a two-layer resin coating method.
  • 1A is a plan view showing an inverted trapezoid groove and an alignment mark formed on an ASIC substrate by a two-layer resin coating method
  • FIG. 1B is a cross-sectional view taken along line A1-A2.
  • 1 is a cross-sectional view showing a GSR element produced according to the present invention.
  • FIG. 1 is a diagram showing 2-3 ⁇ m irregularities caused by circuit wiring on the surface of an ASIC substrate.
  • FIG. 13 is a diagram showing a state in which a first pedestal formed in a groove portion and an alignment mark portion is planarized by CMP. 13 is a diagram showing an inverted trapezoidal groove, a recess for an alignment mark, and an opening for extracting electrodes of an ASIC substrate simultaneously formed in the second resin film, and a curing heat treatment is performed after additional exposure only to the groove.
  • 1 is a diagram showing an alignment mark, a mark on the C1-C2 line, and a concave/convex signal after a metal film is formed on an ASIC substrate.
  • FIG. 2 is a plan view of a magnetic field detection element (assembly) and an alignment mark.
  • FIG. 2 is a plan view of a magnetic field detection element.
  • the method for producing a GSR element of the present invention comprises the steps of: A method for manufacturing a GSR element, comprising: a magnetic wire; a detection coil having a coil pitch of 10 ⁇ m or less, which is made up of a lower coil and an upper coil surrounding the magnetic wire; and electrode wiring, the GSR element being directly manufactured on a substrate of an application specific integrated circuit (hereinafter referred to as ASIC), (11) A process of applying a positive resist resin film onto the ASIC board, exposing and developing the film to simultaneously form an inverted trapezoid groove for installing the magnetic wire and a plurality of concave portions for alignment marks in the resin film, hardening the film by a curing heat treatment, and after forming the inverted trapezoid groove and the concave portions for alignment marks, applying a negative resist resin film, exposing and developing the film to leave the resin film only in the inverted trapezoid groove portion, and forming an R shape at the bottom of the groove by a curing heat treatment
  • step 14A a step of placing the magnetic wire in the inverted trapezoid groove in which the lower coil is formed while applying tension thereto, temporarily fixing the magnetic wire with resin, and then fixing the magnetic wire by a curing heat treatment; a step of removing insulating glass covering the wire in a wire electrode portion for joining the wire to an electrode wiring by CF 4 -RIE;
  • the present invention is characterized in that it comprises:
  • the GSR element 10 of the present invention is composed of an ASIC substrate 101, a SiO2 protective coating 102 on the ASIC substrate 101, a positive resist 103 coated on the SiO2 protective coating 102, an inverted trapezoidal groove 104 formed in the positive resist 103, a resin coating 100 placed at the bottom of the groove and forming an R-shape at the bottom, a lower coil 105 formed on the surface of the inverted trapezoidal groove 104 and on part of the upper surface of the positive resist 103, a magnetic wire 106 placed on the lower coil, a resin coating 108 that fixes the magnetic wire, a positive resist-based resin coating 109 that eliminates the step between the magnetic wire 106 and the groove 104, and an upper coil 107 formed on the resin coating 109 and connected to the lower coil 105.
  • the magnetic wire 106 is wound around a detection coil consisting of a lower coil 105 and an upper coil 107, and
  • a substrate 110 for forming a GSR element which is an intermediate product of the process of the present invention, will be described with reference to Fig. 11.
  • (a) shows a plan view
  • (b) is a cross-sectional view taken along the line A1-A2 in (a).
  • Fig. 11 shows only one GSR element for explanation.
  • An intermediate product of a GSR element forming substrate 110 is formed, which comprises a groove forming portion 11G consisting of an inverted trapezoid groove 114G for forming a GSR element on an ASIC substrate 111, and an alignment mark portion 11A consisting of an alignment mark recess 114A.
  • the groove forming portion 11G is made up of a positive resist 113G and an inverted trapezoidal groove 114G.
  • the alignment mark portion 11A is made up of a plurality of alignment marks 11a, and its cross section is made up of a positive resist 113A and an alignment mark recess 114A.
  • the metal film in the alignment mark portion functions as a reflective film.
  • the method for producing a GSR element of the present invention comprises the steps of: A method for manufacturing a GSR element, which comprises a detection coil having a coil pitch of 5 ⁇ m or less, which is made up of a magnetic wire, a lower coil and an upper coil surrounding the magnetic wire, and electrode wiring, directly fabricating the GSR element on a substrate of an application specific integrated circuit (hereinafter referred to as ASIC), comprising: (21) applying a negative resist-based first resin coating onto the ASIC substrate to form a first base in a groove forming portion and an alignment mark forming portion made of a flat and hard resin; (22) A process of applying a positive resist-based second resin coating thicker than the groove depth onto the first pedestal to form a second pedestal, simultaneously forming a rectangular recess for forming an inverted trapezoid groove (hereinafter referred to as a groove) for arranging the magnetic wire in the groove forming portion of the second pedestal and a recess for forming an alignment mark reces
  • ASIC application specific integrated circuit
  • step 25A placing the magnetic wire on the lower coil in the groove under tension, temporarily fixing the magnetic wire in the groove with resin, and further fixing the magnetic wire in the groove by performing a curing heat treatment while still applying tension; a step of removing insulating glass covering the wire in a wire electrode portion for joining the wire to an electrode wiring by CF 4 -RIE;
  • the present invention is characterized in that it comprises:
  • the grooves and alignment marks can be formed simultaneously in the resin coating, and highly visible alignment marks can be formed on the resin coating, making it possible to integrally form a GSR element consisting of a fine pitch coil on the ASIC substrate.
  • FIG. 12 shows a cross-sectional view of a GSR element manufactured according to the present invention and an alignment mark used in the manufacture.
  • the ASIC substrate 120 has an unevenness 1201 of about 2 to 3 ⁇ m on its surface due to the integrated circuit wiring. Therefore, an alignment mark forming section 123 is required in addition to a normal groove forming section 122.
  • a first seat 1211 is formed on the ASIC 20.
  • an inverted trapezoidal groove 1221 is formed in a second seat 1212 constituting an element.
  • a lower coil 1222 is formed on the surface of the groove 1221, and a magnetic wire 1223 with an insulating glass coating is arranged on the upper part of the lower coil 1222.
  • the magnetic wire is fixed with resin and embedded in the groove 1221.
  • An upper coil 1224 is formed on the magnetic wire 1223 via resin, and is connected to the lower coil 1222 at both ends and wound around the magnetic wire 1223 .
  • Wire electrodes are formed on both ends of the magnetic wire 1223 and both ends of the surrounding coil.
  • a first base 1211 is formed on the ASIC 120.
  • a second base 1212 constituting the alignment mark is formed, which has an alignment mark recess, which is a long, steep, pseudo-inverted trapezoid groove 1231, and a metal film is formed on the surface of the recess.
  • a reflective film made of a metal film is formed on the flat surface.
  • an auto-alignment mechanism enables formation of the lower coil and the upper coil with a coil pitch of 5 ⁇ m or less.
  • the coil pitch is 3 ⁇ m
  • the coil width is 2.0 ⁇ m
  • the coil spacing is 1.0.
  • accuracy of 0.5 ⁇ m or less is required.
  • FIG. 13 is a plan view and a cross-sectional view.
  • 1A is a plan view
  • FIG. 1B is a cross-sectional view taken along line A1-A2 of the plan view of FIG.
  • a groove forming portion 132 and an alignment mark forming portion 133 are formed on an ASIC substrate 130.
  • a second pedestal consisting of an inverted trapezoid groove and a flat surface is formed on a first pedestal 1311 having a flat upper surface.
  • the alignment mark section has an alignment mark recess, which is a long, inverted trapezoidal groove 1331, formed on a first base 1311 with a flat upper surface, and a second base 1312 consisting of a flat surface.
  • the two-layer resin coating method is used to simultaneously form grooves and alignment marks in the resin coating on the ASIC board, and the manufacturing flow for the GSR element consisting of a narrow-pitch coil using highly visible alignment marks is shown in Figure 7 and explained below.
  • the thickness of the first pedestal is 10 ⁇ m in step (1b), and even after the curing heat treatment, it is still about 8 ⁇ m, so there is no problem with CMP.
  • the groove is deformed from a rectangular parallelepiped shape to an inverted trapezoid shape by the stress generated during the curing heat treatment.
  • the upper surface of the second pedestal 72 remains flat.
  • the groove has a depth of 8 ⁇ m.
  • the width of the lower coil is 2.0 ⁇ m, and the thickness is 1.0 ⁇ m.
  • step (2m) to eliminate the step between the groove and the wire, a positive resist resin film is applied, exposed, baked, developed, and cured at 280°C for 1 hour to smooth out the shape of the upper part of the groove. After that, a metal film is formed over the entire ASIC board, and a resist is applied.
  • the upper coil has a width of 2.0 ⁇ m and a thickness of 1.0 ⁇ m.
  • the coil connection portion consisting of the connection portion of the lower coil and the connection portion of the upper coil is formed with a line width of 2.0 ⁇ m and a coil pitch of 3.0 ⁇ m.
  • the method for producing a GSR element of the present invention comprises the steps of: A method for manufacturing a GSR element, comprising: a magnetic wire; a detection coil having a coil pitch of 10 ⁇ m or less, which is made up of a lower coil and an upper coil surrounding the magnetic wire; and electrode wiring, the GSR element being directly manufactured on a substrate of an application specific integrated circuit (hereinafter referred to as ASIC), (31) a step of applying a positive resist type resin film (hereinafter referred to as a P-type resin film) onto the ASIC substrate, exposing and developing the film to simultaneously form grooves for disposing the magnetic wires in the P-type resin film and openings for electrode extraction (hereinafter referred to as openings) on the ASIC substrate; a step of exposing only the groove portion for arranging the magnetic wire to light, and then curing the P-based resin film by a curing heat treatment to harden the P-based resin film, thereby forming an inverted trapezoid groove having
  • ASIC application specific integrated
  • step 31A a step of coating a positive resist type resin film (hereinafter referred to as a P-type resin film) on the ASIC substrate, exposing and developing the film to simultaneously form grooves for placing the magnetic wires in the P-type resin film, openings for electrode extraction (hereinafter referred to as openings) on the ASIC substrate, and alignment marks; and a step of performing additional exposure only on the groove portion for locating the magnetic wire, and then performing a curing heat treatment to harden the P-based resin coating, thereby forming an inverted trapezoidal groove with improved symmetry at the top of the groove.
  • the present invention is characterized in that it comprises:
  • a negative resist-based first resin film (hereinafter referred to as an N-based first resin film) is applied onto the ASIC substrate, exposed to light, and developed. After a curing heat treatment, a planarization treatment is performed to form a flat and hard resin first base in a groove formation portion and an alignment mark formation portion.
  • a step of applying a positive resist-based second resin coating (hereinafter referred to as a P-based second resin coating) having a thickness greater than the depth of the groove on the ASIC substrate to form a second pedestal, and exposing and developing the groove, an opening for electrode extraction of the ASIC substrate (hereinafter referred to as an opening), and the alignment mark on the second pedestal; a step of forming an inverted trapezoidal groove with improved symmetry at the top of the groove by subjecting the second pedestal to additional exposure only in the groove portion and then subjecting the second pedestal to a curing heat treatment;
  • the present invention is characterized in that it comprises:
  • step 31C applying a positive resist type resin film (hereinafter referred to as a P-type resin film) on the ASIC substrate, exposing and developing the film to simultaneously form grooves for arranging the magnetic wires in the P-type resin film and openings for electrode extraction (hereinafter referred to as openings) on the ASIC substrate; a step of exposing only the groove portion for arranging the magnetic wire to additional light, and then curing the P-based resin film by a curing heat treatment to harden the P-based resin film, thereby forming an inverted trapezoid groove with improved symmetry at the top of the groove and the opening portion on the ASIC substrate; Further, a process of applying a negative resist type resin film (hereinafter referred to as an N-type resin film) to the ASIC substrate, exposing and developing the N-type resin film so that the N-type resin film remains only in the groove portion of the inverted trapezoidal groove, and forming an R-shape at the bottom of the groove by a
  • step 31A (31D) applying a positive resist type resin film (hereinafter referred to as a P-type resin film) on the ASIC substrate, exposing and developing the film to simultaneously form grooves for placing the magnetic wires in the P-type resin film, openings for electrode extraction (hereinafter referred to as openings) on the ASIC substrate, and alignment marks; a step of exposing only the groove portion for locating the magnetic wire to additional light, and then curing the P-based resin film by a curing heat treatment to harden the P-based resin film, thereby forming an inverted trapezoidal groove with improved symmetry at the top of the groove; Further, a process of applying a negative resist type resin film (hereinafter referred to as an N-type resin film) to the ASIC substrate, exposing and developing the N-type resin film so that the N-type resin film remains only in the groove portion of the inverted trapezoidal groove, and forming an R-shape at the bottom of the groove by a curing heat treatment;
  • step 35 after arranging the magnetic wire in the inverted trapezoidal groove, a positive resist resin film is applied to the entire surface of the ASIC substrate, exposed to light, and developed to leave a positive resist resin film (hereinafter referred to as a P-type resin film) only on the groove and the magnetic wire, and a curing heat treatment is performed to smooth out the step between the groove and the magnetic wire; forming a metal film on the entire surface of the ASIC substrate to form the upper coil and the electrode wiring;
  • a method for manufacturing a GSR element comprising the steps of:
  • the amount of exposure when additionally exposing only the groove portion for arranging the magnetic wire is 4% or less of the amount of exposure of the groove portion.
  • the thickness of the N-based first resin coating is at least three times the irregularities on the ASIC substrate.
  • FIG. 14 shows a cross-sectional structure of a magnetic field detection element manufactured according to the present invention.
  • Fig. 14 is a cross-sectional view taken along the line A1-A2 shown in Fig. 13. Also shown is a cross-sectional view of the alignment mark portion 133 shown in Fig. 13.
  • On the ASIC substrate 141 there are irregularities 1411 caused by the integrated circuit, and a protective film 143 is formed on the surface other than the electrode extraction opening 1431.
  • a first seat 1491 is disposed in the groove formation portion, and an inverted trapezoidal groove 142 is formed in the second resin film 1492 without being affected by the irregularities 1411 of the ASIC substrate, and an R-shaped negative resist resin coating 1423 is formed on the bottom of the groove.
  • the magnetic wire 145 is disposed and fixed by the negative resist resin film 1451 .
  • the magnetic wire 145 is covered with insulating glass having a thickness of 1.0 ⁇ m and has a diameter of 12 ⁇ m.
  • a positive resist resin coating 1452 is formed between the groove 142 and the magnetic wire 145 .
  • This positive resist resin coating 1452 also extends over the magnetic wire 145, and the upper coil 146 is formed thereon.
  • the lower coil 144 and the upper coil 146 are connected without any problem because of the positive resist resin coating 1452 and the improved symmetry of the upper part of the groove.
  • the alignment mark portion 149 there are irregularities 1411 on the ASIC substrate 141 caused by the integrated circuit, but the first base 1491 is arranged in the alignment mark portion, and an alignment mark recess 1494 is formed in the second resin film 1492 without being affected by the irregularities 1411 of the ASIC substrate.
  • the alignment mark recess is carved down to the first base, and a reflective film 1493 is further formed on it, improving visibility.
  • the magnetic wire is made of a CoFeSiB-based amorphous alloy, has a diameter of 1 to 15 ⁇ m, and is coated with an insulating film (glass film) having a thickness of 0.5 to 2 ⁇ m.
  • the detection coil is composed of a lower coil, an upper coil and a connection portion, with a coil pitch of 1 to 5 ⁇ m, a coil width of 0.5 to 4.5 ⁇ m, and the thicknesses of the lower and upper coils being 0.1 to 1.0 ⁇ m respectively.
  • the electrode wiring is a general term for external electrodes, electrodes (terminals), and wiring (connection wiring) that connects external electrodes and electrodes (terminals).
  • the external electrodes are input/output electrodes from the GSR element, and in the present invention, are connected to or formed integrally with the electrodes of the ASIC.
  • Electrodes also called terminals
  • the detection coil and the electrode wiring are formed by evaporating or plating a conductive metal such as gold.
  • the ASIC substrate has a predetermined size on which a number of ASICs are formed so that a number of GSR devices can be manufactured. For example, if the size of the ASIC board is 20 mm in length and 20 mm in width, This corresponds to an element substrate consisting of an assembly of elements each consisting of one GSR element and one ASIC, and by dividing the element substrate, it is possible to obtain about 50 to 1500 elements.
  • Steps (31), (31A) to (31D) are steps for forming an inverted trapezoid groove for aligning magnetic wires in the ASIC substrate. 15, unevenness 151 of 2 to 3 ⁇ m due to circuit wiring exists on the surface of the ASIC substrate 150.
  • a protective film 1501 such as SiO2 is formed on the surface of the ASIC substrate 150. Therefore, first, in order to eliminate this step, a first seat is formed in the groove forming portion and the alignment mark recess forming portion.
  • a negative resist-based first resin coating is applied onto the ASIC substrate 150, and exposure and development are performed using a mask material to form a first seat consisting of a groove forming portion for arranging magnetic wires for forming the GSR element and an alignment mark forming portion.
  • a curing heat treatment is performed to harden the first resin film that will become the first base. Even at this point, the unevenness on the ASIC board is transferred and remains on the surface of the first resin film that will become the first base.
  • the temperature for the curing heat treatment is 250 to 350° C. If the temperature is less than 250° C., the curing is insufficient, and there is a concern that the shape may change in a later process, whereas if the temperature exceeds 350° C., there is a concern that problems may occur in the ASIC circuit.
  • the unevenness remaining on the first resin coating of the first base consisting of the groove forming portion and the alignment mark forming portion, where the unevenness has been transferred and hardened is flattened by CMP to form a flat first base 16C consisting of the groove forming portion and the alignment mark forming portion, as shown in FIG. 16.
  • a resist may be applied to the entire surface of the ASIC substrate 160, the resist on the first pedestal may be removed, the surface of the ASIC substrate other than the first pedestal may be protected, CMP may be performed to flatten the first pedestal, and the resist that was protecting the surface of the ASIC substrate other than the first pedestal may be peeled off.
  • the thickness of the first resin coating that forms the first pedestal 16C is preferably at least three times the irregularities 161 on the surface of the ASIC substrate 160 on which the first pedestal is placed. If it is less than three times, the first pedestal itself will become thin before the irregularities of the first pedestal can be flattened by CMP in this process.
  • a positive resist resin film 173 is applied to the entire surface of the ASIC substrate, and exposed and developed through a mask material to form rectangular parallelepiped grooves, concave portions for alignment marks, and openings for electrode extraction of the ASIC substrate in the resin film.
  • the amount of exposure at this time is 1500 mm2.
  • additional exposure is applied only to the grooves.
  • the amount of exposure at this time is 5% or less of the initial exposure amount, that is, 1 to 4%.
  • the shape of the groove 174 becomes an inverted trapezoid, as shown in FIG. 17, and because additional exposure has been performed, the resist height of the resist 177 in the groove closest to the electrode extraction opening 176 of the ASIC board and the resist height of the other resist 178 are symmetrical.
  • the alignment mark recess 17A is formed at the same time as the groove portion 17B, it will have an inverted trapezoid shape like the groove, which may reduce visibility. Therefore, the area other than the alignment mark portion is protected with resist, and the inverted trapezoid alignment mark recess 17A formed in the second resin coating is itself used as a mask to excavate the first pedestal by RIE, thereby increasing the steepness of the alignment mark recess.
  • Step (32) is a step of forming a lower coil in the inverted trapezoidal groove.
  • a negative resist type resin film (hereinafter referred to as an N-type resin film) is applied to the bottom of the groove 174 of the ASIC substrate, exposed to light, and developed so that the N-type resin film remains only in the groove portion, and an R-shape is formed in the bottom of the groove by a curing heat treatment.
  • a metal film is formed on the surface of the ASIC substrate.
  • the film thickness is 0.1 to 1.0 ⁇ m.
  • This metal film also functions as a reflective film 105 in the alignment area, improving the visibility of the alignment marks.
  • the alignment mark formed in this manner and the signal of the mark are shown in Figure 18. There is no noise in the signal portion of the alignment mark, and only the signal of the alignment mark is observed, confirming the improvement in visibility.
  • a resist is applied to the entire surface of the ASIC board, and exposure and development are performed through a mask material to form a coil pattern.
  • the electrode extraction openings of the ASIC board are also opened.
  • the resist is peeled off and the metal film in the non-plated areas is etched.
  • the mask pattern for forming the coil by plating and the mask opening are reversed.
  • Step (33) is a step of arranging and fixing the magnetic wire in the groove.
  • the lower coil is formed along the side of the groove, and the magnetic wire is placed thereon while being subjected to a tension of 30 to 100 kg/mm2.
  • both ends of the magnetic wire are temporarily fixed with adhesive, tape, etc., and then a resin film is applied to the entire surface of the substrate, exposed to light, and developed so that the resin film remains only in the grooves.
  • the magnetic wire is then fixed by a curing heat treatment at a temperature of 250 to 350°C. As a result, the magnetic wire is fixed inside the groove and simultaneously heat-treated while tension is applied thereto, thereby improving the GSR characteristics.
  • Step (34) is a step of partially removing the glass coating covering the magnetic wire in order to contact the magnetic wire with an electrode.
  • resist is applied to the entire surface of the substrate.
  • the resist is opened only at the electrode lead-out portions of the magnetic wires of each element. In other words, everything other than the electrode lead-out portions is protected by resist.
  • CF4-RIE By performing CF4-RIE in this state, it is possible to remove the SiO2 that covers only the electrode lead-out portions of the magnetic wires.
  • the resist is removed, the glass coating is partially removed, and the electrodes can be brought into contact with the magnetic wires. If the magnetic wire is not covered with insulating glass, this step can be omitted.
  • Step (35) is forming the upper coil on the magnetic wire.
  • a positive resist resin film is applied to the entire surface of the ASIC board, exposed to light, and developed so that the positive resist resin film (hereinafter referred to as P-type resin film) remains only in the groove and the magnetic wire portion, and a curing heat treatment is performed to smooth out the stepped portions.
  • a metal film is formed over the entire surface of the substrate. The film thickness is 0.1 to 1.0 ⁇ m.
  • resist is applied to the entire surface of the substrate, and using highly visible alignment marks with an auto-alignment mechanism, exposure and development are performed through a mask material to form a coil pattern.
  • the resist is peeled off and the metal film in the non-plated areas is etched.
  • the mask pattern for forming the coil by plating and the mask opening are reversed. This process prevents breaks in the upper coil and also forms highly visible alignment marks, so there are no problems with aligning it with the lower coil.
  • Step (36) is a step of dividing the element substrate, which is an assembly of elements each including a magnetic wire, a detection coil, and the electrode wiring, into individual pieces.
  • FIG. 19 shows a plan view of an element fabricated on an ASIC substrate according to the present invention.
  • the ASIC board 19 is an assembly of ASIC elements, and for example, a 20 mm square ASIC board is made up of about 300 ASIC elements. Since one magnetic field detection element is formed on one ASIC element, a large number of magnetic field detection elements 19a and alignment marks 19b are arranged on the four corners of the ASIC board 19.
  • the magnetic field detection elements are manufactured on a board-by-board basis, and are finally separated into individual pieces.
  • the magnetic field detection element 20 has an entire surface covered with a second resin coating 201, and has a width (left-right direction) of 1.2 mm, a length (up-down direction) of 1.2 mm, and a thickness of 0.75 mm.
  • An inverted trapezoidal groove 202 and a lower coil 203 are formed on the ASIC board 19, and a magnetic wire 204 is disposed and fixed therein.
  • a detection coil consisting of a lower coil 203 and an upper coil 205 winds around the magnetic wire.
  • the detection coil has a coil pitch of 3.0 ⁇ m, a line width of 1.2 ⁇ m, and a thickness of 1.5 ⁇ m.
  • Two wire terminals 206 are formed on the magnetic wire 204, and wiring 207 and a wire electrode 208 are formed to connect to the wire terminals 206.
  • wiring 203a, 205a and two coil electrodes 209 are formed to connect to the lower coil 203 and the upper coil 205.
  • a first base is placed on the ASIC board using a negative resist resin coating, and then a positive resist resin coating is used on top of that to simultaneously expose and develop the groove for placing the magnetic wire, the recesses for the alignment marks, and the electrode extraction section of the ASIC board.
  • a curing heat treatment is performed to harden the resin coating, forming an inverted trapezoidal groove with symmetrical left and right shapes, making it possible to directly manufacture a GSR element with a fine coil with a narrow pitch on the ASIC board.
  • Step (3a) First, a negative resist-based first resin film is applied to a thickness of 10 ⁇ m on an ASIC board that has unevenness of several ⁇ m caused by the integrated circuit. After exposure and development, a curing heat treatment is performed at 280°C for 1 hour, and a flat and hard first pedestal is placed at the location where the inverted trapezoid groove and alignment mark will be placed. That is, a first pedestal is formed, which is composed of the groove forming portion B and the alignment mark forming portion A. At this time, the thickness of the first pedestal is 9 ⁇ m.
  • Step (3b) In this state, the unevenness of the ASIC substrate is still transferred onto the surface of the first pedestal, so a resist is applied to the entire surface of the ASIC substrate, and a mask material is used to expose and develop the resist, removing only the resist on the first pedestal and protecting the ASIC surface other than the first pedestal. Then, the surface of the first pedestal, which has been hardened by a curing heat treatment, is planarized by CMP (Chemical Mechanical Polishing). Thereafter, the resist protecting the ASIC surface other than the first pedestal is removed with a resist remover to form a flattened first pedestal C. At this time, the film thickness of the first pedestal C is about 6 ⁇ m.
  • Step (3c) Next, a positive resist-based second resin coating is applied to the flattened first base with a thickness of 10 ⁇ m, and the groove, alignment mark recess, and ASIC substrate electrode extraction portion are exposed and developed simultaneously. Since the first base C is flattened, the second base of the groove forming portion B and the alignment mark forming portion A is not affected by the unevenness of the ASIC substrate.
  • the exposure dose at this time is 1500 mJ/ cm2 . Then, only the grooves are exposed again using a mask. This time, the exposure dose is 40 mJ/ cm2 .
  • the grooves change to an inverted trapezoid shape due to the stress generated during the heat treatment, and the shape of the upper part of the groove becomes almost symmetrical.
  • the shape and height of the upper part of the groove near the opening are almost the same as that of the upper part of the other groove, and the asymmetry is greatly improved.
  • Step (3d) Next, a negative resist resin film is applied to the entire ASIC board, exposed to light, and developed to leave the resist only in the grooves. After that, a curing heat treatment is performed at 250°C for 1 hour to form an R shape at the bottom of the groove.
  • Step (3e) On the other hand, since the alignment mark portion also has an inverted trapezoidal shape, in order to make the shape steeper, the area other than the alignment mark portion is protected with resist, and the first pedestal is excavated 1 ⁇ m by O 2 -RIE using the inverted trapezoidal alignment mark recess itself formed in the second resin coating as a mask. The protecting resist is then removed with a resist remover.
  • Step (3f) Next, a Cr/Au laminated film is formed over the entire ASIC substrate, with a thickness of 0.01/0.03 ⁇ m. This film is used as a reflective film in the alignment mark recesses to improve visibility. Then, using the alignment mark recesses, resist is applied to the entire ASIC substrate, exposed, and developed. Through plating and etching processes, a lower coil having a width of 1.2 ⁇ m and a thickness of 0.7 ⁇ m is formed along the surface of the inverted trapezoidal groove.
  • Step (3g) Next, a CoFeB magnetic wire covered with 1 ⁇ m thick insulating glass is placed on top of the lower coil in the groove while applying a tension of 76 kg/ mm2 , and temporarily fixed with adhesive, tape, etc. Then, resin is applied, exposed, developed, and cured at 250°C for 1 hour to fix it in the groove. At this time, the magnetic wire 19 is heat-treated while still under tension, which improves the GSR characteristics.
  • Step (3h) Since the surface of the magnetic wire is covered with a glass (SiO 2 ) film, this portion of the glass film is removed in order to bring the electrodes into contact with the magnetic wire.
  • a resist is applied to the entire surface of the ASIC board, and then exposed and developed to open the resist only in the areas where the electrodes are to come into contact with the magnetic wires. After removing the glass coating with CF4-RIE, the resist is peeled off from the entire board.
  • Step (3i) Next, to eliminate the step between the magnetic wire and the groove, a positive resist is applied to the entire ASIC board, exposed to light, and developed, leaving the resist only in the groove, and then the resist is hardened by a curing heat treatment at 250°C for 1 hour. By heat treating the positive resist, the edge shape becomes smooth, preventing breaks when forming the upper coil.
  • Step (3j) a Cr/Au laminated film is formed to a thickness of 0.01/0.03 ⁇ m to form the lead wires of the upper coil and the conductive portion of the magnetic wire, the openings for electrode extraction and the wiring (wiring) of the ASIC board.
  • resist is applied, exposed, and developed to form the upper coil, the lead wire pattern of the conductive part of the magnetic wire, and the opening for the electrode of the ASIC board on the upper part of the magnetic wire.
  • the alignment mark has a first base and a reflective film, so the signal strength is sufficient and it can be aligned with the lower coil by automatic alignment without any problems.
  • This pattern is plated, wet-plated, and then the resist is removed to form an upper coil with a line width of 1.2 ⁇ m and a thickness of 0.8 ⁇ m on top of the magnetic wire.
  • the connection with the lower coil has a gentle shape, and the upper coil is also formed without any breaks.
  • lead lines for the conductive parts of the magnetic wires, openings for electrode extraction of the ASIC board, and wiring are also formed.
  • the first to third inventions make it possible to integrally form a GSR element with a fine pitch coil on an ASIC substrate.
  • the present invention integrates a GSR element with an ASIC to create an ultra-thin, ultra-compact GSR sensor, which is expected to be used in applications that require ultra-compactness and high performance, such as motion devices in living organisms.
  • the present invention can be applied to small, high-performance GSR sensors for use in automobiles or wearable computers.
  • FIG. 170 ASIC substrate subjected to curing heat treatment after additional exposure.
  • 1701 Protective film on the surface of the ASIC substrate 171: Unevenness on the ASIC substrate 17A: Alignment mark recess forming portion, 17B: groove forming portion, 17C: First base 173 after curing heat treatment and flattening
  • CMP Positive resist type second resin coating
  • 174 inverted trapezoid groove
  • 176 ASIC electrode extraction opening
  • 177 Groove resist on the side closer to the opening for extracting the ASIC electrodes
  • 178 Groove resist on the other side

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Abstract

[Problem] When forming GSR elements directly onto an integrated circuit substrate (ASIC), it has been difficult to form micro-coils because of a) the method of forming inverted trapezoidal grooves, b) unevenness in the ASIC substrate surface, and c) the placement of openings in the ASIC substrate. [Solution] a) A positive-resist resin film is applied onto an ASIC substrate, and is simultaneously exposed and developed with grooves for installing magnetic wires and with a plurality of alignment-mark recesses to form inverted trapezoidal grooves, b) the primary bases are flattened by a two-layer resin method to eliminate the unevenness, and c) partial exposure for only the grooves for installing magnetic wires is added to form inverted trapezoidal and bilaterally-symmetrical grooves. GSR elements having a micro-coil pitch of 3 μm or less can thereby be manufactured directly onto ASIC substrates.

Description

GSR素子の製造方法Manufacturing method of GSR element
 本発明は、磁界検出素子と特定用途向け集積回路(以下、ASICという。)との一体化プロセスによるGSR素子の製造方法に関する。 The present invention relates to a method for manufacturing a GSR element through an integration process of a magnetic field detection element and an application specific integrated circuit (hereinafter referred to as ASIC).
高感度磁気センサには、ホールセンサ、GMRセンサ、TMRセンサ、高周波キャリアセンサ、FGセンサ、MIセンサ、GSRセンサなどがある。これらのセンサのうち、ホールセンサ、GMRセンサ、TMRセンサ、キャリアセンサは素子とASICが一体化されて小型化、薄型化は実現されているが、検出感度の改善が課題である。
一方、FGセンサ、MIセンサ、GSRセンサは高い感度を有するが、素子とASICが別々に配置されてワイヤボンディングで接合されており、センサの薄型化、小型化が課題である。
High-sensitivity magnetic sensors include Hall sensors, GMR sensors, TMR sensors, high-frequency carrier sensors, FG sensors, MI sensors, GSR sensors, etc. Of these sensors, Hall sensors, GMR sensors, TMR sensors, and carrier sensors have been made smaller and thinner by integrating the element with an ASIC, but improving detection sensitivity remains an issue.
On the other hand, FG sensors, MI sensors, and GSR sensors have high sensitivity, but the element and ASIC are arranged separately and joined by wire bonding, making it difficult to reduce the thickness and size of the sensors.
この課題を解決するために、本発明者らは、GSR素子をASIC表面の上に形成する技術開発に取り組んだ結果、センサの小型化、薄型化を実現した(特許文献1)。
特許文献1にて、ASIC面上に絶縁性レジストを塗布し、そこに磁性ワイヤを配置する溝を形成し、磁性ワイヤと磁性ワイヤを周回する検出コイルおよび電極からなるGSR素子をASIC面上に一体形成した薄型高感度磁気センサが開示されている。しかし、その製造方法についてその後の改良が続けられているが、現時点ではその技術の詳細は公開されていない。
In order to solve this problem, the present inventors have worked on developing technology for forming a GSR element on the surface of an ASIC, and as a result have achieved a smaller, thinner sensor (Patent Document 1).
Patent Document 1 discloses a thin, highly sensitive magnetic sensor in which an insulating resist is applied to the ASIC surface, a groove is formed therein in which a magnetic wire is disposed, and a GSR element consisting of a magnetic wire, a detection coil surrounding the magnetic wire, and electrodes is integrally formed on the ASIC surface. However, although improvements have been made to the manufacturing method since then, the details of the technology have not been disclosed at present.
一方、センサの高感度化のためには、微細ピッチコイルを形成してコイルの巻き数を増やす必要がある。しかし、コイルピッチを微細化するほど、ASIC基板の位置とマスクの位置をさらに精度よく合わせることが求められる。その精度を実現するためには、ASIC基板上に視認性の高いアライメントマークを精度高く形成する必要がある。 On the other hand, to increase the sensitivity of the sensor, it is necessary to form a fine pitch coil and increase the number of turns in the coil. However, the finer the coil pitch, the more precisely it is required to align the position of the ASIC board and the position of the mask. To achieve this precision, it is necessary to form highly visible alignment marks with high precision on the ASIC board.
一般的には、アライメントマークは平坦な部分に作られたSiO2膜に形成するために、視認性に問題はなかった。またアライメントマークの形成方法は、特許文献2、特許文献3および特許文献4などに開示されているが、いずれも感光性樹脂の上にアライメントマークを形成するものではない。感光性樹脂上に視認性の高いアライメントマークを形成する技術の検討も課題のひとつである。 Generally, alignment marks are formed on a SiO2 film made on a flat portion, so there are no problems with visibility. Methods for forming alignment marks are also disclosed in Patent Documents 2, 3, and 4, but none of them form alignment marks on photosensitive resin. Another issue is to investigate technology for forming highly visible alignment marks on photosensitive resin.
公開特許公報2019-191016Published Patent Publication No. 2019-191016 公開特許公報2006-229132Published Patent Publication No. 2006-229132 公開特許公報2009-004793Published Patent Publication No. 2009-004793 特許公報第2016776号公報Patent Publication No. 2016776
 磁性ワイヤを周回するコイルをワイヤ近傍に形成するためには、磁性ワイヤを配置する溝に沿って下部コイルを形成する必要がある。本発明者らは、Si基板に溝を形成し溝の形状を逆台形状にすることで、断線せずに溝に沿って下部コイルを形成できることを見出した。 In order to form a coil that goes around a magnetic wire near the wire, it is necessary to form a lower coil along the groove in which the magnetic wire is placed. The inventors discovered that by forming a groove in a Si substrate and making the groove in an inverted trapezoid shape, it is possible to form a lower coil along the groove without breaking the wire.
しかし、ASIC基板上にGSR素子を一体化形成する際には、ASIC基板面上には回路配線が存在するので、ASIC基板に直接溝を加工することはできない。そこで、ASIC基板11上にSiO2などの絶縁膜を成膜し、RIE(Reactive Ion Etching)で溝を作製したが、その形状は図1に示すように直方体形状となってしまい、逆台形状の溝を形成できないことがわかった。 However, when integrating a GSR element onto an ASIC substrate, the circuit wiring is present on the surface of the ASIC substrate, so it is not possible to process grooves directly into the ASIC substrate. Therefore, an insulating film such as SiO2 was formed on the ASIC substrate 11, and grooves were created using RIE (Reactive Ion Etching); however, the resulting shape was a rectangular parallelepiped as shown in Figure 1, and it was found that an inverted trapezoid groove could not be formed.
 そこで、ASIC基板上に磁性ワイヤを配置するための逆台形状の溝を形成するプロセスを検討した結果、以下の3つの課題があることがわかった。 As a result of investigating the process of forming an inverted trapezoidal groove for placing magnetic wires on an ASIC board, the following three issues were identified:
第1の課題は、逆台形状の溝の形成方法である。
前述のように、SiO2などの絶縁膜を成膜し、RIEで溝を作製するとみぞの形状は直方体となってしまうため、レジストを用い、フォトリソグラフィ工程のみで溝形成する検討を行った。一般的に構造物として残す感光性樹脂としてはエポキシ系のネガタイプのレジスト(以下、ネガレジストという。)が知られている。ネガレジストの特徴はパターニング後のエッジ形状が急峻であり、構造物として残すためのキュア熱処理後も直方体形状の溝となって形状変化が起こらなかった。したがって、ネガレジストを用いて溝に沿って下部コイルを形成することは困難であることがわかった。
The first problem is how to form the inverted trapezoidal groove.
As mentioned above, if an insulating film such as SiO2 is formed and a groove is created by RIE, the shape of the groove will be rectangular, so we investigated using resist to form the groove only through the photolithography process. Generally, epoxy-based negative type resists (hereinafter referred to as negative resists) are known as photosensitive resins that remain as structures. The characteristic of negative resists is that the edges after patterning are steep, and even after the curing heat treatment to leave the structure, the groove remains rectangular, with no change in shape. Therefore, we found that it is difficult to form a lower coil along the groove using negative resist.
一方、センサの高感度化には、コイルピッチを10μm以下へと微細化しコイルの巻き数を増やす必要がある。しかし、コイルピッチを微細化するほど、ASIC基板(以下、基板という。)の位置と複数個のマスクの位置をさらに精度よく合わせることが求められる。その精度を実現するためには、前記溝形成時に同時に視認性の高いアライメントマークを形成することで、合わせ精度の向上が期待できる。 On the other hand, to increase the sensitivity of the sensor, it is necessary to reduce the coil pitch to 10 μm or less and increase the number of turns in the coil. However, the finer the coil pitch, the more precisely it is required to align the position of the ASIC board (hereinafter referred to as board) and the positions of the multiple masks. In order to achieve this precision, it is expected that alignment precision will be improved by forming highly visible alignment marks at the same time as forming the grooves.
第2の課題は、アライメントマークの形成方法である。
センサの高感度化を達成するためには、コイルピッチを5μm以下へと微細化しコイルの巻き数を増やす必要があるが、コイルピッチを微細化するほど、ASIC基板の位置と複数個のマスクの位置をさらに精度よく合わせることが求められる。そのため本発明者らは、アライメントマークを溝と同時形成することに思い至った。
The second problem is the method of forming the alignment marks.
In order to achieve high sensitivity of the sensor, it is necessary to reduce the coil pitch to 5 μm or less and increase the number of turns of the coil, but the finer the coil pitch, the more accurately it is required to align the position of the ASIC board and the positions of the multiple masks. Therefore, the inventors came up with the idea of forming alignment marks and grooves at the same time.
従来アライメントマークは基板保護膜であるSiO2上に形成するが、溝と同時形成するには樹脂被膜上に形成することになる。しかし、図2に示すようにASIC基板表面には集積回路起因の2~3μmの凹凸が存在する場合がある。この場合には、溝形成に必要な膜厚(5~15μm程度)の樹脂被膜を塗布しても、その表面には凹凸が転写されてしまい、SiO2上のようにアライメントマーク形成に必要な平坦な面を得ることが困難である。 Traditionally, alignment marks are formed on SiO2, a substrate protective film, but to form them simultaneously with grooves, they must be formed on a resin coating. However, as shown in Figure 2, the surface of an ASIC substrate may have unevenness of 2 to 3 μm caused by the integrated circuit. In this case, even if a resin coating of the thickness required for groove formation (approximately 5 to 15 μm) is applied, the unevenness is transferred to the surface, making it difficult to obtain the flat surface required for alignment mark formation, as on SiO2.
また、コイルピッチを微細化するほど、優れた上下のコイルの合わせ精度が必要となり、高度な位置合わせ機能を有するオートアライメント機構などが必要となる。オートアライメント機構は、アライメントマーク画像のコントラストに左右される。前述のようにASIC基板表面の凹凸があると、図43に示すようにシグナルが乱れてマーク画像のコントラストが歪んでしまう。そのため、マークを誤認識し、コイルピッチ5μm以下の微細なコイルを形成しようとすると、下部コイル形成後、上部コイルを形成する際に両者の接続位置がずれ、コイルの接続不良という問題が発生する。 Furthermore, the finer the coil pitch, the more accurate alignment of the upper and lower coils is required, necessitating an auto-alignment mechanism with advanced alignment functions. The auto-alignment mechanism depends on the contrast of the alignment mark image. As mentioned above, if there are irregularities on the surface of the ASIC board, the signal will be disturbed and the contrast of the mark image will be distorted, as shown in Figure 43. Therefore, if the mark is misrecognized and an attempt is made to form a fine coil with a coil pitch of 5 μm or less, the connection positions of the two will be misaligned when forming the upper coil after forming the lower coil, resulting in a problem of poor coil connection.
第3の課題は、ネガレジストに代わり、ポジレジスト系樹脂被膜を用いて逆台形状の溝の形成プロセスを検討する過程で起きた溝が非対称となってしまうという問題である。
ASIC基板には既に集積回路配線が存在し、電極取出し用開口部などの配置が決まっており、図4(a)に示すように、磁性ワイヤを配置する直線的な溝431を形成できる場所には制限がある。すなわち、溝の左右の構造はASIC基板の配線に起因するので、ワイヤを配置する直線的な溝を形成する場所近傍のASIC基板の電極取出し部421は溝に対して左右非対称となってしまう。
その結果、ポジレジスト系の樹脂被膜43に溝431とASIC基板の電極取出し部432を同時にマスク露光、現像をした後に逆台形状の溝を形成するためにキュア熱処理を行うと、図4(b)に示すように、溝の上部の形状が左右非対称になってしまうという問題が生じる。なお、ここで溝の上部の形状が左右非対称とは、溝を形成するレジストの高さが、溝の左右で異なることを言う。すなわち、ASIC基板の電極取出し用開口部432に近い側のレジスト433ともう一方のレジスト434のレジスト高さの差43Hが大きく、非対称な溝形状となる。このような溝形状では、焦点深度が変ってしまう、その後の金属膜のつきまわりが変ってしまうなど、微細コイルの形成が困難となる。
The third problem is that the grooves become asymmetrical when a process for forming an inverted trapezoid groove is examined using a positive resist resin film instead of a negative resist.
The ASIC substrate already has integrated circuit wiring and the layout of the electrode extraction openings and the like is already determined, so there is a limit to the location where linear grooves 431 for arranging the magnetic wires can be formed, as shown in Fig. 4(a). In other words, since the left and right structure of the groove is due to the wiring of the ASIC substrate, the electrode extraction portions 421 of the ASIC substrate near the location where the linear grooves for arranging the wires are formed become asymmetrical with respect to the groove.
As a result, when the groove 431 and the electrode extraction portion 432 of the ASIC substrate are simultaneously exposed to a mask in the positive resist resin coating 43 and developed, and then a curing heat treatment is performed to form an inverted trapezoidal groove, the shape of the upper part of the groove becomes asymmetrical as shown in FIG. 4B. The asymmetrical shape of the upper part of the groove means that the height of the resist forming the groove is different on the left and right sides of the groove. In other words, the difference 43H in resist height between the resist 433 on the side close to the electrode extraction opening 432 of the ASIC substrate and the resist 434 on the other side is large, resulting in an asymmetrical groove shape. With such a groove shape, the focal depth changes, the subsequent deposition of the metal film changes, and so on, making it difficult to form a fine coil.
一般的な方法として、レジストの凸部を平坦にするには、CMP(Chemical-Mechanical Polishing)を用いる方法があるが、磁性ワイヤを配置するための溝部の幅は20μm以下、深さは5~15μmであるため、溝の中に異物が残ってしまう懸念があり、適用は困難である。 A common method for flattening the protruding parts of the resist is to use CMP (Chemical-Mechanical Polishing), but because the grooves for placing the magnetic wires are 20 μm wide or less and 5 to 15 μm deep, there is a concern that foreign matter may remain in the grooves, making this method difficult to apply.
本発明は、これらの問題を解決して、磁界検出素子と特定用途向け集積回路(以下、ASICという。)との一体化プロセスにおいて、
1)まず、ASIC基板上の樹脂被膜上にワイヤを配置する逆台形状の溝とアライメントマークを溝と同時に形成することである。
2)次に、ASIC基板表面への凹凸に対応し、さらなる微細化に対応するためにコントラスト性に優れたアライメントマークを溝と同時に形成することである。
3)そして、ASIC基板の電極取り出し開口部に対応して溝形状の対称性を改善することである。
微細コイルピッチで形成された検出コイルを有するGSR素子をASIC基板上に一体化形成する製造方法を提供するものである。
The present invention solves these problems by integrating a magnetic field detection element with an application specific integrated circuit (hereinafter referred to as ASIC),
1) First, an inverted trapezoid groove for arranging wires and an alignment mark are simultaneously formed on a resin film on an ASIC substrate.
2) Next, alignment marks with excellent contrast are formed simultaneously with the grooves in order to accommodate the irregularities on the surface of the ASIC substrate and to accommodate further miniaturization.
3) And, the symmetry of the groove shape is improved in correspondence with the electrode extraction opening of the ASIC substrate.
The present invention provides a manufacturing method for integrally forming a GSR element having a detection coil formed with a fine coil pitch on an ASIC substrate.
第1の課題である、逆台形状の溝の形成方法に関し、本発明者らは、熱処理後に形状が変化するため、構造物として残すレジストとしてはあまり使われないポジレジスト系の感光性樹脂の特性に着目し、検討を進めた。
その結果、図5に示すように、(a)ポジレジスト系の樹脂被膜をASIC基板全体に塗布後、マスク材を通して露光、現像後に得られる直方体状の溝形状を、(b)キュア熱処理することで、逆台形状にできることを見出した。キュア熱処理をすると、熱処理時に発生する応力で、溝は直方体形状から逆台形状へと変化する。すなわち、逆台形状の溝を形成するにはポジレジスト系の樹脂被膜が必須となる。
Regarding the first problem, namely, a method for forming an inverted trapezoidal groove, the inventors focused on the properties of positive resist photosensitive resins, which are not often used as resists that are left as structures because their shape changes after heat treatment, and conducted further research.
As a result, we found that (a) a rectangular parallelepiped groove shape obtained after applying a positive resist resin coating to the entire ASIC board and then exposing and developing it through a mask material can be made into an inverted trapezoid shape by (b) performing a curing heat treatment, as shown in Figure 5. When the curing heat treatment is performed, the groove changes from a rectangular parallelepiped shape to an inverted trapezoid shape due to the stress generated during the heat treatment. In other words, a positive resist resin coating is essential to form an inverted trapezoid groove.
さらに、溝とアライメントマーク部を感光性樹脂の被膜上に同時に形成することにした。このキュア処理したポジレジスト系の感光性樹脂は、形状がやや変化するが、耐薬品性も良好であり、構造物として利用できることを確認した。 Furthermore, we decided to simultaneously form the groove and alignment mark on the photosensitive resin coating. Although the shape of this cured positive resist photosensitive resin changes slightly, it has good chemical resistance and we have confirmed that it can be used as a structure.
すなわち、ASIC基板全面にポジレジスト系の樹脂被膜を塗布し、マスク材を通して露光した後に現像することで、溝とアライメントマーク用凹部を同時に形成する。
この時、溝の形状は直方体形状である。
次に、キュア熱処理を行う。キュア熱処理をすると、熱処理時に発生する応力で、溝は直方体形状から逆台形状へと変化する。これがSiO2被膜やネガレジスト系の樹脂被膜に代えて、ポジレジスト系樹脂被膜を採用した効果である。
That is, a positive resist resin film is applied to the entire surface of the ASIC substrate, and then exposed to light through a mask material and developed, thereby simultaneously forming grooves and recesses for alignment marks.
At this time, the groove has a rectangular parallelepiped shape.
Next, a curing heat treatment is performed. When the curing heat treatment is performed, the groove changes from a rectangular parallelepiped shape to an inverted trapezoid shape due to the stress generated during the heat treatment. This is the effect of using a positive resist resin coating instead of a SiO2 coating or a negative resist resin coating.
以上より、この逆台形状の溝を形成することにより、ASICと一体となったGSR素子を形成することができる。
ただし、欠点は、アライメントマーク凹部の形状も逆台形状となってしまい、マークの視認性が低下する。この問題はアライメントマーク部以外をレジストで保護し前記逆台形状となったアライメントマーク部自体をマスクとして、RIE加工し、ASIC表面のSiO2を掘りこむことで、掘りこんだアライメントマークのエッジを急峻化させることで、解決できることを見いだした。
As described above, by forming the groove in an inverted trapezoid shape, it is possible to form a GSR element integrated with an ASIC.
However, the drawback is that the alignment mark recess also becomes inverted trapezoidal, reducing the visibility of the mark. We found that this problem can be solved by protecting the area other than the alignment mark with resist, and using the inverted trapezoid alignment mark itself as a mask to perform RIE processing and dig into the SiO2 on the ASIC surface, thereby making the edges of the digged alignment mark steeper.
次に、ネガレジスト系の樹脂被膜を塗布し、露光、現像して溝部のみに樹脂被膜を残してキュア熱処理によって溝の底部にR形状を形成する。
そして、逆台形状の溝とアライメントマーク凹部を形成したASIC基板全面に金属膜を成膜する。これにより、アライメントマーク用凹部が金属膜で覆われ、この膜が反射膜として機能するため、さらにアライメントマークの視認性を向上させることができることが分かった。そして、この金属膜は逆台形状の溝に沿って成膜されており、ここにレジスト塗布し、アライメントマークを使用して露光、現像することで、逆台形状の溝に沿って下部コイルのパターンを形成することができる。
そして、めっき後、レジスト除去し、コイル部及び電極部以外の金属膜をウェットすることで溝部には、厚さ0.2~1.0μmの下部コイルが形成される。溝部の底部にはR部が形成されており、線幅0.5~2μmの微細配線でも下部コイルは断線することなく形成できる。
Next, a negative resist type resin film is applied, exposed to light, and developed to leave the resin film only in the grooves, and a curing heat treatment is performed to form an R shape in the bottom of the groove.
Then, a metal film is formed on the entire surface of the ASIC substrate on which the inverted trapezoid groove and the alignment mark recess are formed. As a result, the alignment mark recess is covered with the metal film, and this film functions as a reflective film, which further improves the visibility of the alignment mark. This metal film is formed along the inverted trapezoid groove, and by applying a resist thereto and exposing and developing using the alignment mark, the pattern of the lower coil can be formed along the inverted trapezoid groove.
After plating, the resist is removed and the metal film other than the coil and electrode parts is wetted to form a lower coil with a thickness of 0.2 to 1.0 μm in the groove. An R part is formed at the bottom of the groove, and the lower coil can be formed without breaking even with fine wiring with a line width of 0.5 to 2 μm.
次に、第2の課題であるアライメントマークを溝と同時に形成する際のASIC基板表面の2~3μmの凹凸により、平坦な面にアライメントマークを形成することができないという問題については、1回の樹脂被膜を使った方法に代えて、機能の異なる樹脂被膜を2回に分けて形成する2層樹脂被膜法を考え、溝とアライメントマークを樹脂被膜上に同時に形成できることを見出した。 Next, to address the second issue, which was that alignment marks could not be formed on a flat surface due to 2-3 μm unevenness on the surface of the ASIC board when the alignment marks and grooves were formed at the same time, instead of the method using a single resin coating, we devised a two-layer resin coating method in which resin coatings with different functions are formed in two separate steps, and found that it was possible to form grooves and alignment marks simultaneously on the resin coating.
以下、本発明の2層樹脂被膜法について説明する。
はじめに、図6および図7により、1回の樹脂被膜を使った場合のASICの表面状態および2層樹脂法により下部コイル形成のための金属膜を成膜時のアライメントマークの表面状態について説明する。
図6の(a)より、ASIC基板60表面の凹凸状態を示している。次に(b)により、溝およびアライメントマークを形成する箇所にレジスト61を塗布し、キュア処理を施した表面状態は、ASIC基板表面の凹凸状態をそのまま転写していることを示している。この状態では、図3に示すように、アライメントマークは凹凸によるマークでもって妨害され、下部コイルと上部コイルとの位置合わせが困難になる。
The two-layer resin coating method of the present invention will now be described.
First, the surface state of an ASIC when a single resin coating is used and the surface state of an alignment mark when a metal film for forming a lower coil is formed by a two-layer resin method will be described with reference to FIGS.
6A shows the unevenness of the surface of the ASIC substrate 60. Next, FIG. 6B shows that the surface state after applying resist 61 to the areas where the grooves and alignment marks are to be formed and curing is performed has the unevenness of the ASIC substrate surface transferred as is. In this state, as shown in FIG. 3, the alignment mark is obstructed by the uneven mark, making it difficult to align the lower coil and the upper coil.
図7の2層樹脂被膜法は、第1層の樹脂71gに転写された凹凸を研磨により除去して平坦化し、その平坦面の上に第2層の樹脂72gを塗布・キュア処理により溝74Ggとアライメントマーク74Agを形成したものである。 The two-layer resin coating method in Figure 7 involves polishing to remove the irregularities transferred to the first layer of resin 71g, flattening it, and then applying a second layer of resin 72g onto the flat surface and curing it to form grooves 74Gg and alignment marks 74Ag.
第1ステップは、凹凸の存在するASIC基板上において第一樹脂被膜(ネガレジスト)を塗布して第1層を形成し、逆台形状の溝とアライメントマークを配置する下に平坦化した硬い樹脂製の第一台座を配置し、第一樹脂被膜に生じる凹凸を除去することである。それ以外のASIC表面である第一台座非配置部の凹凸は電極配線として使用するため、この凹凸は残した。 The first step is to form a first layer by applying a first resin film (negative resist) onto the ASIC substrate with irregularities, then place a flattened first base made of hard resin underneath where the inverted trapezoid groove and alignment mark will be placed, and remove the irregularities that occur in the first resin film. The irregularities on the other parts of the ASIC surface, where the first base is not placed, are left as they will be used as electrode wiring.
第2ステップは、第一台座の上に溝の深さより厚い第二樹脂被膜(ポジレジスト)を塗布して第2層を形成し第二台座とし、この第二台座に(第2層の第二樹脂被膜)に逆台形状の溝とアライメントマーク用凹部を同時に形成し、その上に金属膜を成膜することである。 The second step is to apply a second resin film (positive resist) thicker than the depth of the groove onto the first pedestal to form a second layer, which becomes the second pedestal, and then simultaneously form an inverted trapezoid groove and a recess for an alignment mark in this second pedestal (the second resin film of the second layer), and then deposit a metal film on top of that.
次に、各ステップについて
第1ステップにおける1層目の第一樹脂被膜は、台座上部が平坦で、かつそのエッジ部は急峻な台座形状を確保することが好ましいので、ポリイミド系のネガレジストが好ましい。ただし、ポジレジストの使用も可能である。
なお、第2ステップにおける2層目の第二樹脂被膜は平坦化された第一台座の上に塗布され、キュア熱処理後に逆台形状の溝を形成するためにポジレジストを使用することが必要である。
Next, in each step, the first resin coating layer in the first step is preferably a polyimide-based negative resist because it is preferable to ensure that the top of the base is flat and that the edges of the base have a steep shape. However, a positive resist can also be used.
In addition, the second resin coating film, which is the second layer in the second step, is applied onto the planarized first pedestal, and it is necessary to use a positive resist in order to form an inverted trapezoidal groove after a curing heat treatment.
1層目の第一台座のキュア熱処理した第一樹脂と2層目の第二樹脂被膜との密着性については、懸念課題であったが、樹脂の種類が異なっても強固に一体化することを確認して解決した。また、アライメントマーク部は、溝部と同時に形成するため、溝部と同様に逆台形状となる。そこで、この逆台形状の第二台座そのものをマスクとして、第一台座をRIEで掘りこむことで、アライメントマーク凹部の急峻度を高める。そして、さらに金属膜を反射膜とすることによりアライメントマークの視認性の向上が可能となる。このように2層構造の樹脂被膜を採用することで、1層構造では実現できない凹凸の除去が可能となる。 There was a concern about the adhesion between the heat-cured first resin of the first layer of the first pedestal and the second resin coating of the second layer, but this was resolved by confirming that they were firmly integrated even though the types of resins were different. In addition, the alignment mark portion is formed at the same time as the groove portion, so it has an inverted trapezoid shape like the groove portion. Therefore, by using the inverted trapezoid second pedestal itself as a mask and digging into the first pedestal by RIE, the steepness of the alignment mark recess is increased. Furthermore, by using a metal film as a reflective film, it is possible to improve the visibility of the alignment mark. In this way, by adopting a two-layer resin coating, it is possible to remove unevenness that cannot be achieved with a one-layer structure.
第1ステップでは、凹凸のあるASIC基板面上に第一樹脂被膜を塗布して、溝形成部とアライメントマーク形成部にそれぞれ第一台座を形成するが、凹凸が生じる。キュア熱処理後にも第一台座の表面上には凹凸が残存するので、硬化させた第一台座の上面をCMP(Chemical-Mechanical Polishing)の研磨方法で平坦化する必要がある。
このCMPによりASICの電極部の破損が生じてしまう場合がある。その場合には、CMP前にASIC全面にレジストを塗布し、台座部以外のASIC面を保護し、CMP後にレジスト剥離液で除去することにより平坦化することが好ましい。
In the first step, a first resin film is applied onto the uneven surface of the ASIC substrate to form first pedestals in the groove formation portion and the alignment mark formation portion, but unevenness occurs. Since unevenness remains on the surface of the first pedestal even after the curing heat treatment, it is necessary to flatten the upper surface of the hardened first pedestal by a polishing method such as CMP (Chemical-Mechanical Polishing).
This CMP may damage the electrodes of the ASIC, so it is preferable to apply a resist to the entire surface of the ASIC before CMP to protect the ASIC surface other than the pedestal, and then remove the resist with a resist remover after CMP to achieve flattening.
第二樹脂被膜を塗布し、溝とアライメントマーク凹部をマスク露光、現像して、キュア熱処理をすると、溝は直方形から逆台形状へ、アライメントマーク凹部も直方形から逆台形状へと変化する。これがSiO2被膜に代えて、ポジレジスト系の樹脂被膜を採用した効果である。すでに、第一台座を平坦化しているので、溝面とアライメントマーク部自体は凹凸の無いものとなる。 When the second resin coating is applied, the groove and alignment mark recess are exposed to light using a mask, developed, and then cured with heat, the groove changes from a rectangular shape to an inverted trapezoid, and the alignment mark recess also changes from a rectangular shape to an inverted trapezoid. This is the effect of using a positive resist resin coating instead of a SiO2 coating. Because the first base has already been flattened, the groove surface and alignment mark portion itself are smooth.
 ここで、アライメントマーク凹部の形状も逆台形状となってしまうので、アライメントマーク部のエッジを急峻化するため、さらにアライメントマーク部以外をレジストで保護し、アライメントマーク部はこの逆台形状の第二台座そのものをマスクにしてRIEを行い、第一台座を掘りこむ。この時、第二台座も樹脂被膜であることから、RIEのエッチングの選択比はほぼ同じである。したがって、その掘り込み量は0.5~1.5μmが好ましい。0.5μm以下では、急峻化の効果が小さく、視認性の向上が認められない。1.5μm以上では、第2台座の膜べりが大きくなり、視認性に影響がでる。 Here, the shape of the alignment mark recess also becomes an inverted trapezoid, so in order to make the edges of the alignment mark steeper, the area other than the alignment mark is protected with resist, and the alignment mark area is etched by RIE using the inverted trapezoid second pedestal itself as a mask to engrave the first pedestal. At this time, since the second pedestal is also a resin coating, the etching selectivity of the RIE is roughly the same. Therefore, the amount of engraving is preferably 0.5 to 1.5 μm. Below 0.5 μm, the effect of steepening is small and no improvement in visibility is observed. Above 1.5 μm, the film loss of the second pedestal is large, affecting visibility.
しかしながら、この状態では、ASIC基板上の凹凸が第一樹脂、第二樹脂を通して見えるため、アライメントに必要な視認性の高いコントラストが確保できない。
そこで、アライメントマーク上に反射機能を強化する金属膜を成膜することにより、アライメントマークの視認性を高めることができる。なお、第一台座を平坦化しない場合は、金属膜を成膜してもASIC基板の凹凸が解消できないため、アライメントマークの十分な視認性を確保することができない。つまり、台座の平坦化と反射機能を強める金属膜成膜が必須である。
In this state, however, the unevenness on the ASIC board is visible through the first resin and the second resin, making it impossible to ensure the high visibility contrast required for alignment.
Therefore, by forming a metal film on the alignment mark to enhance the reflection function, the visibility of the alignment mark can be improved. If the first pedestal is not flattened, the unevenness of the ASIC substrate cannot be eliminated even if a metal film is formed, and sufficient visibility of the alignment mark cannot be ensured. In other words, flattening the pedestal and forming a metal film to enhance the reflection function are essential.
他方、逆台形状の溝に下部コイルを形成するために、金属膜生成が必要であるので、反射機能を高めるアライメントマーク部の金属膜と下部コイルのそれとは同じ金属膜とすることが望ましい。また、金属膜を成膜する前に、前記溝部にネガレジスト系の樹脂被膜を塗布し、露光、現像して溝部のみに樹脂被膜を残してキュア熱処理によって溝の底部にR形状を形成することで、金属膜の断線を防止できる。 On the other hand, since a metal film needs to be formed to form the lower coil in the inverted trapezoidal groove, it is desirable to use the same metal film for the alignment mark portion, which enhances the reflective function, and for the lower coil. Also, before forming the metal film, a negative resist resin film is applied to the groove portion, exposed to light, and developed to leave the resin film only in the groove portion, and an R-shape is formed at the bottom of the groove by a curing heat treatment, thereby preventing breakage of the metal film.
2層樹脂被膜法によって、溝とアライメントマークを同時に形成し、かつ視認性の高いアライメントマークを樹脂被膜上に形成することが可能になる。
なお、第1層目の第一台座を形成する第一樹脂被膜の膜厚は、CMPを行うために、ASIC表面の凹凸(通常2μm~3μm程度)の3倍以上が好ましい。
第2層目の第二樹脂の膜厚は、溝形成(溝の深さ5μm~10μm程度)を可能にするため、最低溝の深さ以上の厚さを確保する必要がある。
The two-layer resin coating method makes it possible to simultaneously form grooves and alignment marks, and to form highly visible alignment marks on the resin coating.
The thickness of the first resin film forming the first pedestal of the first layer is preferably three times or more the irregularities (usually about 2 μm to 3 μm) of the ASIC surface in order to perform CMP.
The film thickness of the second resin in the second layer must be thicker than the minimum groove depth in order to enable groove formation (groove depth of about 5 μm to 10 μm).
第3の課題である、ポジレジスト系の樹脂被膜をASIC基板全体に塗布後、マスク材を通して露光、現像後に得られる直方体状の溝形状を、キュア熱処理後に形成された逆台形状の溝上部の形状が非対称となってしまい、コイルの形成が難しいという問題に関しては、前記ポジレジスト系の樹脂被膜に溝を形成する際、ASIC基板の電極の取出し部を同時に開口させるため、前記溝部の左右のポジレジスト系の樹脂被膜のボリューム差が生じ、キュア熱処理時の収縮の仕方がちがうためと考えた。
そこで、検討を進めた結果、溝、アライメントマーク、ASIC基板の電極取出し用開口部を同時に露光、現像した後、さらに溝部のみ部分露光を追加し、キュア熱処理をすることで、溝部の左右の収縮を制御できる図7に示す方法を見出した。この方法を図8の工程フロー図を使って説明する。
この後のコイル形成工程への影響を考慮し、溝の左右のレジストの高さの差は0.2μm以下とすることが好ましい。
Regarding the third issue, that is, after a positive resist resin film is applied to the entire ASIC board, the rectangular parallelepiped groove shape obtained after exposure and development through a mask material becomes asymmetrical at the top of the inverted trapezoid groove formed after curing heat treatment, making it difficult to form a coil, it was thought that this was because, when forming the groove in the positive resist resin film, the electrode extraction portions of the ASIC board are opened at the same time, resulting in a difference in volume of the positive resist resin film on the left and right sides of the groove, and the way they shrink during the curing heat treatment differs.
As a result of further investigation, we discovered the method shown in Figure 7, which can control the shrinkage on the left and right sides of the groove by simultaneously exposing and developing the groove, alignment mark, and electrode extraction opening of the ASIC substrate, and then adding partial exposure only to the groove and performing a curing heat treatment. This method will be explained using the process flow diagram in Figure 8.
Considering the effect on the subsequent coil formation process, it is preferable that the difference in height of the resist on the left and right sides of the groove is 0.2 μm or less.
図8(a)に示すように、ASIC基板81表面には保護膜62が形成されている。
ASIC基板81全面にポジレジスト系の樹脂被膜83を塗布し、マスク材を通して露光、現像することで、溝831とアライメントマーク用凹部(図示せず)とASIC基板の電極取出し用開口部832を樹脂被膜83に形成する
このままキュア熱処理をすると、図8(b)に示すように溝の形状は逆台形状となるが、溝上部は左右非対称となってしまう。
そこで、さらに溝部のみもう一度追加露光する。その後キュア熱処理を行うと、図8(b)に示すように溝831は逆台形状となり、かつ、追加露光を行っているので、溝上部の形状はASIC基板の開口部の位置によらず、左右対称となる。すなわち、ASIC基板の電極取出し用開口部832に近い側の溝レジスト833ともう一方の溝レジスト834のレジスト高さは溝の左右のレジストの高さの差は0.2μm以下となって、ほぼ同じである。
As shown in FIG. 8A, a protective film 62 is formed on the surface of an ASIC substrate 81 .
A positive resist resin film 83 is applied to the entire surface of the ASIC substrate 81, and then exposed and developed through a mask material, thereby forming a groove 831, a recess for an alignment mark (not shown), and an opening 832 for extracting electrodes from the ASIC substrate in the resin film 83. If a curing heat treatment is performed in this state, the shape of the groove will be an inverted trapezoid as shown in Figure 8(b), but the upper part of the groove will be asymmetric.
Therefore, only the groove portion is subjected to additional exposure once more. After that, when a curing heat treatment is performed, the groove 831 becomes an inverted trapezoid as shown in Fig. 8(b), and since additional exposure has been performed, the shape of the upper portion of the groove becomes symmetrical on both sides regardless of the position of the opening in the ASIC substrate. In other words, the resist height of the groove resist 833 on the side close to the electrode extraction opening 832 of the ASIC substrate and the resist height of the other groove resist 834 are almost the same, with the difference in resist height on the left and right sides of the groove being 0.2 µm or less.
1回目の露光量が1500mJ/cm、溝深さ8μm、溝とASIC基板上の電極取出し用の開口部の距離が50μmの場合の溝上部の非対称性(溝の左右のレジスト高さの差:以下、左右差と言う)の関係を図9に示す。
追加露光をしない場合、左右差は0.6μmであるが、追加露光をすることで、40mJ/cmで左右差が最小となり、それ以上の露光量では、反対側の溝の上部が高くなっていく。
微小ピッチコイル形成には、左右差は0.2μm以下が好ましく、この場合、追加露光量は20~60mJ/cmの範囲で左右差0.2μm以下となっている。すなわち、追加露光量は1回目の露光量の1~4%が好ましい。1%より低いとでは溝上部の左右差が0.2μm以上であり、4%を超えると最初の左右差が逆転し、0.2μm以上の左右差となり、溝の形状が変化してしまう。
Figure 9 shows the relationship between the asymmetry of the upper part of the groove (difference in resist height between the left and right sides of the groove: hereafter referred to as left-right difference) when the first exposure dose is 1500 mJ/ cm2 , the groove depth is 8 μm, and the distance between the groove and the opening for electrode extraction on the ASIC substrate is 50 μm.
Without additional exposure, the difference between the left and right sides was 0.6 μm. However, with additional exposure, the difference between the left and right sides was minimized at 40 mJ/cm 2 , and with an exposure amount higher than this, the top of the groove on the opposite side became higher.
To form a fine pitch coil, the left-right difference is preferably 0.2 μm or less, and in this case, the additional exposure amount is in the range of 20 to 60 mJ/ cm2 and the left-right difference is 0.2 μm or less. In other words, the additional exposure amount is preferably 1 to 4% of the first exposure amount. If it is lower than 1%, the left-right difference at the top of the groove is 0.2 μm or more, and if it exceeds 4%, the initial left-right difference is reversed, resulting in a left-right difference of 0.2 μm or more, and the shape of the groove will change.
 以上の課題を解決して作製した溝を用いて、コイル形成を行なう。
 底部がR形状となった溝に金属膜を成膜し、基板全面にレジスト塗布、露光、現像したパターンにめっき後、レジスト除去してコイルパターン以外の下地膜を除去することで下部コイルを形成する。
The groove produced by solving the above problems is used to form the coil.
A metal film is formed in a groove with an R-shaped bottom, and the entire surface of the substrate is coated with resist, exposed, and developed into a pattern. After plating, the resist is removed and the base film other than the coil pattern is removed to form the lower coil.
 下部コイルを形成した溝に磁性ワイヤを張力30~100kg/mm2を負荷して配置し、ワイヤ両端を接着剤、テープなどで仮固定する。さらに樹脂を塗布、露光、現像、キュア熱処理をすることで、磁性ワイヤを溝内部に固定する。この時、磁性ワイヤは両端を固定されたままであり、張力を保持したままキュア熱処理されることにより、GSR特性の向上を図ることができる。 The magnetic wire is placed in the groove that forms the lower coil with a tension of 30 to 100 kg/mm2, and both ends of the wire are temporarily fixed with adhesive, tape, etc. The magnetic wire is then fixed inside the groove by applying resin, exposing it to light, developing it, and curing it with heat. At this point, both ends of the magnetic wire remain fixed, and by performing the curing heat treatment while maintaining the tension, it is possible to improve the GSR characteristics.
溝内部に固定された磁性ワイヤが、絶縁性ガラスで被覆されている場合にはワイヤ端子(磁性ワイヤの両端部)を設けるために磁性ワイヤを被覆している絶縁性ガラスの一部を除去する。
一般的には、フッ酸処理が知られているが、ワイヤ端子周辺の損傷が大きく、素子形成に多大な影響を及ぼしてしまうため、検討した結果、CFガスを用いたRIE法でガラス除去できることを見出し、以降、RIE法でガラス除去を行なう。
If the magnetic wire fixed inside the groove is covered with insulating glass, part of the insulating glass covering the magnetic wire is removed to provide wire terminals (both ends of the magnetic wire).
Generally, hydrofluoric acid treatment is known, but it causes significant damage around the wire terminals and has a significant impact on element formation. As a result of investigation, it was found that glass can be removed by RIE using CF4 gas, and henceforth, glass removal will be performed by RIE.
逆台形状溝に磁性ワイヤを配置後、溝と磁性ワイヤとの段差解消のため、ASIC基板の全面にポジレジスト系樹脂被膜を塗布し、露光、現像して溝と磁性ワイヤ部のみにポジレジスト系の樹脂被膜を残し、キュア熱処理して溝と磁性ワイヤの段差を滑らかにする。
 一般的には、構造物として残すレジストとしてはネガタイプのレジストが知られているが、ネガタイプのレジストはエッジ形状が急峻となるため、次工程で上部コイル用の金属膜がうまくつきまわらず、断線の懸念がある。
そこで、キュア熱処理後に形状が変化することから構造物として残すレジストとしては一般的に使われないポジレジスト系樹脂被膜について検討した。その結果、ポジレジスト系樹脂被膜はキュア熱処理後にそのエッジ形状をなだらかに改善でき、断線の懸念なく段差を解消することができる。
After placing the magnetic wire in the inverted trapezoidal groove, in order to eliminate the step between the groove and the magnetic wire, a positive resist resin film is applied to the entire surface of the ASIC board, exposed to light, and developed so that the positive resist resin film remains only in the groove and the magnetic wire, and a curing heat treatment is performed to smooth out the step between the groove and the magnetic wire.
Generally, negative-type resists are known as resists that are left as structures, but because negative-type resists have sharp edges, the metal film for the upper coil does not adhere well in the next process, raising the risk of breakage.
Therefore, we investigated a positive resist resin coating, which is not generally used as a resist that is left as a structure because its shape changes after the curing heat treatment. As a result, the positive resist resin coating can improve the edge shape gently after the curing heat treatment, and can eliminate steps without the risk of disconnection.
そして、上部コイルを形成するために金属膜を成膜する。その後、レジスト塗布、露光、現像工程により、磁性ワイヤの上には上部コイル、基板上には電極パターン(ワイヤ端子、配線を含む。)を形成し、めっき、ウェット後にレジストを除去することで上部コイルが形成される。
下部コイルとの接続部はなだらかな形状をしており、断線もなく上部コイルを形成できることにより磁性ワイヤを周回する検出コイルが得られる。また、前記アライメントマークを用いることで合わせ精度が向上し微細なコイルピッチにおいても下部コイルとのずれなく上部コイルが形成できる。
このようにASIC基板上の樹脂被膜に逆台形状の溝とアライメントマークを同時に形成し、かつ逆台形状の溝上部の形状の対称性を大幅に改善することで、3μm以下の微細なコイルピッチの形成が可能となることを見出した。
Then, a metal film is formed to form the upper coil. After that, the upper coil is formed on the magnetic wire and the electrode pattern (including wire terminals and wiring) is formed on the substrate through resist coating, exposure, and development processes. After plating and wet plating, the resist is removed to form the upper coil.
The connection part with the lower coil has a gentle shape, and the upper coil can be formed without disconnection, resulting in a detection coil that goes around the magnetic wire. In addition, by using the alignment marks, the alignment precision is improved, and the upper coil can be formed without misalignment with the lower coil even with a fine coil pitch.
In this way, it was discovered that by simultaneously forming an inverted trapezoidal groove and an alignment mark in the resin coating on the ASIC substrate and significantly improving the symmetry of the shape of the upper part of the inverted trapezoidal groove, it is possible to form a fine coil pitch of 3 μm or less.
以上説明したように、本発明はポジレジスト被膜を活用した逆台形溝の形成法、精度の高いアライメントマークを樹脂被膜上に形成する2層樹脂被膜法および溝両側の高さの対称性を確保する追加露光法という3つの新技術を考案してASIC基板上に直接素子を形成する方法を発明したものである。 As explained above, the present invention devisees three new technologies to invent a method for forming elements directly on an ASIC substrate: a method for forming an inverted trapezoidal groove using a positive resist coating, a two-layer resin coating method for forming highly accurate alignment marks on a resin coating, and an additional exposure method for ensuring symmetry in the height of both sides of the groove.
 本発明により、ASIC基板にダメージを与えることなく、上部形状の対称性がある磁性ワイヤを配置するための逆台形状の溝と視認性の高いアライメントマークを感光性樹脂被膜上に同時に形成することができ、かつ、溝の対称性を改善できることから、ASIC基板上に5μm以下の微細なコイルピッチを有するGSR素子を一体化形成することが可能となる。 The present invention makes it possible to simultaneously form an inverted trapezoidal groove for arranging a magnetic wire with a symmetrical upper shape and a highly visible alignment mark on a photosensitive resin coating without damaging the ASIC substrate, and also improves the symmetry of the groove, making it possible to integrally form a GSR element with a fine coil pitch of 5 μm or less on the ASIC substrate.
ASIC基板上のSiO2絶縁膜にRIEで形成した溝を示す図である。1 is a diagram showing a groove formed by RIE in a SiO 2 insulating film on an ASIC substrate. ASIC基板表面の凹凸を示す図である。FIG. 2 is a diagram showing projections and recesses on the surface of an ASIC board; ASIC基板の金属膜の成膜前の表面のアライメントマーク    とA1-A2線におけるマークおよび凹凸のシグナルを示す図である。This figure shows the alignment marks on the surface of an ASIC substrate before the metal film is deposited, and the marks and unevenness signals on the A1-A2 line. ASIC基板の電極取出し用開口部とワイヤ配置用溝をポジレジスト系樹脂被膜に露光、現像した後の素子の平面図(a)、及びA-A‘断面図(b)である。1A is a plan view of an element after an electrode extraction opening and a wire placement groove of an ASIC substrate have been exposed to and developed using a positive resist resin coating, and FIG. 1B is an A-A' cross-sectional view of the element. ASIC基板のポジレジスト系樹脂被膜にワイヤ配置用溝を露光、現像した後の形状(a)、及び、キュア熱処理をして逆台形状になった溝(b)である。1A shows the shape of a wire placement groove formed in a positive resist resin coating on an ASIC board after exposure and development, and FIG. 1B shows the groove after a curing heat treatment to form an inverted trapezoid shape. ASIC基板表面の凹凸状態の断面図(a)および樹脂を塗布・キュア処理した後に凹凸状態が樹脂表面に転写されている状態の断面図(b)である。1A is a cross-sectional view of the uneven state of the ASIC substrate surface, and FIG. 1B is a cross-sectional view of the state in which the uneven state has been transferred to the resin surface after resin has been applied and cured. 2層樹脂法によりASIC基板上に形成された金属皮膜後の  溝およびアライメントマークの断面図である。This is a cross-sectional view of the grooves and alignment marks after a metal film is formed on an ASIC substrate by the two-layer resin method. ASIC基板のポジレジスト系樹脂被膜にワイヤ配置用溝とASIC基板の電極取出し用開口部を露光、現像した後の形状(a)、及び、露光、現像後にワイヤ配置用溝部のみ追加露光し、キュア熱処理をした溝とASIC基板の電極取出し用開口部を示す図である。FIG. 13 shows the shape (a) of a wire placement groove and an opening for electrode extraction of the ASIC substrate after exposure and development of a positive resist resin coating on the ASIC substrate, and a diagram showing the shape (b) of the wire placement groove and the opening for electrode extraction of the ASIC substrate after additional exposure and curing heat treatment of only the wire placement groove portion after exposure and development. ASIC基板の電極取出し用開口部とワイヤ配置用溝をポジレジスト系樹脂被膜に露光、現像後、溝部のみに追加露光する追加露光量と左右差の関係を示すグラフである。13 is a graph showing the relationship between the amount of additional exposure and the difference between the left and right sides when a positive resist resin film is exposed to light for forming electrode extraction openings and wire placement grooves on an ASIC board, and then developed, and the additional exposure is applied only to the grooves. ASIC基板上に底部にR形状を有する逆台形状溝に作製したGSR素子を示す断面図である。1 is a cross-sectional view showing a GSR element fabricated in an inverted trapezoidal groove having an R-shaped bottom on an ASIC substrate. ASIC基板上の溝形成部とアライメントマーク形成部の(a)平面図とA1-A2線の(b)断面図である。1A is a plan view of a groove formation portion and an alignment mark formation portion on an ASIC substrate, and FIG. 1B is a cross-sectional view taken along line A1-A2. ASIC基板上に2層樹脂被膜法により作製したGSR素子およびアライメントマークの断面図である。1 is a cross-sectional view of a GSR element and an alignment mark formed on an ASIC substrate by a two-layer resin coating method. ASIC基板上に2層樹脂被膜法により作製した逆台形状の溝とアライメントマークを示す(a)平面図とA1-A2線の(b)断面図である。1A is a plan view showing an inverted trapezoid groove and an alignment mark formed on an ASIC substrate by a two-layer resin coating method, and FIG. 1B is a cross-sectional view taken along line A1-A2. 本発明により作製したGSR素子を示す断面図である。1 is a cross-sectional view showing a GSR element produced according to the present invention. ASIC基板表面の回路配線起因の2~3μmの凹凸を示す図である。FIG. 1 is a diagram showing 2-3 μm irregularities caused by circuit wiring on the surface of an ASIC substrate. 溝部とアライメントマーク部に形成した第一台座をCMPで平坦化した図である。13 is a diagram showing a state in which a first pedestal formed in a groove portion and an alignment mark portion is planarized by CMP. 第2樹脂被膜に逆台形状溝部とアライメントマーク用凹部とASIC基板の電極取出し用開口部を同時に形成し、溝部のみに追加露光後にキュア熱処理をした図である。13 is a diagram showing an inverted trapezoidal groove, a recess for an alignment mark, and an opening for extracting electrodes of an ASIC substrate simultaneously formed in the second resin film, and a curing heat treatment is performed after additional exposure only to the groove. ASIC基板の金属膜成膜後のアライメントマークとC1-C2線におけるマーク及び、凹凸のシグナルを示す図である。1 is a diagram showing an alignment mark, a mark on the C1-C2 line, and a concave/convex signal after a metal film is formed on an ASIC substrate. 磁界検出素子(集合体)とアライメントマークの平面図を示す図である。FIG. 2 is a plan view of a magnetic field detection element (assembly) and an alignment mark. 磁界検出素子の平面図を示す図である。FIG. 2 is a plan view of a magnetic field detection element.
<第1発明>
 本発明のGSR素子の製造方法は、
 磁性ワイヤ、前記磁性ワイヤを周回する下部コイルと上部コイルよりなる10μm以下のコイルピッチを有する検出コイル、および電極配線からなるGSR素子を特定用途向け集積回路(以下、ASICという。)の基板上に直接製造するGSR素子の製造方法において、
(11)前記ASIC基板上にポジレジスト系の樹脂被膜を塗布し、露光、現像して前記樹脂被膜に前記磁性ワイヤを設置するための逆台形状の溝と複数のアライメントマーク用凹部を同時に形成し、キュア熱処理して硬化し、逆台形状の溝とアライメントマーク用凹部を形成した後に、ネガレジスト系の樹脂被膜を塗布し、露光、現像して前記逆台形の溝部のみに樹脂被膜を残してキュア熱処理によって溝の底部にR形状を形成する工程と、
(12)次に金属皮膜を成膜し、前記金属皮膜を前記アライメントマーク凹部の反射膜として使うことにより視認性の高いアライメントマークを形成する工程と、
(13)前記アライメントマークと前記逆台形状の溝に被覆した前記金属皮膜を使って、前記逆台形状の溝面に沿って前記下部コイルを形成する工程と
(14)前記下部コイルを形成した逆台形状の溝に張力を付加したまま前記磁性ワイヤを配置して樹脂で仮固定し、その後キュア熱処理して固定する工程と、
(15)基板全面にポジレジスト系樹脂被膜を塗布し、露光、現像して前記溝と磁性ワイヤ部のみにポジレジスト系樹脂被膜を残し、キュア熱処理して段差部を滑らかにする工程と、
(16)前記上部コイルと電極を形成する工程と、
(17)前記磁性ワイヤと前記検出コイルと前記電極からなる素子の集合体を個片化する工程と、
からなることを特徴とする。
<First Invention>
The method for producing a GSR element of the present invention comprises the steps of:
A method for manufacturing a GSR element, comprising: a magnetic wire; a detection coil having a coil pitch of 10 μm or less, which is made up of a lower coil and an upper coil surrounding the magnetic wire; and electrode wiring, the GSR element being directly manufactured on a substrate of an application specific integrated circuit (hereinafter referred to as ASIC),
(11) A process of applying a positive resist resin film onto the ASIC board, exposing and developing the film to simultaneously form an inverted trapezoid groove for installing the magnetic wire and a plurality of concave portions for alignment marks in the resin film, hardening the film by a curing heat treatment, and after forming the inverted trapezoid groove and the concave portions for alignment marks, applying a negative resist resin film, exposing and developing the film to leave the resin film only in the inverted trapezoid groove portion, and forming an R shape at the bottom of the groove by a curing heat treatment;
(12) forming a metal film and using the metal film as a reflective film for the alignment mark recesses to form a highly visible alignment mark;
(13) forming the lower coil along the surface of the inverted trapezoid groove using the metal coating covering the alignment mark and the inverted trapezoid groove; and (14) arranging the magnetic wire while applying tension to the inverted trapezoid groove in which the lower coil is formed, and temporarily fixing the magnetic wire with resin, and then fixing the magnetic wire by a curing heat treatment.
(15) a process of applying a positive resist resin coating to the entire surface of the substrate, exposing and developing the positive resist resin coating to leave the positive resist resin coating only on the grooves and magnetic wires, and smoothing the stepped portions by performing a curing heat treatment;
(16) forming the upper coil and electrodes;
(17) A step of singulating an assembly of elements each including the magnetic wire, the detection coil, and the electrodes;
The present invention is characterized in that it comprises:
 また、上記の工程14において、
(14A)前記下部コイルを形成した逆台形状の溝に張力を付加したまま前記磁性ワイヤを配置して樹脂で仮固定し、その後キュア熱処理して固定する工程と、
 前記ワイヤと電極配線を接合するためのワイヤ電極部にある前記ワイヤを被覆している絶縁性ガラスをCF-RIEにより除去する工程と、
からなることを特徴とする。
Also, in the above step 14,
(14A) a step of placing the magnetic wire in the inverted trapezoid groove in which the lower coil is formed while applying tension thereto, temporarily fixing the magnetic wire with resin, and then fixing the magnetic wire by a curing heat treatment;
a step of removing insulating glass covering the wire in a wire electrode portion for joining the wire to an electrode wiring by CF 4 -RIE;
The present invention is characterized in that it comprises:
これにより、逆台形状の下部コイル形成用の溝とアライメントマーク凹部を樹脂被膜に同時に形成し、かつ樹脂被膜上に視認性の高いアライメントマークを形成できることから、ASIC基板上に微細ピッチコイルを有したGSR素子を一体化形成することが可能となる。 This allows the groove for forming the inverted trapezoid lower coil and the alignment mark recess to be formed simultaneously in the resin coating, and also allows a highly visible alignment mark to be formed on the resin coating, making it possible to integrally form a GSR element with a fine pitch coil on an ASIC substrate.
 本発明により製造されるGSR素子の構造の断面図を図10に示す。
 本発明のGSR素子10は、ASIC基板101、ASIC基板101の上のSiO2保護被膜102、SiO2保護被膜102の上に被覆されたポジレジスト103、ポジレジスト103に形成された逆台形状の溝104、溝底部に配置され、底部のR形状を形成する樹脂被膜100,逆台形状の溝104の面およびポジレジスト103の上面の一部に形成された下部コイル105、下部コイルの上に配置された磁性ワイヤ106、磁性ワイヤを固定する樹脂被膜108,磁性ワイヤ106と溝104の段差を解消するためのポジレジスト系の樹脂被膜109,樹脂被膜109の上に形成され、下部コイル105と接続する上部コイル107とから構成されている。
なお、磁性ワイヤ106は下部コイル105と上部コイル107とからなる検出コイルによって周回されており、検出コイルと磁性ワイヤの間隙は絶縁性樹脂108,109により埋められている。
A cross-sectional view of the structure of a GSR element manufactured according to the present invention is shown in FIG.
The GSR element 10 of the present invention is composed of an ASIC substrate 101, a SiO2 protective coating 102 on the ASIC substrate 101, a positive resist 103 coated on the SiO2 protective coating 102, an inverted trapezoidal groove 104 formed in the positive resist 103, a resin coating 100 placed at the bottom of the groove and forming an R-shape at the bottom, a lower coil 105 formed on the surface of the inverted trapezoidal groove 104 and on part of the upper surface of the positive resist 103, a magnetic wire 106 placed on the lower coil, a resin coating 108 that fixes the magnetic wire, a positive resist-based resin coating 109 that eliminates the step between the magnetic wire 106 and the groove 104, and an upper coil 107 formed on the resin coating 109 and connected to the lower coil 105.
The magnetic wire 106 is wound around a detection coil consisting of a lower coil 105 and an upper coil 107, and the gap between the detection coil and the magnetic wire is filled with insulating resins 108 and 109.
以下、GSR素子の製造方法を詳細に説明する。
はじめに、図11により、本発明のプロセスの中間工程生成体であるGSR素子形成用基板110について説明する。(a)は平面図を示し、(b)は(a)のA1-A2線における断面図である。
なお、GSR素子の製造においては、1枚のASIC基板上に複数個のGSR素子を形成する。また、フォトリソグラフィ工程は複数回あるので、アライメントマークは複数個からなる。この図11は、1個のGSR素子のみを示して説明する。
A method for manufacturing a GSR element will now be described in detail.
First, a substrate 110 for forming a GSR element, which is an intermediate product of the process of the present invention, will be described with reference to Fig. 11. (a) shows a plan view, and (b) is a cross-sectional view taken along the line A1-A2 in (a).
In the manufacture of the GSR element, multiple GSR elements are formed on one ASIC substrate. Also, since the photolithography process is performed multiple times, multiple alignment marks are used. Fig. 11 shows only one GSR element for explanation.
ASIC基板111の上のGSR素子を形成するための逆台形状の溝114Gよりなる溝形成部11Gおよびアライメントマーク凹部114Aよりなるアライメントマーク部11AからなるGSR素子形成用基板110の中間工程生成体が形成されている。
溝形成部11Gは、ポジレジスト113Gと逆台形状の溝114Gよりなる。アライメントマーク部11Aは、複数個の+マークのアライメント11aにて、その断面がポジレジスト113Aとアライメントマーク凹部114Aよりなる。
An intermediate product of a GSR element forming substrate 110 is formed, which comprises a groove forming portion 11G consisting of an inverted trapezoid groove 114G for forming a GSR element on an ASIC substrate 111, and an alignment mark portion 11A consisting of an alignment mark recess 114A.
The groove forming portion 11G is made up of a positive resist 113G and an inverted trapezoidal groove 114G. The alignment mark portion 11A is made up of a plurality of alignment marks 11a, and its cross section is made up of a positive resist 113A and an alignment mark recess 114A.
ASIC基板上の樹脂被膜に溝とアライメントマークを同時に形成するプロセスフローを説明する。
工程(1a):
まず、ASIC基板上に溝とアライメントマークを形成するため、ポジレジスト系樹脂被膜を膜厚10μm塗布する。その後、溝と複数のアライメントマークのパターンが配置されたマスク材を用いて露光、現像を行って、図5(a)の中間工程生成体○○を形成する。また、マスクには、ASIC基板の電極部も開口するようなパターンも配置されている。
この時、溝の形状は直方体形状である。
The process flow for simultaneously forming grooves and alignment marks in a resin film on an ASIC substrate will be described.
Step (1a):
First, a positive resist resin film is applied to a thickness of 10 μm to form grooves and alignment marks on the ASIC substrate. After that, exposure and development are performed using a mask material on which grooves and multiple alignment mark patterns are arranged, forming the intermediate process product XX shown in Figure 5(a). The mask also has a pattern arranged to open the electrode parts of the ASIC substrate.
At this time, the groove has a rectangular parallelepiped shape.
工程(1b):
次に 280℃、1時間のキュア熱処理を行い、樹脂被膜を硬化させて図5(b)の中間工程生成体○○を形成する。キュア処理後、溝は、キュア処理時に発生する応力で、図5(b)に示すように直方体形状から逆台形状となる。
この時、溝深さは7μmである。
Step (1b):
Next, a curing heat treatment is performed at 280°C for 1 hour to harden the resin coating and form the intermediate product XX shown in Fig. 5(b). After the curing process, the groove changes from a rectangular parallelepiped shape to an inverted trapezoid shape as shown in Fig. 5(b) due to the stress generated during the curing process.
At this time, the groove depth is 7 μm.
工程(1c):
ここで、アライメントマークの形状を急峻化するために、樹脂を全面塗布した後、マスク露光・現像して、アライメント部以外をレジストで保護する。
Step (1c):
Here, in order to make the shape of the alignment mark steeper, a resin is applied to the entire surface, and then exposure and development are performed using a mask to protect areas other than the alignment area with resist.
工程(1d):
工程(1a)で形成したアライメント凹部自身をマスクしてO-RIEを行い、次いでレジストを剥離してアライメントマークの形状を急峻にする。
Step (1d):
The alignment recesses formed in step (1a) themselves are masked to perform O 2 -RIE, and then the resist is stripped off to make the shape of the alignment mark steeper.
工程(1e):
ネガレジスト系の樹脂被膜を塗布し、露光、現像して溝部のみに樹脂被膜を残してキュア熱処理によって溝の底部にR形状を形成した後、中間工程生成体3の全面に金属膜を0.2μm成膜する。
Step (1e):
A negative resist resin film is applied, exposed and developed to leave the resin film only in the grooves, and a curing heat treatment is performed to form an R shape at the bottom of the groove. Then, a metal film is formed to a thickness of 0.2 μm over the entire surface of the intermediate product 3 .
工程(1f):
金属膜を成膜したASIC基板の全体に樹脂を塗布し、溝部には下部コイルを形成するためのパターンを配置し、アライメントパターンを使って、露光現像を行う。この時、マスクにはアライメント部には保護するためのパターンが配置されている。
Step (1f):
Resin is applied to the entire ASIC board on which the metal film is formed, a pattern for forming the lower coil is placed in the groove, and exposure and development are performed using the alignment pattern. At this time, a protective pattern is placed on the alignment part of the mask.
工程(1g):
めっき、樹脂被膜除去、下部コイル部以外の金属膜のエッチング工程を経て、溝形成部の金属膜は下部コイル55を形成する。アライメントマーク部の金属膜は反射膜として機能する。
Step (1g):
After going through the steps of plating, removing the resin coating, and etching the metal film except for the lower coil portion, the metal film in the groove formation portion forms the lower coil 55. The metal film in the alignment mark portion functions as a reflective film.
工程(1h):
溝にガラスで被覆された直径10μmの磁性ワイヤを張力80kg/mmを負荷して配置し、ワイヤは張力を維持したまま接着剤やテープで治具に仮止めする。その後、ネガレジスト系樹脂を塗布し、90℃でワイヤを溝に仮固定し、露光、ベーク、現像後、280℃で1時間キュア熱処理をして、溝内に固定する。この時、磁性ワイヤは張力を維持したまま熱処理されており、GSR特性が改善できる。
Step (1h):
A glass-coated magnetic wire with a diameter of 10 μm is placed in the groove under a tension of 80 kg/ mm2 , and the wire is temporarily fixed to the jig with adhesive or tape while maintaining the tension. A negative resist resin is then applied, and the wire is temporarily fixed in the groove at 90°C. After exposure, baking, and development, the wire is cured at 280°C for 1 hour and fixed in the groove. At this time, the magnetic wire is heat-treated while maintaining the tension, which improves the GSR characteristics.
工程(1i):
複数の工程(略)を経て、磁性ワイヤを周回するコイルの上部側を形成するため、ASIC基板の全体に金属膜を0.2μm成膜する。
Step (1i):
Through multiple steps (omitted), a metal film is deposited to a thickness of 0.2 μm over the entire ASIC substrate to form the upper side of the coil that winds around the magnetic wire.
工程(1j):
さらに、ASIC基板の全体に樹脂を塗布し、溝部にコイルとワイヤ導通部の引出し線を形成するためのパターンを配置したマスクを用いて露光、現像を行い、上部コイルを作る。露光時に、アライメントマークを使うことで、下部コイルとの位置合わせは何の問題もなくできる。
Step (1j):
Furthermore, resin is applied to the entire ASIC board, and exposure and development are performed using a mask with a pattern for forming the coil and the wire conduction lead wire in the groove, to create the upper coil. By using alignment marks during exposure, alignment with the lower coil can be achieved without any problems.
工程(1k):
めっき、樹脂被膜除去、上部コイル部以外の金属膜のエッチング工程を経て、溝形成部の金属膜は上部コイルとして機能する。
Step (1k):
After going through the steps of plating, removing the resin coating, and etching the metal film except for the upper coil portion, the metal film in the groove formation portion functions as the upper coil.
<第2発明>
 本発明のGSR素子の製造方法は、
 磁性ワイヤと前記磁性ワイヤを周回する下部コイルと上部コイルとからなる5μm以下のコイルピッチを有する検出コイルと電極配線からなるGSR素子を特定用途向け集積回路(以下、ASICという。)の基板上に直接作製するGSR素子の製造方法において、
(21)前記ASIC基板上にネガレジスト系の第一樹脂被膜を塗布して、平坦で硬い樹脂製の溝形成部とアライメントマーク形成部に第一台座を形成する工程と、
(22)前記第一台座の上に溝深さよりも厚いポジレジスト系の第二樹脂被膜を塗布して第二台座とし、前記第二台座の前記溝形成部には前記磁性ワイヤを配置するための逆台形状の溝(以下、溝という。)を形成するための長方形の凹部と前記アライメントマーク形成部にはアライメントマーク用凹部を形成するための凹部を同時に形成し、キュア熱処理して硬化させるとともに逆台形状の前記溝と前記アライメントマーク用凹部を形成する工程と、
(23)前記溝部にネガレジスト系の樹脂被膜を塗布し、露光、現像して溝部のみに樹脂被膜を残してキュア熱処理によって溝の底部にR形状を形成し、前記溝よりなる前記溝形成部と、アライメントマーク凹部よりなるアライメントマーク形成部に金属膜を成膜する工程と、
(24)前記アライメントマーク形成部の前記金属膜の成膜された前記アライメントマーク凹部と、前記アライメントマーク形成部の平坦面に成膜された反射膜とからなる視認性の高いアライメントマークを用いて、前記金属膜の成膜された前記溝形成部の金属皮膜を前記溝の面に沿って前記下部コイルと、前記溝形成部の平坦面の上部コイル接続部(以下、下部コイルと上部コイル接続部とを下部コイルという。)を形成する工程と、
(25)前記溝の前記下部コイルの上に前記磁性ワイヤを張力付加して配置し、樹脂により前記溝内に仮固定し、さらに張力を付加したままキュア熱処理することで、前記磁性ワイヤを溝に固定する工程と、
(26)基板全面にポジレジスト系樹脂被膜を塗布し、露光、現像して前記溝と磁性ワイヤ部のみにポジレジスト系樹脂被膜を残し、キュア熱処理して段差部を滑らかにする工程と、
(27)前記樹脂の上部に、オートアライメント機構により前記アライメントマークを用いて前記上部コイルと前記電極を形成する工程と、
(28)前記磁性ワイヤと前記検出コイルと前記電極からなる素子の集合体からなる素子基板を個片化する工程と、
からなることを特徴とするGSR素子の製造方法。
<Second Invention>
The method for producing a GSR element of the present invention comprises the steps of:
A method for manufacturing a GSR element, which comprises a detection coil having a coil pitch of 5 μm or less, which is made up of a magnetic wire, a lower coil and an upper coil surrounding the magnetic wire, and electrode wiring, directly fabricating the GSR element on a substrate of an application specific integrated circuit (hereinafter referred to as ASIC), comprising:
(21) applying a negative resist-based first resin coating onto the ASIC substrate to form a first base in a groove forming portion and an alignment mark forming portion made of a flat and hard resin;
(22) A process of applying a positive resist-based second resin coating thicker than the groove depth onto the first pedestal to form a second pedestal, simultaneously forming a rectangular recess for forming an inverted trapezoid groove (hereinafter referred to as a groove) for arranging the magnetic wire in the groove forming portion of the second pedestal and a recess for forming an alignment mark recess in the alignment mark forming portion, and hardening the second pedestal by a curing heat treatment to form the inverted trapezoid groove and the alignment mark recess;
(23) applying a negative resist resin film to the grooves, exposing and developing the resin film to leave only the grooves, and forming an R-shape at the bottom of the grooves by a curing heat treatment; and forming a metal film on the groove forming portion formed by the grooves and on an alignment mark forming portion formed by an alignment mark recess;
(24) A process of forming the lower coil and the upper coil connection part (hereinafter, the lower coil and the upper coil connection part are referred to as the lower coil) on the flat surface of the groove forming part by using a highly visible alignment mark consisting of the alignment mark recess on which the metal film of the alignment mark forming part is formed and a reflective film on the flat surface of the alignment mark forming part, the metal coating of the groove forming part on which the metal film is formed being formed along the surface of the groove;
(25) A process of placing the magnetic wire on the lower coil in the groove under tension, temporarily fixing the magnetic wire in the groove with resin, and further fixing the magnetic wire in the groove by performing a curing heat treatment while still applying tension;
(26) a process of applying a positive resist resin coating to the entire surface of the substrate, exposing and developing the positive resist resin coating to leave the positive resist resin coating only on the grooves and magnetic wires, and then performing a curing heat treatment to smooth out the stepped portions;
(27) forming the upper coil and the electrodes on the resin using the alignment marks by an auto-alignment mechanism;
(28) A step of dividing an element substrate consisting of an assembly of elements each consisting of the magnetic wire, the detection coil, and the electrode, into individual pieces;
A method for manufacturing a GSR element comprising the steps of:
また、上記の工程25において、
(25A)前記溝の前記下部コイルの上に前記磁性ワイヤを張力付加して配置し、樹脂により前記溝内に仮固定し、さらに張力を付加したままキュア熱処理することで、前記磁性ワイヤを溝に固定する工程と、
前記ワイヤと電極配線を接合するためのワイヤ電極部にある前記ワイヤを被覆している絶縁性ガラスをCF-RIEにより除去する工程と、
からなることを特徴とする。
Also, in the above step 25,
(25A) placing the magnetic wire on the lower coil in the groove under tension, temporarily fixing the magnetic wire in the groove with resin, and further fixing the magnetic wire in the groove by performing a curing heat treatment while still applying tension;
a step of removing insulating glass covering the wire in a wire electrode portion for joining the wire to an electrode wiring by CF 4 -RIE;
The present invention is characterized in that it comprises:
 これにより、ASIC基板表面に凹凸状態が存在する場合においても、溝とアライメントマークを樹脂被膜で同時に形成し、かつ樹脂被膜上に視認性の高いアライメントマークを形成できるため、ASIC基板上に微細なピッチコイルからなるGSR素子を一体化形成することが可能となる。 As a result, even if the ASIC substrate surface is uneven, the grooves and alignment marks can be formed simultaneously in the resin coating, and highly visible alignment marks can be formed on the resin coating, making it possible to integrally form a GSR element consisting of a fine pitch coil on the ASIC substrate.
 本発明により製造されるGSR素子と製造に用いられるアライメントマークの断面図を図12に示す。
ASIC基板120は、その表面には集積回路配線に起因する2~3μm程度の凹凸1201が存在する。そのため、通常の溝形成部122に加えてアライメントマーク形成部123が必要となる。
FIG. 12 shows a cross-sectional view of a GSR element manufactured according to the present invention and an alignment mark used in the manufacture.
The ASIC substrate 120 has an unevenness 1201 of about 2 to 3 μm on its surface due to the integrated circuit wiring. Therefore, an alignment mark forming section 123 is required in addition to a normal groove forming section 122.
溝形成部(素子形成部)122は、ASIC20の上に第一台座1211が形成されている。その平坦な表面の上には素子を構成する第二台座1212に、逆台形状の溝1221が形成されている。溝1221面には下部コイル1222が形成され、その上部に絶縁性ガラス被覆付きの磁性ワイヤ1223が配置され、樹脂でもって磁性ワイヤを固定するとともに溝1221内に埋設されている。
樹脂を介して磁性ワイヤ1223の上に上部コイル1224が形成され、両端にて下部コイル1222と接続され、磁性ワイヤ1223を周回する構造である。
磁性ワイヤ1223の両端と周回コイルの両端にはそれぞれワイヤ電極が形成される。
In the groove forming section (element forming section) 122, a first seat 1211 is formed on the ASIC 20. On the flat surface of the first seat 1211, an inverted trapezoidal groove 1221 is formed in a second seat 1212 constituting an element. A lower coil 1222 is formed on the surface of the groove 1221, and a magnetic wire 1223 with an insulating glass coating is arranged on the upper part of the lower coil 1222. The magnetic wire is fixed with resin and embedded in the groove 1221.
An upper coil 1224 is formed on the magnetic wire 1223 via resin, and is connected to the lower coil 1222 at both ends and wound around the magnetic wire 1223 .
Wire electrodes are formed on both ends of the magnetic wire 1223 and both ends of the surrounding coil.
アライメントマーク形成部123は、ASIC120の上に第一台座1211が形成されている。その平坦な表面の上にはアライメントマークを構成する第二台座1212には、細長く急峻な擬逆台形状の溝1231であるアライメントマーク凹部が形成され、その凹部表面は金属膜が形成されている。併せて平坦な面も金属膜からなる反射膜が形成されている。 In the alignment mark forming section 123, a first base 1211 is formed on the ASIC 120. On the flat surface of the first base 1211, a second base 1212 constituting the alignment mark is formed, which has an alignment mark recess, which is a long, steep, pseudo-inverted trapezoid groove 1231, and a metal film is formed on the surface of the recess. In addition, a reflective film made of a metal film is formed on the flat surface.
このアライメントマークを用いることにより正確かつ精密な位置合わせが可能となり、オートアライメント機構により下部コイルの形成、上部コイルの形成において5μm以下のコイルピッチでコイルの形成が可能となる。
コイルピッチとは、例えば3μmのコイルピッチの場合、コイル幅を2.0μmとするとコイル間隔は1.0となる。精度は隣のコイルを考慮すると0.5μm以下が求められる。
Use of these alignment marks enables accurate and precise alignment, and an auto-alignment mechanism enables formation of the lower coil and the upper coil with a coil pitch of 5 μm or less.
For example, when the coil pitch is 3 μm, if the coil width is 2.0 μm, the coil spacing is 1.0. Taking into account adjacent coils, accuracy of 0.5 μm or less is required.
次に、図13を用いて、製造工程のある中間工程における溝形成部とアライメントマーク形成部の平面図と断面図により説明する。
(a)は平面図で、(b)は(a)平面図のA1-A2線の断面図である。
ASIC基板130の上に溝形成部132とアライメントマーク形成部133が形成されている。溝形成部132には、上面が平坦な第一台座1311の上に逆台形状の溝と平坦面からなる第二台座が形成されている。
Next, a groove forming portion and an alignment mark forming portion at a certain intermediate step in the manufacturing process will be described with reference to FIG. 13, which is a plan view and a cross-sectional view.
1A is a plan view, and FIG. 1B is a cross-sectional view taken along line A1-A2 of the plan view of FIG.
A groove forming portion 132 and an alignment mark forming portion 133 are formed on an ASIC substrate 130. In the groove forming portion 132, a second pedestal consisting of an inverted trapezoid groove and a flat surface is formed on a first pedestal 1311 having a flat upper surface.
アライメントマーク部には、上面が平坦な第一台座1311の上に細長い逆台形状の溝1331であるアライメントマーク凹部と平坦面からなる第二台座1312が形成されている。 The alignment mark section has an alignment mark recess, which is a long, inverted trapezoidal groove 1331, formed on a first base 1311 with a flat upper surface, and a second base 1312 consisting of a flat surface.
 2層樹脂被膜法によって、ASIC基板上の樹脂被膜に溝とアライメントマークを同時に形成し、かつ視認性の高いアライメントマークを用いて狭ピッチコイルからなるGSR素子の製造フローを図7に示し、以下に説明する。 The two-layer resin coating method is used to simultaneously form grooves and alignment marks in the resin coating on the ASIC board, and the manufacturing flow for the GSR element consisting of a narrow-pitch coil using highly visible alignment marks is shown in Figure 7 and explained below.
工程(2a):
ASIC基板70の表面には、集積回路起因の数μmの凹凸701が存在している。
工程(2b):
ASIC基板に第一樹脂被膜を塗布した後、マスク材を用いて露光、現像を行なって7を形成する。
すなわち、溝を形成する溝形成部7Gとアライメントマーク凹部を形成するアライメントマーク形成部7Aからなる第一台座を形成する。
これにより、第一台座となる部分のみに第一樹脂被膜71が配置される。このとき、第一台座の厚みは10μmである。
Step (2a):
On the surface of the ASIC board 70, there are irregularities 701 of several μm caused by the integrated circuit.
Step (2b):
After a first resin film is applied to the ASIC board, exposure and development are carried out using a mask material to form 7 .
That is, a first pedestal is formed, which is composed of a groove forming portion 7G for forming a groove and an alignment mark forming portion 7A for forming an alignment mark recess.
As a result, the first resin coating 71 is disposed only on the portion that will become the first pedestal. At this time, the thickness of the first pedestal is 10 μm.
工程(2c):
280℃、1時間のキュア熱処理を行なって第一樹脂被膜を硬化させる。この時点においても、第一台座となる第一樹脂被膜の表面にはASIC基板の凹凸が転写されて残っている。
工程(2d):
ASIC基板の全体にレジストを塗布した後、マスク材を用いて露光、現像を行なって第一台座上のレジストを除去する。
Step (2c):
The first resin film is hardened by a curing heat treatment at 280° C. for 1 hour. Even at this stage, the irregularities of the ASIC board remain transferred onto the surface of the first resin film, which becomes the first pedestal.
Step (2d):
After the resist is applied to the entire ASIC board, exposure and development are carried out using a mask material to remove the resist on the first pedestal.
工程(2e):
第一台座を平坦化するためにCMPを行ない、第一台座71を形成する。第一台座の厚みは、工程(1b)により10μmで、キュア熱処理後でも8μm程度はあることからCMPには問題はない。
工程(2f):
溝とアライメントマークを形成するために、第一台座71の上に厚み10μmの第二樹脂被膜を塗布する。第一台座71は平坦化しているので、溝を形成する溝形成部とアライメントマークを形成するアライメントマーク形成部からなる第二台座72はASIC基板の凹凸の影響は受けない。
Step (2e):
CMP is performed to flatten the first pedestal, forming first pedestal 71. The thickness of the first pedestal is 10 μm in step (1b), and even after the curing heat treatment, it is still about 8 μm, so there is no problem with CMP.
Step (2f):
To form the grooves and alignment marks, a second resin coating having a thickness of 10 μm is applied onto the first pedestal 71. Since the first pedestal 71 is flattened, the second pedestal 72 consisting of a groove forming portion for forming the grooves and an alignment mark forming portion for forming the alignment marks is not affected by the unevenness of the ASIC substrate.
工程(2g):
280℃、1時間のキュア熱処理を行なって第二樹脂被膜72を硬化させる。熱処理によって溝はキュア熱処理時に発生する応力で直方体形状から逆台形状へ変形する。第二台座72の上面は平坦を維持する。溝の深さは8μmである。
Step (2g):
A curing heat treatment is performed at 280° C. for 1 hour to harden the second resin coating 72. The groove is deformed from a rectangular parallelepiped shape to an inverted trapezoid shape by the stress generated during the curing heat treatment. The upper surface of the second pedestal 72 remains flat. The groove has a depth of 8 μm.
工程(2h):
アライメントマーク凹部の形状を急峻化するために樹脂を全面に塗布した後、マスク露光・現像してアライメントマーク形成部以外をレジストで保護する。
 アライメントマーク形成部の第二台座72をマスクにしてORIEを行ない、第一台座1Aにアライメントマーク凹部を掘り込み、レジストを剥離する。この時、アライメントマークは18個形成した。
 また、溝形成部にはネガレジスト計の樹脂被膜を塗布・露光・現像して溝部のみに樹脂被膜を残してキュア熱処理によって溝の底部にR形状を形成した。さらにASIC基板の全面に金属膜を成膜した。金属蒸着により厚み0.2μmである。
Step (2h):
In order to make the shape of the alignment mark recesses steeper, a resin is applied to the entire surface, and then exposure and development are performed using a mask to protect areas other than the areas where the alignment marks are to be formed with resist.
Using the second pedestal 72 of the alignment mark formation portion as a mask, O 2 RIE is performed to carve alignment mark recesses into the first pedestal 1A, and the resist is then peeled off. At this time, 18 alignment marks are formed.
In addition, a resin film of negative resist was applied to the groove formation area, exposed to light, and developed, leaving the resin film only in the groove area, and a curing heat treatment was performed to form an R shape at the bottom of the groove. Furthermore, a metal film was formed on the entire surface of the ASIC substrate. It was deposited to a thickness of 0.2 μm by metal deposition.
工程(2i):
ASIC基板全体にレジストを塗布し、溝部に下部コイルを形成するためのパターン、アライメントマークには保護するためのパターンを配置したマスク材を用いて露光、現像を行なった。
工程(2j):
コイル部にめっき後、レジスト膜を除去し、コイル部以外の金属膜をエッチングで除去する。これにより、溝部の金属膜は下部コイルとして、アライメントマークの金属膜は反射膜としてそれぞれ機能する。下部コイルの幅は2.0μm、厚みは1.0μmである。
Step (2i):
A resist was applied to the entire ASIC substrate, and exposure and development were performed using a mask material in which a pattern for forming a lower coil in the groove and a pattern for protecting the alignment marks were arranged.
Step (2j):
After plating the coil portion, the resist film is removed, and the metal film other than the coil portion is removed by etching. As a result, the metal film in the groove functions as the lower coil, and the metal film of the alignment mark functions as a reflective film. The width of the lower coil is 2.0 μm, and the thickness is 1.0 μm.
工程(2k):
溝の下部コイルの上部に、厚さ1μmの絶縁性ガラスで被覆されているCoFeB系の磁性ワイヤに50kg/mmの張力を負荷して配置し、接着剤、テープなどで仮止めした後、磁性ワイヤを樹脂により溝内に埋設する。さらに、この樹脂を280℃の温度にてキュア熱処理により硬化させ、磁性ワイヤを固定する。この時、磁性ワイヤには張力が付加されたまま熱処理されるため、GSR特性を改善できる。
工程(2l):
磁性ワイヤ用電極との配線と接続するために磁性ワイヤの両端部の絶縁性ガラスをCF-RIEで除去して導通部を形成する。
Step (2k):
A CoFeB magnetic wire covered with 1 μm thick insulating glass is placed on the top of the lower coil in the groove with a tension of 50 kg/ mm2 , and after being temporarily fixed with adhesive, tape, etc., the magnetic wire is embedded in the groove with resin. Furthermore, this resin is hardened by a curing heat treatment at a temperature of 280°C to fix the magnetic wire. At this time, the magnetic wire is heat-treated while tension is applied, which improves the GSR characteristics.
Step (2l):
To connect to the wiring of the magnetic wire electrodes, the insulating glass on both ends of the magnetic wire is removed by CF 4 -RIE to form conductive parts.
工程(2m):の
溝とワイヤの段差を解消するため、ポジレジスト系樹脂被膜を塗布、露光、ベーク、現像、280℃、1時間のキュア熱処理をして溝上部の形状をなだらかにした後、ASIC基板の全体に金属膜を成膜し、レジストを塗布する。
工程(2n):
溝部の上部コイルと磁性ワイヤの導通部の引き出し線(配線)を形成するためのパターンとアライメント部保護するためのパターンを配置したマスク材を用いて露光、現像を行なう。
 なお、この時、アライメントマークは第一台座1Aおよび反射膜を有することによりシグナル強度も十分にあり、何の問題もなくオートアライメントにより、下部コイルの接続部と上部コイルの接続部との合わせを行なうことができる。
In step (2m): to eliminate the step between the groove and the wire, a positive resist resin film is applied, exposed, baked, developed, and cured at 280°C for 1 hour to smooth out the shape of the upper part of the groove. After that, a metal film is formed over the entire ASIC board, and a resist is applied.
Step (2n):
Exposure and development are carried out using a mask material on which a pattern for forming the upper coil in the groove and the lead wire (wiring) of the conductive portion of the magnetic wire and a pattern for protecting the alignment portion are arranged.
At this time, since the alignment mark has first base 1A and a reflective film, the signal strength is sufficient, and the connection part of the lower coil and the connection part of the upper coil can be aligned by automatic alignment without any problem.
工程(2o):
コイル部にめっき後、レジスト膜を除去し、コイル部以外の金属膜をエッチングで除去する。ここで上部コイル、電極および磁性ワイヤの導通部の引き出し線(配線)が形成されてそれぞれ機能する。
 上部コイルの幅は2.0μm、厚みは1.0μmである。そして、下部コイルの接続部と上部コイルの接続部からなるコイル接続部は線幅2.0μm、コイルピッチは3.0μmで形成されている。
Step (2o):
After plating the coil portion, the resist film is removed and the metal film other than the coil portion is removed by etching. At this point, the upper coil, electrodes, and lead wires (wiring) of the conductive parts of the magnetic wire are formed and function.
The upper coil has a width of 2.0 μm and a thickness of 1.0 μm. The coil connection portion consisting of the connection portion of the lower coil and the connection portion of the upper coil is formed with a line width of 2.0 μm and a coil pitch of 3.0 μm.
<第3発明>
 本発明のGSR素子の製造方法は、
 磁性ワイヤ、前記磁性ワイヤを周回する下部コイルと上部コイルよりなる10μm以下のコイルピッチを有する検出コイル、および電極配線からなるGSR素子を特定用途向け集積回路(以下、ASICという。)の基板上に直接製造するGSR素子の製造方法において、
(31)前記ASIC基板上にポジレジスト系の樹脂被膜(以下、P系樹脂被膜という。)を塗布し、露光、現像して前記P系樹脂被膜に前記磁性ワイヤを配置するための溝と前記ASIC基板上の電極取出し用開口部(以下、開口部という。)を同時に形成する工程と、
前記磁性ワイヤを配置するための溝部のみを追加露光した後、キュア熱処理して前記P系樹脂被膜を硬化し、溝上部の対称性を改善した逆台形状溝とASIC基板上の前記開口部を形成する工程と、
(32)前記ASIC基板の全面に金属皮膜を成膜し、前記逆台形状の溝に被覆した前記金属皮膜を使って、前記逆台形状溝の溝面に沿って前記下部コイルを形成する工程と、
(33)前記下部コイルを形成した前記逆台形状溝に張力付加した前記磁性ワイヤを配置して樹脂で仮固定し、次いでキュア熱処理して固定する工程と、
(34)前記磁性ワイヤと前記電極配線を接合する部分のみ、前記磁性ワイヤを被覆している絶縁性ガラスをCF-RIEにより除去する工程と、
(35)前記ASIC基板の全面に金属皮膜を成膜し、前記上部コイルと前記電極配線を形成する工程と、
(36)前記磁性ワイヤと前記検出コイルと前記電極配線からなる素子の集合体からなる素子基板を個片化する工程と、
からなることを特徴とする。
<Third Invention>
The method for producing a GSR element of the present invention comprises the steps of:
A method for manufacturing a GSR element, comprising: a magnetic wire; a detection coil having a coil pitch of 10 μm or less, which is made up of a lower coil and an upper coil surrounding the magnetic wire; and electrode wiring, the GSR element being directly manufactured on a substrate of an application specific integrated circuit (hereinafter referred to as ASIC),
(31) a step of applying a positive resist type resin film (hereinafter referred to as a P-type resin film) onto the ASIC substrate, exposing and developing the film to simultaneously form grooves for disposing the magnetic wires in the P-type resin film and openings for electrode extraction (hereinafter referred to as openings) on the ASIC substrate;
a step of exposing only the groove portion for arranging the magnetic wire to light, and then curing the P-based resin film by a curing heat treatment to harden the P-based resin film, thereby forming an inverted trapezoid groove having improved symmetry at the top of the groove and the opening portion on the ASIC substrate;
(32) forming a metal film on the entire surface of the ASIC substrate, and forming the lower coil along a groove surface of the inverted trapezoidal groove using the metal film covering the inverted trapezoidal groove;
(33) A step of placing the tensioned magnetic wire in the inverted trapezoid groove in which the lower coil is formed, temporarily fixing the magnetic wire with resin, and then fixing the magnetic wire by a curing heat treatment;
(34) removing the insulating glass covering the magnetic wire only from the portion where the magnetic wire and the electrode wiring are joined by CF 4 -RIE;
(35) forming a metal film on the entire surface of the ASIC substrate to form the upper coil and the electrode wiring;
(36) A step of dividing an element substrate consisting of an assembly of elements each consisting of the magnetic wire, the detection coil, and the electrode wiring;
The present invention is characterized in that it comprises:
また、上記の工程31において、
(31A)前記ASIC基板上にポジレジスト系の樹脂被膜(以下、P系樹脂被膜という。)を塗布し、露光、現像して前記P系樹脂被膜に前記磁性ワイヤを設置するための溝と前記ASIC基板上の電極取出し用開口部(以下、開口部という。)とアライメントマークとを同時に形成する工程と、
さらに、前記磁性ワイヤを設置するための溝部のみに追加露光をした後、キュア熱処理して前記P系樹脂被膜を硬化し、溝上部の対称性を改善した逆台形状溝を形成する工程と、
からなることを特徴とする。
Also, in the above step 31,
(31A) a step of coating a positive resist type resin film (hereinafter referred to as a P-type resin film) on the ASIC substrate, exposing and developing the film to simultaneously form grooves for placing the magnetic wires in the P-type resin film, openings for electrode extraction (hereinafter referred to as openings) on the ASIC substrate, and alignment marks;
and a step of performing additional exposure only on the groove portion for locating the magnetic wire, and then performing a curing heat treatment to harden the P-based resin coating, thereby forming an inverted trapezoidal groove with improved symmetry at the top of the groove.
The present invention is characterized in that it comprises:
また、上記の工程31において、
(31B)前記ASIC基板上にネガレジスト系の第一樹脂被膜(以下、N系第一樹脂被膜という。)を塗布、露光、現像して、キュア熱処理後に平坦化処理をして、平坦で硬い樹脂製の第一台座を溝形成部とアライメントマーク形成部に形成した後、
前記ASIC基板に溝深さよりも厚いポジレジスト系の第二樹脂被膜(以下、P系第二樹脂被膜という。)を塗布して第二台座とし、前記第二台座に前記溝と前記ASIC基板の電極取出し用開口部(以下、開口部という。)と前記アライメントマークを露光、現像して形成する工程と、
さらに溝部のみに追加露光した後に第二台座をキュア熱処理して溝上部の対称性を改善した逆台形状溝を形成する工程と、
からなることを特徴とする。
Also, in the above step 31,
(31B) A negative resist-based first resin film (hereinafter referred to as an N-based first resin film) is applied onto the ASIC substrate, exposed to light, and developed. After a curing heat treatment, a planarization treatment is performed to form a flat and hard resin first base in a groove formation portion and an alignment mark formation portion.
a step of applying a positive resist-based second resin coating (hereinafter referred to as a P-based second resin coating) having a thickness greater than the depth of the groove on the ASIC substrate to form a second pedestal, and exposing and developing the groove, an opening for electrode extraction of the ASIC substrate (hereinafter referred to as an opening), and the alignment mark on the second pedestal;
a step of forming an inverted trapezoidal groove with improved symmetry at the top of the groove by subjecting the second pedestal to additional exposure only in the groove portion and then subjecting the second pedestal to a curing heat treatment;
The present invention is characterized in that it comprises:
また、上記の工程31において、
(31C)前記ASIC基板上にポジレジスト系の樹脂被膜(以下、P系樹脂被膜という。)を塗布し、露光、現像して前記P系樹脂被膜に前記磁性ワイヤを配置するための溝と前記ASIC基板上の電極取出し用開口部(以下、開口部という。)を同時にする工程と、
前記磁性ワイヤを配置するための溝部のみに追加露光した後、キュア熱処理して前記P系樹脂被膜を硬化し、溝上部の対称性を改善した逆台形状溝とASIC基板上の前記開口部を形成する工程と、
さらに、前記ASIC基板にネガレジスト系の樹脂被膜(以下、N系樹脂被膜という。)を塗布し、露光、現像して前記逆台形状溝の溝部のみにN系樹脂被膜を残し、キュア熱処理によって溝の底部にR形状を形成する工程と、
からなることを特徴とするGSR素子の製造方法。
Also, in the above step 31,
(31C) applying a positive resist type resin film (hereinafter referred to as a P-type resin film) on the ASIC substrate, exposing and developing the film to simultaneously form grooves for arranging the magnetic wires in the P-type resin film and openings for electrode extraction (hereinafter referred to as openings) on the ASIC substrate;
a step of exposing only the groove portion for arranging the magnetic wire to additional light, and then curing the P-based resin film by a curing heat treatment to harden the P-based resin film, thereby forming an inverted trapezoid groove with improved symmetry at the top of the groove and the opening portion on the ASIC substrate;
Further, a process of applying a negative resist type resin film (hereinafter referred to as an N-type resin film) to the ASIC substrate, exposing and developing the N-type resin film so that the N-type resin film remains only in the groove portion of the inverted trapezoidal groove, and forming an R-shape at the bottom of the groove by a curing heat treatment;
A method for manufacturing a GSR element comprising the steps of:
また、上記の工程31Aにおいて、
(31D)前記ASIC基板上にポジレジスト系の樹脂被膜(以下、P系樹脂被膜という。)を塗布し、露光、現像して前記P系樹脂被膜に前記磁性ワイヤを設置するための溝と前記ASIC基板上の電極取出し用開口部(以下、開口部という。)とアライメントマークとを同時に形成する工程と、
前記磁性ワイヤを設置するための溝部のみに追加露光した後、キュア熱処理して前記P系樹脂被膜を硬化し、溝上部の対称性を改善した逆台形状溝を形成する工程と、
さらに、前記ASIC基板にネガレジスト系の樹脂被膜(以下、N系樹脂被膜という。)を塗布し、露光、現像して前記逆台形状溝の溝部のみにN系樹脂被膜を残し、キュア熱処理によって溝の底部にR形状を形成する工程と、
からなることを特徴とする。
Also, in the above step 31A,
(31D) applying a positive resist type resin film (hereinafter referred to as a P-type resin film) on the ASIC substrate, exposing and developing the film to simultaneously form grooves for placing the magnetic wires in the P-type resin film, openings for electrode extraction (hereinafter referred to as openings) on the ASIC substrate, and alignment marks;
a step of exposing only the groove portion for locating the magnetic wire to additional light, and then curing the P-based resin film by a curing heat treatment to harden the P-based resin film, thereby forming an inverted trapezoidal groove with improved symmetry at the top of the groove;
Further, a process of applying a negative resist type resin film (hereinafter referred to as an N-type resin film) to the ASIC substrate, exposing and developing the N-type resin film so that the N-type resin film remains only in the groove portion of the inverted trapezoidal groove, and forming an R-shape at the bottom of the groove by a curing heat treatment;
The present invention is characterized in that it comprises:
また、上記の工程35において、
(35A)前記逆台形状溝に前記磁性ワイヤを配置後、前記ASIC基板の全面にポジレジスト系樹脂被膜を塗布し、露光、現像して前記溝と磁性ワイヤ部のみにポジレジスト系の樹脂被膜(以下、P系樹脂被膜という。)を残し、キュア熱処理して溝と磁性ワイヤの段差を滑らかにする工程と、
前記ASIC基板の全面に金属皮膜を成膜し、前記上部コイルと前記電極配線を形成する工程と、
からなることを特徴とするGSR素子の製造方法。
Also, in the above step 35,
(35A) after arranging the magnetic wire in the inverted trapezoidal groove, a positive resist resin film is applied to the entire surface of the ASIC substrate, exposed to light, and developed to leave a positive resist resin film (hereinafter referred to as a P-type resin film) only on the groove and the magnetic wire, and a curing heat treatment is performed to smooth out the step between the groove and the magnetic wire;
forming a metal film on the entire surface of the ASIC substrate to form the upper coil and the electrode wiring;
A method for manufacturing a GSR element comprising the steps of:
また、請求項5~請求項10のいずれか一項において、
前記磁性ワイヤを配置するための前記溝部のみを追加露光する際の露光量は、前記溝部の前記露光量の4%以下であることを特徴とする。
In addition, in any one of claims 5 to 10,
The amount of exposure when additionally exposing only the groove portion for arranging the magnetic wire is 4% or less of the amount of exposure of the groove portion.
 また、請求項8または請求項9において、
 前記N系第一樹脂被膜の膜厚は、前記ASIC基板上の凹凸の3倍以上であることを特徴とする。
In addition, in claim 8 or claim 9,
The thickness of the N-based first resin coating is at least three times the irregularities on the ASIC substrate.
これにより、ASIC基板表面の凹凸やASICの回路配線(電極取り出し開口部)の存在下において、ASIC基板にダメージを与えることなく、上部形状の対称性がある磁性ワイヤを配置するための逆台形状の溝と視認性の高いアライメントマークを感光性樹脂被膜上に同時に形成することができ、かつ、溝の対称性を改善できることから、ASIC基板上に10μm以下の微細なコイルピッチを有するGSR素子を一体化形成することが可能となる。 As a result, it is possible to simultaneously form an inverted trapezoidal groove for arranging a magnetic wire with a symmetrical upper shape and a highly visible alignment mark on the photosensitive resin coating without damaging the ASIC substrate, even in the presence of unevenness on the ASIC substrate surface or ASIC circuit wiring (electrode extraction openings), and since the symmetry of the groove can be improved, it is possible to integrally form a GSR element with a fine coil pitch of 10 μm or less on the ASIC substrate.
 本発明により製造される磁界検出素子の断面構造を図14に示す。
図14は、図13に示すA1-A2線の断面図である。また、図13に示したアライメントマーク部133の断面図も合わせて示してある。
ASIC基板141上には集積回路起因の凹凸1411があり、電極取出し用開口部1431部以外の表面には保護膜143が形成されている。溝形成部には第一台座1491が配置されており、ASIC基板の凹凸1411に影響を受けることなく、第二の樹脂膜1492には逆台形状の溝142が形成され、溝底部にR形状からなるネガレジスト系樹脂被膜1423が形成されている。
FIG. 14 shows a cross-sectional structure of a magnetic field detection element manufactured according to the present invention.
Fig. 14 is a cross-sectional view taken along the line A1-A2 shown in Fig. 13. Also shown is a cross-sectional view of the alignment mark portion 133 shown in Fig. 13.
On the ASIC substrate 141, there are irregularities 1411 caused by the integrated circuit, and a protective film 143 is formed on the surface other than the electrode extraction opening 1431. A first seat 1491 is disposed in the groove formation portion, and an inverted trapezoidal groove 142 is formed in the second resin film 1492 without being affected by the irregularities 1411 of the ASIC substrate, and an R-shaped negative resist resin coating 1423 is formed on the bottom of the groove.
そのネガレジスト系樹脂被膜1423の上に、下部コイル144を形成した後、磁性ワイヤ145が配置され、ネガレジスト系樹脂被膜1451により固定されている。
磁性ワイヤ145は、厚さ1.0μmの絶縁性ガラスにより被覆され、その直径は12μmである。
After the lower coil 144 is formed on the negative resist resin film 1423 , the magnetic wire 145 is disposed and fixed by the negative resist resin film 1451 .
The magnetic wire 145 is covered with insulating glass having a thickness of 1.0 μm and has a diameter of 12 μm.
溝142と磁性ワイヤ145との段差を解消するために、溝142と磁性ワイヤ145との間にポジレジスト系樹脂被膜1452が形成されている。
 このポジレジスト系樹脂被膜1452は、磁性ワイヤ145の上にも行き渡っており、その上に上部コイル146が形成されている。
下部コイル144と上部コイル146とは、ポジレジスト系樹脂被膜1452があり、溝上部の対称性も向上しているため、問題なく接続されている。
In order to eliminate the step between the groove 142 and the magnetic wire 145 , a positive resist resin coating 1452 is formed between the groove 142 and the magnetic wire 145 .
This positive resist resin coating 1452 also extends over the magnetic wire 145, and the upper coil 146 is formed thereon.
The lower coil 144 and the upper coil 146 are connected without any problem because of the positive resist resin coating 1452 and the improved symmetry of the upper part of the groove.
一方、アライメントマーク部149においても、ASIC基板141上には集積回路起因の凹凸1411があるが、アライメントマーク部には第一台座1491が配置されており、ASIC基板の凹凸1411に影響を受けることなく、第二の樹脂膜1492にアライメントマーク凹部1494が形成されている。アライメントマーク凹部は第一台座まで掘りこまれ、さらに反射膜1493が形成されており、視認性が向上している。 On the other hand, in the alignment mark portion 149, there are irregularities 1411 on the ASIC substrate 141 caused by the integrated circuit, but the first base 1491 is arranged in the alignment mark portion, and an alignment mark recess 1494 is formed in the second resin film 1492 without being affected by the irregularities 1411 of the ASIC substrate. The alignment mark recess is carved down to the first base, and a reflective film 1493 is further formed on it, improving visibility.
 以下、詳細に説明する。
 磁性ワイヤと検出コイルおよび電極配線をASICの基板上に直接製造するGSR素子の製造方法である。
 磁性ワイヤは、CoFeSiB系アモルファス合金であり、その直径は1~15μmにて、0.5~2μmの厚みの絶縁被膜(ガラス被膜)で周囲を被覆したワイヤである。
 検出コイルは、下部コイル、上部コイルおよび接続部とからなり、コイルピッチの幅は1~5μm、コイルの幅は0.5~4.5μm、下部、上部コイルの厚みはそれぞれ0.1~1.0μmである。
The details will be explained below.
This is a manufacturing method for a GSR element in which the magnetic wire, detection coil, and electrode wiring are directly manufactured on the ASIC substrate.
The magnetic wire is made of a CoFeSiB-based amorphous alloy, has a diameter of 1 to 15 μm, and is coated with an insulating film (glass film) having a thickness of 0.5 to 2 μm.
The detection coil is composed of a lower coil, an upper coil and a connection portion, with a coil pitch of 1 to 5 μm, a coil width of 0.5 to 4.5 μm, and the thicknesses of the lower and upper coils being 0.1 to 1.0 μm respectively.
 電極配線は、外部電極、電極(端子)および外部電極と電極(端子)を接続する配線(接続配線)を総称している。
 外部電極とは、GSR素子からの入出力の電極にて、本発明ではASICの電極と接続ないし一体的に形成される。磁性ワイヤの両端および検出コイルの両端には電極(端子ともいう。)が形成される。
 検出コイルと電極配線は、導電性を有する金属例えば金などを蒸着、めっきなどすることにより形成される。
The electrode wiring is a general term for external electrodes, electrodes (terminals), and wiring (connection wiring) that connects external electrodes and electrodes (terminals).
The external electrodes are input/output electrodes from the GSR element, and in the present invention, are connected to or formed integrally with the electrodes of the ASIC. Electrodes (also called terminals) are formed on both ends of the magnetic wire and both ends of the detection coil.
The detection coil and the electrode wiring are formed by evaporating or plating a conductive metal such as gold.
 ASIC基板は、GSR素子を多数製造することができるように多数のASICが形成されている所定の大きさからなる。
 例えば、ASIC基板の大きさは、縦20mm、横20mmとすると、
1個のGSR素子と1個のASICからなる素子の集合体からなる素子基板に相当し、素子基板の個片化により50~1500個程度の素子を得ることができる。
The ASIC substrate has a predetermined size on which a number of ASICs are formed so that a number of GSR devices can be manufactured.
For example, if the size of the ASIC board is 20 mm in length and 20 mm in width,
This corresponds to an element substrate consisting of an assembly of elements each consisting of one GSR element and one ASIC, and by dividing the element substrate, it is possible to obtain about 50 to 1500 elements.
 工程(31)、(31A)~(31D)は、ASIC基板に磁性ワイヤを整列させるための逆台形状の溝を形成する工程である。
 図15に示すように、ASIC基板150の表面には回路配線起因の2~3μmの凹凸151が存在する。また、ASIC基板150表面にはSiO2などの保護膜1501が形成されている。 
そこで、まず、この段差を解消すべく、溝形成部とアライメントマーク用凹部形成部に第一台座を形成する。すなわち、ASIC基板150上にネガレジスト系の第一樹脂被膜を塗布し、マスク材を用いて露光、現像を行い、GSR素子形成のための磁性ワイヤ配置用の溝形成部とアライメントマーク形成部からなる第一台座を形成する。
Steps (31), (31A) to (31D) are steps for forming an inverted trapezoid groove for aligning magnetic wires in the ASIC substrate.
15, unevenness 151 of 2 to 3 μm due to circuit wiring exists on the surface of the ASIC substrate 150. In addition, a protective film 1501 such as SiO2 is formed on the surface of the ASIC substrate 150.
Therefore, first, in order to eliminate this step, a first seat is formed in the groove forming portion and the alignment mark recess forming portion. That is, a negative resist-based first resin coating is applied onto the ASIC substrate 150, and exposure and development are performed using a mask material to form a first seat consisting of a groove forming portion for arranging magnetic wires for forming the GSR element and an alignment mark forming portion.
この後、キュア熱処理を行い、第一台座となる第一樹脂膜を硬化させる。この時点においても、第一台座となる第一樹脂被膜の表面にはASIC基板上の凹凸が転写されて残存している。
なお、キュア熱処理の温度は250~350℃で行なう。250℃未満では硬化が不十分で後工程で形状が変化する懸念が残り、350℃を超えるとASIC回路に不具合が生じる懸念がある。
この後、凹凸が転写されて硬化している溝形成部とアライメントマーク形成部からなる第一台座の第一樹脂被膜上に残存している凹凸をCMPにより平坦化して、図16に示すように、溝形成部とアライメントマーク形成部からなる平坦な第一台座16Cを形成する。
After that, a curing heat treatment is performed to harden the first resin film that will become the first base. Even at this point, the unevenness on the ASIC board is transferred and remains on the surface of the first resin film that will become the first base.
The temperature for the curing heat treatment is 250 to 350° C. If the temperature is less than 250° C., the curing is insufficient, and there is a concern that the shape may change in a later process, whereas if the temperature exceeds 350° C., there is a concern that problems may occur in the ASIC circuit.
Thereafter, the unevenness remaining on the first resin coating of the first base consisting of the groove forming portion and the alignment mark forming portion, where the unevenness has been transferred and hardened, is flattened by CMP to form a flat first base 16C consisting of the groove forming portion and the alignment mark forming portion, as shown in FIG. 16.
 また、第一台座16Cの形成において、ASIC基板160の全面にレジストを塗布した後、第一台座の上のレジストを除去し、第一台座以外のASIC基板の表面を保護した後、第一台座を平坦化するためCMPを行ない、第一台座以外のASIC基板の表面を保護していたレジストを剥離する方法でもよい。 In addition, in forming the first pedestal 16C, a resist may be applied to the entire surface of the ASIC substrate 160, the resist on the first pedestal may be removed, the surface of the ASIC substrate other than the first pedestal may be protected, CMP may be performed to flatten the first pedestal, and the resist that was protecting the surface of the ASIC substrate other than the first pedestal may be peeled off.
そして、第一台座16Cを形成する第一樹脂被膜の膜厚は、第一台座を配置するASIC基板160表面の凹凸161の3倍以上が好ましい。3倍未満では、本工程のCMPで第一台座の凹凸を平坦化する前に、第一台座自身が薄くなってしまうためである。 The thickness of the first resin coating that forms the first pedestal 16C is preferably at least three times the irregularities 161 on the surface of the ASIC substrate 160 on which the first pedestal is placed. If it is less than three times, the first pedestal itself will become thin before the irregularities of the first pedestal can be flattened by CMP in this process.
次に、溝を形成するためのプロセスを図17に示す。
ASIC基板全面にポジレジスト系の樹脂被膜173を塗布し、マスク材を通して露光、現像することで、直方体形状の溝部とアライメントマーク用凹部とASIC基板の電極取出し用開口部を樹脂被膜に形成する。この時の露光量は1500mmである。次に、溝部のみに追加露光を行う。この時の露光量は最初の露光量の5%以下つまり、1~4%である。
Next, the process for forming the grooves is shown in FIG.
A positive resist resin film 173 is applied to the entire surface of the ASIC substrate, and exposed and developed through a mask material to form rectangular parallelepiped grooves, concave portions for alignment marks, and openings for electrode extraction of the ASIC substrate in the resin film. The amount of exposure at this time is 1500 mm2. Next, additional exposure is applied only to the grooves. The amount of exposure at this time is 5% or less of the initial exposure amount, that is, 1 to 4%.
その後キュア熱処理を行うと、図17に示すように、溝174の形状は逆台形状となり、かつ、追加露光を行っているので、ASIC基板の電極取出し用開口部176に近い溝のレジスト177ともう一方のレジスト178のレジスト高さは左右対称となる。 After that, when a curing heat treatment is performed, the shape of the groove 174 becomes an inverted trapezoid, as shown in FIG. 17, and because additional exposure has been performed, the resist height of the resist 177 in the groove closest to the electrode extraction opening 176 of the ASIC board and the resist height of the other resist 178 are symmetrical.
また、アライメントマーク凹部17Aは溝部17Bと同時に形成するので、溝と同様に逆台形状になり、視認性が低下する懸念があるため、アライメントマーク部以外をレジストで保護し、この第二樹脂被膜に形成した逆台形状のアライメントマーク凹部17Aそのものをマスクとして第一台座をRIEで掘り込むことで、アライメントマーク凹部の急峻度を高めることができる。 In addition, since the alignment mark recess 17A is formed at the same time as the groove portion 17B, it will have an inverted trapezoid shape like the groove, which may reduce visibility. Therefore, the area other than the alignment mark portion is protected with resist, and the inverted trapezoid alignment mark recess 17A formed in the second resin coating is itself used as a mask to excavate the first pedestal by RIE, thereby increasing the steepness of the alignment mark recess.
工程(32)は、逆台形状の溝に下部コイルを形成する工程である。
まず、溝174が形成されたASIC基板の溝底部にネガレジスト系の樹脂被膜(以下、N系樹脂被膜という。)を塗布し、露光、現像して前記溝部のみにN系樹脂被膜を残し、キュア熱処理によって溝の底部にR形状を形成する。
Step (32) is a step of forming a lower coil in the inverted trapezoidal groove.
First, a negative resist type resin film (hereinafter referred to as an N-type resin film) is applied to the bottom of the groove 174 of the ASIC substrate, exposed to light, and developed so that the N-type resin film remains only in the groove portion, and an R-shape is formed in the bottom of the groove by a curing heat treatment.
次に、ASIC基板表面に金属膜を成膜する。膜厚は0.1~1.0μmである。また、この金属膜はアライメント部においては反射膜105として機能するため、アライメントマークの視認性が向上できる。
このように形成したアライメントマークと、マークのシグナルを図18に示す。アライメントマークのシグナル部にはノイズもなく、アライメントマークのみのシグナルが出ており、視認性の向上が確認できる。
Next, a metal film is formed on the surface of the ASIC substrate. The film thickness is 0.1 to 1.0 μm. This metal film also functions as a reflective film 105 in the alignment area, improving the visibility of the alignment marks.
The alignment mark formed in this manner and the signal of the mark are shown in Figure 18. There is no noise in the signal portion of the alignment mark, and only the signal of the alignment mark is observed, confirming the improvement in visibility.
次に、ASIC基板全面にレジストを塗布し、マスク材を通して露光、現像を行い、コイルパターンを形成する。
この時、ASIC基板の電極取出し用開口部も開口される。
パターン内にめっき後、レジストを剥離し、めっき以外の部分の金属膜をエッチングする。尚、めっきをせずに、コイルパターン形成後に金属膜をエッチングすることで下部コイルを形成することも、もちろん可能である。この場合、めっきでコイルを形成するマスクパターンとマスクの開口部が反転する。
Next, a resist is applied to the entire surface of the ASIC board, and exposure and development are performed through a mask material to form a coil pattern.
At this time, the electrode extraction openings of the ASIC board are also opened.
After plating within the pattern, the resist is peeled off and the metal film in the non-plated areas is etched. Of course, it is also possible to form the lower coil by etching the metal film after forming the coil pattern without plating. In this case, the mask pattern for forming the coil by plating and the mask opening are reversed.
工程(33)は、磁性ワイヤを溝部に配置、固定する工程である。
前述のように溝部の側面に沿って下部コイルが形成されている。ここに、磁性ワイヤを張力30~100kg/mm2を負荷しながら配置する。
この時、磁性ワイヤの両端部を接着剤、テープなどで仮止めし、その後、樹脂被膜を基板全面に塗布、露光、現像により溝部のみに樹脂被膜を残し、250~350℃の温度にてキュア熱処理して磁性ワイヤを固定する。
これにより磁性ワイヤは溝内部に固定されると同時に張力を付加したまま熱処理されるため、GSR特性の向上を図ることができる。
Step (33) is a step of arranging and fixing the magnetic wire in the groove.
As described above, the lower coil is formed along the side of the groove, and the magnetic wire is placed thereon while being subjected to a tension of 30 to 100 kg/mm2.
At this time, both ends of the magnetic wire are temporarily fixed with adhesive, tape, etc., and then a resin film is applied to the entire surface of the substrate, exposed to light, and developed so that the resin film remains only in the grooves. The magnetic wire is then fixed by a curing heat treatment at a temperature of 250 to 350°C.
As a result, the magnetic wire is fixed inside the groove and simultaneously heat-treated while tension is applied thereto, thereby improving the GSR characteristics.
工程(34)は、磁性ワイヤに電極を接触させるため、磁性ワイヤを被覆するガラス被膜を部分的に除去する工程である。
 まず、基板全面にレジストを塗布する。次に各素子の磁性ワイヤの電極引出部のみレジストを開口する。つまり、電極引出部以外はレジストで保護されている。この状態でCF4-RIEを行うことで、磁性ワイヤの電極引出部のみ被覆されているSiO2を除去することができる。その後、レジストを除去し、ガラス被膜を部分的に除去し、磁性ワイヤに電極を接触させることができる。
 なお、磁性ワイヤに絶縁性ガラスが被覆されていない場合には本工程は省略することができる。
Step (34) is a step of partially removing the glass coating covering the magnetic wire in order to contact the magnetic wire with an electrode.
First, resist is applied to the entire surface of the substrate. Next, the resist is opened only at the electrode lead-out portions of the magnetic wires of each element. In other words, everything other than the electrode lead-out portions is protected by resist. By performing CF4-RIE in this state, it is possible to remove the SiO2 that covers only the electrode lead-out portions of the magnetic wires. After that, the resist is removed, the glass coating is partially removed, and the electrodes can be brought into contact with the magnetic wires.
If the magnetic wire is not covered with insulating glass, this step can be omitted.
工程(35)は、磁性ワイヤの上に上部コイルを形成する工程である。
まず、逆台形状溝に磁性ワイヤを配置後、ASIC基板の全面にポジレジスト系樹脂被膜を塗布し、露光、現像して前記溝と磁性ワイヤ部のみにポジレジスト系の樹脂被膜(以下、P系樹脂被膜という。)を残し、キュア熱処理して段差部を滑らかにする。
その後、基板全面に金属膜を成膜する。膜厚は0.1~1.0μmである。
Step (35) is forming the upper coil on the magnetic wire.
First, after placing the magnetic wire in the inverted trapezoidal groove, a positive resist resin film is applied to the entire surface of the ASIC board, exposed to light, and developed so that the positive resist resin film (hereinafter referred to as P-type resin film) remains only in the groove and the magnetic wire portion, and a curing heat treatment is performed to smooth out the stepped portions.
Thereafter, a metal film is formed over the entire surface of the substrate. The film thickness is 0.1 to 1.0 μm.
次に、基板全面にレジストを塗布し、オートアライメント機構により視認性の高いアライメントマークを使い、マスク材を通して露光、現像を行い、コイルパターンを形成する。
パターン内にめっき後、レジストを剥離し、めっき以外の部分の金属膜をエッチングする。尚、めっきをせずに、コイルパターン形成後に金属膜をエッチングすることで下部コイルを形成することも、もちろん可能である。この場合、めっきでコイルを形成するマスクパターンとマスクの開口部が反転する。
このプロセスにより、上部コイルは断線なく、かつ、視認性の高いアライメントマークを形成しているため、下部コイルとの合わせも問題ない。
Next, resist is applied to the entire surface of the substrate, and using highly visible alignment marks with an auto-alignment mechanism, exposure and development are performed through a mask material to form a coil pattern.
After plating within the pattern, the resist is peeled off and the metal film in the non-plated areas is etched. Of course, it is also possible to form the lower coil by etching the metal film after forming the coil pattern without plating. In this case, the mask pattern for forming the coil by plating and the mask opening are reversed.
This process prevents breaks in the upper coil and also forms highly visible alignment marks, so there are no problems with aligning it with the lower coil.
工程(36)は、磁性ワイヤと検出コイルと前記電極配線からなる素子の集合体からなる素子基板を個片化する工程である。
図19に本発明によるASIC基板上に作製した素子の平面図を示す。
ASIC基板19はASIC素子の集合体であり、例えば、20mm角のASIC基板は、300個程度のASIC素子からなる。そして、1つのASIC素子上に、1つの磁界検出素子を形成するので、ASIC基板19上には、多数個の磁界検出素子19aと、基板の4隅にアライメントマーク19bが配置されている。磁界検出素子はこの基板単位で製造し、最後に個片化を行う。
Step (36) is a step of dividing the element substrate, which is an assembly of elements each including a magnetic wire, a detection coil, and the electrode wiring, into individual pieces.
FIG. 19 shows a plan view of an element fabricated on an ASIC substrate according to the present invention.
The ASIC board 19 is an assembly of ASIC elements, and for example, a 20 mm square ASIC board is made up of about 300 ASIC elements. Since one magnetic field detection element is formed on one ASIC element, a large number of magnetic field detection elements 19a and alignment marks 19b are arranged on the four corners of the ASIC board 19. The magnetic field detection elements are manufactured on a board-by-board basis, and are finally separated into individual pieces.
次に、図20の平面図を説明する。
磁界検出素子20は、表面全体が第二樹脂被膜201により被覆され、そのサイズは幅(左右方向)1.2mm、長さ(上下方向)1.2mmよりなる。厚さは0.75mmである。
ASIC基板19上に逆台形状の溝202、下部コイル203が形成され、磁性ワイヤ204が配置・固定されている。磁性ワイヤの周囲は、下部コイル203および上部コイル205からなる検出コイルが周回している。検出コイルのコイルピッチは3.0μmで、線幅は1.2μm、厚さ1.5μmである。
磁性ワイヤ204には、ワイヤ端子206が2個形成され、それぞれワイヤ端子206と接続する配線207およびワイヤ電極208が形成されている。また、下部コイル203及び上部コイル205と接続する配線203a,205aおよびコイル電極209が2個形成されている。
Next, the plan view of FIG. 20 will be described.
The magnetic field detection element 20 has an entire surface covered with a second resin coating 201, and has a width (left-right direction) of 1.2 mm, a length (up-down direction) of 1.2 mm, and a thickness of 0.75 mm.
An inverted trapezoidal groove 202 and a lower coil 203 are formed on the ASIC board 19, and a magnetic wire 204 is disposed and fixed therein. A detection coil consisting of a lower coil 203 and an upper coil 205 winds around the magnetic wire. The detection coil has a coil pitch of 3.0 μm, a line width of 1.2 μm, and a thickness of 1.5 μm.
Two wire terminals 206 are formed on the magnetic wire 204, and wiring 207 and a wire electrode 208 are formed to connect to the wire terminals 206. In addition, wiring 203a, 205a and two coil electrodes 209 are formed to connect to the lower coil 203 and the upper coil 205.
以上の工程により、ASIC基板上にネガレジスト系樹脂被膜で第一台座を配置し、その上にポジレジスト系樹脂被膜を用いて磁性ワイヤを設置する溝と複数のアライメントマーク用凹部とASIC基板の電極取出し部を同時に露光、現像後、さらに溝部のみに追加露光しキュア熱処理して、樹脂被膜を硬化させることで、逆台形状で溝の左右の形状が対称である溝を形成することができ、狭ピッチな微細コイルを有するGSR素子をASIC基板上に直接製造することが可能となる。 By using the above process, a first base is placed on the ASIC board using a negative resist resin coating, and then a positive resist resin coating is used on top of that to simultaneously expose and develop the groove for placing the magnetic wire, the recesses for the alignment marks, and the electrode extraction section of the ASIC board. After that, an additional exposure is applied only to the groove section, and a curing heat treatment is performed to harden the resin coating, forming an inverted trapezoidal groove with symmetrical left and right shapes, making it possible to directly manufacture a GSR element with a fine coil with a narrow pitch on the ASIC board.
 本発明のASIC基板上にポジレジスト系の樹脂被膜を用い磁性ワイヤを設置するための溝と複数のアライメントマークとASIC基板の電極取出し部を同時に露光、現像後、溝部のみに追加露光し、キュア熱処理をすることで、溝形状を対称にし、かつ、視認性の高いアライメントマークを用いて微細ピッチコイルを有するGSR素子を直接形成する製造フローを説明する。 This describes a manufacturing flow for directly forming a GSR element with a fine pitch coil using highly visible alignment marks by using a positive resist resin coating on the ASIC substrate of the present invention to simultaneously expose and develop grooves for placing magnetic wires, multiple alignment marks, and the electrode extraction section of the ASIC substrate, and then additionally exposing only the grooves and performing a curing heat treatment, thereby making the groove shape symmetrical.
工程(3a); 
まず、集積回路起因の数μmの凹凸の存在するASIC基板上において、ネガレジスト系の第一樹脂被膜を10μm塗布する。露光、現像後、280℃で1時間、キュア熱処理を行い、逆台形状の溝とアライメントマークを配置する箇所に平坦で硬い第一台座を配置する。
すなわち、溝形成部Bとアライメントマーク形成部Aからなる第一台座を形成する。この時、第一台座の厚さは9μmである。
Step (3a);
First, a negative resist-based first resin film is applied to a thickness of 10 μm on an ASIC board that has unevenness of several μm caused by the integrated circuit. After exposure and development, a curing heat treatment is performed at 280°C for 1 hour, and a flat and hard first pedestal is placed at the location where the inverted trapezoid groove and alignment mark will be placed.
That is, a first pedestal is formed, which is composed of the groove forming portion B and the alignment mark forming portion A. At this time, the thickness of the first pedestal is 9 μm.
工程(3b);
この状態では、第一台座表面にはまだASIC基板の凹凸が転写され残っている。そこで、ASIC基板全面にレジストを塗布し、マスク材を用いて露光、現像をして第一台座上のみレジストを除去し、かつ第一台座以外のASIC面を保護した後、キュア熱処理で硬化した第一台座表面をCMP(Chemical Mechanical Polishing)で平坦化する。
その後、レジスト剥離液で第一台座以外のASIC表面を保護していたレジストを除去することで平坦化された第一台座Cを形成する。この時の第一台座Cの膜厚は6μm程度である。
Step (3b);
In this state, the unevenness of the ASIC substrate is still transferred onto the surface of the first pedestal, so a resist is applied to the entire surface of the ASIC substrate, and a mask material is used to expose and develop the resist, removing only the resist on the first pedestal and protecting the ASIC surface other than the first pedestal.Then, the surface of the first pedestal, which has been hardened by a curing heat treatment, is planarized by CMP (Chemical Mechanical Polishing).
Thereafter, the resist protecting the ASIC surface other than the first pedestal is removed with a resist remover to form a flattened first pedestal C. At this time, the film thickness of the first pedestal C is about 6 μm.
工程(3c);
次に、平坦化した第一台座の上にポジレジスト系の第二樹脂被膜を10μm塗布し、溝部、アライメントマーク凹部、ASIC基板電極用取出し部を同時に露光、現像する。第一台座Cは平坦化しているので、溝形成部Bとアライメントマーク形成部Aの第二台座はASIC基板の凹凸の影響は受けない。この時の露光量は1500mJ/cmである。
そして、マスクを用いて溝部のみもう一度露光する。この時の露光量は40mJ/cmである。その後、キュア熱処理を行うと、熱処理時に発生する応力により、溝は逆台形状へと変化し、かつ、溝の上部の形状はほぼ左右対称となる。すなわち、開口部に近い溝の上部ともう一方の溝の上部は形状、高さがほぼ同じであり、非対称性が大幅に改善されている。
Step (3c);
Next, a positive resist-based second resin coating is applied to the flattened first base with a thickness of 10 μm, and the groove, alignment mark recess, and ASIC substrate electrode extraction portion are exposed and developed simultaneously. Since the first base C is flattened, the second base of the groove forming portion B and the alignment mark forming portion A is not affected by the unevenness of the ASIC substrate. The exposure dose at this time is 1500 mJ/ cm2 .
Then, only the grooves are exposed again using a mask. This time, the exposure dose is 40 mJ/ cm2 . When a curing heat treatment is then performed, the grooves change to an inverted trapezoid shape due to the stress generated during the heat treatment, and the shape of the upper part of the groove becomes almost symmetrical. In other words, the shape and height of the upper part of the groove near the opening are almost the same as that of the upper part of the other groove, and the asymmetry is greatly improved.
工程(3d);
次に、ネガレジスト系の樹脂被膜をASIC基板全体に塗布、露光、現像して溝部のみにレジストを残す。その後、250℃で1時間キュア熱処理を行うことで溝の底部にR形状を形成する。
Step (3d);
Next, a negative resist resin film is applied to the entire ASIC board, exposed to light, and developed to leave the resist only in the grooves. After that, a curing heat treatment is performed at 250°C for 1 hour to form an R shape at the bottom of the groove.
工程(3e);
一方、アライメントマーク部も逆台形状であるため、その形状を急峻化するため、アライメントマーク部以外をレジストで保護し、第二樹脂被膜に形成した逆台形状のアライメントマーク凹部そのものをマスクとして第一台座をO-RIEで1μm掘り込む。その後、保護していたレジストをレジスト剥離液で除去する。
Step (3e);
On the other hand, since the alignment mark portion also has an inverted trapezoidal shape, in order to make the shape steeper, the area other than the alignment mark portion is protected with resist, and the first pedestal is excavated 1 μm by O 2 -RIE using the inverted trapezoidal alignment mark recess itself formed in the second resin coating as a mask. The protecting resist is then removed with a resist remover.
工程(3f);
次に、ASIC基板全体に、Cr/Auの積層膜を0.01/0.03μm成膜する。この膜はアライメントマーク凹部では反射膜として用い、視認性を高める。そして、このアライメントマーク凹部を使い、ASIC基板全体にレジスト塗布、露光、現像を行う。
めっき、エッチング工程を経て、逆台形状の溝面に沿って幅1.2μm、厚さ0.7μmの下部コイルを形成する。
Step (3f);
Next, a Cr/Au laminated film is formed over the entire ASIC substrate, with a thickness of 0.01/0.03 μm. This film is used as a reflective film in the alignment mark recesses to improve visibility. Then, using the alignment mark recesses, resist is applied to the entire ASIC substrate, exposed, and developed.
Through plating and etching processes, a lower coil having a width of 1.2 μm and a thickness of 0.7 μm is formed along the surface of the inverted trapezoidal groove.
工程(3g);
次に溝の下部コイルの上に、厚さ1μmの絶縁性ガラスで被覆されたCoFeB系の磁性ワイヤを張力76kg/mmを付加しながら配置し、接着剤、テープなどで仮止めする。そして、樹脂を塗布、露光、現像、250℃、1時間のキュア熱処理をして溝に固定する。この時、磁性ワイヤ19には張力が付加されたまま熱処理されるので、GSR特性を改善できる。
Step (3g);
Next, a CoFeB magnetic wire covered with 1 μm thick insulating glass is placed on top of the lower coil in the groove while applying a tension of 76 kg/ mm2 , and temporarily fixed with adhesive, tape, etc. Then, resin is applied, exposed, developed, and cured at 250°C for 1 hour to fix it in the groove. At this time, the magnetic wire 19 is heat-treated while still under tension, which improves the GSR characteristics.
工程(3h);
磁性ワイヤはその表面をガラス(SiO)被膜で覆われているので、磁性ワイヤに電極を接触させるため、この部分のガラス被膜を除去する。
 まず、ASIC基板全面にレジストを塗布し、露光、現像して磁性ワイヤに電極を接触させる部分のみレジストを開口する。そして、CF4-RIEでガラス被膜を除去後、基板全体のレジストをレジスト剥離する。
Step (3h);
Since the surface of the magnetic wire is covered with a glass (SiO 2 ) film, this portion of the glass film is removed in order to bring the electrodes into contact with the magnetic wire.
First, a resist is applied to the entire surface of the ASIC board, and then exposed and developed to open the resist only in the areas where the electrodes are to come into contact with the magnetic wires. After removing the glass coating with CF4-RIE, the resist is peeled off from the entire board.
工程(3i);
次に、磁性ワイヤと溝部の段差を解消するため、ポジレジストをASIC基板全体に塗布、露光、現像して、溝部のみレジストを残し、250℃、1時間キュア熱処理することで、レジストを硬化させる。ポジレジストは熱処理をすることで、端部形状がなだらかになることから上部コイルの形成時の断線が防止できる。
Step (3i);
Next, to eliminate the step between the magnetic wire and the groove, a positive resist is applied to the entire ASIC board, exposed to light, and developed, leaving the resist only in the groove, and then the resist is hardened by a curing heat treatment at 250°C for 1 hour. By heat treating the positive resist, the edge shape becomes smooth, preventing breaks when forming the upper coil.
工程(3j);
そして、上部コイルと磁性ワイヤの導通部の引出し線、ASIC基板の電極取出し用開口部および配線(配線)を形成するため、Cr/Auの積層膜を0.01/0.03μm成膜する。
その後、レジスト塗布、露光、現像を行い、磁性ワイヤの上部に上部コイルと磁性ワイヤの導通部の引出し線パターンとASIC基板の電極取出し用開口部を形成する。この時、アライメントマークは第一台座及び反射膜を有することによりシグナル強度も十分にあり、何の問題もなくオートアライメントにより下部コイルとの合わせを行うことができる。
このパターンにめっき、ウェット後にレジストを除去することで磁性ワイヤの上部に線幅1.2μm、厚さ0.8μmの上部コイルが形成される。下部コイルとの接続部はなだらか形状をしており、断線もなく上部コイルも形成される。
併せて、磁性ワイヤの導通部の引出し線、ASIC基板の電極取出し用開口部および配線も形成される。
Step (3j);
Then, a Cr/Au laminated film is formed to a thickness of 0.01/0.03 μm to form the lead wires of the upper coil and the conductive portion of the magnetic wire, the openings for electrode extraction and the wiring (wiring) of the ASIC board.
After that, resist is applied, exposed, and developed to form the upper coil, the lead wire pattern of the conductive part of the magnetic wire, and the opening for the electrode of the ASIC board on the upper part of the magnetic wire. At this time, the alignment mark has a first base and a reflective film, so the signal strength is sufficient and it can be aligned with the lower coil by automatic alignment without any problems.
This pattern is plated, wet-plated, and then the resist is removed to form an upper coil with a line width of 1.2 μm and a thickness of 0.8 μm on top of the magnetic wire. The connection with the lower coil has a gentle shape, and the upper coil is also formed without any breaks.
At the same time, lead lines for the conductive parts of the magnetic wires, openings for electrode extraction of the ASIC board, and wiring are also formed.
このように、第1発明~第3発明により、ASIC基板上に微細ピッチコイルを有したGSR素子を一体化形成することが可能となる。 In this way, the first to third inventions make it possible to integrally form a GSR element with a fine pitch coil on an ASIC substrate.
 本発明は、GSR素子とASICを一体化してGSRセンサの超薄型化、超小型化を実現するもので、生体内のモーションデバイスのように超小型で高性能を要求される用途での使用が期待される。 The present invention integrates a GSR element with an ASIC to create an ultra-thin, ultra-compact GSR sensor, which is expected to be used in applications that require ultra-compactness and high performance, such as motion devices in living organisms.
 本発明は、自動車用あるいはウェアラブルコンピュータ用などの小型、高性能のGSRセンサに応用可能である。 The present invention can be applied to small, high-performance GSR sensors for use in automobiles or wearable computers.
1:SiO2絶縁膜に溝を形成したASIC基板
11:ASIC基板、12:ASIC基板表面の保護膜、13:SiO2絶縁膜、14:溝(溝部)
2:ASIC基板表面の凹凸を示す図
3::ASIC基板の金属膜成膜前のアライメントマークとA1-A2線におけるマーク及び、凹凸のシグナル
30:基板、31:基板上のアライメントマーク凹部、32:マスクのアライメントマーク
301:ASIC基板の凹凸起因のシグナル、311:アライメントマーク凹部のシグナル、312:マスクのアライメントマークのシグナル
4:ポジレジスト系樹脂被膜にワイヤ配置用の溝とASIC基板の電極取出し用開口部を有するASIC基板
41:ASIC基板、42:ASIC基板表面の保護膜、
43:露光、現像、キュア熱処理後のポジレジスト系樹脂被膜
421:ASIC基板表面の保護膜の電極開口部
43H:逆台形状の溝の左右のレジスト高さの差
431:キュア熱処理後の逆台形状のワイヤ配置用溝、
432:ポジレジスト系樹脂被膜に形成したキュア熱処理後の電極取出し用開口部、
433:電極取出し部に近い側のキュア熱処理後の逆台形状のワイヤ配置用溝上部、
434:もう一方のキュア熱処理後の逆台形状のワイヤ配置用溝上部
51:ポジレジスト系樹脂被膜に、露光、現像した溝部を有するASIC基板
511:ASIC基板、512:ASIC基板表面の保護膜、
513:ポジレジスト系樹脂被膜、514:ワイヤ配置用溝
52:ポジレジスト系樹脂被膜に、露光、現像後、キュア熱処理をして逆台形状の溝部を有するASIC基板
521:ASIC基板、522:ASIC基板表面の保護膜、
523:キュア熱処理後のポジレジスト系樹脂被膜、524:キュア熱処理後のワイヤ配置用溝
6a:ASIC基板の表面の凹凸状態
60:ASIC基板
6b:第一樹脂被膜を塗布したASIC基板
61:第一樹脂被膜(第一台座)
7:溝、アライメントマークを形成した第二樹脂被膜をキュア処理し、金属膜を成膜したASIC基板
7A: アライメントマーク形成部、7G:溝形成部
70:ASIC基板、701:ASIC基板の凹凸
71:CMP後の平坦化した第一樹脂被膜(第一台座)
72:キュア熱処理した第二樹枝被膜
73:溝底部のR形状を作る樹脂被膜
74A:細長い逆台形状の溝、74G:逆台形状の溝、
75A:金属膜からなる反射膜、75G:金属膜
8:露光、現像後のワイヤ配置用溝とASIC基板の電極取出し用開口部を有するASIC基板
81:ASIC基板、
82:ASIC基板表面の保護膜、
821:ASIC基板表面の保護膜の電極開口部、
83:露光、現像後のポジレジスト系樹脂被膜、
831:ワイヤ配置用溝、
832:ポジレジスト系樹脂被膜に形成した、ASIC基板の電極取 出し用開口部、
833:電極取出し用の開口部に近い逆台形状の溝の上部、
834:もう一方の溝の上部
10:GSR素子
101:ASIC基板、102:保護被膜(SiO2)、53:ポジレジスト、104:逆台形状の溝、105:下部コイル、106:磁性ワイヤ、107:上部コイル、108:磁性ワイヤを溝内に固定するネガレジスト系樹脂被膜、109:溝とワイヤの段差を解消するためのポジレジスト系樹脂被膜
110:GSR素子形成用基板(中間工程生成体)
111:ASIC基板、112:保護被膜(SiO2)、113:ポジレジスト、
11G:溝形成部、113G:ポジレジスト、114G:逆台形状の溝、
11A:アライメント形成部、11a:アライメントマーク(+マーク)、113A:ポジレジスト、114A:逆台形状の凹部
12:ASIC基板上のGSR素子およびアライメントマーク
120:ASIC基板、
1201:ASIC基板の凹凸、
1211:第一樹脂被膜(第一台座)、
1212:第二樹脂被膜(第二台座)、
122:溝形成部、
1221:樹脂、
1222:下部コイル、
1223:磁性ワイヤ、
1224:上部コイル、
1225:溝底部にR形状を形成する樹脂被膜、  
123:アライメントマーク形成部、
1231:アライメントマーク、
1232:反射膜  
13:逆台形状の溝とアライメントマーク 
130:ASIC基板、
1311:第一樹脂被膜(第一台座1A)、
1312:第二樹脂被膜(第二台座1B)、
132:溝形成部、
1321:逆台形状の溝、
133:アライメントマーク形成部、
1331:細長い逆台形状の溝(アライメントマーク凹部)  
14:GSR素子を示す断面図
141:ASIC基板、
142:逆台形状のワイヤ配置用溝、
1421:電極取出し用の開口部に近い逆台形状の溝の上部、
1422:もう一方の溝の上部、
1423:逆台形状溝の底部のR形状を形成する樹脂被膜、
143:ASIC基板表面の保護膜
1431:ASIC基板表面の保護膜に形成された電極開口部
1432:ポリイミド系樹脂被膜に形成したASICの電極取出し用 開口部
144:下部コイル、
145:磁性ワイヤ、
1451:ワイヤを溝に固定する樹脂被膜、
1452:ワイヤと溝の段差を解消するための樹脂被膜、
146:上部コイル
149:アライメントマーク
1491:第一台座、
1492:第二台座、
1493:アライメント部の反射膜、
1494:アライメントマーク凹部
15:回路配線起因の2~3μmの凹凸を示す図
150:ASIC基板、
1501:ASIC基板表面の保護膜
151:ASIC基板上の凹凸
16:第一台座をCMPで平坦化した図
160:ASIC基板、
1601:ASIC基板表面の保護膜
16A:アライメントマーク用凹部形成部、
16B:溝形成部、
16C:キュア熱処理、CMP後の平坦化した第一台座
17:追加露光後にキュア熱処理をした図
170:ASIC基板、
1701:ASIC基板表面の保護膜
171:ASIC基板上の凹凸、
17A:アライメントマーク用凹部形成部、
17B:溝形成部、
17C:キュア熱処理、平坦化CMP後の第一台座
173:ポジレジスト系の第二樹脂被膜、
174:逆台形状の溝、
176:ASIC電極取出し用開口部、
177:ASIC電極取出し用開口部に近い側の溝レジスト
178:もう一方の側の溝レジスト、
179:アライメントマーク凹部
180:基板、
181:基板上のアライメントマーク凹部、
182:マスクのアライメントマーク
183:アライメントマーク凹部のシグナル、
184:マスクのアライメントマークのシグナル
19:ASIC基板、
19a:磁界検出素子、
19b:アライメントマーク
20: 磁界検出素子の平面図
201:第二樹脂被膜
202:溝
203:下部コイル、
203a:下部コイルに接続する配線
204:磁性ワイヤ
205:上部コイル、
205a:上部コイルに接続する配線
206:ワイヤ端子
207:ワイヤ配線
208:ワイヤ電極
209:コイル電極
 
1: ASIC substrate with a groove formed in an SiO2 insulating film 11: ASIC substrate, 12: protective film on the surface of the ASIC substrate, 13: SiO2 insulating film, 14: groove (groove portion)
2: Figure showing unevenness on the surface of the ASIC substrate 3: Alignment mark before metal film deposition on the ASIC substrate, mark on the A1-A2 line, and signal of unevenness 30: substrate, 31: alignment mark recess on substrate, 32: mask alignment mark 301: signal caused by unevenness on the ASIC substrate, 311: signal of alignment mark recess, 312: signal of alignment mark on mask 4: ASIC substrate having grooves for wire placement and openings for electrode extraction of the ASIC substrate in a positive resist resin coating 41: ASIC substrate, 42: protective film on the surface of the ASIC substrate,
43: Positive resist resin coating after exposure, development, and curing heat treatment 421: Electrode opening in protective film on the surface of the ASIC board 43H: Difference in resist height between the left and right of an inverted trapezoid groove 431: Inverted trapezoid groove for wire placement after curing heat treatment
432: An opening for electrode extraction formed in a positive resist resin coating after a curing heat treatment;
433: Upper part of the inverted trapezoidal wire arrangement groove after the curing heat treatment on the side close to the electrode extraction part,
434: the other inverted trapezoidal wire placement groove upper portion after curing heat treatment 51: ASIC substrate having a groove portion exposed and developed in a positive resist resin coating 511: ASIC substrate, 512: protective film on the surface of the ASIC substrate,
513: positive resist resin coating, 514: wire placement groove 52: ASIC substrate having an inverted trapezoid groove formed by exposing, developing and curing the positive resist resin coating, 521: ASIC substrate, 522: protective film on the surface of the ASIC substrate,
523: positive resist resin coating after curing heat treatment, 524: wire placement groove after curing heat treatment, 6a: uneven state of the surface of the ASIC substrate, 60: ASIC substrate, 6b: ASIC substrate coated with first resin coating, 61: first resin coating (first base)
7: ASIC substrate on which the second resin film on which the grooves and alignment marks are formed is cured and a metal film is formed. 7A: Alignment mark forming portion, 7G: Groove forming portion 70: ASIC substrate, 701: Concave and convex of the ASIC substrate 71: Planarized first resin film (first base) after CMP
72: Second dendritic coating subjected to heat curing treatment 73: Resin coating forming R-shape at bottom of groove 74A: Long and narrow inverted trapezoidal groove 74G: Inverted trapezoidal groove
75A: Reflective film made of metal film, 75G: Metal film 8: ASIC substrate having a groove for wire placement after exposure and development and an opening for electrode extraction of the ASIC substrate 81: ASIC substrate,
82: ASIC substrate surface protective film,
821: electrode opening in protective film on the surface of the ASIC board;
83: Positive resist resin coating after exposure and development,
831: Wire placement groove,
832: An opening for electrode extraction of an ASIC board formed in a positive resist resin coating;
833: Upper part of the inverted trapezoidal groove near the opening for electrode extraction;
834: Upper part of the other groove 10: GSR element 101: ASIC substrate, 102: Protective coating (SiO2), 53: Positive resist, 104: Inverted trapezoid groove, 105: Lower coil, 106: Magnetic wire, 107: Upper coil, 108: Negative resist resin coating for fixing the magnetic wire in the groove, 109: Positive resist resin coating for eliminating the step between the groove and the wire 110: Substrate for forming the GSR element (intermediate process product)
111: ASIC substrate, 112: protective coating (SiO2), 113: positive resist,
11G: groove forming portion, 113G: positive resist, 114G: inverted trapezoid groove,
11A: alignment forming portion, 11a: alignment mark (+ mark), 113A: positive resist, 114A: inverted trapezoid recess, 12: GSR element and alignment mark on ASIC substrate, 120: ASIC substrate,
1201: unevenness of ASIC board,
1211: first resin coating (first base);
1212: second resin coating (second base);
122: groove forming portion,
1221: resin,
1222: lower coil,
1223: magnetic wire,
1224: upper coil,
1225: Resin coating that forms an R shape at the bottom of the groove;
123: alignment mark forming unit,
1231: alignment mark,
1232: Reflective film
13: Inverted trapezoid groove and alignment mark
130: ASIC board,
1311: first resin coating (first base 1A),
1312: second resin coating (second base 1B),
132: groove forming portion,
1321: inverted trapezoid groove,
133: alignment mark forming unit,
1331: Long, inverted trapezoidal groove (alignment mark recess)
14: Cross-sectional view showing a GSR element 141: ASIC substrate,
142: inverted trapezoidal wire placement groove;
1421: Upper part of the inverted trapezoidal groove near the opening for electrode extraction;
1422: the top of the other groove,
1423: resin coating forming the R-shape of the bottom of the inverted trapezoidal groove;
143: Protective film on the surface of the ASIC substrate 1431: Electrode opening formed in the protective film on the surface of the ASIC substrate 1432: Opening for taking out the ASIC electrodes formed in the polyimide resin coating 144: Lower coil,
145: magnetic wire,
1451: Resin coating that secures the wire in the groove;
1452: Resin coating to eliminate the step between the wire and the groove;
146: upper coil 149: alignment mark 1491: first base,
1492: Second pedestal,
1493: reflective film of alignment section,
1494: Alignment mark recess 15: Diagram showing 2-3 μm unevenness caused by circuit wiring 150: ASIC substrate,
1501: Protective film on the surface of the ASIC substrate 151: Unevenness on the ASIC substrate 16: First base is flattened by CMP 160: ASIC substrate,
1601: protective film on the surface of the ASIC substrate 16A: concave portion for alignment mark,
16B: groove forming portion,
16C: Curing heat treatment, flattened first base 17 after CMP. FIG. 170: ASIC substrate subjected to curing heat treatment after additional exposure.
1701: Protective film on the surface of the ASIC substrate 171: Unevenness on the ASIC substrate
17A: Alignment mark recess forming portion,
17B: groove forming portion,
17C: First base 173 after curing heat treatment and flattening CMP: Positive resist type second resin coating,
174: inverted trapezoid groove,
176: ASIC electrode extraction opening,
177: Groove resist on the side closer to the opening for extracting the ASIC electrodes; 178: Groove resist on the other side;
179: Alignment mark recess 180: Substrate,
181: Alignment mark recess on substrate;
182: mask alignment mark 183: alignment mark recess signal
184: mask alignment mark signal; 19: ASIC substrate;
19a: magnetic field detection element,
19b: alignment mark 20: plan view of magnetic field detection element 201: second resin coating 202: groove 203: lower coil,
203a: Wiring connected to the lower coil; 204: Magnetic wire; 205: Upper coil;
205a: Wiring connected to the upper coil 206: Wire terminal 207: Wire wiring 208: Wire electrode 209: Coil electrode

Claims (12)

  1. 磁性ワイヤ、前記磁性ワイヤを周回する下部コイルと上部コイルよりなる10μm以下のコイルピッチを有する検出コイル、および電極配線からなるGSR素子を特定用途向け集積回路(以下、ASICという。)の基板上に直接製造するGSR素子の製造方法において、
    (11)前記ASIC基板上にポジレジスト系の樹脂被膜を塗布し、露光、現像して前記樹脂被膜に前記磁性ワイヤを設置するための逆台形状の溝と複数のアライメントマーク用凹部を同時に形成し、キュア熱処理して硬化し、逆台形状の溝とアライメントマーク用凹部を形成した後に、ネガレジスト系の樹脂被膜を塗布し、露光、現像して前記逆台形の溝部のみに樹脂被膜を残してキュア熱処理によって溝の底部にR形状を形成する工程と、
    (12)次に金属皮膜を成膜し、前記金属皮膜を前記アライメントマーク凹部の反射膜として使うことにより視認性の高いアライメントマークを形成する工程と、
    (13)前記アライメントマークと前記逆台形状の溝に被覆した前記金属皮膜を使って、前記逆台形状の溝面に沿って前記下部コイルを形成する工程と
    (14)前記下部コイルを形成した逆台形状の溝に張力を付加したまま前記磁性ワイヤを配置して樹脂で仮固定し、その後キュア熱処理して固定する工程と、
    (15)基板全面にポジレジスト系樹脂被膜を塗布し、露光、現像して前記溝と磁性ワイヤ部のみにポジレジスト系樹脂被膜を残し、キュア熱処理して段差部を滑らかにする工程と、
    (16)前記上部コイルと電極を形成する工程と、
    (17)前記磁性ワイヤと前記検出コイルと前記電極からなる素子の集合体を個片化する工程と、
    からなることを特徴とするGSR素子の製造方法。
    A method for manufacturing a GSR element, comprising: a magnetic wire; a detection coil having a coil pitch of 10 μm or less, which is made up of a lower coil and an upper coil surrounding the magnetic wire; and electrode wiring, the GSR element being directly manufactured on a substrate of an application specific integrated circuit (hereinafter referred to as ASIC),
    (11) A process of applying a positive resist resin film onto the ASIC board, exposing and developing the film to simultaneously form an inverted trapezoid groove for installing the magnetic wire and a plurality of concave portions for alignment marks in the resin film, hardening the film by a curing heat treatment, and after forming the inverted trapezoid groove and the concave portions for alignment marks, applying a negative resist resin film, exposing and developing the film to leave the resin film only in the inverted trapezoid groove portion, and forming an R shape at the bottom of the groove by a curing heat treatment;
    (12) forming a metal film and using the metal film as a reflective film for the alignment mark recesses to form a highly visible alignment mark;
    (13) forming the lower coil along the surface of the inverted trapezoid groove using the metal coating covering the alignment mark and the inverted trapezoid groove; and (14) arranging the magnetic wire while applying tension to the inverted trapezoid groove in which the lower coil is formed, and temporarily fixing the magnetic wire with resin, and then fixing the magnetic wire by a curing heat treatment.
    (15) a process of applying a positive resist resin coating to the entire surface of the substrate, exposing and developing the positive resist resin coating to leave the positive resist resin coating only on the grooves and magnetic wires, and smoothing the stepped portions by performing a curing heat treatment;
    (16) forming the upper coil and electrodes;
    (17) A step of singulating an assembly of elements each including the magnetic wire, the detection coil, and the electrodes;
    A method for manufacturing a GSR element comprising the steps of:
  2.  請求項1において、前記工程14が、
    (14A)前記下部コイルを形成した逆台形状の溝に張力を付加したまま前記磁性ワイヤを配置して樹脂で仮固定し、その後キュア熱処理して固定する工程と、
     前記ワイヤと電極配線を接合するためのワイヤ電極部にある前記ワイヤを被覆している絶縁性ガラスをCF-RIEにより除去する工程と、
    からなることを特徴とするGSR素子の製造方法。
    2. The method of claim 1 , wherein step 14 comprises:
    (14A) a step of placing the magnetic wire in the inverted trapezoid groove in which the lower coil is formed while applying tension thereto, temporarily fixing the magnetic wire with resin, and then fixing the magnetic wire by a curing heat treatment;
    a step of removing insulating glass covering the wire in a wire electrode portion for joining the wire to an electrode wiring by CF 4 -RIE;
    A method for manufacturing a GSR element comprising the steps of:
  3. 磁性ワイヤと前記磁性ワイヤを周回する下部コイルと上部コイルとからなる5μm以下のコイルピッチを有する検出コイルと電極配線からなるGSR素子を特定用途向け集積回路(以下、ASICという。)の基板上に直接作製するGSR素子の製造方法において、
    (21)前記ASIC基板上にネガレジスト系の第一樹脂被膜を塗布して、溝形成部とアライメントマーク形成部に平坦で硬い樹脂製の第一台座を形成する工程と、
    (22)前記第一台座の上に溝深さよりも厚いポジレジスト系の第二樹脂被膜を塗布して第二台座とし、前記第二台座の前記溝形成部には前記磁性ワイヤを配置するための逆台形状の溝(以下、溝という。)を形成するための長方形の凹部と前記アライメントマーク形成部にはアライメントマーク用凹部を形成するための凹部を同時に形成し、キュア熱処理して硬化させるとともに逆台形状の前記溝と前記アライメントマーク用凹部を形成し、
    さらに、前記アライメントマーク用凹部は前記第二台座をマスクにRIE加工をして第一台座を掘り込む工程と、
    (23)前記溝部にネガレジスト系の樹脂被膜を塗布し、露光、現像して溝部のみに樹脂被膜を残してキュア熱処理によって溝の底部にR形状を形成し、前記溝よりなる前記溝形成部と、アライメントマーク凹部よりなるアライメントマーク形成部に金属膜を成膜する工程と、
    (24)前記アライメントマーク形成部の前記金属膜の成膜された前記アライメントマーク凹部と、前記アライメントマーク形成部の平坦面に成膜された反射膜とからなる視認性の高いアライメントマークを用いて、前記金属膜の成膜された前記溝形成部の金属皮膜を前記溝の面に沿って前記下部コイルと、前記溝形成部の平坦面の上部コイル接続部(以下、下部コイルと上部コイル接続部とを下部コイルという。)を形成する工程と、
    (25)前記溝の前記下部コイルの上に前記磁性ワイヤを張力付加して配置し、樹脂により前記溝内に仮固定し、さらに張力を付加したままキュア熱処理することで、前記磁性ワイヤを溝に固定する工程と、
    (26)基板全面にポジレジスト系樹脂被膜を塗布し、露光、現像して前記溝と磁性ワイヤ部のみにポジレジスト系樹脂被膜を残し、キュア熱処理して段差部を滑らかにする工程と、
    (27)前記樹脂の上部に、オートアライメント機構により前記アライメントマークを用いて前記上部コイルと前記電極を形成する工程と、
    (28)前記磁性ワイヤと前記検出コイルと前記電極からなる素子の集合体からなる素子基板を個片化する工程と、
    からなることを特徴とするGSR素子の製造方法。
    A method for manufacturing a GSR element, which comprises a detection coil having a coil pitch of 5 μm or less, which is made up of a magnetic wire, a lower coil and an upper coil surrounding the magnetic wire, and electrode wiring, directly fabricating the GSR element on a substrate of an application specific integrated circuit (hereinafter referred to as ASIC), comprising:
    (21) applying a negative resist-based first resin coating onto the ASIC substrate to form a flat and hard resin first base in a groove formation portion and an alignment mark formation portion;
    (22) A second resin coating of a positive resist system having a thickness greater than the depth of the groove is applied onto the first pedestal to form a second pedestal, and a rectangular recess for forming an inverted trapezoid groove (hereinafter referred to as a groove) for arranging the magnetic wire is simultaneously formed in the groove forming portion of the second pedestal, and a recess for forming an alignment mark recess is simultaneously formed in the alignment mark forming portion, and the second pedestal is cured by a curing heat treatment to harden the groove and the alignment mark recess, and the inverted trapezoid groove and the alignment mark recess are formed.
    Further, the alignment mark recess is formed by performing RIE processing on the first pedestal using the second pedestal as a mask;
    (23) applying a negative resist resin film to the grooves, exposing and developing the resin film to leave only the grooves, and forming an R-shape at the bottom of the grooves by a curing heat treatment; and forming a metal film on the groove forming portion formed by the grooves and on an alignment mark forming portion formed by an alignment mark recess;
    (24) A process of forming the lower coil and the upper coil connection part (hereinafter, the lower coil and the upper coil connection part are referred to as the lower coil) on the flat surface of the groove forming part by using a highly visible alignment mark consisting of the alignment mark recess on which the metal film of the alignment mark forming part is formed and a reflective film on the flat surface of the alignment mark forming part, the metal coating of the groove forming part on which the metal film is formed being formed along the surface of the groove;
    (25) A process of placing the magnetic wire on the lower coil in the groove under tension, temporarily fixing the magnetic wire in the groove with resin, and further fixing the magnetic wire in the groove by performing a curing heat treatment while still applying tension;
    (26) a process of applying a positive resist resin coating to the entire surface of the substrate, exposing and developing the positive resist resin coating to leave the positive resist resin coating only on the grooves and magnetic wires, and smoothing the stepped portions by performing a curing heat treatment;
    (27) forming the upper coil and the electrodes on the resin using the alignment marks by an auto-alignment mechanism;
    (28) A step of dividing an element substrate consisting of an assembly of elements each consisting of the magnetic wire, the detection coil, and the electrode, into individual pieces;
    A method for manufacturing a GSR element comprising the steps of:
  4. 請求項3において、前記工程25が、
    (25A)前記溝の前記下部コイルの上に前記磁性ワイヤを張力付加して配置し、樹脂により前記溝内に仮固定し、さらに張力を付加したままキュア熱処理することで、前記磁性ワイヤを溝に固定する工程と、
    前記ワイヤと電極配線を接合するためのワイヤ電極部にある前記ワイヤを被覆している絶縁性ガラスをCF-RIEにより除去する工程と、
    からなることを特徴とするGSR素子の製造方法。
     
    In claim 3, the step 25 comprises:
    (25A) placing the magnetic wire on the lower coil in the groove under tension, temporarily fixing the magnetic wire in the groove with resin, and further fixing the magnetic wire in the groove by performing a curing heat treatment while still applying tension;
    a step of removing insulating glass covering the wire in a wire electrode portion for joining the wire to an electrode wiring by CF 4 -RIE;
    A method for manufacturing a GSR element comprising the steps of:
  5.  磁性ワイヤ、前記磁性ワイヤを周回する下部コイルと上部コイルよりなる10μm以下のコイルピッチを有する検出コイル、および電極配線からなるGSR素子を特定用途向け集積回路(以下、ASICという。)の基板上に直接製造するGSR素子の製造方法において、
    (31)前記ASIC基板上にポジレジスト系の樹脂被膜(以下、P系樹脂被膜という。)を塗布し、露光、現像して前記P系樹脂被膜に前記磁性ワイヤを配置するための溝と前記ASIC基板上の電極取出し用開口部(以下、開口部という。)を同時に形成する工程と、
    前記磁性ワイヤを配置するための溝部のみを追加露光した後、キュア熱処理して前記P系樹脂被膜を硬化し、溝上部の対称性を改善した逆台形状溝とASIC基板上の前記開口部を形成する工程と、
    (32)前記ASIC基板の全面に金属皮膜を成膜し、前記逆台形状の溝に被覆した前記金属皮膜を使って、前記逆台形状溝の溝面に沿って前記下部コイルを形成する工程と、
    (33)前記下部コイルを形成した前記逆台形状溝に張力付加した前記磁性ワイヤを配置して樹脂で仮固定し、次いでキュア熱処理して固定する工程と、
    (34)前記磁性ワイヤと前記電極配線を接合する部分のみ、前記磁性ワイヤを被覆している絶縁性ガラスをCF4-RIEにより除去する工程と、
    (35)前記ASIC基板の全面に金属皮膜を成膜し、前記上部コイルと前記電極配線を形成する工程と、
    (36)前記磁性ワイヤと前記検出コイルと前記電極配線からなる素子の集合体からなる素子基板を個片化する工程と、
    からなることを特徴とするGSR素子の製造方法。
    A method for manufacturing a GSR element, comprising: a magnetic wire; a detection coil having a coil pitch of 10 μm or less, which is made up of a lower coil and an upper coil surrounding the magnetic wire; and electrode wiring, the GSR element being directly manufactured on a substrate of an application specific integrated circuit (hereinafter referred to as ASIC),
    (31) a step of applying a positive resist type resin film (hereinafter referred to as a P-type resin film) onto the ASIC substrate, exposing and developing the film to simultaneously form grooves for disposing the magnetic wires in the P-type resin film and openings for electrode extraction (hereinafter referred to as openings) on the ASIC substrate;
    a step of exposing only the groove portion for arranging the magnetic wire to light, and then curing the P-based resin film by a curing heat treatment to harden the P-based resin film, thereby forming an inverted trapezoid groove having improved symmetry at the top of the groove and the opening portion on the ASIC substrate;
    (32) forming a metal film on the entire surface of the ASIC substrate, and forming the lower coil along a groove surface of the inverted trapezoidal groove using the metal film covering the inverted trapezoidal groove;
    (33) A step of placing the tensioned magnetic wire in the inverted trapezoid groove in which the lower coil is formed, temporarily fixing the magnetic wire with a resin, and then fixing the magnetic wire by a curing heat treatment;
    (34) removing the insulating glass covering the magnetic wire only from the portion where the magnetic wire and the electrode wiring are joined by CF4-RIE;
    (35) forming a metal film on the entire surface of the ASIC substrate to form the upper coil and the electrode wiring;
    (36) A step of dividing an element substrate consisting of an assembly of elements each consisting of the magnetic wire, the detection coil, and the electrode wiring;
    A method for manufacturing a GSR element comprising the steps of:
  6. 請求項5において、前記工程(31)が、
    (31A)前記ASIC基板上にポジレジスト系の樹脂被膜(以下、P系樹脂被膜という。)を塗布し、露光、現像して前記P系樹脂被膜に前記磁性ワイヤを設置するための溝と前記ASIC基板上の電極取出し用開口部(以下、開口部という。)とアライメントマークとを同時に形成する工程と、
    さらに、前記磁性ワイヤを設置するための溝部のみに追加露光をした後、キュア熱処理して前記P系樹脂被膜を硬化し、溝上部の対称性を改善した逆台形状溝を形成する工程と、
    からなることを特徴とするGSR素子の製造方法。
    6. The method of claim 5, wherein the step (31) comprises:
    (31A) a step of coating a positive resist type resin film (hereinafter referred to as a P-type resin film) on the ASIC substrate, exposing and developing the film to simultaneously form grooves for placing the magnetic wires in the P-type resin film, openings for electrode extraction (hereinafter referred to as openings) on the ASIC substrate, and alignment marks;
    and a step of performing additional exposure only on the groove portion for locating the magnetic wire, and then performing a curing heat treatment to harden the P-based resin coating, thereby forming an inverted trapezoidal groove with improved symmetry at the top of the groove.
    A method for manufacturing a GSR element comprising the steps of:
  7. 請求項5において、前記工程(31)が、
    (31B)前記ASIC基板上にネガレジスト系の第一樹脂被膜(以下、N系第一樹脂被膜という。)を塗布、露光、現像して、キュア熱処理後に平坦化処理をして、平坦で硬い樹脂製の第一台座を溝形成部とアライメントマーク形成部に形成した後、
    前記ASIC基板に溝深さよりも厚いポジレジスト系の第二樹脂被膜(以下、P系第二樹脂被膜という。)を塗布して第二台座とし、前記第二台座に前記溝と前記ASIC基板の電極取出し用開口部(以下、開口部という。)と前記アライメントマークを露光、現像して形成する工程と、
    さらに溝部のみに追加露光した後に第二台座をキュア熱処理して溝上部の対称性を改善した逆台形状溝を形成する工程と、
    からなることを特徴とするGSR素子の製造方法。
    6. The method of claim 5, wherein the step (31) comprises:
    (31B) A negative resist-based first resin film (hereinafter referred to as an N-based first resin film) is applied onto the ASIC substrate, exposed to light, and developed. After a curing heat treatment, a planarization treatment is performed to form a flat and hard resin first base in a groove formation portion and an alignment mark formation portion.
    a step of applying a positive resist-based second resin coating (hereinafter referred to as a P-based second resin coating) having a thickness greater than the depth of the groove on the ASIC substrate to form a second pedestal, and exposing and developing the groove, an opening for electrode extraction of the ASIC substrate (hereinafter referred to as an opening), and the alignment mark on the second pedestal;
    a step of forming an inverted trapezoidal groove with improved symmetry at the top of the groove by subjecting the second pedestal to additional exposure only in the groove portion and then subjecting the second pedestal to a curing heat treatment;
    A method for manufacturing a GSR element comprising the steps of:
  8. 請求項5において、前記工程(1)が、
    (31C)前記ASIC基板上にポジレジスト系の樹脂被膜(以下、P系樹脂被膜という。)を塗布し、露光、現像して前記P系樹脂被膜に前記磁性ワイヤを配置するための溝と前記ASIC基板上の電極取出し用開口部(以下、開口部という。)を同時にする工程と、
    前記磁性ワイヤを配置するための溝部のみに追加露光した後、キュア熱処理して前記P系樹脂被膜を硬化し、溝上部の対称性を改善した逆台形状溝とASIC基板上の前記開口部を形成する工程と、
    さらに、前記ASIC基板にネガレジスト系の樹脂被膜(以下、N系樹脂被膜という。)を塗布し、露光、現像して前記逆台形状溝の溝部のみにN系樹脂被膜を残し、キュア熱処理によって溝の底部にR形状を形成する工程と、
    からなることを特徴とするGSR素子の製造方法。
    In claim 5, the step (1) comprises:
    (31C) applying a positive resist type resin film (hereinafter referred to as a P-type resin film) on the ASIC substrate, exposing and developing the film to simultaneously form grooves for arranging the magnetic wires in the P-type resin film and openings for electrode extraction (hereinafter referred to as openings) on the ASIC substrate;
    a step of exposing only the groove portion for arranging the magnetic wire to additional light, and then curing the P-based resin film by a curing heat treatment to harden the P-based resin film, thereby forming an inverted trapezoid groove with improved symmetry at the top of the groove and the opening portion on the ASIC substrate;
    Further, a process of applying a negative resist type resin film (hereinafter referred to as an N-type resin film) to the ASIC substrate, exposing and developing the N-type resin film so that the N-type resin film remains only in the groove portion of the inverted trapezoidal groove, and forming an R-shape at the bottom of the groove by a curing heat treatment;
    A method for manufacturing a GSR element comprising the steps of:
  9.  請求項6において、前記工程(31A)が、
    (31D)前記ASIC基板上にポジレジスト系の樹脂被膜(以下、P系樹脂被膜という。)を塗布し、露光、現像して前記P系樹脂被膜に前記磁性ワイヤを設置するための溝と前記ASIC基板上の電極取出し用開口部(以下、開口部という。)とアライメントマークとを同時に形成する工程と、
    前記磁性ワイヤを設置するための溝部のみに追加露光した後、キュア熱処理して前記P系樹脂被膜を硬化し、溝上部の対称性を改善した逆台形状溝を形成する工程と、
    さらに、前記ASIC基板にネガレジスト系の樹脂被膜(以下、N系樹脂被膜という。)を塗布し、露光、現像して前記逆台形状溝の溝部のみにN系樹脂被膜を残し、キュア熱処理によって溝の底部にR形状を形成する工程と、
    からなることを特徴とするGSR素子の製造方法。
    In claim 6, the step (31A) comprises:
    (31D) applying a positive resist type resin film (hereinafter referred to as a P-type resin film) on the ASIC substrate, exposing and developing the film to simultaneously form grooves for placing the magnetic wires in the P-type resin film, openings for electrode extraction (hereinafter referred to as openings) on the ASIC substrate, and alignment marks;
    a step of exposing only the groove portion for locating the magnetic wire to additional light, and then curing the P-based resin film by a curing heat treatment to harden the P-based resin film, thereby forming an inverted trapezoidal groove with improved symmetry at the top of the groove;
    Further, a process of applying a negative resist type resin film (hereinafter referred to as an N-type resin film) to the ASIC substrate, exposing and developing the N-type resin film so that the N-type resin film remains only in the groove portion of the inverted trapezoidal groove, and forming an R-shape at the bottom of the groove by a curing heat treatment;
    A method for manufacturing a GSR element comprising the steps of:
  10. 請求項5において、前記工程(35)が、
    (35A)前記逆台形状溝に前記磁性ワイヤを配置後、前記ASIC基板の全面にポジレジスト系樹脂被膜を塗布し、露光、現像して前記溝と磁性ワイヤ部のみにポジレジスト系の樹脂被膜(以下、P系樹脂被膜という。)を残し、キュア熱処理して溝と磁性ワイヤの段差を滑らかにする工程と、
    前記ASIC基板の全面に金属皮膜を成膜し、前記上部コイルと前記電極配線を形成する工程と、
    からなることを特徴とするGSR素子の製造方法。
    6. The method of claim 5, wherein step (35) comprises:
    (35A) after arranging the magnetic wire in the inverted trapezoidal groove, a positive resist resin film is applied to the entire surface of the ASIC substrate, exposed to light, and developed to leave a positive resist resin film (hereinafter referred to as a P-type resin film) only on the groove and the magnetic wire portion, and a curing heat treatment is performed to smooth out the step between the groove and the magnetic wire;
    forming a metal film on the entire surface of the ASIC substrate to form the upper coil and the electrode wiring;
    A method for manufacturing a GSR element comprising the steps of:
  11. 請求項5~請求項10のいずれか一項において、
    前記磁性ワイヤを配置するための前記溝部のみを追加露光する際の露光量は、前記溝部の前記露光量の4%以下であることを特徴とするGSR素子の製造方法
    In any one of claims 5 to 10,
    a method for manufacturing a GSR element, the method comprising the steps of: exposing only the grooves for arranging the magnetic wires to light; and exposing the grooves to light; wherein the amount of light exposure is 4% or less of the amount of light exposure for the grooves.
  12.  請求項8または請求項9において、
     前記N系第一樹脂被膜の膜厚は、前記ASIC基板上の凹凸の3倍以上であることを特徴とするGSR素子の製造方法。
     
    In claim 8 or claim 9,
    A method for manufacturing a GSR element, characterized in that the thickness of the N-based first resin coating is at least three times the irregularities on the ASIC substrate.
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