WO2024055832A1

WO2024055832A1 - Non-volatile memory and erasing method therefor, and computer system

Info

Publication number: WO2024055832A1
Application number: PCT/CN2023/114860
Authority: WO
Inventors: 陈慧
Original assignee: 东芯半导体股份有限公司
Priority date: 2022-09-15
Filing date: 2023-08-25
Publication date: 2024-03-21
Also published as: CN115440284A

Abstract

Provided in the present disclosure are a non-volatile memory and an erasing method therefor, and a computer system. The non-volatile memory comprises a first area, which needs to be erased, and a second area, which does not need to be erased, wherein the first area and the second area share a substrate. The erasing method comprises: executing an erasing operation on a first area; in response to the cumulative number of erasing operations which are executed on the first area reaching a predetermined number N, executing anti-erasing checking on a second area of a memory, wherein N ≥ 2, and the result of the anti-erasing checking indicates whether the second area is interfered with by the erasing operation; and in response to determining that the second area is interfered with by the erasing operation, executing a repair operation on the second area. By means of the erasing method provided in the present disclosure, the impact of an erasing operation on an area which does not need to be erased can be reduced.

Description

Non-volatile memory and erasing method, computer system

Technical field

The present application relates to the field of semiconductor memory, and in particular, to an erasure technology of non-volatile memory.

Background technique

Semiconductor memory devices can generally be classified into volatile memories and non-volatile (NV: Non-Volatile) memories. Volatile memory (such as DRAM, SRAM, etc.) loses stored data in the absence of applied power. In contrast, non-volatile memory (such as EEPROM, EAROM, PROM, EPROM, NAND Flash, NOR Flash, etc.) is capable of retaining stored data in the absence of applied power. With the development of portable electronic products (such as personal computers, smart phones, digital cameras, multimedia playback devices, etc.), the demand for non-volatile memory is increasing, and the requirements for its performance are also getting higher and higher.

In non-volatile memory, there are three basic operations: read/program/erase. Flash memory, such as NAND flash memory or NOR flash memory, is widely used as a non-volatile memory. Since the programming operation of any flash memory device can only be performed within empty or erased memory cells, in most cases, an erase operation must be performed before the flash memory can be programmed. The erase operation of flash memory is usually implemented using the "Fower-Nordheim tunnel effect".

The following takes Figure 1 as an example to schematically describe the erase operation of the flash memory.

FIG. 1 illustrates a schematic structural diagram of a memory unit 100 in an existing NOR flash memory. Each memory cell in NOR flash memory is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) with a floating gate (also called a floating gate). As shown in FIG. 1 , the memory cell 100 may include a substrate 10 , a source electrode 11 , a drain electrode 12 , a tunnel oxide layer 13 , a floating gate 14 , an oxide layer 15 and a control gate 16 . When a negative voltage (eg, approximately -10V) is applied to the control gate 16 of the memory cell 100 and a positive voltage (eg, approximately 8V) is applied to the substrate 10 of the memory cell 100, the floating gate 14 of the memory cell 100 The stored electrons will escape from the floating gate 14 and tunnel through the tunnel oxide layer 13 to reach the substrate 10 . When the electrons in the floating gate 14 of the memory cell 100 are reduced to a certain extent, or in other words when the threshold voltage of the memory cell 100 is lower than the reference voltage, the memory cell 100 is considered to be successfully erased.

In NOR flash memory, multiple memory cells usually share one substrate (for example, multiple memory cells with a total storage space of up to 4M share one substrate). However, in actual operation, when performing an erase operation on NOR flash memory, erasure is usually performed in units of 4k, 16k, 32k, etc. storage space. That is to say, when performing an erase operation on a NOR flash memory, these memory cells sharing a substrate can be divided into an area A that needs to be erased (hereinafter referred to as area A) and an area B that does not need to be erased (hereinafter referred to as area A). B). When a positive voltage is applied to the substrate of area A to erase area A, area B sharing the substrate will be disturbed. For example, the electrons stored in the floating gate of area B will tunnel through the tunnel oxide layer and reach substrate, causing the threshold voltage of region B to be pulled down.

Therefore, it is desirable to propose a technical solution to reduce the impact of the above-mentioned erasing operation on the area B that does not need to be erased.

Contents of the invention

The technical solution proposed by the present invention aims to solve the above-mentioned problem of the impact of erasing operations on areas that do not need to be erased.

In one aspect of the present invention, a method for erasing a non-volatile memory is provided, wherein the non-volatile memory includes a first area that needs to be erased and a second area that does not need to be erased, and the The first region and the second region share a substrate, and the erasing method includes: performing an erasing operation on the first region; in response to the cumulative number of erasing operations performed on the first region reaching Perform an anti-erasure check on the second area of the memory a predetermined number of times N, where N≥2, and the result of the anti-erasure check indicates whether the second area is disturbed by the erasure operation; and respond After determining that the second area is disturbed by the erasing operation, a repair operation is performed on the second area.

In at least one embodiment of one aspect of the present invention, the step of performing an anti-erasure check on the second area of the memory includes: based on determining that the threshold voltage of the memory cell in the second area is between a first reference voltage and Within the predetermined voltage range of the second reference voltage, determine the second area The memory cell is disturbed by the erase operation, wherein the first reference voltage is an upper limit of the predetermined voltage range, and the second reference voltage is a lower limit of the predetermined voltage range and is used to indicate the verified Whether the memory location is one that should be protected from erasure.

In at least one embodiment of an aspect of the present invention, the step of performing an anti-erasure check on the second area of the memory further includes: comparing the threshold voltage of the memory cells in the second area with the first reference The voltage is compared with the second reference voltage to determine whether the threshold cell of the memory cell is within the predetermined voltage range.

In at least one embodiment of one aspect of the present invention, the step of performing a repair operation on the second area includes: performing a weak programming operation on the disturbed memory cells in the second area to change the damaged memory cells in the second area. The threshold voltage of the disturbed memory cell is increased to be greater than or equal to a repair target reference voltage, wherein the repair target reference voltage is greater than the first reference voltage, and wherein the first reference voltage is the same as the repair target reference voltage. The difference between the reference voltages is greater than or equal to the difference between the first reference voltage and the second reference voltage.

In at least one embodiment of an aspect of the present invention, the erasing method further includes: performing erasure verification on the first area, and the result of the erasure verification indicates whether the first area is successfully erasing; and in response to determining that the first area has not been successfully erased, performing the erasing operation on the first area again.

In at least one embodiment of one aspect of the present invention, the step of performing erasure verification on the first area is performed in response to the erasure operation performed on the first area not reaching the predetermined number N. ongoing.

In at least one embodiment of one aspect of the present invention, the erasing method further includes: after performing the anti-erasure verification on the second area, in response to determining that the second area is not an erase operation is disturbed, performing the erase check on the first area; and in response to determining that the second area is disturbed by the erase operation, performing the erase check on the disturbed memory cells of the second area. After the repair operation, the erasure verification is performed on the first area.

In at least one embodiment of an aspect of the present invention, the step of performing erasure verification on the first area includes: based on the threshold voltages of all memory cells in the first area being less than the erasure target reference voltage, determining The first area is successfully erased; and based on the threshold voltage of at least one memory cell in the first area being greater than or equal to the erasure target reference voltage, it is determined The first area was not successfully erased.

In at least one embodiment of one aspect of the present invention, only when the cumulative number of erase operations performed on the first area reaches the predetermined number N, the second area of the memory is executed. The anti-erasure check and reset the accumulated number of erase operations to zero, wherein the predetermined number N≤128 or the predetermined number N≤64, and wherein the non-volatile Flexible memory includes NOR flash memory.

In another aspect of the present invention, a non-volatile memory is provided, which stores computer instructions. When the computer instructions are executed by a processing unit, the processing unit executes on the non-volatile memory as described in the preceding paragraph. The erasing method described in any of the paragraphs.

In yet another aspect of the present invention, a computer system is provided, including: a computer storage medium storing computer instructions; a non-volatile memory; and a processing unit, which performs processing on all the computer instructions when executing the computer instructions. The non-volatile memory performs an erasure method as described in any of the preceding paragraphs.

The technical solution proposed by the present invention may have one or more of the following advantages:

(1) The present invention proposes to perform verification and/or repair on the unnecessary erasing area only after performing multiple erasing operations. Verification and/or repair, the present invention can have higher erasure efficiency for NOR memory.

(2) The present invention proposes to perform verification and/or repair of the areas that do not need to be erased after performing a predetermined number of erasing operations. Compared with performing verification and/or repairing the areas that need to be erased in the NOR memory after all the areas that need to be erased have been successfully erased, There is no need to erase the area for verification and/or repair. The present invention can have higher accuracy in judging whether the area that does not need to be erased is disturbed, and thus provides better performance in repairing the area that does not need to be erased. Timeliness.

Description of drawings

The drawings are used to provide a further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

The drawings are not intended to be drawn to scale. In the drawings, each identical or approximately identical component shown in various figures may be designated by the same reference numeral. For clarity, not every component is labeled in each figure. The present invention will now be described by way of examples and with reference to the accompanying drawings Embodiments of various aspects, wherein:

Figure 1 illustrates a schematic structural diagram of a storage unit in an existing NOR flash memory.

Figure 2 shows a flow chart of a non-volatile memory erasing method according to an embodiment of the present invention.

Figure 3 shows a block diagram of a non-volatile memory according to an embodiment of the invention.

Figure 4 shows a block diagram of a computer system according to an embodiment of the invention.

Reference signs:

100 storage units

10 substrate

11 source

12 drain

13 tunnel oxide layer

14 floating gate

15 oxide layer

16 control grid

300 non-volatile memory

301 storage area

303 Processing Department

400 computer systems

401 Non-volatile memory

402 Computer storage media

403 Processing Department

Detailed ways

In order to better understand the technical content of the present invention, specific embodiments are described below along with the accompanying drawings.

Aspects of the invention are described in this disclosure with reference to the accompanying drawings, in which a number of illustrated embodiments are shown. The embodiments of the present disclosure are not necessarily intended to include all aspects of the invention. It should be understood that the various concepts and embodiments introduced above, as well as those described in greater detail below, The embodiments may be implemented in any of many ways, as the disclosed concepts and embodiments are not limited to any embodiment. Additionally, some aspects of the present disclosure may be used alone or in any suitable combination with other aspects of the present disclosure.

Those skilled in the art will recognize that various embodiments may be practiced without one or more specific details or with other alternative and/or additional methods, operations, or components. In other instances, well-known structures or operations have not been shown or described in detail so as not to obscure aspects of the various embodiments of the invention. Likewise, for purposes of explanation, specific numbers, operations, and configurations are set forth in order to provide a thorough understanding of embodiments of the invention. However, the invention may be practiced without the specific details. Furthermore, it is to be understood that the various embodiments illustrated in the drawings are illustrative representations and are not necessarily drawn to scale. It should also be understood that the voltage values or voltage ranges described herein are exemplary only and are not intended to limit the scope of the invention.

Referring to FIG. 2, FIG. 2 shows a flow chart of a non-volatile memory erasing method 200 (hereinafter referred to as the erasing method 200) according to an embodiment of the present invention. In some embodiments, the erasing method 200 may be applied to the NOR flash memory including the memory unit 100 shown in FIG. 1 to erase the area A in the NOR flash memory that needs to be erased.

At step 201, the erasure process is initiated. In some embodiments, parameter n may be set to indicate the erase performed during an erase process for area A (which may be simply referred to as area A) in a non-volatile memory (eg, NOR flash memory) that needs to be erased The cumulative number of operations. During the startup of the erase process, this parameter n can be set to zero. The erasing method 200 may proceed to step 203.

At step 203, an erasure operation is performed on area A. After initiating the erase process, an erase operation can be performed on area A in the memory. For example, when performing an erase operation, a negative voltage (eg, about -10V) may be applied to the control gates 16 of all memory cells 100 in area A and the area A and area B that do not need to be erased (which may be simply referred to as area B) A positive voltage (for example, about 8V) is applied to the common substrate 10 . In some embodiments, area A can be further divided into multiple sub-areas. In one erasure operation, the erasure operation can be performed simultaneously on several or all sub-areas in area A, or only on area A. A subregion performs an erasure operation. The erasing method 200 may proceed to step 205.

At step 205, parameter n is increased by one. In some embodiments, after an erasure operation is performed on area A, a value indicating the cumulative number of erasure operations performed during the erasure process may be Parameter n is increased by 1. The erasing method 200 may proceed to step 207.

At step 207, determine whether parameter n=N? In some embodiments, after each erasure operation is performed and the parameter n is increased by 1, the parameter n may be compared with the predetermined number of times N to determine whether the parameter n reaches the predetermined number of times N. In some embodiments, the predetermined number N may be set to any integer in the range of 2 to 128. In other embodiments, the predetermined number N may be set to any integer in the range of 2 to 64, such as N=5, 10, 20, 30, 40, 50, 60, and so on. When it is determined that parameter n=N, the erasing method 200 may proceed to step 209. When it is determined that the parameter n≠N, the erasing method 200 may proceed to step 215.

At step 209, an erasure verification is performed on area B. In some embodiments, when the cumulative number of erase operations performed on area A reaches a predetermined number N, an anti-erasure check may be performed on area B in the non-volatile memory (eg, NOR flash memory) to determine Whether the above erasure operation performed on area A causes interference to area B. The memory unit 100 in area B and the memory unit 100 in area A share the substrate 10 . For example, when performing anti-erasure verification on region B, the threshold voltages of the memory cells 100 in region B may be compared with the first reference voltage and the second reference voltage. The first reference voltage is an upper limit reference voltage for anti-erasure verification, and the second reference voltage is a lower limit reference voltage for anti-erasure verification. The upper limit reference cell may be used to indicate whether a repair operation as shown below should be performed on the memory cell 100 being verified. For example, if the threshold voltage of the memory cell 100 is greater than the upper limit reference voltage, it may be considered that there is no need to perform a repair operation on the memory cell. On the contrary, if the threshold voltage of the memory cell 100 is less than or equal to the upper limit reference voltage, it is considered that a repair operation may need to be performed on the memory cell. The lower limit reference voltage may be used to indicate whether the memory cell 100 being verified is an erase cell that should be prevented from being erased. For example, when the threshold voltage of the memory cell 100 is less than the lower limit reference voltage, it can be considered that the memory cell is not a memory cell that should be prevented from being erased (for example, the memory cell may be a memory cell that should be erased), and further it can be considered that it is not necessary. Perform the repair operations described below on the storage unit. On the contrary, when the threshold voltage of the memory cell 100 is greater than or equal to the lower limit reference voltage, the memory cell can be considered to be a memory cell that should be prevented from being erased. As described below, the memory cell 100 can be configured when the threshold voltage of the memory cell is less than or equal to the lower limit reference voltage. When the upper limit reference voltage is greater than or equal to the lower limit reference voltage, a repair operation is performed on the memory cell. By setting two reference voltages in the anti-erasure verification, namely, the upper limit reference voltage and the lower limit reference voltage, and comparing the threshold voltage of the area B that does not need to be erased with the upper limit reference voltage and the lower limit respectively. Comparison with the reference voltage can correctly determine whether the area B that does not need to be erased is disturbed, thereby allowing timely repair of the area B that does not need to be erased. As a non-limiting example, the first reference voltage and the second reference voltage may be any voltage value between 5V and 7V, wherein the first reference voltage may be greater than the second reference voltage. In addition, in step 209, when it is determined that the cumulative number of erasure operations performed on the area A reaches the predetermined number N, that is, when it is determined that the parameter n reaches N, the parameter n may be reset to zero. The erasing method 200 may proceed to step 211.

At step 211, determine whether area B is interfered? In some embodiments, whether area B is disturbed may be determined based on the result of an anti-erasure check performed on area B. For example, when the threshold voltage of a memory cell 100 in area B is less than or equal to the first reference voltage and greater than or equal to the second reference voltage, it can be determined that the memory cell in area B is disturbed by the erasure operation. Otherwise, when the threshold voltages of all the memory cells 100 in the region B are not within the predetermined voltage range of the first reference voltage and the second reference voltage, it is determined that the region B is not disturbed by the erase operation. When it is determined that the memory cell 100 in area B is disturbed, the erasing method 200 may proceed to step 213 . When it is determined that all memory cells 100 in area B are not disturbed, the erasing method 200 may proceed to step 215 .

At step 213, a repair operation is performed on area B. In some embodiments, when it is determined that the memory unit 100 of area B is disturbed, a repair operation may be performed on the disturbed memory unit 100 of area B to reduce the impact of the erase operation on area B. For example, when performing a repair operation on region B, a weak programming operation may be performed on the disturbed memory cells 100 of region B to increase the threshold voltage of the disturbed memory cells 100 of region B to be greater than or equal to the repair target reference voltage. As a non-limiting example, the repair target reference voltage may be any voltage value between 7V and 8V, where the repair target reference voltage may be greater than the first reference voltage. In some embodiments, the first reference voltage may be set closer to the second reference voltage than the repair target reference voltage. For example, the difference between the repair target reference voltage and the first reference voltage may be greater than or equal to the difference between the first reference voltage and the second reference voltage. For another example, the difference between the repair target reference voltage and the first reference voltage may be greater than or equal to twice the difference between the first reference voltage and the second reference voltage. For another example, the difference between the repair target reference voltage and the first reference voltage may be greater than or equal to three times the difference between the first reference voltage and the second reference voltage. The erasing method 200 may proceed to step 215.

At step 215, erasure verification is performed on area A. In some embodiments, when performing erasure verification on area A, the threshold voltage of the memory cell 100 in area A may be compared with the erase target reference voltage to determine whether area A is successfully erased. As a non-limiting example, the erase target reference voltage may be any voltage value between 2V and 4V. The erasure method 200 may proceed to step 217.

At step 217, it is determined whether area A is successfully erased. In some embodiments, whether area A is successfully erased may be determined based on a result of an erasure check performed on area A. For example, when the threshold voltages of all memory cells 100 in area A are less than the erase target reference voltage, it may be determined that area A is successfully erased. Otherwise, when the threshold voltage of at least one memory cell 100 in area A is greater than or equal to the erasure target reference voltage, it is determined that area A has not been successfully erased. When it is determined that area A is successfully erased, erasing method 200 may proceed to step 219 . When it is determined that area A has not been successfully erased, the erasing method 200 may return to step 203 and continue to perform the erasing operation on area A.

At step 219, the erasure process ends. When it is determined that area A in the memory is successfully erased, the erasing process of area A may be ended.

The above steps are exemplary and are not intended to be limiting. Those skilled in the art can add one or more steps according to their needs, or delete one or more of the above steps, or combine or replace one or more of the above steps, or combine one or more of the above steps or Adjust the order of multiple.

Hereinafter, the nonvolatile memory according to the embodiment of the present invention will be described with reference to FIG. 3 . Figure 3 shows a block diagram of a non-volatile memory 300 according to an embodiment of the invention.

In some embodiments, the non-volatile memory 300 may be a NAND flash memory, a NOR flash memory, or other non-volatile memory. As shown in FIG. 3 , the nonvolatile memory 300 may include a storage area 301 and a processing part 303 . Storage area 301 may be used to store computer instructions. The processing part 303 may execute the computer instructions stored in the storage area 301 automatically or upon receiving a signal from an external computing device (eg, a computer or a communication terminal, etc.) to implement the erasing method 200 as described above. one or more of the steps. In some embodiments, processing portion 303 may be a semiconductor chip, such as within non-volatile memory 300 .

Hereinafter, the computer system according to the embodiment of the present invention will be described with reference to FIG. 4 . Figure 4 shows A block diagram of a computer system 400 is shown in accordance with an embodiment of the invention.

As shown in FIG. 4 , the computer system 400 may include a nonvolatile memory 401 , a computer storage medium 402 and a processing unit 403 . The non-volatile memory 401 may be NAND flash memory, NOR flash memory, etc. Computer storage media 402 may be used to store computer instructions. Processing unit 403 may control non-volatile memory 401 automatically or upon receipt of a signal externally (eg, via wireless transmission) or internally (eg, from other circuits or components within computer system 400 ). The non-volatile memory 401 is controlled below. For example, the processing unit 403 may execute computer instructions stored in the computer storage medium 402 to implement one or more of the steps in the erasing method 200 as described above for the non-volatile memory 401 . As an example, the processing unit 403 may include ASIC (Application Specific Integrated Circuit: Application Specific Integrated Circuit), IC (Integrated Circuit: Integrated Circuit), DSP (Digital Signal Processor: Digital Signal Processor), FPGA (Field Programmable Gate Array: Field Programmable Gate Array) Programming gate array), various logic circuits, and various signal processing circuits, etc.

Although the invention has been described in terms of preferred embodiments thereof, it is not intended to be limited thereto, but only to the extent set forth in the appended claims.

Claims

A method of erasing a non-volatile memory, wherein the non-volatile memory includes a first area that needs to be erased and a second area that does not need to be erased, and the first area and the second area Sharing the substrate, the erasing method includes:

Perform an erasure operation on the first area;

In response to the cumulative number of erase operations performed on the first area reaching a predetermined number N, performing an anti-erasure check on the second area of the memory, where N≥2, the anti-erasure check The result indicates whether the second area is disturbed by the erase operation; and

In response to determining that the second area is disturbed by the erasure operation, a repair operation is performed on the second area.
The erasing method of claim 1, wherein the step of performing an erasure-proof verification on the second area of the memory includes:

Based on determining that the threshold voltage of the memory cells in the second area is within a predetermined voltage range from the first reference voltage to the second reference voltage, it is determined that the memory cells in the second area are disturbed by the erase operation, wherein the The first reference voltage is an upper limit of the predetermined voltage range, and the second reference voltage is a lower limit of the predetermined voltage range and is used to indicate whether the verified memory cell is a memory cell that should be prevented from being erased.
The erasing method according to claim 2, wherein the step of performing an erasure prevention check on the second area of the memory further includes:

The threshold voltage of the memory cell in the second region is compared with the first reference voltage and the second reference voltage to determine whether the threshold voltage of the memory cell is within the predetermined voltage range.
The erasing method of claim 2, wherein the step of performing a repair operation on the second area includes: performing a weak programming operation on the disturbed memory cells in the second area to change the second area. The threshold voltage of the region of the disturbed memory cell is increased to be greater than or equal to the repair target reference voltage,

wherein the repair target reference voltage is greater than the first reference voltage, and

Wherein, the difference between the first reference voltage and the repair target reference voltage is greater than or equal to the difference between the first reference voltage and the second reference voltage.
The erasing method according to claim 1, characterized in that the erasing method further includes:

Perform an erasure check on the first area, the result of the erasure check indicating whether the first area is successfully erased; and

In response to determining that the first area has not been successfully erased, the erasing operation is performed on the first area again.
The erasing method of claim 5, wherein the step of performing erasure verification on the first area is in response to the erasure operation performed on the first area not reaching the predetermined number of times. carried out by N.
The erasing method according to claim 5, characterized in that the erasing method further includes:

After performing the anti-erasure verification on the second area, in response to determining that the second area is not disturbed by the erasure operation, performing the erasure verification on the first area; and

After performing the repair operation on the disturbed memory cells of the second area in response to determining that the second area is disturbed by the erase operation, performing the erase verification on the first area.
The erasing method of claim 5, wherein the step of performing erasure verification on the first area includes:

Based on the threshold voltages of all memory cells in the first area being less than the erase target reference voltage, it is determined that the first area is successfully erased; and

Based on the fact that the threshold voltage of at least one memory cell in the first area is greater than or equal to the erase target reference voltage, it is determined that the first area has not been successfully erased.
The erasing method according to claim 5, characterized in that only when the accumulated number of erasing operations performed on the first area reaches the predetermined number N, the second area of the memory is a region performs the anti-erasure check and resets the cumulative number of erase operations to zero,

Wherein, the predetermined number of times N≤128 or the predetermined number of times N≤64, and

Wherein, the non-volatile memory includes NOR flash memory.
A non-volatile memory, characterized in that computer instructions are stored therein. When the computer instructions are executed by a processing unit, the processing unit executes any one of claims 1 to 9 on the non-volatile memory. The erasing method described in the item.
A computer system, characterized by including:

Computer storage media storing computer instructions;

non-volatile memory; and

A processing unit, when executing the computer instruction, performs the erasing method according to any one of claims 1 to 9 on the non-volatile memory.