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WO2024051553A1 - 一种图腾柱pfc电路、其控制方法及电源装置 - Google Patents

一种图腾柱pfc电路、其控制方法及电源装置 Download PDF

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Publication number
WO2024051553A1
WO2024051553A1 PCT/CN2023/115861 CN2023115861W WO2024051553A1 WO 2024051553 A1 WO2024051553 A1 WO 2024051553A1 CN 2023115861 W CN2023115861 W CN 2023115861W WO 2024051553 A1 WO2024051553 A1 WO 2024051553A1
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WO
WIPO (PCT)
Prior art keywords
half cycle
signal
diode
time period
inductor
Prior art date
Application number
PCT/CN2023/115861
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English (en)
French (fr)
Inventor
张贺军
卢茂勇
吴其北
朱吉新
Original Assignee
华为数字能源技术有限公司
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Publication of WO2024051553A1 publication Critical patent/WO2024051553A1/zh

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0051—Diode reverse recovery losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/06—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
    • H02M7/066—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode particular circuits having a special characteristic
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present application relates to the field of circuit control technology, and in particular to a totem pole PFC circuit, its control method and power supply device.
  • Bridgeless PFC (Power Factor Correction) circuits include many types, one of which is totem pole PFC.
  • the specific structure is shown in Figure 1.
  • the totem pole PFC circuit with this structure has fewer moving points in the power loop, It has the characteristics of small number of devices and small occupation area.
  • the totem pole PFC circuit with this structure cannot achieve soft start.
  • due to the existence of parasitic diodes in the transistors (such as G1 and G2) (the structure shown in the dotted box in Figure 1), Moreover, the parasitic diode has a reverse recovery current and a large loss, which results in a low switching frequency of the totem pole PFC circuit with this structure.
  • This application provides a totem pole PFC circuit, its control method and a power supply device to increase the switching frequency of the totem pole PFC circuit with soft start function.
  • inventions of the present application provide a totem pole PFC circuit.
  • the totem pole PFC circuit includes a soft start module, a first diode, a second diode and a capacitor, wherein the soft start module passes through the first and second diode.
  • the pole tube is electrically connected to the positive busbar, and is electrically connected to the negative busbar through the second diode; and the soft start module is also electrically connected to the positive busbar, the negative busbar and the power input terminal respectively;
  • the soft start module when the AC signal provided by the power input terminal is in the positive half cycle, can transmit the AC signal in the positive half cycle to the positive bus and the negative bus through the first diode, and store it in the positive bus and the negative bus. in the capacitance between the negative buses; when the AC signal provided by the power input terminal is in the negative half cycle, the soft start module can transmit the AC signal in the negative half cycle to the positive bus and the negative bus through the second diode. Similarly Stored into a capacitor located between the positive and negative buses.
  • the soft start module the first diode and the second diode, the rectification effect on the AC signal provided by the power input end is realized, and the AC signal is adjusted into a DC signal and then output.
  • the AC signal is transmitted through the first diode and the second diode, rather than through the parasitic diode of the transistor as in the prior art, because the first diode and the second diode are both Silicon carbide-based diodes, and silicon carbide-based diodes have the characteristics of small loss and no reverse recovery current.
  • the parasitic diodes of transistors are also silicon-based diodes, because silicon-based diodes have reverse
  • the reverse recovery current is high and the loss is high, so using silicon carbide-based diodes can eliminate the reverse recovery current and reduce losses, thereby increasing the switching frequency of the totem pole PFC circuit.
  • the totem pole PFC circuit provided in the embodiment of the present application can realize soft start and increase the switching frequency at the same time.
  • the soft start module may include: a first inductor, a second inductor, a first soft start unit and a second soft start unit.
  • the first end of the power input end is connected to the first node, and the second end of the power input end is connected to the second node; when the AC signal provided by the power input end is in a positive half cycle, the first node is at a positive potential and the second node is at a negative potential. ; When the AC signal provided by the power input terminal is in the negative half cycle, the first node is at a negative potential and the second node is at a positive potential; the connection point between the first diode and the first soft-start unit is the third node; The connection point between the diode and the second soft-start unit is the fourth node.
  • the specific setting method is: the first inductor is connected between the first node and the third node, that is, the first end of the first inductor and the first node Electrically connected, the second end of the first inductor is electrically connected to the third node; the first soft start unit is electrically connected to the second node, the third node, and the negative bus respectively;
  • the first soft start unit when the AC signal provided by the power input terminal is in the positive half cycle, that is, when the first node is at the positive potential and the second node is at the negative potential, within the first preset time period, the first soft start unit will be in the positive half cycle of the AC signal.
  • the signal is stored in the first inductor to charge the first inductor,
  • the electric energy provided by the power input end is stored in the first inductor, so that the first end of the first inductor (i.e., the first node) is at a positive potential, and the second end (i.e., the third node) is at a negative potential;
  • the first soft-start unit transfers the electric energy stored in the first inductor to the capacitor through the first diode to charge the capacitor, so as to transfer the electric energy provided by the power input end to the capacitor, so that the first inductor One end (i.e., the first node) is at a negative potential, and the second end (i.e., the third node) is at a positive potential.
  • the first preset duration and the second preset duration alternately occur at least once, so that the electric energy is intermittently transferred to the capacitor, and the power factor correction processing of the AC signal in the positive half cycle
  • the specific arrangement method is: the second inductor is connected between the first node and the fourth node, that is, the first end of the second inductor is electrically connected to the first node, The second end of the second inductor is electrically connected to the fourth node; the second soft start unit is electrically connected to the second node, the fourth node, and the positive bus respectively;
  • the second soft start unit when the AC signal provided by the power input terminal is in the negative half cycle, that is, the first node is at the negative potential, and when the second node is at the positive potential, within the third preset time period, the second soft start unit will be in the negative half cycle of the AC signal.
  • the signal is stored in the second inductor to charge the second inductor, so that the electric energy provided by the power input terminal is stored in the second inductor, so that the first end of the second inductor (i.e., the first node) is at a negative potential, and the second end (that is, the fourth node) is at a positive potential; within the fourth preset time period, the second soft-start unit transfers the electric energy stored in the second inductor to the capacitor through the second diode to charge the capacitor to input power.
  • the electric energy provided by the second inductor is transferred to the capacitor, so that the first end of the second inductor (ie, the first node) is at a positive potential, and the second end (ie, the fourth node) is at a negative potential.
  • the third preset duration and the fourth preset duration alternately appear at least once, thereby causing the electric energy to be transferred to the capacitor intermittently and realizing the power factor correction processing of the AC signal in the negative half cycle.
  • the function of the soft start module can be realized. Regardless of whether the AC signal provided by the power input terminal is in the negative half cycle or the positive half cycle, the electric energy can be stored in the corresponding in the inductor and then transferred to the capacitor to process the AC signal provided by the power input end.
  • the switching of the totem pole PFC circuit with soft start function is improved. frequency.
  • the first soft start unit can be set to:
  • the first soft start unit includes: a first transistor and a first thyristor, wherein:
  • the first electrode of the first transistor is electrically connected to the third node (that is, the first electrode is electrically connected to the first inductor and the positive electrode of the first diode respectively), and the second electrode of the first transistor is respectively connected to the negative bus and the first
  • the positive electrode of the thyristor is electrically connected, and the control electrode of the first transistor is electrically connected to the first control signal line;
  • the cathode of the first thyristor is electrically connected to the second end of the power input terminal (ie, the second node), and the gate of the first thyristor is electrically connected to the second control signal line.
  • the first control signal line can control the first transistor to turn on, and the second control signal line can control the first thyristor to turn on, so that the first inductor, the first transistor, the first thyristor and the power supply
  • the input end can form a charging loop to store the AC signal in the positive half cycle into the first inductor; within the second preset time period, the first control signal line can control the first transistor to turn off, and the second control signal line continues to maintain
  • the first thyristor is turned on, so that the first inductor, the first diode, the capacitor, the first thyristor and the power input terminal can form a discharge circuit, and the electric energy stored in the first inductor is transferred to the capacitor, so that the first transistor is and control the conduction state of the first thyristor to realize the transfer of electric energy and signal processing.
  • the second soft start unit can be set to:
  • the second soft start unit includes: a second transistor and a second thyristor, wherein:
  • the first electrode of the second transistor is electrically connected to the fourth node (that is, the first electrode is electrically connected to the negative electrode of the second inductor and the second diode respectively), and the second electrode of the second transistor is respectively connected to the positive bus and the second
  • the negative electrode of the thyristor is electrically connected, and the control electrode of the second transistor is electrically connected to the third control signal line;
  • the anode of the second thyristor is electrically connected to the second end of the power input terminal (ie, the second node), and the gate of the second thyristor is electrically connected to the fourth control signal line.
  • the third control signal line can control the second transistor to turn on, and the fourth control signal line can control the second thyristor to turn on, so that the second inductor, the second transistor, the second thyristor and the power supply
  • the input end can form a charging loop to store the AC signal in the negative half cycle into the second inductor; within the fourth preset time period, the third control signal line can control the second transistor to turn off, and the fourth control signal line continues to maintain
  • the second thyristor is turned on, so that the second inductor, the second diode, the capacitor, the second thyristor and the power input terminal can form a discharge circuit, and the electric energy stored in the second inductor is transferred to the capacitor, thereby passing through the second transistor. and control the conduction state of the second thyristor to realize the transfer of electric energy and signal processing.
  • the first transistor has a parasitic diode, the anode of the parasitic diode is electrically connected to the negative bus, and the cathode is connected to the third transistor.
  • the three nodes are electrically connected; when the first transistor is a silicon-based diode, the parasitic diode is also a silicon-based diode, and if current passes through the silicon-based diode, the silicon-based diode is prone to generate reverse recovery current;
  • the silicon carbide-based diode Since the electric energy is transferred to the capacitor through the first diode within the second preset time period, and the first diode is a silicon carbide-based diode, the silicon carbide-based diode has no reverse recovery current; and, in the second preset time period, Within a long period of time, when the first inductor, the first diode, the capacitor, the first thyristor and the power input terminal form a discharge circuit, because the anode potential of the parasitic diode of the first transistor is less than the cathode potential, the current in the discharge circuit is also not will pass through the parasitic diode; based on this, there is no reverse recovery current during the second preset time period.
  • the second transistor also has a parasitic diode, the cathode of the parasitic diode is electrically connected to the positive bus, and the anode is electrically connected to the fourth node; when the second transistor is a silicon-based diode, the parasitic diode is also a silicon-based diode, and If current passes through a silicon-based diode, the silicon-based diode is prone to reverse recovery current;
  • the silicon carbide-based diode Since the electric energy is transferred to the capacitor through the second diode within the fourth preset time period, and the second diode is a silicon carbide-based diode, the silicon carbide-based diode has no reverse recovery current; and, in the fourth preset time period, Within a long time, when the second inductor, the second diode, the capacitor, the second thyristor and the power input terminal form a discharge circuit, because the anode potential of the parasitic diode of the second transistor is less than the cathode potential, the current in the discharge circuit is also not will pass through the parasitic diode, so there is no reverse recovery current within the fourth preset time period.
  • the charging process and the discharging process can be switched quickly and effectively, thereby effectively increasing the switching frequency of the totem pole PFC circuit.
  • the manufacturing process of silicon-based transistors is relatively mature and the manufacturing cost is low.
  • the combination of silicon-based transistors and silicon carbide-based diodes can effectively increase the switching frequency of totem pole PFC circuits while also reducing the manufacturing cost of totem pole PFC circuits. cost and improve the manufacturing yield of totem pole PFC circuits.
  • control method is such as the above-mentioned totem pole PFC circuit provided by the embodiment of the present application.
  • the control method may include:
  • the soft start module can transmit the AC signal in the positive half cycle to the positive bus and the negative bus through the first diode, and store it in the positive bus and the negative bus. in the capacitance between them; when the AC signal provided by the power input terminal is in the negative half cycle, the soft start module can transmit the AC signal in the negative half cycle to the positive bus and the negative bus through the second diode, and also store it in Located in the capacitor between the positive and negative buses.
  • the soft start module the first diode and the second diode, the rectification effect on the AC signal provided by the power input end is realized, and the AC signal is adjusted into a DC signal and then output.
  • the AC signal is transmitted through the first diode and the second diode, rather than through the parasitic diode of the transistor as in the prior art, because the first diode and the second diode are both Silicon carbide-based diodes, and silicon carbide-based diodes have the characteristics of small loss and no reverse recovery current.
  • the parasitic diodes of transistors are also silicon-based diodes, because silicon-based diodes have reverse The reverse recovery current and the loss are high, so using silicon carbide-based diodes can eliminate the reverse recovery current and reduce losses, thereby increasing the switching frequency of the totem pole PFC circuit.
  • the totem pole PFC circuit provided in the embodiment of the present application can realize soft start and increase the switching frequency at the same time.
  • control method provided by the embodiment of the present application is described in detail below based on the AC signal of the positive half cycle and the AC signal of the negative half cycle respectively.
  • the soft start module when the soft start module includes: a first inductor, a second inductor, a first soft start unit and a second soft start unit, the AC signal in the positive half cycle is transmitted to the positive half cycle through the first diode.
  • bus and negative bus and stored in the capacitor which can specifically include:
  • the first soft start unit When the AC signal provided by the power input terminal is in the positive half cycle, that is, when the first node is at the positive potential and the second node is at the negative potential, within the first preset time period, the first soft start unit first converts the AC signal in the positive half cycle. stored in the first inductor to charge the first inductor to store the electric energy provided by the power input end in the first inductor; within the second preset time period, the first soft-start unit then charges the electric energy stored in the first inductor Transfer the electric energy provided by the power input end to the capacitor through the first diode to charge the capacitor;
  • the AC signal provided by the power input end can be divided, and the time period in the positive half cycle of the AC signal is defined as the first time period, the time period in the negative half cycle of the AC signal is defined as the second time period; within the first time period, multiple first preset time lengths and multiple second preset time lengths can be divided, each first preset time period
  • the duration and each second preset duration are set alternately, for example, the first preset duration, the second preset duration, the first preset duration, the second preset duration... are arranged and set alternately in this way.
  • each first preset time period and each second preset time period are set alternately, and the charging process is performed within the first preset time period, and the discharging process is performed within the second preset time period, so the charging process and the discharging process are The process is carried out alternately, thereby realizing the power factor correction processing of the AC signal in the positive half cycle.
  • the setting of the first preset duration and the second preset duration can be determined based on the relationship between the AC signal provided by the power input terminal and the set carrier signal; for example, the value of the AC signal is greater than or The time period equal to the value of the set positive carrier signal is set as the first preset time length, and the time period during which the value of the AC signal is less than the value of the set positive carrier signal is set as the second preset time length.
  • first preset duration and the second preset duration can also be set in other ways, and are not limited here;
  • each repetition period can be the same, and each repetition period is equally divided to divide the first preset duration. and a second preset duration.
  • the first soft start unit includes: a first transistor and a first thyristor, and the control electrode of the first transistor is electrically connected to the first control signal line, and the gate electrode of the first thyristor is connected to the second control signal line.
  • the first control signal line can provide signals in the following ways:
  • the first control signal line provides the first logic signal
  • the first control signal line provides the second logic signal during both the second preset time period of the first time period and the second time period.
  • the first logic signal may be a high-level signal, and the second logic signal may be a low-level signal; or, the first logic signal may be a low-level signal, and the second logic signal may be a high-level signal; the first The selection of the logic signal and the second logic signal can be determined according to the type of the first transistor.
  • the first transistor when the first transistor is an N-type transistor, within the first preset time period, the first transistor needs to be turned on to form a charging path.
  • the first logic provided by the first control signal line The signal may be a high-level signal to control the N-type first transistor to turn on; during the second preset time period and the entire second time period, the first transistor needs to be turned off.
  • the first control signal line provides the The second logic signal may be a low-level signal to control the N-type first transistor to be turned off;
  • the first transistor When the first transistor is a P-type transistor, within the first preset time period, the first transistor needs to be turned on to form a charging path.
  • the first logic signal provided by the first control signal line may be a low-level signal, so as to The P-type first transistor is controlled to be turned on; during the second preset time period and the entire second time period, the first transistor needs to be turned off.
  • the second logic signal provided by the first control signal line can be a high-level signal. , to control the P-type first transistor to turn off.
  • the second control signal line can provide signals in the following ways:
  • the first thyristor needs to remain in the on state, so the second control signal line can provide a pulse signal during the first time period, and the starting moment of the first time period is at the first Within an effective pulse, so that at the beginning of the first time period, when the positive electrode potential of the first thyristor is higher than the negative electrode potential, driven by the effective pulse applied to the gate, the conduction of the first thyristor can be controlled. pass to facilitate processing of AC signals.
  • the width of the effective pulse is 2 ⁇ s to 10 ⁇ s, and the time interval between two adjacent effective pulses is 2ms; the reason for this setting is:
  • the pulse signal provided when a pulse signal is provided to the gate of the thyristor, the pulse signal provided includes a double pulse signal and a wide pulse signal.
  • the double pulse signal continuously outputs two effective pulses every 70°, and each effective pulse The width is 10°, and the time interval between two consecutive valid pulses is very short, much less than 2ms; this kind of pulse signal may have situations such as no valid pulse output when the AC signal crosses the zero point, resulting in The thyristor may fail to conduct at zero point, which will cause the totem pole PFC circuit to not work properly, further causing the totem pole PFC circuit to experience abnormalities when processing AC signals;
  • the wide pulse signal outputs an effective pulse with a larger pulse width every 70°, making the pulse width of each effective pulse larger. This will cause the gate of the thyristor to be driven most of the time, further causing the thyristor to The consumption increases, causing the reverse recovery current (i.e. leakage current) to increase accordingly, ultimately leading to a reduction in switching frequency;
  • the width of the effective pulse in the pulse signal provided to the gate is 2 ⁇ s to 10 ⁇ s, and the time interval between two adjacent effective pulses is 2 ms.
  • This can avoid the effective pulse having a large width, and thus This avoids the increase in the consumption of the first thyristor and the increase in the reverse recovery current; combined with the fact that the starting moment of the first time period is within the first valid pulse, even when the AC signal crosses the zero point, the gate of the first thyristor will still be applied drive to avoid the situation where the thyristor may not be able to conduct when the AC signal crosses the zero point, thereby maintaining the While ensuring that the totem pole PFC circuit is working properly, the switching frequency can also be increased.
  • the effective pulse provided by the second control signal line can be further set.
  • the rising edge and falling edge of the first effective pulse can be set.
  • the specific setting method can include:
  • the earliest moment among multiple moments when the value of the AC signal in the positive half-cycle is equal to the preset value is aligned with the falling edge of the first valid pulse
  • the latest time among the multiple times when the absolute value of the AC signal in the negative half cycle is equal to the preset value is aligned with the rising edge of the first valid pulse.
  • the preset value can be, but is not limited to, 10V, and of course can also be other values such as 5V, 8V or 13V.
  • the specific value can be set according to actual needs and is not limited here.
  • the switching frequency can be increased while ensuring the normal operation of the totem pole PFC circuit.
  • the width of each effective pulse in the pulse signal provided by the second control signal line can be set to the same, which can reduce the complexity of the provided pulse signal, improve the accuracy of control, and avoid control errors;
  • the width of each effective pulse in the pulse signal provided by the second control signal line can be set to be partially the same.
  • the width of the first effective pulse is larger, and the width of the remaining effective pulses is smaller and the same. This can effectively ensure communication.
  • the soft start module when the soft start module includes: a first inductor, a second inductor, a first soft start unit and a second soft start unit, the AC signal in the negative half cycle is transmitted to the positive through the second diode.
  • bus and negative bus and stored in the capacitor which can specifically include:
  • the second soft start unit When the AC signal provided by the power input terminal is in the negative half cycle, that is, the first node is at the negative potential, and when the second node is at the positive potential, within the third preset time period, the second soft start unit first transmits the AC signal in the negative half cycle. stored in the second inductor to charge the second inductor to store the electric energy provided by the power input end in the second inductor; within the fourth preset time period, the second soft start unit then charges the electric energy stored in the second inductor Transfer the electric energy provided by the power input terminal to the capacitor through the second diode to charge the capacitor;
  • a plurality of third preset time durations and fourth preset time durations may be divided into the second time period, and each third preset time duration and each fourth preset time duration are set alternately, for example, the third preset time duration, the third preset time duration, and the fourth preset time duration.
  • the four preset durations, the third preset duration, the fourth preset duration ...are arranged and set alternately in this way.
  • the third preset time lengths and the fourth preset time lengths are alternately set, and the charging process is performed in the third preset time period, and the discharging process is performed in the fourth preset time period, so the charging process and the discharging process are The process is carried out alternately, thereby realizing the power factor correction processing of the AC signal in the negative half cycle.
  • the setting of the third preset duration and the fourth preset duration can be determined based on the relationship between the AC signal provided by the power input terminal and the set carrier signal; for example, the value of the AC signal is greater than or The time period equal to the set value of the carrier wave signal is set as the third preset time length, and the time period in which the value of the AC signal is less than the set value of the carrier wave signal is set as the fourth preset time length.
  • the third preset duration and the fourth preset duration can also be set in other ways, and are not limited here;
  • each repetition period can be the same, and each repetition period is equally divided to divide the third preset duration. and a fourth preset duration.
  • the second soft start unit includes: a second transistor and a second thyristor, and the control electrode of the second transistor is electrically connected to the third control signal line, and the gate electrode of the second thyristor is connected to the fourth control signal line.
  • the third control signal line can provide signals in the following ways:
  • the third control signal line provides the first logic signal
  • the third control signal line provides the second logic signal during both the fourth preset time period of the second time period and the first time period.
  • the fourth control signal line can provide signals in the following ways:
  • the second thyristor needs to remain in the on state, so the fourth control signal line can provide a pulse signal during the second time period, and the starting moment of the second time period is at the first Within an effective pulse, so that at the beginning of the second time period, when the positive electrode potential of the second thyristor is higher than the negative electrode potential, driven by the effective pulse applied to the gate, the third thyristor can be controlled.
  • the two thyristors are turned on to facilitate the processing of AC signals.
  • the width of the effective pulse is 2 ⁇ s to 10 ⁇ s, and the time interval between two adjacent effective pulses is 2 ms.
  • the width of the effective pulse in the pulse signal provided to the gate is 2 ⁇ s to 10 ⁇ s, and the time interval between two adjacent effective pulses is 2 ms.
  • This can avoid the effective pulse having a large width. , thereby avoiding the increase in consumption of the second thyristor and the increase in reverse recovery current; combined with the fact that the starting moment of the second time period is within the first valid pulse, even when the AC signal crosses the zero point, the gate of the second thyristor will still It is driven to avoid the thyristor being unable to conduct when the AC signal crosses the zero point, thereby ensuring the normal operation of the totem pole PFC circuit and increasing the switching frequency.
  • the effective pulse provided by the fourth control signal line can be further set.
  • the rising edge and falling edge of the first effective pulse can be set.
  • the specific setting method can include:
  • the earliest moment among multiple moments when the absolute value of the AC signal in the negative half cycle is equal to the preset value is aligned with the falling edge of the first valid pulse
  • the latest time among the multiple times when the value of the AC signal in the positive half cycle is equal to the preset value is aligned with the rising edge of the first valid pulse.
  • the preset value can be, but is not limited to, 10V, and of course can also be other values such as 5V, 8V or 13V.
  • the specific value can be set according to actual needs and is not limited here.
  • the switching frequency can be increased while ensuring the normal operation of the totem pole PFC circuit.
  • the width of each effective pulse in the pulse signal provided by the fourth control signal line can be set to the same, which can reduce the complexity of the provided pulse signal, improve control accuracy, and avoid control errors;
  • the width of each effective pulse in the pulse signal provided by the fourth control signal line can be set to be partially the same.
  • the width of the first effective pulse is larger, and the width of the remaining effective pulses is smaller and the same. This can effectively ensure communication.
  • the switching frequency can be at least 100KHz.
  • the sum of the adjacent first preset duration and the second preset duration is at most 10 ⁇ s;
  • the switching frequency of the totem pole PFC circuit is at least 100KHz, which effectively increases the switching frequency of the totem pole PFC circuit and broadens the application range of the totem pole PFC circuit.
  • embodiments of the present application also provide a power supply device, including: a controller, and the above-mentioned totem pole PFC circuit as provided in the embodiment of the present application; the controller is used to: control the totem pole PFC circuit to provide power to the power input end. AC signals are processed.
  • the controller can be electrically connected to the first control signal line, the second control signal line, the third control signal line and the fourth control signal line, and the controller can enable each control signal line to provide a corresponding signal. , to ensure the normal operation of the totem pole PFC circuit while achieving soft start and increasing the switching frequency.
  • the power supply device may also include other structures that can be used to implement the power supply device (for example, but not limited to, an inverter, etc.), which is not limited here. .
  • Figure 1 is a schematic structural diagram of a totem pole PFC circuit in the current technology
  • Figure 2 is a schematic structural diagram of another totem pole PFC circuit in the current technology
  • Figure 3 is a schematic structural diagram of a totem pole PFC circuit provided by an embodiment of the present application.
  • Figure 4 is a specific structural schematic diagram of a totem pole PFC circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a charging circuit provided by an embodiment of the present application.
  • Figure 6 is a schematic diagram of a discharge circuit provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of another charging circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of another discharge circuit provided by an embodiment of the present application.
  • FIG. 9 is a timing diagram provided by an embodiment of the present application.
  • FIG. 10 is another timing diagram provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a power supply device provided by an embodiment of the present application.
  • PFC circuit It is a circuit used for power factor correction.
  • the rectifier bridge of a conventional rectifier filter circuit will only be turned on when the input sine wave voltage is close to the peak value.
  • the input current will be seriously non-sinusoidal, resulting in the generation of a large number of harmonic current components.
  • the harmonic current components also cause interference.
  • the PFC circuit shapes the input AC current into a sine wave that is similar to and in phase with the input voltage, so that the input power is as close to 1 as possible.
  • Boost topologies Most commonly used PFC circuits are Boost topologies. According to the different characteristics of Boost topology in different operating modes (intermittent conduction mode/critical conduction mode/continuous conduction mode), the control methods corresponding to different characteristics can be divided into multiple types. kind.
  • Totem pole PFC circuit The traditional PFC circuit consists of a rectifier bridge plus a Boost PFC circuit, which is composed of two stages, and is therefore called a bridge PFC circuit; in order to further improve efficiency, bridgeless PFC combines the rectifier bridge and the PFC circuit
  • the synthesized single-stage circuit eliminates the loss of the rectifier bridge part and realizes the functions of rectification and power factor correction at the same time, so it is called a bridgeless PFC circuit.
  • the totem pole PFC circuit is a topology with optimal efficiency among bridgeless PFC circuits. It is simpler than other bridgeless PFC circuits and can also be called a totem pole bridgeless PFC circuit.
  • a transistor has a gate, a source and a drain.
  • the source and drain of the transistor can be controlled to be turned on and off, so by Controlling the voltage applied to the gate can control the conduction state of the source and drain of the transistor; this control of the voltage applied to the gate can be understood as soft start.
  • first electrode can be understood as the source electrode
  • second electrode can be understood as the drain electrode
  • first electrode can be understood as the drain electrode
  • second electrode can be understood as the drain electrode
  • It can be understood as the source; the control electrode can be understood as the gate.
  • the totem pole PFC circuit has the characteristics of few moving points in the power loop, a small number of devices, and a small occupied area.
  • the totem pole PFC circuit with this structure cannot achieve soft start.
  • Transistors such as G1 and G2
  • the parasitic diodes have reverse recovery current and large losses, which leads to the switching of the totem pole PFC circuit of this structure. The frequency is lower.
  • the totem pole PFC circuit may include: a first branch, a second branch and a third branch provided between the positive bus Vb+ and the negative bus Vb-.
  • the first branch is provided with There are a first transistor G1 and a second transistor G2 connected in series, a first thyristor SCR1 and a second thyristor SCR2 connected in series are provided in the second branch, and a capacitor C is provided in the third branch;
  • the totem pole PFC circuit also includes Inductor L, the first end of the inductor L (right end as shown in Figure 2) is connected to the connection point A between the first transistor G1 and the second transistor G2 in the first branch, and the second end of the inductor L (such as The left end shown in Figure 2) is electrically connected to the first end (the upper end shown in Figure 2) of the power input terminal AC, and the second end (the lower end shown in Figure 2) of the power input terminal AC is electrically connected to the The connection point B between the first thyristor SCR1 and the second
  • the first terminal of the power input terminal AC is the positive pole and the second terminal is the negative pole.
  • the first transistor G1 and the first thyristor SCR1 are both turned on, and the second transistor G2 and the second thyristor SCR2 are both disconnected, the power input terminal AC, the inductor LL, the first transistor G1 and the first thyristor SCR1 form a charging loop and charge the inductor LL; in the discharge mode: The first thyristor SCR1 continues to be turned on, and the second thyristor SCR2, the first transistor G1 and the second transistor G2 are all turned off.
  • the parasitic diode of the second transistor G2 is higher than the cathode potential, the parasitic diode is turned on.
  • the power input terminal AC, the inductor LL, the parasitic diode of the second transistor G2, the capacitor C, and the first thyristor SCR1 form a discharge circuit, and the electric energy stored in the inductor LL is transferred to the capacitor C to charge the capacitor C;
  • the first terminal of the power input terminal AC is the negative pole and the second terminal is the positive pole.
  • the charging mode the first transistor G1 and the first thyristor SCR1 are both turned off, and the second transistor G2 and the second thyristor SCR2 are all turned on, the power input terminal AC, the second thyristor SCR2, the second transistor G2, and the inductor LL form a charging loop and charge the inductor LL;
  • the discharge mode the second thyristor SCR2 continues to be turned on, and the second thyristor SCR2 continues to be turned on.
  • a thyristor SCR1 the first transistor G1 and the second transistor G2 are all turned off, but because the anode potential of the parasitic diode of the first transistor G1 is higher than the cathode potential, the parasitic diode is turned on, and the power input terminal AC and the second thyristor SCR2 , the capacitor C, the parasitic diode of the first transistor G1, and the inductor LL form a discharge loop, and the electric energy stored in the inductor LL is transferred to the capacitor C to charge the capacitor C.
  • the AC signal provided by the power input terminal AC is converted into a DC signal and transmitted to the positive bus Vb+ and the negative bus Vb- to realize signal conversion.
  • the first thyristor SCR1 and the second thyristor SCR2 are used to achieve digital inrush current limit and soft start at the same time; however, the first transistor G1 and the second thyristor SCR2
  • transistors G2 are all silicon-based transistors
  • the parasitic diodes in the silicon-based transistors are silicon-based diodes, and silicon-based diodes have reverse recovery currents and large losses. This results in the switching frequency of the totem pole PFC circuit with this structure being relatively high. Low.
  • Embodiments of the present application provide a totem pole PFC circuit, its control method and power supply device.
  • the totem pole PFC circuit can be applied to energy storage equipment (such as but not limited to batteries) and uninterrupted current usage scenarios, and is set in the power grid. With the electrical equipment, the AC power provided by the grid is rectified and power factor corrected and then output to the electrical equipment to facilitate the use of the electrical equipment.
  • the totem pole PFC circuit includes a soft start module 10, a first diode D1, a second diode D2 and a capacitor C.
  • the soft start module 10 passes through the A diode D1 is electrically connected to the positive bus Vb+, and is electrically connected to the negative bus Vb- through a second diode D2; and, the soft start module 10 is also respectively connected to the positive bus Vb+, the negative bus Vb- and the power input terminal AC. electrical connection;
  • the soft start module 10 can transmit the AC signal in the positive half cycle to the positive bus Vb+ and the negative bus Vb- through the first diode D1, and is stored in the capacitor C between the positive bus Vb+ and the negative bus Vb-; when the AC signal provided by the power input terminal AC is in the negative half cycle, the soft start module 10 can pass the second diode D2 to change the AC signal in the negative half cycle.
  • the AC signal is transmitted to the positive bus Vb+ and the negative bus Vb-, and is also stored in the capacitor C located between the positive bus Vb+ and the negative bus Vb-.
  • the soft start module the first diode and the second diode, the rectification effect on the AC signal provided by the power input end is realized, and the AC signal is adjusted into a DC signal and then output.
  • the adjusted DC signal can power the load to ensure that the load works under the power supply.
  • the AC signal is transmitted through the first diode and the second diode, rather than through the parasitic diode of the transistor as in the prior art, because the first diode and the second diode are both Silicon carbide-based diodes, and silicon carbide-based diodes have the characteristics of small loss and no reverse recovery current.
  • the parasitic diodes of transistors are also silicon-based diodes, because silicon-based diodes have reverse
  • the reverse recovery current is high and the loss is high, so using silicon carbide-based diodes can eliminate the reverse recovery current and reduce losses, thereby increasing the switching frequency of the totem pole PFC circuit.
  • the totem pole PFC circuit provided in the embodiment of the present application can realize soft start and increase the switching frequency at the same time.
  • the soft start module 10 may include: a first inductor L1, a second inductor L2, a first soft start unit 11 and a second soft start unit. 12.
  • the first end of the power input terminal AC (the upper end as shown in the figure) is connected to the first node P1, and the second end of the power input terminal AC (the lower end as shown in the figure) is connected to the second node P2; in the power supply
  • the first node P1 is at the positive potential and the second node P2 is at the negative potential;
  • the first node P1 is at the negative potential.
  • the second node P2 is at a positive potential;
  • connection point between the first diode D1 and the first soft-start unit 11 is the third node P3;
  • connection point between the second diode D2 and the second soft-start unit 12 is the fourth node P4.
  • the first inductor L1 is connected between the first node P1 and the third node P3, that is, the first end of the first inductor L1 (ie, the left end shown in the figure) is electrically connected to the first node P1, and the first end of the first inductor L1
  • the second end i.e., the right end shown in the figure is electrically connected to the third node P3;
  • the first soft start unit 11 is electrically connected to the second node P2, the third node P3, and the negative bus Vb- respectively;
  • the first soft start unit 11 when the AC signal provided by the power input terminal AC is in the positive half cycle, that is, when the first node P1 is at a positive potential and the second node P2 is at a negative potential, within the first preset time period, the first soft start unit 11 will be at
  • the AC signal of the positive half cycle is stored in the first inductor L1, charging the first inductor L1, so that the electric energy provided by the power input terminal AC is stored in the first inductor L1, so that the first end of the first inductor L1 (i.e.
  • the first soft The starting unit 11 transfers the electric energy stored in the first inductor L1 to the capacitor C through the first diode D1, and charges the capacitor C, so as to transfer the electric energy provided by the power input terminal AC into the capacitor C, so that the first inductor L1
  • the first end that is, the left end shown in the figure, that is, the first node P1) is at a negative potential
  • the second end that is, the right end shown in the figure, that is, the third node P3 is at a positive potential.
  • the first preset duration and the second preset duration alternately occur at least once, thereby causing the electric energy to be intermittently transferred to the capacitor C and realizing power factor correction of the AC signal in the positive half cycle.
  • the second inductor L2 is connected between the first node P1 and the fourth node P4, that is, the first end of the second inductor L2 (ie, the left end shown in the figure) is electrically connected to the first node P1, and the second inductor L2 The second end (i.e., the right end shown in the figure) is electrically connected to the fourth node P4;
  • the second soft start unit 12 is electrically connected to the second node P2, the fourth node P4, and the positive bus Vb+ respectively;
  • the second soft start unit 12 when the AC signal provided by the power input terminal AC is in the negative half cycle, that is, when the first node P1 is at a negative potential and the second node P2 is at a positive potential, within the third preset time period, the second soft start unit 12 will be at
  • the AC signal of the negative half cycle is stored in the second inductor L2 to charge the second inductor L2, so that the electric energy provided by the power input terminal AC is stored in the second inductor L2, so that the first end of the second inductor L2 (i.e.
  • the left end shown in the figure, that is, the first node P1) is at a negative potential
  • the second end that is, the right end shown in the figure, that is, the fourth node P4 is at a positive potential
  • the second soft The starting unit 12 transfers the electric energy stored in the second inductor L2 to the capacitor C through the second diode D2, charges the capacitor C, and transfers the electric energy provided by the power input terminal AC into the capacitor C, so that the second inductor L2
  • the first end that is, the left end shown in the figure, that is, the first node P1) is at a positive potential
  • the second end that is, the right end shown in the figure, that is, the fourth node P4 is at a negative potential.
  • the third preset duration and the fourth preset duration alternately occur at least once, thereby causing the electric energy to be intermittently transferred to the capacitor C and realizing power factor correction of the AC signal in the negative half cycle. deal with.
  • the function of the soft start module can be realized. Regardless of whether the AC signal provided by the power input terminal is in the negative half cycle or the positive half cycle, the electric energy can be stored in the corresponding in the inductor and then transferred to the capacitor to process the AC signal provided by the power input end.
  • the switching of the totem pole PFC circuit with soft start function is improved. frequency.
  • the first soft start unit 11 can be set to:
  • the first soft start unit 11 includes: a first transistor G1 and a first thyristor SCR1, where:
  • the first electrode of the first transistor G1 is electrically connected to the third node P3 (that is, the first electrode is electrically connected to the anode of the first inductor L1 and the first diode D1 respectively), and the second electrode of the first transistor G1 is respectively connected to the anode of the first inductor L1 and the first diode D1.
  • the negative bus Vb- is electrically connected to the positive electrode of the first thyristor SCR1, and the control electrode of the first transistor G1 is electrically connected to the first control signal line k1;
  • the cathode of the first thyristor SCR1 is electrically connected to the second end of the power input terminal AC (that is, the second node P2), and the gate of the first thyristor SCR1 is electrically connected to the second control signal line k2.
  • the first control signal line k1 can control the first transistor G1 to turn on, and the second control signal line k2 can control the first thyristor SCR1 to turn on, so that the first inductor L1 and the first transistor G1 , the first thyristor SCR1 and the power input terminal AC can form a charging loop, as shown by the loop indicated by the dotted arrow in Figure 5, which stores the AC signal in the positive half cycle into the first inductor L1; within the second preset time period, the A control signal line k1 can control the first transistor G1 to turn off, and the second control signal line k2 continues to keep the first thyristor SCR1 turned on, so that the first inductor L1, the first diode D1, the capacitor C, and the first thyristor SCR1 and the power input terminal AC can form a discharge loop, such as the loop indicated by the dotted arrow in Figure 6, which transfers the electric energy stored in the first inductor L1 to
  • the second soft start unit 12 can be set to:
  • the second soft start unit 12 includes: a second transistor G2 and a second thyristor SCR2, where:
  • the first electrode of the second transistor G2 is electrically connected to the fourth node P4 (that is, the first electrode is electrically connected to the negative electrode of the second inductor L2 and the second diode D2 respectively), and the second electrode of the second transistor G2 is respectively connected to the negative electrode of the second inductor L2 and the second diode D2.
  • the positive bus Vb+ is electrically connected to the negative electrode of the second thyristor SCR2, and the control electrode of the second transistor G2 is electrically connected to the third control signal line k3;
  • the anode of the second thyristor SCR2 is electrically connected to the second end of the power input AC (that is, the second node P2), and the gate of the second thyristor SCR2 is electrically connected to the fourth control signal line k4.
  • the third control signal line k3 can control the second transistor G2 to turn on, and the fourth control signal line k4 can control the second thyristor SCR2 to turn on, so that the second inductor L2 and the second transistor G2 , the second thyristor SCR2 and the power input AC can form a charging loop, as shown by the dotted arrow in Figure 7, which stores the AC signal in the negative half cycle into the second inductor L2; within the fourth preset time period, the The third control signal line k3 can control the second transistor G2 to turn off, and the fourth control signal line k4 continues to keep the second thyristor SCR2 turned on, so that the second inductor L2, the second diode D2, the capacitor C, and the second thyristor SCR2 and the power input terminal AC can form a discharge loop, such as the loop indicated by the dotted arrow in Figure 8, to transfer the electric energy stored in the second inductor L2 to the capacitor C,
  • the first transistor G1 has a parasitic diode, the anode of the parasitic diode is electrically connected to the negative bus Vb-, and the cathode is electrically connected to the third node P3; the first transistor G1 is silicon-based When using a diode, the parasitic diode is also a silicon-based diode, and if current passes through the silicon-based diode, the silicon-based diode is prone to generate reverse recovery current;
  • the silicon carbide-based diode Since the electric energy is transferred to the capacitor C through the first diode D1 within the second preset time period, and the first diode D1 is a silicon carbide-based diode, the silicon carbide-based diode has no reverse recovery current; and, at the Within the preset time period, when the first inductor L1, the first diode D1, the capacitor C, the first thyristor SCR1 and the power input terminal AC form a discharge loop (the loop indicated by the dotted arrow in Figure 6), due to the The anode potential of the parasitic diode of a transistor G1 is smaller than the cathode potential, so that the current in the discharge circuit does not pass through the parasitic diode; based on this, there is no reverse recovery current within the second preset time period.
  • the second transistor G2 also has a parasitic diode.
  • the cathode of the parasitic diode is electrically connected to the positive bus Vb+, and the anode is electrically connected to the fourth node P4;
  • the parasitic diode is also a silicon-based diode, and if current passes through the silicon-based diode, the silicon-based diode is prone to generate reverse recovery current;
  • the silicon carbide-based diode Since electric energy is transferred to the capacitor C through the second diode D2 within the fourth preset time period, and the second diode D2 is a silicon carbide-based diode, the silicon carbide-based diode has no reverse recovery current; and, in the fourth preset time period, the second diode D2 is a silicon carbide-based diode.
  • the charging process and the discharging process can be switched quickly and effectively, thereby effectively increasing the switching frequency of the totem pole PFC circuit.
  • the manufacturing process of silicon-based transistors is relatively mature and the manufacturing cost is low.
  • the combination of silicon-based transistors and silicon carbide-based diodes can effectively increase the switching frequency of totem pole PFC circuits while also reducing the manufacturing cost of totem pole PFC circuits. cost and improve the manufacturing yield of totem pole PFC circuits.
  • control method is such as the above-mentioned totem pole PFC circuit provided by the embodiment of the present application.
  • the control method may include:
  • the soft start module can transmit the AC signal in the positive half cycle to the positive bus and the negative bus through the first diode, and store it in the positive bus and the negative bus. in the capacitance between them; when the AC signal provided by the power input terminal is in the negative half cycle, the soft start module can transmit the AC signal in the negative half cycle to the positive bus and the negative bus through the second diode, and also store it in Located in the capacitor between the positive and negative buses.
  • the soft start module the first diode and the second diode, the rectification effect on the AC signal provided by the power input end is realized, and the AC signal is adjusted into a DC signal and then output.
  • the AC signal is transmitted through the first diode and the second diode, rather than through the parasitic diode of the transistor as in the prior art, because the first diode and the second diode are both Silicon carbide-based diodes, and silicon carbide-based diodes have the characteristics of small loss and no reverse recovery current.
  • the parasitic diodes of transistors are also silicon-based diodes, because silicon-based diodes have reverse
  • the reverse recovery current is high and the loss is high, so using silicon carbide-based diodes can eliminate the reverse recovery current and reduce losses, thereby increasing the switching frequency of the totem pole PFC circuit.
  • the totem pole PFC circuit provided in the embodiment of the present application can realize soft start and increase the switching frequency at the same time.
  • control method provided by the embodiment of the present application is described in detail below based on the AC signal of the positive half cycle and the AC signal of the negative half cycle respectively.
  • the soft start module 10 when the soft start module 10 includes: a first inductor L1 , a second inductor L2 , a first soft start unit 11 and a second soft start unit 12 .
  • Diode D1 transmits the AC signal in the positive half cycle to the positive bus Vb+ and the negative bus Vb-, and stores it in the capacitor C. It can specifically include:
  • the first soft start Unit 11 When the AC signal provided by the power input terminal AC is in the positive half cycle, that is, when the first node P1 shown in Figure 4 is at a positive potential and the second node P2 is at a negative potential, within the first preset time period, the first soft start Unit 11 first stores the AC signal in the positive half cycle into the first inductor L1 and charges the first inductor L1 to store the electric energy provided by the power input terminal AC in the first inductor L1; within the second preset time period, The first soft-start unit 11 then transfers the electric energy stored in the first inductor L1 to the capacitor C through the first diode D1, charging the capacitor C, so as to transfer the electric energy provided by the power input terminal AC into the capacitor C;
  • the AC signal Vac provided by the power input terminal AC can be divided.
  • the time period in the positive half cycle of the AC signal Vac is defined as the first time period T1
  • the period of the AC signal Vac in the negative half cycle is defined as the first time period T1.
  • the time period is defined as the second time period T2; within the first time period T1, a plurality of first preset time lengths t1 and a plurality of second preset time lengths t2 can be divided, each first preset time length t1 and each second preset time period t2.
  • the duration t2 is alternately set, for example, the first preset duration t1, the second preset duration t2, the first preset duration t1, the second preset duration t2... are arranged alternately in this way.
  • each first preset time period and each second preset time period are set alternately, and the charging process is performed within the first preset time period, and the discharging process is performed within the second preset time period, so the charging process and the discharging process are The process is carried out alternately, thereby realizing the power factor correction processing of the AC signal in the positive half cycle.
  • the setting of the first preset duration and the second preset duration can be determined based on the relationship between the AC signal provided by the power input terminal and the set carrier signal; for example, the value of the AC signal is greater than or The time period equal to the value of the set positive carrier signal is set as the first preset time length, and the time period during which the value of the AC signal is less than the value of the set positive carrier signal is set as the second preset time length.
  • first preset duration and the second preset duration can also be set in other ways, and are not limited here;
  • each repetition period can be the same, and each repetition period is equally divided to divide the first preset duration. and a second preset duration.
  • the first soft start unit 11 includes: a first transistor G1 and a first thyristor SCR1, and the control electrode of the first transistor G1 is electrically connected to the first control signal line k1 , when the gate of the first thyristor SCR1 is electrically connected to the second control signal line k2, then:
  • the first control signal line can provide signals in the following ways:
  • the first control signal line provides the first logic signal
  • the first control signal line provides the second logic signal during both the second preset time period of the first time period and the second time period.
  • the first logic signal may be a high-level signal, and the second logic signal may be a low-level signal; or, the first logic signal may be a low-level signal, and the second logic signal may be a high-level signal; the first The selection of the logic signal and the second logic signal can be determined according to the type of the first transistor.
  • the first transistor when the first transistor is an N-type transistor, within the first preset time period, the first transistor needs Turn on to form a charging circuit.
  • the first logic signal provided by the first control signal line can be a high-level signal to control the N-type first transistor to turn on; during the second preset time period and the entire second time period , the first transistor needs to be turned off.
  • the second logic signal provided by the first control signal line can be a low-level signal to control the N-type first transistor to be turned off;
  • the first transistor When the first transistor is a P-type transistor, within the first preset time period, the first transistor needs to be turned on to form a charging path.
  • the first logic signal provided by the first control signal line may be a low-level signal, so as to The P-type first transistor is controlled to be turned on; during the second preset time period and the entire second time period, the first transistor needs to be turned off.
  • the second logic signal provided by the first control signal line can be a high-level signal. , to control the P-type first transistor to turn off.
  • the curve indicated by Vac represents the AC signal provided by the power input terminal AC
  • VcarrA represents the positive carrier signal
  • T1 represents The first time period
  • T2 represents the second time period
  • the value of the AC signal Vac (referring to the value at any time within t1) is greater than or equal to the value of the positive carrier signal VcarrA, and the first control signal line k1 provides a high-level signal within t1, so that The first transistor G1 is turned on within t1 to form a charging loop so as to store the AC signal Vac in the positive half cycle into the first inductor L1; at this time, t1 is the first preset time length;
  • the value of the AC signal Vac (referring to the value at any time within t2) is smaller than the value of the positive carrier signal VcarrA, and the first control signal line k1 provides a low-level signal within t2, so that the first The transistor G1 is turned off within t2, so that the electric energy stored in the first inductor L1 is transferred to the capacitor C through the first diode D1; at this time, t2 is the second preset time length; and, within T1, t1 and t2 appears alternately;
  • the first control signal line k1 always provides a low-level signal in T2 to determine that the first transistor G1 remains turned off in T2.
  • Figure 9 shows the current change trend of the first inductor, as shown in iL1, and iL1 is similar to the change trend of the AC signal Vac (can be understood as AC voltage) in the positive half cycle, realizing the change of the AC signal Vac The following effect.
  • the second control signal line can provide signals in the following ways:
  • the first thyristor SCR1 needs to remain on, so the second control signal line k2 can provide a pulse signal during the first time period T1.
  • the starting moment of a period of time T1 is within the first effective pulse, so that at the starting moment of the first period of time T1, when the positive electrode potential of the first thyristor SCR1 is higher than the negative electrode potential, when the voltage applied to the gate Driven by effective pulses, the first thyristor SCR1 can be controlled to be turned on so as to process the AC signal Vac.
  • the width of the effective pulse is 2 ⁇ s to 10 ⁇ s, and the time interval between two adjacent effective pulses is 2ms; the reason for this setting is:
  • the pulse signal provided when a pulse signal is provided to the gate of the thyristor, the pulse signal provided includes a double pulse signal and a wide pulse signal.
  • the double pulse signal continuously outputs two effective pulses every 70°, and each effective pulse The width is 10°, and the time interval between two consecutive valid pulses is actually very short, much less than 2ms; this kind of pulse signal may have situations such as no valid pulse output when the AC signal crosses the zero point, causing the AC signal to When the zero point is crossed, the thyristor may fail to conduct, which will cause the totem pole PFC circuit to not work properly, further causing the totem pole PFC circuit to have abnormalities when processing AC signals;
  • the wide pulse signal outputs an effective pulse with a larger pulse width every 70°, making the pulse width of each effective pulse larger. This will cause the gate of the thyristor to be driven most of the time, further causing the thyristor to The consumption increases, causing the reverse recovery current (i.e. leakage current) to increase accordingly, ultimately leading to a reduction in switching frequency;
  • the width of the effective pulse in the pulse signal provided to the gate is 2 ⁇ s to 10 ⁇ s, and the time interval between two adjacent effective pulses is 2 ms.
  • This can avoid the effective pulse having a large width, and thus This avoids the increase in the consumption of the first thyristor and the increase in the reverse recovery current; combined with the fact that the starting moment of the first time period is within the first valid pulse, even when the AC signal crosses the zero point, the gate of the first thyristor will still be applied Drive to avoid the thyristor failure to conduct when the AC signal crosses the zero point, thereby ensuring the normal operation of the totem pole PFC circuit and increasing the switching frequency.
  • the effective pulse provided by the second control signal line can be further set.
  • the rising edge and falling edge of the first effective pulse can be set.
  • the specific setting method can include:
  • the earliest moment among multiple moments when the value of the AC signal in the positive half-cycle is equal to the preset value is aligned with the falling edge of the first valid pulse
  • the latest time among the multiple times when the absolute value of the AC signal in the negative half cycle is equal to the preset value is aligned with the rising edge of the first valid pulse.
  • the preset value can be, but is not limited to, 10V. Of course, it can also be other values such as 5V, 8V or 13V. The specific value can be determined according to the actual situation. Actual settings need to be made and are not limited here.
  • the default value is V0/2.
  • the value of the AC signal Vac of the left positive half cycle is equal to V0/2, one is at the beginning of the left positive half cycle, and the other is on the left side.
  • the time corresponding to the value at the beginning of the left positive half cycle is earlier than the time corresponding to the value at the end of the left positive half cycle, so the time corresponding to the value at the beginning of the left positive half cycle can be compared with the time corresponding to the value at the end of the left positive half cycle.
  • the falling edge of a valid pulse is aligned;
  • the figure only shows one positive half-cycle AC signal Vac and one negative half-cycle AC signal Vac, in actual situations, the length of the AC signal Vac is not limited to this.
  • the left side and the right side of the negative half cycle shown in the figure both have the AC signal Vac exactly the same as the waveform shown in the figure, but it is not shown in the figure;
  • the right negative half-cycle AC signal Vac located after the AC signal Vac of the right negative half-cycle
  • the right negative half-cycle AC signal Vac is adjacent to and before the positive half-cycle AC signal Vac after it
  • the right negative half-cycle AC signal Vac There are also two moments when the absolute value of Vac is equal to V0/2. One is at the beginning of the negative half cycle on the right, and the other is at the end of the negative half cycle on the right. Obviously, the value at the beginning of the negative half cycle on the right corresponds to a moment earlier than the moment at the beginning of the negative half cycle on the right. The time corresponding to the value at the end of the right negative half cycle, so the time corresponding to the value at the end of the right negative half cycle can be aligned with the rising edge of the first valid pulse.
  • the switching frequency can be increased while ensuring the normal operation of the totem pole PFC circuit.
  • the width of each effective pulse in the pulse signal provided by the second control signal line k2 can be set to the same, as shown in Figure 9, which can reduce the complexity of the provided pulse signal and improve the control accuracy. , to avoid control errors;
  • the width of each effective pulse in the pulse signal provided by the second control signal line k2 can be set to be partially the same. As shown in Figure 10, the width of the first effective pulse is larger, and the width of the remaining effective pulses is smaller. Similarly, this can effectively ensure that the gate of the first thyristor SCR1 is driven when the AC signal Vac crosses zero, ensuring that the first thyristor SCR1 is in a conductive state when the zero crosses, thereby ensuring the normal operation of the totem pole PFC circuit.
  • the soft start module 10 when the soft start module 10 includes: the first inductor L1, the second inductor L2, the first soft start unit 11 and the second soft start unit 12, through the second diode D2, it will be in the negative half cycle.
  • the AC signal is transmitted to the positive bus Vb+ and the negative bus Vb-, and stored in the capacitor C, which can specifically include:
  • the second soft start The unit 12 first stores the AC signal in the negative half cycle into the second inductor L2 and charges the second inductor L2 to store the electric energy provided by the power input terminal AC in the second inductor L2; within the fourth preset time period, The second soft-start unit 12 then transfers the electric energy stored in the second inductor L2 to the capacitor C through the second diode D2, charging the capacitor C, so as to transfer the electric energy provided by the power input terminal AC into the capacitor C;
  • a plurality of third preset time lengths t3 and fourth preset time lengths t4 can be divided, and each third preset time length t3 and each fourth preset time length t4 alternate.
  • Settings, for example, the third preset time length t3, the fourth preset time length t4, the third preset time length t3, the fourth preset time length t4... are arranged and set alternately in this way.
  • the third preset time lengths and the fourth preset time lengths are alternately set, and the charging process is performed in the third preset time period, and the discharging process is performed in the fourth preset time period, so the charging process and the discharging process are The process is carried out alternately, thereby realizing the power factor correction processing of the AC signal in the negative half cycle.
  • the setting of the third preset duration and the fourth preset duration can be determined based on the relationship between the AC signal provided by the power input terminal and the set carrier signal; for example, the value of the AC signal is greater than or The time period equal to the set value of the carrier wave signal is set as the third preset time length, and the time period in which the value of the AC signal is less than the set value of the carrier wave signal is set as the fourth preset time length.
  • the third preset duration and the fourth preset duration can also be set in other ways, and are not limited here;
  • each repetition period can be the same, and each repetition period is equally divided to divide the third preset duration. and a fourth preset duration.
  • the second soft start unit 12 includes: a second transistor G2 and a second thyristor SCR2, and the control electrode of the second transistor G2 is electrically connected to the third control signal line k3 , when the gate of the second thyristor SCR2 is electrically connected to the fourth control signal line k4, then:
  • the third control signal line can provide signals in the following ways:
  • the third control signal line provides the first logic signal
  • the third control signal line provides the second logic signal during both the fourth preset time period of the second time period and the first time period.
  • VcarrB represents the load wave signal
  • the value of the AC signal Vac (referring to the value at any time within t3) is greater than or equal to the value of the load wave signal VcarrB, and the third control signal line k3 provides a high-level signal within t3, so that The second transistor G2 is turned on during t3 to form a charging loop so as to store the AC signal Vac in the negative half cycle into the second inductor L2; at this time, t3 is the third preset time length;
  • the value of the AC signal Vac (referring to the value at any time in t4) is smaller than the value of the load wave signal VcarrB.
  • the third control signal line k3 provides a low-level signal in t4, so that the second The transistor G2 is turned off within t4, so that the electric energy stored in the second inductor L2 is transferred to the capacitor C through the second diode D2; at this time, t4 is the fourth preset time length; and, within T2, t3 and t4 appears alternately;
  • the third control signal line k3 always provides a low-level signal in T1 to determine that the second transistor G2 remains turned off in T1.
  • Figure 9 shows the current change trend of the second inductor, as shown in iL2, and iL2 is similar to the change trend of the AC signal Vac (which can be understood as the AC voltage) in the negative half cycle, realizing the change of the AC signal Vac The following effect.
  • the fourth control signal line can provide signals in the following ways:
  • the second thyristor SCR2 needs to remain on, so the fourth control signal line k4 can provide a pulse signal during the second time period T2.
  • the starting moment of the second period T2 is within the first valid pulse, so that at the starting moment of the second period T2, when the positive electrode potential of the second thyristor SCR2 is higher than the negative electrode potential, when the voltage applied to the gate Driven by effective pulses, the second thyristor SCR2 can be controlled to be turned on, so as to process the AC signal Vac.
  • the width of the effective pulse is 2 ⁇ s to 10 ⁇ s, and the time interval between two adjacent effective pulses is 2ms; the reason for this setting is:
  • the pulse signal provided when a pulse signal is provided to the gate of the thyristor, the pulse signal provided includes a double pulse signal and a wide pulse signal.
  • the double pulse signal continuously outputs two effective pulses every 70°, and each effective pulse The width is 10°, and the time interval between two consecutive valid pulses is very short, much less than 2ms; this kind of pulse signal may have situations such as no valid pulse output when the AC signal crosses the zero point, resulting in The thyristor may fail to conduct at zero point, which will cause the totem pole PFC circuit to not work properly, further causing the totem pole PFC circuit to experience abnormalities when processing AC signals;
  • the wide pulse signal outputs an effective pulse with a larger pulse width every 70°, making the pulse width of each effective pulse larger. This will cause the gate of the thyristor to be driven most of the time, further causing the thyristor to The consumption increases, causing the reverse recovery current (i.e. leakage current) to increase accordingly, ultimately leading to a reduction in switching frequency;
  • the width of the effective pulse in the pulse signal provided to the gate is 2 ⁇ s to 10 ⁇ s, and the time interval between two adjacent effective pulses is 2 ms.
  • This can avoid the effective pulse having a large width, and thus This avoids the increase in the consumption of the second thyristor and the increase in the reverse recovery current; combined with the fact that the starting moment of the second time period is within the first valid pulse, even when the AC signal crosses the zero point, the gate of the second thyristor will still be applied Drive to avoid the thyristor failure to conduct when the AC signal crosses the zero point, thereby ensuring the normal operation of the totem pole PFC circuit and increasing the switching frequency.
  • the effective pulse provided by the fourth control signal line can be further set.
  • the rising edge and falling edge of the first effective pulse can be set.
  • the specific setting method can include:
  • the earliest moment among multiple moments when the absolute value of the AC signal in the negative half cycle is equal to the preset value is aligned with the falling edge of the first valid pulse
  • the latest time among the multiple times when the value of the AC signal in the positive half cycle is equal to the preset value is aligned with the rising edge of the first effective pulse.
  • the preset value can be, but is not limited to, 10V, and of course can also be other values such as 5V, 8V or 13V.
  • the specific value can be set according to actual needs and is not limited here.
  • the default value is V0/2.
  • the absolute value of the AC signal Vac of the right negative half cycle is equal to V0/2, one is at the beginning of the right negative half cycle, and the other is at the right At the end of the negative half cycle on the right side, it is obvious that the time corresponding to the value located at the beginning of the negative half cycle on the right is earlier than the time corresponding to the value located at the end of the negative half cycle on the right side, so the time corresponding to the value located at the beginning of the negative half cycle on the right side can be The moment is aligned with the falling edge of the first valid pulse;
  • the figure only shows one positive half-cycle AC signal Vac and one negative half-cycle AC signal Vac, in actual situations, the length of the AC signal Vac is not limited to this.
  • the left side and the right side of the negative half cycle shown in the figure both have the AC signal Vac exactly the same as the waveform shown in the figure, but it is not shown in the figure;
  • the AC signal Vac of the left positive half cycle is adjacent to and before the AC signal Vac of the right negative half cycle. Therefore, there are also two moments when the absolute value of the left positive half cycle AC signal Vac is equal to V0/2. , one is located at the beginning of the left positive half cycle, and the other is the end of the left positive half cycle. Obviously, the value corresponding to the beginning of the left positive half cycle is earlier than the time corresponding to the value located at the end of the left positive half cycle, so it can Align the moment corresponding to the value at the end of the left positive half cycle with the rising edge of the first valid pulse.
  • the switching frequency can be increased while ensuring the normal operation of the totem pole PFC circuit.
  • the width of each effective pulse in the pulse signal provided by the fourth control signal line k4 can be set to the same, as shown in Figure 9, which can reduce the complexity of the provided pulse signal and improve the control accuracy. , to avoid control errors;
  • the width of each effective pulse in the pulse signal provided by the fourth control signal line k4 can be set to be partially the same. As shown in Figure 10, the width of the first effective pulse is larger, and the width of the remaining effective pulses is smaller. Similarly, this can effectively ensure that the gate of the second thyristor SCR2 is driven when the AC signal Vac crosses zero, ensuring that the second thyristor SCR2 is in a conductive state when the zero crosses, thereby ensuring the normal operation of the totem pole PFC circuit.
  • the switching frequency can be at least 100KHz.
  • the sum of the adjacent first preset duration and the second preset duration is at most 10 ⁇ s;
  • the switching frequency of the totem pole PFC circuit is at least 100KHz, which effectively increases the switching frequency of the totem pole PFC circuit and broadens the application range of the totem pole PFC circuit.
  • the embodiment of this application uses thyristors, transistors, diodes, inductors and capacitors to construct a totem pole PFC circuit, which can not only achieve soft start, but also increase the switching frequency;
  • this totem pole PFC circuit uses thyristors, it can realize digital surge current limitation, which helps to remove the structure of using relays and resistors to achieve the soft-start function in the traditional solution, simplifying the complexity of the structure and reducing Reduces the size of the totem pole PFC circuit;
  • the thyristor has the characteristics of fast startup speed.
  • the startup speed is at the ms level, which can realize the rapid startup of the totem pole PFC circuit and is conducive to further increasing the switching frequency of the totem pole PFC circuit;
  • the thyristor has good anti-electromagnetic interference performance, so that the totem pole PFC circuit has good electromagnetic compatibility, which can broaden the application of the totem pole PFC circuit in some special fields (such as the military field).
  • an embodiment of the present application also provides a power supply device, as shown in Figure 11, including: a controller 101, and the above-mentioned totem pole PFC circuit 102 provided in the embodiment of the present application;
  • the controller 101 is used to control the totem pole PFC circuit 102 to process the AC signal provided by the power input terminal AC.
  • the controller 101 may be electrically connected to the first control signal line k1, the second control signal line k2, the third control signal line k3 and the fourth control signal line k4, through the controller 101 can enable each control signal line to provide corresponding signals to ensure the normal operation of the totem pole PFC circuit 102 while achieving soft start and increasing the switching frequency.
  • the power supply device may also include other structures that can be used to implement the power supply device (for example, but not limited to, an inverter, etc.), which is not limited here. .

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Abstract

一种图腾柱PFC电路、控制方法及电源装置，在电源输入端提供的交流信号处于正半周时，软启动模块(10)通过第一二极管，将处于正半周的交流信号传输至电容中；在交流信号处于负半周时，软启动模块(10)通过第二二极管，将处于负半周的交流信号传输至电容中。由于第一二极管和第二二极管均为碳化硅基二极管，且碳化硅基二极管具有损耗小、无反向恢复电流的特点，所以可以消除图腾柱PFC电路的反向恢复电流，降低损耗，提高开关频率。结合软启动模块(10)的软启动功能，该图腾柱PFC电路可以在实现软启动的同时，提高开关频率。

Description

一种图腾柱PFC电路、其控制方法及电源装置
相关申请的交叉引用
本申请要求在2022年09月09日提交中国专利局、申请号为202211103710.8、申请名称为“一种图腾柱PFC电路、其控制方法及电源装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电路控制技术领域，尤其涉及一种图腾柱PFC电路、其控制方法及电源装置。
背景技术
无桥PFC(Power Factor Correction，功率因数校正)电路包括多种类型，其中一种类型为图腾柱PFC，具体结构如图1所示，该种结构的图腾柱PFC电路具有功率回路动点少、器件数量少、占用面积小等特点，然而该种结构的图腾柱PFC电路无法实现软启动，同时由于晶体管(如G1和G2)存在寄生二极管(如图1中虚线框内所示的结构)，且寄生二极管存在反向恢复电流，且损耗较大，这样导致该种结构的图腾柱PFC电路的开关频率较低。
发明内容
本申请提供了一种图腾柱PFC电路、其控制方法及电源装置，用以提高具有软启动功能的图腾柱PFC电路的开关频率。
第一方面，本申请实施例提供了一种图腾柱PFC电路，该图腾柱PFC电路包括软启动模块、第一二极管、第二二极管和电容，其中，软启动模块通过第一二极管与正母线电连接，以及通过第二二极管与负母线电连接；并且，软启动模块还分别与正母线、负母线和电源输入端电连接；
这样，在电源输入端提供的交流信号处于正半周时，软启动模块可以通过第一二极管，将该处于正半周的交流信号传输至正母线和负母线中，并存储至位于正母线和负母线之间的电容中；在电源输入端提供的交流信号处于负半周时，软启动模块可以通过第二二极管，将该处于负半周的交流信号传输至正母线和负母线中，同样存储至位于正母线和负母线之间的电容中。
如此，通过软启动模块、第一二极管和第二二极管，实现了对电源输入端提供的交流信号的整流作用，将该交流信号调整为直流信号后输出。
并且，交流信号是通过第一二极管和第二二极管传输的，而并不是像现有技术那样通过晶体管的寄生二极管传输的，由于第一二极管和第二二极管均为碳化硅基二极管，且碳化硅基二极管具有损耗小、无反向恢复电流的特点，而目前常用的晶体管均为硅基二极管，使得晶体管的寄生二极管也为硅基二极管，因硅基二极管存在反向恢复电流，且损耗较高，所以采用碳化硅基二极管，可以消除反向恢复电流，降低损耗，从而可以提高该图腾柱PFC电路的开关频率。再结合软启动模块的软启动功能，使得本申请实施例提供的图腾柱PFC电路，可以在实现软启动的同时，提高开关频率。
在一些实施方式中，软启动模块可以包括：第一电感、第二电感、第一软启动单元和第二软启动单元。
为了便于说两个电感和两个软启动单元的连接关系，首先在该图腾柱PFC电路中定义四个节点，其中：
电源输入端的第一端与第一节点连接，电源输入端的第二端与第二节点连接；在电源输入端提供的交流信号处于正半周时，第一节点处于正电位，第二节点处于负电位；在电源输入端提供的交流信号处于负半周时，第一节点处于负电位，第二节点处于正电位；第一二极管与第一软启动单元之间的连接点为第三节点；第二二极管与第二软启动单元之间的连接点为第四节点。
此时，对于第一电感和第一软启动单元而言，具体的设置方式为：第一电感连接于第一节点和第三节点之间，也即第一电感的第一端与第一节点电连接，第一电感的第二端与第三节点电连接；第一软启动单元分别与第二节点、第三节点、以及负母线电连接；
这样，在电源输入端提供的交流信号处于正半周时，即第一节点处于正电位，第二节点处于负电位时，在第一预设时长内，第一软启动单元将处于正半周的交流信号存储至第一电感中，为第一电感充电， 以将电源输入端提供的电能储存在第一电感中，使得第一电感的第一端(即第一节点)处于正电位，第二端(即第三节点)处于负电位；在第二预设时长内，第一软启动单元将第一电感中存储的电能通过第一二极管转移至电容中，为电容充电，以将电源输入端提供的电能转移电容中，使得第一电感的第一端(即第一节点)处于负电位，第二端(即第三节点)处于正电位。并且，在正半周的时间内，第一预设时长和第二预设时长交替出现至少一次，从而使得电能间歇性地转移至电容中，并实现对处于正半周的交流信号的功率因数校正处理。
对于第二电感和第二软启动单元而言，具体的设置方式为：第二电感连接于第一节点和第四节点之间，也即第二电感的第一端与第一节点电连接，第二电感的第二端与第四节点电连接；第二软启动单元分别与第二节点、第四节点、以及正母线电连接；
这样，在电源输入端提供的交流信号处于负半周时，即第一节点处于负电位，第二节点处于正电位时，在第三预设时长内，第二软启动单元将处于负半周的交流信号存储至第二电感中，为第二电感充电，以将电源输入端提供的电能储存在第二电感中，使得第二电感的第一端(即第一节点)处于负电位，第二端(即第四节点)处于正电位；在第四预设时长内，第二软启动单元将第二电感中存储的电能通过第二二极管转移至电容中，为电容充电，以将电源输入端提供的电能转移电容中，使得第二电感的第一端(即第一节点)处于正电位，第二端(即第四节点)处于负电位。并且，在负半周的时间内，第三预设时长和第四预设时长交替出现至少一次，从而使得电能间歇性地转移至电容中，并实现对处于负半周的交流信号的功率因数校正处理。
如此，通过第一软启动单元和第二软启动单元的设置，可以实现软启动模块的功能，不管电源输入端提供的交流信号处于负半周还是处于正半周，均可以将电能先存储至对应的电感中，再转移至电容中，实现对电源输入端提供的交流信号的处理，在实现图腾柱PFC电路的整流与功率因数校正功能的基础上，提高具有软启动功能的图腾柱PFC电路的开关频率。
在一些实施方式中，若要实现第一软启动单元的功能，可以将第一软启动单元设置为：
第一软启动单元包括：第一晶体管和第一晶闸管，其中：
第一晶体管的第一极与第三节点电连接(也即第一极分别与第一电感和第一二极管的正极电连接)，第一晶体管的第二极分别与负母线和第一晶闸管的正极电连接，第一晶体管的控制极与第一控制信号线电连接；
第一晶闸管的负极与电源输入端的第二端(也即第二节点)电连接，第一晶闸管的门极与第二控制信号线电连接。
这样，在第一预设时长内，第一控制信号线可以控制第一晶体管导通，第二控制信号线可以控制第一晶闸管导通，使得第一电感、第一晶体管、第一晶闸管和电源输入端可以构成充电回路，将处于正半周的交流信号存储至第一电感中；在第二预设时长内，第一控制信号线可以控制第一晶体管断开，且第二控制信号线继续保持第一晶闸管导通，使得第一电感、第一二极管、电容、第一晶闸管和电源输入端可以构成放电回路，将第一电感中存储的电能转移至电容中，从而通过对第一晶体管和第一晶闸管的导通状态的控制，实现电能的转移和信号处理。
在一些实施方式中，若要实现第二软启动单元的功能，类似地，可以将第二软启动单元设置为：
第二软启动单元包括：第二晶体管和第二晶闸管，其中：
第二晶体管的第一极与第四节点电连接(也即第一极分别与第二电感和第二二极管的负极电连接)，第二晶体管的第二极分别与正母线和第二晶闸管的负极电连接，第二晶体管的控制极与第三控制信号线电连接；
第二晶闸管的正极与电源输入端的第二端(也即第二节点)电连接，第二晶闸管的门极与第四控制信号线电连接。
这样，在第三预设时长内，第三控制信号线可以控制第二晶体管导通，第四控制信号线可以控制第二晶闸管导通，使得第二电感、第二晶体管、第二晶闸管和电源输入端可以构成充电回路，将处于负半周的交流信号存储至第二电感中；在第四预设时长内，第三控制信号线可以控制第二晶体管断开，且第四控制信号线继续保持第二晶闸管导通，使得第二电感、第二二极管、电容、第二晶闸管和电源输入端可以构成放电回路，将第二电感中存储的电能转移至电容中，从而通过对第二晶体管和第二晶闸管的导通状态的控制，实现电能的转移和信号处理。
在一些实施方式中，第一晶体管存在寄生二极管，该寄生二极管的正极与负母线电连接，负极与第 三节点电连接；在第一晶体管为硅基二极管时，该寄生二极管同样为硅基二极管，且如果电流通过硅基二极管，该硅基二极管容易产生反向恢复电流；
基于此，在第一预设时长内，在第一电感、第一晶体管、第一晶闸管和电源输入端构成充电回路时，因第一晶体管的寄生二极管的正极电位小于负极电位，使得充电回路中的电流并不会通过该寄生二极管，所以第一预设时长内并不存在反向恢复电流；
由于在第二预设时长内电能通过第一二极管转移至电容中，且第一二极管为碳化硅基二极管，该碳化硅基二极管无反向恢复电流；并且，在第二预设时长内，在第一电感、第一二极管、电容、第一晶闸管和电源输入端构成放电回路时，因第一晶体管的寄生二极管的正极电位小于负极电位，使得放电回路中的电流也不会通过该寄生二极管；基于此，在第二预设时长内也不存在反向恢复电流。
同样地，第二晶体管也存在寄生二极管，该寄生二极管的负极与正母线电连接，正极与第四节点电连接；在第二晶体管为硅基二极管时，该寄生二极管同样为硅基二极管，且如果电流通过硅基二极管，该硅基二极管容易产生反向恢复电流；
基于此，在第三预设时长内，在第二电感、第二晶体管、第二晶闸管和电源输入端构成充电回路时，因第二晶体管的寄生二极管的正极电位小于负极电位，使得充电回路中的电流并不会通过该寄生二极管，所以第三预设时长内并不存在反向恢复电流。由于在第四预设时长内电能通过第二二极管转移至电容中，且第二二极管为碳化硅基二极管，该碳化硅基二极管无反向恢复电流；并且，在第四预设时长内，在第二电感、第二二极管、电容、第二晶闸管和电源输入端构成放电回路时，因第二晶体管的寄生二极管的正极电位小于负极电位，使得放电回路中的电流也不会通过该寄生二极管，所以在第四预设时长内也不存在反向恢复电流。
因此，不管是充电过程还是放电过程，均不存在反向恢复电流，所以可以实现充电过程和放电过程快速、有效地切换，从而可以有效提高图腾柱PFC电路的开关频率。并且，硅基晶体管的制作工艺较成熟，制作成本较低，采用硅基晶体管与碳化硅基二极管相结合，在有效提高图腾柱PFC电路的开关频率的同时，还可以降低图腾柱PFC电路的制作成本，提高图腾柱PFC电路的制作良率。
第二方面，本申请实施例还提供了控制方法，该控制方法如本申请实施例提供的上述图腾柱PFC电路，该控制方法可以包括：
在电源输入端提供的交流信号处于正半周时，软启动模块可以通过第一二极管，将该处于正半周的交流信号传输至正母线和负母线中，并存储至位于正母线和负母线之间的电容中；在电源输入端提供的交流信号处于负半周时，软启动模块可以通过第二二极管，将该处于负半周的交流信号传输至正母线和负母线中，同样存储至位于正母线和负母线之间的电容中。
如此，通过软启动模块、第一二极管和第二二极管，实现了对电源输入端提供的交流信号的整流作用，将该交流信号调整为直流信号后输出。
并且，交流信号是通过第一二极管和第二二极管传输的，而并不是像现有技术那样通过晶体管的寄生二极管传输的，由于第一二极管和第二二极管均为碳化硅基二极管，且碳化硅基二极管具有损耗小、无反向恢复电流的特点，而目前常用的晶体管均为硅基二极管，使得晶体管的寄生二极管也为硅基二极管，因硅基二极管存在反向恢复电流，且损耗较高，所以采用碳化硅基二极管，可以消除反向恢复电流，降低损耗，从而可以提高该图腾柱PFC电路的开关频率。再结合软启动模块的软启动功能，使得本申请实施例提供的图腾柱PFC电路，可以在实现软启动的同时，提高开关频率。
下面分别基于正半周的交流信号和负半周的交流信号，对本申请实施例提供的控制方法进行详细说明。
1、针对处于正半周的交流信号。
在一些实施例中，在软启动模块包括：第一电感、第二电感、第一软启动单元和第二软启动单元时，通过第一二极管，将处于正半周的交流信号传输至正母线和负母线，并存储至电容中，可以具体包括：
在电源输入端提供的交流信号处于正半周时，即第一节点处于正电位，第二节点处于负电位时，在第一预设时长内，第一软启动单元首先将处于正半周的交流信号存储至第一电感中，为第一电感充电，以将电源输入端提供的电能储存在第一电感中；在第二预设时长内，第一软启动单元再将第一电感中存储的电能通过第一二极管转移至电容中，为电容充电，以将电源输入端提供的电能转移电容中；
其中，可以对电源输入端提供的交流信号进行划分，将交流信号中处于正半周的时间段定义为第一 时间段，将交流信号中处于负半周的时间段定义为第二时间段；在第一时间段内可以划分出多个第一预设时长和多个第二预设时长，各第一预设时长和各第二预设时长交替设置，例如，第一预设时长、第二预设时长、第一预设时长、第二预设时长……这样交替地排列设置。
这样，在第一时间段，各第一预设时长和各第二预设时长交替设置，而第一预设时长内进行充电过程，第二预设时长内进行放电过程，所以充电过程和放电过程交替进行，从而实现对处于正半周的交流信号的功率因数校正处理。
在一些实施例中，第一预设时长和第二预设时长的设置，可以根据电源输入端提供的交流信号与设定的载波信号的大小关系进行确定；例如，将交流信号的值大于或等于设定的正载波信号的值的时间段设置为第一预设时长，将交流信号的值小于设定的正载波信号的值的时间段设置为第二预设时长。
当然，第一预设时长和第二预设时长，还可以根据其他方式进行设置，在此并不限定；
其中，对于其他方式，例如但不限于包括：
若将相邻的第一预设时长和第二预设时长看作是一个重复周期时，各重复周期的大小可以是相同的，将每个重复周期进行等分以划分出第一预设时长和第二预设时长。
在一些实施例中，在第一软启动单元包括：第一晶体管和第一晶闸管，且第一晶体管的控制极与第一控制信号线电连接，第一晶闸管的门极与第二控制信号线电连接时，那么：
1.1、第一控制信号线可以按照以下方式提供信号：
在第一时间段的第一预设时长内，第一控制信号线提供第一逻辑信号；
在第一时间段的第二预设时长内、以及第二时间段内，第一控制信号线均提供第二逻辑信号。
其中，第一逻辑信号可以为高电平信号，第二逻辑信号可以为低电平信号；或者，第一逻辑信号可以为低电平信号，第二逻辑信号可以为高电平信号；第一逻辑信号和第二逻辑信号的选取，可以根据第一晶体管的类型进行确定。
具体地，在一些实施例中，在第一晶体管为N型晶体管时，在第一预设时长内，第一晶体管需要导通以形成充电路，此时第一控制信号线提供的第一逻辑信号可以为高电平信号，以控制N型的第一晶体管导通；在第二预设时长和整个第二时间段内，第一晶体管需要断开，此时第一控制信号线提供的第二逻辑信号可以为低电平信号，以控制N型的第一晶体管断开；
在第一晶体管为P型晶体管时，在第一预设时长内，第一晶体管需要导通以形成充电路，此时第一控制信号线提供的第一逻辑信号可以为低电平信号，以控制P型的第一晶体管导通；在第二预设时长和整个第二时间段内，第一晶体管需要断开，此时第一控制信号线提供的第二逻辑信号可以为高电平信号，以控制P型的第一晶体管断开。
1.2、第二控制信号线可以按照以下方式提供信号：
在一些实施例中，在第一时间段内，第一晶闸管需要保持导通状态，所以第二控制信号线可以在第一时间段内提供脉冲信号，第一时间段的起始时刻处于第一个有效脉冲内，使得在第一时间段的起始时刻，在第一晶闸管的正极电位高于负极电位的情况下，在向门极施加的有效脉冲的驱动下，即可控制第一晶闸管导通，以便于对交流信号进行处理。
并且，对于该脉冲信号而言，有效脉冲的宽度为2μs至10μs，相邻两个有效脉冲之间的时间间隔为2ms；这样设置的原因在于：
在目前技术中，向晶闸管的门极提供脉冲信号时，提供的脉冲信号包括双脉冲信号和宽脉冲信号，其中，双脉冲信号为每隔70°连续输出两个有效脉冲，且每个有效脉冲的宽度为10°，连续两个有效脉冲之间的时间间隔是非常短的，远小于2ms；该种脉冲信号可能会存在诸如交流信号过零点时无有效脉冲输出的情况，导致在交流信号过零点时可能会出现晶闸管无法导通的情况，这样会导致图腾柱PFC电路无法正常工作，进一步导致图腾柱PFC电路在对交流信号进行处理时出现异常；
宽脉冲信号为每隔70°输出一个具有较大脉宽的有效脉冲，使得每个有效脉冲的脉冲宽度较大，这样会导致晶闸管的门极大部分时间都在被施加驱动，进一步地导致晶闸管的消耗增加，使得反向恢复电流(也即漏电流)也相应增加，最终导致开关频率的降低；
在本申请中实施例中，向门极提供的脉冲信号中有效脉冲的宽度为2μs至10μs，相邻两个有效脉冲之间的时间间隔为2ms，这样可以避免有效脉冲的宽度较大，进而避免第一晶闸管的消耗增加及反向恢复电流增加；再结合第一时间段的起始时刻处于第一个有效脉冲内，即使交流信号过零点时，第一晶闸管的门极也依然会被施加驱动，避免交流信号过零点时可能会出现晶闸管无法导通的情况，从而在保 证图腾柱PFC电路正常工作的同时，还可以提高开关频率。
进一步地，在一些实施例中，还可以对第二控制信号线提供的有效脉冲进行进一步地设置，例如可以对第一个有效脉冲的上升沿和下降沿进行设置，具体的设置方式可以包括：
对于任一正半周，处于该正半周的交流信号的值等于预设值的多个时刻中的最早时刻与第一个有效脉冲的下降沿对齐；
对于位于该正半周之前且与该正半周相邻的负半周，处于该负半周的交流信号的绝对值等于预设值的多个时刻中的最晚时刻与第一个有效脉冲的上升沿对齐。
其中，预设值可以但不限于为10V，当然还可以为5V、8V或13V等其他数值，具体可以根据实际需要进行设置，在此并不限定。
如此，可以确保第一时间段的起始时刻处于第一个有效脉冲内，在交流信号过零点时，第一晶闸管的门极也依然会被施加驱动，避免交流信号过零点时可能会出现晶闸管无法导通的情况，从而在保证图腾柱PFC电路正常工作的同时，还可以提高开关频率。
在一些实施例中，第二控制信号线提供的脉冲信号中的各有效脉冲的宽度可以均设置为相同，这样可以降低提供的脉冲信号的复杂度，提高控制的精度，避免出现控制误差；
或者，第二控制信号线提供的脉冲信号中的各有效脉冲的宽度可以设置为部分相同，第一个有效脉冲的宽度较大，其余的有效脉冲的宽度较小且相同，如此可以有效保证交流信号过零点时第一晶闸管的门极被施加驱动，保证在过零点时第一晶闸管处于导通状态，从而保证图腾柱PFC电路正常工作。
2、针对处于负半周的交流信号。
在一些实施例中，在软启动模块包括：第一电感、第二电感、第一软启动单元和第二软启动单元时，通过第二二极管，将处于负半周的交流信号传输至正母线和负母线，并存储至电容中，可以具体包括：
在电源输入端提供的交流信号处于负半周时，即第一节点处于负电位，第二节点处于正电位时，在第三预设时长内，第二软启动单元首先将处于负半周的交流信号存储至第二电感中，为第二电感充电，以将电源输入端提供的电能储存在第二电感中；在第四预设时长内，第二软启动单元再将第二电感中存储的电能通过第二二极管转移至电容中，为电容充电，以将电源输入端提供的电能转移电容中；
其中，在第二时间段内可以划分出多个第三预设时长和第四预设时长，各第三预设时长和各第四预设时长交替设置，例如，第三预设时长、第四预设时长、第三预设时长、第四预设时长……这样交替地排列设置。
这样，在第二时间段，各第三预设时长和各第四预设时长交替设置，而第三预设时长内进行充电过程，第四预设时长内进行放电过程，所以充电过程和放电过程交替进行，从而实现对处于负半周的交流信号的功率因数校正处理。
在一些实施例中，第三预设时长和第四预设时长的设置，可以根据电源输入端提供的交流信号与设定的载波信号的大小关系进行确定；例如，将交流信号的值大于或等于设定的负载波信号的值的时间段设置为第三预设时长，将交流信号的值小于设定的负载波信号的值的时间段设置为第四预设时长。
当然，第三预设时长和第四预设时长，还可以根据其他方式进行设置，在此并不限定；
其中，对于其他方式，例如但不限于包括：
若将相邻的第三预设时长和第四预设时长看作是一个重复周期时，各重复周期的大小可以是相同的，将每个重复周期进行等分以划分出第三预设时长和第四预设时长。
在一些实施例中，在第二软启动单元包括：第二晶体管和第二晶闸管，且第二晶体管的控制极与第三控制信号线电连接，第二晶闸管的门极与第四控制信号线电连接时，那么：
1、第三控制信号线可以按照以下方式提供信号：
在第二时间段的第三预设时长内，第三控制信号线提供第一逻辑信号；
在第二时间段的第四预设时长内、以及第一时间段内，第三控制信号线均提供第二逻辑信号。
其中，第一逻辑信号和第二逻辑信号的设置方式，可以参见上述内容中的相关描述，重复之处不再赘述。
2、第四控制信号线可以按照以下方式提供信号：
在一些实施例中，在第二时间段内，第二晶闸管需要保持导通状态，所以第四控制信号线可以在第二时间段内提供脉冲信号，第二时间段的起始时刻处于第一个有效脉冲内，使得在第二时间段的起始时刻，在第二晶闸管的正极电位高于负极电位的情况下，在向门极施加的有效脉冲的驱动下，即可控制第 二晶闸管导通，以便于对交流信号进行处理。
并且，对于该脉冲信号而言，有效脉冲的宽度为2μs至10μs，相邻两个有效脉冲之间的时间间隔为2ms。
这样，在本申请中实施例中，向门极提供的脉冲信号中有效脉冲的宽度为2μs至10μs，相邻两个有效脉冲之间的时间间隔为2ms，这样可以避免有效脉冲的宽度较大，进而避免第二晶闸管的消耗增加及反向恢复电流增加；再结合第二时间段的起始时刻处于第一个有效脉冲内，即使交流信号过零点时，第二晶闸管的门极也依然会被施加驱动，避免交流信号过零点时可能会出现晶闸管无法导通的情况，从而在保证图腾柱PFC电路正常工作的同时，还可以提高开关频率。
进一步地，在一些实施例中，还可以对第四控制信号线提供的有效脉冲进行进一步地设置，例如可以对第一个有效脉冲的上升沿和下降沿进行设置，具体的设置方式可以包括：
对于任一负半周，处于该负半周的交流信号的绝对值等于预设值的多个时刻中的最早时刻与第一个有效脉冲的下降沿对齐；
对于位于该负半周之前且与该负半周相邻的正半周，处于该正半周的交流信号的值等于预设值的多个时刻中的最晚时刻与第一个有效脉冲的上升沿对齐。
其中，预设值可以但不限于为10V，当然还可以为5V、8V或13V等其他数值，具体可以根据实际需要进行设置，在此并不限定。
如此，可以确保第二时间段的起始时刻处于第一个有效脉冲内，在交流信号过零点时，第二晶闸管的门极也依然会被施加驱动，避免交流信号过零点时可能会出现晶闸管无法导通的情况，从而在保证图腾柱PFC电路正常工作的同时，还可以提高开关频率。
在一些实施例中，第四控制信号线提供的脉冲信号中的各有效脉冲的宽度可以均设置为相同，这样可以降低提供的脉冲信号的复杂度，提高控制的精度，避免出现控制误差；
或者，第四控制信号线提供的脉冲信号中的各有效脉冲的宽度可以设置为部分相同，第一个有效脉冲的宽度较大，其余的有效脉冲的宽度较小且相同，如此可以有效保证交流信号过零点时第二晶闸管的门极被施加有驱动，保证在过零点时第二晶闸管处于导通状态，从而保证图腾柱PFC电路正常工作。
在一些实施例中，不管是位于正半周的交流信号，还是位于负半周的交流信号，在进行信号处理的过程中，并不会出现反向恢复电流，所以损耗较小，可以有效提高开关频率，其中开关频率可以至少为100KHz，在换算成时间时，可以确定出：
在正半周，若将相邻的第一预设时长和第二预设时长看作是一个重复周期时，该重复周期的时长最大为1/100KHz＝10μs，所以在第一预设时长和第二预设时长交替出现时，相邻的第一预设时长和第二预设时长之和最大为10μs；
在负半周，若将相邻的第三预设时长和第四预设时长看作是一个重复周期时，该重复周期的时长最大也为1/100KHz＝10μs，所以在第三预设时长和第四预设时长交替出现时，相邻的第三预设时长和第四预设时长之和最大依然为10μs。
如此，可以保证图腾柱PFC电路的开关频率至少为100KHz，有效提高了图腾柱PFC电路的开关频率，拓宽该图腾柱PFC电路的应用范围。
第三方面，本申请实施例还提供了一种电源装置，包括：控制器、以及如本申请实施例提供的上述图腾柱PFC电路；控制器用于：控制图腾柱PFC电路对电源输入端提供的交流信号进行处理。
在一些实施例中，控制器可以与第一控制信号线、第二控制信号线、第三控制信号线和第四控制信号线电连接，通过控制器可以使得各控制信号线可以提供相应的信号，以保证图腾柱PFC电路正常工作的同时，实现软启动，提高开关频率。
在一些实施例中，电源装置除了可以包括控制器和图腾柱PFC电路之外，还可以包括其他可以用于实现电源装置的结构(例如但不限于为逆变器等)，在此并不限定。
附图说明
图1为目前技术中的一种图腾柱PFC电路的结构示意图；
图2为目前技术中的另一种图腾柱PFC电路的结构示意图；
图3为本申请实施例提供的一种图腾柱PFC电路的结构示意图；
图4为本申请实施例提供的一种图腾柱PFC电路的具体结构示意图；
图5为本申请实施例提供的一种充电回路的示意图；
图6为本申请实施例提供的一种放电回路的示意图；
图7为本申请实施例提供的另一种充电回路的示意图；
图8为本申请实施例提供的另一种放电回路的示意图；
图9为本申请实施例提供的一种时序图；
图10为本申请实施例提供的另一种时序图；
图11为本申请实施例提供的一种电源装置的结构示意图。
具体实施方式
以下，先对本申请实施例中涉及的部分用语进行解释说明，以便于本领域技术人员容易理解。
(1)PFC电路：是一种用于功率因数校正的电路。常规整流滤波电路的整流桥，只有在输入正弦波电压接近峰值时才会导通，输入的电流会有严重的非正弦性，导致产生了大量谐波电流成分，同时谐波电流成分还存在干扰其他电力设备的可能。PFC电路通过对输入的交流电流进行整形，使输入的电流被整形为与输入电压近似且同相位的正弦波，以使输入功率尽可能的接近于1。
常用的PFC电路多为Boost升压拓扑结构，根据Boost拓扑在不同工作模式(断续导通模式/临界导通模式/连续导通模式)下的特性不同，对应不同特性控制方法可以分为多种。
(2)图腾柱PFC电路：传统的PFC电路由整流桥加上Boost PFC电路组成，由两级构成，也因此称为有桥PFC电路；为了进一步提高效率，无桥PFC将整流桥和PFC电路合成单级电路，没有了整流桥部分的损耗，同时实现整流与功率因数校正的作用，故称为无桥PFC电路。图腾柱PFC电路是无桥PFC电路中一种效率最优的拓扑，相对其他无桥PFC电路也更为简单，也可称为图腾柱无桥PFC电路。
(3)软启动：以晶体管为例，晶体管具有栅极、源极和漏极，在向栅极施加一定的电压时，可以控制晶体管的源极和漏极的导通和关断，所以通过对栅极施加的电压的控制，可以控制晶体管的源极和漏极的导通状态；这种对栅极施加电压的控制，可以理解为软启动。
需要说明的是，在本申请的描述中“至少一个”是指一个或多个，其中，多个是指两个或两个以上。鉴于此，本申请实施例中也可以将“多个”理解为“至少两个”。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，字符“/”，如无特殊说明，一般表示前后关联对象是一种“或”的关系。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
并且，在本申请的描述中，“第一极”可以理解为源极，“第二极”可以理解为漏极；或者，“第一极”可以理解为漏极，“第二极”可以理解为源极；控制极可以理解为栅极。
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
如图1所示的图腾柱PFC电路，该种图腾柱PFC电路具有功率回路动点少、器件数量少、占用面积小等特点，然而该种结构的图腾柱PFC电路无法实现软启动，同时由于晶体管(如G1和G2)存在寄生二极管(如图1中虚线框内所示的结构)，且寄生二极管存在反向恢复电流，且损耗较大，这样导致该种结构的图腾柱PFC电路的开关频率较低。
如图2所示的图腾柱PFC电路，该电路可以包括：设置于正母线Vb+和负母线Vb-之间的第一支路、第二支路和第三支路，第一支路中设置有串联连接的第一晶体管G1和第二晶体管G2，第二支路中设置有串联连接的第一晶闸管SCR1和第二晶闸管SCR2，第三支路中设置有电容C；图腾柱PFC电路还包括电感L，电感L的第一端(如图2中所示的右端)与第一支路中第一晶体管G1和第二晶体管G2之间的连接点A连接，电感L的第二端(如图2中所示的左端)与电源输入端AC的第一端(如图2中所示的上端)电连接，电源输入端AC的第二端(如图2中所示的下端)与第二支路中第一晶闸管SCR1和第二晶闸管SCR2之间的连接点B连接。
电源输入端AC输入的信号为交流信号时，图2所示的图腾柱PFC电路的工作原理如下：
在交流信号处于正半周时，电源输入端AC的第一端为正极，第二端为负极，此时，在充电模式下：第一晶体管G1和第一晶闸管SCR1均导通，第二晶体管G2和第二晶闸管SCR2均断开，电源输入端AC、电感LL、第一晶体管G1和第一晶闸管SCR1形成充电回路，且为电感LL充电；在放电模式下： 第一晶闸管SCR1继续导通，第二晶闸管SCR2、第一晶体管G1和第二晶体管G2均断开，但因第二晶体管G2的寄生二极管的正极电位高于负极电位，所以该寄生二极管导通，电源输入端AC、电感LL、第二晶体管G2的寄生二极管、电容C、第一晶闸管SCR1形成放电回路，且将电感LL中存储的电能转移至电容C中，为电容C充电；
在交流信号处于负半周时，电源输入端AC的第一端为负极，第二端为正极，此时，在充电模式下：第一晶体管G1和第一晶闸管SCR1均断开，第二晶体管G2和第二晶闸管SCR2均导通，电源输入端AC、第二晶闸管SCR2、第二晶体管G2、电感LL形成充电回路，且为电感LL充电；在放电模式下：第二晶闸管SCR2继续导通，第一晶闸管SCR1、第一晶体管G1和第二晶体管G2均断开，但因第一晶体管G1的寄生二极管的正极电位高于负极电位，所以该寄生二极管导通，电源输入端AC、第二晶闸管SCR2、电容C、第一晶体管G1的寄生二极管、电感LL形成放电回路，且将电感LL中存储的电能转移至电容C中，为电容C充电。
在上述充电模式和放电模式的交替作用下，将电源输入端AC提供的交流信号转换为直流信号，并传输至正母线Vb+和负母线Vb-中，实现信号的转换。
其中，对于图2中所示的图腾柱PFC电路，采用第一晶闸管SCR1和第二晶闸管SCR2，实现了数字化的浪涌电流限值，同时实现了软启动；然而，第一晶体管G1和第二晶体管G2均为硅基晶体管时，硅基晶体管中的寄生二极管为硅基二极管，而硅基二极管存在反向恢复电流，且损耗较大，这样导致该种结构的图腾柱PFC电路的开关频率较低。
有鉴于此，提高具有软启动功能的图腾柱PFC电路的开关频率，是本领域人员亟待解决的。
本申请实施例提供了一种图腾柱PFC电路、其控制方法及电源装置，该图腾柱PFC电路可以应用至储能设备(例如但不限于电池)、以及不间断电流使用场景中，设置于电网与用电设备之间，对电网提供的交流电进行整流和功率因数校正后输出至用电设备，以便于用电设备使用。
如图3所示的图腾柱PFC电路的结构示意图，该图腾柱PFC电路包括软启动模块10、第一二极管D1、第二二极管D2和电容C，其中，软启动模块10通过第一二极管D1与正母线Vb+电连接，以及通过第二二极管D2与负母线Vb-电连接；并且，软启动模块10还分别与正母线Vb+、负母线Vb-和电源输入端AC电连接；
这样，在电源输入端AC提供的交流信号处于正半周时，软启动模块10可以通过第一二极管D1，将该处于正半周的交流信号传输至正母线Vb+和负母线Vb-中，并存储至位于正母线Vb+和负母线Vb-之间的电容C中；在电源输入端AC提供的交流信号处于负半周时，软启动模块10可以通过第二二极管D2，将该处于负半周的交流信号传输至正母线Vb+和负母线Vb-中，同样存储至位于正母线Vb+和负母线Vb-之间的电容C中。
如此，通过软启动模块、第一二极管和第二二极管，实现了对电源输入端提供的交流信号的整流作用，将该交流信号调整为直流信号后输出。在正母线和负母线之间设置有负载时，调整后的直流信号可以为负载供电，保证负载在供电的驱动下工作。
并且，交流信号是通过第一二极管和第二二极管传输的，而并不是像现有技术那样通过晶体管的寄生二极管传输的，由于第一二极管和第二二极管均为碳化硅基二极管，且碳化硅基二极管具有损耗小、无反向恢复电流的特点，而目前常用的晶体管均为硅基二极管，使得晶体管的寄生二极管也为硅基二极管，因硅基二极管存在反向恢复电流，且损耗较高，所以采用碳化硅基二极管，可以消除反向恢复电流，降低损耗，从而可以提高该图腾柱PFC电路的开关频率。再结合软启动模块的软启动功能，使得本申请实施例提供的图腾柱PFC电路，可以在实现软启动的同时，提高开关频率。
如图4所示的图腾柱PFC电路的具体结构示意图，在一些实施方式中，软启动模块10可以包括：第一电感L1、第二电感L2、第一软启动单元11和第二软启动单元12。
为了便于说两个电感和两个软启动单元的连接关系，首先在该图腾柱PFC电路中定义四个节点，如图4所示，其中：
电源输入端AC的第一端(如图中所示的上端)与第一节点P1连接，电源输入端AC的第二端(如图中所示的下端)与第二节点P2连接；在电源输入端AC提供的交流信号处于正半周时，第一节点P1处于正电位，第二节点P2处于负电位；在电源输入端AC提供的交流信号处于负半周时，第一节点P1处于负电位，第二节点P2处于正电位；
第一二极管D1与第一软启动单元11之间的连接点为第三节点P3；
第二二极管D2与第二软启动单元12之间的连接点为第四节点P4。
此时，参见图4所示，对于第一电感L1和第一软启动单元11而言，具体的设置方式为：
第一电感L1连接于第一节点P1和第三节点P3之间，也即第一电感L1的第一端(即图中所示的左端)与第一节点P1电连接，第一电感L1的第二端(即图中所示的右端)与第三节点P3电连接；
第一软启动单元11分别与第二节点P2、第三节点P3、以及负母线Vb-电连接；
这样，在电源输入端AC提供的交流信号处于正半周时，即第一节点P1处于正电位，第二节点P2处于负电位时，在第一预设时长内，第一软启动单元11将处于正半周的交流信号存储至第一电感L1中，为第一电感L1充电，以将电源输入端AC提供的电能储存在第一电感L1中，使得第一电感L1的第一端(即图中所示的左端，也即第一节点P1)处于正电位，第二端(即图中所示的右端，也即第三节点P3)处于负电位；在第二预设时长内，第一软启动单元11将第一电感L1中存储的电能通过第一二极管D1转移至电容C中，为电容C充电，以将电源输入端AC提供的电能转移电容C中，使得第一电感L1的第一端(即图中所示的左端，也即第一节点P1)处于负电位，第二端(即图中所示的右端，也即第三节点P3)处于正电位。并且，在正半周的时间内，第一预设时长和第二预设时长交替出现至少一次，从而使得电能间歇性地转移至电容C中，并实现对处于正半周的交流信号的功率因数校正处理。
继续参见图4所示，对于第二电感L2和第二软启动单元12而言，具体的设置方式为：
第二电感L2连接于第一节点P1和第四节点P4之间，也即第二电感L2的第一端(即图中所示的左端)与第一节点P1电连接，第二电感L2的第二端(即图中所示的右端)与第四节点P4电连接；
第二软启动单元12分别与第二节点P2、第四节点P4、以及正母线Vb+电连接；
这样，在电源输入端AC提供的交流信号处于负半周时，即第一节点P1处于负电位，第二节点P2处于正电位时，在第三预设时长内，第二软启动单元12将处于负半周的交流信号存储至第二电感L2中，为第二电感L2充电，以将电源输入端AC提供的电能储存在第二电感L2中，使得第二电感L2的第一端(即图中所示的左端，也即第一节点P1)处于负电位，第二端(即图中所示的右端，也即第四节点P4)处于正电位；在第四预设时长内，第二软启动单元12将第二电感L2中存储的电能通过第二二极管D2转移至电容C中，为电容C充电，以将电源输入端AC提供的电能转移电容C中，使得第二电感L2的第一端(即图中所示的左端，也即第一节点P1)处于正电位，第二端(即图中所示的右端，也即第四节点P4)处于负电位。并且，在负半周的时间内，第三预设时长和第四预设时长交替出现至少一次，从而使得电能间歇性地转移至电容C中，并实现对处于负半周的交流信号的功率因数校正处理。
如此，通过第一软启动单元和第二软启动单元的设置，可以实现软启动模块的功能，不管电源输入端提供的交流信号处于负半周还是处于正半周，均可以将电能先存储至对应的电感中，再转移至电容中，实现对电源输入端提供的交流信号的处理，在实现图腾柱PFC电路的整流与功率因数校正功能的基础上，提高具有软启动功能的图腾柱PFC电路的开关频率。
继续参见图4所示，在一些实施方式中，若要实现第一软启动单元11的功能，可以将第一软启动单元11设置为：
第一软启动单元11包括：第一晶体管G1和第一晶闸管SCR1，其中：
第一晶体管G1的第一极与第三节点P3电连接(也即第一极分别与第一电感L1和第一二极管D1的正极电连接)，第一晶体管G1的第二极分别与负母线Vb-和第一晶闸管SCR1的正极电连接，第一晶体管G1的控制极与第一控制信号线k1电连接；
第一晶闸管SCR1的负极与电源输入端AC的第二端(也即第二节点P2)电连接，第一晶闸管SCR1的门极与第二控制信号线k2电连接。
这样，在第一预设时长内，第一控制信号线k1可以控制第一晶体管G1导通，第二控制信号线k2可以控制第一晶闸管SCR1导通，使得第一电感L1、第一晶体管G1、第一晶闸管SCR1和电源输入端AC可以构成充电回路，如图5中虚线箭头所指示的回路，将处于正半周的交流信号存储至第一电感L1中；在第二预设时长内，第一控制信号线k1可以控制第一晶体管G1断开，且第二控制信号线k2继续保持第一晶闸管SCR1导通，使得第一电感L1、第一二极管D1、电容C、第一晶闸管SCR1和电源输入端AC可以构成放电回路，如图6中虚线箭头所指示的回路，将第一电感L1中存储的电能转移至电 容C中，从而通过对第一晶体管G1和第一晶闸管SCR1的导通状态的控制，实现电能的转移和信号处理。
继续参见图4所示，在一些实施方式中，若要实现第二软启动单元12的功能，类似地，可以将第二软启动单元12设置为：
第二软启动单元12包括：第二晶体管G2和第二晶闸管SCR2，其中：
第二晶体管G2的第一极与第四节点P4电连接(也即第一极分别与第二电感L2和第二二极管D2的负极电连接)，第二晶体管G2的第二极分别与正母线Vb+和第二晶闸管SCR2的负极电连接，第二晶体管G2的控制极与第三控制信号线k3电连接；
第二晶闸管SCR2的正极与电源输入端AC的第二端(也即第二节点P2)电连接，第二晶闸管SCR2的门极与第四控制信号线k4电连接。
这样，在第三预设时长内，第三控制信号线k3可以控制第二晶体管G2导通，第四控制信号线k4可以控制第二晶闸管SCR2导通，使得第二电感L2、第二晶体管G2、第二晶闸管SCR2和电源输入端AC可以构成充电回路，如图7中虚线箭头所指示的回路，将处于负半周的交流信号存储至第二电感L2中；在第四预设时长内，第三控制信号线k3可以控制第二晶体管G2断开，且第四控制信号线k4继续保持第二晶闸管SCR2导通，使得第二电感L2、第二二极管D2、电容C、第二晶闸管SCR2和电源输入端AC可以构成放电回路，如图8中虚线箭头所指示的回路，将第二电感L2中存储的电能转移至电容C中，从而通过对第二晶体管G2和第二晶闸管SCR2的导通状态的控制，实现电能的转移和信号处理。
在一些实施方式中，结合图4所示，第一晶体管G1存在寄生二极管，该寄生二极管的正极与负母线Vb-电连接，负极与第三节点P3电连接；在第一晶体管G1为硅基二极管时，该寄生二极管同样为硅基二极管，且如果电流通过硅基二极管，该硅基二极管容易产生反向恢复电流；
基于此，在第一预设时长内，在第一电感L1、第一晶体管G1、第一晶闸管SCR1和电源输入端AC构成充电回路(如图5中虚线箭头所指示的回路)时，因第一晶体管G1的寄生二极管的正极电位小于负极电位，使得充电回路中的电流并不会通过该寄生二极管，所以第一预设时长内并不存在反向恢复电流；
由于在第二预设时长内电能通过第一二极管D1转移至电容C中，且第一二极管D1为碳化硅基二极管，该碳化硅基二极管无反向恢复电流；并且，在第二预设时长内，在第一电感L1、第一二极管D1、电容C、第一晶闸管SCR1和电源输入端AC构成放电回路(如图6中虚线箭头所指示的回路)时，因第一晶体管G1的寄生二极管的正极电位小于负极电位，使得放电回路中的电流也不会通过该寄生二极管；基于此，在第二预设时长内也不存在反向恢复电流。
同样地，继续结合图4所示，第二晶体管G2也存在寄生二极管，该寄生二极管的负极与正母线Vb+电连接，正极与第四节点P4电连接；在第二晶体管G2为硅基二极管时，该寄生二极管同样为硅基二极管，且如果电流通过硅基二极管，该硅基二极管容易产生反向恢复电流；
基于此，在第三预设时长内，在第二电感L2、第二晶体管G2、第二晶闸管SCR2和电源输入端AC构成充电回路(如图7中虚线箭头所指示的回路)时，因第二晶体管G2的寄生二极管的正极电位小于负极电位，使得充电回路中的电流并不会通过该寄生二极管，所以第三预设时长内并不存在反向恢复电流。由于在第四预设时长内电能通过第二二极管D2转移至电容C中，且第二二极管D2为碳化硅基二极管，该碳化硅基二极管无反向恢复电流；并且，在第四预设时长内，在第二电感L2、第二二极管D2、电容C、第二晶闸管SCR2和电源输入端AC构成放电回路(如图8中虚线箭头所指示的回路)时，因第二晶体管G2的寄生二极管的正极电位小于负极电位，使得放电回路中的电流也不会通过该寄生二极管，所以在第四预设时长内也不存在反向恢复电流。
因此，不管是充电过程还是放电过程，均不存在反向恢复电流，所以可以实现充电过程和放电过程快速、有效地切换，从而可以有效提高图腾柱PFC电路的开关频率。并且，硅基晶体管的制作工艺较成熟，制作成本较低，采用硅基晶体管与碳化硅基二极管相结合，在有效提高图腾柱PFC电路的开关频率的同时，还可以降低图腾柱PFC电路的制作成本，提高图腾柱PFC电路的制作良率。
基于同一技术构思，本申请实施例还提供了一种控制方法，该控制方法如本申请实施例提供的上述图腾柱PFC电路，该控制方法可以包括：
在电源输入端提供的交流信号处于正半周时，软启动模块可以通过第一二极管，将该处于正半周的交流信号传输至正母线和负母线中，并存储至位于正母线和负母线之间的电容中；在电源输入端提供的交流信号处于负半周时，软启动模块可以通过第二二极管，将该处于负半周的交流信号传输至正母线和负母线中，同样存储至位于正母线和负母线之间的电容中。
如此，通过软启动模块、第一二极管和第二二极管，实现了对电源输入端提供的交流信号的整流作用，将该交流信号调整为直流信号后输出。
并且，交流信号是通过第一二极管和第二二极管传输的，而并不是像现有技术那样通过晶体管的寄生二极管传输的，由于第一二极管和第二二极管均为碳化硅基二极管，且碳化硅基二极管具有损耗小、无反向恢复电流的特点，而目前常用的晶体管均为硅基二极管，使得晶体管的寄生二极管也为硅基二极管，因硅基二极管存在反向恢复电流，且损耗较高，所以采用碳化硅基二极管，可以消除反向恢复电流，降低损耗，从而可以提高该图腾柱PFC电路的开关频率。再结合软启动模块的软启动功能，使得本申请实施例提供的图腾柱PFC电路，可以在实现软启动的同时，提高开关频率。
下面分别基于正半周的交流信号和负半周的交流信号，对本申请实施例提供的控制方法进行详细说明。
1、针对处于正半周的交流信号。
在一些实施例中，结合图4所示的结构，在软启动模块10包括：第一电感L1、第二电感L2、第一软启动单元11和第二软启动单元12时，通过第一二极管D1，将处于正半周的交流信号传输至正母线Vb+和负母线Vb-，并存储至电容C中，可以具体包括：
在电源输入端AC提供的交流信号处于正半周时，即图4中所示的第一节点P1处于正电位，第二节点P2处于负电位时，在第一预设时长内，第一软启动单元11首先将处于正半周的交流信号存储至第一电感L1中，为第一电感L1充电，以将电源输入端AC提供的电能储存在第一电感L1中；在第二预设时长内，第一软启动单元11再将第一电感L1中存储的电能通过第一二极管D1转移至电容C中，为电容C充电，以将电源输入端AC提供的电能转移电容C中；
其中，可以对电源输入端AC提供的交流信号Vac进行划分，参见图9所示，将交流信号Vac中处于正半周的时间段定义为第一时间段T1，将交流信号Vac中处于负半周的时间段定义为第二时间段T2；在第一时间段T1内可以划分出多个第一预设时长t1和多个第二预设时长t2，各第一预设时长t1和各第二预设时长t2交替设置，例如，第一预设时长t1、第二预设时长t2、第一预设时长t1、第二预设时长t2……这样交替地排列设置。
这样，在第一时间段，各第一预设时长和各第二预设时长交替设置，而第一预设时长内进行充电过程，第二预设时长内进行放电过程，所以充电过程和放电过程交替进行，从而实现对处于正半周的交流信号的功率因数校正处理。
在一些实施例中，第一预设时长和第二预设时长的设置，可以根据电源输入端提供的交流信号与设定的载波信号的大小关系进行确定；例如，将交流信号的值大于或等于设定的正载波信号的值的时间段设置为第一预设时长，将交流信号的值小于设定的正载波信号的值的时间段设置为第二预设时长。
当然，第一预设时长和第二预设时长，还可以根据其他方式进行设置，在此并不限定；
其中，对于其他方式，例如但不限于包括：
若将相邻的第一预设时长和第二预设时长看作是一个重复周期时，各重复周期的大小可以是相同的，将每个重复周期进行等分以划分出第一预设时长和第二预设时长。
在一些实施例中，结合图4所示的结构，在第一软启动单元11包括：第一晶体管G1和第一晶闸管SCR1，且第一晶体管G1的控制极与第一控制信号线k1电连接，第一晶闸管SCR1的门极与第二控制信号线k2电连接时，那么：
1.1、第一控制信号线可以按照以下方式提供信号：
在第一时间段的第一预设时长内，第一控制信号线提供第一逻辑信号；
在第一时间段的第二预设时长内、以及第二时间段内，第一控制信号线均提供第二逻辑信号。
其中，第一逻辑信号可以为高电平信号，第二逻辑信号可以为低电平信号；或者，第一逻辑信号可以为低电平信号，第二逻辑信号可以为高电平信号；第一逻辑信号和第二逻辑信号的选取，可以根据第一晶体管的类型进行确定。
具体地，在一些实施例中，在第一晶体管为N型晶体管时，在第一预设时长内，第一晶体管需要 导通以形成充电路，此时第一控制信号线提供的第一逻辑信号可以为高电平信号，以控制N型的第一晶体管导通；在第二预设时长和整个第二时间段内，第一晶体管需要断开，此时第一控制信号线提供的第二逻辑信号可以为低电平信号，以控制N型的第一晶体管断开；
在第一晶体管为P型晶体管时，在第一预设时长内，第一晶体管需要导通以形成充电路，此时第一控制信号线提供的第一逻辑信号可以为低电平信号，以控制P型的第一晶体管导通；在第二预设时长和整个第二时间段内，第一晶体管需要断开，此时第一控制信号线提供的第二逻辑信号可以为高电平信号，以控制P型的第一晶体管断开。
结合图9所示的时序图，以正载波信号为三角波信号，第一晶体管G1为N型晶体管为例，Vac指示的曲线表示电源输入端AC提供的交流信号，VcarrA表示正载波信号，T1表示第一时间段，T2表示第二时间段；那么：
在T1中的t1内，交流信号Vac的值(指的是t1内任一时刻的值)大于或等于正载波信号VcarrA的值，第一控制信号线k1在t1内提供高电平信号，使得第一晶体管G1在t1内导通以构成充电回路，以便于将处于正半周的交流信号Vac存储至第一电感L1中；此时t1为第一预设时长；
在T1中的t2内，交流信号Vac的值(指的是t2内任一时刻的值)小于正载波信号VcarrA的值，第一控制信号线k1在t2内提供低电平信号，使得第一晶体管G1在t2内断开，以便于将存储至第一电感L1的电能通过第一二极管D1转移至电容C中；此时t2为第二预设时长；并且，在T1内，t1和t2交替出现；
在T2内，由于不需要第一晶体管G1参与到信号处理的过程中，所以在T2内第一控制信号线k1始终提供低电平信号，以确定第一晶体管G1在T2内保持断开。
其中，在图9中示出了第一电感的电流变化趋势，如iL1所示，且iL1与处于正半周的交流信号Vac(可以理解为交流电压)的变化趋势类似，实现了对交流信号Vac的追随效果。
1.2、第二控制信号线可以按照以下方式提供信号：
在一些实施例中，结合图9所示，在第一时间段T1内，第一晶闸管SCR1需要保持导通状态，所以第二控制信号线k2可以在第一时间段T1内提供脉冲信号，第一时间段T1的起始时刻处于第一个有效脉冲内，使得在第一时间段T1的起始时刻，在第一晶闸管SCR1的正极电位高于负极电位的情况下，在向门极施加的有效脉冲的驱动下，即可控制第一晶闸管SCR1导通，以便于对交流信号Vac进行处理。
并且，对于该脉冲信号而言，有效脉冲的宽度为2μs至10μs，相邻两个有效脉冲之间的时间间隔为2ms；这样设置的原因在于：
在目前技术中，向晶闸管的门极提供脉冲信号时，提供的脉冲信号包括双脉冲信号和宽脉冲信号，其中，双脉冲信号为每隔70°连续输出两个有效脉冲，且每个有效脉冲的宽度为10°，连续两个有效脉冲之间的时间间隔其实是非常短的，远小于2ms；该种脉冲信号可能会存在诸如交流信号过零点时无有效脉冲输出的情况，导致在交流信号过零点时可能会出现晶闸管无法导通的情况，这样会导致图腾柱PFC电路无法正常工作，进一步导致图腾柱PFC电路在对交流信号进行处理时出现异常；
宽脉冲信号为每隔70°输出一个具有较大脉宽的有效脉冲，使得每个有效脉冲的脉冲宽度较大，这样会导致晶闸管的门极大部分时间都在被施加驱动，进一步地导致晶闸管的消耗增加，使得反向恢复电流(也即漏电流)也相应增加，最终导致开关频率的降低；
在本申请中实施例中，向门极提供的脉冲信号中有效脉冲的宽度为2μs至10μs，相邻两个有效脉冲之间的时间间隔为2ms，这样可以避免有效脉冲的宽度较大，进而避免第一晶闸管的消耗增加及反向恢复电流增加；再结合第一时间段的起始时刻处于第一个有效脉冲内，即使交流信号过零点时，第一晶闸管的门极也依然会被施加驱动，避免交流信号过零点时可能会出现晶闸管无法导通的情况，从而在保证图腾柱PFC电路正常工作的同时，还可以提高开关频率。
进一步地，在一些实施例中，还可以对第二控制信号线提供的有效脉冲进行进一步地设置，例如可以对第一个有效脉冲的上升沿和下降沿进行设置，具体的设置方式可以包括：
对于任一正半周，处于该正半周的交流信号的值等于预设值的多个时刻中的最早时刻与第一个有效脉冲的下降沿对齐；
对于位于该正半周之前且与该正半周相邻的负半周，处于该负半周的交流信号的绝对值等于预设值的多个时刻中的最晚时刻与第一个有效脉冲的上升沿对齐。
其中，预设值可以但不限于为10V，当然还可以为5V、8V或13V等其他数值，具体可以根据实 际需要进行设置，在此并不限定。
例如，结合图10所示，预设值为V0/2，左侧正半周的交流信号Vac的值等于V0/2的时刻具有两个，一个位于左侧正半周的开头，另一个为左侧正半周的结尾，显然位于左侧正半周的开头的值对应的时刻早于位于左侧正半周的结尾的值对应的时刻，所以可以将位于左侧正半周的开头的值对应的时刻与第一个有效脉冲的下降沿对齐；
并且，虽然图中仅示出了一个正半周的交流信号Vac和一个负半周的交流信号Vac，但在实际情况中，交流信号Vac的长度并不限于此，在图中所示的正半周的左侧，以及图中所示的负半周的右侧均具有与图中所示的这一段波形完全相同的交流信号Vac，只是在图中未示出而已；
因此，对于位于右侧负半周的交流信号Vac之后的正半周交流信号Vac而言，右侧负半周交流信号Vac与其之后的正半周交流信号Vac相邻且位于其之前，右侧负半周交流信号Vac的绝对值等于V0/2的时刻同样具有两个，一个位于右侧负半周的开头，另一个为右侧负半周的结尾，显然位于右侧负半周的开头的值对应的时刻早于位于右侧负半周的结尾的值对应的时刻，所以可以将位于右侧负半周的结尾的值对应的时刻与第一个有效脉冲的上升沿对齐。
如此，可以确保第一时间段的起始时刻处于第一个有效脉冲内，在交流信号过零点时，第一晶闸管的门极也依然会被施加驱动，避免交流信号过零点时可能会出现晶闸管无法导通的情况，从而在保证图腾柱PFC电路正常工作的同时，还可以提高开关频率。
在一些实施例中，第二控制信号线k2提供的脉冲信号中的各有效脉冲的宽度可以均设置为相同，如图9所示，这样可以降低提供的脉冲信号的复杂度，提高控制的精度，避免出现控制误差；
或者，第二控制信号线k2提供的脉冲信号中的各有效脉冲的宽度可以设置为部分相同，如图10所示，第一个有效脉冲的宽度较大，其余的有效脉冲的宽度较小且相同，如此可以有效保证交流信号Vac过零点时第一晶闸管SCR1的门极被施加驱动，保证在过零点时第一晶闸管SCR1处于导通状态，从而保证图腾柱PFC电路正常工作。
2、针对处于负半周的交流信号。
在一些实施例中，在软启动模块10包括：第一电感L1、第二电感L2、第一软启动单元11和第二软启动单元12时，通过第二二极管D2，将处于负半周的交流信号传输至正母线Vb+和负母线Vb-，并存储至电容C中，可以具体包括：
在电源输入端AC提供的交流信号处于负半周时，即图4中所示的第一节点P1处于负电位，第二节点P2处于正电位时，在第三预设时长内，第二软启动单元12首先将处于负半周的交流信号存储至第二电感L2中，为第二电感L2充电，以将电源输入端AC提供的电能储存在第二电感L2中；在第四预设时长内，第二软启动单元12再将第二电感L2中存储的电能通过第二二极管D2转移至电容C中，为电容C充电，以将电源输入端AC提供的电能转移电容C中；
其中，如图9所示，在第二时间段T2内可以划分出多个第三预设时长t3和第四预设时长t4，各第三预设时长t3和各第四预设时长t4交替设置，例如，第三预设时长t3、第四预设时长t4、第三预设时长t3、第四预设时长t4……这样交替地排列设置。
这样，在第二时间段，各第三预设时长和各第四预设时长交替设置，而第三预设时长内进行充电过程，第四预设时长内进行放电过程，所以充电过程和放电过程交替进行，从而实现对处于负半周的交流信号的功率因数校正处理。
在一些实施例中，第三预设时长和第四预设时长的设置，可以根据电源输入端提供的交流信号与设定的载波信号的大小关系进行确定；例如，将交流信号的值大于或等于设定的负载波信号的值的时间段设置为第三预设时长，将交流信号的值小于设定的负载波信号的值的时间段设置为第四预设时长。
当然，第三预设时长和第四预设时长，还可以根据其他方式进行设置，在此并不限定；
其中，对于其他方式，例如但不限于包括：
若将相邻的第三预设时长和第四预设时长看作是一个重复周期时，各重复周期的大小可以是相同的，将每个重复周期进行等分以划分出第三预设时长和第四预设时长。
在一些实施例中，结合图4所示的结构，在第二软启动单元12包括：第二晶体管G2和第二晶闸管SCR2，且第二晶体管G2的控制极与第三控制信号线k3电连接，第二晶闸管SCR2的门极与第四控制信号线k4电连接时，那么：
1、第三控制信号线可以按照以下方式提供信号：
在第二时间段的第三预设时长内，第三控制信号线提供第一逻辑信号；
在第二时间段的第四预设时长内、以及第一时间段内，第三控制信号线均提供第二逻辑信号。
其中，第一逻辑信号和第二逻辑信号的设置方式，可以参见上述内容中的相关描述，重复之处不再赘述。
结合图9所示的时序图，以负载波信号为三角波信号，第二晶体管G2为N型晶体管为例，VcarrB表示负载波信号，那么：
在T2中的t3内，交流信号Vac的值(指的是t3内任一时刻的值)大于或等于负载波信号VcarrB的值，第三控制信号线k3在t3内提供高电平信号，使得第二晶体管G2在t3内导通以构成充电回路，以便于将处于负半周的交流信号Vac存储至第二电感L2中；此时t3为第三预设时长；
在T2中的t4内，交流信号Vac的值(指的是t4内任一时刻的值)小于负载波信号VcarrB的值，第三控制信号线k3在t4内提供低电平信号，使得第二晶体管G2在t4内断开，以便于将存储至第二电感L2的电能通过第二二极管D2转移至电容C中；此时t4为第四预设时长；并且，在T2内，t3和t4是交替出现的；
在T1内，由于不需要第二晶体管G2参与到信号处理的过程中，所以在T1内第三控制信号线k3始终提供低电平信号，以确定第二晶体管G2在T1内保持断开。
其中，在图9中示出了第二电感的电流变化趋势，如iL2所示，且iL2与处于负半周的交流信号Vac(可以理解为交流电压)的变化趋势类似，实现了对交流信号Vac的追随效果。
2、第四控制信号线可以按照以下方式提供信号：
在一些实施例中，结合图9所示，在第二时间段T2内，第二晶闸管SCR2需要保持导通状态，所以第四控制信号线k4可以在第二时间段T2内提供脉冲信号，第二时间段T2的起始时刻处于第一个有效脉冲内，使得在第二时间段T2的起始时刻，在第二晶闸管SCR2的正极电位高于负极电位的情况下，在向门极施加的有效脉冲的驱动下，即可控制第二晶闸管SCR2导通，以便于对交流信号Vac进行处理。
并且，对于该脉冲信号而言，有效脉冲的宽度为2μs至10μs，相邻两个有效脉冲之间的时间间隔为2ms；这样设置的原因在于：
在目前技术中，向晶闸管的门极提供脉冲信号时，提供的脉冲信号包括双脉冲信号和宽脉冲信号，其中，双脉冲信号为每隔70°连续输出两个有效脉冲，且每个有效脉冲的宽度为10°，连续两个有效脉冲之间的时间间隔是非常短的，远小于2ms；该种脉冲信号可能会存在诸如交流信号过零点时无有效脉冲输出的情况，导致在交流信号过零点时可能会出现晶闸管无法导通的情况，这样会导致图腾柱PFC电路无法正常工作，进一步导致图腾柱PFC电路在对交流信号进行处理时出现异常；
宽脉冲信号为每隔70°输出一个具有较大脉宽的有效脉冲，使得每个有效脉冲的脉冲宽度较大，这样会导致晶闸管的门极大部分时间都在被施加驱动，进一步地导致晶闸管的消耗增加，使得反向恢复电流(也即漏电流)也相应增加，最终导致开关频率的降低；
在本申请中实施例中，向门极提供的脉冲信号中有效脉冲的宽度为2μs至10μs，相邻两个有效脉冲之间的时间间隔为2ms，这样可以避免有效脉冲的宽度较大，进而避免第二晶闸管的消耗增加及反向恢复电流增加；再结合第二时间段的起始时刻处于第一个有效脉冲内，即使交流信号过零点时，第二晶闸管的门极也依然会被施加驱动，避免交流信号过零点时可能会出现晶闸管无法导通的情况，从而在保证图腾柱PFC电路正常工作的同时，还可以提高开关频率。
进一步地，在一些实施例中，还可以对第四控制信号线提供的有效脉冲进行进一步地设置，例如可以对第一个有效脉冲的上升沿和下降沿进行设置，具体的设置方式可以包括：
对于任一负半周，处于该负半周的交流信号的绝对值等于预设值的多个时刻中的最早时刻与第一个有效脉冲的下降沿对齐；
对于位于该负半周之前且与该负半周相邻的正半周，处于该正半周的交流信号的值等于预设值的多个时刻中的最晚时刻与第一个有效脉冲的上升沿对齐。
其中，预设值可以但不限于为10V，当然还可以为5V、8V或13V等其他数值，具体可以根据实际需要进行设置，在此并不限定。
例如，结合图10所示，预设值为V0/2，右侧负半周的交流信号Vac的绝对值等于V0/2的时刻具有两个，一个位于右侧负半周的开头，另一个为右侧负半周的结尾，显然位于右侧负半周的开头的值对应的时刻早于位于右侧负半周的结尾的值对应的时刻，所以可以将位于右侧负半周的开头的值对应的时 刻与第一个有效脉冲的下降沿对齐；
并且，虽然图中仅示出了一个正半周的交流信号Vac和一个负半周的交流信号Vac，但在实际情况中，交流信号Vac的长度并不限于此，在图中所示的正半周的左侧，以及图中所示的负半周的右侧均具有与图中所示的这一段波形完全相同的交流信号Vac，只是在图中未示出而已；
因此，左侧正半周的交流信号Vac为与右侧负半周的交流信号Vac相邻且位于其之前的信号，所以左侧正半周交流信号Vac的绝对值等于V0/2的时刻同样具有两个，一个位于左侧正半周的开头，另一个为左侧正半周的结尾，显然位于左侧正半周的开头的值对应的时刻早于位于左侧正半周的结尾的值对应的时刻，所以可以将位于左侧正半周的结尾的值对应的时刻与第一个有效脉冲的上升沿对齐。
如此，可以确保第二时间段的起始时刻处于第一个有效脉冲内，在交流信号过零点时，第二晶闸管的门极也依然会被施加驱动，避免交流信号过零点时可能会出现晶闸管无法导通的情况，从而在保证图腾柱PFC电路正常工作的同时，还可以提高开关频率。
在一些实施例中，第四控制信号线k4提供的脉冲信号中的各有效脉冲的宽度可以均设置为相同，如图9所示，这样可以降低提供的脉冲信号的复杂度，提高控制的精度，避免出现控制误差；
或者，第四控制信号线k4提供的脉冲信号中的各有效脉冲的宽度可以设置为部分相同，如图10所示，第一个有效脉冲的宽度较大，其余的有效脉冲的宽度较小且相同，如此可以有效保证交流信号Vac过零点时第二晶闸管SCR2的门极被施加有驱动，保证在过零点时第二晶闸管SCR2处于导通状态，从而保证图腾柱PFC电路正常工作。
在一些实施例中，不管是位于正半周的交流信号，还是位于负半周的交流信号，在进行信号处理的过程中，并不会出现反向恢复电流，所以损耗较小，可以有效提高开关频率，其中开关频率可以至少为100KHz，在换算成时间时，可以确定出：
在正半周，若将相邻的第一预设时长和第二预设时长看作是一个重复周期时，该重复周期的时长最大为1/100KHz＝10μs，所以在第一预设时长和第二预设时长交替出现时，相邻的第一预设时长和第二预设时长之和最大为10μs；
在负半周，若将相邻的第三预设时长和第四预设时长看作是一个重复周期时，该重复周期的时长最大也为1/100KHz＝10μs，所以在第三预设时长和第四预设时长交替出现时，相邻的第三预设时长和第四预设时长之和最大依然为10μs。
如此，可以保证图腾柱PFC电路的开关频率至少为100KHz，有效提高了图腾柱PFC电路的开关频率，拓宽该图腾柱PFC电路的应用范围。
需要强调的是，在本申请实施例中，上述内容中介绍的图腾柱PFC电路及其控制方法，具有以下几点优势：
(1)本申请实施例采用了晶闸管、晶体管、二极管、电感和电容构建图腾柱PFC电路，不仅可以实现软启动，还可以提高开关频率；
(2)该图腾柱PFC电路由于采用了晶闸管，所以可以实现数字化的浪涌电流限制，有助于移除传统方案中采用继电器和电阻实现软启动功能的结构，简化了结构的复杂度，减小了图腾柱PFC电路的体积；
(3)晶闸管具有启动速度快的特点，启动速度在ms级别，可以实现图腾柱PFC电路的快速启动，有利于进一步提高图腾柱PFC电路的开关频率；
(4)晶闸管具有较好的抗电磁干扰性能，使得图腾柱PFC电路具有较好的电磁兼容性，从而可以拓宽图腾柱PFC电路在某些特殊领域(如军事领域)的应用。
基于同一技术构思，本申请实施例还提供了一种电源装置，如图11所示，包括：控制器101、以及如本申请实施例提供的上述图腾柱PFC电路102；
控制器101用于：控制图腾柱PFC电路102对电源输入端AC提供的交流信号进行处理。
在一些实施例中，如图11所示，控制器101可以与第一控制信号线k1、第二控制信号线k2、第三控制信号线k3和第四控制信号线k4电连接，通过控制器101可以使得各控制信号线可以提供相应的信号，以保证图腾柱PFC电路102正常工作的同时，实现软启动，提高开关频率。
在一些实施例中，电源装置除了可以包括控制器和图腾柱PFC电路之外，还可以包括其他可以用于实现电源装置的结构(例如但不限于为逆变器等)，在此并不限定。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (14)

  1. 一种图腾柱PFC电路，其特征在于，包括：软启动模块、第一二极管、第二二极管、以及电容；
    所述第一二极管和所述第二二极管均为碳化硅基二极管；
    所述电容设于正母线和负母线之间；
    所述软启动模块通过所述第一二极管与所述正母线电连接，通过所述第二二极管与所述负母线电连接，所述软启动模块还分别与所述正母线、所述负母线和电源输入端电连接；所述软启动模块用于：
    在所述电源输入端提供的交流信号处于正半周时，通过所述第一二极管，将处于所述正半周的所述交流信号传输至所述正母线和所述负母线，并存储至所述电容中；在所述交流信号处于负半周时，通过所述第二二极管，将处于所述负半周的所述交流信号传输至所述正母线和所述负母线，并存储至所述电容中。
  2. 如权利要求1所述的图腾柱PFC电路，其特征在于，所述软启动模块包括：第一电感、第二电感、第一软启动单元和第二软启动单元；
    所述第一电感的第一端与所述电源输入端的第一端电连接，所述第一电感的第二端分别与所述第一二极管的正极、所述第一软启动单元电连接；
    所述第一软启动单元分别与所述负母线和所述电源输入端的第二端电连接；
    所述第二电感的第一端与所述电源输入端的第一端电连接，所述第二电感的第二端分别与所述第二二极管的负极、所述第二软启动单元电连接；
    所述第二软启动单元分别与所述正母线和所述电源输入端的第二端电连接；
    所述第一软启动单元用于：在所述正半周时，在第一预设时长内，将处于所述正半周的所述交流信号存储至所述第一电感中，在第二预设时长内，将所述第一电感中存储的电能通过所述第一二极管转移至所述电容中；其中，在所述正半周内，所述第一预设时长和所述第二预设时长交替出现至少一次；
    所述第二软启动单元用于：在所述负半周时，在第三预设时长内，将处于所述负半周的所述交流信号存储至所述第二电感中，在第四预设时长内，将所述第二电感中存储的电能通过所述第二二极管转移至所述电容中；其中，在所述负半周内，所述第三预设时长和所述第四预设时长交替出现至少一次。
  3. 如权利要求2所述的图腾柱PFC电路，其特征在于，所述第一软启动单元包括：第一晶体管和第一晶闸管；
    所述第一晶体管的第一极分别与所述第一电感和所述第一二极管的正极电连接，所述第一晶体管的第二极分别与所述负母线和所述第一晶闸管的正极电连接，所述第一晶体管的控制极与第一控制信号线电连接；
    所述第一晶闸管的负极与所述电源输入端的第二端电连接，所述第一晶闸管的门极与第二控制信号线电连接。
  4. 如权利要求3所述的图腾柱PFC电路，其特征在于，所述第一晶体管为硅基晶体管。
  5. 如权利要求2所述的图腾柱PFC电路，其特征在于，所述第二软启动单元包括：第二晶体管和第二晶闸管；
    所述第二晶体管的第一极分别与所述第二电感和所述第二二极管的负极电连接，所述第二晶体管的第二极分别与所述正母线和所述第二晶闸管的负极电连接，所述第二晶体管的控制极与第三控制信号线电连接；
    所述第二晶闸管的正极与所述电源输入端的第二端电连接，所述第二晶闸管的门极与第四控制信号线电连接。
  6. 如权利要求5所述的图腾柱PFC电路，其特征在于，所述第二晶体管为硅基晶体管。
  7. 一种电源装置，其特征在于，包括：控制器、以及如权利要求1-6任一项所述的图腾柱PFC电路；
    所述控制器用于：控制所述图腾柱PFC电路对电源输入端提供的交流信号进行处理。
  8. 一种基于权利要求1-6任一项所述的图腾柱PFC电路的控制方法，其特征在于，包括：
    在电源输入端提供的交流信号处于正半周时，软启动模块通过第一二极管，将处于所述正半周的所述交流信号传输至正母线和负母线，并存储至电容中；
    在所述交流信号处于负半周时，所述软启动模块通过第二二极管，将处于所述负半周的所述交流信号传输至所述正母线和所述负母线，并存储至所述电容中。
  9. 如权利要求8所述的控制方法，其特征在于，所述软启动模块包括：第一电感、第二电感、第一软启动单元和第二软启动单元时，通过第一二极管，将处于所述正半周的所述交流信号传输至正母线和负母线，并存储至电容中，以及通过第二二极管，将处于所述负半周的所述交流信号传输至所述正母线和所述负母线，并存储至所述电容中，包括：
    在所述正半周时，在第一预设时长内，所述第一软启动单元将处于所述正半周的所述交流信号存储至所述第一电感中，在第二预设时长内，所述第一软启动单元将所述第一电感中存储的电能通过所述第一二极管转移至所述电容中；其中，所述交流信号处于所述正半周的时间为第一时间段，所述第一时间段内设有多个所述第一预设时长和多个所述第二预设时长，所述第一预设时长和所述第二预设时长交替设置；
    在所述负半周时，在第三预设时长内，所述第二软启动单元将处于所述负半周的所述交流信号存储至所述第二电感中，在第四预设时长内，将所述第二电感中存储的电能通过所述第二二极管转移至所述电容中；其中，所述交流信号处于所述负半周的时间为第二时间段，所述第二时间段内设有多个所述第三预设时长和多个所述第四预设时长，所述第三预设时长和所述第四预设时长交替设置。
  10. 如权利要求9所述的控制方法，其特征在于，所述第一软启动单元包括：第一晶体管和第一晶闸管，且所述第一晶体管的控制极与第一控制信号线电连接，所述第一晶闸管的门极与第二控制信号线电连接时，在所述第一时间段的所述第一预设时长内，所述第一控制信号线提供第一逻辑信号，在所述第一时间段的所述第二预设时长内，所述第一控制信号线提供第二逻辑信号；在所述第二时间段内，所述第一控制信号线提供所述第二逻辑信号；
    所述第二控制信号线在所述第一时间段内提供脉冲信号，所述脉冲信号的有效脉冲宽度为2μs至10μs，相邻两个有效脉冲之间的时间间隔为2ms，所述第一时间段的起始时刻处于第一个所述有效脉冲内。
  11. 如权利要求10所述的控制方法，其特征在于，对于任一所述正半周，处于该正半周的所述交流信号的值等于预设值的多个时刻中的最早时刻与第一个所述有效脉冲的下降沿对齐；
    对于位于该正半周之前且与该正半周相邻的所述负半周，处于该负半周的所述交流信号的绝对值等于所述预设值的多个时刻中的最晚时刻与第一个所述有效脉冲的上升沿对齐。
  12. 如权利要求9所述的控制方法，其特征在于，所述第二软启动单元包括：第二晶体管和第二晶闸管，且所述第二晶体管的控制极与第三控制信号线电连接，所述第二晶闸管的门极与第四控制信号线电连接时，在所述第二时间段的所述第三预设时长内，所述第三控制信号线提供第一逻辑信号，在所述第二时间段的所述第四预设时长内，所述第三控制信号线提供第二逻辑信号；在所述第一时间段内，所述第三控制信号线提供所述第二逻辑信号；
    所述第四控制信号线在所述第二时间段内提供脉冲信号，所述脉冲信号的有效脉冲宽度为2μs至10μs，相邻两个有效脉冲之间的时间间隔为2ms，所述第二时间段的起始时刻处于第一个所述有效脉冲内。
  13. 如权利要求12所述的控制方法，其特征在于，对于任一所述负半周，处于该负半周的所述交流信号的绝对值等于预设值的多个时刻中的最早时刻与第一个所述有效脉冲的下降沿对齐；
    对于位于该负半周之前且与该负半周相邻的所述正半周，处于该正半周的所述交流信号的值等于所述预设值的多个时刻中的最晚时刻与第一个所述有效脉冲的上升沿对齐。
  14. 如权利要求9-13任一项所述的控制方法，其特征在于，相邻的所述第一预设时长和所述第二预设时长之和、以及所述第三预设时长和所述第四预设时长之和均最大为10μs。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102130580A (zh) * 2011-03-30 2011-07-20 艾默生网络能源系统北美公司 一种图腾柱无桥功率因素校正电路
CN205610494U (zh) * 2016-04-07 2016-09-28 深圳市高斯宝电气技术有限公司 一种无桥pfc开关电源电路
US20160285353A1 (en) * 2015-03-27 2016-09-29 Samsung Electronics Co., Ltd. Switch driving circuit, and power factor correction circuit having the same
CN206023576U (zh) * 2016-08-12 2017-03-15 纵领电子(上海)有限公司 基于碳化硅二极管的Buck电路
CN111327186A (zh) * 2020-03-23 2020-06-23 上海空间电源研究所 一种无桥功率因数校正电路的电感电流过零检测方法
CN115580132A (zh) * 2022-09-09 2023-01-06 华为数字能源技术有限公司 一种图腾柱pfc电路、其控制方法及电源装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102130580A (zh) * 2011-03-30 2011-07-20 艾默生网络能源系统北美公司 一种图腾柱无桥功率因素校正电路
US20160285353A1 (en) * 2015-03-27 2016-09-29 Samsung Electronics Co., Ltd. Switch driving circuit, and power factor correction circuit having the same
CN205610494U (zh) * 2016-04-07 2016-09-28 深圳市高斯宝电气技术有限公司 一种无桥pfc开关电源电路
CN206023576U (zh) * 2016-08-12 2017-03-15 纵领电子(上海)有限公司 基于碳化硅二极管的Buck电路
CN111327186A (zh) * 2020-03-23 2020-06-23 上海空间电源研究所 一种无桥功率因数校正电路的电感电流过零检测方法
CN115580132A (zh) * 2022-09-09 2023-01-06 华为数字能源技术有限公司 一种图腾柱pfc电路、其控制方法及电源装置

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