WO2023124942A1

WO2023124942A1 - Embedded control circuit with dual-bus interface, and chip and electronic device

Info

Publication number: WO2023124942A1
Application number: PCT/CN2022/138407
Authority: WO
Inventors: 王世好
Original assignee: 合肥市芯海电子科技有限公司
Priority date: 2021-12-29
Filing date: 2022-12-12
Publication date: 2023-07-06
Also published as: CN114281722A; CN114281722B

Abstract

Provided in the present disclosure are an embedded control circuit with a dual-bus interface, and a chip and an electronic device. The embedded control circuit comprises: one or more peripheral modules; a processor, which is connected to the one or more peripheral modules; a first bus interface circuit, which is connected to the one or more peripheral modules; a second bus interface circuit, which is connected to the one or more peripheral modules; and a bus interface selection circuit, which is configured to communicate with a host processor and operatively connect the first bus interface circuit or the second bus interface circuit to the host processor. By means of the present disclosure, a peripheral can be accessed by means of at least two bus interfaces.

Description

Embedded control circuit, chip and electronic equipment with dual bus interface

technical field

The present disclosure relates to the technical field of electronic circuits, in particular to an embedded control circuit with a dual-bus interface, a chip and electronic equipment.

Background technique

In an electronic device such as a personal computer, an embedded controller (Embedded Controller, EC for short) manages at least some peripheral devices (peripherals for short). The processor of the electronic device (referred to as the host processor for short) and the processor of the embedded controller need to access these peripherals. In the related art, no effective solution has been proposed so far for how the host processor and the processor of the embedded controller can access the peripherals more efficiently, conveniently and reliably.

Contents of the invention

In view of this, the embodiments of the present disclosure provide an embedded control circuit, a chip and an electronic device with a dual-bus interface, so as to realize peripheral device access.

According to an aspect of the present disclosure, an embedded control circuit is provided, including: one or more peripheral modules; a processor connected to one or more peripheral modules; a first bus interface circuit connected to one or more The peripheral module is connected; the second bus interface circuit is connected to the one or more peripheral modules; the bus interface selection circuit is configured to communicate with the host processor and is operable to connect the first bus interface circuit or the second bus interface The circuit is connected to a host processor.

In some embodiments, the bus interface selection circuit is configured to connect the first bus interface circuit or the second bus interface circuit to the host processor based on the initialization configuration.

In some embodiments, the one or more peripheral modules include: one or more first peripheral modules, each of the one or more first peripheral modules includes a first interface and a first peripheral module Two interfaces; wherein, the embedded control circuit also includes: a first bus, connected between the first interface of each first peripheral module and the first bus interface circuit and the second bus interface circuit; the second bus, connected between Between the second interface of each first peripheral module and the processor; wherein, the first bus interface circuit and the second bus interface circuit are configured to access one or more first peripheral modules through the first bus; processing device configured to access one or more first peripheral modules through a second bus.

In some embodiments, at least one first peripheral module includes: an arbitration logic circuit, and the arbitration logic circuit is configured to: when the first peripheral module is accessed by the host processor, the second interface of the first peripheral module disconnecting from the second bus; and/or disconnecting the first interface of the first peripheral module from the first bus when the first peripheral module is accessed by the processor.

In some embodiments, the arbitration logic circuit is further configured to: connect the second interface of the first peripheral module to the second bus when the first peripheral module is released by the host processor; and/or When the module is released by the processor, the first interface of the first peripheral module is connected to the second bus.

In some embodiments, one or more peripheral modules include: one or more second peripheral modules; wherein, the embedded control circuit further includes: a circuit system; a third bus, connected to one or more second peripheral modules Set between the module and the circuit system, and between one or more second peripheral modules and the processor; wherein, the circuit system is configured to communicate with the host processor through the first bus interface circuit or the second bus interface circuit Communication, accessing one or more second peripheral modules through the third bus based on commands from the host processor; the processor is configured to access one or more second peripheral modules through the third bus.

In some embodiments, the first bus interface circuit and/or the second bus interface circuit are configured to: determine whether the host processor accesses the first peripheral module or the second peripheral module based on the target address of the access; In the case where the host processor accesses one or more first peripheral modules, the one or more first peripheral modules are accessed through the first bus; when the host processor accesses one or more second peripheral modules, the circuit The system forwards access commands from the host processor.

In some embodiments, the circuit system is configured to: determine whether the host processor accesses one or more second peripheral modules based on the target address of the access; In some cases, one or more second peripheral modules are accessed through the third bus based on commands from the host processor.

In some embodiments, the embedded control circuit further includes: a fourth bus connected between the processor and the circuit system.

In some embodiments, the processor is configured to: send interrupt information of one or more second peripheral modules to the circuit system through the fourth bus; the circuit system is configured to: through the first bus interface circuit or the second bus interface The circuit sends an interrupt message to the host processor.

In some embodiments, the circuitry is configured to access the one or more second peripheral modules based on preconfigured permissions.

In some embodiments, the embedded control circuit further includes: an interrupt signal line connected between the processor and the circuit system; the circuit system is configured to: the register of the second peripheral module accessed by the host processor is configured as When access is prohibited, an interrupt signal is transmitted to the processor through the interrupt signal line.

In some embodiments, at least one first peripheral module is configured to: determine whether the host processor accesses the first peripheral module based on the target address of the access; in the case that the host processor accesses the first peripheral module , in response to host processor access.

According to another aspect of the present disclosure, a chip is provided, including the embedded control circuit of the embodiment of the present disclosure.

According to still another aspect of the present disclosure, an electronic device is provided, including: the embedded control circuit of the embodiment of the present disclosure or the chip of the embodiment of the present disclosure.

One or more technical solutions provided in the embodiments of the present disclosure, the embedded control circuit includes one or more peripheral modules, a processor, connected to one or more peripheral modules; the first bus interface circuit and the second bus interface The circuit is connected with one or more peripheral modules; the bus interface selection circuit can communicate with the host processor and is operable to connect the first bus interface circuit or the second bus interface circuit to the host processor. Peripheral modules can be accessed via at least two bus interfaces.

Description of drawings

Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments with reference to the accompanying drawings in which:

FIG. 1 shows a schematic block diagram of an embedded control circuit based on a shared interface in an exemplary embodiment of the present disclosure;

FIG. 2 shows a schematic block diagram of a peripheral module 130 of an exemplary embodiment of the present disclosure;

FIG. 3 shows a schematic block diagram of an embedded control circuit based on an eSPI bus and a shared interface according to an exemplary embodiment of the present disclosure;

FIG. 4 shows a schematic block diagram of an embedded control circuit for direct memory access in an exemplary embodiment of the present disclosure;

FIG. 5 shows a flowchart of a direct memory access peripheral access method according to an exemplary embodiment of the present disclosure;

FIG. 6 shows a schematic block diagram of a circuit system 440 of an exemplary embodiment of the present disclosure;

7 shows a schematic block diagram of an embedded control circuit using an eSPI bus and direct memory access according to an exemplary embodiment of the present disclosure;

FIG. 8 shows a schematic block diagram of a circuit system 740 of an exemplary embodiment of the present disclosure;

FIG. 9 shows a schematic block diagram of an embedded control circuit based on a direct memory access and sharing interface according to an exemplary embodiment of the present disclosure;

FIG. 10 shows a flowchart of a method for accessing peripherals based on direct memory access and shared interfaces according to an exemplary embodiment of the present disclosure;

11 shows a schematic block diagram of an embedded control circuit based on a direct memory access and sharing interface using an eSPI bus according to an exemplary embodiment of the present disclosure;

12 shows a schematic block diagram of an embedded control circuit of a dual-bus interface in an exemplary embodiment of the present disclosure;

Fig. 13 shows a schematic block diagram of an embedded control circuit of an LPC-eSPI dual-bus interface according to an exemplary embodiment of the present disclosure.

Detailed ways

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the drawings, it should be understood that the disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein; A more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for exemplary purposes only, and are not intended to limit the protection scope of the present disclosure.

It should be understood that the various steps described in the method implementations of the present disclosure may be executed in different orders, and/or executed in parallel. Additionally, method embodiments may include additional steps and/or omit performing illustrated steps. The scope of the present disclosure is not limited in this respect.

As used herein, the term "comprise" and its variations are open-ended, ie "including but not limited to". The term "based on" is "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one further embodiment"; the term "some embodiments" means "at least some embodiments." Relevant definitions of other terms will be given in the description below. It should be noted that concepts such as "first" and "second" mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the sequence of functions performed by these devices, modules or units or interdependence.

It should be noted that the modifications of "one" and "multiple" mentioned in the present disclosure are illustrative and not restrictive, and those skilled in the art should understand that unless the context clearly indicates otherwise, it should be understood as "one or more" multiple".

The embodiment of the present disclosure relates to the improvement of the technical scheme of integrating the peripheral module in the embedded controller and accessing the peripheral module by the host processor and the processor of the embedded controller.

Some embodiments of the present disclosure relate to an embedded control circuit based on a shared interface, where a peripheral module is integrated in the embedded control circuit, the peripheral module includes two interfaces, and the host processor accesses the bus interface circuit and one interface of the peripheral module The peripheral module, the processor of the embedded control circuit accesses the peripheral module through another interface. In some embodiments, at least one peripheral module includes an interface unit for connecting peripherals. In some embodiments, at least one peripheral module corresponds to an interface unit for connecting peripherals, which is connected to the processor independently of the peripheral modules.

Some embodiments of the present disclosure relate to an embedded control circuit for direct memory access, where peripheral modules are integrated in the embedded control circuit, a circuit system is set in the embedded control circuit, and the host processor accesses the peripheral device through the bus interface circuit and the circuit system module, the processor of the embedded control circuit can access the peripheral module through the line between it and the peripheral module. In these embodiments, when the peripheral module is integrated in the embedded control circuit, the address of the peripheral module is opened to the host processor, and the host processor uses the address of the peripheral module to access the peripheral module without modifying the bus interface circuit. It is convenient to integrate peripheral modules in embedded control circuits.

Some embodiments of the present disclosure relate to an embedded control circuit with shared interface and direct memory access, and peripheral modules are integrated in the embedded control circuit. Some peripheral modules are peripheral modules that include two interfaces. The host processor can access the peripheral modules through one interface of these peripheral modules through the bus interface circuit. The processor of the embedded control circuit can access the peripheral modules through the other interface of these peripheral modules. An interface to access peripheral modules. Other peripheral modules are peripheral modules with direct memory access through circuitry, the host processor accesses the peripheral modules through the bus interface circuit and the circuitry, and the processor of the embedded control circuit can access these peripheral modules.

Some embodiments of the present disclosure relate to a bus interface circuit of an embedded control circuit. The bus interface circuit may include interface circuits of at least two bus protocols, and the bus interface selection circuit selects one of the interface circuits of at least two bus protocols to communicate with the host. Processor communication.

It should be understood that the "first bus", "second bus", "third bus" and "fourth bus" mentioned in the present disclosure only distinguish the transmission lines between different devices in some embodiments, which Different buses may be used, or at least part of the lines and interfaces may be shared through a bus matrix or the like. This disclosure does not limit it.

In the subsequent description of the present disclosure, the embodiments of the present disclosure can be combined arbitrarily. Exemplary embodiments of the present disclosure are described below.

The embodiment of the present disclosure provides an embedded control circuit based on a shared interface.

FIG. 1 shows a schematic block diagram of an embedded control circuit based on a shared interface in an exemplary embodiment of the present disclosure. As shown in FIG. 1 , the embedded control circuit 100 includes: a bus interface circuit for communicating with a host processor 110 , a processor 120 , a peripheral module 130 , a first bus 140 and a second bus 150 . A plurality of peripheral modules 130 are shown in FIG. 1, labeled as peripheral modules 130-1 through 130-n. Wherein, the first bus 140 is connected between the first interface of the peripheral module 130 and the bus interface circuit 110 , and the second bus 150 is connected between the second interface of each peripheral module 130 and the processor 120 . The bus interface circuit 110 accesses the peripheral module 130 through the first bus 140 . The processor 120 accesses the peripheral module 130 through the second bus 150 . Since the host processor and the processor 120 use different buses, the access to the peripheral modules does not interfere with each other, which can increase the bus bandwidth and improve the access speed. For example, the host processor can access the peripheral module 130 - 1 through the first bus 140 , while the processor 120 can access the peripheral module 130 - n through the second bus 150 .

In this embodiment, various types of bus interfaces can be used to communicate with the host processor, including but not limited to LPC (Low Pin Count, referred to as LPC) bus, serial peripheral interface (Serial Peripheral Interface, referred to as SPI) bus , Enhanced Serial Peripheral Interface (eSPI for short) bus, etc. The bus interface circuit 110 includes a bus interface or a plurality of bus interfaces. The bus interface circuit 110 is operable to use one of the plurality of bus interfaces for communication. This implementation does not limit this. In this embodiment, the bus interface circuit 110 can communicate with the host processor according to the bus protocol. As an example, the eSPI bus can be used between the embedded control circuit 100 and the host processor, the embedded control circuit 100 is a slave device (eSPI slave) in the eSPI bus, and the host processor is used as a master device (eSPI slave) in the eSPI bus. master), the bus interface 110 can be an eSPI slave module. This embodiment does not limit it.

In this embodiment, the first bus 140 may include any bus compatible with the bus interface circuit 110, and examples of the first bus 140 may include a local bus (local bus), an advanced extensible interface (Advanced eXtensible Interface, referred to as AXI) Bus, Advanced Peripheral Bus (Advanced Peripheral Bus, APB for short), etc., are not limited in this implementation.

In this embodiment, the second bus 150 may include any bus compatible with the processor 120, and examples of the second bus 150 may include a local bus (local bus), an advanced extensible interface (Advanced eXtensible Interface, referred to as AXI) bus , Advanced Peripheral Bus (Advanced Peripheral Bus, APB for short), etc., which are not limited in this implementation.

In this embodiment, the I/O interface corresponding to each peripheral module 130 is defined on the bus interface circuit 110 . In the present disclosure, an interface may also be referred to as a port, and is collectively referred to as an interface in the description of the present disclosure.

In this embodiment, the peripheral module 130 may include some circuit modules of various peripheral devices. Examples of peripheral devices include mouse, keyboard, USB, PD/TYPE-C, breathing light, ambient light and so on. This implementation does not limit this.

In some embodiments, the peripheral module 130 may include an interface unit for connecting peripherals. As an implementation, the peripheral module 130 comprising an interface unit for connecting peripherals acquires data from the peripherals connected to the interface unit, and/or provides data to the peripherals connected to it, and the peripheral module 130 communicates with the host Communication between processors may not go through the processor 120 . In this embodiment, the processor 120 can read and/or write to the peripheral module 130 through the second bus 150 , for example, configured as parameters of the peripheral module 130 . The host processor can read and/or write the peripheral module 130 through the bus interface circuit 110 and the first bus 140, for example, write data to the peripheral module 130 to be sent by a peripheral connected thereto, or read data from the peripheral module 130 130 reads data from its connected peripherals, or configures parameters of the peripheral module 130, etc. Examples of the peripheral module 130 including an interface unit for connecting peripherals include a serial interface module (such as a UART serial port, etc.), and the serial interface module includes an interface unit that is used to connect a serial communication physical interface (such as a UART Connector). The serial interface module and serial communication physical interface can adopt serial communication interface standards such as RS-232C, RS-422, RS-423 and RS-485.

In some embodiments, the interface unit corresponding to the peripheral module 130 for connecting peripherals is connected to the processor 120 independently of the peripheral module 130 . The processor 120 may provide data from the peripheral module 130 to the interface unit corresponding to the peripheral module 130, or provide data from the interface unit to the peripheral module 130 corresponding to the interface unit. The host processor can provide data to the peripheral module 130, and the data provided by the host processor to the peripheral module 130 can be provided to the corresponding interface unit of the peripheral module 130 via the processor 120; the processor 120 can provide the data of the interface unit to The peripheral module 130 corresponding to the interface unit, the host processor can obtain the data from the peripheral module 130 . Generally, the processor 120 can be connected to an interface unit independent of the peripheral module 130 through a fast bus or the like. An example of an interface unit for connecting peripherals connected to the processor 120 independently of the peripherals module 130 includes a keyboard interface unit. As an example, the keyboard controller located on the keyboard detects the pressing and release of the key, and sends the keyboard code to the keyboard interface unit, and the processor 120 detects that the keyboard interface unit receives the keyboard code, and the processor 120 provides the keyboard code to the keyboard The peripheral module 130 corresponding to the interface unit.

In some embodiments, part of the peripheral module 130 includes an interface unit for connecting to a peripheral, the part of the peripheral module 130 obtains data from the peripheral connected to the interface unit, and/or provides data to the connected peripheral, Communications between the peripheral module 130 and the host processor may not go through the processor 120 . The interface units for connecting peripherals corresponding to some peripheral modules 130 are connected to the processor 120 independently of the peripheral modules 130. The processor 120 may provide data from the peripheral module 130 to the interface unit corresponding to the peripheral module 130, or provide data from the interface unit to the peripheral module 130 corresponding to the interface unit. The host processor can provide data to the peripheral module 130, and the data provided by the host processor to the peripheral module 130 can be provided to the corresponding interface unit of the peripheral module 130 via the processor 120; the processor 120 can provide the data of the interface unit to The peripheral module 130 corresponding to the interface unit, the host processor can obtain the data from the peripheral module 130 .

As an example, the peripheral module 130 includes a keyboard module and a serial interface module, wherein the interface unit (called the keyboard interface unit) of the keyboard module is independent from the keyboard module, the keyboard interface unit is connected to the processor 120, and the serial interface module Including the interface unit used to connect the serial communication physical interface.

In this example, the serial interface module receives the data sent by the host processor through the bus interface circuit 110, and sends the data through the serial communication physical interface; receives data through the serial communication physical interface, and the data received by the serial interface module serial communication physical interface The data is sent to the host processor through the bus interface circuit 110, and the data transmission is not processed by the processor 120. The processor 120 can configure the serial interface module through the second bus 150 , or the host processor can configure the serial interface module through the bus interface circuit 110 and the first bus 140 .

In this example, the processor 120 may provide data from the keyboard module to the keyboard interface unit, or provide data from the keyboard interface unit to the keyboard module. The host processor can provide data to the keyboard module, and the data provided by the host processor to the keyboard module can be provided to the keyboard interface unit through the processor 120; the processor 120 can provide the data of the keyboard interface unit to the keyboard module 130, and the host processor can provide This data is obtained from the keyboard module 130 . For example, the processor 120 obtains the keyboard code from the keyboard interface unit, provides the keyboard code to the keyboard module, and the host processor reads the keyboard code from the keyboard module through the bus interface circuit 110 .

In some embodiments, the bus interface circuit 110 is configured to receive a write command from the host processor, and write data to the register of the peripheral module 130 corresponding to the write command through the first bus 140 . In some embodiments, the bus interface circuit 110 is configured to receive a read command from the host processor, and read data from the register of the peripheral module 130 corresponding to the read command through the first bus 140 .

In some embodiments, the processor 120 is configured to read data from registers of the peripheral module 130 through the second bus 150 . In some embodiments, the processor 120 is configured to write data to the registers of the peripheral module 130 through the second bus 150 .

In some embodiments, the peripheral module 130 communicates with the peripheral through the processor 120, and the processor 120 is used to receive the input of the peripheral, and send the corresponding peripheral module 130 to the corresponding peripheral through the second bus 150 based on the received input. Register write data.

In some embodiments, as shown in FIG. 2, the peripheral module 130 may include one or more registers 131 that are controlled by the processor 120 (via the second bus 150) and the host processor (via the bus interface circuit 110 and first bus 140) for reading and/or writing. The processor 120 reads and/or writes one or more registers 131 of the peripheral module 130 through the second interface of the peripheral module 130 . The bus interface circuit 110 reads and/or writes one or more registers 131 of the peripheral module 130 through the first interface of the peripheral module 130 . The peripheral module 130 can set one or more registers 131 based on its functions, and examples of the registers 131 of the peripheral module 130 can include: configuration registers, status registers, control registers, read data registers, or write data registers.

In some embodiments, as shown in FIG. 2 , the peripheral module 130 may include one or more functional circuits 132 , and the one or more functional circuits together with the peripheral implement the functions of the peripheral. Examples of the peripheral module 130 include a serial interface module, the serial interface module is used to connect to a serial communication physical interface, the functional circuit of the serial interface module includes a level conversion circuit, and the level conversion circuit is based on the serial communication interface standard. Flat conversion. Another example of the peripheral module 130 includes a light-emitting unit control module, which is used to connect one or more light-emitting units (such as light-emitting diodes). The functional circuit of the light-emitting unit control module may include a controller, and the controller controls one or more light-emitting units. The plurality of light emitting units emit light.

In some embodiments, as shown in FIG. 2 , the peripheral module 130 includes: an arbitration logic circuit 133 connected to the first bus 140 and the second bus 150 . The arbitration logic circuit 133 is used to arbitrate access requests from the processor 120 and the host processor (via the bus interface circuit 110).

As an implementation manner, as shown in FIG. 2 , the arbitration logic circuit 133 is configured to connect to the arbitration control register 134 to provide the arbitration logic circuit 133 with an arbitration policy. As an implementation manner, the processor 120 is also connected to the arbitration control register 134 to write an arbitration policy into the arbitration control register 134 . As an example, the arbitration control register 134 is located outside the peripheral module 130, which is not limited in this embodiment.

As an implementation manner, the arbitration logic circuit 133 disconnects the second interface of the peripheral module 130 from the second bus 150 when the peripheral module 130 is accessed by the host processor. As an implementation manner, the arbitration logic circuit 133 disconnects the first interface of the peripheral module 130 from the first bus 140 when the peripheral module 130 is accessed by the processor 120 . Arbitration can be avoided every time the host processor and the processor 120 access, and the efficiency problem and potential function problem caused by the complex arbitration logic of the single bus can be avoided.

As an implementation manner, the arbitration logic circuit 133 connects the second interface of the peripheral module to the second bus 150 when the peripheral module 130 is released by the host processor. As an implementation manner, the arbitration logic circuit 133 connects the first interface of the peripheral module 130 to the second bus 150 when the peripheral module 130 is released by the processor 120 .

The peripheral module 130 communicates at least part of the information with the processor 120 and/or the host processor (via the bus interface circuit 110 ) through an interrupt.

In some embodiments, as shown in FIG. 2 , the peripheral module 130 further includes: a first interrupt unit 135 . The first interrupt unit 135 can be used to send write-related interrupt information. This embodiment does not limit it.

As an implementation manner, the first interrupt unit 135 is configured to: send the first interrupt information to the bus interface circuit 110 after the register 131 of the peripheral module 130 is written with data by the processor 120. The bus interface circuit 110 transmits the first interrupt information to the host processor, and can read and/or write the register 131 of the peripheral module 130 in response to a command from the host processor. And/or, after data is written into the register 131 of the peripheral module 130 by the host processor, the second interrupt information is sent to the processor 120 . The processor 120 may read and/or write the register 131 of the peripheral module 130 in response to the second interrupt information.

As another implementation manner, the first interrupt unit 135 is configured to: send first interrupt information to the bus interface circuit 110 after the register 131 of the peripheral module 130 is written with data by a peripheral connected thereto. The bus interface circuit 110 transmits the first interrupt information to the host processor, and can read and/or write the register 131 of the peripheral module 130 in response to a command from the host processor. In some cases, after the register 131 of the peripheral module 130 is written with data by the host processor, the peripheral module 130 and its connected peripherals send data.

In some embodiments, as shown in FIG. 2 , at least one peripheral module 130 further includes: a second interrupt unit 136 . The first interrupt unit 135 can be used to send read-related interrupt information. This embodiment does not limit it.

As an implementation manner, the second interrupt unit 136 is configured to send third interrupt information to the host processor after the data written by the host processor in the register 131 of the peripheral module 130 is read by the processor 120 . And/or, after the data written by the processor 120 in the register 131 of the peripheral module 130 is read by the host processor, the fourth interrupt information is sent to the processor 120 .

In some embodiments, the processor 120 is used to: detect whether the register of the peripheral module 130 is written with data by the host processor; The second bus 150 reads data from the registers of the corresponding peripheral modules 130 . In some cases, the processor 120 may send the read data to a peripheral interface unit connected thereto and corresponding to the peripheral module.

In some embodiments, the bus interface circuit 110 is further configured to set the first flag bit of the register corresponding to the peripheral module 130 as read after reading data from the register of the peripheral module 130 . In some embodiments, the processor 120 is further configured to query the first flag bit of the register of the peripheral module 130, and determine whether the data in the register of the corresponding peripheral module 130 is read by the host processor based on the first flag bit .

Taking the eSPI bus as an example, the embedded control circuit based on the shared structure of the exemplary embodiment of the present disclosure is described below, and the communication between the host processor and the embedded control circuit is performed through the eSPI bus.

FIG. 3 shows a schematic block diagram of an embedded control circuit based on an eSPI bus and a shared interface in an exemplary embodiment of the present disclosure. As shown in FIG. 3 , the embedded control circuit 300 includes: eSPI slave module 310 , processor 320 , peripheral module 330 , first bus 340 and second bus 350 . FIG. 3 shows a plurality of peripheral modules 330, including a keyboard module 330-1, a mouse module 330-2, a serial port module 330-3, and other peripherals 330-n. Among them, the first bus 340 is connected between the first interface of the keyboard module 330-1, the mouse module 330-2, the serial port module 330-3, and other peripherals 330-n and the eSPI slave module 310, and the second bus 350 is connected Between the second interface of the peripheral module 330 and the processor 320 . The eSPI slave module 310 accesses the peripheral module 330 through the first bus 340 . The processor 320 accesses the peripheral module 330 through the second bus 350 .

The embedded control circuit 300 passes through the eSPI interface between the host processor and the embedded control circuit 300 and the IO interface that is located on the embedded control circuit 300 and can be accessed by the host processor (this interface is defined on the eSPI slave module, which is address accessible by the host processor) to manage peripherals.

In this embodiment, the keyboard module 330-1, the mouse module 330-2, the serial port module 330-3, and other peripherals 330-n have two interfaces, which are respectively connected to the first bus 340 (such as the local bus 1) and on the second bus 350 (eg local bus 2). The read/write operations of the first bus 340 and the second bus 350 to the register are arbitrated by the access arbitration logic circuit, the arbitration strategy (selection priority) is selected by the arbitration control register, and the arbitration control is connected to an arbitration control register outside the module , the arbitration control register is configured by the processor 320 .

In this embodiment, as shown in FIG. 3 , a bus matrix 352 is used for connection. The processor 320 is connected to the bus matrix 352, and the second bus 350 (through the bridge 351) is connected to the bus matrix 352, and the second bus 350 is connected to the second interface of the peripheral module 330, and then the processor 320 communicates with the second bus matrix 352 through the bus matrix 352. Bus 352 accesses peripheral modules 330 . The peripheral module 330 corresponds to and is independent of the peripheral module 330 and the interface unit (such as a keyboard interface unit) connected to the processor 320 is connected to the bus matrix 352 through a bus such as a fast bus, and then the processor 320 and the interface unit are connected to the bus matrix 352 through a bus. The matrix 352 communicates with an associated bus.

Taking the serial port as an example, the register of the serial port module 330-3 has two interfaces, one interface is connected to the host processor through the first bus 340, so that the host processor can configure or operate the serial port through this interface, and one interface is connected through the second bus 340 350 is connected to the processor 320, so that the processor 320 of the embedded control circuit 300 can configure and access the serial port through this interface. When the host processor and the processor 320 configure or operate the registers of the serial port through two different interfaces at the same time, the access arbitration mechanism gives the host processor or the processor 320 a higher access priority according to the configuration.

An exemplary serial port working process is described as follows. The serial port module 330 - 3 acquires data from and/or provides data to peripheral devices connected to its interface unit, and the communication between the serial port module 330 - 3 and the host processor may not go through the processor 120 . The host processor reads and/or writes to the serial port module 330-3, for example, writes data to the serial port module 330-3 to be sent by a peripheral device connected to it, or reads data from the serial port module 330-3 from its connection Peripheral data, or configure the parameters of the serial port module 330-3, etc.

An exemplary keyboard operation is described below. The keyboard interface unit corresponding to the keyboard module 330 - 1 is independent of the keyboard module 330 - 1 and connected to the processor 320 . When the computer operator presses a key on the keyboard, the processor 320 obtains the keyboard code corresponding to the action of the keyboard key through the keyboard interface unit, and writes the keyboard code into the keyboard module 330 through the bus matrix 352, the bridge 351, and the second bus 350 -1 in the register. The keyboard module 330-1 generates an interrupt from the module 310 through eSPI and reports it to the host processor. The host processor receives the interrupt, initiates a read operation, reads the keyboard code value in the register of the keyboard module 330-1, sets the code value has been read flag, and clears the corresponding register. The keyboard module 330-1 generates an interrupt, notifying the processor 320 that the host processor has read the keyboard code value. If there is no interrupt, the processor 320 can query the Status flag of the keyboard module 330-1 to determine whether the keyboard code value has been read by the host processor.

An embodiment of the present disclosure provides an embedded control circuit for direct memory access.

FIG. 4 shows a schematic block diagram of an embedded control circuit for direct memory access in an exemplary embodiment of the present disclosure. As shown in FIG. 4 , the embedded control circuit 400 includes: a bus interface circuit 410 for communicating with a host processor, Processor 420 , one or more peripheral modules 430 , circuitry 440 , first bus 450 and second bus 460 . In this embodiment, the embedded control circuit may include one or more peripheral modules 430 , for example, peripheral modules 430 - 1 to 430 - n are shown in FIG. 4 .

As shown in FIG. 4 , circuitry 440 is connected to bus interface circuit 410 . The first bus 450 is connected between the peripheral module 430 and the circuit system 440 ; the second bus 460 is connected between the peripheral module 430 and the processor 420 . Wherein, the circuit system 440 communicates with the host processor through the bus interface circuit 410 , and accesses the peripheral module 430 through the first bus 450 based on the commands of the host processor. The processor 420 is configured to access the peripheral module 430 through the second bus 460 . In this embodiment, the I/O interface of the peripheral module 430 may not be defined in the bus interface circuit 410, and the circuit system 440 is configured to access the peripheral module 430 through the first bus 450 based on the command of the host processor. Integrating (eg adding) the peripheral module 430 in the circuit may not modify the bus interface circuit.

In this embodiment, the circuit system 440 may use a direct memory access (DMA) command to access the peripheral module 430 .

In this embodiment, various types of bus interfaces can be used to communicate with the host processor, including but not limited to LPC bus, SPI bus, eSPI bus and so on. The bus interface circuit 410 includes a bus interface or a plurality of bus interfaces. The bus interface circuit 410 is operable to use one of the plurality of bus interfaces for communication. This implementation does not limit this. In this embodiment, the bus interface circuit 410 can communicate with the host processor according to the bus protocol. As an example, the eSPI bus can be used between the embedded control circuit 400 and the host processor, the embedded control circuit 400 is a slave device (eSPI slave) in the eSPI bus, and the host processor is used as a master device (eSPI slave) in the eSPI bus. master), the bus interface circuit 410 can be an eSPI slave module. This embodiment does not limit it.

In this embodiment, the first bus 450 may include any bus compatible with the peripheral module 430 and the circuit system 440. Examples of the first bus 450 may include a local bus, an AXI bus, APB, AHB, etc., which are not made in this implementation. limited. In this embodiment, the circuit system 440 may serve as a master device (master) of the first bus 450 , and the peripheral module 430 may serve as a slave device (slave) of the first bus 450 . The peripheral module 430 can respond to various bus commands sent by the circuit system 440 .

In this embodiment, the second bus 460 may include any bus compatible with the peripheral module 430 and the processor 420, and examples of the second bus 460 may include a local bus, an AXI bus, APB, AHB, etc., which are not made in this implementation. limited. In this embodiment, the processor 420 may serve as a master of the second bus 460 , and the peripheral module 430 may serve as a slave of the second bus 460 . The peripheral module 430 can respond to various bus commands sent by the processor 420 .

In some embodiments, the embedded control circuit 400 can use a bus matrix, through which the circuit system 440, the processor 420 and the peripheral module 430 can be accessed in parallel to improve access efficiency and reduce power consumption.

In this embodiment, the circuit system 440 can communicate with the host processor through the bus interface circuit 410, access the peripheral module 430 through the first bus 450 based on the command of the host processor, and the processor 420 can access the peripheral module 430 through the second bus 460 Set module 430 . FIG. 5 shows a flow chart of a peripheral device access method for direct memory access according to an exemplary embodiment of the present disclosure. As shown in FIG. 5 , the peripheral device access method includes step S501 and step S502. In step S501 , the circuit system 440 communicates with the host processor through the bus interface circuit 410 , and accesses the peripheral module 430 through the first bus 450 based on a command from the host processor. In step S502 , the processor 420 accesses the peripheral module 430 through the second bus 460 .

In some embodiments, in step S502 , the processor 420 writes data to the register of the peripheral module 430 through the second bus 460 . In some embodiments, in step S502 , the processor 420 reads data from the register of the peripheral module 430 through the second bus 460 .

In some embodiments, the circuit system 440 is configured to: receive a write command from the host processor through the bus interface circuit 410 , and write data to the register of the peripheral module 430 corresponding to the write command through the first bus 450 based on the write command. As an implementation, in step S501, the circuit system 440 receives the write command of the host processor through the bus interface circuit 410, and writes data to the register of the peripheral module 430 corresponding to the write command through the first bus 450 based on the write command. .

In some embodiments, the circuit system 440 is configured to: receive a read command from the host processor through the bus interface circuit 410 , and read data from the register of the peripheral module 430 corresponding to the read command through the first bus 450 based on the read command. As an implementation, in step S501, the circuit system 440 receives the read command of the host processor through the bus interface circuit 410, and reads data from the register of the peripheral module 430 corresponding to the read command through the first bus 450 based on the read command. .

In some embodiments, as shown in FIG. 4 , the embedded control circuit 400 further includes: a third bus 470 connected between the processor 420 and the circuit system 440 . Information can be transmitted between the circuit system 440 and the processor 420 through the third bus 470. Examples of information may include configuration of the circuit system 440 by the processor 420, interrupt information of the peripheral module 430 sent by the processor 420 to the host processor, etc. , which is not limited in this implementation. As an implementation manner, the processor 420 may serve as a master device (master) of the third bus 470 , and the circuit system 440 may serve as a slave device (slave) of the third bus 470 . The circuit system 440 can respond to various bus commands sent by the processor 420 .

In some embodiments, as shown in FIG. 4 , the embedded control circuit 400 further includes: an interrupt signal line 480 connected between the processor 420 and the circuit system 440 . The interrupt signal line 480 may be configured to transmit any interrupt signal between the processor 420 and the circuit system 440, which is not limited in this embodiment. As an implementation manner, the circuit system 440 is configured to transmit an interrupt signal to the processor 420 through the interrupt signal line 480 .

In some embodiments, circuitry 440 is configured to access peripheral module 430 based on preconfigured permissions. In this embodiment, each target address can be configured to allow reading and writing, or allow reading and prohibit writing, or allow writing and prohibit reading, which is not limited in this embodiment. As an implementation manner, the processor 420 configures the authority of the circuit system 440 to access the peripheral module 430 through the third bus 470 . The circuitry 440 is configured to access the peripheral module 430 based on the permission information configured by the processor 420 .

In some embodiments, the circuitry 440 is configured to access the peripheral module 430 based on pre-configured permissions, and when the registers of the peripheral module 430 accessed by the host processor are configured to prohibit access, the interrupt signal line 480 An interrupt signal is transmitted to the processor 420 to notify the processor 420 that the host processor requests access to a prohibited register.

As an implementation manner, an example of writing data to the peripheral module 430 under authority control is described as follows. The bus interface circuit 410 receives write commands from the host processor and sends the write commands to the circuitry 440 . The circuit system 440 receives the write command, and parses the write command to obtain the target address and the data to be written. The circuit system 440 judges whether the target address is an address that allows writing. If the target address is an address that allows writing, the circuit system 440 writes the above data into the register of the peripheral module 430 corresponding to the target address through the first bus 450 . In some examples, if the target address is a write-prohibited address, circuitry 440 transmits an interrupt signal to processor 420 via interrupt signal line 480 to notify processor 420 that the host processor requests access to the write-prohibited register.

As an implementation manner, an example of reading data from the peripheral module 430 under permission control is described as follows. The bus interface circuit 410 receives a read command from the host processor and sends the read command to the circuitry 440 . The circuit system 440 receives the read command and parses the read command to obtain the target address. The circuit system 440 determines whether the target address is an address that is allowed to be read. If the target address is an address that is allowed to be read, the circuit system 440 reads data from the register of the peripheral module 430 corresponding to the target address through the first bus 450 . After the read data, the circuit system 440 generates a bus command corresponding to the read command, and sends the bus command to the bus interface circuit 410 . The bus interface circuit 410 sends the bus command to the host processor, so that the host processor receives the bus command to obtain the read data. In some examples, if the target address is a read-prohibited address, circuitry 440 transmits an interrupt signal to processor 420 via interrupt signal line 480 to notify processor 420 that the host processor requests access to the read-prohibited register.

In some embodiments, the processor 420 sends the interrupt information of the peripheral module 430 to the circuit system 440 through the third bus 470 . Further, the circuit system 440 sends the interrupt information to the host processor through the bus interface circuit 410 .

As an implementation manner, an example in which the processor 420 sends the interrupt information of the peripheral module 430 to the host processor is described as follows. The processor 420 detects interrupt information of the peripheral module 430 . The processor 420 sends the detected interruption information to the circuit system 440 through the third bus 470 . The circuit system 440 generates a bus command corresponding to the interrupt information, and sends the generated bus command to the bus interface circuit 410. The bus interface circuit 410 sends the bus command to the host processor, so that the host processor receives the bus command to obtain the interrupt information. As an example, after obtaining the interrupt information, the host processor responds to the embedded control circuit based on the interrupt information. In some examples, the host processor initiates a process of writing data to the register of the peripheral module 430 corresponding to the interrupt information based on the interrupt information. In some examples, the host processor initiates a process of reading data from the register of the peripheral module 430 corresponding to the interrupt information based on the interrupt information.

FIG. 6 shows a schematic block diagram of a circuit system 440 of an exemplary embodiment of the present disclosure. As shown in FIG. 6 , the circuit system 440 includes: a receiving circuit 441 configured to receive a bus command sent by the bus interface circuit 410; an analysis circuit 442, connected to the receiving circuit 441, configured to parse the received bus command to obtain the target address; the first controller 443, connected to the parsing circuit 442, configured to access the register of the peripheral module 430 corresponding to the target address. In this embodiment, the parsing circuit 442 parses the bus command according to the bus interface protocol used by the bus interface circuit 410 .

In some embodiments, the bus command includes a write command, and the parsing circuit 442 parses the bus command to obtain target data, and the target address is an address to be written. The first controller 443 is configured to: write target data into the register of the peripheral module 430 corresponding to the target address.

As an implementation manner, an example of writing data to the peripheral module 430 is described as follows. The bus interface circuit 410 receives the write command from the host processor, and sends the write command to the receiving circuit 441 . The receiving circuit 441 receives the write command and sends the write command to the parsing circuit 442 . The parsing circuit 442 parses the write command to obtain the target address and the data to be written. The first controller 443 writes the above data into the register of the peripheral module 430 corresponding to the target address through the first bus 450 .

In some embodiments, the bus command includes a read command, and the target address obtained by parsing the bus command by the parsing circuit 422 is the address to be read.

In some embodiments, as shown in FIG. 6 , the circuit system 440 further includes a buffer module 444, which is connected between the receiving circuit 441 and the parsing circuit 442, and is used for buffering the received bus command for the parsing circuit 442 to parse the bus command .

As an implementation manner, an example of writing data to the peripheral module 430 is described as follows. The bus interface circuit 410 receives the write command from the host processor, and sends the write command to the receiving circuit 441 . The receiving circuit 441 receives the write command, and the receiving circuit 441 buffers the write command into the buffer module 444 . The parsing circuit 442 obtains the write command from the buffer module 444, and the parsing circuit 442 parses the write command to obtain the target address and the data to be written. The first controller 443 writes the above data into the register of the peripheral module 430 corresponding to the target address through the first bus 450 .

In some embodiments, as shown in FIG. 6 , the circuit system 440 further includes: a generating circuit 445 configured to generate a bus command; a sending circuit 446 connected to the generating circuit 445 and configured to send the generating circuit to the bus interface circuit 410 445 generated bus commands so that the generated bus commands are received by the host processor.

In some embodiments, the first controller 443 is also configured to send the data read from the target address to the generating circuit 445, so that the generating circuit 445 generates a corresponding bus command, and the sending circuit 446 sends the generated bus command sent to the bus interface circuit 410.

As an implementation manner, an example of reading data from the peripheral module 430 is described as follows. The bus interface circuit 410 receives the read command from the host processor and sends the read command to the receiving circuit 441 . The receiving circuit 441 receives the read command and sends the read command to the parsing circuit 442 . The parsing circuit 442 parses the read command to obtain the target address. The first controller 443 reads data from the register of the peripheral module 430 corresponding to the target address through the first bus 450 . The first controller 443 sends the read data to the generation circuit 445 . The generating circuit 445 generates a bus command corresponding to the read command, and sends the bus command to the sending circuit 446 . The sending circuit 446 sends the bus command to the bus interface circuit 410 . The bus interface circuit 410 sends the bus command to the host processor, so that the host processor receives the bus command to obtain the read data.

In some embodiments, as shown in FIG. 6 , the circuit system 440 further includes: a second controller 447 configured to receive information sent by the processor 420 through the third bus 470 .

In some embodiments, the second controller 447 is further configured to receive the interrupt information sent by the processor 420 through the third bus 470, and send the interrupt information to the generation circuit 445, so that the generation circuit 445 generates a corresponding bus command, And the generated bus command is sent to the bus interface circuit 410 by the sending circuit 446 , so as to send the interrupt information to the host processor through the bus interface circuit 410 .

As an implementation manner, an example in which the processor 420 sends the interrupt information of the peripheral module 430 to the host processor is described as follows. The processor 420 detects interrupt information of the peripheral module 430 . The processor 420 sends the detected interrupt information to the generating circuit 445 through the third bus 470 . The generating circuit 445 generates a bus command corresponding to the interrupt information. The transmission circuit 446 transmits the bus command generated by the generation circuit 445 to the bus interface circuit 410 . The bus interface circuit 410 sends the bus command to the host processor, so that the host processor receives the bus command to obtain the interrupt information. As an example, after obtaining the interrupt information, the host processor responds to the embedded control circuit based on the interrupt information. In some examples, the host processor initiates a process of writing data to the register of the peripheral module 430 corresponding to the interrupt information based on the interrupt information. In some examples, the host processor initiates a process of reading data from the register of the peripheral module 430 corresponding to the interrupt information based on the interrupt information.

In some embodiments, the circuit system 440 further includes: a security control module 448 connected to the first controller 443 and the second controller 447 . The security control module 448 is configured to provide permission information. The first controller 443 is further configured to determine the authority to access the target address based on the authority information in the security control module 448 . As an implementation manner, the second controller 447 is further configured to receive the permission information sent by the processor 420 through the third bus 470 , and write the permission information into the security control module 448 . In this embodiment, each target address can be configured to allow reading and writing, or allow reading and prohibit writing, or allow writing and prohibit reading, which is not limited in this embodiment.

As an implementation manner, an example of writing data to the peripheral module 430 under permission control is described as follows. The bus interface circuit 410 receives the write command from the host processor, and sends the write command to the receiving circuit 441 . The receiving circuit 441 receives the write command and sends the write command to the parsing circuit 442. As an example, the receiving circuit 441 can cache the write command in the buffer module 444, and the parsing circuit 442 obtains the write command from the buffer module 444. The parsing circuit 442 parses the write command to obtain the target address and the data to be written. The first controller 443 judges whether the target address is an address that allows writing. Write the above data. In some examples, the first controller 443 may access the security control module 448, acquire permission information from the security control module 448, and determine whether the target address is an address that is allowed to be written based on the permission information. In some examples, when the target address is an address prohibited from writing, the first controller 443 transmits an interrupt signal to the processor 420 through the interrupt signal line 480, so that the processor 420 knows that the host processor requests to write to the prohibited address. address to write data.

As an implementation manner, an example of reading data from the peripheral module 430 under permission control is described as follows. The bus interface circuit 410 receives the read command from the host processor and sends the read command to the receiving circuit 441 . The receiving circuit 441 receives the read command and sends the read command to the parsing circuit 442 , in some examples, the receiving circuit 441 buffers the read command into the buffer module 444 , and the parsing circuit 442 obtains the read command from the buffer module 444 . The parsing circuit 442 parses the read command to obtain the target address. The first controller 443 judges whether the target address is an address that allows reading. In some examples, the first controller 443 accesses the security control module 448, obtains permission information from the security control module 448, and determines whether the target address is permission based on the permission information. address to read. If the target address is an address that is allowed to be read, the first controller 443 reads data from the register of the peripheral module 430 corresponding to the target address through the first bus 450 . The first controller 443 sends the read data to the generation circuit 445 . The generating circuit 445 generates a bus command corresponding to the read command, and sends the bus command to the sending circuit 446 . The sending circuit 446 sends the bus command to the bus interface circuit 410 . The bus interface circuit 410 sends the bus command to the host processor, so that the host processor receives the bus command to obtain the read data. In some examples, when the target address is an address prohibited from reading, the first controller 443 transmits an interrupt signal to the processor 420 through the interrupt signal line 480, so that the processor 420 is informed that the host processor requests to read the read prohibited address. fetched address.

The embedded control circuit for direct memory access in the exemplary embodiment of the present disclosure is described below by taking the eSPI bus as an example, and the host processor communicates with the embedded control circuit through the eSPI bus.

FIG. 7 shows a schematic block diagram of an embedded control circuit using an eSPI bus and direct memory access according to an exemplary embodiment of the present disclosure. As shown in FIG. 7 , the embedded control circuit 700 includes: eSPI slave module 710 , processor 720 , one or more peripheral modules 730 , circuitry 740 . In this embodiment, the embedded control circuit may include one or more peripheral modules 730 , for example, peripheral modules 730 - 1 to 730 - n are shown in FIG. 7 .

As shown in FIG. 7, the circuit system 740 is connected to the eSPI slave module 710, and the eSPI slave module 710 communicates with the host processor using the eSPI protocol. The eSPI slave module 710, the processor 720, and the peripheral module 730 are connected through a bus matrix 750. In this embodiment, the bus matrix adopts an AHB bus. In this embodiment, the bus between the eSPI slave module 710, the processor 720, and the peripheral module 730 may include data lines, control lines and address lines.

In this embodiment, the circuit system 740 accesses the peripheral module 730 through the bus matrix 750 . On the AHB bus between the circuit system 740 and the peripheral module 730, the circuit system 740 acts as the master device (master) of the AHB bus, the peripheral module 730 acts as the slave device of the AHB bus, and the peripheral module 730 responds to each of the circuit system 740 A bus command.

In this embodiment, the processor 720 accesses the peripheral module 730 through the bus matrix 750 . On the AHB bus between the processor 720 and the peripheral module 730, the processor 720 acts as the master device (master) of the AHB bus, and the peripheral module 730 acts as the slave device (slave) of the AHB bus, and the peripheral module 730 responds to the processor Various bus commands of 720.

In this embodiment, the processor 720 accesses the circuit system 740 through the bus matrix 750 . On the AHB bus between the processor 720 and the circuit system 740, the processor 720 acts as a master device (master) of the AHB bus, and the circuit system 740 acts as a slave device (slave) of the AHB bus, and the circuit system 740 responds to each of the processor 720 A bus command. As an implementation manner, the processor 720 accesses the circuit system 740 through the bus matrix 750 to configure the access authority of the circuit system 740 to the peripheral module 730 . As another implementation manner, the processor 720 accesses the circuit system 740 through the bus matrix 750 to send interrupt information of the peripheral module 730 to the host processor.

In this embodiment, an interrupt signal line 760 is connected between the processor 720 and the circuit system 740 . Circuitry 740 is capable of sending an interrupt signal to circuitry 740 via interrupt signal line 760 .

FIG. 8 shows a schematic block diagram of a circuit system 740 of an exemplary embodiment of the present disclosure. As shown in FIG. 8 , the circuit system 740 includes: an eSPI command receiving module 741 configured to receive a bus command sent by the eSPI slave module 710; The command buffering module 744 is connected with the eSPI command receiving module 741 for buffering the received eSPI command; the eSPI command parsing module 742 is connected with the eSPI command receiving module 741 and is configured to parse the received eSPI command to obtain the target address; AHB The master interface 743 is connected with the eSPI command analysis module 742 and configured to access the registers of the peripheral module 730 corresponding to the target address.

The eSPI command includes a write command, and the eSPI command parsing module 742 parses the eSPI command to obtain target data, and the target address is the address to be written. The AHB master interface 743 is configured to: write target data to the register of the peripheral module 730 corresponding to the target address.

As an implementation manner, an example of writing data to the peripheral module 730 is described as follows. The eSPI slave module 710 receives a write command from the host processor, and sends the write command to the eSPI command receiving module 741 . The eSPI command receiving module 741 receives the write command, and writes the write command into the command buffer module 744 . The eSPI command parsing circuit 742 obtains the write command from the command buffer module 744, and parses the write command to obtain the target address and the data to be written. The AHB master interface 743 writes the above data into the register of the peripheral module 730 corresponding to the target address through the bus matrix 750.

As shown in Figure 8, the circuit system 740 also includes: an eSPI command generating module 745 configured to generate an eSPI command; an eSPI command sending module 746 connected to the eSPI command generating module 745 and configured to send an eSPI command to the eSPI slave module 710 The eSPI command generated by the generating module 745, so that the generated eSPI command is received by the host processor.

eSPI commands include read commands. The AHB master interface 743 is also configured to: after reading the data, send the data read from the target address to the eSPI command generation module 745, so that the corresponding eSPI command is generated by the eSPI command generation module 745, and the eSPI command transmission module 746 sends the generated eSPI command to the eSPI slave module 710 .

As an implementation manner, an example of reading data from the peripheral module 730 is described as follows. After the AHB master interface 743 reads data from the target address, the AHB master interface 743 sends the read data to the eSPI command generation module 745. The eSPI command generating module 745 generates an eSPI command corresponding to the read command, and sends the eSPI command to the eSPI command sending module 746 . The eSPI command sending module 746 sends the eSPI command to the eSPI slave module 710 . The eSPI slave module 710 sends the eSPI command to the host processor, so that the host processor receives the eSPI command to obtain the read data.

As shown in FIG. 8 , the circuit system 740 further includes: an AHB slave interface 747 configured to receive information sent by the processor 720 through the bus matrix 750 . The AHB slave interface 747 is configured to receive the interrupt information sent by the processor 720 through the bus matrix 750, and send the interrupt information to the eSPI command generating module 745, so that the eSPI command generating module 745 generates a corresponding eSPI command, and the eSPI command sending module 746 sends the generated eSPI command to the eSPI slave module 710 , thereby sending interrupt information to the host processor through the eSPI slave module 710 .

As an implementation manner, an example in which the processor 720 sends the interrupt information of the peripheral module 730 to the host processor is described as follows. The processor 720 detects interrupt information of the peripheral module 730 . The processor 720 sends the detected interrupt information to the eSPI command generation module 745 through the bus matrix. The eSPI command generation module 745 generates an eSPI command corresponding to the interrupt information. The eSPI command sending module 746 sends the eSPI command generated by the eSPI command generating module 745 to the eSPI slave module 710 . The eSPI slave module 710 sends the eSPI command to the host processor, so that the host processor receives the eSPI command to obtain interrupt information. As an example, after obtaining the interrupt information, the host processor responds to the embedded control circuit based on the interrupt information. In some examples, the host processor initiates a process of writing data to the register of the peripheral module 730 corresponding to the interrupt information based on the interrupt information. In some examples, the host processor initiates a process of reading data from the register of the peripheral module 730 corresponding to the interrupt information based on the interrupt information.

In some embodiments, the circuit system 740 further includes: a security control module 748, connected to the AHB master interface 743 and the AHB slave interface 747. The security control module 748 is configured to provide permission information. The AHB master interface 743 is also configured to determine the authority to access the target address based on the authority information in the security control module 748. As an implementation manner, the AHB slave interface 747 is also configured to receive the permission information sent by the processor 720 through the bus matrix 750, and write the permission information into the security control module 748. In this embodiment, each target address can be configured to allow reading and writing, or allow reading and prohibit writing, or allow writing and prohibit reading, which is not limited in this embodiment.

As an implementation manner, an example of writing data to the peripheral module 730 under permission control is described as follows. The eSPI slave module 710 receives a write command from the host processor, and sends the write command to the eSPI command receiving module 741 . The eSPI command receiving module 741 receives the write command, and the write command is cached to the command buffer module 744. The eSPI command parsing module 742 obtains the write command from the command buffer module 744, and parses the write command to obtain the target address and the data to be written. The AHB master interface 743 can access the security control module 748, obtain permission information from the security control module 448, and determine whether the target address is an address that allows writing based on the permission information. When the target address is an address that allows writing, the AHB master interface 743 writes the above-mentioned data to the register of the peripheral module 730 corresponding to the target address through the bus matrix 750. In the case that the target address is a write-prohibited address, the AHB master interface 743 transmits an interrupt signal to the processor 720 through the interrupt signal line 760, so that the processor 720 knows that the host processor requests to write data to the write-prohibited address.

As an implementation manner, an example of reading data from the peripheral module 730 under permission control is described as follows. The eSPI slave module 710 receives a read command from the host processor, and sends the read command to the eSPI command receiving module 741 . The eSPI command receiving module 741 receives the read command, and buffers the read command into the command buffer module 744 . The eSPI command parsing module 742 obtains the read command from the command buffer module 744, and parses the read command to obtain the target address. The AHB master interface 743 accesses the security control module 748, obtains authority information from the security control module 748, and determines whether the target address is an address that is allowed to be read based on the authority information. When the target address is an address that allows reading, the AHB master interface 743 reads data from the register of the peripheral module 730 corresponding to the target address through the bus matrix 750. The AHB master interface 743 sends the read data to the eSPI command generation module 745. The eSPI command generating module 745 generates an eSPI command corresponding to the read command, and sends the eSPI command to the eSPI command sending module 746 . The eSPI command sending module 746 sends the eSPI command to the eSPI slave module 710 . The eSPI slave module 710 sends the eSPI command to the host processor, so that the host processor receives the eSPI command to obtain the read data. In the case that the target address is an address that is prohibited from being read, the AHB master interface 743 transmits an interrupt signal to the processor 720 through the interrupt signal line 760, so that the processor 720 knows that the host processor requests to read the address that is prohibited from being read.

As shown in Figures 7 and 8, the circuit system 740 also includes: an interrupt control 749, connected to the interrupt signal line 760, for responding to the command of the AHB master interface 743 and/or the AHB slave interface 747, through the interrupt signal line 760 to the processing The device 720 transmits an interrupt signal.

As an example, an example of reading data from a peripheral module based on eSPI is described below. The processor 720 detects an interrupt of the peripheral module 730 . In the case of detecting that the peripheral module 730 is interrupted related to the host processor, the processor 720 writes the interrupt information into the shared register of the eSPI slave module 710 through the AHB slave interface 747. Exemplary interrupt information includes interrupt status and interrupt ID. The eSPI slave module 710 receives the written information, and sends an alarm by pulling down an IO pin or a dedicated Alert signal. The host processor receives the alarm signal and queries the cause of the alarm event through the GET_STATUS command. The eSPI slave module 710 receives the GET_STATUS command, and sends the interrupt information in the shared register to the host processor through the eSPI packet. The host processor determines the cause of the alarm based on the interrupt information, and the host processor initiates a GET_PC or GET_NP command to read data. The eSPI slave module 710 receives the command, the circuit system 740 converts the command into a DMA operation, reads the data back from the register of the corresponding peripheral module 730, and the eSPI slave module 710 uploads the command to the host processor through the eSPI packet.

For example, for the keyboard, when the operator presses the keyboard, the keyboard scanning module detects and keeps the key code of the pressed button, and initiates an interrupt to the processor 720, and the processor 720 queries the interrupt ID from the keyboard scanning module, the reason for the interruption (or interrupt status) is that after the operator has a button operation, the processor 720 writes the interrupt ID and the interrupt status into the shared register of the eSPI slave module 710 through the AHB slave interface 747, and after the eSPI receives the write information from the module 710, Alarm by pulling down IO pin or dedicated Alert signal. After the host processor receives the alarm signal, it queries the cause of the alarm event through the GET_STATUS command. After receiving the GET_STATUS command from the module 710, the eSPI sends the interrupt ID and interrupt status in the shared register to the host processor through the eSPI packet. When it is known that the operator presses the keyboard, the host processor initiates a GET_PC/NP command to read the keycode of the operator pressing the key. After the eSPI receives the command from the module 710, the circuit system 740 converts the command into a DMA operation. Read back the keycode held by the keyboard scanning module, and send an eSPI packet from the module 710 through eSPI to upload to the host processor.

As an example, the description of writing data to the peripheral module 730 based on eSPI is as follows. The host processor sends the write command. The eSPI slave module 710 receives the write command, and the circuit system 740 obtains the write address and data from the write command, and writes the data into the register of the peripheral module 730 corresponding to the write address.

For example, for the ambient light, when the host processor wants to send the light effect data to the ambient light for display, the host processor first initiates a data write operation and initiates a write data packet, and the eSPI receives the packet from the module 710, and the circuit system 740 decodes it. After the package finds that it is a write command to a certain register of the ambient light, it converts the command into a DMA operation, and writes the data from the host processor into the specified address of the ambient light, so that the ambient light changes the display state and completes the processing of the host The display effect required by the device. Exemplarily, the ambient light may be interrupted during work, such as when there is no data to display (the data cache is empty), and for example, when the ambient light displays an error. When the ambient light generates an interrupt, like the keyboard, it sends an interrupt to the processor 720, and the processor 720 then sends an alarm to the host processor from the module 710 through eSPI, and the host processor queries the cause of the alarm and reads relevant data.

Embodiments of the present disclosure provide an embedded control circuit based on a direct memory access and sharing interface.

FIG. 9 shows a schematic block diagram of an embedded control circuit based on a direct memory access and shared interface according to an exemplary embodiment of the present disclosure. As shown in FIG. 9 , the embedded control circuit 900 includes: Bus interface circuit 910 , processor 920 , one or more first peripheral modules 931 , one or more second peripheral modules 932 , circuit system 940 ; first bus 951 , second bus 952 and third bus 961 . Wherein, the plurality of first peripheral modules 931 are marked as 931-1 to 931-n in FIG. 9 , and the plurality of second peripheral modules 931 are marked as 932-1 to 932-m in FIG. 9 . It should be understood that this embodiment does not limit the number of the first peripheral module 931 and the second peripheral module 932 , and the embedded control circuit 900 may include any number of the first peripheral module 931 and the second peripheral module 932 .

In some embodiments, the embedded control circuit 900 further includes: a fourth bus 962 connected between the processor 920 and the circuit system 940 to transmit information between the processor 920 and the circuit system 940 .

In some embodiments, the embedded control circuit 900 further includes: an interrupt signal line connected between the processor 920 and the circuit system 940 . The interrupt signal line may be configured to transmit any interrupt signal between the processor 920 and the circuit system 940 , which is not limited in this embodiment. As an implementation manner, the circuit system 940 is configured to transmit an interrupt signal to the processor 920 through the interrupt signal line 980 . Refer to FIG. 4 and its description, which will not be described in detail in this embodiment.

Each of the first peripheral modules 931 includes a first interface and a second interface. The first bus 951 is connected between the first interface of each first peripheral module 931 and the bus interface circuit 910 . The second bus 952 is connected between the second interface of each first peripheral module 931 and the processor 920 . The bus interface circuit 910 is provided with an I/O interface corresponding to each first peripheral module 931 . The bus interface circuit 910 is configured to access the first peripheral module 931 through the first bus 951 . The processor 920 is configured to access the first peripheral module 931 through the second bus 952 .

The third bus 961 is connected between the second peripheral module 932 and the circuit system 940 . The third bus 961 is also connected between the second peripheral module 932 and the processor 920 . The circuit system 940 is configured to communicate with the host processor through the bus interface circuit 910 , and access the second peripheral module 932 through the third bus 961 based on the commands of the host processor. In this embodiment, the circuit system 940 acts as a master device of the third bus 961 , and the second peripheral module 932 acts as a slave device of the third bus 961 , and the second peripheral module 932 can respond to various bus commands of the circuit system 940 . The processor 920 accesses the second peripheral module 932 through the third bus 961 . In this embodiment, the processor 920 can be used as the master device of the third bus 961, the second peripheral module 932 can be used as the slave device of the third bus 961, and the second peripheral module 932 can respond to various buses of the processor 920. Order.

In some embodiments, at least part of the first bus 951, the second bus 952, the third bus 961 and the fourth bus 962 can adopt a bus matrix, and the bus interface circuit 910, the processor 920, the first peripheral module 931, the second The two peripheral modules 932 and at least part of the circuit system 940 are accessed through the bus matrix.

In this embodiment, the first peripheral module 931 may refer to the descriptions of FIG. 1 , FIG. 2 and FIG. 3 mentioned above in this disclosure, and details are not repeated here. In this embodiment, the circuit system 940 and the second peripheral module 932 may refer to the descriptions of FIG. 4 , FIG. 6 , FIG. 7 and FIG. 8 in the present disclosure, and details are not repeated here.

In this embodiment, the host processor can access the first peripheral module 931 through the bus interface circuit 910 and the first bus 951 . The host processor can also access the second peripheral module 932 through the bus interface circuit 910 , the circuitry 940 and the third bus 961 . An embodiment in which the embedded control circuit 900 distinguishes the host processor's access to the first peripheral module 931 and the second peripheral module 932 will be described below.

In some embodiments, the bus interface circuit 910 is configured to: determine whether the host processor accesses the first peripheral module 931 or the second peripheral module 932 based on the target address of the access, and when the host processor accesses the first peripheral module In the case of 931, the first peripheral module 931 is accessed through the first bus 951; in the case of the host processor accessing the second peripheral module 932, the access command of the host processor is forwarded to the circuit system 940. The circuit system 940 accesses the second peripheral module 932 through the third bus 961 based on an access command of the host processor.

In some embodiments, the circuit system 940 is configured to: determine whether the second peripheral module 932 is accessed by the host processor based on the target address of the access; The command of the processor accesses the second peripheral module 932 through the third bus 961 .

In some embodiments, each first peripheral module 931 is configured to: determine whether the host processor accesses itself based on the target address of the access; .

FIG. 10 shows a flowchart of a method for accessing peripherals based on direct memory access and shared interfaces according to an exemplary embodiment of the present disclosure, which is applied to the embedded control circuit 900 shown in FIG. 9 . The method for accessing peripherals includes steps S1001 to S1004. It should be understood that although step numbers are marked in FIG. 10 , the sequence of steps S1001 to S1004 is not limited in this embodiment.

In step S1001 , the bus interface circuit 910 accesses the first peripheral module 931 through the first bus 951 . In this embodiment, the bus interface circuit 910 accessing the first peripheral module 931 through the first bus 951 includes reading and/or writing registers of the first peripheral module 931 . In this embodiment, the first bus 951 is connected between the bus interface circuit 910 and the first interface of the first peripheral module 931, and the bus interface circuit 910 passes through the first bus 951 and the first interface of the first peripheral module 931 Registers of the first peripheral module 931 are accessed.

As an implementation manner, in step S1001 , the bus interface circuit 910 receives a write command from the host processor, and writes data to the register of the first peripheral module 931 corresponding to the write command through the first bus 951 . The bus interface circuit 910 may also receive a read command from the host processor, and read data from the register of the first peripheral module 931 corresponding to the read command through the first bus 951 .

In step S1002 , the circuit system 940 communicates with the host processor through the bus interface circuit 910 , and accesses the second peripheral module 932 through the third bus 961 based on a command from the host processor.

As an implementation, in step S1002, the circuit system 940 receives the write command of the host processor through the bus interface circuit 910, and based on the write command, writes to the register of the second peripheral module 932 corresponding to the write command through the third bus 961 data. The circuit system 940 can also receive a read command from the host processor through the bus interface circuit 910 , and read data from the register of the second peripheral module 932 corresponding to the read command through the third bus 961 based on the read command.

In some embodiments, circuitry 940 accesses second peripheral module 932 based on preconfigured permissions. In this embodiment, each target address can be configured to allow reading and writing, or allow reading and prohibit writing, or allow writing and prohibit reading, which is not limited in this embodiment. As an implementation manner, the processor 920 configures the authority of the circuit system 940 to access the second peripheral module 932 through the fourth bus 962 connected between the processor 920 and the circuit system 940 . The circuitry 940 accesses the second peripheral module 932 based on the permission information configured by the processor 920.

As an implementation manner, an example of writing data to the second peripheral module 932 under authority control is described as follows. The bus interface circuit 910 receives write commands from the host processor and sends the write commands to the circuitry 940 . The circuit system 940 receives the write command, and parses the write command to obtain the target address and the data to be written. The circuit system 940 judges whether the target address is an address that allows writing. If the target address is an address that allows writing, the circuit system 940 writes to the register of the second peripheral module 932 corresponding to the target address through the third bus 961. the above data. In some examples, when the target address is a write-prohibited address, the circuit system 940 transmits an interrupt signal to the processor 920 through the interrupt signal line between the circuit system 940 and the processor 920, so as to notify the processor 920 that the host process device requests access to write-prohibited registers.

As an implementation manner, an example of reading data from the second peripheral module 932 under permission control is described as follows. Bus interface circuit 910 receives read commands from the host processor and sends the read commands to circuitry 940 . The circuit system 940 receives the read command and parses the read command to obtain the target address. The circuit system 940 determines whether the target address is an address that is allowed to be read. If the target address is an address that is allowed to be read, the circuit system 940 reads data from the register of the second peripheral module 932 corresponding to the target address through the third bus 961 . After reading the data, the circuit system 940 generates a bus command corresponding to the read command, and sends the bus command to the bus interface circuit 910 . The bus interface circuit 910 sends the bus command to the host processor, so that the host processor receives the bus command to obtain the read data. In some examples, when the target address is an address that is prohibited from being read, the circuit system 940 transmits an interrupt signal to the processor 920 through the interrupt signal line between the circuit system 940 and the processor 920, so as to notify the processor 920 that the host process device requests access to registers that are prohibited from being read.

In step S1003 , the processor 920 accesses the first peripheral module 931 through the second bus 952 . In this embodiment, the processor 920 reads data from the register of the first peripheral module 931 through the second bus 952 . The processor 920 can also write data to the register of the first peripheral module 931 through the second bus 952 .

In step S1004 , the processor 920 accesses the second peripheral module 932 through the third bus 961 . In some examples, accessing the second peripheral module 932 by the processor 920 through the third bus 961 may include: accessing by the processor 920 to read and/or write registers of the second peripheral module 932 through the third bus 961 .

In some embodiments, the processor 920 sends the interrupt information of the second peripheral module 932 to the circuit system 940 through the bus between it and the circuit system 940 . Interrupt information is sent by circuitry 940 through bus interface circuit 910 to the host processor.

As an implementation manner, an example in which the processor 920 sends the interrupt information of the second peripheral module 932 to the host processor is described as follows. The processor 920 detects interrupt information of the second peripheral module 932 . The processor 920 sends the detected interrupt information to the circuit system 940 through the bus between it and the circuit system 940 . The circuit system 940 generates a bus command corresponding to the interrupt information, and sends the generated bus command to the bus interface circuit 910. The bus interface circuit 910 sends the bus command to the host processor, so that the host processor receives the bus command to obtain the interrupt information. As an example, after obtaining the interrupt information, the host processor responds to the embedded control circuit based on the interrupt information. In some examples, the host processor initiates a process of writing data to the register of the second peripheral module 932 corresponding to the interrupt information based on the interrupt information. In some examples, the host processor initiates a process of reading data from the register of the second peripheral module 932 corresponding to the interrupt information based on the interrupt information.

Taking the eSPI bus as an example, the embedded control circuit of the exemplary embodiment of the present disclosure will describe the direct memory access and shared interface. The host processor communicates with the embedded control circuit through the eSPI bus.

FIG. 11 shows a schematic block diagram of an embedded control circuit based on a direct memory access and sharing interface using an eSPI bus according to an exemplary embodiment of the present disclosure. As shown in FIG. 11 , the embedded control circuit 1100 includes: eSPI slave module 1110 for processor communication, processor 1120 , one or more first peripheral modules 1131 , one or more second peripheral modules 1132 , circuit system 1140 and bus matrix 1150 . Wherein, the plurality of first peripheral modules 1131 are marked as 1131-1 to 1131-n in FIG. 11 , and the plurality of second peripheral modules 1132 are marked as 1132-1 to 1132-m in FIG. 11 . In this implementation, a bus matrix is used, and this embodiment will be described below in conjunction with FIG. 11 .

Each of the first peripheral modules 1131 includes a first interface and a second interface. (local bus) is connected between the first interface of each first peripheral module 1131 and the eSPI slave module 1110. The second interface of each first peripheral module 1131 is connected to the APB bus, and the processor 1120 is connected to the bus matrix 1150. The APB bus is connected to the bus matrix through the first bridge and the first fast bus, and then each first peripheral The second interface of the module 1131 is connected with the processor 1120 . The eSPI slave module 1110 is configured to access the first peripheral module 1131 through a local bus. The processor 1120 is configured to access the first peripheral module 1131 through the bus matrix, the first express bus, the first bridge and the APB bus.

The circuit system 1140 is connected to the DMA bus, the DMA bus is connected to the bus matrix 1150, the second peripheral module 1132 is connected to the second fast bus, and the second fast bus is connected to the bus matrix, and then between the second peripheral module 1132 and the circuit system 1140 are connected through the DMA bus, the bus matrix 1150 and the second fast bus. The processor 1120 is connected to the bus matrix, and the bus matrix 1150 and the second fast bus are used between the second peripheral module 1132 and the processor 1120 . The circuit system 1140 is configured to communicate with the host processor through the eSPI slave module 1110 , and access the second peripheral module 1132 through the DMA bus, the bus matrix 1150 and the second fast bus based on the command of the host processor. In this embodiment, the circuit system 1140 acts as a master device, and the second peripheral module 1132 acts as a slave device, and the second peripheral module 1132 can respond to various bus commands of the circuit system 1140 . The processor 1120 accesses the second peripheral module 1132 through the bus matrix 1150 and the second fast bus. In this embodiment, the processor 1120 may act as a master device, the second peripheral module 1132 may act as a slave device, and the second peripheral module 1132 may respond to various bus commands of the processor 1120 .

In this embodiment, some second peripheral modules 1132 can be directly connected to the second fast bus, such as the second peripheral module 1132-1 shown in FIG. Type C interface, etc. Some second peripheral modules 1132 can be connected to the second fast bus through the second bridge, such as the second peripheral modules 1132-2 to 1132-m shown in Figure 11, the second peripheral modules 1132-2 to 1132- Examples of m include an ambient light control module, a breathing light control module, and the like. It should be understood that this embodiment does not limit whether the second peripheral module 1132 is connected to the second fast bus through a bridge.

In this embodiment, the first peripheral module 1131 may refer to the descriptions of FIG. 1 , FIG. 2 and FIG. 3 in the present disclosure, and details are not repeated here. In this embodiment, the circuit system 1140 and the second peripheral module 1132 may refer to the descriptions of FIG. 4 , FIG. 6 , FIG. 7 and FIG. 8 in the present disclosure, and details are not repeated here.

In this embodiment, the host processor can access the first peripheral module 1131 through the eSPI slave module 1110 and the local bus. The host processor can also access the second peripheral module 1132 through the eSPI slave module 1110, the circuitry 1140, the DMA bus, the bus matrix 1150, and the second fast bus. An embodiment in which the embedded control circuit 1100 distinguishes the host processor's access to the first peripheral module 1131 and the second peripheral module 1132 will be described below.

In some embodiments, the eSPI slave module 1110 is configured to: determine whether the host processor accesses the first peripheral module 1131 or the second peripheral module 1132 based on the target address of the access, and when the host processor accesses the first peripheral module In the case of 1131, access the first peripheral module 1131 through the local bus; in the case of the host processor accessing the second peripheral module 1132, forward the access command of the host processor to the circuit system 1140. The circuit system 1140 accesses the second peripheral module 1132 through the DMA bus, the bus matrix 1150 and the second fast bus based on an access command of the host processor.

In some embodiments, the circuit system 1140 is configured to: determine whether the second peripheral module 1132 is accessed by the host processor based on the target address of the access; The command of the processor accesses the second peripheral module 1132 through the DMA bus, the bus matrix 1150 and the second fast bus.

In some embodiments, each first peripheral module 1131 is configured to: determine whether the host processor accesses itself based on the target address of the access; .

An embodiment of the present disclosure provides an embedded control circuit with a dual-bus interface.

Fig. 12 shows a schematic block diagram of an embedded control circuit of a dual-bus interface in an exemplary embodiment of the present disclosure. As shown in Fig. 12 , the embedded control circuit 1200 includes: one or more peripheral modules 1230; a processor 1220 , connected with one or more peripheral modules 1230; first bus interface circuit 1211, connected with one or more peripheral modules 1230; second bus interface circuit 1212, connected with one or more peripheral modules 1230; bus interface The selection circuit 1213 is configured to communicate with the host processor, and is operable to connect the first bus interface circuit 1211 or the second bus interface circuit 1212 to the host processor.

In this embodiment, the first bus interface circuit 1211 or the second bus interface circuit 1212 can use various types of bus interfaces to communicate with the host processor, including but not limited to LPC bus, SPI bus, eSPI bus and so on. Exemplarily, the first bus interface circuit 1211 can be an LPC circuit, and the second bus interface circuit 1212 can be an eSPI circuit, so that the embedded control circuit 1200 can communicate with the host processor through the LPC bus protocol or the eSPI bus protocol. It should be understood that the first bus interface circuit 1211 and the second bus interface circuit 1212 may use any combination of two bus protocols, which is not limited in this embodiment.

In some embodiments, the bus interface selection circuit 1213 is configured to connect the first bus interface circuit 1211 or the second bus interface circuit 1212 to the host processor based on the initialization configuration. After initial configuration, the embedded control circuit 1200 is configured to communicate with the host processor through one of the first bus interface circuit 1211 and the second bus interface circuit 1212 . The bus interface selection circuit 1213 connects one of the first bus interface circuit 1211 and the second bus interface circuit 1212 to the host processor based on the initial configuration, thereby communicating with the host processor through the configured bus interface circuit.

In some embodiments, the peripheral module 1230 includes: one or more first peripheral modules, each of the one or more first peripheral modules includes a first interface and a second interface. Between the first interface of each first peripheral module and the first bus interface circuit and the second bus interface circuit, the first bus is connected; between the second interface of each first peripheral module and the processor, through Second bus connection. The first bus interface circuit 1211 and the second bus interface circuit 1212 are configured to access one or more first peripheral modules through the first bus. The processor 1220 is configured to access one or more first peripheral modules through the second bus.

In this embodiment, for the first peripheral module, reference may be made to the descriptions of FIG. 1 , FIG. 2 and FIG. 3 in the present disclosure, and details are not repeated here.

In some embodiments, the peripheral module 1230 includes: one or more second peripheral modules. The embedded control circuit also includes: a circuit system. The one or more second peripheral modules are connected to the circuit system through the third bus. One or more second peripheral modules are connected to the processor 1120 through a third bus. The circuit system is configured to communicate with the host processor through the first bus interface circuit 1211 or the second bus interface circuit 1212, and access one or more second peripheral modules through the third bus based on the command of the host processor; the processor 1220 , configured to access one or more second peripheral modules through the third bus.

In this embodiment, the circuit system and the second peripheral module may refer to the descriptions of FIG. 4 , FIG. 6 , FIG. 7 and FIG. 8 mentioned above in this disclosure, and details are not repeated here.

In some embodiments, the peripheral module 1230 includes one or more first peripheral modules and one or more second peripheral modules. In this embodiment, the host processor can access the first peripheral module through the first bus interface circuit 1211 or the second bus interface circuit 1212 and the first bus. The host processor can also access the second peripheral module through the first bus interface circuit 1211 or the second bus interface circuit 1212, the circuit system and the third bus. An embodiment in which the embedded control circuit 1200 distinguishes between the host processor's access to the first peripheral module and the second peripheral module will be described below.

As an implementation manner, the first bus interface circuit 1211 and/or the second bus interface circuit 1212 are configured to: determine whether the host processor is accessing the first peripheral module or the second peripheral module based on the target address of the access; When the host processor accesses one or more first peripheral modules, access one or more first peripheral modules through the first bus; when the host processor accesses one or more second peripheral modules, The host processor's access command is forwarded to the circuitry. The circuitry accesses the second peripheral module through the third bus.

As an implementation manner, the circuit system is configured to: determine whether the host processor accesses one or more second peripheral modules based on the target address of the access; when the host processor accesses the one or more second peripheral modules, In some cases, one or more second peripheral modules are accessed through the third bus based on commands from the host processor.

The embedded control circuit of the exemplary embodiment of the present disclosure is described below by taking the LPC and eSPI bus as examples, and the host processor communicates with the embedded control circuit through the eSPI or LPC bus.

Fig. 13 shows the schematic block diagram of the embedded control circuit of the LPC-eSPI dual-bus interface of the exemplary embodiment of the present disclosure, as shown in Fig. 13, the embedded control circuit 1300 includes: a peripheral module; a processor 1320, and Peripheral module connection; LPC slave module 1311, connected with one or more peripheral modules; eSPI slave module 1312, connected with one or more peripheral modules; LPC-eSPI interface selector 1313, configured to communicate with the host processor communicate, and operatively connect the LPC slave module 1311 or the eSPI slave module 1312 to a host processor; circuitry 1340. Wherein, the peripheral modules include: one or more first peripheral modules 1331 and one or more second peripheral modules 1332, marked as first peripheral modules 1331-1 to 1331-n in FIG. Modules 1332-1 to 1332-m are provided.

In some embodiments, the LPC-eSPI interface selector 1313 is configured to connect the LPC slave module 1311 or the eSPI slave module 1312 to the host processor based on the initial configuration. After initial configuration, the embedded control circuit 1300 is configured to communicate with the host processor through a bus interface circuit in the LPC slave module 1311 and the eSPI slave module 1312 . The LPC-eSPI interface selector 1313 connects one bus interface circuit in the LPC slave module 1311 and the eSPI slave module 1312 to the host processor based on the initial configuration, thereby communicating with the host processor through the configured bus interface circuit.

In this embodiment, each first peripheral module 1331 includes a first interface and a second interface. The first interface of each first peripheral module 1331 is connected to the LPC slave module 1311 and the eSPI slave module 1312 through a local bus (local bus). The second interface of each first peripheral module 1331 is connected to the processor through the APB bus, the first bridge, the first fast bus and the bus matrix 1350 . The LPC slave module 1311 and the eSPI slave module 1312 access one or more first peripheral modules 1331 through the local bus. The processor 1320 accesses the first peripheral module 1331 through the first fast bus, the first bridge and the APB bus of the bus matrix 1350 .

In this embodiment, for the first peripheral module 1331, reference may be made to the descriptions of FIG. 1 , FIG. 2 and FIG. 3 in the present disclosure, and details are not repeated here.

In this embodiment, the second peripheral module 1332 and the circuit system 1340 are connected through a DMA bus, a bus matrix 1350 and a second fast bus. The second peripheral module 1332 is connected to the processor 1320 through a bus matrix 1350 and a second fast bus. The circuit system 1340 communicates with the host processor through the LPC slave module 1311 or the eSPI slave module 1312, the command based on the host processor passes through the DMA bus, the bus matrix and the second fast bus second peripheral module 1332, and the processor 1320 passes through the bus matrix 1350 . The second fast bus accesses the second peripheral module 1332 .

In some embodiments, the processor 1320 can also access the circuit system 1340 through the bus matrix 1350, the first bridge, and the APB bus. Information can be transmitted between the processor 1320 and the circuit system 1340 through the bus matrix 1350 , the first bridge, and the APB bus. For example, the processor 1320 can transmit permission information for accessing the second peripheral module 1332 to the circuit system 1340 on this line.

In this embodiment, the circuit system 1340 and the second peripheral module 1332 may refer to the descriptions of FIG. 4 , FIG. 6 , FIG. 7 and FIG. 8 in the present disclosure, and details are not repeated here.

In this embodiment, the host processor can access the first peripheral module 1331 through the LPC slave module 1311 or the eSPI slave module 1312 and the local bus. The host processor can also access the second peripheral module 1332 through the LPC slave module 1311 or the eSPI slave module 1312, the circuitry 1340 and the DMA bus, the bus matrix 1350, and the second fast bus. An embodiment in which the embedded control circuit 1300 distinguishes the host processor's access to the first peripheral module 1331 and the second peripheral module 1332 will be described below.

As an implementation, the LPC slave module 1311 and/or the eSPI slave module 1312 are configured to: determine whether the host processor accesses the first peripheral module 1331 or the second peripheral module 1332 based on the target address of the access; In the case that the processor accesses one or more first peripheral modules 1331, one or more first peripheral modules 1331 are accessed through the first bus; when the host processor accesses one or more second peripheral modules 1332 , forward the access command of the host processor to the circuit system 1340 . The circuit system 1340 accesses the second peripheral module 1332 through the DMA bus, the bus matrix 1350 and the second fast bus.

As an implementation, the circuit system 1340 is configured to: determine whether the host processor accesses one or more second peripheral modules 1332 based on the target address of the access; In the case of the module 1332, one or more second peripheral modules 1332 are accessed through the DMA bus, the bus matrix 1350, and the second fast bus based on commands from the host processor.

As an implementation, each first peripheral module 1331 is configured to: determine whether the host processor accesses itself based on the target address of the access; .

The exemplary implementation of the present disclosure also provides a chip, which may include the aforementioned embedded control circuit of the present disclosure.

The solutions of the present disclosure may be integrated into an electronic device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system ( GPS) devices; mobile phones; cellular phones; smart phones; Session Initiation Protocol (SIP) phones; tablets; phablets; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants ( PDA); monitor; computer monitor; television; tuner; radio; satellite radio; music player; digital music player; portable music player; digital video player; video player; digital video disc (DVD) Players; Portable Digital Video Players; Motor Vehicles; Vehicle Components; Avionics Systems; Unmanned Aerial Vehicles; and Multicopters.

The above descriptions are only exemplary embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modifications, equivalent replacements and simple improvements made on the essential content of the present disclosure shall be included in the protection scope of the present disclosure. Inside.

Claims

An embedded control circuit comprising:

one or more peripheral modules;

a processor connected to the one or more peripheral modules;

a first bus interface circuit connected to the one or more peripheral modules;

a second bus interface circuit connected to the one or more peripheral modules;

A bus interface selection circuit configured to communicate with a host processor and operatively connect the first bus interface circuit or the second bus interface circuit to the host processor.
The embedded control circuit according to claim 1, wherein the bus interface selection circuit is configured to connect the first bus interface circuit or the second bus interface circuit to the host processing device.
The embedded control circuit according to claim 1, wherein the one or more peripheral modules include: one or more first peripheral modules, each of the one or more first peripheral modules A first peripheral module includes a first interface and a second interface;

Wherein, the embedded control circuit also includes: a first bus, connected between the first interface of each first peripheral module and the first bus interface circuit and the second bus interface circuit; the second bus , connected between the second interface of each first peripheral module and the processor;

Wherein, the first bus interface circuit and the second bus interface circuit are configured to access the one or more first peripheral modules through the first bus; the processor is configured to access the one or more first peripheral modules through the The second bus accesses the one or more first peripheral modules.
The embedded control circuit according to claim 3, wherein at least one of the first peripheral modules comprises: an arbitration logic circuit configured to:

disconnecting the second interface of the first peripheral module from the second bus when the first peripheral module is accessed by the host processor; and/or

disconnecting the first interface of the first peripheral module from the first bus when the first peripheral module is accessed by the processor.
The embedded control circuit according to claim 4, wherein the arbitration logic circuit is further configured as:

connecting the second interface of the first peripheral module to the second bus when the first peripheral module is released by the host processor; and/or

When the first peripheral module is released by the processor, connect the first interface of the first peripheral module to the second bus.
The embedded control circuit according to any one of claims 1 to 5, wherein the one or more peripheral modules include: one or more second peripheral modules;

Wherein, the embedded control circuit also includes:

electrical system;

a third bus connected between the one or more second peripheral modules and the circuitry, and between the one or more second peripheral modules and the processor;

Wherein, the circuit system is configured to communicate with the host processor through the first bus interface circuit or the second bus interface circuit, and access all The one or more second peripheral modules; the processor configured to access the one or more second peripheral modules through the third bus.
The embedded control circuit according to claim 6, wherein the first bus interface circuit and/or the second bus interface circuit are configured to:

determining whether the host processor accesses the first peripheral module or the second peripheral module based on the accessed target address;

In case the host processor accesses the one or more first peripheral modules, accessing the one or more first peripheral modules through the first bus;

Where the host processor accesses the one or more second peripheral modules, forwarding the host processor access command to the circuitry.
The embedded control circuit of claim 6, wherein the circuitry is configured to:

determining whether the one or more second peripheral modules are accessed by the host processor based on the accessed target address;

When the host processor accesses the one or more second peripheral modules, the one or more second peripheral modules are accessed through the third bus based on a command of the host processor.
The embedded control circuit according to claim 6, further comprising: a fourth bus connected between the processor and the circuit system.
The embedded control circuit according to claim 9, wherein the processor is configured to: send interrupt information of the one or more second peripheral modules to the circuit system through the fourth bus; The circuitry is configured to: send the interrupt information to a host processor through the first bus interface circuit or the second bus interface circuit.
The embedded control circuit of claim 6, wherein the circuitry is configured to access the one or more second peripheral modules based on preconfigured permissions.
The embedded control circuit according to claim 11, further comprising: an interrupt signal line connected between the processor and the circuit system; the circuit system is configured to: when the host processor accesses When the register of the second peripheral module is configured to prohibit access, an interrupt signal is transmitted to the processor through the interrupt signal line.
The embedded control circuit according to claim 3 or 6, wherein at least one of the first peripheral modules is configured to:

determining whether the first peripheral module is accessed by the host processor based on the accessed target address;

When the host processor accesses the first peripheral module, responding to the host processor's access.
A chip comprising the embedded control circuit according to any one of claims 1-13.
An electronic device, comprising: the embedded control circuit according to any one of claims 1 to 13 or the chip according to claim 14.