WO2023115580A1 - Ferroelectric memory, manufacturing method therefor, and electronic device - Google Patents

Abstract

A ferroelectric memory, comprising a substrate and at least one ferroelectric tunnel junction set arranged on the substrate. Each ferroelectric tunnel junction set comprises N ferroelectric tunnel junction units and N+1 conductive metal layers which are stacked. The N ferroelectric tunnel junction units and the N+1 conductive metal layers are alternately arranged. Each ferroelectric tunnel junction unit comprises a first conductive oxide layer, a ferroelectric layer and a second conductive oxide layer which are sequentially stacked. N is an integer greater than or equal to 1. The present application further provides a manufacturing method for the ferroelectric memory and an electronic device. In the ferroelectric memory of the present application, the conductive metal layers and the conductive oxide layers are compounded to improve the on/off ratio. Meanwhile, the ferroelectric tunnel junction set has an excellent ferroelectric/electrode interface, thereby enhancing the ferroelectric performance of the memory, mitigating the risk of ferroelectric fatigue of the memory, and improving the number and reliability of writing cycles.

Description

Ferroelectric memory and its preparation method, electronic equipment technical field

The present application relates to a ferroelectric memory, a preparation method of the ferroelectric memory and electronic equipment containing the ferroelectric memory.

Background technique

With the development of automotive and Internet of Things (IoT) technologies, the demand for chips is growing rapidly. In the future, edge computing AI chips need faster embedded memories with lower power consumption. Non-volatile memory devices that can be used as embedded memory include non-volatile magnetic random access memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric memory (Ferroelectric RAM, FeRAM), phase change memory (Phase Change RAM, PCRAM), resistance Variable memory (Resistive Random Access Memory, RRAM) and ferroelectric memory based on ferroelectric tunnel junction (Ferroelectric Tunneling Junction, FTJ), etc.

Among them, Ferroelectric Tunneling Junction (Ferroelectric Tunneling Junction, FTJ) is a device with an ultra-thin ferroelectric film sandwiched between electrodes on both sides as a tunneling barrier layer, which has quantum tunneling effect and electro-resistance effect. By applying a voltage to the electrodes, the ferroelectric polarization direction of the ferroelectric film in the FTJ memory can be reversed, and the interface charge state can be changed, so that the FTJ memory can switch between high resistance and low resistance. Compared with other new types of memory, FTJ memory has significant advantages in power consumption and operation speed. Its operation speed is comparable to that of Dynamic Random Access Memory (DRAM), and its power consumption for reading and writing is comparable to that of Static Random Access Memory (DRAM). Static Random-Access Memory (SRAM) can compete, and also has non-volatile characteristics, so it has attracted much attention.

However, in the actual production and application process, the FTJ memory mainly has the following defects: as shown in Figure 1, the existing FTJ memory includes a bottom electrode 3', a ferroelectric layer 2' and a top electrode 1 stacked on the substrate in sequence ', where the top electrode 1' and the bottom electrode 3' are made of metals commonly used in integrated circuits, which have both conductive and blocking effects, but the ferroelectric/electrode interface in the ferroelectric tunnel junction is poor, and there are serious interface defects, which cause iron The problem of electrical fatigue reduces the number of reads and writes of the FTJ memory with this structure. On the basis of the FTJ memory in Figure 1, in order to obtain high-quality ferroelectric films and reduce ferroelectric fatigue caused by defects at the ferroelectric/electrode interface, the top electrode 1" and bottom electrode 3" in the FTJ memory in Figure 2 It is made of conductive oxide, but only conductive oxide is used as the electrode, the lead resistance is large, and the switch is relatively low. In addition, there is no barrier layer in the ferroelectric tunnel junction in Fig. 1 and Fig. 2, and the ferroelectric performance and reliability of the memory are poor.

Contents of the invention

In a first aspect, the present application provides a ferroelectric memory, which includes a substrate and at least one ferroelectric tunnel junction group on the substrate, each of the ferroelectric tunnel junction groups includes stacked N Ferroelectric tunnel junction units and N+1 layers of conductive metal layers, the N ferroelectric tunnel junction units and the N+1 layers of conductive metal layers are alternately arranged, and each of the ferroelectric tunnel junction units includes a stack of The first conductive oxide layer, the ferroelectric layer and the second conductive oxide layer are provided, wherein, N is an integer greater than or equal to 1.

It can be seen that the present application arranges conductive metal layers on the opposite surfaces of the ferroelectric tunnel junction unit respectively. When the first conductive oxide layer and the adjacent conductive metal layer are combined as the first electrode, the second conductive oxide layer When the oxide layer and the adjacent conductive metal layer are combined as the second electrode, compared with the fully conductive oxide electrodes provided on both surfaces of the ferroelectric layer, the above-mentioned first electrode and second electrode of the present application can effectively reduce the electrode lead resistance, which helps to improve the switching ratio; because there are good interfaces between the ferroelectric layer and the conductive oxide layer, and between the conductive metal layer and the conductive oxide layer, compared with setting all-metal on both surfaces of the ferroelectric layer Electrodes, this application adds the first conductive oxide layer and the second conductive oxide layer between the ferroelectric layer and the conductive metal layer, which can make the ferroelectric tunnel junction have a good interface effect between each layer and reduce the ferroelectric The interface defect of ferroelectric/electrode is conducive to improving the ferroelectric performance of ferroelectric tunnel junction; because the interface defect of ferroelectric/electrode, especially the interface stress, can cause the ferroelectric fatigue of ferroelectric memory, therefore, the ferroelectric tunnel of this application After the ferroelectric/electrode interface defects of the junction are reduced, it is beneficial to reduce the risk of ferroelectric fatigue in the ferroelectric memory, thereby improving the cycle times and reliability of the ferroelectric memory writing, and prolonging the life of the ferroelectric memory. In addition, the application implements multi-directional three-dimensional integration of multiple ferroelectric tunnel junction units, which improves the storage state of the ferroelectric memory.

With reference to the first aspect, in some embodiments, a first barrier layer is provided between the ferroelectric tunnel junction unit and the adjacent conductive metal layer.

It can be seen that by adding the first barrier layer between the conductive metal layer and the ferroelectric tunnel junction unit, it has an excellent barrier effect while having a conductive effect, so that there is a good barrier between the ferroelectric tunnel junction unit and the conductive metal layer. The interface reduces the interface defects of the ferroelectric/electrode, which is beneficial to improve the ferroelectric performance of the ferroelectric tunnel junction group, reduces the risk of ferroelectric fatigue in the ferroelectric memory, and thus increases the cycle times of ferroelectric memory writing.

In combination with the first aspect, in some embodiments, the material of the first conductive oxide layer is La _1-x Sr _x MnO ₃ , La _{1- x} Ca _x MnO ₃ , La _1-x Sr _x CoO ₃ , YBaCuO ₂ , SrRuO ₃ , Nd: at least one of SrTiO ₃ and SrIrO ₃ , wherein 0<x<1; the material of the second conductive oxide layer is La _1-x Sr _x MnO ₃ , La _1-x Ca At least one of _x MnO ₃ , La _1-x Sr _x CoO ₃ , YBaCuO ₂ , SrRuO ₃ , Nd:SrTiO ₃ and SrIrO ₃ , where 0<x<1.

It can be seen that the perovskite conductive material selected as the material of the first conductive oxide layer and the second conductive oxide layer can be beneficial to the superlattice epitaxial growth of the ferroelectric tunnel junction unit, thereby ensuring the ferroelectric tunnel junction The junction unit has a good ferroelectric/electrode interface and reduces ferroelectric/electrode interface defects.

In combination with the first aspect, in some embodiments, the material of the ferroelectric layer is (Bi,La)FeO ₃ , (Ba,Sr)TiO ₃ , (Pb,La) _{1- x} (Zr,Ti) _x O ₃ and at least one of Hf-based oxides.

It can be seen that the selection of the above-mentioned titanite material or Hf-based oxide ferroelectric material for the ferroelectric layer can be beneficial to the growth of the ferroelectric layer on the first conductive oxide layer of the perovskite class, and is also beneficial to the growth of the calcium oxide layer. The second conductive oxide layer of titanium ore is grown on the ferroelectric layer of the above material to form an atomically ordered superlattice, ensuring that the ferroelectric tunnel junction unit has a good ferroelectric/electrode interface.

With reference to the first aspect, in some embodiments, the material of the conductive metal layer is at least one of W, Co and Al.

It can be seen that using conventional metals to make the conductive metal layer can reduce the cost.

In combination with the first aspect, in some embodiments, the material of the first barrier layer is at least one of Ir/IrO, Ru/RuO, Ti/TiN, Ta/TaN, Ta/TaSiN, Ti/TiSiN, Zr/ZrO A group.

It can be seen that the selection of the above materials is conducive to realizing the effect of conducting and blocking the first barrier layer at the same time. The first barrier layer forms a potential barrier between the conductive metal layer and the ferroelectric tunnel junction unit, and electrons have to pass through this barrier. The potential barrier must have a certain energy. If a positive voltage is applied to the conductive metal layer, the electric field in the barrier region will be weakened, and the barrier height will be reduced. Some electrons can cross this potential barrier, forming a forward current, and promoting The ferroelectric polarization direction of the ferroelectric layer is reversed; and if a reverse voltage is applied to the first barrier layer, the applied electric field is in the same direction as the electric field in the barrier region, which increases the height of the barrier instead, and it is difficult for electrons to cross the barrier , the reverse current is very small, which prevents the polarized electrons of the ferroelectric tunnel junction unit from diffusing into the conductive metal layer, thereby reducing the risk of ferroelectric fatigue in the ferroelectric tunnel junction unit, thereby improving the ferroelectric Reliability and lifetime of tunnel junction cells.

With reference to the first aspect, in some embodiments, a buffer layer is provided on the surface of the substrate close to the ferroelectric tunnel junction group.

It can be seen that adding a buffer layer on the surface of the substrate, the buffer layer can optimize the surface of the substrate, provide lattice parameters that match the subsequent growth of the sacrificial layer, reduce the internal stress of the ferroelectric tunnel junction, and then reduce the ferroelectric Internal defects of electrical storage.

With reference to the first aspect, in some embodiments, the material of the buffer layer is SrTiO ₃ or LaNiO ₃ .

With reference to the first aspect, in some embodiments, the substrate includes at least one connection region and a thinned region around each connection region, and each connection region is provided with one ferroelectric tunnel junction group , the conductive metal layer close to the substrate in each ferroelectric tunnel junction group extends to the corresponding thinned region.

With reference to the first aspect, in some embodiments, a surface of the substrate corresponding to each of the thinned regions is provided with a second barrier layer.

In combination with the first aspect, in some embodiments, the material of the second barrier layer is at least one of Ir/IrO, Ru/RuO, Ti/TiN, Ta/TaN, Ta/TaSiN, Ti/TiSiN, Zr/ZrO A group.

With reference to the first aspect, in some embodiments, two openings are provided on opposite side edges of each conductive metal layer in each ferroelectric tunnel junction group, and each ferroelectric tunnel junction group is provided with two openings. The sidewalls with the openings are disposed on the insulating layer, and the insulating layer extends into each of the openings.

It can be seen that by disposing the insulating layer, each conductive metal layer and each ferroelectric tunnel junction unit can be effectively isolated.

In a second aspect, the present application provides a preparation method of a ferroelectric memory, the preparation method comprising:

At least one fin body is formed on the surface of the substrate, each of the fin bodies includes alternately stacked N+1 sacrificial layers and N ferroelectric tunnel junction units, and each of the ferroelectric tunnel junction units includes sequentially stacked A first conductive oxide layer, a ferroelectric layer and a second conductive oxide layer are provided, wherein N is an integer greater than or equal to 1; and

Each layer of the sacrificial layer in each of the fins is removed and a conductive metal layer is formed at the position of the sacrificial layer to form at least one ferroelectric tunnel junction group, thereby obtaining the ferroelectric memory.

It can be seen that the preparation method of the present application forms a sacrificial layer on the substrate first, and then replaces the sacrificial layer with a conductive metal layer, which can avoid the direct growth of ferroelectric tunnel junction units on the surface of the conductive metal layer under high temperature conditions. It is possible to realize the recombination of the conductive metal layer and the ferroelectric tunnel junction unit in the process, which is conducive to reducing the interface defects between the various layers in the ferroelectric memory, especially conducive to the formation of a good ferroelectric/electrode interface; moreover, it can be formed at one time The vertically stacked and horizontally arranged multi-layer conductive metal layers are conducive to the multi-directional three-dimensional integration of multiple ferroelectric tunnel junction units on the substrate and improve the storage state. The preparation method is simple, simplifies the manufacturing process, improves the production efficiency, and is beneficial to reduce the cost, can be realized by using conventional molding equipment, is easy to operate, and is easy to realize industrialization.

With reference to the second aspect, in some embodiments, the method for preparing the at least one fin body includes:

forming an N+1 intermediate sacrificial layer and N ferroelectric tunnel junctions on the surface of the substrate; and

Patterning each layer of the intermediate sacrificial layer and each of the ferroelectric tunnel junctions to respectively form at least one layer of the sacrificial layer and at least one ferroelectric tunnel junction unit, thereby obtaining the at least one fin body.

It can be seen that the present application first forms an integrated intermediate sacrificial layer and ferroelectric tunnel junction layer, and then etches the intermediate sacrificial layer and ferroelectric tunnel junction layer to prepare at least one ferroelectric tunnel junction group. The preparation method of the application can simultaneously prepare multiple ferroelectric tunnel junction groups on one substrate, the method is simple, easy to realize, can improve production efficiency and reduce cost.

With reference to the second aspect, in some embodiments, before removing each layer of the sacrificial layer in each of the fins, the preparation method further includes:

Partially etching the opposite side edge portions of each layer of the sacrificial layer in each of the fins to form two openings; and

An insulating layer is formed on the sidewall of each of the fins provided with the opening, and the insulating layer extends into each of the openings.

It can be seen that the above method can form an insulating layer isolating each ferroelectric tunnel junction unit, and at the same time, the insulating layer can play a role in supporting the ferroelectric tunnel junction unit, which is convenient for removing the sacrificial layer and performing subsequent operations at the position of the original sacrificial layer .

With reference to the second aspect, in some embodiments, between removing the sacrificial layer and forming the conductive metal layer, the preparation method further includes:

A first barrier layer is formed at the position of each sacrificial layer.

It can be seen that a layer of first barrier layer is first grown on the surface of the ferroelectric tunnel junction unit, and then a conductive metal layer is formed on the surface of the first barrier layer, which is conducive to improving the interface between the ferroelectric tunnel junction unit and the conductive metal layer. Combining force to form an excellent ferroelectric/electrode interface, and the first barrier layer has a conductive effect and a blocking effect, which can help improve the ferroelectric performance of the ferroelectric tunnel junction group and reduce the risk of ferroelectric fatigue in the ferroelectric memory risk, thereby improving the cycle times and reliability of ferroelectric memory writing, and prolonging the life of ferroelectric memory.

In conjunction with the second aspect, in some embodiments, each layer of the sacrificial layer and each of the ferroelectric tunnel junction units are formed on the surface of the substrate by a superlattice epitaxial growth process at a growth temperature of 400-800 ℃.

It can be seen that the ferroelectric tunnel junction unit with excellent ferroelectric/electrode interface can be grown by superlattice epitaxial growth process, which reduces interface defects, reduces the risk of ferroelectric fatigue in ferroelectric memory, and improves the ferroelectric performance of ferroelectric memory. performance.

With reference to the second aspect, in some embodiments, the superlattice epitaxy growth method includes physical vapor deposition (PVD), atomic layer deposition (ALD) or molecular beam epitaxy (MBE).

With reference to the second aspect, in some embodiments, before forming at least one fin body on the surface of the substrate, the preparation method further includes:

A buffer layer is formed on the surface of the substrate.

It can be seen that by adding a buffer layer on the surface of the substrate, the surface of the substrate can be made smoother, and the buffer layer and the sacrificial layer have matching lattice parameters, which facilitates the growth of a sacrificial layer with a good interface and a ferroelectric tunnel junction unit. It is also possible to reduce internal stress and internal defects of the ferroelectric memory.

With reference to the second aspect, in some embodiments, the substrate includes at least one connection region and a thinned region around each connection region, each connection region is formed with one fin body, each The conductive metal layer close to the substrate in the fin body extends to the corresponding thinned region.

It can be seen that each of the conductive metal layers close to the substrate extends to the corresponding thinned region, which can facilitate the extraction and connection of the electrodes on the surface of the substrate to connect to the power supply.

With reference to the second aspect, in some embodiments, while forming the first barrier layer, the preparation method further includes:

A second barrier layer is formed on the surface of the substrate corresponding to each of the thinned regions.

It can be seen that the formation of the second barrier layer in the thinned region is beneficial to the growth of the metal conductive layer in the thinned region and reduces the interface stress between the metal conductive layer and the substrate in the thinned region.

While forming a layer of first barrier layer on the surface of each of the ferroelectric tunnel junction units corresponding to each of the window opening regions, the preparation method further includes: A second barrier layer is formed on the surface of the region.

With reference to the second aspect, in some embodiments, the material of each sacrificial layer is Sr ₃ Al ₂ O ₆ or La _1-x Sr _x MnO ₃ .

In a third aspect, the present application provides an electronic device, the electronic device includes the above-mentioned ferroelectric memory.

Description of drawings

1 and 2 are schematic diagrams of two types of ferroelectric memories in the prior art.

FIG. 3 is a schematic diagram of a ferroelectric tunnel junction according to an embodiment of the present application.

FIG. 4 is a schematic structural diagram of a ferroelectric memory according to an embodiment of the present application.

FIG. 5 is a cross-sectional view along V-V of the ferroelectric memory in FIG. 4 .

FIG. 6 is a flowchart of a method for preparing a ferroelectric memory according to an embodiment of the present application.

FIG. 7A is a first schematic diagram of the preparation process of the ferroelectric memory according to the embodiment of the present application.

FIG. 7B is a second schematic diagram of the preparation process of the ferroelectric memory according to the embodiment of the present application.

FIG. 7C is a third schematic diagram of the preparation process of the ferroelectric memory according to the embodiment of the present application.

FIG. 7D is a schematic diagram 4 of the preparation process of the ferroelectric memory according to the embodiment of the present application.

FIG. 7E is a schematic diagram 5 of the preparation process of the ferroelectric memory according to the embodiment of the present application.

FIG. 7F is a sixth schematic diagram of the preparation process of the ferroelectric memory according to the embodiment of the present application.

Fig. 7G is a cross-sectional view along VIIG-VIIG of the schematic diagram in Fig. 7F.

FIG. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed ways

Embodiments of the present application are described below with reference to the drawings in the embodiments of the present application.

Usually, the ferroelectric/electrode interface of the ferroelectric tunnel junction with all-metal electrodes has defects, which can easily cause the ferroelectric fatigue problem of the ferroelectric memory, thereby reducing the number of reads and writes of the ferroelectric memory. Generally, a fully conductive oxide is used as the ferroelectric tunnel junction of the electrode, and the lead resistance of the conductive oxide electrode is large, and the switch is relatively low. Moreover, there is no barrier layer between the all-metal electrode and the ferroelectric layer, and between the all-conductive oxide electrode and the ferroelectric layer, so the ferroelectric performance and reliability of the ferroelectric memory are poor.

In view of this, please refer to FIG. 3 to FIG. 5 , a ferroelectric memory 100 according to an embodiment of the present application. The ferroelectric memory 100 can be used as an embedded non-volatile memory device in the fields of the Internet of Things, information processing, and the like. The ferroelectric memory 100 includes a substrate 1 and at least one ferroelectric tunnel junction group 10 on the substrate 1 . As shown in FIG. 3 , the ferroelectric tunnel junction group 10 includes N ferroelectric tunnel junction units 2 and N+1 conductive metal layers 3 stacked on the substrate 1, and the N ferroelectric tunnel junction units 2 Alternately arranged with the N+1 conductive metal layers 3, each of the ferroelectric tunnel junction units 2 includes a first conductive oxide layer 21, a ferroelectric layer 22 and a second conductive oxide layer 23 stacked in sequence, Wherein, N is an integer greater than or equal to 1. For example, when N is 1, there is one ferroelectric tunnel junction unit 2 and two layers of conductive metal layer 3, and the obtained ferroelectric tunnel junction group 10 is sequentially stacked with one layer of conductive metal layer 3 and one ferroelectric tunnel junction unit. 2 and the structure of another conductive metal layer 3; when N is 2, there are two ferroelectric tunnel junction units 2, and four conductive metal layers 3, and the obtained ferroelectric tunnel junction group 10 is a stacked one The structure of a conductive metal layer 3, a ferroelectric tunnel junction unit 2, another conductive metal layer 3, another ferroelectric tunnel junction unit 2 and another conductive metal layer 3, at this time, the two ferroelectric tunnel junction units 2 share a layer of conductive metal layer 3; by analogy, the ferroelectric tunnel junction group 10 can realize the three-dimensional stacking of multiple ferroelectric tunnel junction groups 2, it can be understood that the ferroelectric memory 100 can realize multiple ferroelectric tunnel junction groups 2 The horizontal arrangement of the electrical tunnel junction groups 10 further enables the ferroelectric memory 100 to have multiple storage states at the same time.

Since both the first conductive oxide layer 21 and the second conductive oxide layer 23 can conduct electricity, during use, the first conductive oxide layer 21 and the conductive metal layer 3 adjacent to it can be used as the The first electrode a of the ferroelectric layer 22, the second conductive oxide layer 23 and the conductive metal layer 3 adjacent to it can be used as the second electrode b of the ferroelectric layer 22, and conduct electricity through two layers The metal layer 3 is respectively connected to the positive and negative poles of the external power supply. In this application, the conductive metal layer 3 is combined with the first conductive oxide layer 21 (or the second conductive oxide layer 23) and then used as an electrode to connect to an external power source. Compared with the two opposite surfaces of the ferroelectric layer 22, fully conductive oxide electrodes are provided. Connect the external power supply, the above-mentioned first electrode a and the second electrode b of the present application can effectively reduce the lead wire resistance of the electrode, and help to improve the switching ratio; because the ferroelectric layer 22 and the first conductive oxide layer 21 (or the second Conductive oxide layer 23), the conductive metal layer 3 and the first conductive oxide layer 21 (or the second conductive oxide layer 23) all have a good interface, compared to the ferroelectric layer 22 on the two opposite surfaces For pure metal electrodes, the present application adds a first conductive oxide layer 21 and a second conductive oxide layer 23 between the ferroelectric layer 22 and the conductive metal layer 3, so that the layers of the ferroelectric tunnel junction group 10 can have Good interface effect reduces the interface defect of ferroelectric/electrode, which is beneficial to improve the ferroelectric performance of the ferroelectric tunnel junction group 10; due to the interface defect of ferroelectric/electrode, especially the interface stress, it will cause ferroelectric memory Therefore, after the ferroelectric/electrode interface defects of the ferroelectric tunnel junction group 10 of the present application are reduced, it is beneficial to reduce the risk of ferroelectric fatigue in the ferroelectric memory 100, thereby increasing the number of cycles written in the ferroelectric memory 100 and reliability, extending the lifetime of the ferroelectric memory 100. In addition, the present application implements multi-directional three-dimensional integration of multiple ferroelectric tunnel junction units 2 , which improves the storage state of the ferroelectric memory 100 .

As shown in FIG. 3 and FIG. 5, the substrate 1 is composed of a semiconductor material, such as a silicon substrate, and the substrate 1 includes a connecting region A located under each of the ferroelectric tunnel junction groups 10 and a connection area located under each of the ferroelectric tunnel junction groups 10 In the thinned region B around the connection region A, the conductive metal layer 3 disposed close to the substrate 1 is located on the surface of the connection region A and extends to the thinned region B. Thin area B, thereby forming a contact electrode.

As shown in Figure 4, the material of the ferroelectric tunnel junction unit 2 is a superlattice with an atomically ordered epitaxial structure, between the ferroelectric tunnel junction unit 2 and the conductive metal layer 3 and the ferroelectric tunnel junction unit 2 The stress inside the junction unit 2 is very small, and the dislocation and defect density at the interface are greatly reduced, so that the ferroelectric tunnel junction unit 2 has a good ferroelectric/electrode interface, which improves the ferroelectric tunnel junction The ferroelectric performance of the unit 2 reduces the problem of ferroelectric fatigue, thereby increasing the number of cycles for writing the ferroelectric memory 100 .

As shown in Figure 3 and Figure 5, the thickness of the ferroelectric layer 22 is 1nm-5nm, if the thickness of the ferroelectric layer 22 is too thin, there will be a large leakage current, and it is difficult to show ferroelectricity in the experiment If the thickness of the ferroelectric layer 22 is too thick, then it is difficult to take place the quantum tunneling effect, and the device is no longer a tunnel junction device, and the thickness of the ferroelectric layer 22 is too thick and will increase the ferroelectric tunnel junction unit 2 And the overall thickness of the finally formed ferroelectric memory 100 is not conducive to making the ferroelectric memory 100 thinner and smaller.

The material of the first conductive oxide layer 21 and the second conductive oxide layer 23 is a ferromagnetic material, and the thickness of the first conductive oxide layer 21 and the second conductive oxide layer 23 is greater than Ferromagnetism can only be observed in the experiment when the thickness is greater than or equal to 10nm, and the ferromagnetism is better when the thickness is greater than or equal to 10nm. However, when the thickness of the first conductive oxide layer 21 and the second conductive oxide layer 23 When it exceeds 50nm, the lead resistance of the electrode is relatively large, and the overall thickness of the ferroelectric memory 100 will be increased. Therefore, in this embodiment, the first conductive oxide layer 21 and the second conductive oxide layer 23 The thickness is 10-50nm.

The ferroelectric tunnel junction unit 2 composed of the ferroelectric layer 22, the first conductive oxide layer 21 and the second conductive oxide layer 23 of the above thickness has a nanoscale ultra-thin thickness, which is conducive to the realization of multilayer The lamination of the ferroelectric tunnel junction unit 2 further improves the storage state of the ferroelectric memory 100 while reducing the total thickness of the ferroelectric memory 100 . In addition, the width and length of the ferroelectric tunnel junction unit 2 can be designed according to actual needs. In this embodiment, the width and length of each ferroelectric tunnel junction unit 2 are 10nm-2um.

The material of the ferroelectric layer 22 can be (Bi, La) FeO ₃ , (Ba, Sr) TiO ₃ , (Pb, La) _1-x (Zr, Ti) _x O ₃ and other oxide perovskite materials and Hf-based oxide ferroelectric materials, etc., but not limited thereto. The materials of the first conductive oxide layer 21 and the second conductive oxide layer 23 may be La _1-x Sr _x MnO ₃ , La _1-x Ca _x MnO ₃ , La _1-x Sr _x CoO ₃ , Perovskite conductive materials such as YBaCuO ₂ , SrRuO ₃ , Nd:SrTiO ₃ and SrIrO ₃ , where 0<x<1, but not limited thereto. Wherein, the materials of the first conductive oxide layer 21 and the second conductive oxide layer 23 may be the same or different. The above-mentioned perovskite conductive material is conducive to the epitaxial growth of ferroelectric materials with excellent ferroelectric layer at the ferroelectric/electrode interface, and at the same time on the above-mentioned ferroelectric material is conducive to the growth of the above-mentioned perovskite conductive material with excellent conductivity at the ferroelectric/electrode interface oxide film, therefore, the first conductive oxide layer 21, the second conductive oxide layer 23 and the ferroelectric layer 22 use the above materials, which can be beneficial to the first conductive oxide layer 21, the The superlattice epitaxial growth of the second conductive oxide layer 23 and the ferroelectric layer 22 forms an atomically ordered epitaxial structure, thereby ensuring that the ferroelectric layer 22 is in contact with the first conductive oxide layer 21 and the first ferroelectric layer 22 respectively. The second conductive oxide layer 23 has a good ferroelectric/electrode interface, thereby improving the ferroelectric performance of the ferroelectric tunnel junction unit 2 .

As shown in FIG. 4 and FIG. 5 , the material of the conductive metal layer 3 may be conductive metals such as W, Co, and Al. By replacing part of the conductive oxide with a traditional metal, the thickness of the first conductive oxide layer 21 and the second conductive oxide layer 23 grown by high-temperature epitaxial growth can be effectively reduced. , which is beneficial to reduce the lead resistance of the electrode and improve the switching ratio.

As shown in Figure 4, a layer of first barrier layer 4 is arranged between the ferroelectric tunnel junction unit 2 and the adjacent conductive metal layer 3, and the first barrier layer 4 and the conductive metal layer 3 contact, the first barrier layer 4 forms a potential barrier between the conductive metal layer 3 and the ferroelectric tunnel junction unit 2, electrons must have a certain energy to pass through this potential barrier, if the conductive metal layer 3 is added Positive voltage will weaken the electric field in the potential barrier region, and the height of the potential barrier will be reduced. Part of the electrons in the conductive metal layer 3 can cross this potential barrier, forming a forward current, and prompting the reversal of the ferroelectric polarization direction of the ferroelectric layer 22. ; and if a reverse voltage is applied to the first barrier layer 4, the direction of the applied electric field is the same as that of the electric field in the barrier region, which instead increases the height of the barrier. At this time, it is difficult for the electrons in the ferroelectric tunnel junction unit 2 to cross this barrier and enter In the conductive metal layer 3 , the reverse current is very small, so that the conduction and barrier effects between the first barrier layer 4 and the conductive metal layer 3 are realized. Since the first barrier layer 4 has a conductive effect and a barrier effect, therefore, as shown in FIG. The first barrier layer 4 between the oxide layer 23) and the conductive metal layer 3 can also serve as a part of the first electrode a (or the second electrode b). By adding the first barrier layer 4 between the conductive metal layer 3 and the ferroelectric tunnel junction unit 2, while having a conductive effect, it also has an excellent barrier effect, which can prevent the electrons from the ferroelectric tunnel junction unit 2 from going to the conductive metal layer. The diffusion effect of 3 is further beneficial to reduce the risk of ferroelectric fatigue in the ferroelectric tunnel junction unit 2, thereby increasing the number of write cycles of the ferroelectric memory 100 and prolonging the life of the ferroelectric memory 100.

According to the above-mentioned conductive and blocking characteristics of the first barrier layer 4 , it is necessary to select a suitable material to achieve the purpose of improving the reliability and life of the ferroelectric tunnel junction unit 2 . In this embodiment, the material of the first barrier layer 4 can be at least one of the combinations of Ir/IrO, Ru/RuO, Ti/TiN, Ta/TaN, Ta/TaSiN, Ti/TiSiN, Zr/ZrO, etc. The first barrier layer 4 formed of such materials can effectively improve the conduction and barrier effects of the first barrier layer 4 , thereby improving the reliability and lifespan of the ferroelectric memory 100 .

The thickness of the first barrier layer 4 is 1nm-5nm, further 1nm-4nm, further 1nm-3.5nm, if the thickness of the first barrier layer 4 is greater than 5nm, it can tunnel carriers/charges If the thickness is smaller, the read current difference is relatively small, and misreading is prone to occur; if the thickness is less than 1 nm, the isolation and barrier effect cannot be achieved. Therefore, the thickness of the first barrier layer 4 is selected from 1 nm-5 nm.

As shown in FIG. 4 and FIG. 5 , the ferroelectric memory 100 further includes a buffer layer 6 located on the surface of the substrate 1 , and the buffer layer 6 is disposed corresponding to the ferroelectric tunnel junction group 10 . The buffer layer 6 can flatten the surface of the substrate 1 and provide lattice parameters that match the subsequently grown sacrificial layer 20 (in conjunction with FIG. 7A ), which is conducive to the epitaxial growth of a ferroelectric tunnel junction unit 2 with a good interface and orderly atoms. ; At the same time, adding the buffer layer 6 can reduce the internal stress, thereby improving the ferroelectric performance of the ferroelectric memory 100 .

The material of the buffer layer 6 can be SrTiO ₃ , LaNiO ₃ etc.; the thickness of the buffer layer 6 is 2nm-100nm, if the thickness of the buffer layer 6 is too thin, it will not be able to match the lattice parameters and reduce the stress If the thickness of the buffer layer 6 is too thick, the overall thickness of the ferroelectric memory 100 will be thicker, which is not conducive to the miniaturization of the ferroelectric memory 100 .

As shown in Figures 4 and 5, the substrate 1 is provided with a second barrier layer 5 corresponding to the surface of each thinned region B, and the second barrier layer 5 can optimize the surface of the substrate 1, which is beneficial to The growth of the conductive metal layer 3 on the surface of the thinned region B. The second barrier layer 5 also extends to the surface of the buffer layer 6 close to the ferroelectric tunnel junction group 10, the thickness of the second barrier layer 5 is 1nm-5nm, and the material of the second barrier layer 5 Can be any combination of Ir/IrO, Ru/RuO, Ti/TiN, Ta/TaN, Ta/TaSiN, Ti/TiSiN, Zr/ZrO, etc., the second barrier layer 5 is mainly to improve the conductive metal layer 3 Bonding strength with the substrate 1.

As shown in FIG. 4 , two openings 8 are provided on opposite side edges of each conductive metal layer 3 in each ferroelectric tunnel junction group 10 , and each ferroelectric tunnel junction group 10 is provided with The sidewalls of the openings 8 are provided on the insulating layer 7, and the insulating layer 7 extends into each of the openings 8, and the insulating layer 7 is used to isolate the ferroelectric tunnel junction unit 2 of different layers and the conductive elements of different layers. Metal layer 3.

In this application, as shown above, N may be an integer greater than or equal to 1, therefore, one ferroelectric tunnel junction group 10 may include one or more ferroelectric tunnel junction units 2, and the ferroelectric memory One or more ferroelectric tunnel junctions 10 may be included in 100 . When each ferroelectric tunnel junction group 10 has a plurality of ferroelectric tunnel junction units 2 stacked, wherein, a plurality of ferroelectric tunnel junction units 2 can have different coercive field values, and the coercive field is ferroelectric The critical field strength at which the polarization state of the electric material is reversed under the action of an external electric field, therefore, the plurality of ferroelectric tunnel junction units 2 will exhibit different polarization directions under different external excitation conditions, so that the The ferroelectric memory 100 can have multiple different storage states at the same time. In this embodiment, as shown in FIG. 4 and FIG. 5, the ferroelectric memory 100 includes a ferroelectric tunnel junction group 10, wherein the ferroelectric tunnel junction group 10 includes two ferroelectric tunnel junction units stacked. 2.

When a plurality of ferroelectric tunnel junction units 2 are stacked, since a plurality of ferroelectric tunnel junction units 2 have different coercive field performance parameters respectively, therefore, between the plurality of ferroelectric tunnel junction units 2 A variety of different storage states can be realized by adjusting the following physical parameters: 1) adjusting the material type, thickness, and molding process conditions of the ferroelectric layer 22 located in different ferroelectric tunnel junction units 2; Different currents of ferroelectric tunnel junction cell 2. One or more of the above-mentioned parameters can be adjusted, so that the coercive fields of the multiple ferroelectric tunnel junction units 2 have a large difference, and it is easier to modulate the multiple ferroelectric tunnel junction units 2 with Different resistance states reduce the probability of misreading of different ferroelectric tunnel junction units 2 . Since both surfaces of each ferroelectric layer 22 are provided with the first electrode a and the second electrode a, the flow of the corresponding ferroelectric layer 22 can be controlled by regulating the electrodes corresponding to the different ferroelectric tunnel junction units 2. The current is more precisely regulated and is not limited by the stacking height of the ferroelectric tunnel junction unit 2, and the current will not be too small to be read because the stacking height is too high; moreover, since each ferroelectric tunnel junction unit 2 exists independently, The ferroelectric layers 22 in different ferroelectric tunnel junction units 2 will not affect each other, and the ferroelectricity of each layer of ferroelectric layer 22 is less affected by other layers, and can stably present a variety of different ferroelectric layers. resistance state; in addition, since the electrodes of each ferroelectric tunnel junction unit 2 can be adjusted independently, the operation difficulty of the ferroelectric memory 100 is relatively low, which is beneficial to the practical application of the ferroelectric memory 100 .

In this application, conductive metal layers 3 are respectively arranged on opposite surfaces of ferroelectric tunnel junction unit 2. When the first conductive oxide layer 21 and the adjacent conductive metal layer 3 are composited as the first electrode a, the second conductive oxide layer 21 is used as the first electrode a. When the oxide layer 23 and the adjacent conductive metal layer 2 are used as the second electrode b in combination, compared with the fully conductive oxide electrodes provided on the opposite surfaces of the ferroelectric layer 22, the above-mentioned first electrode a and the second electrode of the present application The two electrodes b can effectively reduce the lead resistance of the electrode and help to improve the switching ratio; since the ferroelectric layer 22 and the first conductive oxide layer 21 (or the second conductive oxide layer 23), the conductive metal layer 3 and the first conductive There is a good interface between the oxide layer 21 (or the second conductive oxide layer 23). Compared with setting all-metal electrodes on both surfaces of the ferroelectric layer 22, the present application has a good interface between the ferroelectric layer 22 and the conductive metal layer 3. Adding the first conductive oxide layer 21 and the second conductive oxide layer 23 between them can make the layers of the ferroelectric tunnel junction group 10 have a good interface effect, reduce the interface defects of the ferroelectric/electrode, and help to improve The ferroelectric properties of the ferroelectric tunnel junction group 10; due to the interface defects of the ferroelectric/electrode, especially the interface stress, the ferroelectric fatigue of the ferroelectric memory 100 can be caused, therefore, the ferroelectric/electrode of the ferroelectric tunnel junction group 10 of the present application After the electrode interface defects are reduced, it is beneficial to reduce the risk of ferroelectric fatigue in the ferroelectric memory 100, thereby improving the cycle times and reliability of writing in the ferroelectric memory, and prolonging the service life of the ferroelectric memory. In addition, the present application implements multi-directional three-dimensional integration of multiple ferroelectric tunnel junction units 2 , which improves the storage state of the ferroelectric memory 100 .

The ferroelectric memory 100 can realize high-performance storage of the memory, and the ferroelectric memory 100 can be embedded in a complementary metal-oxide semiconductor chip (Complementary Metal-Oxide-Semiconductor, COMS), planar CMOS, fin field effect transistor ( FinFET) and Gate-All-Around FET (Gate-All-Around FET, GAA FET), etc., to form a high-performance chip with ultra-fast, low-power non-volatile embedded memory.

As shown in FIG. 6 , the present application also provides a method for preparing the above-mentioned ferroelectric memory 100 , including the following steps (it is understood that the following steps can be combined with FIG. 7A to FIG. 7G ).

S1, forming at least one fin body 30 on the surface of the substrate 1, each of the fin bodies 30 includes alternately stacked N+1 sacrificial layers 20 and N ferroelectric tunnel junction units 2, each of the ferroelectric Each tunnel junction unit 2 includes a first conductive oxide layer 21 , a ferroelectric layer 22 and a second conductive oxide layer 23 stacked in sequence, wherein N is an integer greater than or equal to 1.

S2, removing each layer of the sacrificial layer 20 in each of the fins 30 and forming a conductive metal layer 3 at the position of the sacrificial layer 20 to form at least one ferroelectric tunnel junction group 10, thereby obtaining the Ferroelectric memory 100.

For step S1, please refer to FIG. 7A and FIG. 7B. The specific forming method of the fin body 30 includes steps:

Referring to FIG. 7A in step S11 , an N+1 intermediate sacrificial layer 20 a and N ferroelectric tunnel junctions 2 a are formed on the surface of the substrate 1 . Each ferroelectric tunnel junction 2a includes a first intermediate conductive oxide layer 21a, an intermediate ferroelectric layer 22a and a second intermediate conductive oxide layer 23a stacked in sequence.

In this embodiment, the substrate 1 is a silicon substrate. An intermediate buffer layer 6 a is also formed before the intermediate sacrificial layer 20 a is formed on the surface of the substrate 1 .

In this embodiment, the intermediate buffer layer 6a (corresponding to the subsequently formed buffer layer 6), the intermediate sacrificial layer 20a (corresponding to the subsequently formed sacrificial layer 20), and the ferroelectric tunnel junction 2a ( The ferroelectric tunnel junction unit 2) corresponding to the subsequent formation is grown on the surface of the substrate 1 . A specific growth method may be physical vapor deposition (PVD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE). The growth temperature of superlattice epitaxial growth is 400-800°C.

Step S12, referring to FIG. 7B , patterning each layer of the intermediate sacrificial layer 20a and each of the ferroelectric tunnel junctions 2a to form at least one layer of the sacrificial layer 20 and at least one ferroelectric tunnel junction unit 2 respectively , so as to obtain the at least one fin body 30 .

The substrate 1 includes at least one connection region A and a thinned region B located around each connection region A, and each of the ferroelectric tunnel junctions 2a and each ferroelectric tunnel junction 2a corresponding to the thinned region B is removed by dry etching. Layer the sacrificial layer 20 a as an intermediate to form at least one fin body 30 . Wherein, the substrate 1 is also partially etched corresponding to the thinned region B, and the etching depth is smaller than the thickness of the substrate 1 . In this embodiment, the intermediate buffer layer 6 corresponding to the thinned region B is also etched simultaneously to form the buffer layer 6 located in the connection region A. In this embodiment, only one fin body 30 is formed on the surface of the substrate 1 . It can be understood that, in other embodiments, a plurality of fins 30 arranged horizontally may be formed on the surface of the substrate 1 to facilitate subsequent formation of a plurality of ferroelectric tunnel junction groups 10 .

Each layer in the buffer layer 6, the sacrificial layer 20, and the ferroelectric tunnel junction unit 2 grown by superlattice epitaxial growth in step S11 combined with the growth temperature has an atomically ordered epitaxial structure. Has an excellent interface effect.

In this embodiment, the material of the buffer layer 6 is SrTiO ₃ or LaNiO ₃ , and the thickness of the buffer layer 6 is 2-100 nm. The material of the sacrificial layer 20 is a material that can be selectively etched, specifically Sr ₃ Al ₂ O ₆ or La _1-x Sr _x MnO ₃ , and the thickness of the sacrificial layer 20 may be 10 nm-100 nm.

By adding the buffer layer 6, the surface of the substrate 1 can be flattened, and the quality of epitaxial growth of each layer can be improved; moreover, the buffer layer 6 can also buffer the internal stress of the sacrificial layer 20 grown on its surface, further Improve the growth quality of each layer, reduce the internal stress and internal defects of the ferroelectric memory 100; in addition, through material selection, the buffer layer 6 can provide lattice parameters matched with the sacrificial layer 20 grown on its surface, the sacrificial layer 20 and the first conductive oxide layer 21 have matching lattice parameters, therefore, by adding the buffer layer 6, it is beneficial to epitaxially grow the ferroelectric tunnel junction unit 2 with ordered atoms and excellent interface.

The thickness of the sacrificial layer 20 determines the thickness of the subsequently replaced conductive metal layer 3 , therefore, the thickness of the sacrificial layer 20 can be designed according to the actual thickness of the conductive metal layer 3 . The number of layers of the ferroelectric tunnel junction unit 2 is not limited to the number of layers shown in FIG. 7A , but can be any number of layers.

For step S2, please refer to FIG. 7C to FIG. 7G. The specific preparation method of the ferroelectric tunnel junction 10 includes steps:

Step S21 , referring to FIG. 7C , is to partially etch the opposite side edge portions of each sacrificial layer 20 in each fin body 30 to form two openings 8 .

The opening 8 is formed by dry etching (such as etching with hydrochloric acid vapor). The exposed sacrificial layer 20 is etched away, and the etching vapor will not affect the ferroelectric tunnel junction unit 2 .

In this embodiment, the number of the openings 8 increases with the increase in the stacked number of the ferroelectric tunnel junction units 2 .

Referring to FIG. 7D in step S22 , an insulating layer 7 is formed on the sidewall of each of the fins 30 provided with the opening 8 , and the insulating layer 7 extends into each of the openings 8 .

By forming the insulating layer 7 on the opposite side walls of each of the fins 30, it can provide support for the subsequent formation of the window area 40, referring to FIG. 7E; at the same time, the molding of the insulating layer 7 can be used for isolation The ferroelectric tunnel junction units 2 in different layers and the subsequently formed conductive metal layer 3 in different layers are shown in FIG. 4 .

In this embodiment, the insulating layer 7 may also extend to a part of the surface of the fin body 30 away from the substrate 1 .

Step S23 , referring to FIG. 7E , removes the remaining sacrificial layer 20 by dry etching (such as hydrochloric acid vapor etching), so as to release the channel layer of the ferroelectric tunnel junction unit 2 and form a window region 40 . In this embodiment, the number of the window opening regions 40 increases with the increase of the stacked number of the ferroelectric tunnel junction units 2 .

Referring to FIG. 7F and FIG. 7G in step S23, a barrier coating film 50 is formed on the surface of each ferroelectric tunnel junction unit 2 corresponding to each window area 40 and the surface of the substrate 1 corresponding to the window area 40, and The window area 40 formed with the barrier cladding film 50 is filled with a metal material to form a conductive metal cladding film 60, wherein the barrier cladding film 50 and the conductive metal cladding film 60 extend until the ferroelectric tunnel junction unit 2 is not insulated Layer 7 covers the surface.

In this embodiment, the barrier coating film 50 and the conductive metal coating film 60 also extend to the thinned region B of the substrate 1 .

In this embodiment, the material of the barrier coating film 50 may be a combination of Ir/IrO, Ru/RuO, Ti/TiN, Ta/TaN, Ta/TaSiN, Ti/TiSiN, Zr/ZrO and the like. The barrier cladding film 50 can be formed on the surface of the buffer layer 6 and the surface of the ferroelectric tunnel junction unit 2 by superepitaxy growth, and the specific growth method can be referred to above.

In this embodiment, the material of the conductive metal coating film 60 can be conductive metals such as W, Co, Al, etc., and can be formed on the surface of the barrier coating film 50 by the aforementioned methods such as PVD, ALD, or MBE.

In step S24, please refer to FIG. 4 and FIG. 5 in combination, remove the barrier coating film 50 and the conductive metal coating film 60 located on the sidewall of each ferroelectric tunnel junction unit 2, to form a ferroelectric tunnel junction unit located at each 2 The first barrier layer 4 on the opposite surfaces, the second barrier layer 5 on the substrate 1 and the buffer layer 6, and the conductive metal layer 3 on the surface of the first barrier layer 4.

The first barrier layer formed on the opposite surfaces of each ferroelectric tunnel junction unit 2 is formed by etching away the barrier coating film 50 and the conductive metal coating film 60 on the side walls of each ferroelectric tunnel junction unit 2. 4 and the conductive metal layer 3 are not conducting.

In this embodiment, the thickness of the first barrier layer 4 is 1 nm-5 nm. It can be understood that the thickness of the conductive metal layer 3 is the same as that of the aforementioned sacrificial layer 20 , specifically 10 nm-100 nm.

By forming an integrated barrier coating film 50 and a conductive metal coating film 60, and then etching, a multi-layer first barrier layer 4 and a multi-layer conductive metal layer 3 can be formed at one time, which simplifies the manufacturing process and significantly improves the efficiency. , and can ensure the consistency of the thickness of each first barrier layer 4 and each conductive metal layer 3 , and improve the ferroelectric performance of the ferroelectric memory 100 . In addition, a first barrier layer 4 is first grown on the surface of the ferroelectric tunnel junction unit 2, and then a conductive metal layer 3 is formed on the surface of the first barrier layer 4, which is conducive to the growth of the conductive metal layer 3 and improves the ferroelectric tunnel junction. The interface bonding force between the unit 2 and the conductive metal layer 3 is to form an excellent ferroelectric/electrode interface, and the first barrier layer 4 has a conductive effect and a barrier effect, which can help to improve the ferroelectric tunnel junction group 10. Ferroelectric properties reduce the risk of ferroelectric fatigue in the ferroelectric memory 100 , thereby improving the cycle times and reliability of writing in the ferroelectric memory 100 and prolonging the life of the ferroelectric memory 100 .

In the preparation method of the ferroelectric memory 100 of the present application, the ferroelectric tunnel junction unit 2 can be guaranteed to have a good ferroelectric/electrode interface by adopting the method of lattice-matched epitaxial growth on the substrate 1. It is beneficial to improve the ferroelectric performance of the ferroelectric memory 100 and increase the number of write cycles; by replacing the sacrificial layer 20 with the conductive metal layer 3, it is possible to avoid directly growing a ferroelectric tunnel junction on the surface of the conductive metal layer 3 under high temperature conditions Unit 2 can realize the compounding of the conductive metal layer 3 and the first conductive oxide layer 21 (or the second conductive oxide layer 23) in the process; moreover, it can form vertically stacked and horizontally arranged multilayer conductive The metal layer 3 is beneficial to realize multi-directional three-dimensional integration of multiple ferroelectric tunnel junction units 2 and improve the storage state. The preparation method is simple, simplifies the manufacturing process, improves the production efficiency, and is beneficial to reduce the cost, can be realized by using conventional molding equipment, is easy to operate, and is easy to realize industrialization.

As shown in FIG. 8 , the embodiment of the present application also provides an electronic device 200 , which includes a casing 210 and the above-mentioned ferroelectric memory 100 inside the casing 210 . The electronic device 200 shown in FIG. 8 is a mobile phone, but not limited to the mobile phone.

It should be noted that the above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto, and any person familiar with the technical field can easily think of changes or substitutions within the scope of the technology disclosed in the application , should be covered within the protection scope of the present application; in the case of no conflict, the implementation modes and the features in the implementation modes of the application can be combined with each other. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims (23)

1. A ferroelectric memory, characterized in that it includes a substrate and at least one ferroelectric tunnel junction group on the substrate, each of the ferroelectric tunnel junction groups includes stacked N ferroelectric tunnel junction units and N+1 conductive metal layers, the N ferroelectric tunnel junction units and the N+1 conductive metal layers are arranged alternately, each of the ferroelectric tunnel junction units includes first conductive oxide stacked in sequence layer, a ferroelectric layer and a second conductive oxide layer, wherein N is an integer greater than or equal to 1.
2. The ferroelectric memory according to claim 1, wherein a first barrier layer is provided between the ferroelectric tunnel junction unit and the adjacent conductive metal layer.
3. The ferroelectric memory according to claim 1 or 2, wherein the material of the first conductive oxide layer is La _1-x Sr _x MnO ₃ , La _1-x Ca _x MnO ₃ , La _1-x At least one of Sr _x CoO ₃ , YBaCuO ₂ , SrRuO ₃ , Nd:SrTiO ₃ and SrIrO ₃ , where 0<x<1;

   The material of the second conductive oxide layer is La _1-x Sr _x MnO ₃ , La _1-x Ca _x MnO ₃ , La _1-x Sr _x CoO ₃ , YBaCuO ₂ , SrRuO ₃ , Nd:SrTiO ₃ and SrIrO At least one of ₃ , where 0<x<1.
4. The ferroelectric memory according to claim 1, wherein the material of the ferroelectric layer is (Bi, La) FeO ₃ , (Ba, Sr) TiO ₃ , (Pb, La) _1-x (Zr, At least one of Ti) _x O ₃ and Hf-based oxides.
5. The ferroelectric memory according to claim 1, wherein the material of the conductive metal layer is at least one of W, Co and Al.
6. The ferroelectric memory according to claim 2, wherein the material of the first barrier layer is Ir/IrO, Ru/RuO, Ti/TiN, Ta/TaN, Ta/TaSiN, Ti/TiSiN, Zr/ At least one group of ZrO.
7. The ferroelectric memory according to claim 1, wherein a buffer layer is provided on the surface of the substrate close to the ferroelectric tunnel junction group.
8. The ferroelectric memory according to claim 7, wherein the material of the buffer layer is SrTiO ₃ or LaNiO ₃ .
9. The ferroelectric memory according to claim 1, wherein the substrate comprises at least one connection region and a thinned region around each connection region, each connection region is provided with one of the ferroelectric Electric tunnel junction groups, the conductive metal layer close to the substrate in each ferroelectric tunnel junction group extends to the corresponding thinned region.
10. The ferroelectric memory according to claim 9, wherein a second barrier layer is provided on a surface of the substrate corresponding to each of the thinned regions.
11. The ferroelectric memory according to claim 10, wherein the material of the second barrier layer is Ir/IrO, Ru/RuO, Ti/TiN, Ta/TaN, Ta/TaSiN, Ti/TiSiN, Zr/ At least one group of ZrO.
12. The ferroelectric memory according to claim 1, characterized in that two openings are provided on opposite side edges of each conductive metal layer in each ferroelectric tunnel junction group, and each ferroelectric The tunnel junction is provided with an insulating layer on the side wall of the opening, and the insulating layer extends into each of the openings.
13. A method for preparing a ferroelectric memory, comprising:

    At least one fin body is formed on the surface of the substrate, each of the fin bodies includes alternately stacked N+1 sacrificial layers and N ferroelectric tunnel junction units, and each of the ferroelectric tunnel junction units includes sequentially stacked A first conductive oxide layer, a ferroelectric layer and a second conductive oxide layer are provided, wherein N is an integer greater than or equal to 1; and

    Each layer of the sacrificial layer in each of the fins is removed and a conductive metal layer is formed at the position of the sacrificial layer to form at least one ferroelectric tunnel junction group, thereby obtaining the ferroelectric memory.
14. The preparation method according to claim 13, wherein the preparation method of the at least one fin body comprises:

    forming an N+1 intermediate sacrificial layer and N ferroelectric tunnel junctions on the surface of the substrate; and

    Patterning each layer of the intermediate sacrificial layer and each of the ferroelectric tunnel junctions to respectively form at least one layer of the sacrificial layer and at least one ferroelectric tunnel junction unit, thereby obtaining the at least one fin body.
15. The preparation method according to claim 13 or 14, wherein before removing each layer of the sacrificial layer in each of the fin bodies, the preparation method further comprises:

    Partially etching the opposite side edge portions of each layer of the sacrificial layer in each of the fins to form two openings; and

    An insulating layer is formed on the sidewall of each of the fins provided with the opening, and the insulating layer extends into each of the openings.
16. The preparation method according to any one of claims 13 to 15, wherein, between removing the sacrificial layer and forming the conductive metal layer, the preparation method further comprises:

    A first barrier layer is formed at the position of each sacrificial layer.
17. The preparation method according to claim 13, wherein each sacrificial layer and each ferroelectric tunnel junction unit are formed on the surface of the substrate by a superlattice epitaxial growth process at a growth temperature of 400-800°C.
18. The preparation method according to claim 17, wherein the superlattice epitaxial growth method includes physical vapor deposition (PVD), atomic layer deposition (ALD) or molecular beam epitaxy (MBE).
19. The preparation method according to claim 13, characterized in that, before forming at least one fin body on the surface of the substrate, the preparation method further comprises:

    A buffer layer is formed on the surface of the substrate.
20. The manufacturing method according to claim 16, wherein the substrate comprises at least one connection region and a thinning region located around each connection region, and each connection region is formed with one fin , the conductive metal layer close to the substrate in each fin body extends to the corresponding thinned region.
21. The preparation method according to claim 20, wherein, while forming the first barrier layer, the preparation method further comprises:

    A second barrier layer is formed on the surface of the substrate corresponding to each of the thinned regions.
22. The preparation method according to claim 13, characterized in that, the material of the sacrificial layer is Sr ₃ Al ₂ O ₆ or La _{1- x} Sr _x MnO ₃ .
23. An electronic device, characterized in that the electronic device comprises the ferroelectric memory according to any one of claims 1-12.

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