WO2023112312A1

WO2023112312A1 - Semiconductor device and manufacturing method for same

Info

Publication number: WO2023112312A1
Application number: PCT/JP2021/046752
Authority: WO
Inventors: 俊明岩松
Original assignee: 三菱電機株式会社
Priority date: 2021-12-17
Filing date: 2021-12-17
Publication date: 2023-06-22
Also published as: JPWO2023112312A1

Abstract

The purpose of the present disclosure is to provide a semiconductor device and a manufacturing method therefor, whereby reliability can be enhanced. A semiconductor device according to the present disclosure comprises: a silicon carbide substrate of a first conductivity type; a drift layer of the first conductivity type formed on the silicon carbide substrate; a plurality of well regions of a second conductivity type formed selectively on a surface layer of the drift layer; a source region of the first conductivity type formed selectively on a surface layer of each of the well regions; a low resistance region formed on the surface layer of the drift layer, between the well regions adjacent when viewed planarly, and having an impurity concentration higher than that of the drift layer; a gate insulating film formed throughout on the source region, on the well regions, and on the low resistance region; and a gate electrode formed on the gate insulating film. The gate insulating film includes a first region contacting the well regions, and a second region contacting the low resistance region. The density of a positive fixed charge in the second region is higher than the density of a positive fixed charge in the first region.

Description

Semiconductor device and its manufacturing method

The present disclosure relates to a semiconductor device having a high voltage MOSFET and a manufacturing method thereof.

As a semiconductor device for power control, a semiconductor device with a gate electrode of MOS structure such as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or Insulated Gate Bipolar Transistor (IGBT) (hereinafter referred to as "semiconductor (also called "switching element") are widely used.

In order to save energy in power electronics equipment such as inverters, it is necessary to reduce the loss of semiconductor switching elements such as MOSFETs. Since the loss of a semiconductor switching element is determined by the conduction loss of the element and the switching loss of the element, wide bandgap semiconductor materials such as silicon carbide (SiC) or gallium nitride (GaN) are used to reduce these. Development of semiconductor switching elements is underway.

On the other hand, in order to control high power, it is necessary to improve the reliability and stability of semiconductor switching elements. In particular, the SiC-MOSFET has a higher dielectric breakdown resistance than the Si-MOSFET, so the drift concentration can be set to a high concentration. A large electric field is applied. When a large voltage is applied to the gate insulating film, it causes deterioration and destruction of the gate insulating film, that is, a decrease in the breakdown voltage of the semiconductor switching element. Here, SiC-MOSFET means a MOSFET using SiC, and Si-MOSFET means a MOSFET using Si.

For example, Patent Documents 1 to 4 below disclose conventional semiconductor devices.

In Patent Document 1, by providing a p-type electric field relaxation region in a JFET (Junction Field-Effect Transistor) region formed in an n-type epitaxial layer in contact with the gate insulating film, the SiC-MOSFET is turned off when the gate insulating film is affected. Structures have been proposed to moderate the electric field intensity.

In Patent Document 2, the purpose is to improve the reliability of the gate oxide film during the OFF operation of the MOSFET. A structure that mitigates the

　In order to improve the switching characteristics of semiconductor devices, it is effective to reduce the capacitance. Patent Document 3 proposes a structure in which the gate insulating film on the JFET region is thickened in order to suppress the reduction of the drain current and improve the switching characteristics.

In the SiC-MOS structure, there is a high density of interface states at the interface between the gate insulating film and the semiconductor layer, and the channel mobility is extremely low. Therefore, in the SiC-MOS structure, the channel resistance increases and the on-resistance accordingly increases. Patent Literature 4 discloses applying a process technology for introducing an appropriate amount of nitrogen to the interface between the gate insulating film and the drift layer.

Japanese Patent No. 5895750 Japanese Patent No. 5995701 JP 2014-60272 A JP 2011-82454 A

In the structure of Patent Document 1, when the MOSFET is turned on, the drain-source current is hindered by the depletion layer spreading from the electric field relaxation region, and the resistance value of the well region (so-called JFET resistance value) increases. . Especially in SiC-MOSFET, the film thickness of the epitaxial layer, which is the drift region, can be made thin and the carrier density in the epitaxial layer can be increased. resistance and channel resistance. In Patent Document 1, an attempt is made to suppress the resistance by setting the film thickness of the electric field relaxation layer thin, but the resistance value is not sufficiently low. Therefore, in the SiC-MOSFET disclosed in Patent Document 1, the reliability of the gate insulating film is improved, but the problem is the reduction of the on-resistance.

When a negative bias is applied as a gate voltage when the MOSFET is off, holes are injected from the JFET section into the gate insulating film. This hole injection may damage the gate insulating film. Patent Document 2 discloses setting a negative fixed charge in the gate insulating film. There were cases of damage.

In Patent Document 3, increasing the thickness of the gate insulating film on the well reduces the drain current flowing through the channel, so only the gate insulating film on the JFET region is thickened. In Patent Document 3, the gate insulating film on the JFET region is thickened in order to reduce the capacitance, and fixed charge is not mentioned. From the viewpoint of the reliability of the gate insulating film, it is effective to reduce the electric field by increasing the thickness of the gate insulating film. It is valid to set

In Patent Document 4, a moderate amount of nitrogen is introduced into the interface between the gate insulating film on the well of the SiC-MOSFET and the drift layer. When the nitrogen concentration is set to a high concentration, there is a problem that the threshold voltage is extremely lowered. Therefore, there is an upper limit to the concentration of nitrogen introduced into the interface between the gate insulating film on the well of the SiC-MOSFET and the drift layer. In addition, Document 4 does not refer to the reliability of the gate insulating film in the MOSFET or JFET portion.

As described above, in conventional semiconductor devices, it is not possible to achieve both a reduction in resistance during ON operation and a reduction in breakdown voltage of the gate insulating film during OFF operation, and there is room for improvement in order to improve reliability. was there.

The present disclosure has been made to solve such problems, and aims to provide a semiconductor device capable of improving reliability and a method of manufacturing the same.

In order to solve the above problems, a semiconductor device according to the present disclosure includes a silicon carbide substrate of a first conductivity type, a drift layer of the first conductivity type formed on the silicon carbide substrate, and a surface layer of the drift layer selectively having a a plurality of well regions of the second conductivity type formed in the region, source regions of the first conductivity type selectively formed in the surface layer of each well region, and the well regions adjacent to each other in plan view on the surface layer of the drift layer a low-resistance region formed between the regions and having an impurity concentration higher than that of the drift layer; a gate insulating film formed over the source region, each well region, and the low-resistance region; a gate electrode formed on the film, the gate insulating film including a first region in contact with each well region and a second region in contact with the low resistance region, the density of positive fixed charges in the second region being , higher than the density of positive fixed charges in the first region.

According to the present disclosure, it is possible to improve the reliability of a semiconductor device by achieving both a reduction in resistance during ON operation and suppression of a decrease in withstand voltage of a gate insulating film during OFF operation.

The objects, features, aspects, and advantages of the present disclosure will become more apparent with the following detailed description and accompanying drawings.

1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to Embodiment 1; FIG. FIG. 4 is a cross-sectional view showing an example of a manufacturing process of the semiconductor device according to Embodiment 1; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of the semiconductor device according to Embodiment 1; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of the semiconductor device according to Embodiment 1; FIG. 11 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a second embodiment; FIG. 11 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a second embodiment; FIG. 11 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a second embodiment; FIG. 11 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a second embodiment; FIG. 11 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a second embodiment; FIG. 11 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a second embodiment; FIG. 10 is a diagram showing the result of device simulation showing the relationship between the fixed charge of the gate oxide film and the electric field passing through the gate oxide film on the JFET region according to the second embodiment; FIG. 10 is a diagram showing the result of device simulation showing the relationship between the fixed charge of the gate oxide film and the current passing through the gate oxide film on the JFET region according to the second embodiment; FIG. 11 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a third embodiment; FIG. 11 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a third embodiment; FIG. 14 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a fourth embodiment; FIG. 14 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a fourth embodiment; FIG. 14 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a fourth embodiment; FIG. 14 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a fourth embodiment; FIG. 14 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a fourth embodiment; 14 is a flow chart showing an example of a method of manufacturing a module including a semiconductor device according to a fourth embodiment;

Embodiments will be described below with reference to the attached drawings. It should be noted that the drawings are schematic representations, and the interrelationships between the sizes and positions of the images shown in different drawings are not necessarily described accurately and may be changed as appropriate. Moreover, in the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.

Also, in the following description, terms such as "upper", "lower", "side", "bottom", "front" or "back" may be used that mean specific positions and directions. These terms are used for convenience to facilitate understanding of the content of the embodiments, and are irrelevant to the direction in which they are actually implemented.

In the present disclosure, the term “fixed charge” means a charge that does not substantially move during operation in the operating temperature range of the semiconductor device according to the present disclosure, and is in a positively or negatively charged state, or in a positively or negatively charged state. It means a substance or the like in an electrically charged state. Fixed charge is, for example, a charge state caused by crystal distortion or defect, a charge state caused by interatomic bond distortion or defect, positively or negatively charged atoms, molecules, fine particles, microcrystals, etc. Impurities, etc. A substance or the like may be in a positively charged state due to electrons being emitted from a donor level to be created, a negatively charged state due to electrons being captured in an acceptor level, or the like.

<Embodiment 1>
<Configuration>
FIG. 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 100 according to Embodiment 1. FIG. The semiconductor device 100 is an n-channel SiC-MOSFET.

As shown in FIG. 1, an n-type drift layer 3 is formed on an n-type (first conductivity type) silicon carbide substrate 1 . A p-type (second conductivity type) well region 6 is selectively formed in the surface layer of the drift layer 3 .

An n-type source region 5 is formed in the surface layer of the well region 6 , and a p-type well contact region 9 is formed adjacent to the source region 5 . Well contact region 9 is provided to equalize the potentials of source region 5 and well region 6 . By providing the well contact region 9, the operation of the parasitic transistor can be suppressed.

In the surface layer of the drift layer 3, low-resistance regions 20 having an impurity concentration higher than that of the drift layer 3 are formed between the well regions 6 adjacent to each other in plan view. A low resistance region 20 is included in the JFET region 4 .

The drift layer 3 , the source region 5 , the well region 6 , the well contact region 9 and the low resistance region 20 constitute the semiconductor layer 2 .

An insulating gate insulating film 7 is formed from a portion of the source region 5 to the drift layer 3 , and a gate electrode 8 is formed on the gate insulating film 7 . An interlayer insulating film 13 is formed to cover the gate electrode 8 to separate the gate electrode 8 and the source electrode 11 . Interlayer insulating film 13 is not formed on well contact region 9 in order to provide contact hole 31 . A barrier metal 32 is formed on interlayer insulating film 13 and well contact region 9 . A source electrode 11 is formed on the barrier metal 32 . A drain electrode 12 is formed on the back surface of silicon carbide substrate 1 .

There is nitrogen at the interface between the gate insulating film 7 and the well region 6, and positive fixed charges 41 are provided by the nitrogen. Nitrogen is also present at the interface between the gate insulating film 7 and the JFET region 4, which will be described later, and positive fixed charges 40 are provided by the nitrogen. Fixed charge 41 is provided in gate insulating film 7 near the interface between gate insulating film 7 and well region 6 . The fixed charge 40 is provided in the gate insulating film 7 near the interface between the gate insulating film 7 and the JFET region 4 . Gate insulating film 7 includes a first region in contact with well region 6 and a second region in contact with JFET region 4 . The interface between the gate insulating film 7 and the JFET region 4 is synonymous with the interface between the gate insulating film 7 and the low resistance region 20 .

The nitrogen concentration at the interface between the gate insulating film 7 and the JFET region 4 is higher than the nitrogen concentration at the interface between the gate insulating film 7 and the well region 6 . That is, the fixed charges 40 at the interface between the gate insulating film 7 and the JFET region 4 are denser than the fixed charges 41 at the interface between the gate insulating film 7 and the well region 6 .

The characteristics of the MOSFET during ON operation when a gate voltage is applied to the gate electrode are determined by the amount of carriers formed at the interface of the gate insulating film on the well region and their mobility. For example, as disclosed in Patent Document 4, there is a high-density interface state density at the interface between the gate insulating film and the well region in a conventional SiC-MOSFET, and the channel mobility of the MOSFET is extremely low. The resistance increased, and the ON resistance increased accordingly. As a countermeasure against such a problem, in Patent Document 4, characteristics are improved by applying a process technology for introducing an appropriate amount of nitrogen into the interface between the gate insulating film and the well region. However, as the concentration of nitrogen introduced into the interface between the gate insulating film and the well region increases, the amount of positive fixed charge also increases. A new problem arises. Therefore, there is an upper limit to the concentration of nitrogen introduced into the interface between the gate insulating film and the well region.

On the other hand, the resistance value of the JFET region affects the ON characteristics of the MOSFET, but the amount of fixed charges at the interface between the gate insulating film and the JFET region does not directly affect the MOSFET characteristics. During off-operation, it is necessary to consider the reliability of the gate insulating film, and it is effective to provide a higher concentration of nitrogen at the interface between the gate insulating film and the JFET region than the nitrogen concentration that limits the characteristics of the MOSFET. is.

<Operation of semiconductor device 100>
Operations of the semiconductor device 100 will be described.

In the semiconductor device 100 , when a positive voltage is applied to the gate electrode 8 , a current path is formed at the interface between the well region 6 and the gate insulating film 7 . When a positive voltage is applied to drain electrode 12 in this state, current flows from drain electrode 12 through silicon carbide substrate 1 , drift layer 3 , well region 6 and source region 5 to source electrode 11 .

In particular, in the semiconductor device 100 using a wide bandgap semiconductor material such as SiC, the drift layer 3 can be highly doped and thinned and has a low resistance. It is very effective to reduce the conduction loss of the semiconductor device 100 to reduce the resistance (JFET resistance) of the current path (JFET region 4) and the resistance of the channel portion (channel resistance).

On the other hand, when the positive voltage applied to the gate electrode 8 is removed or the negative voltage is applied to the gate electrode 8, the well region 6 near the interface of the gate insulating film 7 is depleted. Thereby, even if a high voltage is applied to the drain electrode 12, the current between the drain electrode 12 and the source electrode 11 can be interrupted.

At this time, the gate insulating film 7 is exposed to a high electric field. The amount of holes flowing from the drift layer 3 due to such an electric field can be reduced, and the reliability of the gate insulating film 7 is ensured. In particular, when SiC is used as the semiconductor material, the breakdown electric field increases. Therefore, the drift layer 3 is often designed so that a high electric field is applied, and the electric field strength applied to the gate insulating film 7 increases correspondingly. Therefore, the structure of the semiconductor device 100 according to the first embodiment is effective from the viewpoint of ensuring the reliability of the gate insulating film 7 because the positive fixed charge 40 suppresses the inflow of holes.

<Method for Manufacturing Semiconductor Device 100>
A method of manufacturing the semiconductor device 100 will be described with reference to FIGS.

As shown in FIG. 2, an n-type low-resistance silicon carbide substrate 1 is prepared (first step), and an n-type drift layer 3 is formed on silicon carbide substrate 1 by epitaxial growth (second step). In Embodiment 1, the drift layer 3 has an n-type impurity concentration of 1×10 ¹³ cm ⁻³ to 1×10 ¹⁸ cm ⁻³ and a thickness of 4 μm to 200 μm.

As shown in FIG. 3, p-type well regions 6 spaced apart from each other are selectively formed in the surface layer of the drift layer 3 (third step). Then, an n-type source region 5 is selectively formed in the surface layer of the well region 6 (fourth step). Specifically, Al ions are implanted to form a p-type well region 6 and N ions are implanted to form an n-type source region 5 using a resist or oxide film processed by photolithography as a mask. do.

The impurity concentration in well region 6 is approximately 1×10 ¹⁵ cm ⁻³ to 1×10 ¹⁸ cm ⁻³ . Further, the implantation depth of Al ions implanted when forming the well region 6 is 0.3 μm to 2.0 μm.

Source region 5 is formed so that its bottom surface is not deeper than the bottom surface of well region 6 . The impurity concentration in the source region 5 is higher than that in the well region 6 and is about 1×10 ¹⁷ cm ⁻³ to 1×10 ²¹ cm ⁻³ .

A well contact region 9 is formed in the surface layer of the well region 6 so as to be adjacent to the source region 5 in plan view. The impurity concentration of well contact region 9 is higher than that of well region 6 .

An n-type low-resistance region 20 is formed in a region where the well region 6 is not formed, that is, in the surface layer of the drift layer 3 and between the well regions 6 adjacent in plan view (fifth step). Specifically, N ions are implanted to form the n-type low resistance region 20 . The impurity concentration in the low resistance region 20 is approximately 1×10 ¹⁸ cm ⁻³ to 1×10 ²¹ cm ⁻³ . The depth of implantation of N ions to form the low resistance region 20 is 0.3 μm to 1.0 μm. The low-resistance region 20 has a higher impurity concentration as it approaches the gate insulating film 7 in the depth direction. By forming the low-resistance region 20, the impurity concentration in the vicinity of the outermost surface of the drift layer 3 becomes high, so that the JFET resistance can be lowered.

Next, annealing is performed in an atmosphere of an inert gas such as Ar gas using a heat treatment device. Annealing is performed at 1300° C. to 1900° C. for about 30 seconds to 1 hour. By performing this annealing, the ion-implanted n-type impurities such as N and p-type impurities such as Al are activated.

Next, as shown in FIG. 4, a gate insulating film 7 and a gate electrode 8 are formed (sixth and seventh steps). The gate insulating film 7 is formed by dry thermal oxidation at 1150° C. or higher. The gate insulating film 7 may be formed by a deposition method, or may be formed by performing heat treatment in a nitrogen or ammonia atmosphere after forming the gate insulating film 7 . Moreover, the gate insulating film 7 may be formed by subjecting the surface of the drift layer 3 to high temperature annealing in a hydrogen atmosphere before forming the gate insulating film 7 .

Specifically, gate insulating film 7 is formed by forming a silicon dioxide film by thermal oxidation in a high temperature oxidizing atmosphere. Alternatively, after forming a deposited silicon dioxide film by CVD (Chemical Vapor Deposition), nitriding is performed in a high-temperature ammonia atmosphere (NH ₃ ), nitrous oxide (N ₂ O) gas atmosphere, or nitric oxide (NO) gas atmosphere. A gate insulating film 7 is thus formed.

In the step of forming the gate insulating film 7, positive fixed charges 41 are formed at the interface between the gate insulating film 7 and the well region 6, and positive fixed charges 40 are formed at the interface between the gate insulating film 7 and the JFET region 4. do. Note that the drift layer 3 (low-resistance region 20) of the JFET region 4 is implanted with high-concentration nitrogen before the gate insulating film 7 is formed. More nitrogen is segregated than the amount of nitrogen. A positive fixed charge 40 having a higher concentration than the interface between the gate insulating film 7 and the well region 6 is formed at the interface between the JFET region 4 and the gate insulating film 7 in which nitrogen is segregated at a high concentration.

Since the gate insulating film 7 is formed by the same oxidation process, the thickness of the gate insulating film 7 formed on the well region 6 and the thickness of the gate insulating film 7 formed on the JFET region 4 are approximately equal to each other. are equivalent. However, if a high-concentration impurity is implanted into the low-resistance region 20 before forming the gate insulating film 7, an implantation damage layer is formed on the surface of the drift layer 3, and the implantation damage layer is oxidized to increase the speed. The oxidation can thicken the gate insulating film 7 formed on the JFET region 4 .

The gate electrode 8 is formed by depositing polysilicon by the CVD method and etching it using a resist processed by photolithography as a mask. Polysilicon may contain impurities such as phosphorus and boron. By containing impurities in the gate electrode 8, the resistance of the gate electrode 8 can be reduced.

Finally, after forming the interlayer insulating film 13, the source electrode 11 and the drain electrode 12 are formed to complete the high breakdown voltage MOSFET (semiconductor device 100) as shown in FIG. ).

The wiring leading out the gate electrode 8 and the source electrode 11 are formed by sputtering or evaporating a metal made of Al, Cu, Ti, Ni, Mo, W, Ta, their nitrides, their laminated films, or their alloy layers. It is deposited by a method and formed by patterning. The drain electrode 12 is formed by sputtering or evaporating a metal film of Ti, Ni, Ag, Au, or the like.

<Embodiment 2>
In the semiconductor device 100 according to the first embodiment, the gate insulating film 7 on the well region 6 and the gate insulating film 7 on the JFET region 4 are formed in the same step. In the second embodiment, an example in which the gate insulating film on the JFET region 4 is formed in a plurality of steps so as to be thicker than the gate insulating film on the well region 6 will be described.

<Method for Manufacturing Semiconductor Device 101>
A method of manufacturing the semiconductor device 101 according to the second embodiment will be described with reference to FIGS. 5 to 10. FIG.

As shown in FIG. 5, an n-type low-resistance silicon carbide substrate 1 is prepared, and an n-type drift layer 3 is formed on the silicon carbide substrate 1 by epitaxial growth. In Embodiment 2, the n-type impurity concentration in the drift layer 3 is 1×10 ¹³ cm ⁻³ to 1×10 ¹⁸ cm ⁻³ . Also, the thickness of the drift layer 3 is 4 μm to 200 μm.

As shown in FIG. 6, p-type well regions 6 spaced apart from each other are formed in the surface layer of the drift layer 3 . Then, an n-type source region 5 is formed in the surface layer of the well region 6 . Specifically, Al ions are implanted to form a p-type well region 6 and N ions are implanted to form an n-type source region 5 using a resist or oxide film processed by photolithography as a mask. do.

An n-type low-resistance region 20 is formed in a region where the well region 6 is not formed, that is, in the surface layer of the drift layer 3 and between the well regions 6 adjacent in plan view. Specifically, N ions are implanted to form the n-type low resistance region 20 . The impurity concentration in the low resistance region 20 is approximately 1×10 ¹⁸ cm ⁻³ to 1×10 ²¹ cm ⁻³ . The depth of implantation of N ions to form the low resistance region 20 is 0.3 μm to 1.0 μm. By forming the low-resistance region 20, the impurity concentration in the vicinity of the outermost surface of the drift layer 3 becomes high, so that the JFET resistance can be lowered.

Next, as shown in FIG. 7, a gate insulating film 15 (first gate insulating film) is formed. The gate insulating film 15 is formed by dry thermal oxidation at 1150° C. or higher. The gate insulating film 15 may be formed by a deposition method, or may be formed by performing heat treatment in a nitrogen or ammonia atmosphere after forming the gate insulating film 15 . Also, the gate insulating film 15 may be formed by subjecting the surface of the drift layer 3 to high temperature annealing in a hydrogen atmosphere before forming the gate insulating film 15 .

Specifically, gate insulating film 15 is formed by forming a silicon dioxide film by thermal oxidation in a high temperature oxidizing atmosphere. Alternatively, after forming a silicon dioxide deposition film by CVD, the gate insulating film is formed by nitriding in a high-temperature ammonia atmosphere (NH ₃ ), nitrous oxide (N ₂ O) gas atmosphere, or nitrogen monoxide (NO) gas atmosphere. 15 is formed. By performing the step of forming the gate insulating film 15, positive fixed charges are formed at the interface between the gate insulating film 15 and the well region 6 and the interface between the gate insulating film 15 and the JFET region 4, respectively.

After that, using a resist or oxide film processed by photolithography as a mask, only the gate insulating film 15 on the JFET region 4 is left, and the other gate insulating films 15 are removed (8th step). A wet process using hydrofluoric acid or dry etching may be used to remove the gate insulating film 15 .

Next, as shown in FIG. 8, a gate insulating film 16 (second gate insulating film) is formed by dry thermal oxidation at 1150° C. or higher (ninth step). Note that the gate insulating film 16 may be formed by a deposition method. After forming the gate insulating film 16, heat treatment is performed in a nitrogen or ammonia atmosphere. By performing the step of forming the gate insulating film 16, only the gate insulating film on the JFET region 4 can be thickened. In other words, the gate insulating film formed on the JFET region 4 consists of two layers of the

gate insulating films

15 and 16 and is thicker than the gate insulating film 16 formed outside the JFET region 4 .

Nitrogen is introduced into the interface between the gate insulating film 15 and the JFET region 4 in two nitridation processes, so that the nitrogen concentration is higher than that at the interface between the gate insulating film 16 and the well region 6 . Therefore, the positive fixed charges 40 at the interface between the gate insulating film 15 and the JFET region 4 are denser than the positive fixed charges 41 at the interface between the gate insulating film 16 and the well region 6 .

The subsequent steps are the same as in the first embodiment. As shown in FIG. 9, the gate electrode 8 is formed by depositing polysilicon by the CVD method and etching it using a resist processed by photolithography as a mask. Polysilicon may contain impurities such as phosphorus and boron. By containing impurities in the gate electrode 8, the resistance of the gate electrode 8 can be reduced.

Finally, after forming the interlayer insulating film 13, the source electrode 11 and the drain electrode 12 are formed to complete the high voltage MOSFET (semiconductor device 101) as shown in FIG.

<Hole Current Injected into Gate Oxide Film>
FIG. 11 shows the result of device simulation showing the relationship between the fixed charge of the gate oxide film and the electric field passing through the gate oxide film on the JFET region according to the second embodiment. FIG. 12 shows the result of a device simulation showing the relationship between the fixed charge of the gate oxide film and the current passing through the gate oxide film on the JFET region according to the second embodiment. Here, the gate oxide film corresponds to the gate insulating film 15 . Further, the gate oxide film passing current refers to the hole current injected into the gate oxide film.

The thickness of the gate oxide film (T _ox ) is two types of 40 nm and 60 nm, and the fixed charge at the interface between the gate oxide film and the JFET region is compared with three types of positive, negative, and zero. are doing.

As shown in FIG. 11, the electric field is relaxed by thickening the gate oxide film. Also, as shown in FIG. 12, focusing on the hole current that affects the breakdown life of the gate oxide film, it can be seen that positive fixed charge is effective. The amount of hole current injected into the gate oxide film can be set based on the relationship between the thickness of the gate oxide film on the JFET region 4 and the fixed charges. 11 and 12, it is most effective to thicken the gate oxide film and set positive fixed charges.

<Embodiment 3>
In the semiconductor device 100 according to the first embodiment, the gate insulating film 7 on the well region 6 and the gate insulating film 7 on the JFET region 4 are formed in the same process, the film thicknesses of both are substantially the same, and the positive fixed charge is generated. are different configurations. In the semiconductor device 102 according to the third embodiment, an example will be described in which the gate insulating film 7 on the JFET region 4 is formed significantly thicker than the gate insulating film 7 on the well region 6 by accelerated oxidation.

<Method for Manufacturing Semiconductor Device 102>
A method of manufacturing the semiconductor device 102 according to the second embodiment will be described with reference to FIGS.

As shown in FIG. 13, an n-type low-resistance silicon carbide substrate 1 is prepared, and an n-type drift layer 3 is formed on the silicon carbide substrate 1 by epitaxial growth. In Embodiment 1, the drift layer 3 has an n-type impurity concentration of 1×10 ¹³ cm ⁻³ to 1×10 ¹⁸ cm ⁻³ and a thickness of 4 μm to 200 μm.

As shown in FIG. 14, p-type well regions 6 spaced apart from each other are formed in the surface layer of the drift layer 3 . Then, an n-type source region 5 is formed in the surface layer of the well region 6 . Specifically, Al ions are implanted to form a p-type well region 6 and N ions are implanted to form an n-type source region 5 using a resist or oxide film processed by photolithography as a mask. do.

After that, the outermost layer of the drift layer 3 (low-resistance region 20) of the JFET region 4 is doped with a low concentration of about 20 nm and a concentration of about 1×10 ¹⁹ cm ⁻³ to 1×10 ²¹ cm ⁻³ . Implant N ions with energy. Since the implanted layer has a thickness of about 20 nm, the region into which the N ions are implanted is entirely oxidized to form the gate insulating film 7 in the subsequent step of forming the gate insulating film 7 . With the presence of this injection layer, accelerated oxidation becomes more remarkable, and the gate insulating film 7 on the JFET region 4 can be formed thicker.

Instead of implanting N ions to a depth of about 20 nm from the surface of the drift layer 3 (JFET region 4, low resistance region 20), silicon, oxygen, and fluorine are simultaneously implanted at a concentration of 1×10 ¹⁹ cm ⁻³ to 1×10 cm −3 . About ²¹ cm ⁻³ may be implanted. In this case, since a larger implantation damage layer can be formed in the implantation region of the surface, the gate insulating film 7 on the JFET region 4 can be formed thicker.

By forming the gate insulating film 7 so that the concentration is the highest at the outermost surface of the drift layer 3 (that is, the JFET region 4 and the low resistance region 20), N ions at the interface between the gate insulating film 7 and the JFET region 4 are reduced. The concentration becomes high within the JFET region 4 . In order to reduce the concentration of the JFET region 4, the impurity profile of the depth method of the JFET region 4 may not be uniform, and low resistance is possible if there is a high concentration region even partially.

The subsequent steps are the same as in the first or second embodiment.

<Nitrogen concentration peak position>
As described in the first to third embodiments, before forming the gate insulating film, nitrogen is implanted into the JFET region, and the implanted JFET region is oxidized to form the gate insulating film. Nitrogen is segregated at the interface with the region.

In addition, after forming the gate insulating film, nitriding treatment or the like is performed to segregate nitrogen at the interface between the gate insulating film and the JFET region. In any of these manufacturing methods, forming a nitrogen concentration peak on the side of the gate insulating film near the interface between the gate insulating film and the JFET region is most effective for forming positive fixed charges. The vicinity of the interface between the gate insulating film and the JFET region includes the interface or the gate insulating film side of about 10 nm from the interface.

<Embodiment 4>
In the first to third embodiments, the setting of positive fixed charge by nitrogen at the interface between the gate insulating film and the JFET region has been described. Embodiment 4 describes impurities other than nitrogen.

<Method for Manufacturing Semiconductor Device 103>
A method of manufacturing the semiconductor device 103 according to the fourth embodiment will be described with reference to FIGS. 15 to 19. FIG.

As shown in FIG. 15, an n-type low-resistance silicon carbide substrate 1 is prepared, and an n-type drift layer 3 is formed on the silicon carbide substrate 1 by epitaxial growth. In this embodiment, the drift layer 3 has an n-type impurity concentration of 1×10 ¹³ cm ⁻³ to 1×10 ¹⁸ cm ⁻³ and a thickness of 4 μm to 200 μm.

As shown in FIG. 15, an n-type low-resistance silicon carbide substrate 1 is prepared, and an n-type drift layer 3 is formed on silicon carbide substrate 1 by epitaxial growth. In Embodiment 1, the drift layer 3 has an n-type impurity concentration of 1×10 ¹³ cm ⁻³ to 1×10 ¹⁸ cm ⁻³ and a thickness of 4 μm to 200 μm.

As shown in FIG. 16, p-type well regions 6 spaced apart from each other are formed in the surface layer of the drift layer 3 . Then, an n-type source region 5 is formed in the surface layer of the well region 6 . Specifically, Al ions are implanted to form a p-type well region 6 and N ions are implanted to form an n-type source region 5 using a resist or oxide film processed by photolithography as a mask. do.

Next, as shown in FIG. 17, a gate insulating film 17 is formed. The gate insulating film 17 is formed by dry thermal oxidation at 1150° C. or higher. Note that the gate insulating film 17 may be formed by a deposition method. Cesium (Cs) is ion-implanted into the formed gate insulating film 17 . Annealing is then performed before the step of forming the semiconductor exposed region, and the cesium, which becomes a region containing fixed charges due to thermal diffusion, is redistributed in a region closer to the semiconductor.

After that, using a resist processed by photolithography as a mask, only the gate insulating film 17 on the JFET region 4 is left, and other insulating films are removed. The gate insulating film 17 may be removed by a wet process using hydrofluoric acid or by dry etching.

Next, as shown in FIG. 18, a gate insulating film 18 is formed by dry thermal oxidation at 1150° C. or higher. The gate insulating film 18 is formed by a deposition method at about 700.degree. C. to 900.degree. After forming the gate insulating film 18, heat treatment is performed in a nitrogen or ammonia atmosphere. By performing the step of forming the gate insulating film 18, only the

gate insulating films

17 and 18 on the JFET region 4 are thickened and become insulating films containing cesium. The gate insulating film 17 contains elements different from those of the gate insulating film 18 .

The subsequent steps are the same as in the second embodiment. As shown in FIG. 19, the gate electrode 8 is formed by depositing polysilicon by CVD and etching it using a resist processed by photolithography as a mask. Polysilicon may contain impurities such as phosphorus and boron. By containing impurities in the gate electrode 8, the resistance of the gate electrode 8 can be reduced.

In the above description, the case of implanting cesium as an impurity (element) that becomes a fixed charge into the gate insulating film 17 on the JFET region 4 has been described, but the present invention is not limited to this. Realizing the formation of fixed charges in the gate insulating film 17 by including at least one of barium (Ba), rubidium (Rb), and strontium (Sr) in the gate insulating film 17 on the JFET region 4. can be done.

Since cesium, barium, rubidium, and strontium belong to alkali metals or alkaline earth metals, they have a low first ionization energy and tend to become positively charged ions. In addition, since cesium, barium, rubidium, and strontium have large atomic numbers unlike light elements such as sodium, which easily move even at room temperature, their charges do not move in the normal device operating temperature range. Cesium, barium, rubidium, and strontium are therefore materials that act as positive fixed charges.

In FIG. 17, the case where _the gate _insulating film 17 is silicon oxide has been described. ( _Al2O3 , _Al2O _, etc.), tantalum oxide ( _Ta2O5 ), hafnium oxynitride ( _HfOxNy ₎ _, zirconium oxynitride ₍ ZrOxNy ₎ , aluminum oxynitride ( _AlOxNy ₎ , tantalum oxynitride (TaO _x N _y ), and those having a composite composition of these materials (hafnium oxide aluminate, hafnium oxynitride aluminate, etc.), or those containing elements contained in semiconductor substrates such as silicon ( hafnium oxide silicate, hafnium oxide aluminate silicate) may also be used. Alternatively, a laminated film of silicon oxide and a material having a dielectric constant higher than that of silicon oxide, or a laminated film of silicon oxynitride and a material having a dielectric constant higher than that of silicon oxide may be used. These laminated films may contain cesium, barium, rubidium, or strontium.

In FIG. 18, the case where the gate insulating film 18 is silicon oxide has been described. Tantalum oxynitride, those having a composite composition of these materials (hafnium oxide aluminate, hafnium oxynitride aluminate, etc.), or those containing elements contained in semiconductor substrates such as silicon (hafnium oxide silicate, hafnium aluminum oxide phosphate silicate) may also be used. Furthermore, a laminated film of silicon oxide and a material having a dielectric constant higher than that of silicon oxide, or a laminated film of silicon oxynitride and a material having a dielectric constant higher than that of silicon oxide may be used.

In the case of the laminated film, a silicon oxide film or a silicon oxynitride film is used for the film in contact with the silicon carbide substrate 1 among the laminated films. Since the interface between the gate insulating film 18 and the well region 6 serves as the channel of the MOSFET, it is possible to realize a lower resistance by preventing deterioration of carrier mobility.

In the above description, the structure in which the

gate insulating films

17 and 18 are deposited on the JFET region 4 in two or more steps to be thicker than the gate insulating film 18 on the well region 6 has been described. Since the amount of fixed charge formed in the gate insulating film 17 can be controlled by the dose amount of the element introduced into the gate insulating film 17, if the gate insulating film 17 above the JFET region 4 is dosed with a high concentration element, It can have the same thickness as the gate insulating film 18 on the well region 6 . However, in this case, only the gate insulating film 17 is formed on the JFET region 4 without forming the gate insulating film 18 thereon.

<Evaluation of electrical characteristics of semiconductor device 103>
After forming MOSFETs on silicon carbide substrate 1, a module is formed. After forming the MOSFET, the electrical characteristics of the MOSFET are evaluated in order to judge whether the element (semiconductor device 103) is good or bad. It is then cut (diced) and divided into individual elements (chips). Non-defective devices are used when assembling the power module. A non-defective element is an element that satisfies expected characteristics when the electrical characteristics of the MOSFET are evaluated.

FIG. 20 is a flow chart showing an example of a method for manufacturing a module including the semiconductor device 103 according to the fourth embodiment. Although the method of manufacturing a module including the semiconductor device 103 according to the fourth embodiment will be described here, the method of manufacturing a module including each of the

semiconductor devices

100, 101, and 102 described in the first to third embodiments is the same. be.

In step S<b>101 , MOSFETs are formed on the silicon carbide substrate 1 .

　In step S102, the electrical characteristics of the MOSFET are evaluated.

In step S103, electrical stress is applied to the interface between the gate insulating film 17 of the MOSFET and the JFET region 4 to form fixed charges.

In step S104, the wafer on which a plurality of semiconductor devices 103 are formed is diced to take out one semiconductor device 103 (chip).

In step S105, chips are selected based on the electrical characteristics evaluated in step S102.

In step S106, a power module is assembled using the chips selected in step S105.

A method of applying electrical stress in step S103 will be described. The source electrode 11 and the gate electrode 8 are shorted to 0V. A voltage of 80% of the withstand voltage of the MOSFET is applied to the drain electrode 12 for several seconds to several hours (12th step). The environment in which the voltage is applied may be a room temperature environment or a high temperature environment of about 150.degree.

Under the above voltage conditions, since there is no potential difference between the source electrode 11 and the gate electrode 8, no stress is applied to the gate insulating film 18 in the channel region. On the other hand, electrical stress is applied to the gate insulating film 17 on the JFET region 4 by the drain electric field. This stress can form positive fixed charges 40 only on the JFET region 4 , that is, only on the interface between the gate insulating film 17 and the JFET region 4 . Since the charge amount increases along with the voltage application time, the time and temperature for forming the designed charge amount may be selected. When it is desired to shorten the application time and increase the throughput, the application is performed at a high temperature. Also, the voltage may be applied to a plurality of elements at the same time.

Within the scope of the present disclosure, it is possible to freely combine each embodiment, and to modify or omit each embodiment as appropriate.

Although the present disclosure has been described in detail, the above description is, in all aspects, exemplary and non-limiting. It is understood that a myriad of variations not illustrated may be envisioned.

1 silicon carbide substrate 2 semiconductor layer 3 drift layer 4 JFET region 5 source region 6 well region 7 gate insulating film 8 gate electrode 9 well contact region 11 source electrode 12 drain electrode 13 interlayer insulation film, 15 gate insulating film, 16 gate insulating film, 17 gate insulating film, 18 gate insulating film, 20 low resistance region, 31 contact hole, 32 barrier metal, 40 fixed charge, 41 fixed charge, 100 semiconductor device.

Claims

a first conductivity type silicon carbide substrate;
a first conductivity type drift layer formed on the silicon carbide substrate;
a plurality of well regions of a second conductivity type selectively formed on a surface layer of the drift layer;
a first conductivity type source region selectively formed in a surface layer of each of the well regions;
a low-resistance region that is a surface layer of the drift layer and is formed between the well regions that are adjacent to each other in plan view and has an impurity concentration higher than that of the drift layer;
a gate insulating film formed over the source region, the well regions, and the low resistance region;
a gate electrode formed on the gate insulating film;
with
the gate insulating film includes a first region in contact with each of the well regions and a second region in contact with the low resistance region;
The semiconductor device, wherein the density of positive fixed charges in the second region is higher than the density of positive fixed charges in the first region.
2. The semiconductor device according to claim 1, wherein said low resistance region has a higher impurity concentration as it approaches said gate insulating film in the depth direction.
3. The semiconductor device according to claim 1, wherein said second region of said gate insulating film is thicker than said first region of said gate insulating film.
4. The semiconductor device according to claim 1, wherein said second region of said gate insulating film contains an element different from that of said first region of said gate insulating film.
5. The element according to claim 4, wherein the concentration peak of the element in the second region of the gate insulating film is at the interface between the second region and the low resistance region or at the second region within 10 nm from the interface. semiconductor device.
6. The semiconductor device according to claim 4, wherein said element in said second region of said gate insulating film includes at least one of cesium, barium, strontium, and rubidium.
7. The semiconductor device according to claim 1, wherein said second region of said gate insulating film contains an insulating material different from said first region of said gate insulating film.
The insulating material in the second region of the gate insulating film includes silicon nitride, silicon oxynitride, hafnium oxide, hafnium oxynitride, zirconium oxide, zirconium oxynitride, aluminum oxide, aluminum oxynitride, tantalum oxide, and tantalum oxynitride. 8. The semiconductor device according to claim 7, comprising at least one of
The nitrogen concentration at the interface between the second region of the gate insulating film and the low resistance region is higher than the nitrogen concentration at the interface between the first region of the gate insulating film and each of the well regions. 9. The semiconductor device according to any one of items 1 to 8.
a first step of preparing a silicon carbide substrate of a first conductivity type;
a second step of forming a first conductivity type drift layer on the silicon carbide substrate;
a third step of selectively forming a plurality of well regions of the second conductivity type on the surface layer of the drift layer;
a fourth step of selectively forming a first conductivity type source region in a surface layer of each of the well regions;
a fifth step of forming a low-resistance region having an impurity concentration higher than that of the drift layer between the well regions that are adjacent to each other in plan view and that is a surface layer of the drift layer;
a sixth step of forming a gate insulating film over the source region, each well region, and the low resistance region;
a seventh step of forming a gate electrode on the gate insulating film;
with
the gate insulating film includes a first region in contact with each of the well regions and a second region in contact with the low resistance region;
The method of manufacturing a semiconductor device, wherein the density of positive fixed charges in the second region is higher than the density of positive fixed charges in the first region.
In the fifth step, the low-resistance region is formed by implanting first-conductivity-type impurities a plurality of times with different implantation energies in the surface layer of the drift layer and between the well regions that are adjacent to each other in a plan view. 11. The method of manufacturing a semiconductor device according to claim 10, comprising the step of:
The sixth step is
an eighth step of forming a first gate insulating film only on the low resistance region;
a ninth step of forming a second gate insulating film over the source region, each of the well regions, and the first gate insulating film after the eighth step;
12. The method of manufacturing a semiconductor device according to claim 10, comprising:
13. The method of manufacturing a semiconductor device according to claim 12, wherein the first gate insulating film contains an insulating material different from that of the second gate insulating film.
a tenth step of forming a source electrode on the source region;
an eleventh step of forming a drain electrode on the back surface of the silicon carbide substrate;
a twelfth step of applying a voltage of 0 V or less to the source electrode and the gate electrode and applying a voltage of 80% or more of a predetermined device withstand voltage for 5 seconds or more;
14. The method of manufacturing a semiconductor device according to any one of claims 10 to 13, further comprising:
15. The method of manufacturing a semiconductor device according to claim 14, wherein in said twelfth step, a voltage of 0 V is applied to said source electrode and said gate electrode.