WO2023090197A1 - Wiring board and method for manufacturing same - Google Patents

Abstract

The present invention addresses the problem that, when forming a capacitor electrode by electrolytic plating using a seed layer, if step constriction occurs due to side etching in a step during formation of the seed layer, complete formation of the seed layer may fail, and complete formation of the electrode by electrolytic plating may fail. Thus, the purpose of the present invention is to provide a wiring board in which side etching does not occur in a seed layer.　Accordingly, in the present invention, in a wiring board having an MIM capacitor structure comprising a board (1) having an insulating surface, a first seed layer (3), a first conductive layer (4), a first insulating layer (6), a second seed layer (8), and a second conductive layer (9), a step for patterning the first seed layer by etching comprises performing etching using an etching mask having a width greater than the first conductive layer in at least one direction.

Description

Wiring board and its manufacturing method

The present invention relates to a wiring board and its manufacturing method.

A multilayer wiring board using a glass material as a core board (hereinafter referred to as a "glass circuit board", etc.) is often used as an interposer. In these multilayer wiring substrates, thin film capacitors having an MIM structure (Metal Insulator Metal) in which a dielectric is sandwiched between a lower electrode layer and an upper electrode layer are formed as part of the passive circuit inside the substrate. be.

In Patent Document 1, "a substrate having an insulating surface, a first conductive layer disposed on the substrate, the first portion having a first thickness and a second thickness less than the first thickness. a first conductive layer including a second portion adjacent to the first portion; a first insulating layer spaced from the second portion and disposed on the first portion; and a second conductive layer disposed opposite the first portion.

WO2019/244382

When forming an MIM capacitor on an insulating substrate, first, a first seed layer is provided, and a first conductive layer is provided by plating or the like using the first seed layer, and this is used as a lower electrode of the capacitor. An insulating layer is provided above the lower electrode, and a second conductive layer is further provided above the insulating layer by plating using a second seed layer and the second seed layer to form an upper electrode.
In such a first conductive layer-insulating layer-second conductive layer capacitor, since there is generally a difference in thermal expansion coefficient between the conductive layer and the dielectric layer, stress strain may occur in the capacitor.
Therefore, Patent Document 1 discloses providing a step in the vicinity of the boundary between the first conductive layer and the first insulating layer in order to relieve the stress in the first conductive layer of the MIM.

However, in a capacitor in which a seed layer is used to form a lower electrode and an upper electrode, side etching is likely to occur because the film thickness of the seed layer is thin. If the second seed layer is formed on the side-etched portion by using a technique such as sputtering, there is a high possibility that the second seed layer will be incompletely formed.
SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a wiring substrate and a manufacturing technique for the wiring substrate in which side etching does not occur in the seed layer.

In order to solve the above problems, one typical method for manufacturing a wiring board according to the present invention comprises: a substrate having an insulating surface; a first seed layer disposed on the substrate; a first conductive layer disposed over the first conductive layer; a first insulating layer disposed over the first conductive layer; a second seed layer disposed over the first insulating layer; A wiring board having a second conductive layer disposed above the layer,
Patterning the first seed layer by etching includes etching using an etch mask wider than the first conductive layer in at least one direction.

In order to solve the above problems, one typical wiring board of the present invention is
a substrate having an insulating surface;
In a wiring board including the following layers (1) to (5),
(1) a first seed layer disposed on the substrate; (2) a first conductive layer disposed above the first seed layer; and (3) a first insulating layer disposed above the first conductive layer. (4) a second seed layer disposed above the first insulating layer; (5) a second conductive layer disposed above the second seed layer. consists of
When b is the horizontal width of the first seed layer in the MIM capacitor, which is wider than the first conductive layer of the MIM capacitor, and a is the horizontal width of the first conductive layer,
a and b satisfy the following formula (2).
50 nm≦(b−a)/2≦50 μm (2)

According to the present invention, it is possible to provide a wiring substrate and a method of manufacturing the wiring substrate in which side etching does not occur in the seed layer.
Problems, configurations, and effects other than those described above will be clarified by the description in the following embodiments.

FIG. 1 is a cross-sectional view showing a basic structure to which the present invention is directed. FIG. 2 is a cross-sectional view for explaining the step of forming the first conductive layer. FIG. 3 is a cross-sectional view for explaining the step of forming the first conductive layer. FIG. 4 is a cross-sectional view for explaining the step of forming the first conductive layer. FIG. 5 is a cross-sectional view for explaining the step of forming the first conductive layer. FIG. 6 is a cross-sectional view for explaining side etching in a conventional example. FIG. 7 is a cross-sectional view for explaining the step of forming the second conductive layer in the embodiment. FIG. 8 is a cross-sectional view for explaining the step of forming the second conductive layer in the embodiment. FIG. 9 is a cross-sectional view for explaining the process of forming the MIM structure. FIG. 10 is a cross-sectional view for explaining the etching process of the first seed layer. FIG. 11 is a cross-sectional view illustrating a wiring board on which MIM capacitors are formed. FIG. 12 is a cross-sectional view of a wiring board formed on a multilayer wiring board. 13A and 13B are cross-sectional views for explaining the formation process of the second embodiment. 14A and 14B are cross-sectional views for explaining the formation process of the second embodiment. 15A and 15B are cross-sectional views for explaining the formation process of the second embodiment. 16A and 16B are cross-sectional views for explaining the formation process of the second embodiment. 17A and 17B are cross-sectional views for explaining the formation process of the second embodiment.

A basic structure to which the present invention is applied, a manufacturing method according to a conventional example, a first embodiment, a second embodiment, etc. of the present invention will be described below with reference to the drawings. However, the present invention is not limited by these disclosures. Moreover, in the description of the drawings, the same parts are denoted by the same reference numerals.
When there are a plurality of components having the same or similar functions, they may be described with the same reference numerals and different suffixes. Further, when there is no need to distinguish between these constituent elements, the subscripts may be omitted in the description.
The position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc., in order to facilitate understanding of the invention. As such, the present invention is not necessarily limited to the locations, sizes, shapes, extents, etc., disclosed in the drawings.

In the present disclosure, the term "surface" may refer not only to the surface of the plate-like member, but also to the interface between the layers included in the plate-like member that is substantially parallel to the surface of the plate-like member. In addition, the terms "upper surface" and "lower surface" refer to the upper or lower surface of the drawing when a plate-like member or a layer included in the plate-like member is illustrated. The "upper surface" and "lower surface" may also be referred to as "first surface" and "second surface".

In addition, the “side surface” means a surface of a plate-like member or a layer included in the plate-like member or a portion of the thickness of the layer. Furthermore, a part of a surface and a side surface may be collectively referred to as an "end".
Moreover, "upper" means the vertically upward direction when the plate-like member or layer is placed horizontally. Further, "upward" and "downward" opposite to this are sometimes referred to as "Z-axis positive direction" and "Z-axis negative direction", and horizontal directions are referred to as "X-axis direction" and "Y-axis direction". It is sometimes called "direction".

Further, "planar shape" and "planar view" mean the shape when a surface or layer is viewed from above, that is, from the positive direction to the negative direction of the z-axis. Furthermore, the terms "cross-sectional shape" and "cross-sectional view" mean the shape of a plate-like member or layer cut in a specific direction and viewed from the horizontal direction.
Further, "core" means the core of a face or layer, but not the periphery. The term "central direction" means a direction from the periphery of a surface or layer toward the center of the planar shape of the surface or layer.

[Basic structure]
First, with reference to FIG. 1, the basic structure of a wiring board having MIM capacitors, which is the premise of the manufacturing method of the present invention, will be described.
FIG. 1 shows a substrate 1 having an insulating surface, a first seed layer 3 arranged on the substrate 1, a first conductive layer 4 arranged above the first seed layer 3, and the first conductive layer 4 arranged above the first seed layer 3. a first insulating layer 6 disposed above one conductive layer 4; a second seed layer 8 disposed above said first insulating layer 6; a second seed layer 8 disposed above said second seed layer 8; 2 is a cross-sectional view of a wiring board having a conductive layer 9; FIG.
In the wiring substrate of FIG. 1, the first conductive layer 4 serves as the lower electrode of the MIM, the first insulating layer 6 serves as the dielectric layer of the MIM, the second conductive layer 9 serves as the upper electrode of the MIM, and the substrate 1 configure MIM capacitors at

<Description of each element>
The material, shape, etc. of each element of the MIM capacitor, which is the premise of the manufacturing method of the present invention, will be described below in detail.
(substrate)
The substrate 1 is desirably made of transparent glass having optical transparency. There are no particular restrictions on the composition of the glass or the blending ratio of each component contained in the glass, and the method of manufacturing the glass.
Examples of glass include alkali-free glass, alkali glass, borosilicate glass, quartz glass, sapphire glass, and photosensitive glass, but any glass material containing silicate as a main component may be used.
Furthermore, other so-called glass materials may be used. However, when a semiconductor is mounted on the substrate 1 of the present disclosure and used, it is desirable to use alkali-free glass.
The thickness of the glass substrate is preferably 1 mm or less, but more preferably 0.1 mm or more and 0.8 mm or less in consideration of the ease of the glass through-hole forming process and the handling during manufacturing.

Examples of the method for manufacturing a glass substrate include a float method, a down-draw method, a fusion method, an up-draw method, a roll-out method, and the like. not limited to The coefficient of linear expansion of the glass is preferably -1 ppm/K or more and 15.0 ppm/K or less.
The reason for this is that if the concentration is -1 ppm/K or less, it becomes difficult to select the glass material itself, and it cannot be manufactured at a low cost. On the other hand, when it is 15.0 ppm/K or more, the difference in thermal expansion coefficient from other layers is large, and the reliability is lowered. Moreover, when a silicon chip is mounted on the substrate 1, the connection reliability with the silicon chip is lowered.
The linear expansion coefficient of glass is more preferably 0.5 ppm/K or more and 8.0 ppm/K or less, and still more preferably 1.0 ppm/K or more and 4.0 ppm/K or less.
A functional film such as an antireflection film or an IR cut filter may be formed in advance on the glass substrate. In addition, functions such as strength imparting, antistatic imparting, coloring, and texture control may be imparted. Examples of these functional films include a hard coat film for imparting strength, an antistatic film for imparting antistatic properties, an optical filter film for coloring, and an antiglare and light scattering film for texture control. Not as long. As a method for forming these functional films, deposition techniques such as vapor deposition, sputtering, and wet methods are used.

(First seed layer)
The metal layer forming the first seed layer 3 functions as a power supply layer for electrolytic plating in the formation of wiring in the semi-additive method.
The seed metal layer provided directly above the substrate 1 and on the inner wall of the through hole formed in the substrate 1 is formed by, for example, sputtering or CVD, and includes Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu ₃ N ₄ , Cu alloys alone or in combination are used .
An electroless plating layer (electroless copper plating, electroless nickel plating, etc.) may be formed over the first seed layer 3 of the present disclosure.

(Adhesion layer)
In the embodiments of the present disclosure, prior to forming a seed layer over the substrate 1 and the first insulating layer 6, the upper surface of the substrate 1 and the first insulating layer 6 is subjected to the electrical properties, manufacturability and cost considerations. Considering this, it is desirable to form the adhesion layer 2 from titanium deposited by a sputtering method.
In the capacitor, the lower adhesion layer 5 has the function of improving the adhesion between the first conductive layer, which is the lower electrode, and the dielectric layer, and the upper adhesion layer 7 improves the adhesion between the dielectric layer and the seed metal layer. It has the function of improving The material of the lower adhesion layer and the upper adhesion layer is Ti, for example. In addition, for example, Cu, Ni, Al, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, Cu alloys alone or in combination may be used. Ti is superior in terms of adhesion, electrical conductivity, ease of manufacture, and cost.

It is desirable that the thickness of the lower adhesion layer and the upper adhesion layer is, for example, 10 nm or more and 1 μm or less. If it is less than 10 nm, the adhesion strength may be insufficient. If the thickness exceeds 1 μm, in the manufacturing process to be described later, not only does the film formation take too long to impede mass production, but there is a possibility that the process of removing unnecessary portions will take even more time. The thicknesses of the lower adhesion layer and the upper adhesion layer are more preferably 10 nm or more and 500 nm or less.
Although the thicknesses of the lower adhesion layer and the upper adhesion layer may be different, it is preferable that they have the same thickness in order to simplify the structure. Further, if the adhesion between the lower electrode and the dielectric layer is sufficient, the lower adhesion layer may be omitted. If the adhesion between the dielectric layer and the seed metal layer is sufficient, the upper adhesion layer may be omitted.

(wiring)
The adhesion layer 2, the first seed layer 3, and the first conductive layer 4 formed on the substrate 1 can be used as wiring for circuit formation in regions on the substrate 1 other than where MIM capacitors are formed. . For use as a circuit, the total thickness of the titanium and copper layers is preferably 5 μm or less because it is advantageous for fine wiring formation by the semi-additive method. If the thickness is more than 5 μm, it is difficult to form fine wiring with a pitch of 30 μm or less.
As a method for forming the first conductive layer, electrolytic copper plating is desirable because it is simple and inexpensive and has good electrical conductivity, considering that it is also used as a circuit. However, in addition to electrolytic copper plating, electrolytic nickel plating, electrolytic chrome plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, and the like may be used.

(First insulating layer)
The dielectric layer, which is the first insulating layer 6, should be selected from alumina, silica, silicon nitride, tantalum oxide, titanium oxide, calcium titanate, barium titanate, and strontium titanate from the viewpoint of insulation and dielectric constant. can be done.
The thickness of the dielectric layer is desirably 10 nm or more and 5 μm or less. If the thickness of the dielectric layer is 10 nm or less, the insulating properties cannot be maintained and the function as a capacitor cannot be exhibited. If the thickness of the dielectric layer is 5 μm or more, it takes too much time to form the film, which not only impedes mass production, but also takes more time in the process of removing unnecessary portions. More preferably, it is 50 nm or more and 1 μm or less.

(Second seed layer)
The second seed layer 8 is a power supply layer for forming the upper electrode, which is the second conductive layer of the capacitor, by a semi-additive method. The second seed layer 8 is made of, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, a Cu alloy alone or in combination. can be applied. Copper is desirable because it can be easily removed by etching later.
The thickness of the seed metal layer is desirably 50 nm or more and 5 μm or less. If the thickness of the seed metal layer is less than 50 nm, there is a possibility that poor conduction will occur in the subsequent electroplating process. If the thickness of the seed metal layer exceeds 5 μm, it will take a long time to remove it by etching. The thickness of the seed metal layer is more preferably 100 nm or more and 500 nm or less.

(Second conductive layer)
The upper electrode, which is the second conductive layer 9, is an electrolytic plating layer. Electrolytic copper plating is desirable because it is simple, inexpensive, and has good electrical conductivity. However, in addition to electrolytic copper plating, electrolytic nickel plating, electrolytic chrome plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, and the like may be used.
The thickness of the upper electrode (thickness of electrolytic copper plating) is desirably 3 μm or more and 30 μm or less. If the thickness is less than 3 μm, the circuit may disappear depending on the etching process after the upper electrode is formed. Furthermore, there is a danger that the connection reliability and electrical conductivity of the circuit will be lowered. If the electrolytic copper plating thickness exceeds 30 μm, it is necessary to form a resist layer with a thickness of 30 μm or more, which increases manufacturing costs. Furthermore, since the resist resolution is lowered, it becomes difficult to form fine wiring with a pitch of 30 μm or less. More preferably, it is 5 μm or more and 25 μm or less. More desirably, the thickness is 10 μm or more and 20 μm or less.

[Manufacturing method in conventional example]
Next, with reference to FIGS. 2 to 6, a conventional example of manufacturing a wiring board having an MIM capacitor structured as shown in FIG. 1 will be described.
First, as shown in FIG. 2, an adhesion layer 2 and a first seed layer 3 are formed above a substrate 1 having an insulating surface, and a pattern of a resist 11 is formed thereon.
Next, as shown in FIG. 3, the first conductive layer 4 is formed by electrolytic plating using the first seed layer 3 as a power supply layer.
Next, as shown in FIG. 4, the resist 11 is removed, and as shown in FIG. 5, unnecessary portions of the adhesion layer 2 and the first seed layer 3 are removed using the first conductive layer 4 as an etching mask.
However, when the above-described manufacturing method is adopted, side etching of the adhesion layer 2 and the first seed layer 3 may occur in the region around the end portion of the first conductive layer 4, as indicated by X in FIG. . Since the adhesion layer 2 and the first seed layer 3 are small in film thickness, the speed of etching in the x direction is high, and it is extremely difficult to prevent side etching.

In the manufacturing process of the MIM structure, after forming the first conductive layer 4 as the lower electrode, the first insulating layer 6 as the dielectric layer is formed. After the seed layer 8 is formed, power is supplied to the second seed layer to form the second conductive layer 9 that will serve as the upper electrode.
At this time, when the upper adhesion layer 7 and the second seed layer 8 are formed by a sputtering method, the sputter coating on the side wall of the first conductive layer 4, which is the lower electrode layer, will not adhere to the first conductive layer 4. Much depends on the shape of the end.
Therefore, as shown in FIG. 6, when the adhesion layer 2 and the first seed layer 3 are side-etched, the coverage of the film by sputtering becomes insufficient, and the second seed layer 8 is formed discontinuously. It will happen. As a result, power is not supplied during the formation of the second conductive layer 9 by electroplating, resulting in the problem that the plated film is not formed.

Furthermore, if the adhesion layer 2 and the first seed layer 3 are etched using the first conductive layer 4 as an etching mask as shown in FIG. This will adversely affect the precision and yield of the capacitor. In this respect, according to the embodiments of the present disclosure, the smoothness of the interface between the lower electrode and the dielectric can be maintained, and short-circuiting of capacitors due to surface roughness and variations in capacitance due to variations in electrode surface area can be reduced. Therefore, it is possible to improve the yield of the capacitor and to stably manufacture the capacitor.

[First embodiment]
In order to solve the problems of the conventional manufacturing method as described above, the first embodiment of the present invention adopts the manufacturing method described below.
The first embodiment will be described below with reference to FIGS. 2 to 4 and 7 to 11. FIG.

(Step 1)
Since Steps 1 to 6 in the first embodiment are the same as in the conventional example, they will be explained with reference to FIGS. 2 to 4. FIG.
First, although not shown in FIGS. 2 to 11 and FIGS. 13 to 17, the substrate 1 may have a through hole penetrating from the upper surface of the substrate 1 to the lower surface. The cross-sectional shape and diameter of the through hole may be, for example, a shape in which the diameter of the central portion is narrower than the top diameter and the bottom diameter of the through hole, or a shape in which the bottom diameter is smaller than the top diameter. Further, the shape may be such that the diameter of the central portion is larger than the top and bottom diameters of the through hole.

(Step 2)
Next, as shown in FIG. 2, when the surface of the substrate 1 and through holes are formed, the adhesion layer 2 and the first seed layer 3 are also formed in the through holes. The adhesion layer 2 and the first seed layer 3 act as power supply layers for electroplating in the wiring forming process in the semi-additive method.
The steps of forming the adhesion layer 2 and the first seed layer 3 include forming titanium as the adhesion layer 2 on the substrate 1 by sputtering, then forming a copper layer as the first seed layer 3 by sputtering, and then forming a copper layer. Additionally, an additional metal layer is preferably formed by electroless plating. If the titanium and copper layers are formed only by the sputtering method, it may not be possible to form a uniform metal film on the inner walls of the through holes. For this reason, it is desirable to enhance the metal layer by electroless plating. The electroless plating layer may be electroless copper plating or electroless nickel plating, but electroless nickel plating is preferable because it has good adhesion to the glass, titanium, or copper layer.
If the nickel plating layer is too thick, it may become difficult to form fine wiring. Further, the adhesion may be lowered due to the increase in film stress. Therefore, the electroless nickel plating thickness is preferably 1 μm or less. Moreover, it is more preferably 0.5 μm or less, and still more preferably 0.3 μm or less.
In addition, the electroless nickel plating film may contain phosphorus, which is a co-deposit derived from the reducing agent, and sulfur, lead, bismuth, and the like contained in the electroless nickel plating solution. Through the above steps, a substrate having a seed metal layer formed on a glass substrate having through holes is obtained.

(Step 3)
Subsequently, as shown in FIG. 2, a pattern of resist 11 is formed above the first seed layer. In the pattern forming method using the resist 11, first, a layer of the resist 11 is formed on the entire surface of the first seed layer. A negative dry film resist, a negative liquid resist, and a positive liquid resist can be used as the resist, but the negative photoresist is preferable because the formation of the resist layer is simple and inexpensive.

(Step 4)
Subsequently, a pattern for forming a desired conductor circuit layer is formed on the photoresist layer by a known photolithographic method. That is, the pattern of the resist 11 is aligned so that the portion where the conductor circuit layer is to be formed later is exposed, and patterning is realized by exposure and development. Although the thickness of the resist layer depends on the thickness of the conductive circuit layer, it is preferably 5 μm or more and 25 μm or less. If the thickness is less than 5 μm, the electroplated layer, which will be the conductive circuit layer, cannot be increased to 5 μm or more, and the connection reliability of the circuit may be lowered. If the thickness is more than 25 μm, it becomes difficult to form fine wiring with a pitch of 30 μm or less. Thus, a substrate having a photoresist pattern formed thereon is obtained.

(Step 5)
Subsequently, by supplying power to the first seed layer and immersing it in a plating solution, an electrolytic plating layer, which is a first conductive layer that will later become a conductive circuit layer, is formed on the upper surface of the first seed layer where the photoresist pattern is not formed. to form

(Step 6)
Subsequently, the unnecessary photoresist pattern is removed to expose the first conductive layer and the first seed layer 3 as shown in FIG. Although the method for removing the resist 11 is not limited to any particular method, for example, the resist 11 can be peeled off with an alkaline aqueous solution.

(Step 7)
Subsequently, as shown in FIG. 7, a lower adhesion layer 5, a first insulating layer 6, an upper adhesion layer 7, and a second seed layer 8 are sequentially formed over the entire surface of the lower electrode, which is the first conductive layer 4. Form deposits. Methods for forming the above layers include a vacuum deposition method, a sputtering method, an ion plating method, an MBE method, a laser abrasion method, and a CVD method, but are not limited by this embodiment.
The lower adhesion layer 5 under the first insulating layer 6 has the function of improving the adhesion between the first insulating layer 6 and the first conductive layer 4 . However, if the adhesion between the first insulating layer 6 and the first conductive layer 4 is sufficient, the lower adhesion layer 5 may be omitted.
In this embodiment, after forming the first conductive layer, the first insulating layer and the second seed layer are formed without etching the first seed layer. Therefore, when the second seed layer is formed, it is possible to suppress abnormal throwing power of the second seed layer. As a result, the second conductive layer can also be stably formed.
The second seed layer functions as a power feeding layer for forming the upper electrode of the capacitor by a semi-additive method.

(Step 8)
Subsequently, as shown in FIG. 8, a pattern of resist 11 is formed on the upper surface of the second seed layer 8 in a region other than where the second conductive layer 9 is to be formed. The formation of the pattern of the resist 11 can be performed by the same method as the photoresist pattern described above. In this case, the opening region of the pattern of the resist 11 is formed so as to be inside the first conductive layer 4 (lower electrode). is formed inside the first conductive layer 4 (lower electrode).

(Step 9)
Subsequently, power is supplied to the second seed layer to form the second conductive layer 9 (upper electrode) by electroplating.

(Step 10)
Subsequently, the pattern of the resist 11 is removed. The removal of the photoresist pattern can be carried out by using a known alkaline aqueous solution.

(Step 11)
Subsequently, as shown in FIG. 9, a pattern of resist 11 is formed so as to surround the second conductive layer 9 (upper electrode). The formation of the pattern of the resist 11 can be performed by the same method as the photoresist pattern described above. In this case, the non-opening region of the photoresist pattern is formed so as to be outside the upper electrode and inside the first conductor layer (lower electrode). It is formed so as to be inside the first conductive layer 4 (lower electrode) except for the portion of .
Thus, etching is performed so that the end surfaces of the second seed layer 8, the upper adhesion layer 7, the first insulating layer 6, and the lower adhesion layer 5 are outside the second conductive layer and inside the first conductive layer, respectively, A MIM capacitor structure is formed.

(Step 12)
The removal of unnecessary portions of the second seed layer 8 and the upper adhesion layer 7 is not limited to being performed in this step. 7 may be removed. By doing so, the area of the first insulating layer 6 on the outer surface of the MIM capacitor device is increased, and current leakage from the side surface between the upper electrode and the lower electrode can be suppressed.

(Step 13)
Subsequently, the pattern of the resist 11 is removed. The removal of the photoresist pattern can be carried out by using a known alkaline aqueous solution.

(Step 14)
Subsequently, as shown in FIG. 10, a pattern of resist 11 is again formed so as to surround first conductive layer 4 as well. That is, the pattern of the resist 11 is formed such that the pattern of the resist 11 becomes an etching mask wider than the first conductive layer in at least one width direction (the direction in the xy plane perpendicular to the z-axis).
That is, the width of the etching mask, which is wider than the first conductive layer, corresponds to the width of the first seed layer 3 in the MIM capacitor. In this case, the non-opening region of the photoresist pattern is formed so as to be outside the lower electrode, and even in a plan view in the stacking direction, the first conductive layer 4 is formed except for the portion of the connection line to the outside of the MIM capacitor. (lower electrode).

More specifically, the relationship between the width b in the xy plane (horizontal direction) of the resist 11 in at least one direction and the width a in the xy plane of the first conductive layer (lower electrode) in the same direction is, of course, as follows. Expression (1) is satisfied.
[Number 1]
a<b (1)
Furthermore, it is desirable that a and b satisfy the following formula (2).
[Number 2]
50 nm≦(b−a)/2≦50 μm (2)
In equation (2), "(ba)/2" indicates the width difference between the first conductive layer (lower electrode) 4 and the resist 11 on one side. The reason why the upper limit of the width difference on one side is set to 50 μm is that if it is larger than this, the pattern design is restricted.
Furthermore, it is desirable that the height c of the adhesion layer 2 and the first seed layer 3 in the z-axis direction (total thickness of the two layers) satisfies the following formula (3).
[Number 3]
50 nm≦c≦5 μm (3)
The reason why the lower limit of c is set to 50 nm in Equation (3) is that 50 nm is required as the minimum value for the adhesion layer 2 and the first seed layer 3 to function as power supply layers. The reason why the upper limit of c is set to 5 μm is that the wiring width that can be formed is restricted when the seed layer is etched.
Furthermore, it is desirable that a, b, and c satisfy the following formula (4).
[Number 4]
0.01≦((ba)/2)/c≦1000 (4)
If the shape satisfies the formula (4), side etching does not occur below the first conductive layer (lower electrode), and in subsequent steps, the second seed layer is in a sufficiently stable state without disconnection failure. It is possible to form with
The resist pattern can be formed by the same method as the photoresist pattern described above.

(Step 15)
Subsequently, the exposed portion of the first seed layer is removed.
The electroless Ni layer, the copper layer, and the titanium layer can be removed sequentially by chemical etching. The type of etchant is appropriately selected according to the metal species to be removed, and the removal method is not limited to the methods described in the present disclosure.

(Step 16)
Subsequently, when the pattern of the resist 11 is removed. As shown in FIG. 11, a wiring substrate having MIM capacitors formed thereon can be formed. The removal of the photoresist pattern can be carried out by using a known alkaline aqueous solution. A capacitor is formed by the above steps.

(Step 17)
Thereafter, as shown in FIG. 12, an insulating resin layer 12 and via holes 13 are formed on the wiring board. After that, a multilayer wiring board is formed by repeatedly forming a laminated conductor circuit layer and an insulating resin layer.
Incidentally, the conductor circuit and laminated structure on the wiring substrate can be formed using a known semi-additive method or subtractive method.
Further, it is possible to form the external connection terminals after forming the multilayer wiring board, and furthermore, it is possible to form solder balls on the external connection terminals.
A wiring board according to the present disclosure may have laminated conductor circuit layers, external connection terminals, and solder balls on one side, or may have both sides as a modification. Further, semiconductor chips and chip parts may be mounted.

[Second embodiment]
Next, a second embodiment will be described below with reference to FIGS. 2 to 4 and 13 to 17. FIG.
In the second embodiment, steps 1 to 6 are the same as those in the first embodiment, so descriptions of steps 1 to 6 are omitted.
In the second embodiment, step 6 of the first embodiment shown in FIG. 4 is followed by step 20, described below.

(Step 20)
After step 6 of the first embodiment, as shown in FIG. 13, a pattern of resist 11 is formed so as to surround the first conductive layer. The resist pattern can be formed by the same method as the resist pattern described above. In this case, the non-opening region of the resist pattern is formed so as to be outside the lower electrode, and even in a plan view in the stacking direction, the first conductive layer 4 ( bottom electrode).

In this case, the length b of the resist 11 in the xy plane, the length a of the first conductive layer (lower electrode) in the xy plane in the same direction, and the height of the adhesion layer 2 and the first seed layer 3 in the z-axis direction The desired relationship between thickness (total thickness of the two layers) and c is the same as described in step 14 in the first embodiment.

(Step 21)
Subsequently, the first seed layer 3 and the adhesion layer 2 are removed using the pattern of the resist 11 as an etching mask.
The first seed layer 3 and the adhesion layer 2 can be removed by chemically etching the electroless Ni layer, the copper layer, and the titanium layer sequentially. The type of etchant is appropriately selected depending on the metal species to be removed, and is not limited at all.

(Step 22)
Subsequently, by removing the pattern of the resist 11, the cross section shown in FIG. 14 can be obtained.
In addition, the removal of the resist 11 can be performed by a known method of removing and peeling with an alkaline aqueous solution.

(Step 23)
Subsequently, as shown in FIG. 15, the lower adhesion layer 5, the first insulating layer 6, the upper adhesion layer 5, the first insulating layer 6, and the upper adhesion layer are formed over the entire surface of the lower electrode, which is the first conductive layer 4, in the same manner as in step 7 of the first embodiment. A layer 7 and a second seed layer 8 are sequentially deposited. Methods for forming the above layers include a vacuum deposition method, a sputtering method, an ion plating method, an MBE method, a laser abrasion method, and a CVD method, but are not limited by this embodiment.
The lower adhesion layer 5 under the first insulating layer 6 has the function of improving the adhesion between the first insulating layer 6 and the first conductive layer 4 . However, if the adhesion between the first insulating layer 6 and the first conductive layer 4 is sufficient, the lower adhesion layer 5 may be omitted.
The second seed layer functions as a power feeding layer for forming the upper electrode of the capacitor by a semi-additive method.

(Step 24)
Subsequently, as shown in FIG. 16, a pattern of resist 11 is formed in a region other than where the second conductive layer 9 is to be formed. The formation of the pattern of the resist 11 can be performed by the same method as the photoresist pattern described above. In this case, the opening region of the pattern of the resist 11 is formed so as to be inside the first conductive layer 4 (lower electrode). is formed inside the first conductive layer 4 (lower electrode).

(Step 25)
Subsequently, power is supplied to the second seed layer to form the second conductive layer 9 (upper electrode) by electroplating.

(Step 26)
Subsequently, the pattern of the resist 11 is removed. The removal of the photoresist pattern can be carried out by using a known alkaline aqueous solution.

(Step 27)
Subsequently, as shown in FIG. 17, a pattern of resist 11 is formed so as to surround the second conductive layer 9 (upper electrode). The formation of the pattern of the resist 11 can be performed by the same method as the photoresist pattern described above. In this case, the non-opening region of the photoresist pattern is formed so as to be outside the upper electrode and inside the first conductor layer (lower electrode). It is formed so as to be inside the first conductive layer 4 (lower electrode) except for the portion of . It is desirable to form them so that they are on the outside and inside, respectively.

(Step 28)
Subsequently, as in step 12, unnecessary portions of the second seed layer 8, the upper adhesion layer 7, the first insulating layer 6, and the lower adhesion layer 5 are removed using the pattern of the resist 11 as a mask. The removal of the second seed layer 8, the upper adhesion layer 7, the first insulating layer, and the lower adhesion layer 5 can be carried out using known methods such as chemical etching and dry etching. A different removal method may be employed for each layer, or the same removal method may be applied to all layers.
As described above, the pattern of the resist 11 is formed inside the first conductive layer 4 (lower electrode). It is formed so as to remain only inside one conductive layer (lower electrode).

The unnecessary portions of the second seed layer and the upper adhesion layer 7 may be removed by etching using the second conductive layer 9 (upper electrode) as a mask immediately after the step 27, even if they are not removed in the step 28. Also good. By doing so, the area of the first insulating layer on the outer surface of the MIM capacitor device is increased, and current leakage from the side surface between the upper electrode and the lower electrode can be suppressed.

(Step 29)
Subsequently, when the pattern of the resist 11 is removed. As in the first embodiment, a wiring substrate having MIM capacitors formed thereon can be formed as shown in FIG. The removal of the resist pattern can be carried out by using a known alkaline aqueous solution. A capacitor is formed by the above steps.

The steps after step 29 in the second embodiment are the same as in the first embodiment, so descriptions thereof are omitted.

<effect>
When an MIM capacitor is manufactured by the conventional manufacturing method, side etching occurs below the first conductive layer 4 (lower electrode), and the second conductive layer 9 (upper electrode) is not normally formed at a rate of 50%. %, but if the manufacturing methods according to the first and second embodiments of the present disclosure are employed, the second conductive layer 9 (upper electrode) can be normally formed at a rate of 100%. . A noticeable improvement could be seen.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present invention.

1: substrate, 2: adhesion layer, 3: first seed layer, 4: first conductive layer, 5: lower adhesion layer, 6: first insulating layer, 7: upper adhesion layer, 8: second seed layer, 9 : second conductive layer 11: resist 12: insulating resin layer 13: via hole

Claims (7)

a substrate having an insulating surface;
In a wiring board including the following layers (1) to (5),
(1) a first seed layer disposed on the substrate; (2) a first conductive layer disposed above the first seed layer; and (3) a first insulating layer disposed above the first conductive layer. (4) a second seed layer disposed above the first insulating layer; (5) a second conductive layer disposed above the second seed layer; forming a seed layer;
forming the first conductive layer over the first seed layer;
forming the first insulating layer over the first conductive layer;
forming the second seed layer over the first insulating layer;
patterning the second conductive layer over the second seed layer;
forming an etching mask with a resist pattern on the pattern of the second conductive layer and etching the second seed layer and the first insulating layer;
etching the first seed layer;
A method of manufacturing a wiring board comprising: a substrate having an insulating surface;
In a wiring board including the following layers (1) to (5),
(1) a first seed layer disposed on the substrate; (2) a first conductive layer disposed above the first seed layer; and (3) a first insulating layer disposed above the first conductive layer. (4) a second seed layer disposed above the first insulating layer; (5) a second conductive layer disposed above the second seed layer; forming a seed layer;
forming the first conductive layer over the first seed layer;
etching the first seed layer;
forming the first insulating layer over the first conductive layer;
forming the second seed layer over the first insulating layer;
patterning the second conductive layer over the second seed layer;
forming an etching mask with a resist pattern on the pattern of the second conductive layer and etching the second seed layer and the first insulating layer;
A method of manufacturing a wiring board comprising: In the method for manufacturing a wiring board according to claim 1 or 2,
The layers (1) to (5) form an MIM capacitor,
The step of etching the first seed layer includes etching using an etch mask corresponding to the width of the first seed layer in the MIM capacitor that is wider than the first conductive layer in the MIM capacitor in at least one direction. A method of manufacturing a wiring board performed. In the method for manufacturing a wiring board according to claim 3,
When b is the horizontal width of the first seed layer in the MIM capacitor, which is wider than the first conductive layer of the MIM capacitor, and a is the horizontal width of the first conductive layer,
a and b are a method of manufacturing a wiring board that satisfies the following formula (2).
[Number 2]
50 nm≦(b−a)/2≦50 μm (2) In the method for manufacturing a wiring board according to claim 4,
When the thickness of the first seed layer (the total thickness of the first seed layer and the lower adhesion layer when the lower adhesion layer is provided below the first seed layer) is c, a , b and c satisfy the following formula (4).
[Number 4]
0.01≦((ba)/2)/c≦1000 (4) a substrate having an insulating surface;
In a wiring board including the following layers (1) to (5),
(1) a first seed layer disposed on the substrate; (2) a first conductive layer disposed above the first seed layer; and (3) a first insulating layer disposed above the first conductive layer. (4) a second seed layer disposed above the first insulating layer; (5) a second conductive layer disposed above the second seed layer. consists of
When b is the horizontal width of the first seed layer in the MIM capacitor, which is wider than the first conductive layer of the MIM capacitor, and a is the horizontal width of the first conductive layer,
a and b are wiring boards that satisfy the following formula (2).
[Number 2]
50 nm≦(b−a)/2≦50 μm (2) In the wiring board according to claim 6,
When the thickness of the first seed layer (the total thickness of the first seed layer and the lower adhesion layer when the lower adhesion layer is provided below the first seed layer) is c, a , b and c are wiring substrates satisfying the following formula (4).
[Number 4]
0.01≦((ba)/2)/c≦1000 (4)

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