WO2022262570A1

WO2022262570A1 - Clock management circuit, chip and electronic device

Info

Publication number: WO2022262570A1
Application number: PCT/CN2022/096152
Authority: WO
Inventors: 陈健
Original assignee: 展讯通信（上海）有限公司
Priority date: 2021-06-15
Filing date: 2022-05-31
Publication date: 2022-12-22
Also published as: CN113325918A; CN113325918B

Abstract

A clock management circuit, a chip and an electronic device. The clock management circuit comprises: a first logic circuit (11), a clock source management circuit (12) and a clock demand feedback circuit (13); the first logic circuit (11) is connected to several first circuit modules that need to be driven by a first clock signal, and is adapted to receive clock-dependent signals outputted by the several first circuit modules and generate a first logic result signal on the basis of the clock-dependent signals; the clock source management circuit (12) is connected to the first logic circuit, and is adapted to receive the first logic result signal and generate a corresponding clock source control signal on the basis of the first logic result signal, wherein the clock source control signal is outputted to a corresponding clock source as so to control the clock source to turn on or off; and the clock demand feedback circuit (13) is connected to several second circuit modules that need to be driven by a second clock signal and a clock signal selection terminal, is adapted to receive clock demand signals outputted by the several second circuit modules to generate a clock demand feedback signal, and outputs the clock demand feedback signal to the first logic circuit selected by the clock signal selection terminal.

Description

Clock management circuit, chip and electronic equipment

This application claims priority to a Chinese patent application with application number 202110661902.X and titled "Clock Management Circuit, Chip, and Electronic Device" filed with the China Patent Office on June 15, 2021, the entire contents of which are hereby incorporated by reference In this application.

technical field

The invention relates to the technical field of electronic circuits, in particular to a clock management circuit, a chip and electronic equipment.

Background technique

SoC chips are called system-on-chips, also known as system-on-chips. In the SoC chip, the clock signal provided by the clock source, after being divided by different frequency dividers, reaches each circuit module in the system that needs to be driven by the clock. The transmission path of this clock "energy" is like the nutrients of a big tree flowing from the trunk to each branch, so it is called a clock tree.

In order to ensure the normal operation of the SoC chip, it is necessary to manage the clocks of each module in the system.

Existing clock management is often initiated by software through registers. With the increase of SoC chip scale and the emergence of multiple power domains, there are more and more clock sources, and the clock tree and clock domains are becoming more and more complex. It is difficult to manage the clock in a timely and accurate manner by means of software.

Contents of the invention

The problem to be solved by the invention is: how to manage the clock more timely and accurately.

In order to solve the above problems, an embodiment of the present invention provides a clock management circuit, the clock management circuit includes a first logic circuit, a clock source management circuit and a clock demand feedback circuit; wherein:

The first logic circuit is connected to a plurality of first circuit modules that need to be driven by a first clock signal, and is adapted to receive clock-dependent signals output by the plurality of first circuit modules, and generate a first logic circuit based on the clock-dependent signals. result signal;

The clock source management circuit, connected to the first logic circuit, is adapted to receive the first logic result signal, and generate a corresponding clock source control signal based on the first logic result signal, and the clock source control signal output to a corresponding clock source, so as to control the first clock source to be turned on or off;

The clock demand feedback circuit is connected to a plurality of second circuit modules that need to be driven by a second clock signal and a clock signal selection terminal, and is adapted to receive the clock demand signals output by the plurality of second circuit modules, generate a clock demand feedback signal, and Outputting the clock demand feedback signal to the first logic circuit selected by the clock signal selection end.

An embodiment of the present invention also provides a chip, and the chip includes the above-mentioned clock management circuit.

An embodiment of the present invention also provides an electronic device, which includes the above-mentioned chip.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

Applying the solution of the present invention, the clock of the chip is managed through the clock management circuit composed of the first logic circuit, the clock source management circuit and the clock demand feedback circuit. Compared with managing the clock by software, the solution of the present invention is to manage the clock by hardware way to control the clock. The hardware logic is used to arbitrate and feed back the demand for the clock, so that the clock source can be turned off in time, and the control logic is clear, which can effectively reduce the probability of control errors, and the clock management is more accurate.

Description of drawings

FIG. 1 is a schematic structural diagram of a clock management circuit in an embodiment of the present invention;

Fig. 2 is the specific circuit structure diagram of a kind of clock management circuit in the embodiment of the present invention;

FIG. 3 is a schematic diagram of a specific circuit structure of another clock management circuit in an embodiment of the present invention.

detailed description

In the SoC chip, the clock signal provided by the clock source, after being divided by different frequency dividers, reaches each circuit module in the system that needs to be driven by the clock. The transmission path of this clock "energy" is like the nutrients of a big tree flowing from the trunk to each branch, so it is called a clock tree. The clock tree includes multiple clock domains, and each clock domain corresponds to a clock source, that is, the clock "energy" transfer path of a clock source constitutes a clock domain.

In order to ensure the normal operation of the SoC chip, it is necessary to manage the clocks of each circuit module in the system. However, each circuit module in the system has different requirements on the clock, and the clocks between each circuit module have direct or indirect constraints. Therefore, clock management is the guarantee that the SoC chip can work normally.

Existing clock management is often initiated by software through registers. Specifically, each device used to transfer clock "energy", including frequency dividers, clock sources, and various circuit modules, is provided with a gated clock. The so-called gated clock refers to a clock with an input clock signal and another non-clock signal as a logic output, so as to control the time when the input clock signal works.

At present, the non-clock signal input by each gated clock is triggered by the register, and the software logic used to trigger the register to perform the corresponding operation is very complicated. For example, if a circuit module needs to turn on the clock source, the clock source of the circuit module Each register of the path needs to be checked step by step whether it is turned on, and finally the purpose of turning on the clock source can be achieved.

With the increase of SoC chip scale and the emergence of multiple power domains, there are more and more clock sources, and the clock tree and clock domains are becoming more and more complex. The software logic used to trigger the registers to perform corresponding operations is also more complicated. Triggering the corresponding devices to start working step by step through software logic is not only error-prone, but also time-consuming. As a result, it is difficult to control the clock and turn off the clock source in a timely and accurate manner, and it is also difficult to reduce the power consumption of the SoC chip.

In view of the above problems, an embodiment of the present invention provides a clock management circuit, which controls the clock through hardware. The hardware logic is used to arbitrate and feed back the demand for the clock, and each hardware is connected to each other. As long as a circuit module needs a clock, the clock source can be managed through the connection relationship between the hardware, and there is no need to design complex software logic. The clock source can be turned off in time, and the control logic is clear, which can effectively reduce the probability of control errors, and the clock management is more accurate.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Referring to FIG. 1 , an embodiment of the present invention provides a clock management circuit, which may include: a first logic circuit 11 , a clock source management circuit 12 and a clock demand feedback circuit 13 . in:

The first logic circuit 11 is connected to a plurality of first circuit modules that need to be driven by a first clock signal, and is adapted to receive clock-dependent signals output by the plurality of first circuit modules, and generate a first Logical result signal.

The clock source management circuit 12 is connected to the first logic circuit, adapted to receive the first logic result signal, and generate a corresponding clock source control signal based on the first logic result signal, and the clock source control The signal is output to a corresponding clock source to control the first clock source to be turned on or off.

The clock demand feedback circuit 13 is connected to a plurality of second circuit modules driven by a second clock signal and a clock signal selection terminal, and is adapted to receive clock demand signals output by the plurality of second circuit modules to generate a clock demand feedback signal, and output the clock demand feedback signal to the first logic circuit selected by the clock signal selection end.

For example, in the chip structure shown in FIG. 2 , there are n clock sources, which are respectively clock source PLL1 to clock source PLLn. n>1, and n is an integer. The transmission path of the clock signal generated from the clock source PLL1 to the clock source PLLn constitutes the clock tree of the chip. Wherein, in the clock domain where the clock source PLL1 is located, the first frequency division circuit only includes a first-level first frequency divider Clock1 Divider. In the clock domain where the clock source PLLn is located, the first frequency division circuit only includes a first-level frequency divider Clockn Divider. The second frequency division circuit only includes a second frequency divider Clocks Divider.

The clock signal generated by the clock source PLL1 is divided by the first frequency divider Clock1 Divider to obtain the first clock signal and input to the first circuit module Mod1-1 to the first circuit module Mod1-m. m>1, and m is an integer.

The clock signal generated by the clock source PLLn is divided by the first frequency divider Clockn Divider to obtain the first clock signal and input to the first circuit module Modn-1 to the first circuit module Modn-k. n>k>1, and all k are integers.

The clock signal generated by the clock source PLL1 ~ clock source PLLn, after being selected by the clock selector Clock Selector, is input to the second frequency divider Clocks Divider for frequency division, and then input to the second circuit module ModS-1 to the second circuit module ModS -j. n>S>j, and both S and j are integers.

In a specific implementation, the number of the first logic circuits is not limited, and may be one, or two, or more than two. In the chip shown in FIG. 2 , there are two first logic circuits, which are respectively the

first logic circuits

111 and 112 . Wherein, the first logic circuit 111 is connected to the first circuit module Mod1-1 to the first circuit module Mod1-m, and the first logic circuit 112 is connected to the first circuit module Modn-1 to the first circuit module Modn-k.

It should be noted that the first circuit modules directly connected to the same first logic circuit share the same frequency clock signal on the SoC chip. For example, in FIG. 2, the first circuit module Mod1-1 to the first circuit module Mod1-m share the first clock signal with frequency f1, and the first circuit module Modn-1 to the first circuit module Modn-k, A first clock signal with frequency f2 is shared.

In an SoC chip, circuit modules that share a clock signal of the same frequency are usually generated by the same frequency division circuit. For example, in FIG. 2, the first clock signal shared by the first circuit module Mod1-1 to the first circuit module Mod1-m is generated by the first frequency divider Clockn Divider, and the first circuit module Modn-1 to the second The first clock signal shared by the circuit module Modn-k is generated by the first frequency divider Clockn Divider.

In a specific implementation, the clock dependent signal is generally used to indicate whether the first circuit module needs the first clock signal, that is, whether to turn on or turn off the clock source. Specifically, it may be represented by a logic value. For example, when the logic value of the clock-dependent signal is "1", it means that the clock source is turned on, and when the logic value is "0", it means that the clock source is turned off. Alternatively, when the logic value of the clock dependent signal is "0", it means that the clock source is turned on, and when the logic value is "1", it means that the clock source is turned off.

In an embodiment of the present invention, referring to FIG. 1, the first logic circuit 11 may include: a first logic subcircuit and a second logic subcircuit; wherein:

The first logic sub-circuit is connected to a plurality of first circuit modules driven by a first clock signal, and is adapted to receive clock-dependent signals output by the plurality of first circuit modules, and output clock-dependent signals based on the clock-dependent signals. a result signal, the clock-dependent result signal being input to the second logic sub-circuit and a first divider circuit that generates the first clock signal;

The second logic subcircuit is connected to the first clock management enable signal output end and the clock demand feedback circuit, and is adapted to be based on the first clock management enable signal output from the first clock management enable signal output end , a clock dependent result signal and a clock demand feedback signal output by the clock demand feedback circuit to generate the first logic result signal.

In a specific implementation, each second logic subcircuit can be set to correspond to a first clock management enabling signal output terminal, and the first clock management enabling signal output terminal controls the second logic subcircuit to enter the clock management mode . Of course, multiple second logic subcircuits can also be set to correspond to a first clock management enabling signal output terminal, and the multiple second logic subcircuits are simultaneously controlled by the first clock management enabling signal output terminal to enter clock management. model.

In a specific implementation, the output end of the first clock management enabling signal may be implemented by a register. This register can be read and written under the control of the register controller.

Referring to FIG. 2 , the first logic circuit 111 may include a first logic sub-circuit 111 a and a second logic sub-circuit 111 b. Wherein, the first logic sub-circuit 111a is connected with the first circuit module Mod1-1 to the first circuit module Mod1-m. The second logic subcircuit 111b is connected to the first clock management enable signal output end of the first logic subcircuit 111a.

The first logic circuit 112 may include a first logic sub-circuit 112a and a second logic sub-circuit 112b. Wherein, the first logic sub-circuit 112a is connected to the first circuit module Modn-1 to the first circuit module Modn-k. The second logic subcircuit 112b is connected to the first clock management enable signal output terminal of the first logic subcircuit 112a.

The first logic subcircuit performs a logic operation on the logic value of the clock-dependent signal received as input to obtain a clock-dependent result signal. The clock-dependent result signal, on the one hand, is input to the first frequency division circuit to trigger the first frequency division circuit to perform frequency division work, and on the other hand, is input to the second logic sub-circuit. The second logic sub-circuit performs logic operations on the first clock management enable signal, the clock dependence result signal and the clock demand feedback signal output by the clock demand feedback circuit to generate the first logic result signal.

Referring to FIG. 2 , the output end of the first clock management enabling signal corresponding to the second logic subcircuit 111 b is a register Force1Reg. The output end of the first clock management enabling signal corresponding to the second logic sub-circuit 112b is the register Forcen Reg. When the clocks of the first circuit module Mod1-1 to the first circuit module Mod1-m need to be managed, the register Force1Reg can be controlled to output a logic signal.

Similarly, when the clocks of the first circuit modules Modn-1 to Modn-k need to be managed, the register Forcen Reg can be controlled to output logic signals.

When the register Force1Reg and the register Forcen Reg need to perform clock management, the level value of the logic signal output is the same as the logic value of the clock-dependent signal indicating that the clock source is turned on.

In a specific implementation, referring to FIG. 1 , the number of the clock source management circuit 12 may be one or multiple, which is not specifically limited. The clock source management circuit 12 can not only be used to turn on or turn off the corresponding clock source, but also can manage the frequency of the clock signal generated by the clock source. Each clock source management circuit 12 may only manage one clock source, or may manage multiple clock sources.

In a specific implementation, the clock source of the SoC chip may be located inside the chip or outside the chip, which is not specifically limited. The clock source can be realized by devices such as digital phase-locked loop (DPLL), analog phase-locked loop (APLL), RC oscillator (RC-oscillator, RCO) or crystal oscillator (Crystal oscillator).

For example, in FIG. 2, the clock source PLL1 to the clock source PLLn are implemented by a phase-locked loop. Each clock source uniquely corresponds to a clock source management circuit. Specifically, the clock source PLL1 is controlled by the clock source management circuit 121, and the clock source PLLn is controlled by the clock source management circuit 12n.

In specific implementation, referring to FIG. 1 , the clock demand feedback circuit 13 may include: a third logic subcircuit 131 and a clock demand feedback subcircuit 132; wherein:

The third logic sub-circuit 131 is connected to several second circuit modules that need to be driven by a second clock signal, and is adapted to receive clock demand signals output by the several second circuit modules, and generate a clock demand based on the clock demand signals Feedback signal, the clock demand feedback signal is output to the second frequency division circuit corresponding to the clock demand signal and the clock demand feedback sub-circuit;

The clock demand feedback sub-circuit 132 is connected to the third logic sub-circuit and the clock signal selection terminal, and is adapted to output the clock demand feedback signal to the first logic circuit selected by the clock signal selection terminal;

The clock signal selection terminal is also connected to a clock selector to control the clock selector to select a clock signal output by a clock source corresponding to the clock selection signal to the second circuit module.

2, the third logic sub-circuit 131 is connected to the second circuit module ModS-1 to the second circuit module ModS-j, and receives the clock demand signal generated by the second circuit module ModS-1 to the second circuit module ModS-j, And performing a logic operation on the logic value of the clock demand signal to obtain a clock demand feedback signal.

In a specific implementation, the clock signal selection end may be implemented by a second register. For example, in FIG. 2, the clock signal selection terminal can be realized by the second register SelReg. The second register Sel Reg is read and written under the control of the second register controller. Specifically, the second register controller can control the second register SelReg to output the clock selection signal Sel.

The clock selection signal Sel may carry indication information of the selected clock source, and is used to indicate the clock sources required by the second circuit module ModS-1 to the second circuit module ModS-j. The clock selection signal Sel is input to the clock demand feedback sub-circuit 132 on the one hand, and input to the Clock Selector on the other hand.

Assuming that the clock source selected by the clock selection signal Sel is the clock source PLL1, after receiving the clock selection signal Sel, the clock demand feedback subcircuit 132 can output the clock demand feedback signal to the first clock source selected by the clock selection signal Sel. The second logic sub-circuit 111b, thereby enabling the second logic sub-circuit 111b to generate a clock source control signal for controlling the clock source PLL1 to be turned on, thereby turning on the clock source PLL1. After the clock source PLL1 is turned on, the clock signal generated by the clock source PLL1 is input to the clock selector Clock Selector, and under the control of the clock selection signal Sel, the clock signal generated by the clock source PLL1 is output to the second frequency division circuit corresponding to the clock selection signal Sel Clocks Divider performs frequency division, and then input to the second circuit module ModS-1 to the second circuit module ModS-j.

In a specific implementation, the first circuit module is usually provided with a clock signal by a fixed clock source. The second circuit module is usually provided with a clock signal by a variable clock source. That is to say, the clock signal required by the first circuit module in practical application is fixed, while the clock signal required by the second circuit module is variable.

In the embodiment of the present invention, in order to meet the clock switching requirement of the second circuit module, the clock requirement feedback sub-circuit 132 provides the second circuit module with a clock signal generated by a corresponding clock source according to the clock requirement of the second circuit module.

In FIG. 2 , the second circuit module ModS-1 to the second circuit module ModS-j have the same clock requirements, that is, all required clock signals are the same frequency.

It can be understood that, in practical applications, the second circuit module ModS-1 to the second circuit module ModS-j may also have different clock requirements. Second circuit modules with the same clock requirements are connected to the same second frequency dividing circuit. At this time, the clock demand feedback sub-circuit 132 can be connected to a plurality of second logic sub-circuits at the same time, so as to feed back clock signals for the second circuit modules with different clock demands at the same time, so that the second circuit modules with different clock demands can receive clock signals at the same time. Signal.

Correspondingly, the second frequency divider Clocks Divider is composed of a plurality of second frequency dividers. When the second circuit module ModS-1 to the second circuit module ModS-j have different clock requirements, in the clock selection signal Sel output by the second register Sel Reg, in addition to carrying the indication information of the selected clock source, it can also be Carry the indication information of the second circuit module or the second frequency divider corresponding to the selected different clock sources, thereby enabling the clock selector Clock Selector to provide accurate clock signals for the second circuit modules with different clock requirements.

It should be noted that the clock selection signal Sel determines which second logic subcircuit the clock demand feedback subcircuit 132 feeds back the clock demand feedback signal to, and the second logic subcircuit that has not received the clock demand feedback signal indicates that the second circuit module A clock signal generated by a corresponding clock source is not required.

In specific implementation, referring to FIG. 1, there may be various specific circuit structures of the first logic sub-circuit and the second logic sub-circuit, as long as any first circuit module in the managed first circuit modules needs to turn on or turn off the clock source, it is enough that the first logic circuit can output the first logic result signal sought, so that the corresponding clock source can be controlled to be turned on or off.

In a specific implementation, the meanings expressed by the clock-dependent signals at different logical values may be related. The specific circuit structure of the third logic sub-circuit 131 may be related to the meanings represented by the clock demand signal under different logic values.

In an embodiment of the present invention, when the clock dependent signal indicates that the clock source is turned on at a logic "1", the first logic sub-circuit and the second logic sub-circuit may both be composed of an OR gate circuit. At this time, as long as any first circuit module connected to the first logic circuit needs to turn on the clock source, the logic value of the clock dependent result signal is logic "1".

Referring to FIG. 2 , the clock-dependent signal output by the first circuit module Mod1-1 to the first circuit module Mod1-m is at a high level, and indicates that the clock source is turned on, then the clock-dependent result signal output by the first logic sub-circuit 111a is also Correspondingly, the output end of the first clock management enable signal can also output a logic high level signal. At this time, regardless of whether the clock demand feedback sub-circuit 132 outputs the clock demand feedback signal, the second logic result signal output by the second logic sub-circuit 111b is at a high level, so that the clock source management circuit 121 recognizes the second logic result signal After that, the clock source PLL1 can be controlled to turn on.

In another embodiment of the present invention, when the clock dependent signal is at a logic "1" indicating that the clock source is turned off, the first logic sub-circuit and the second logic sub-circuit may both be composed of an AND gate circuit. At this time, as long as any first circuit module connected to the first logic circuit needs to turn on the clock source, the logic value of the clock dependent result signal is logic "1".

Referring to FIG. 2 , the clock-dependent signal output by the first circuit module Mod1-1 to the first circuit module Mod1-m is low level, and indicates that the clock source is turned on, then the clock-dependent result signal that the first logic sub-circuit 111a can output is also is low level. When the output terminal of the first clock management enable signal outputs a logic low level signal, the second logic result signal output by the second logic sub-circuit 111b can be low regardless of whether the clock demand feedback sub-circuit 132 outputs the clock demand feedback signal. In this way, after the clock source management circuit 121 recognizes the second logic result signal, it controls the clock source PLL1 to turn on.

In an embodiment of the present invention, when the logic "1" of the clock demand signal indicates that a clock signal is required, the third logic sub-circuit is composed of an OR gate circuit. Correspondingly, the second logic sub-circuit is also composed of an OR gate circuit. At this time, the clock demand feedback signal is a high-level signal, which is input to the corresponding second logic sub-circuit after passing through the clock demand feedback sub-circuit 132, and the second logic sub-circuit outputs a high-level signal, so that the corresponding clock source is turned on .

In another embodiment of the present invention, when the logic "0" of the clock demand signal indicates that a clock signal is required, the third logic sub-circuit is composed of an AND gate circuit. Correspondingly, the second logic subcircuit is also composed of an AND gate circuit. At this time, the clock demand feedback signal is a low-level signal, which is input to the corresponding second logic sub-circuit after passing through the clock demand feedback sub-circuit 132, and the second logic sub-circuit outputs a low-level signal, so that the corresponding clock source is turned on .

It should be noted that, the specific circuit structure of the first logic subcircuit, the second logic subcircuit and the third logic subcircuit is not limited to the description in the above embodiment, as long as the output of the circuit module can be used to manage the clock source It is enough for the circuit to output the correct signal representing the demand of the circuit module.

In the embodiment shown in Fig. 2, the first frequency division circuit only comprises the first frequency divider of one stage, i.e. the first frequency divider Clock1 Divider and the first frequency divider Clockn Divider, and the second frequency division circuit also only comprises One-stage second frequency divider Clocks Divider.

However, in practical applications, the first frequency division circuit may include more than two first frequency dividers connected in cascade, and the second frequency division circuit may also include more than two second frequency dividers connected in cascade.

For example, referring to FIG. 3 , in the clock domain where the clock source PLL1 is located, the first circuit module Modj-1 to the first circuit module Modj-k are connected to the clock source PLL1 through a two-stage first frequency divider. Described secondary first frequency divider comprises: first frequency divider Clock1 Divider and first frequency divider Clockj Divider. The first frequency divider Clockj Divider and the first frequency divider Clock1 Divider are cascaded with each other.

For example, the frequency of the clock signal generated by the clock source is 128MHZ, and the frequency of the clock signal becomes 64MHZ through the first frequency divider Clockl Divider. After passing through the first frequency divider Clockj Divider, the first clock signal is obtained. At this time, the frequency of the first clock signal is 32MHZ.

When the first frequency dividing circuit includes more than two cascaded first frequency dividers, the first logic sub-circuit includes more than two cascaded first gate circuits, and the first gate circuit and the first The dividers are connected in one-to-one correspondence.

For example, referring to FIG. 3, when the first frequency division circuit includes two first frequency dividers, the first logic sub-circuit includes two first gate circuits, which are first gate circuit M1 and first gate circuit M1 respectively. Circuit M2. The clock-dependent signals generated by the first circuit module Modj-1 to the first circuit module Modj-k are input to the first gate circuit M2 after logic operation is performed by the first gate circuit M1. The second gate circuit M2 performs logic operations on the output signal of the first gate circuit M1 and the clock-dependent signal output by the first circuit module directly connected to it (such as the first circuit module Mod1-m) to obtain a clock-dependent result signal.

It can be understood that when any first circuit module connected to the first frequency division circuit needs to turn on or off the clock source, the clock source management circuit can respond quickly and in time.

In a specific implementation, the second frequency division circuit may also include more than two second frequency dividers cascaded. Correspondingly, the third logic sub-circuit may include more than two cascaded second gate circuits, and the second gate circuits are connected to the second frequency divider in a one-to-one correspondence. Specifically, it can be set with reference to the connection relationship when the first frequency division circuit and the first logic sub-circuit are both in two stages in FIG. 3 , and details will not be described here.

It should be noted that both FIG. 2 and FIG. 3 are only a simplified schematic diagram of the chip. In practice, the hierarchical structure of the clock tree and the dependencies of each clock domain are much more complicated. However, it can be understood that regardless of the hierarchical structure of the clock tree and the dependencies of each clock domain, the solution of the present invention can be used to manage clocks.

In the solution of the present invention, clock management is realized by automatically transmitting system clock requirements through a clock tree reversed by hardware. This hardware clock control scheme only requires each circuit module to manage whether it needs to work. If you don't need it, you can turn off the clock requirement of this module. By going against the clock tree and synthesizing and transmitting the demand for the upper-level clock until the source of the clock, the clock can be controlled accurately and in time, the logic is clear (no error), and the dynamic power consumption of the system can be better reduced. The power consumption of the clock source itself. Moreover, compared with completely using software to manage the clock, the complexity is reduced, thereby simplifying the structure of the entire chip.

An embodiment of the present invention also provides an electronic device, and the electronic device may include the above-mentioned chip.

With regard to the chips and electronic devices described in the above-mentioned embodiments, each module/unit contained therein may be realized by means of hardware such as circuits, or at least some modules/units may be realized by means of software programs, and the software programs run on the chip. For the internally integrated processor, the remaining (if any) modules/units can be implemented by means of hardware such as circuits; for each device or product applied to or integrated in a chip module, each module/unit contained in it can be implemented using a circuit The different modules/units can be located in the same component (such as chips, circuit modules, etc.) or different components of the chip module, or at least some modules/units can be implemented in the form of software programs. Running on the processor integrated in the chip module, the remaining (if any) modules/units can be realized by hardware such as circuits; They are all realized by means of hardware such as circuits, and different modules/units can be located in the same component (such as a chip, circuit module, etc.) or in different components in the terminal, or at least some modules/units can be implemented by means of software programs. The software program runs on the processor integrated in the terminal, and the remaining (if any) modules/units can be realized by means of hardware such as circuits.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims

A clock management circuit, characterized by comprising: a first logic circuit, a clock source management circuit, and a clock demand feedback circuit; wherein:

The first logic circuit is connected to a plurality of first circuit modules that need to be driven by a first clock signal, and is adapted to receive clock-dependent signals output by the plurality of first circuit modules, and generate a first logic circuit based on the clock-dependent signals. result signal;

The clock source management circuit, connected to the first logic circuit, is adapted to receive the first logic result signal, and generate a corresponding clock source control signal based on the first logic result signal, and the clock source control signal output to a corresponding clock source, so as to control the first clock source to be turned on or off;

The clock demand feedback circuit is connected to a plurality of second circuit modules that need to be driven by a second clock signal and a clock signal selection terminal, and is adapted to receive the clock demand signals output by the plurality of second circuit modules, generate a clock demand feedback signal, and Outputting the clock demand feedback signal to the first logic circuit selected by the clock signal selection end.
The clock management circuit according to claim 1, wherein the first logic circuit comprises: a first logic subcircuit and a second logic subcircuit; wherein:

The first logic sub-circuit is connected to several first circuit modules that need to be driven by a first clock signal, and is adapted to receive clock-dependent signals output by the several first circuit modules, and output clock-dependent signals based on the clock-dependent signals. a result signal, the clock-dependent result signal being input to the second logic sub-circuit and a first divider circuit that generates the first clock signal;

The second logic subcircuit is connected to the first clock management enable signal output end and the clock demand feedback circuit, and is adapted to be based on the first clock management enable signal output from the first clock management enable signal output end , a clock dependent result signal and a clock demand feedback signal output by the clock demand feedback circuit to generate the first logic result signal.
The clock management circuit according to claim 2, wherein when the clock dependent signal is logic “1” indicating that the clock source is turned on, the first logic sub-circuit and the second logic sub-circuit are both composed of an OR gate circuit Composition; when the clock dependent signal is at a logic “1” indicating that the clock source is turned off, the first logic sub-circuit and the second logic sub-circuit are both composed of an AND gate circuit.
The clock management circuit according to claim 2, wherein the first frequency dividing circuit comprises more than two cascaded first frequency dividers, and the first logic sub-circuit comprises more than two cascaded first frequency dividers. A gate circuit, the first gate circuit is connected to the first frequency divider in a one-to-one correspondence.
The clock management circuit according to claim 1, wherein the output terminal of the first clock management enabling signal is a first register.
The clock management circuit according to claim 1, wherein the clock demand feedback circuit comprises: a third logic subcircuit and a clock demand feedback subcircuit; wherein:

The third logic sub-circuit is connected to a plurality of second circuit modules that need to be driven by a second clock signal, and is adapted to receive clock demand signals output by the plurality of second circuit modules, and generate clock demand feedback based on the clock demand signals signal, the clock demand feedback signal is output to the second frequency division circuit corresponding to the clock demand signal and the clock demand feedback subcircuit;

The clock demand feedback subcircuit is connected to the third logic subcircuit and a clock signal selection terminal, and is adapted to output the clock demand feedback signal to the first logic circuit selected by the clock signal selection terminal;

The clock signal selection end is also connected to a clock selector to control the clock selector to select a clock signal consistent with the clock signal selection end to the second circuit module.
The clock management circuit according to claim 6, characterized in that, when the clock demand signal indicates that a clock signal is needed at a logic "1", the third logic sub-circuit is composed of an OR gate circuit; when the clock demand signal When the signal logic "0" indicates that a clock signal is needed, the third logic sub-circuit is composed of an AND gate circuit.
The clock management circuit according to claim 6, wherein the second frequency dividing circuit comprises more than two second frequency dividers cascaded, and the third logic sub-circuit comprises more than two cascaded first frequency dividers. Two gate circuits, the second gate circuit is connected to the second frequency divider in a one-to-one correspondence.
The clock management circuit according to claim 1, wherein the clock signal selection terminal is a second register.
A chip comprising the clock management circuit according to any one of claims 1-9.
An electronic device, comprising the chip described in claim 10.