WO2022135009A1 - Storage computing array and data reading/writing computing method - Google Patents

Abstract

A storage computing array, comprising: a plurality of storage computing units connected with each other in an array structure, wherein each storage computing unit comprises a gating switch, and N resistive memories which are connected in series with one another and connected with the gating switch in series or in parallel; wherein the one or more resistive memories each are connected to a bi-directional selector. Hence, in the storage computing array, as N resistive memories connected in series with one another are connected to one gating switch in the storage computing unit, more storage computing units can be provided at the same area overhead. Moreover, in the storage computing array, N resistive memories connected in series with one another are provided in each storage computing unit, and therefore the amount of data stored in each storage computing unit can be significantly improved by such arrangement, and the storage efficiency of the storage computing array is thereby improved.

Description

A storage computing array and a data reading and writing computing method

This application claims the priority of the Chinese patent application filed on December 24, 2020, with the application number of 202011552408.1 and the invention titled "A storage computing array and a data reading and writing computing method", the entire contents of which are approved by Reference is incorporated in this application.

technical field

The invention relates to the technical field of integrated circuits, in particular to a storage computing array and a data reading and writing computing method.

Background technique

In the prior art, a storage computing array is generally composed of storage computing units, wherein the storage computing unit is usually composed of a 1T1R storage structure and a logic computing module. In the 1T1R storage structure, a gate switch and an Resistive memory in series. Since the data storage capacity of the storage-computation array is determined by the number of resistive memories in the storage-computation array, the storage-computation array under this configuration has the technical defect of low storage efficiency. At present, there is no more effective solution to the above problems.

It can be seen that how to improve the storage efficiency of the storage computing array is a technical problem to be solved urgently by those skilled in the art.

SUMMARY OF THE INVENTION

In view of this, the purpose of the present invention is to provide a storage computing array and a data read/write computing method, so as to improve the storage efficiency of the storage computing array. Its specific plan is as follows:

A storage computing array including:

A plurality of storage and calculation units connected to each other in an array structure, each of the storage and calculation units includes a gate switch, and N resistive memories connected in series or in parallel with the gate switch; wherein one or more Resistive memories are each connected with a bidirectional selector, N≥1.

Preferably, the N resistive memories connected in series have the same structure but different physical sizes.

Preferably, it also includes:

A metal thin film bidirectional selector or diode connected in parallel with the resistive memory; wherein, the turn-on voltage of the metal thin film bidirectional selector is greater than or equal to the write voltage of the resistive memory connected in parallel with the metal thin film bidirectional selector, and less than The breakdown voltage of the resistive memory; or the turn-on voltage of the diode is greater than or equal to the write voltage of the resistive memory in parallel with the diode, and less than the breakdown voltage of the resistive memory.

Preferably, the gate switch is specifically an NMOS transistor or a PMOS transistor or a transmission gate.

Preferably, the resistive memory is specifically a magnetoresistive memory or a ferroelectric memory or a phase change memory or a resistive memory.

Preferably, it also includes:

An enabling switch used to jointly control the storage and computing units connected in rows or columns in the array structure.

Correspondingly, the present invention also discloses a data read and write calculation method, which is applied to the storage and calculation array as disclosed above, including:

When the first data stored in the storage and calculation array is to be read, the resistive memory in the target storage and calculation unit is divided into a plurality of resistance intervals, and a corresponding target preset voltage is set for each resistance interval. The target storage and calculation unit is loaded with a first current, respectively reads the target voltage corresponding to each resistance interval, and sequentially compares the target voltage with the target preset voltage according to the order of the resistance interval to obtain a target comparison result , to read the first data through the target comparison result;

When the second data is to be written into the storage and calculation array, the target data to be written in the target storage and calculation unit is determined according to the second data, and is determined according to the resistance value of the target storage and calculation unit Applying the sequence of different currents on the target storage and calculation unit to obtain a target current sequence, so as to write the target data in the target storage and calculation unit through the target current sequence;

When the storage calculation array is to be calculated, the target electrical signal and the target storage data corresponding to the target storage calculation unit are determined, and the target electrical signal and the target storage data are multiplied to obtain the target electrical signal and the target storage data. The calculation value of the target storage calculation unit is added, and the calculation value of all storage calculation units in the storage calculation array is added to obtain the calculation value of the storage calculation array.

Preferably, the resistive memory in the target storage and calculation unit is divided into a plurality of resistance intervals, and a corresponding target preset voltage is set for each resistance interval, and a first current is loaded on the target storage and calculation unit, respectively. Read the target voltage corresponding to each resistance interval, compare the target voltage with the target preset voltage in turn according to the order of the resistance interval, and obtain a target comparison result, so as to read the first voltage through the target comparison result. A data process, including:

Obtain the total resistance of N mutually connected resistive memories in the target storage and calculation unit in the storage and calculation array;

Divide N resistive memories connected in series into 2 ^N resistance intervals according to the total resistance, and set a corresponding preset voltage for each resistance interval to obtain a first preset voltage sequence;

Loading the first current on the target storage and computing unit, and reading the corresponding voltages of 2 ^N resistance intervals respectively, to obtain a first voltage sequence;

Comparing the first preset voltage sequence with the first voltage sequence in sequence according to the sequence corresponding to the 2 ^N resistance intervals, to obtain a first comparison sequence;

The first target sub-data stored in the target storage computing unit is read according to the first comparison sequence, and the first data stored in the storage computing array is read according to the first target sub-data.

Preferably, the resistive memory in the target storage and calculation unit is divided into a plurality of resistance intervals, and a corresponding target preset voltage is set for each resistance interval, and a first current is loaded on the target storage and calculation unit, respectively. Read the target voltage corresponding to each resistance interval, compare the target voltage with the target preset voltage in turn according to the order of the resistance interval, and obtain a target comparison result, so as to read the first voltage through the target comparison result. A data process, including:

Obtain the total resistance of N mutually connected resistive memories in the target storage and calculation unit in the storage and calculation array;

Divide N resistive memories connected in series into 2 ^N-1 resistance intervals according to the total resistance, and set a corresponding preset voltage for each resistance interval to obtain a second preset voltage sequence;

Loading the first current on the target storage and computing unit, and respectively reading the voltages corresponding to 2 ^N-1 resistance intervals to obtain a second voltage sequence;

Comparing the second preset voltage sequence with the second voltage sequence in sequence according to the sequence corresponding to the ^2N-1 resistance intervals, to obtain a second comparison sequence;

The second target sub-data stored in the target storage computing unit is read according to the second comparison sequence, and the first data stored in the storage computing array is read according to the second target sub-data.

It can be seen that in the storage computing array provided by the present invention, N resistive memories connected in series are connected to a gate switch in the storage computing unit. Therefore, compared with the prior art, through this The setting method can set a larger number of storage computing units under the same area overhead. In addition, since in the storage and calculation array, N resistive memories connected in series are set in each storage and calculation unit, the data storage capacity of each storage and calculation unit can be significantly increased by this setting method, and the Thereby, the storage efficiency of the storage computing array is improved.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to the provided drawings without creative work.

FIG. 1 is a schematic structural diagram of a series connection between a gate switch and N mutually series-connected resistive memories in a storage computing unit provided by an embodiment of the present invention;

2 is a schematic structural diagram of a parallel connection between a gating switch and N resistive memories in series in a storage computing unit provided by an embodiment of the present invention;

3 is a schematic structural diagram of a diode connected in parallel on each resistive memory in the storage and computation array shown in FIG. 1 according to an embodiment of the present invention;

4 is a schematic structural diagram of a diode connected in parallel on each resistive memory in the storage and calculation array shown in FIG. 2 according to an embodiment of the present invention;

5 is a schematic structural diagram when a gate switch in a target storage computing unit is connected in series with N series resistive memories, and an enable switch controls the storage computing units connected in columns in the storage computing array;

Fig. 6 is when the gating switch in the target storage calculation unit is connected in parallel with N series resistive memories, the structural representation when the enable switch controls the storage calculation unit connected with the column in the storage calculation array;

FIG. 7 is a flowchart of a data read/write calculation method provided by an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

The embodiment of the present invention discloses a storage computing array, the storage computing array includes: a plurality of storage computing units connected with each other in an array structure, each storage computing unit includes a gate switch, and N connected in series or in parallel with the gate switch Resistive memories connected in series with each other; wherein, one or more resistive memories are each connected with a bidirectional selector, N≥1.

In this embodiment, a new type of storage computing array is provided, by which the storage efficiency of the storage computing array can be significantly improved. Specifically, in the storage computing array, the storage computing unit in the storage computing array is mainly improved. A gate switch and N resistive memories are arranged in the storage computing unit of the storage computing array, wherein the N resistive memories are connected in series with each other, and after the N resistive memories are connected in series, they will be connected with the selected Connect the switches in series or in parallel.

Please refer to FIG. 1 and FIG. 2 . FIG. 1 is a schematic structural diagram of a series connection between a gate switch and N resistive memories in series in a storage calculation unit provided by an embodiment of the present invention, and FIG. 2 is a storage calculation unit provided by an embodiment of the present invention. A schematic structural diagram of the parallel connection between the gate switch and N resistive memories in series in the unit. In Figure 1 and Figure 2, R _a <b> represents a resistive memory, 0≤a≤N, 0≤b≤i, WL<c> denotes a gate switch, 1≤c≤N, a, b, Both c and i are integers; BL and SL represent two signal input terminals of the storage computing unit.

It should be noted that, in the process of using the storage computing unit to build the storage computing array, the storage computing array can be built with neatly aligned rows and columns, or the storage computing array can be built with staggered rows and columns. That is, the storage computing unit of the next row is arranged between the two storage computing units of the previous row. It is assumed that the size of the storage-computation array is M×K, that is, there are M rows of storage-computation units and K columns of storage-computation units in the storage-computation array. Then, in the actual construction process, the SL terminals of each storage and calculation unit can be connected in sequence in the row direction, and the BL terminals of each storage and calculation unit can be connected in sequence in the column direction, and then each storage calculation unit can be sequentially connected in the row direction. The gate switches in the cells are connected to the same row control line, and connect the row control lines connected to the same resistive memory to the same column control line in the column direction.

It can be understood that when N resistive memories are set in the storage computing unit, the storage computing unit can be used to store more data. Compared with the prior art, the technical solution provided by this embodiment Because more resistive memories can be arranged in each storage computing unit, the storage efficiency of the storage computing array can be significantly improved through the storage computing array. Moreover, the storage computing array provided by the present application can not only make the storage computing array have a higher integration degree, but also improve the data processing speed of the storage computing array.

In addition, as a preferred embodiment, N resistive memories connected in series have the same structure but different physical sizes. That is, through such an arrangement, the storage and computing arrays can have different write currents.

It can be seen that, in the storage computing array provided in this embodiment, N resistive memories connected in series are connected to a gate switch in the storage computing unit. Therefore, compared with the prior art, this In this way, a larger number of storage and computing units can be set under the same area cost. In addition, since in the storage and calculation array, N resistive memories connected in series are set in each storage and calculation unit, the data storage capacity of each storage and calculation unit can be significantly increased by this setting method, and the Thereby, the storage efficiency of the storage computing array is improved.

Based on the above embodiment, this embodiment further describes and optimizes the technical solution. As a preferred implementation manner, the storage computing array further includes:

Metal thin film bidirectional selector or diode in parallel with resistive memory;

Wherein, the on-voltage of the metal film bidirectional selector is greater than or equal to the write voltage of the resistive memory in parallel with the metal thin-film bidirectional selector, and is less than the breakdown voltage of the resistive memory; or the on-voltage of the diode is greater than or equal to that of the diode in parallel The write voltage of the resistive memory is lower than the breakdown voltage of the resistive memory.

It can be understood that, in practical applications, due to the large difference between the currents loaded on each resistive memory in the storage and computing array, in this case, there may be a phenomenon that the resistive memory is broken down by the loading current. Therefore, in this embodiment, in order to avoid the above situation, a metal thin film bidirectional selector or diode is connected in parallel with each resistive memory.

It should be noted that the materials of the metal film bidirectional selectors or diodes are the same, but the thickness of each metal film bidirectional selector or diode is different, because the resistive memories connected in parallel with the metal film bidirectional selectors or diodes have different write currents.

Please refer to FIG. 3 and FIG. 4 . FIG. 3 is a schematic structural diagram of a diode connected in parallel with each resistive memory in the storage computing array shown in FIG. 1 according to an embodiment of the present invention. FIG. 4 is a schematic structural diagram of a diode connected in parallel with each resistive memory in the storage-computation array shown in FIG. 2 according to an embodiment of the present invention.

Obviously, through the technical solution provided in this embodiment, the reliability of the storage computing array during use can be further guaranteed.

Based on the above embodiment, this embodiment further describes and optimizes the technical solution. As a preferred implementation manner, the gate switch is specifically an NMOS transistor or a PMOS transistor or a transmission gate.

Because the NMOS tube, PMOS tube or transmission gate can control the on or off of the storage and calculation unit, and can meet the actual application requirements of the storage and calculation array, in this embodiment, the gate switch is set to the NMOS tube. Or a PMOS tube or a transmission gate, so that the setting method of the strobe switch can be more flexible and diverse.

Based on the above embodiments, this embodiment further describes and optimizes the technical solution. As a preferred implementation, the resistive memory is specifically a magnetoresistive memory or a ferroelectric memory or a phase change memory or a resistive memory.

It can be understood that, because magnetoresistive memory or ferroelectric memory or phase change memory or resistive memory are relatively common memories in practical operation, when the resistive memory is set as magnetoresistive memory or ferroelectric memory or phase change memory, When a variable memory or a resistive variable memory is used, the construction difficulty of the storage computing array provided by the present application in the actual construction process can be relatively reduced.

Based on the above embodiment, this embodiment further describes and optimizes the technical solution. As a preferred implementation manner, the storage computing array further includes:

An enable switch for common control of memory-computing units connected in rows or columns in an array structure.

In this embodiment, an enable switch for jointly controlling the storage and computing units connected in rows or columns in the array structure is also provided in the storage computing array. It is conceivable that, after the enabling switch is set in the storage computing array, the enabling switch can be used to jointly control the storage computing units connected by rows or the storage computing units connected by columns in the storage computing array. Therefore, the convenience for people to use the storage computing array can be further improved.

Please refer to FIG. 5 and FIG. 6 . FIG. 5 shows when the enable switch controls the storage and calculation units connected in columns in the storage and calculation array when the gate switch in the target storage and calculation unit is connected in series with N series resistive memories. 6 is a schematic diagram of the structure when the enable switch controls the storage and calculation units connected in columns in the storage and calculation array when the gating switch in the target storage and calculation unit is connected in parallel with N series resistive memories. It should be noted that, in FIG. 5 and FIG. 6 , Ten ₀ and Ten _M are enable switches. Moreover, in this embodiment, the target storage computing unit refers to any storage computing unit in the storage computing array.

Corresponding to the storage computing array disclosed in the above-mentioned embodiment, the embodiment of the present invention also provides a data read/write computing method corresponding to the above-mentioned storage computing array. Please refer to FIG. 7 , which is provided by an embodiment of the present invention. A flowchart of a data read-write calculation method, wherein the data read-write calculation method includes:

Step S11: when the first data stored in the storage and calculation array is to be read, the resistive memory in the target storage and calculation unit is divided into a plurality of resistance sections, and a corresponding target preset voltage is set for each resistance section, Load the first current on the target storage and calculation unit, read the target voltage corresponding to each resistance interval respectively, compare the target voltage with the target preset voltage in sequence according to the order of the resistance interval, and obtain the target comparison result, so as to pass the target comparison As a result, the first data is read;

It can be understood that when the data stored in the storage computing array needs to be read, the data stored in each storage computing unit in the storage computing array is actually read. Here, the target storage computing in the storage computing array is read. The unit is taken as an example for detailed description. When reading the data stored in the target storage and calculation unit, firstly, the resistive memory in the target storage and calculation unit is divided into a plurality of resistance intervals, and a corresponding target preset voltage is set for each resistance interval; The first current is loaded on the target storage and calculation unit, and the target voltage corresponding to each resistance interval is read respectively. After that, the read target voltage is compared with the target preset voltage in sequence according to the order of the resistance interval, and the target voltage is obtained. The result of the comparison is compared, and the first data stored in the storage computing array is read through the target comparison result.

It is conceivable that when the target comparison result is obtained, it is equivalent to obtaining the data stored in the target storage and calculation unit. At this time, the data stored in each storage and calculation unit is aggregated to read The first data stored in the storage computing array is obtained.

Specifically, in the storage computing array shown in FIG. 1 , when the first data stored in the storage computing array needs to be read, first select the target storage computing unit from which the data is to be read from the storage computing array, and then , the gate switch in the target storage and calculation unit and all resistive memories are turned on, at this time, the first current can be loaded on the target storage and calculation unit through the signal input terminal of the target storage and calculation unit. In the storage computing array shown in FIG. 2, when the first data stored in the storage computing array needs to be read, the target storage computing array to which the data is to be read is selected from the storage computing array, and then the target storage computing array is selected from the storage computing array. The gate switch in the storage and calculation unit is turned off, and at this time, the first current can be loaded on the target storage and calculation unit through the signal input terminal of the target storage and calculation unit.

Step S12: when the second data is to be written into the storage computing array, the target data to be written in the target storage computing unit is determined according to the second data, and the target storage computing unit is determined according to the resistance value of the target storage computing unit. The sequence of applying different currents to obtain the target current sequence, so as to write the target data in the target storage computing unit through the target current sequence;

It can be understood that when the second data is to be written into the storage computing array, it is equivalent to need to write data corresponding to the second data in each storage computing unit in the storage computing array. Here, writing data into the target storage computing unit is taken as an example for specific description.

Firstly, the target data to be written in the target storage and calculation unit is determined according to the second data, and then, the sequence of loading different currents on the target storage and calculation unit is determined according to the resistance value of the target storage and calculation unit, because each layer of resistance The write currents Ii of different types of memory are different, so, under a certain write current Iwrite, only the resistive memory with Ii<Iwrite can be written. Under the principle mechanism, the state stored by different resistive memory combinations can be obtained by current control.

That is, first, the application sequence of the write current is established according to the state of each resistive memory corresponding to the required write state, so as to obtain the target current sequence. The resistance state of the resistive memory is changed by the current, and finally, the states of the plurality of resistive memories are changed to the state corresponding to the write state. Obviously, the target data can be written in the target storage computing unit through this setting.

Specifically, in the storage computing array shown in FIG. 1, when the second data needs to be written in the storage computing array, a target storage computing unit to which data is to be written is first selected from the storage computing array, and then the control The target storage and calculation unit is in an on state, while the gate switch in the adjacent storage and calculation unit is in an off state, and is loaded at both ends of the signal of the target storage and calculation unit according to the resistance value of the resistive memory in the target storage and calculation unit A target current sequence to write target data in the target storage computing unit through the target current sequence. In the storage computing array shown in FIG. 2 , when the second data needs to be written in the storage computing array, a target storage computing unit to which data is to be written is first selected from the storage computing array, and then the storage computing unit is controlled. All storage and calculation units in the array except the target storage and calculation unit are in an on state, and the gate switch in the target storage and calculation unit is controlled to be in an off state, and then the target current sequence is loaded on the target storage and calculation unit to The resistance state of the resistive memory is changed by the current passing through the state of the resistive memory, thereby achieving the purpose of writing data to the target storage computing unit.

In addition, in practical applications, if the gate switch in the target storage computing unit and its N resistive memories connected in series with each other are in series structure, the parity interleaving method can be used to complete all storage computing units in the storage computing array. data read and write. Specifically, in the actual operation process, corresponding digital labels may be set to the storage and calculation units in the storage and calculation array in turn, and then, the storage and calculation units with odd numbers in the storage and calculation array are divided into the first array. The storage and calculation units with even numbers in the storage and calculation array are divided into second arrays; after that, the data in the first array is read or written, and when the data in the first array is read or written. , the data in the second array is read or written, and when the read or write of the data in the second array is completed, the data read or write to the entire storage computing array is completed. Obviously, through this data reading and writing method, data reading or writing to all storage computing units in the storage computing array can be completed within 2N clock cycles, thereby achieving faster data reading and writing effects.

Step S13: when the storage calculation array is to be calculated, determine the target electrical signal and the target storage data corresponding to the target storage calculation unit, and multiply the target electrical signal and the target storage data to obtain the calculation of the target storage calculation unit. The calculated value of all storage computing units in the storage computing array is added to obtain the computing value of the storage computing array.

In practical applications, if you want to perform calculations on the storage computing array, you need to perform calculations on each storage computing unit in the storage computing array. Here, the target storage computing unit is taken as an example for specific description. When calculating the target storage computing unit, first obtain the target electrical signal loaded on the target storage computing unit and the target storage data stored in the target storage computing unit; then, compare the target electrical signal with the target storage data. Multiply to get the calculation value of the target storage calculation unit; finally, calculate the other storage calculation units in the storage calculation array except the target storage calculation unit by the same method, and compare the calculated values of all storage calculation units in the storage calculation array with each other. Add, you will get the calculation value of the storage calculation array.

Obviously, through the technical solution provided by this embodiment, data reading, data writing and data calculation of the storage computing array are realized, and the storage computing array provided by this embodiment does not require additional settings in the storage computing array The logical computing module can perform computation on the storage computing array, thereby relatively reducing the design cost required by the storage computing array.

Based on the above embodiment, this embodiment further describes and optimizes the technical solution. As a preferred implementation, the above step S11: divide the resistive memory in the target storage calculation unit into a plurality of resistance intervals, and each A corresponding target preset voltage is set in one resistance interval, the first current is loaded on the target storage and calculation unit, the target voltage corresponding to each resistance interval is read respectively, and the target voltage and the target preset voltage are sequentially performed according to the order of the resistance interval. The process of comparing and obtaining the target comparison result, so as to read the first data through the target comparison result, includes:

Obtain the total resistance of N mutually connected resistive memories in the target storage computing unit in the storage computing array;

Divide N resistive memories connected in series with each other into 2 ^N resistance intervals according to the total resistance, and set a corresponding preset voltage for each resistance interval to obtain a first preset voltage sequence;

Load the first current on the target storage and calculation unit, and read the voltages corresponding to the 2 ^N resistance intervals respectively to obtain the first voltage sequence;

Comparing the first preset voltage sequence with the first voltage sequence in sequence according to the sequence corresponding to the 2 ^N resistance intervals, to obtain the first comparison sequence;

The first target sub-data stored in the target storage computing unit is read according to the first comparison sequence, and the first data stored in the storage computing array is read according to the first target sub-data.

It can be understood that, because a large number of resistive memories are provided in the storage computing unit, different stored data in the storage computing unit can be obtained by combining the resistive memories in different ways.

Among them, in order to read the data stored in the target storage and calculation unit, the total resistance of the N resistive memories in series in the target storage and calculation unit can be obtained first, and the N resistive memories in series can be divided according to the total resistance into 2 ^N resistance intervals, then, each resistance interval will correspond to a data state, and at this time, the target storage computing unit will correspond to N bits of data.

Then, a corresponding preset voltage is set for each resistance section, that is, the preset voltage corresponding to the first resistance section is set as the first reference voltage, and the preset voltage corresponding to the second resistance section is set as Second reference voltage... Set the preset voltage corresponding to the 2 ^Nth resistance interval as the 2 ^Nth reference voltage, then the first preset voltage sequence is the first reference voltage, the second reference voltage... The second A collection of ^N reference voltages.

Load the first current on the target storage and calculation unit, and read the voltages corresponding to 2 ^N resistance intervals respectively, wherein the voltage readings corresponding to the first resistance interval are the first read voltage and the second resistance interval. The voltage reading is the second reading voltage... The voltage reading corresponding to the 2 ^N resistance interval is the 2 ^N reading voltage, then, the first voltage sequence is the first reading voltage, the second reading voltage... The 2 ^N reading voltage A collection of read voltages.

After that, the first preset voltage sequence and the first voltage sequence are sequentially compared in the order corresponding to the ^2N resistance intervals, that is, the first read voltage is compared with the first reference voltage, and the second read voltage is compared with the first reference voltage. Compare the voltage with the second reference voltage...Compare the 2nd ^N read voltage with the 2nd ^N reference voltage to obtain the first comparison result, the second comparison result...the 2nd ^N comparison result, then, the first comparison sequence That is, the set of the first comparison result, the second comparison result...the second ^N comparison result. It should be noted that if the ith reference voltage is greater than the ith read voltage, the ith comparison result is 1, and if the ith reference voltage is less than the ith read voltage, the ith comparison result is 0, where 1≤i≤2 ^N.

It is conceivable that when the first comparison sequence is obtained, it is equivalent to obtaining the first target sub-data stored in the target storage computing unit, and finally, the same method is used to read and remove the target storage computing from the storage computing array. Data stored by other storage computing units other than the unit. Obviously, when the data stored in all the storage computing units in the storage computing array is obtained, the first data stored in the storage computing array will be read.

Based on the above embodiment, this embodiment further describes and optimizes the technical solution. As a preferred implementation, the above step S11: divide the resistive memory in the target storage calculation unit into a plurality of resistance intervals, and each A corresponding target preset voltage is set in one resistance interval, the first current is loaded on the target storage and calculation unit, the target voltage corresponding to each resistance interval is read respectively, and the target voltage and the target preset voltage are sequentially performed according to the order of the resistance interval. The process of comparing and obtaining the target comparison result, so as to read the first data through the target comparison result, includes:

Obtain the total resistance of N mutually connected resistive memories in the target storage computing unit in the storage computing array;

Divide the N resistive memories connected in series into 2 ^N-1 resistance intervals according to the total resistance, and set a corresponding preset voltage for each resistance interval to obtain a second preset voltage sequence;

Load the first current on the target storage computing unit, and read the voltages corresponding to the 2 ^N-1 resistance intervals respectively to obtain the second voltage sequence;

Comparing the second preset voltage sequence with the second voltage sequence in sequence according to the sequence corresponding to the 2 ^N-1 resistance intervals, to obtain a second comparison sequence;

The second target sub-data stored in the target storage computing unit is read according to the second comparison sequence, and the first data stored in the storage computing array is read according to the second target sub-data.

Or, in practical applications, in order to read the data stored in the target storage and calculation unit, the total resistance of N mutually connected resistive memories in the target storage and calculation unit can also be obtained first, and N are connected in series with each other according to the total resistance. The resistive memory is divided into 2 ^N-1 resistance intervals, then, each resistance interval corresponds to a data state, and at this time, the target storage computing unit corresponds to N-1 bits of data.

Then, a corresponding preset voltage is set for each resistance section, that is, the preset voltage corresponding to the first resistance section is set to the first preset voltage, and the preset voltage corresponding to the second resistance section is set to For the second preset voltage... Set the preset voltage corresponding to the 2 ^N-1 resistance interval as the 2 ^N-1 preset voltage, then, the second preset voltage sequence is the first preset voltage, The second preset voltage...the set of 2 ^N-1 preset voltages.

Load the first current on the target storage and calculation unit, and read the voltages corresponding to 2 ^N-1 resistance intervals respectively, wherein the voltage readings corresponding to the first resistance interval are the first voltage and the second resistance interval. The corresponding voltage reading is the second voltage... The voltage reading corresponding to the 2nd ^N-1 resistance interval is the 2nd ^N-1 voltage, then, the second voltage sequence is the first voltage, the second voltage... The second voltage A collection of ^N-1 voltages.

After that, compare the second preset voltage sequence with the second voltage sequence in sequence according to the sequence corresponding to the 2 ^N-1 resistance intervals, that is, compare the first voltage with the first preset voltage, and compare the first voltage with the first preset voltage. The second voltage is compared with the second preset voltage..., the 2nd ^N-1 voltage is compared with the 2nd ^N-1 preset voltage, and the first comparison value, the second comparison value are obtained respectively... The 2nd ^N-1 The comparison value, then, the second comparison sequence is the set of the first comparison value, the second comparison value...the 2nd ^N-1 comparison value. It should be noted that if the jth preset voltage is greater than the jth voltage, the jth comparison value is 1, and if the jth preset voltage is less than the jth voltage, the jth comparison value is 0, where 1≤j≤2 ^N-1 .

It is conceivable that when the second comparison sequence is obtained, it is equivalent to obtaining the second target sub-data stored in the target storage computing unit, and finally, the same method is used to read the storage computing array to remove the target storage computing. Data stored by other storage computing units other than the unit. Obviously, when the data stored in all the storage computing units in the storage computing array is obtained, the first data stored in the storage computing array will be read.

Obviously, with the technical solution provided in this embodiment, the data reading method of the storage computing array can be made more flexible and diverse.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments may be referred to each other. Finally, it should also be noted that in this document, relational terms such as first and second are used only to distinguish one entity or operation from another, and do not necessarily require or imply these entities or that there is any such actual relationship or sequence between operations. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device that includes a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

A storage computing array and a data reading and writing computing method provided by the present invention have been described in detail above. The principles and implementations of the present invention are described with specific examples in this paper. The descriptions of the above embodiments are only used for Help to understand the method of the present invention and its core idea; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation and application scope. In summary, the content of this specification It should not be construed as a limitation of the present invention.

Claims (9)

1. A storage computing array, characterized in that it includes:

   A plurality of storage and calculation units connected to each other in an array structure, each of the storage and calculation units includes a gate switch, and N resistive memories connected in series or in parallel with the gate switch; wherein one or more Resistive memories are each connected with a bidirectional selector, N≥1.
2. The storage computing array according to claim 1, wherein the N resistive memories connected in series have the same structure, but have different physical sizes.
3. The storage computing array according to claim 1, further comprising:

   A metal thin film bidirectional selector or diode connected in parallel with the resistive memory; wherein, the turn-on voltage of the metal thin film bidirectional selector is greater than or equal to the write voltage of the resistive memory connected in parallel with the metal thin film bidirectional selector, and less than The breakdown voltage of the resistive memory; or the turn-on voltage of the diode is greater than or equal to the write voltage of the resistive memory in parallel with the diode, and less than the breakdown voltage of the resistive memory.
4. The storage computing array according to claim 1, wherein the gate switch is specifically an NMOS transistor or a PMOS transistor or a transmission gate.
5. The storage computing array according to claim 1, wherein the resistive memory is specifically a magnetoresistive memory or a ferroelectric memory or a phase change memory or a resistive memory.
6. The storage computing array according to claim 1, further comprising:

   An enabling switch used to jointly control the storage and computing units connected in rows or columns in the array structure.
7. A data read-write computing method, characterized in that, applied to the storage computing array as claimed in any one of claims 1 to 6, comprising:

   When the first data stored in the storage and calculation array is to be read, the resistive memory in the target storage and calculation unit is divided into a plurality of resistance intervals, and a corresponding target preset voltage is set for each resistance interval. The target storage and calculation unit is loaded with a first current, and the target voltage corresponding to each resistance interval is read respectively, and the target voltage is compared with the target preset voltage in sequence according to the order of the resistance interval to obtain a target comparison result. , to read the first data through the target comparison result;

   When the second data is to be written into the storage and calculation array, the target data to be written in the target storage and calculation unit is determined according to the second data, and is determined according to the resistance value of the target storage and calculation unit Applying the sequence of different currents on the target storage and calculation unit to obtain a target current sequence, so as to write the target data in the target storage and calculation unit through the target current sequence;

   When the storage calculation array is to be calculated, the target electrical signal and the target storage data corresponding to the target storage calculation unit are determined, and the target electrical signal and the target storage data are multiplied to obtain the target electrical signal and the target storage data. The calculation value of the target storage calculation unit is added, and the calculation value of all storage calculation units in the storage calculation array is added to obtain the calculation value of the storage calculation array.
8. The data reading and writing calculation method according to claim 7, wherein the resistive memory in the target storage and calculation unit is divided into a plurality of resistance intervals, and a corresponding target preset is set for each resistance interval voltage, load the first current on the target storage and calculation unit, read the target voltage corresponding to each resistance interval respectively, and compare the target voltage with the target preset voltage in turn according to the order of the resistance interval, to obtain The process of reading the first data through the target comparison result, including:

   obtaining the total resistance of N mutually series-connected resistive memories in the target storage computing unit in the storage computing array;

   Divide N resistive memories connected in series into 2 ^N resistance intervals according to the total resistance, and set a corresponding preset voltage for each resistance interval to obtain a first preset voltage sequence;

   Loading the first current on the target storage and computing unit, and reading the corresponding voltages of 2 ^N resistance intervals respectively, to obtain a first voltage sequence;

   Comparing the first preset voltage sequence with the first voltage sequence in sequence according to the sequence corresponding to the 2 ^N resistance intervals, to obtain a first comparison sequence;

   The first target sub-data stored in the target storage computing unit is read according to the first comparison sequence, and the first data stored in the storage computing array is read according to the first target sub-data.
9. The data reading and writing calculation method according to claim 7, wherein the resistive memory in the target storage and calculation unit is divided into a plurality of resistance intervals, and a corresponding target preset is set for each resistance interval voltage, load the first current on the target storage and calculation unit, read the target voltage corresponding to each resistance interval respectively, and compare the target voltage with the target preset voltage in turn according to the order of the resistance interval, to obtain The process of reading the first data through the target comparison result, including:

   obtaining the total resistance of N mutually series-connected resistive memories in the target storage computing unit in the storage computing array;

   Divide N resistive memories connected in series into 2 ^N-1 resistance intervals according to the total resistance, and set a corresponding preset voltage for each resistance interval to obtain a second preset voltage sequence;

   Loading the first current on the target storage and computing unit, and respectively reading the voltages corresponding to 2 ^N-1 resistance intervals to obtain a second voltage sequence;

   Comparing the second preset voltage sequence with the second voltage sequence in sequence according to the sequence corresponding to the ^2N-1 resistance intervals, to obtain a second comparison sequence;

   The second target sub-data stored in the target storage computing unit is read according to the second comparison sequence, and the first data stored in the storage computing array is read according to the second target sub-data.

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