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WO2022109920A1 - 驱动方法、栅极驱动单元和显示触控装置 - Google Patents

驱动方法、栅极驱动单元和显示触控装置 Download PDF

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Publication number
WO2022109920A1
WO2022109920A1 PCT/CN2020/131743 CN2020131743W WO2022109920A1 WO 2022109920 A1 WO2022109920 A1 WO 2022109920A1 CN 2020131743 W CN2020131743 W CN 2020131743W WO 2022109920 A1 WO2022109920 A1 WO 2022109920A1
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WO
WIPO (PCT)
Prior art keywords
pull
control
node
electrically connected
potential
Prior art date
Application number
PCT/CN2020/131743
Other languages
English (en)
French (fr)
Inventor
胡双
赵敬鹏
白雅杰
唐滔良
朱文涛
潘宏鑫
董兴
刘蕊
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to DE112020007187.1T priority Critical patent/DE112020007187T5/de
Priority to CN202080003016.1A priority patent/CN114793462B/zh
Priority to PCT/CN2020/131743 priority patent/WO2022109920A1/zh
Priority to US17/434,956 priority patent/US11733806B2/en
Publication of WO2022109920A1 publication Critical patent/WO2022109920A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G06F3/04184—Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present disclosure relates to the technical field of display touch control, and in particular, to a driving method, a gate driving unit and a display touch control device.
  • the In Cell (in-cell) touch technology adopts the mode of inserting the touch scan into the display time of a frame to increase the frequency of the touch scan.
  • the display scan and touch scan are alternately performed within the display time of one frame; after the start of the display time of one frame, the touch time needs to be inserted after the fixed row of grid lines is displayed and scanned. After scanning, and then resuming the scanning of the fixed row grid lines, the touch scanning is continued, and the operation is alternately performed until the end of the display time of one frame, and the entire display screen is scanned.
  • the potential of the pull-up node cannot be well maintained at a high voltage during the touch stage, resulting in the phenomenon of screen flickering.
  • Embodiments of the present disclosure provide a driving method, a gate driving unit, and a display touch control device, which solve the problem of a screen flicker phenomenon in the touch control stage of the existing display touch control device.
  • At least one embodiment of the present disclosure provides a driving method, which is applied to a gate driving unit in a display touch device, wherein the gate driving unit includes at least one pull-down circuit; the pull-down circuit is respectively connected with the upper The pull-up node is connected to the pull-down voltage terminal, and is configured to control the connection or disconnection between the pull-up node and the pull-down voltage terminal; a frame of picture display time includes alternately set display stages and touch stages, and at least one of the touch The stage is arranged between two adjacent display stages;
  • the driving method includes:
  • the pull-down transistor is turned off by controlling the potential of the pull-down node
  • the turn-off time of the pull-down transistor is greater than or equal to the duration of the touch phase.
  • the gate driving unit further includes a control voltage terminal and a pull-down control circuit;
  • the pull-down control circuit is respectively electrically connected to the control voltage terminal, the pull-up node and the pull-down node, and is configured according to the The control voltage signal provided by the control voltage terminal and the potential of the pull-up node control the potential of the pull-down node;
  • the driving method includes:
  • the pull-down control circuit controls the potential of the pull-down node, so that the pull-down transistor is turned off.
  • the driving method includes:
  • the first pull-down transistor and the second pull-down transistor are turned off by controlling the potential of the first pull-down node and the potential of the second pull-down node;
  • the turn-off time of the first pull-down transistor is greater than the duration of the touch phase, and the turn-off time of the second pull-down transistor is greater than or equal to the duration of the touch phase.
  • the gate driving unit further includes a first control voltage terminal, a second control voltage terminal, and a pull-down control circuit;
  • the pull-down control circuit is connected to the first control voltage terminal, the second control voltage terminal,
  • the pull-up node, the first pull-down node and the second pull-down node are electrically connected, and are configured to control the voltage according to the first control voltage signal provided by the first control voltage terminal and the potential of the pull-up node the potential of the first pull-down node, and control the potential of the second pull-down node according to the second control voltage signal provided by the second control voltage terminal and the potential of the pull-up node;
  • the driving method includes: :
  • the pull-down control circuit controls the potential of the first pull-down node, so that the first The pull-down transistor is turned off;
  • the pull-down control circuit controls the potential of the second pull-down node, so that the second The pull-down transistor is turned off.
  • the potential of the first control voltage signal is controlled to be an active voltage
  • the potential of the second control voltage signal is controlled to be an inactive voltage
  • the potential of the second control voltage signal is controlled to be an active voltage
  • the potential of the first control voltage signal is controlled to be an inactive voltage
  • the duration of the first switching period and the duration of the second switching period are respectively the display time of one frame; or,
  • the duration of the first switching period and the duration of the second switching period are respectively greater than or equal to the display time of N frames; N is an integer greater than or equal to 1.
  • At least one embodiment of the present disclosure further provides a gate driving unit, comprising at least one pull-down circuit; the pull-down circuit is connected to a pull-up node and a pull-down voltage terminal, respectively, and is configured to control the pull-up circuit.
  • the pull-down voltage terminals of the pull node are connected or disconnected;
  • a frame of picture display time includes alternately arranged display stages and touch stages, and at least one of the touch stages is set between two adjacent display stages;
  • the pull-down circuit is configured to control the disconnection between the pull-up node and the pull-down voltage terminal during the touch control stage.
  • At least one embodiment of the present disclosure further provides a touch display device, including a gate driving circuit, wherein the gate driving circuit includes the above-mentioned gate driving units in multiple stages.
  • the pull-down circuit includes a pull-down transistor, a control electrode of the pull-down transistor is electrically connected to the pull-down node, a first electrode of the pull-down transistor is electrically connected to the pull-up node, and a second electrode of the pull-down transistor is electrically connected to the pull-down node.
  • the pull-down voltage terminal is electrically connected;
  • the pull-down control circuit is electrically connected to the control voltage terminal, the pull-up node and the pull-down node, respectively, and is configured to control the control voltage according to the control voltage signal provided by the control voltage terminal and the potential of the pull-up node. the potential of the pull-down node;
  • the signal providing unit is configured to control the potential of the control voltage signal to be an inactive voltage during the touch phase, so that the pull-down control circuit controls the potential of the pull-down node, thereby controlling the pull-down transistor to be turned off .
  • the gate driving unit includes a first pull-down node, a second pull-down node, a first pull-down circuit, and a second pull-down circuit; the first pull-down circuit includes a first pull-down transistor, and the first pull-down circuit includes a first pull-down transistor.
  • the two pull-down circuits include a second pull-down transistor, a control electrode of the first pull-down transistor is electrically connected to the first pull-down node, and a first electrode of the first pull-down transistor is electrically connected to the pull-up node, The second electrode of the first pull-down transistor is electrically connected to the pull-down voltage terminal; the control electrode of the second pull-down transistor is electrically connected to the second pull-down node, and the first electrode of the second pull-down transistor is electrically connected to the second pull-down node.
  • the pull-up node is electrically connected, and the second pole of the second pull-down transistor is electrically connected to the pull-down voltage terminal;
  • the gate driving unit further includes a first control voltage terminal, a second control voltage terminal and a pull-down control circuit;
  • the pull-down control circuit is connected with the first control voltage terminal, the second control voltage terminal, the pull-up control circuit node, the first pull-down node and the second pull-down node are electrically connected, and are configured to control the first control voltage signal according to the first control voltage signal provided by the first control voltage terminal and the potential of the pull-up node Pulling down the potential of the node, and controlling the potential of the second pull-down node according to the second control voltage signal provided by the second control voltage terminal and the potential of the pull-up node;
  • FIG. 1 is a circuit diagram of at least one embodiment of a gate driving unit in a display touch device according to the present disclosure
  • FIG. 2 is a working timing diagram of at least one embodiment of the gate driving unit during the display time of the first frame
  • FIG. 3 is a working timing diagram of at least one embodiment of the gate driving unit at the display time of the second frame;
  • FIG. 4 is a simulation operation timing diagram of at least one embodiment of the gate driving unit shown in FIG. 1;
  • FIG. 5 is a schematic structural diagram of a display touch device according to at least one embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a display touch device according to at least one embodiment of the present disclosure.
  • FIG. 7 is a circuit diagram of a display touch device according to at least one embodiment of the present disclosure.
  • FIG. 8 is a structural diagram of at least one embodiment of the gate driving unit described in the present disclosure.
  • FIG. 9 is a circuit diagram of at least one embodiment of the gate driving unit described in the present disclosure.
  • the transistors used in at least one embodiment of the present disclosure may all be triodes, thin film transistors, field effect transistors, or other devices with the same characteristics.
  • one of the poles is called the first pole, and the other pole is called the second pole.
  • control electrode when the transistor is a triode, the control electrode may be the base electrode, the first electrode may be the collector electrode, and the second electrode may be the emitter electrode; or the control electrode may be the base electrode electrode, the first electrode can be an emitter electrode, and the second electrode can be a collector electrode.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode;
  • the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the driving method described in at least one embodiment of the present disclosure is applied to a gate driving unit in a display touch device, wherein the gate driving unit includes at least one pull-down circuit; the pull-down circuit is respectively connected to a pull-up node and a pull-down voltage terminal. connected, configured to control the connection or disconnection between the pull-up node and the pull-down voltage terminals; a frame of picture display time includes alternately set display stages and touch stages, and at least one of the touch stages is set adjacent to between the two display stages; the driving method includes:
  • the pull-down circuit controls the disconnection between the pull-up node and the pull-down voltage terminal.
  • the pull-down voltage terminal may be a low voltage terminal, but is not limited thereto.
  • the pull-down circuit in the touch stage, is used to control the disconnection between the pull-up node and the pull-down voltage terminal, so that when the display touch device operates in the touch stage, the pull-up node is The potential of the pull-up node will not be pulled down due to leakage, and the potential of the pull-up node can be well maintained, so that in the display stage after the touch stage is over, the output transistor controlled by the pull-up node (the first pole of the output transistor is connected to the The output clock signal terminal is electrically connected, and the second pole of the output transistor is electrically connected to the gate drive signal output terminal) can be turned on correctly, the control output transistor can be turned on correctly in the display stage, and the splash screen phenomenon is improved.
  • the pull-down circuit controls the disconnection time between the pull-up node and the pull-down voltage terminal to be greater than or equal to the duration of the touch-control phase, that is, at least in the touch-control phase, all The pull-down circuit controls the disconnection between the pull-up node and the pull-down voltage terminal, so that the potential of the pull-up node can be well maintained in the touch stage.
  • the gate driving unit may include a pull-down node and a pull-down circuit
  • the pull-down circuit may include a pull-down transistor, a control electrode of the pull-down transistor is electrically connected to the pull-down node, a first electrode of the pull-down transistor is electrically connected to the pull-up node, and a second electrode of the pull-down transistor is electrically connected to the pull-down node.
  • the pull-down voltage terminal is electrically connected;
  • the driving method includes:
  • the pull-down transistor is turned off, so that the pull-up node and the pull-down voltage terminal are disconnected;
  • the gate driving unit when the gate driving unit includes a pull-down node and a pull-down circuit, the gate-driving unit may further include a control voltage terminal and a pull-down control circuit; the pull-down control circuits are respectively is electrically connected to the control voltage terminal, the pull-up node and the pull-down node, and is configured to control the potential of the pull-down node according to the control voltage signal provided by the control voltage terminal and the potential of the pull-up node;
  • the driving method includes:
  • the pull-down control circuit controls the potential of the pull-down node, so that the pull-down transistor is turned off.
  • the inactive voltage is a low voltage, so that the transistor can be turned off; when the pull-down control circuit includes a control When the transistor connected to the control voltage signal is a p-type transistor, the inactive voltage is a high voltage, so that the transistor can be turned off.
  • the driving method described in at least one embodiment of the present disclosure may further include:
  • the potential of the control voltage signal provided by the control voltage terminal is controlled to be an effective voltage.
  • the effective voltage is a high voltage, so that the transistor can be turned on; when the control electrode included in the pull-down control circuit is an n-type transistor, the effective voltage is a low voltage, so that the transistor can be turned on.
  • the gate driving unit may include a first pull-down node, a second pull-down node, a first pull-down circuit, and a second pull-down circuit;
  • the first pull-down circuit includes a first pull-down transistor, and the The second pull-down circuit includes a second pull-down transistor, a control electrode of the first pull-down transistor is electrically connected to the first pull-down node, and a first electrode of the first pull-down transistor is electrically connected to the pull-up node , the second electrode of the first pull-down transistor is electrically connected to the pull-down voltage terminal;
  • the control electrode of the second pull-down transistor is electrically connected to the second pull-down node, and the first electrode of the second pull-down transistor is electrically connected is electrically connected to the pull-up node, and the second pole of the second pull-down transistor is electrically connected to the pull-down voltage terminal;
  • the driving method includes:
  • the first pull-down transistor and the second pull-down transistor are turned off by controlling the potential of the first pull-down node and the potential of the second pull-down node, so that all pull-down transistors are turned off.
  • the pull-up node is disconnected from the pull-down voltage terminal;
  • the turn-off time of the first pull-down transistor is greater than the duration of the touch phase, and the turn-off time of the second pull-down transistor is greater than or equal to the duration of the touch phase.
  • the gate driving unit when the gate driving unit includes a first pull-down node, a second pull-down node, a first pull-down circuit and a second pull-down circuit, the gate driving unit may further include a first pull-down node, a second pull-down node, a first pull-down circuit, and a second pull-down circuit.
  • the pull-down control circuit controls the potential of the first pull-down node, so that the first The pull-down transistor is turned off;
  • the inactive voltage is a low voltage, so that the transistor can be turned off ;
  • the transistors whose control electrodes of the pull-down control circuit are connected to the first control voltage signal and the second control voltage signal are p-type transistors, the inactive voltage is a high voltage, so that the transistor can be turned off break.
  • the potential of the second control voltage signal is controlled to be an active voltage
  • the potential of the first control voltage signal is controlled to be an inactive voltage
  • the gate driving unit may include two control voltage terminals: a first control voltage terminal and a second control voltage terminal, and the switching period includes a first switching period and a second switching period.
  • the gate driving unit is provided with a first pull-down node and a second pull-down node; in the display stage in the first switching period, the potential of the first control voltage signal is an effective voltage, and in the second switching period In the display stage, the potential of the second control voltage signal is an effective voltage; by using the first control voltage signal and the second control voltage signal, and making the first control voltage signal and the second control voltage signal time-division effective, the first control voltage signal and the second control voltage signal can be effectively
  • the potential of the pull-down node and the potential of the second pull-down node are time-divisionally effective.
  • the duration of the first switching period and the duration of the second switching period are the display time of one frame; or,
  • the duration of the first switching period may be greater than or equal to the display time of N frames
  • the duration of the second switching period may be greater than or equal to the display time of N frames.
  • the duration of the switching period may be, for example, the display time of 2 frames, the display time of 3 frames, the display time of 4 frames, the display time of 5 frames, 1 s (second) or 2 s (second), but not limited thereto.
  • FIG. 1 is a circuit diagram of at least one embodiment of a gate driving unit in a display touch device according to the present disclosure.
  • the gate of M5B and the drain of M5B are both electrically connected to the second control voltage terminal Ve, and the source of M5B is electrically connected to the second pull-down node P22;
  • the gate of M6B is electrically connected to the pull-up node P1, the drain of M6B is electrically connected to the second pull-down node P22, and the source of M6B is electrically connected to the first low-voltage terminal;
  • the pull-down node control circuit includes a first pull-down node control transistor M7A and a second pull-down node control transistor M7B;
  • the gate of M7A is electrically connected to the input terminal I1, the drain of M7A is electrically connected to the first pull-down node P21, and the source of M7A is electrically connected to the first low voltage terminal;
  • the gate of M7B is electrically connected to the input terminal I1, the drain of M7B is electrically connected to the second pull-down node P22, and the source of M7B is electrically connected to the first low-voltage terminal;
  • the first pull-down circuit includes a first pull-down transistor M8A
  • the second pull-down circuit includes a second pull-down transistor M8B
  • the pull-up node control circuit includes an input transistor M1, a reset transistor M2 and a frame reset transistor M15;
  • the gate of M1 and the drain of M1 are both electrically connected to the input terminal I1, and the source of M1 is electrically connected to the pull-up node P1;
  • the gate of M2 is electrically connected to the first reset terminal R1, the drain of M2 is electrically connected to the pull-up node P1, and the source of M2 is electrically connected to the first low voltage terminal;
  • the gate of M15 is electrically connected to the frame reset terminal R0, the drain of M15 is electrically connected to the pull-up node P1, and the source of M15 is electrically connected to the first low voltage terminal;
  • the carry signal output circuit includes a first carry output transistor M11, a second carry output transistor M12A and a third carry output transistor M12B;
  • the gate of M12B is electrically connected to the second pull-down node P22, the drain of M12B is electrically connected to the carry signal output terminal O1, and the source of M12B is electrically connected to the first low voltage terminal;
  • the gate of M3 is electrically connected with the pull-up node P1, the drain of M3 is electrically connected with the output clock signal terminal K1, and the source of M3 is electrically connected with the gate drive signal output terminal G1;
  • the gate of M13B is electrically connected to the second pull-down node P22, the drain of M13B is electrically connected to the gate driving signal output terminal G1, and the source of M13B is electrically connected to the second low voltage terminal;
  • the gate of M4 is electrically connected to the second reset terminal R2, the drain of M4 is electrically connected to the gate driving signal output terminal G1, and the source of M4 is electrically connected to the second low voltage terminal;
  • the first terminal of C1 is electrically connected to the pull-up node P1, and the second terminal of C1 is electrically connected to the gate driving signal output terminal G1.
  • At least one embodiment of the gate driving unit shown in FIG. 1 of the present disclosure may be a gate driving unit used in a Full in cell Oxide (oxide) touch display screen.
  • the output clock signal provided by the output clock signal terminal K1 is a low-voltage signal, so every 73 -76 lines of gate line scanning time, the potential of the pull-up node P1 needs to maintain a high voltage of at least 480us, until the high voltage signal provided by K1 is input to ensure the normal output of the gate drive circuit including the multi-stage gate drive unit.
  • a blanking area is further provided between the display times of the two frames.
  • the control voltage signal switching is performed in the blank area. Therefore, the switching period of the control voltage signal is related to the display refresh rate. For example, when the display refresh rate is 60 Hz, the display time of one frame of picture lasts for about 16.7ms, and the control voltage signal is switched every M ⁇ 16.7ms. ; When the display refresh rate is 120Hz, the display time of one frame of picture lasts about 8.3ms, and the control voltage signal is switched every M ⁇ 8.3ms. Among them, M is a positive integer.
  • switching the control voltage signal refers to: controlling the potential of the first control voltage signal to jump from a high voltage to a low voltage, and controlling the potential of the second control voltage signal to jump from a low voltage to a high voltage or, controlling the potential of the first control voltage signal to jump from a low voltage to a high voltage, and controlling the potential of the second control voltage signal to jump from a high voltage to a low voltage.
  • the threshold voltage shift phenomenon of the transistor whose control electrode is connected to the control voltage signal and the threshold voltage of the transistor whose control electrode is electrically connected to the pull-down node can be enabled. Drift phenomenon is improved.
  • the inventor found that every 2s (seconds), the first control voltage signal provided by Vo jumps from a high voltage signal to a low voltage signal, and the second control voltage signal provided by Ve jumps from a low voltage signal to a high signal voltage signal; or, the first control voltage signal provided by Vo jumps from a low voltage signal to a high voltage signal, and the second control voltage signal provided by Ve jumps from a high voltage signal to a low voltage signal.
  • the charging capacity of the pull-up node P1 will be insufficient.
  • the picture displayed on the display panel will flicker once every 2s. This failure is the LHB flashing screen failure.
  • the display time of the first frame includes a first display stage S11 , a first touch stage S21 , a second display stage S12 , a second touch stage S22 , a third display stage S13 , and a third display stage S13 , which are set in sequence.
  • the first control voltage signal provided by S0 and Vo is a high voltage
  • the first control voltage signal provided by Ve is a low voltage
  • the first control voltage signal and the second control voltage signal are all low voltage .
  • the first display stage included in the display time of the second frame is labeled S31
  • the first touch stage included in the display time of the second frame is labeled S41
  • the second display stage included in the display time of the second frame is labeled S41
  • the stage is marked S32
  • the second touch stage included in the second frame display time is marked S42
  • the third display stage included in the second frame display time is marked S33
  • the stage is marked as S43
  • the fourth display stage included in the display time of the second frame is marked as S34
  • the fourth touch stage included in the display time of the second frame is marked as S44
  • the fifth display stage included in the display time of the second frame is S35
  • the fifth touch stage included in the second frame picture display time is labeled S45
  • the sixth display stage included in the second frame picture display time is labeled S36
  • the sixth touch stage included in the second frame picture display time is S46
  • the seventh display stage included in the second frame picture display time is
  • the control stage is labeled S412; the thirteenth display stage included in the second frame picture display time is labeled S313, and the thirteenth touch stage included in the second frame picture display time is labeled S413;
  • the fourteen display stages are labeled S314, the fourteenth touch stage included in the second frame display time is labeled S414; the fifteenth display stage included in the second frame display time is labeled S315, and the second frame display time includes The fifteenth touch stage is labeled S415; the sixteenth display stage included in the display time of the second frame is labeled S316, and the sixteenth touch stage included in the display time of the second frame is labeled S416;
  • S31, S41, S32, S42, S33, S43, S34, S44, S35, S45, S36, S46, S37, S47, S38, S48, S39, S49, S310, S410, S311, S411, S312, S412, S313, S413, S314, S414, S315, S415, S316 and S416 are set in sequence;
  • the second control voltage signal provided by S0 and Ve is a high voltage
  • the second control voltage signal provided by Vo the first control voltage signal is a low voltage
  • the first control voltage signal and the second control voltage signal are all low voltage .
  • the symbol STV is the frame start signal
  • the input terminal of the first-stage gate driving unit included in the gate driving circuit is connected to the frame start signal STV.
  • M8A and M8B are under high voltage bias in a shorter time gap, so that the leakage of the pull-up node P1 becomes smaller, so that The potential of P1 can maintain a high voltage for a long enough time, the high voltage maintenance time of P1 can be close to 600us, and the flickering phenomenon disappears.
  • FIG. 4 is a simulation operation timing diagram of at least one embodiment of the gate driving unit shown in FIG. 1 .
  • the label STV is the frame start signal.
  • the potential of P1 can be maintained at a high voltage in the touch stage S40 .
  • the gate driving unit includes at least one pull-down circuit; the pull-down circuit is respectively connected to a pull-up node and a pull-down voltage terminal, and is configured to control the connection between the pull-up node and the pull-down voltage terminal. or disconnected; a frame of image display time includes alternately arranged display stages and touch stages, and at least one of the touch stages is set between two adjacent display stages;
  • the pull-down circuit is configured to control the disconnection between the pull-up node and the pull-down voltage terminal during the touch control stage.
  • the gate driving unit controls the disconnection between the pull-up node and the pull-down voltage terminal through the pull-down circuit in the touch stage, so that when the display touch device operates in the touch stage , the potential of the pull-up node will not be pulled down due to leakage, and the potential of the pull-up node can be well maintained, so that in the display stage after the touch stage, the output transistor controlled by the pull-up node (the output transistor The first pole is electrically connected to the output clock signal terminal, and the second pole of the output transistor is electrically connected to the gate drive signal output terminal) can be turned on correctly, the control output transistor can be turned on correctly in the display stage, and the splash screen phenomenon is improved.
  • the display touch device includes a gate driving circuit, and the gate driving circuit includes the above-mentioned gate driving units in multiple stages.
  • the pull-down circuit includes a pull-down transistor, a control electrode of the pull-down transistor is electrically connected to the pull-down node, a first electrode of the pull-down transistor is electrically connected to the pull-up node, and a second electrode of the pull-down transistor is electrically connected to the pull-down node.
  • the pull-down voltage terminal is electrically connected;
  • the pull-down control circuit is electrically connected to the control voltage terminal, the pull-up node and the pull-down node, respectively, and is configured to control the control voltage according to the control voltage signal provided by the control voltage terminal and the potential of the pull-up node. the potential of the pull-down node;
  • the signal providing unit is configured to control the potential of the control voltage signal to be an inactive voltage during the touch phase, so that the pull-down control circuit controls the potential of the pull-down node, thereby controlling the pull-down transistor to be turned off .
  • the display touch device includes a gate driving circuit and a signal providing unit 50; the gate driving circuit includes a multi-level gate driving unit;
  • the gate driving unit includes a pull-down control circuit 51, a control voltage terminal D0, a pull-down node P2 and a pull-down circuit 60;
  • the pull-down control circuit 51 is respectively electrically connected to the control voltage terminal D0, the pull-down node P2 and the pull-up node P1, and is used for the control voltage signal provided at the control voltage terminal D0 and the pull-up node P1. Under the control of the potential, the potential of the pull-down node P2 is controlled;
  • the pull-down circuit 60 includes a pull-down transistor M0; the gate of the pull-down transistor M0 is electrically connected to the pull-down node P2, the drain of the pull-down transistor M0 is electrically connected to the pull-up node P1, and the pull-down transistor M0 is electrically connected to the pull-down node P1.
  • the source of V is electrically connected to the first low voltage terminal; the first low voltage terminal is used to provide the first low voltage V1;
  • the signal providing unit 50 is electrically connected to the control voltage terminal D0, and is used to control the control voltage signal provided by the control voltage terminal D0 to be an effective voltage signal when the display touch device is in the display stage, and use the control voltage signal to be an effective voltage signal.
  • the control voltage signal provided by the control voltage terminal D0 is controlled to be an invalid voltage signal.
  • the potential of the valid voltage signal is the valid voltage
  • the potential of the invalid voltage signal is the invalid voltage
  • the pull-down voltage terminal is the first low voltage terminal, but not limited thereto.
  • M0 is an NMOS transistor (N-type metal-oxide-semiconductor transistor), but not limited thereto.
  • the pull-down control circuit may include a first pull-down control transistor and a second pull-down control transistor, wherein,
  • the control electrode of the first pull-down control transistor and the first electrode of the first pull-down control transistor are both electrically connected to the control voltage terminal, and the second electrode of the first pull-down control transistor is electrically connected to the pull-down control transistor. Node electrical connection;
  • the effective voltage signal when the first pull-down control transistor is an n-type transistor, the effective voltage signal is a high-voltage signal, and the low-voltage signal is a low-voltage signal; when the first pull-down control transistor is an n-type transistor When the pull control transistor is a p-type transistor, the effective voltage signal is a low voltage signal, and the low voltage signal is a high voltage signal; but not limited thereto.
  • the gate driving unit includes a first pull-down node, a second pull-down node, a first pull-down circuit, and a second pull-down circuit; the first pull-down circuit includes a first pull-down transistor, and the first pull-down circuit includes a first pull-down transistor.
  • the two pull-down circuits include a second pull-down transistor, a control electrode of the first pull-down transistor is electrically connected to the first pull-down node, and a first electrode of the first pull-down transistor is electrically connected to the pull-up node, The second electrode of the first pull-down transistor is electrically connected to the pull-down voltage terminal; the control electrode of the second pull-down transistor is electrically connected to the second pull-down node, and the first electrode of the second pull-down transistor is electrically connected to the second pull-down node.
  • the pull-up node is electrically connected, and the second pole of the second pull-down transistor is electrically connected to the pull-down voltage terminal;
  • the gate driving unit further includes a first control voltage terminal, a second control voltage terminal and a pull-down control circuit;
  • the pull-down control circuit is connected with the first control voltage terminal, the second control voltage terminal, the pull-up control circuit node, the first pull-down node and the second pull-down node are electrically connected, and are configured to control the first control voltage signal according to the first control voltage signal provided by the first control voltage terminal and the potential of the pull-up node Pulling down the potential of the node, and controlling the potential of the second pull-down node according to the second control voltage signal provided by the second control voltage terminal and the potential of the pull-up node;
  • the signal providing unit is configured to control the potential of the first control voltage signal provided by the first control voltage terminal to be an inactive voltage during the touch phase, so that the pull-down control circuit controls the first pull-down the potential of the node, thereby controlling the first pull-down transistor to turn off, and is also configured to control the potential of the second control voltage signal provided by the second control voltage terminal to be an inactive voltage during the touch phase, so that the The pull-down control circuit controls the potential of the second pull-down node, thereby controlling the second pull-down transistor to be turned off.
  • the display touch device includes a gate driving circuit and a signal providing unit 50, and the gate driving circuit includes a multi-level gate driving unit;
  • the gate driving unit includes a pull-down control circuit 51, a first control voltage terminal Vo, a second control voltage terminal Ve, a first pull-down node P21, a second pull-down node P22, and a first pull-down circuit 61 and a second pull-down circuit 62;
  • the working cycle of the display touch device includes a plurality of switching cycles, and the switching cycles include a first switching period and a second switching period;
  • the pull-down control circuit 51 is respectively electrically connected to the first control voltage terminal Vo, the second control voltage terminal Ve, the first pull-down node P21, the second pull-down node P22 and the pull-up node P1, It is used to control the potential of the first pull-down node P21 under the control of the first control voltage signal provided by the first control voltage terminal Vo and the potential of the pull-up node P1, and is used to control the potential of the first pull-down node P21 at the second Under the control of the second control voltage signal provided by the control voltage terminal Ve and the potential of the pull-up node P1, the potential of the second pull-down node P22 is controlled;
  • the signal providing unit 50 is electrically connected to the first control voltage terminal Ve and the second control voltage terminal Vo, respectively, and is used for controlling the display and touch device during the first switching period when the display touch device is in the display stage.
  • the first control voltage signal provided by the first control voltage terminal Vo is an effective voltage signal, and is used to control the second control device during the second switching period when the display touch device works in the display stage
  • the second control voltage signal provided by the voltage terminal Ve is an effective voltage signal, and is also used for controlling the first control voltage signal and the second control voltage signal to be both when the display touch device works in the touch stage. Invalid voltage signal;
  • the first pull-down circuit 61 includes a first pull-down transistor M8A, and the second pull-down node 62 includes a second pull-down transistor M8B;
  • the gate of M8A is electrically connected to the first pull-down node P21, the drain of M8A is electrically connected to the pull-up node P1, and the source of M8A is electrically connected to the first low-voltage terminal;
  • the gate of M8B is electrically connected to the second pull-down node P22, the drain of M8B is electrically connected to the pull-up node P1, and the source of M8B is electrically connected to the first low-voltage terminal;
  • the first low voltage terminal is used to provide the first low voltage V1.
  • the pull-down voltage terminal is the first low voltage terminal, but not limited thereto.
  • both M8A and M8B are NMOS transistors, but not limited thereto.
  • the working cycle of the display touch device includes a plurality of switching cycles, and the switching cycle includes a first switching period and a second switching period, and the signal providing unit is further configured to perform the first switching period.
  • the potential of the first control voltage signal is controlled to be an effective voltage
  • the potential of the second control voltage signal is controlled to be an inactive voltage
  • the second control voltage signal is controlled to be an inactive voltage.
  • the potential of the second control voltage signal is controlled to be an active voltage
  • the potential of the first control voltage signal is controlled to be an inactive voltage.
  • the gate driving unit may include two control voltage terminals: a first control voltage terminal and a second control voltage terminal, and the switching period includes a first switching period and a second switching period At this time, the gate driving unit is provided with a first pull-down node and a second pull-down node; in the display stage in the first switching period, the potential of the first control voltage signal is an effective voltage, and in the second switching period In the display stage in the time period, the potential of the second control voltage signal is an effective voltage; at least one embodiment of the present disclosure adopts the first control voltage signal and the second control voltage signal, and makes the first control voltage signal and the second control voltage The signal is time-divisionally effective, so that the potential of the first pull-down node and the potential of the second pull-down node are time-divisionally effective.
  • the pull-down control circuit may include a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, and a fourth pull-down control transistor, wherein,
  • the control electrode of the first pull-down control transistor and the first electrode of the first pull-down control transistor are both electrically connected to the first control voltage terminal, and the second electrode of the first pull-down control transistor is connected to the first control voltage terminal.
  • the first pull-down node is electrically connected;
  • the control electrode of the second pull-down control transistor is electrically connected to the pull-up node, the first electrode of the second pull-down control transistor is electrically connected to the first pull-down node, and the first electrode of the second pull-down control transistor is electrically connected to the first pull-down node.
  • the diode is electrically connected to the first low-voltage terminal;
  • the control electrode of the third pull-down control transistor and the first electrode of the third pull-down control transistor are both electrically connected to the second control voltage terminal, and the second electrode of the third pull-down control transistor is electrically connected to the second control voltage terminal.
  • the pull-down node is electrically connected;
  • the control electrode of the fourth pull-down control transistor is electrically connected to the pull-up node
  • the first electrode of the fourth pull-down control transistor is electrically connected to the second pull-down node
  • the second pull-down control transistor of the fourth pull-down control transistor is electrically connected to the second pull-down node.
  • the pole is electrically connected to the first low voltage terminal.
  • the pull-down control circuit 51 includes a first pull-down control transistor M5A, a second pull-down control transistor M5B, a third pull-down control transistor M6A, and a third pull-down control transistor M6A.
  • Four pull-down control transistors M6B where,
  • the gate of the first pull-down control transistor M5A and the drain of the first pull-down control transistor M5A are both electrically connected to the first control voltage terminal Vo, and the source of the first pull-down control transistor M5A electrically connected to the first pull-down node P21;
  • the gate of the second pull-down control transistor M6A is electrically connected to the pull-up node P1
  • the drain of the second pull-down control transistor M6A is electrically connected to the first pull-down node P21
  • the second pull-down control transistor M6A is electrically connected to the first pull-down node P21.
  • the source of the transistor M6A is electrically connected to the first low voltage terminal; the first low voltage terminal is used to provide the first low voltage V1;
  • the gate of the third pull-down control transistor M5B and the drain of the third pull-down control transistor M5B are both electrically connected to the second control voltage terminal Ve, and the source of the third pull-down control transistor M5B is connected to the second control voltage terminal Ve.
  • the second pull-down node P22 is electrically connected;
  • the gate of the fourth pull-down control transistor M6B is electrically connected to the pull-up node P1
  • the drain of the fourth pull-down control transistor M6B is electrically connected to the second pull-down node P22
  • the fourth pull-down control transistor M6B is electrically connected to the second pull-down node P22.
  • the source of M6B is electrically connected to the first low voltage terminal.
  • M5A, M5B, M6A and M6B are all NMOS transistors, the valid voltage signal is a high voltage signal, and the invalid voltage signal is a low voltage signal, but not limited thereto.
  • each pull-down control transistor when each pull-down control transistor is a p-type transistor, the valid voltage signal is a low voltage signal, and the invalid voltage signal is a high voltage signal, but not limited thereto.
  • the gate driving unit may further include a pull-up node control circuit 81 , a pull-down node control circuit 82, gate drive signal output circuit 83 and carry signal output circuit 84;
  • the pull-up node control circuit 81 is respectively electrically connected with the first reset terminal R1, the frame reset terminal R0, the input terminal I1, the pull-up node P1 and the first low voltage terminal, and is used for the input signal provided by the input terminal I1 Under the control of the pull-up node P1 and the input terminal I1, the connection between the pull-up node P1 and the input terminal I1 is controlled to be connected or disconnected, and under the control of the reset signal provided by the first reset terminal R1, the pull-up node P1 is controlled to be connected to The connection or disconnection between the first low voltage terminals is used to control the connection between the pull-up node P1 and the first low voltage terminal under the control of the frame reset signal provided by the frame reset terminal R0 or disconnected; the pull-down node control circuit 82 is respectively electrically connected to the input terminal I1, the first pull-down node P21, the second pull-down node P22 and the first low voltage terminal, for the input signal provided at the input terminal I1 Under the control of , control the
  • the carry signal output circuit 84 is respectively electrically connected to the pull-up node P1, the first pull-down node P21, the second pull-down node P22, the output clock signal terminal K1, the carry signal output terminal O1 and the first low voltage terminal, and is used for Under the control of the potential of the pull-up node P1, the carry signal output terminal O1 and the output clock signal terminal K1 are controlled to be connected or disconnected, and used to control the potential of the first pull-down node P21 under the control of the carry signal output terminal O1 and the first low voltage terminal to be connected or disconnected, and also used to control the carry signal output terminal O1 under the control of the potential of the second pull-down node P22 Connecting or disconnecting with the first low-voltage terminal;
  • the gate drive signal output circuit 83 is respectively connected with the pull-up node P1, the first pull-down node P21, the second pull-down node P22, the second reset terminal R2, the output clock signal terminal K1, the gate drive signal output terminal G1 and the first pull-down node P22.
  • the carry signal output terminal O1 is used for cascading with the gate driving unit of the adjacent upper row and the gate driving unit of the adjacent lower row, and the input terminal I1 may be connected to the adjacent upper row of gate driving units.
  • the carry signal output terminal of one row of gate driving units is electrically connected, the first reset terminal R1 can be connected to the carry signal output terminal of the adjacent next row gate driving unit, and the gate driving signal output terminal G1 is used to provide a corresponding driving signal.
  • the gate drive signal of the row gate line is used for cascading with the gate driving unit of the adjacent upper row and the gate driving unit of the adjacent lower row, and the input terminal I1 may be connected to the adjacent upper row of gate driving units.
  • the carry signal output terminal of one row of gate driving units is electrically connected
  • the first reset terminal R1 can be connected to the carry signal output terminal of the adjacent next row gate driving unit
  • the gate driving signal output terminal G1 is used to provide a corresponding driving signal.
  • the gate drive signal of the row gate line is used for cas
  • the gate of the first pull-down control transistor M5A and the drain of the first pull-down control transistor M5A are both electrically connected to the first control voltage terminal Vo, and the source of the first pull-down control transistor M5A electrically connected to the first pull-down node P21;
  • the gate of the second pull-down control transistor M6A is electrically connected to the pull-up node P1
  • the drain of the second pull-down control transistor M6A is electrically connected to the first pull-down node P21
  • the second pull-down control transistor M6A is electrically connected to the first pull-down node P21.
  • the source of the transistor M6A is electrically connected to the first low voltage terminal; the first low voltage terminal is used to provide the first low voltage V1;
  • the gate of the third pull-down control transistor M5B and the drain of the third pull-down control transistor M5B are both electrically connected to the second control voltage terminal Ve, and the source of the third pull-down control transistor M5B is connected to the second control voltage terminal Ve.
  • the second pull-down node P22 is electrically connected;
  • the pull-down control circuit includes a first pull-down node control transistor M7A and a second pull-down node control transistor M7B;
  • the gate of M7A is electrically connected to the input terminal I1, the drain of M7A is electrically connected to the first pull-down node P21, and the source of M7A is electrically connected to the first low voltage terminal;
  • the gate of M7B is electrically connected to the input terminal I1, the drain of M7B is electrically connected to the second pull-down node P22, and the source of M7B is electrically connected to the first low-voltage terminal;
  • the pull-up node control circuit includes an input transistor M1, a reset transistor M2 and a frame reset transistor M15; the first pull-down circuit includes a first pull-down transistor M8A, and the second pull-down circuit includes a second pull-down transistor M8B;
  • the gate of M1 and the drain of M1 are both electrically connected to the input terminal I1, and the source of M1 is electrically connected to the pull-up node P1;
  • the gate of M2 is electrically connected to the first reset terminal R1, the drain of M2 is electrically connected to the pull-up node P1, and the source of M2 is electrically connected to the first low voltage terminal;
  • the gate of M8A is electrically connected to the first pull-down node P21, the drain of M8A is electrically connected to the pull-up node P1, and the source of M8A is electrically connected to the first low-voltage terminal;
  • the gate of M8B is electrically connected to the second pull-down node P22, the drain of M8B is electrically connected to the pull-up node P1, and the source of M8B is electrically connected to the first low-voltage terminal;
  • the gate of M15 is electrically connected to the frame reset terminal R0, the drain of M15 is electrically connected to the pull-up node P1, and the source of M15 is electrically connected to the first low voltage terminal;
  • the carry signal output circuit 84 includes a first carry output transistor M11, a second carry output transistor M12A and a third carry output transistor M12B;
  • the gate driving signal output circuit 83 includes a first gate driving output transistor M3, a second gate driving output transistor M13A, a third gate driving output transistor M13B, a fourth gate driving output transistor M4 and an output capacitor C1, in,
  • the gate of M11 is electrically connected to the pull-up node P1, the drain of M11 is electrically connected to the output clock signal terminal K1, and the source of M11 is electrically connected to the carry signal output terminal O1;
  • the gate of M12A is electrically connected to the first pull-down node P21, the drain of M12A is electrically connected to the carry signal output terminal O1, and the source of M12A is electrically connected to the first low voltage terminal;
  • the gate of M12B is electrically connected to the second pull-down node P22, the drain of M12B is electrically connected to the carry signal output terminal O1, and the source of M12B is electrically connected to the first low voltage terminal;
  • the gate of M3 is electrically connected to the pull-up node P1, the drain of M3 is electrically connected to the output clock signal terminal K1, and the source of M3 is electrically connected to the gate driving signal output terminal G1;
  • the gate of M13A is electrically connected to the first pull-down node P21, the drain of M13A is electrically connected to the gate driving signal output terminal G1, the source of M13A is electrically connected to the second low voltage terminal, and the second low voltage terminal is for providing the second low voltage V2;
  • the gate of M13B is electrically connected to the second pull-down node P22, the drain of M13B is electrically connected to the gate driving signal output terminal G1, and the source of M13B is electrically connected to the second low voltage terminal;
  • the gate of M4 is electrically connected to the second reset terminal R2, the drain of M4 is electrically connected to the gate driving signal output terminal G1, and the source of M4 is electrically connected to the second low voltage terminal;
  • the first terminal of C1 is electrically connected to the pull-up node P1, and the second terminal of C1 is electrically connected to the gate driving signal output terminal G1.
  • all transistors are NMOS transistors, but not limited thereto.
  • the second reset terminal R2 may be electrically connected to the gate driving signal output terminal of the adjacent next-stage gate driving unit, but not limited thereto.
  • the display touch device provided by at least one embodiment of the present disclosure may be any product or component with display touch function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.

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Abstract

本公开提供一种驱动方法、栅极驱动单元和显示触控装置。所述驱动方法，应用于显示触控装置中的栅极驱动单元，所述栅极驱动单元包括至少一个下拉电路；所述下拉电路分别与上拉节点和下拉电压端连接，配置为控制所述上拉节点所述下拉电压端之间连通或断开；一帧画面显示时间包括交替设置的显示阶段和触控阶段，至少一所述触控阶段设置于相邻的两所述显示阶段之间；所述驱动方法包括：在所述触控阶段，所述下拉电路控制所述上拉节点与所述下拉电压端之间断开。本公开解决现有的显示触控装置在触控阶段出现闪屏现象的问题。

Description

驱动方法、栅极驱动单元和显示触控装置 技术领域
本公开涉及显示触控技术领域，尤其涉及一种驱动方法、栅极驱动单元和显示触控装置。
背景技术
目前In Cell(内嵌式)触控技术采用将触控扫描插入到一帧画面显示时间之中的模式来提高触控扫描的频率。在此种模式下，在一帧画面显示时间之内，显示扫描与触控扫描交替进行；一帧画面显示时间开始后，显示扫描固定行栅线后，需要插入触控时间，以进行触控扫描，然后再恢复扫描固定行栅线后，继续进行触控扫描，一直交替工作到一帧画面显示时间结束，扫描完整个显示屏幕。现有的显示触控装置会出现由于在触控阶段上拉节点的电位不能很好的维持为高电压，从而导致的闪屏不良现象。
发明内容
本公开实施例提供了一种驱动方法、栅极驱动单元和显示触控装置，解决现有的显示触控装置在触控阶段出现闪屏现象的问题。
在一个方面中，本公开至少一实施例提供了一种驱动方法，应用于显示触控装置中的栅极驱动单元，所述栅极驱动单元包括至少一个下拉电路；所述下拉电路分别与上拉节点和下拉电压端连接，配置为控制所述上拉节点所述下拉电压端之间连通或断开；一帧画面显示时间包括交替设置的显示阶段和触控阶段，至少一所述触控阶段设置于相邻的两所述显示阶段之间；
所述驱动方法包括：
在所述触控阶段，所述下拉电路控制所述上拉节点与所述下拉电压端之间断开。
可选的，所述下拉电路控制所述上拉节点与所述下拉电压端之间断开的时间，大于或等于所述触控阶段持续的时间。
可选的，所述栅极驱动单元包括一个下拉节点和一个下拉电路；所述下 拉电路包括下拉晶体管，所述下拉晶体管的控制极与所述下拉节点电连接，所述下拉晶体管的第一极与所述上拉节点电连接，所述下拉晶体管的第二极与所述下拉电压端电连接；
所述驱动方法包括：
在所述触控阶段，通过控制所述下拉节点的电位，以使得所述下拉晶体管关断；
所述下拉晶体管的关断时间大于或等于所述触控阶段持续的时间。
可选的，所述栅极驱动单元还包括一个控制电压端和下拉控制电路；所述下拉控制电路分别与所述控制电压端、所述上拉节点和所述下拉节点电连接，配置为根据所述控制电压端提供的控制电压信号和所述上拉节点的电位，控制所述下拉节点的电位；所述驱动方法包括：
在所述触控阶段，通过控制所述控制电压信号的电位为无效电压，所述下拉控制电路控制所述下拉节点的电位，从而使得所述下拉晶体管关断。
可选的，本公开至少一实施例所述的驱动方法还包括：
当所述显示触控装置工作于显示阶段时，控制所述控制电压端提供的控制电压信号的电位为有效电压。
可选的，所述栅极驱动单元包括第一下拉节点、第二下拉节点、第一下拉电路和第二下拉电路；所述第一下拉电路包括第一下拉晶体管，所述第二下拉电路包括第二下拉晶体管，所述第一下拉晶体管的控制极与所述第一下拉节点电连接，所述第一下拉晶体管的第一极与所述上拉节点电连接，所述第一下拉晶体管的第二极与所述下拉电压端电连接；所述第二下拉晶体管的控制极与所述第二下拉节点电连接，所述第二下拉晶体管的第一极与所述上拉节点电连接，所述第二下拉晶体管的第二极与所述下拉电压端电连接；
所述驱动方法包括：
在所述触控阶段，通过控制所述第一下拉节点的电位和所述第二下拉节点的电位，以使得所述第一下拉晶体管和所述第二下拉晶体管关断；
所述第一下拉晶体管的关断时间大于所述触控阶段持续的时间，所述第二下拉晶体管的关断时间大于或等于所述触控阶段持续的时间。
可选的，所述栅极驱动单元还包括第一控制电压端、第二控制电压端和 下拉控制电路；所述下拉控制电路与所述第一控制电压端、所述第二控制电压端、所述上拉节点、所述第一下拉节点和所述第二下拉节点电连接，配置为根据所述第一控制电压端提供的第一控制电压信号和所述上拉节点的电位，控制所述第一下拉节点的电位，并根据所述第二控制电压端提供的第二控制电压信号和所述上拉节点的电位，控制所述第二下拉节点的电位；所述驱动方法包括：
在所述触控阶段，通过控制所述第一控制电压端提供的第一控制电压信号的电位为无效电压，所述下拉控制电路控制所述第一下拉节点的电位，从而使得所述第一下拉晶体管关断；
在所述触控阶段，通过控制所述第二控制电压端提供的第二控制电压信号的电位为无效电压，所述下拉控制电路控制所述第二下拉节点的电位，从而使得所述第二下拉晶体管关断。
可选的，所述显示触控装置的工作周期包括多个切换周期，所述切换周期包括第一切换时间段和第二切换时间段，所述驱动方法还包括：
在所述第一切换时间段，当所述显示触控装置工作于显示阶段时，控制所述第一控制电压信号的电位为有效电压，控制第二控制电压信号的电位为无效电压；
在所述第二切换时间段，当所述显示触控装置工作于显示阶段时，控制所述第二控制电压信号的电位为有效电压，控制所述第一控制电压信号的电位为无效电压。
可选的，所述第一切换时间段持续的时间和所述第二切换时间段持续的时间分别为一帧画面显示时间；或者，
所述第一切换时间段持续的时间和所述第二切换时间段持续的时间分别大于或等于N帧画面显示时间；N为大于或等于1的整数。
在第二个方面中，本公开至少一实施例还提供了一种栅极驱动单元，包括至少一个下拉电路；所述下拉电路分别与上拉节点和下拉电压端连接，配置为控制所述上拉节点所述下拉电压端之间连通或断开；一帧画面显示时间包括交替设置的显示阶段和触控阶段，至少一所述触控阶段设置于相邻的两所述显示阶段之间；
所述下拉电路配置为在所述触控阶段，控制所述上拉节点与所述下拉电压端之间断开。
在第三个方面中，本公开至少一实施例还提供了一种显示触控装置，包括栅极驱动电路，所述栅极驱动电路包括多级上述的栅极驱动单元。
可选的，所述栅极驱动单元包括下拉控制电路、一个下拉节点、一个下拉电路和一个控制电压端；所述显示控制装置还包括信号提供单元；
所述下拉电路包括下拉晶体管，所述下拉晶体管的控制极与所述下拉节点电连接，所述下拉晶体管的第一极与所述上拉节点电连接，所述下拉晶体管的第二极与所述下拉电压端电连接；
所述下拉控制电路分别与所述控制电压端、所述上拉节点和所述下拉节点电连接，配置为根据所述控制电压端提供的控制电压信号和所述上拉节点的电位，控制所述下拉节点的电位；
所述信号提供单元配置为在所述触控阶段，通过控制所述控制电压信号的电位为无效电压，以使得所述下拉控制电路控制所述下拉节点的电位，从而控制所述下拉晶体管关断。
可选的，所述栅极驱动单元包括第一下拉节点、第二下拉节点、第一下拉电路和第二下拉电路；所述第一下拉电路包括第一下拉晶体管，所述第二下拉电路包括第二下拉晶体管，所述第一下拉晶体管的控制极与所述第一下拉节点电连接，所述第一下拉晶体管的第一极与所述上拉节点电连接，所述第一下拉晶体管的第二极与所述下拉电压端电连接；所述第二下拉晶体管的控制极与所述第二下拉节点电连接，所述第二下拉晶体管的第一极与所述上拉节点电连接，所述第二下拉晶体管的第二极与所述下拉电压端电连接；
所述栅极驱动单元还包括第一控制电压端、第二控制电压端和下拉控制电路；所述下拉控制电路与所述第一控制电压端、所述第二控制电压端、所述上拉节点、所述第一下拉节点和所述第二下拉节点电连接，配置为根据所述第一控制电压端提供的第一控制电压信号和所述上拉节点的电位，控制所述第一下拉节点的电位，并根据所述第二控制电压端提供的第二控制电压信号和所述上拉节点的电位，控制所述第二下拉节点的电位；
所述信号提供单元配置为在所述触控阶段，通过控制所述第一控制电压 端提供的第一控制电压信号的电位为无效电压，以使得所述下拉控制电路控制所述第一下拉节点的电位，从而控制所述第一下拉晶体管关断，还配置为在所述触控阶段，通过控制所述第二控制电压端提供的第二控制电压信号的电位为无效电压，以使得所述下拉控制电路控制所述第二下拉节点的电位，从而控制所述第二下拉晶体管关断。
可选的，所述显示触控装置的工作周期包括多个切换周期，所述切换周期包括第一切换时间段和第二切换时间段，所述信号提供单元还配置为在所述第一切换时间段，当所述显示触控装置工作于显示阶段时，控制所述第一控制电压信号的电位为有效电压，控制第二控制电压信号的电位为无效电压，并配置为在所述第二切换时间段，当所述显示触控装置工作于显示阶段时，控制所述第二控制电压信号的电位为有效电压，控制所述第一控制电压信号的电位为无效电压。
附图说明
图1是本公开所述的显示触控装置中的栅极驱动单元的至少一实施例的电路图；
图2是在第一帧画面显示时间，所述栅极驱动单元的至少一实施例的工作时序图；
图3是在第二帧画面显示时间，所述栅极驱动单元的至少一实施例的工作时序图；
图4是图1所示的栅极驱动单元的至少一实施例的仿真工作时序图；
图5是本公开至少一实施例所述的显示触控装置的结构示意图；
图6是本公开至少一实施例所述的显示触控装置的结构示意图；
图7是本公开至少一实施例所述的显示触控装置的电路图；
图8是本公开所述的栅极驱动单元的至少一实施例的结构图；
图9是本公开所述的栅极驱动单元的至少一实施例的电路图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行 清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开至少一实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开至少一实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
本公开至少一实施例所述的驱动方法，应用于显示触控装置中的栅极驱动单元，所述栅极驱动单元包括至少一个下拉电路；所述下拉电路分别与上拉节点和下拉电压端连接，配置为控制所述上拉节点所述下拉电压端之间连通或断开；一帧画面显示时间包括交替设置的显示阶段和触控阶段，至少一所述触控阶段设置于相邻的两所述显示阶段之间；所述驱动方法包括：
在所述触控阶段，所述下拉电路控制所述上拉节点与所述下拉电压端之间断开。
在本公开至少一实施例中，所述下拉电压端可以为低电压端，但不以此为限。
本公开至少一实施例所述的驱动方法在触控阶段，通过下拉电路控制上拉节点与下拉电压端之间断开，以使得当所述显示触控装置工作于触控阶段时，上拉节点的电位不会由于漏电而被拉低，能够很好的维持上拉节点的电位，从而使得在触控阶段结束后的显示阶段，上拉节点控制的输出晶体管(该输出晶体管的第一极与输出时钟信号端电连接，该输出晶体管的第二极与栅极驱动信号输出端电连接)能够正确的打开，控制输出晶体管在所述显示阶段能够正确打开，改善闪屏现象。
可选的，所述下拉电路控制所述上拉节点与所述下拉电压端之间断开的 时间，大于或等于所述触控阶段持续的时间，也即，至少在所述触控阶段，所述下拉电路控制上拉节点与下拉电压端之间断开，以能够在触控阶段很好的维持上拉节点的电位。
在具体实施时，所述栅极驱动单元可以包括一个下拉节点和一个下拉电路；
所述下拉电路可以包括下拉晶体管，所述下拉晶体管的控制极与所述下拉节点电连接，所述下拉晶体管的第一极与所述上拉节点电连接，所述下拉晶体管的第二极与所述下拉电压端电连接；
所述驱动方法包括：
在所述触控阶段，通过控制所述下拉节点的电位，以使得所述下拉晶体管关断，从而使得所述上拉节点与所述下拉电压端之间断开；
所述下拉晶体管的关断时间大于或等于所述触控阶段持续的时间。
在本公开至少一实施例中，当所述栅极驱动单元包括一个下拉节点和一个下拉电路时，所述栅极驱动单元还可以包括一个控制电压端和下拉控制电路；所述下拉控制电路分别与所述控制电压端、所述上拉节点和所述下拉节点电连接，配置为根据所述控制电压端提供的控制电压信号和所述上拉节点的电位，控制所述下拉节点的电位；所述驱动方法包括：
在所述触控阶段，通过控制所述控制电压信号的电位为无效电压，所述下拉控制电路控制所述下拉节点的电位，从而使得所述下拉晶体管关断。
当所述下拉控制电路包括的控制极接入所述控制电压信号的晶体管为n型晶体管时，所述无效电压为低电压，以能够使得该晶体管关断；当所述下拉控制电路包括的控制极接入所述控制电压信号的晶体管为p型晶体管时，所述无效电压为高电压，以能够使得该晶体管关断。
在具体所述时，本公开至少一实施例所述的驱动方法还可以包括：
当所述显示触控装置工作于显示阶段时，控制所述控制电压端提供的控制电压信号的电位为有效电压。
当所述下拉控制电路包括的控制极接入所述控制电压信号的晶体管为n型晶体管时，所述有效电压为高电压，以能够使得该晶体管打开；当所述下拉控制电路包括的控制极接入所述控制电压信号的晶体管为p型晶体管时， 所述有效电压为低电压，以能够使得该晶体管打开。
可选的，所述栅极驱动单元可以包括第一下拉节点、第二下拉节点、第一下拉电路和第二下拉电路；所述第一下拉电路包括第一下拉晶体管，所述第二下拉电路包括第二下拉晶体管，所述第一下拉晶体管的控制极与所述第一下拉节点电连接，所述第一下拉晶体管的第一极与所述上拉节点电连接，所述第一下拉晶体管的第二极与所述下拉电压端电连接；所述第二下拉晶体管的控制极与所述第二下拉节点电连接，所述第二下拉晶体管的第一极与所述上拉节点电连接，所述第二下拉晶体管的第二极与所述下拉电压端电连接；
所述驱动方法包括：
在所述触控阶段，通过控制所述第一下拉节点的电位和所述第二下拉节点的电位，以使得所述第一下拉晶体管和所述第二下拉晶体管关断，以使得所述上拉节点与所述下拉电压端之间断开；
所述第一下拉晶体管的关断时间大于所述触控阶段持续的时间，所述第二下拉晶体管的关断时间大于或等于所述触控阶段持续的时间。
在本公开至少一实施例中，当所述栅极驱动单元包括第一下拉节点、第二下拉节点、第一下拉电路和第二下拉电路时，所述栅极驱动单元还可以包括第一控制电压端、第二控制电压端和下拉控制电路；所述下拉控制电路与所述第一控制电压端、所述第二控制电压端、所述上拉节点、所述第一下拉节点和所述第二下拉节点电连接，配置为根据所述第一控制电压端提供的第一控制电压信号和所述上拉节点的电位，控制所述第一下拉节点的电位，并根据所述第二控制电压端提供的第二控制电压信号和所述上拉节点的电位，控制所述第二下拉节点的电位；所述驱动方法包括：
在所述触控阶段，通过控制所述第一控制电压端提供的第一控制电压信号的电位为无效电压，所述下拉控制电路控制所述第一下拉节点的电位，从而使得所述第一下拉晶体管关断；
在所述触控阶段，通过控制所述第二控制电压端提供的第二控制电压信号的电位为无效电压，所述下拉控制电路控制所述第二下拉节点的电位，从而使得所述第二下拉晶体管关断。
当所述下拉控制电路包括的控制极接入所述第一控制电压信号和所述第 二控制电压信号的晶体管为n型晶体管时，所述无效电压为低电压，以能够使得该晶体管关断；当所述下拉控制电路包括的控制极接入所述第一控制电压信号和所述第二控制电压信号的晶体管为p型晶体管时，所述无效电压为高电压，以能够使得该晶体管关断。
可选的，所述栅极驱动单元可以包括第一控制电压端和第二控制电压端；所述显示触控装置的工作周期包括多个切换周期，所述切换周期包括第一切换时间段和第二切换时间段，所述驱动方法还包括：
在所述第一切换时间段，当所述显示触控装置工作于显示阶段时，控制所述第一控制电压信号的电位为有效电压，控制所述第二控制电压信号的电位为无效电压；
在所述第二切换时间段，当所述显示触控装置工作于显示阶段时，控制所述第二控制电压信号的电位为有效电压，控制所述第一控制电压信号的电位为无效电压。
在具体实施时，所述栅极驱动单元可以包括两个控制电压端：第一控制电压端和第二控制电压端，所述切换周期包括第一切换时间段和第二切换时间段，此时所述栅极驱动单元中设有第一下拉节点和第二下拉节点；在第一切换时间段中的显示阶段，第一控制电压信号的电位为有效电压，在第二切换时间段中的显示阶段，第二控制电压信号的电位为有效电压；通过采用第一控制电压信号和第二控制电压信号，并使得第一控制电压信号和第二控制电压信号分时有效，能够使得第一下拉节点的电位和第二下拉节点的电位分时有效。
在本公开至少一实施例中，所述切换周期包括依次设置的第一切换时间段和第二切换时间段；或者，所述切换周期包括依次设置的第二切换时间段和第一切换时间段；但不以此为限。
在本公开至少一实施例中，所述第一切换时间段持续的时间和所述第二切换时间段持续的时间为一帧画面显示时间；或者，
所述第一切换时间段持续的时间大于或等于N帧画面显示时间，所述第二切换时间段持续的时间大于或等于N帧画面显示时间；N为大于或等于1的整数。
可选的，所述第一切换时间段持续的时间和所述第二切换时间段持续的时间可以为一帧画面显示时间，以使得第一切换时间段持续的时间和第二切换时间段持续的时间较短，从而改善控制极接入控制电压信号的晶体管的阈值电压漂移现象，并改善控制极与下拉节点电连接的晶体管的阈值电压漂移现象。
可选的，所述第一切换时间段持续的时间可以大于或等于N帧画面显示时间，所述第二切换时间段持续的时间可以大于或等于N帧画面显示时间，例如，所述第一切换时间段持续的时间例如可以为2帧画面显示时间、3帧画面显示时间、4帧画面显示时间、5帧画面显示时间、1s(秒)或2s(秒)，但不以此为限。
图1是本公开所述的显示触控装置中的栅极驱动单元的至少一实施例的电路图。
如图1所示，所述栅极驱动单元的至少一实施例包括第一下拉电路、第二下拉电路、下拉控制电路、第一控制电压端Vo、第二控制电压端Ve、第一下拉节点P21、第二下拉节点P22、上拉节点控制电路、下拉节点控制电路、栅极驱动信号输出电路和进位信号输出电路；
所述下拉控制电路可以包括第一下拉控制晶体管M5A、第二下拉控制晶体管M6A、第三下拉控制晶体管M5B和第四下拉控制晶体管M6B，其中，
M5A的栅极与M5A的漏极都与所述第一控制电压端Vo电连接，M5A的源极与第一下拉节点P21电连接；
M6A的栅极与所述上拉节点P1电连接，M6A的漏极与所述第一下拉节点P21电连接，M6A的源极与第一低电压端电连接；所述第一低电压端用于提供第一低电压V1；
M5B的栅极与M5B的漏极都与所述第二控制电压端Ve电连接，所述M5B的源极与所述第二下拉节点P22电连接；
M6B的栅极与所述上拉节点P1电连接，M6B的漏极与所述第二下拉节点P22电连接，M6B的源极与所述第一低电压端电连接；
所述下拉节点控制电路包括第一下拉节点控制晶体管M7A和第二下拉节点控制晶体管M7B；
M7A的栅极与输入端I1电连接，M7A的漏极与第一下拉节点P21电连接，M7A的源极与所述第一低电压端电连接；
M7B的栅极与输入端I1电连接，M7B的漏极与第二下拉节点P22电连接，M7B的源极与所述第一低电压端电连接；
所述第一下拉电路包括第一下拉晶体管M8A，所述第二下拉电路包括第二下拉晶体管M8B；所述上拉节点控制电路包括输入晶体管M1、复位晶体管M2和帧复位晶体管M15；
M1的栅极和M1的漏极都与输入端I1电连接，M1的源极与上拉节点P1电连接；
M2的栅极与第一复位端R1电连接，M2的漏极与上拉节点P1电连接，M2的源极与所述第一低电压端电连接；
M8A的栅极与第一下拉节点P21电连接，M8A的漏极与上拉节点P1电连接，M8A的源极与所述第一低电压端电连接；
M8B的栅极与第二下拉节点P22电连接，M8B的漏极与上拉节点P1电连接，M8B的源极与所述第一低电压端电连接；
M15的栅极与帧复位端R0电连接，M15的漏极与上拉节点P1电连接，M15的源极与所述第一低电压端电连接；
所述进位信号输出电路包括第一进位输出晶体管M11、第二进位输出晶体管M12A和第三进位输出晶体管M12B；
所述栅极驱动信号输出电路包括第一栅极驱动输出晶体管M3、第二栅极驱动输出晶体管M13A、第三栅极驱动输出晶体管M13B、第四栅极驱动输出晶体管M4和输出电容C1，其中，
M11的栅极与上拉节点P1电连接，M11的漏极与输出时钟信号端K1电连接，M11的源极与进位信号输出端O1电连接；
M12A的栅极与第一下拉节点P21电连接，M12A的漏极与进位信号输出端O1电连接，M12A的源极与第一低电压端电连接；
M12B的栅极与第二下拉节点P22电连接，M12B的漏极与进位信号输出端O1电连接，M12B的源极与所述第一低电压端电连接；
M3的栅极与上拉节点P1电连接，M3的漏极与输出时钟信号端K1电连 接，M3的源极与栅极驱动信号输出端G1电连接；
M13A的栅极与第一下拉节点P21电连接，M13A的漏极与栅极驱动信号输出端G1电连接，M13A的漏极与第二低电压端电连接，所述第二低电压端用于提供第二低电压V2；
M13B的栅极与第二下拉节点P22电连接，M13B的漏极与栅极驱动信号输出端G1电连接，M13B的源极与所述第二低电压端电连接；
M4的栅极与第二复位端R2电连接，M4的漏极与栅极驱动信号输出端G1电连接，M4的源极与第二低电压端电连接；
C1的第一端与所述上拉节点P1电连接，C1的第二端与所述栅极驱动信号输出端G1电连接。
在图1所示的至少一实施例中，所述下拉电压端为第一低电压端，但不以此为限。
在图1所示的至少一实施例中，所有的晶体管都为NMOS管(N型金属-氧化物-半导体晶体管)，例如金属-氧化物为IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)，但不以此为限。
本公开如图1所示的栅极驱动单元的至少一实施例可以为Full in cell(全内嵌式)Oxide(氧化物)触控显示屏采用的栅极驱动单元。
所述Full in cell(全内嵌式)Oxide(氧化物)触控显示屏在工作时，可以采用LHB(Long Horizon Blanking，长横向空白)触控扫描模式(所述LHB触控扫描模式指的是：将触控扫描时间插入到一帧画面显示时间之中的模式)，例如，一帧画面显示时间可以包括16个显示阶段，在一帧画面显示时间中可以插入16个触控阶段，在每个显示阶段会扫描72行栅线，每72行像素电路显示完成后进入480us的触控阶段，在触控阶段，输出时钟信号端K1提供的输出时钟信号为低电压信号，因此每隔73-76行栅线扫描时间，上拉节点P1的电位至少需保持480us的高电压，直至K1提供的高电压信号输入，才能保证包括多级所述栅极驱动单元的栅极驱动电路正常输出。
在本公开至少一实施例中，两帧画面显示时间之间还设有blanking(空白)区域。在优选情况下，在所述空白区域，进行控制电压信号切换。因此，控制电压信号切换的周期与显示刷新率有关系，例如，当所述显示刷新率为 60Hz时，则一帧画面显示时间持续约16.7ms，则每隔M×16.7ms进行控制电压信号切换；当所述显示刷新率为120Hz时，则一帧画面显示时间持续约8.3ms，则每隔M×8.3ms进行控制电压信号切换。其中，M为正整数。
在本公开至少一实施例中，进行控制电压信号切换指的是：控制第一控制电压信号的电位由高电压跳变为低电压，控制第二控制电压信号的电位由低电压跳变为高电压；或者，控制第一控制电压信号的电位由低电压跳变为高电压，控制第二控制电压信号的电位由高电压跳变为低电压。
在本公开至少一实施例中，通过进行控制电压信号切换，以能够使得控制极接入所述控制电压信号的晶体管的阈值电压漂移现象，以及，控制极与下拉节点电连接的晶体管的阈值电压漂移现象被改善。
在相关技术中，发明人发现每隔2s(秒)，Vo提供的第一控制电压信号由高电压信号跳变为低电压信号，Ve提供的第二控制电压信号由低电压信号跳变为高电压信号；或者，Vo提供的第一控制电压信号由低电压信号跳变为高电压信号，Ve提供的第二控制电压信号由高电压信号跳变为低电压信号，每次控制电压信号高低电压切换时，都会出现上拉节点P1的充电能力不足的情况，宏观上表现为每2s显示面板上显示的画面就会闪烁一次，此不良即为LHB闪屏不良。基于此，本公开至少一实施例采用了一种驱动方法，为显示触控装置中的栅极驱动单元的控制电压端提供控制电压信号，通过使得控制电压信号与同步信号S0同步，以改善LHB闪屏现象。
如图2所示，第一帧画面显示时间包括依次设置的第一显示阶段S11、第一触控阶段S21、第二显示阶段S12、第二触控阶段S22、第三显示阶段S13、第三触控阶段S23、第四显示阶段S14、第四触控阶段S24、第五显示阶段S15、第五触控阶段S25、第六显示阶段S16、第六触控阶段S26、第七显示阶段S17、第七触控阶段S27、第八显示阶段S18、第八触控阶段S28、第九显示阶段S19、第九触控阶段S29、第十显示阶段S110、第十触控阶段S210、第十一显示阶段S111、第十一触控阶段S211、第十二显示阶段S112、第十二触控阶段S212、第十三显示阶段S113、第十三触控阶段S213、第十四显示阶段S114、第十四触控阶段S214、第十五显示阶段S115、第十五触控阶段S215、第十六显示阶段S116和第十六触控阶段S216；
在S11、S12、S13、S14、S15、S16、S17、S18、S19、S110、S111、S112、S113、S114、S115和S116，S0和Vo提供的第一控制电压信号为高电压，Ve提供的第二控制电压信号为低电压；
在S21、S22、S23、S24、S25、S26、S27、S28、S29、S210、S211、S212、S213、S214、S215和S216，S0、第一控制电压信号和第二控制电压信号都为低电压。
如图3所示，第二帧画面显示时间包括的第一显示阶段标号为S31，第二帧画面显示时间包括的第一触控阶段标号为S41，第二帧画面显示时间包括的第二显示阶段标号为S32，第二帧画面显示时间包括的第二触控阶段标号为S42，第二帧画面显示时间包括的第三显示阶段标号为S33，第二帧画面显示时间包括的第三触控阶段标示为S43，第二帧画面显示时间包括的第四显示阶段标号为S34，第二帧画面显示时间包括的第四触控阶段标号为S44；第二帧画面显示时间包括的第五显示阶段标号为S35，第二帧画面显示时间包括的第五触控阶段标号为S45；第二帧画面显示时间包括的第六显示阶段标号为S36，第二帧画面显示时间包括的第六触控阶段标号为S46；第二帧画面显示时间包括的第七显示阶段标号为S37，第二帧画面显示时间包括的第七触控阶段标号为S47；第二帧画面显示时间包括的第八显示阶段标号为S38，第二帧画面显示时间包括的第八触控阶段标号为S48；第二帧画面显示时间包括的第九显示阶段标号为S39，第二帧画面显示时间包括的第九触控阶段标号为S49；第二帧画面显示时间包括的第十显示阶段标号为S310，第二帧画面显示时间包括的第十触控阶段标号为S410；第二帧画面显示时间包括的第十一显示阶段标号为S311，第二帧画面显示时间包括的第十一触控阶段标号为S411；第二帧画面显示时间包括的第十二显示阶段标号为S312，第二帧画面显示时间包括的第十二触控阶段标号为S412；第二帧画面显示时间包括的第十三显示阶段标号为S313，第二帧画面显示时间包括的第十三触控阶段标号为S413；第二帧画面显示时间包括的第十四显示阶段标号为S314，第二帧画面显示时间包括的第十四触控阶段标号为S414；第二帧画面显示时间包括的第十五显示阶段标号为S315，第二帧画面显示时间包括的第十五触控阶段标号为S415；第二帧画面显示时间包括的第十六显示阶段标号为S316，第二 帧画面显示时间包括的第十六触控阶段标号为S416；
如图3所示，S31、S41、S32、S42、S33、S43、S34、S44、S35、S45、S36、S46、S37、S47、S38、S48、S39、S49、S310、S410、S311、S411、S312、S412、S313、S413、S314、S414、S315、S415、S316和S416依次设置；
在S31、S32、S33、S34、S35、S36、S37、S38、S39、S310、S311、S312、S313、S314、S315和S316，S0和Ve提供的第二控制电压信号为高电压，Vo提供的第一控制电压信号为低电压；
在S41、S42、S43、S44、S45、S46、S47、S48、S49、S410、S411、S412、S413、S414、S415和S416，S0、第一控制电压信号和第二控制电压信号都为低电压。
在图3中，标号为STV的是帧起始信号，所述栅极驱动电路包括的第一级栅极驱动单元的输入端接入帧起始信号STV。
通过Vo提供的第一控制电压信号和Ve提供的第二控制电压信号的帧频切换设计，使得M8A和M8B在更短时间间隙处于高压偏置下，使得上拉节点P1的漏电变小，使得P1的电位能够维持足够长时间的高电压，P1的高电压维持时间能够接近600us，闪屏现象消失。
图4是图1所示的栅极驱动单元的至少一实施例的仿真工作时序图。其中，标号为STV的是帧起始信号。
如图4所示，P1的电位在触控阶段S40能够维持为高电压。
本公开至少一实施例所述的栅极驱动单元包括至少一个下拉电路；所述下拉电路分别与上拉节点和下拉电压端连接，配置为控制所述上拉节点所述下拉电压端之间连通或断开；一帧画面显示时间包括交替设置的显示阶段和触控阶段，至少一所述触控阶段设置于相邻的两所述显示阶段之间；
所述下拉电路配置为在所述触控阶段，控制所述上拉节点与所述下拉电压端之间断开。
本公开至少一实施例所述的栅极驱动单元通过所述下拉电路在触控阶段，控制上拉节点与下拉电压端之间断开，以使得当所述显示触控装置工作于触控阶段时，上拉节点的电位不会由于漏电而被拉低，能够很好的维持上拉节点的电位，从而使得在触控阶段结束后的显示阶段，上拉节点控制的输出晶 体管(该输出晶体管的第一极与输出时钟信号端电连接，该输出晶体管的第二极与栅极驱动信号输出端电连接)能够正确的打开，控制输出晶体管在所述显示阶段能够正确打开，改善闪屏现象。
本公开至少一实施例所述的显示触控装置包括栅极驱动电路，所述栅极驱动电路包括多级上述的栅极驱动单元。
可选的，所述栅极驱动单元可以包括下拉控制电路、一个下拉节点、一个下拉电路和一个控制电压端；所述显示控制装置还可以包括信号提供单元；
所述下拉电路包括下拉晶体管，所述下拉晶体管的控制极与所述下拉节点电连接，所述下拉晶体管的第一极与所述上拉节点电连接，所述下拉晶体管的第二极与所述下拉电压端电连接；
所述下拉控制电路分别与所述控制电压端、所述上拉节点和所述下拉节点电连接，配置为根据所述控制电压端提供的控制电压信号和所述上拉节点的电位，控制所述下拉节点的电位；
所述信号提供单元配置为在所述触控阶段，通过控制所述控制电压信号的电位为无效电压，以使得所述下拉控制电路控制所述下拉节点的电位，从而控制所述下拉晶体管关断。
本公开至少一实施例所述的显示触控装置包括栅极驱动电路和信号提供单元50；所述栅极驱动电路包括多级栅极驱动单元；
如图5所示，所述栅极驱动单元包括下拉控制电路51、控制电压端D0、下拉节点P2和下拉电路60；
所述下拉控制电路51分别与所述控制电压端D0、所述下拉节点P2和上拉节点P1电连接，用于在所述控制电压端D0提供的控制电压信号和所述上拉节点P1的电位的控制下，控制所述下拉节点P2的电位；
所述下拉电路60包括下拉晶体管M0；所述下拉晶体管M0的栅极与所述下拉节点P2电连接，所述下拉晶体管M0的漏极与所述上拉节点P1电连接，所述下拉晶体管M0的源极与第一低电压端电连接；所述第一低电压端用于提供第一低电压V1；
所述信号提供单元50，与所述控制电压端D0电连接，用于当所述显示触控装置工作于显示阶段时，控制所述控制电压端D0提供的控制电压信号 为有效电压信号，并用于当所述显示触控装置工作于触控阶段时，控制所述控制电压端D0提供的控制电压信号为无效电压信号。
在本公开至少一实施例中，所述有效电压信号的电位为有效电压，所述无效电压信号的电位为无效电压。
在图5所示的至少一实施例中，所述下拉电压端为第一低电压端，但不以此为限。
在图5所示的至少一实施例中，M0为NMOS管(N型金属-氧化物-半导体晶体管)，但不以此为限。
在具体实施时，所述下拉控制电路可以包括第一下拉控制晶体管和第二下拉控制晶体管，其中，
所述第一下拉控制晶体管的控制极与所述第一下拉控制晶体管的第一极都与所述控制电压端电连接，所述第一下拉控制晶体管的第二极与所述下拉节点电连接；
所述第二下拉控制晶体管的控制极与所述上拉节点电连接，所述第二下拉控制晶体管的第一极与所述下拉节点电连接，所述第二下拉控制晶体管的第二极与所述第一低电压端电连接。
在本公开至少一实施例中，当所述第一下拉控制晶体管为n型晶体管时，所述有效电压信号为高电压信号，所述低电压信号为低电压信号；当所述第一下拉控制晶体管为p型晶体管时，所述有效电压信号为低电压信号，所述低电压信号为高电压信号；但不以此为限。
可选的，所述栅极驱动单元包括第一下拉节点、第二下拉节点、第一下拉电路和第二下拉电路；所述第一下拉电路包括第一下拉晶体管，所述第二下拉电路包括第二下拉晶体管，所述第一下拉晶体管的控制极与所述第一下拉节点电连接，所述第一下拉晶体管的第一极与所述上拉节点电连接，所述第一下拉晶体管的第二极与所述下拉电压端电连接；所述第二下拉晶体管的控制极与所述第二下拉节点电连接，所述第二下拉晶体管的第一极与所述上拉节点电连接，所述第二下拉晶体管的第二极与所述下拉电压端电连接；
所述栅极驱动单元还包括第一控制电压端、第二控制电压端和下拉控制电路；所述下拉控制电路与所述第一控制电压端、所述第二控制电压端、所 述上拉节点、所述第一下拉节点和所述第二下拉节点电连接，配置为根据所述第一控制电压端提供的第一控制电压信号和所述上拉节点的电位，控制所述第一下拉节点的电位，并根据所述第二控制电压端提供的第二控制电压信号和所述上拉节点的电位，控制所述第二下拉节点的电位；
所述信号提供单元配置为在所述触控阶段，通过控制所述第一控制电压端提供的第一控制电压信号的电位为无效电压，以使得所述下拉控制电路控制所述第一下拉节点的电位，从而控制所述第一下拉晶体管关断，还配置为在所述触控阶段，通过控制所述第二控制电压端提供的第二控制电压信号的电位为无效电压，以使得所述下拉控制电路控制所述第二下拉节点的电位，从而控制所述第二下拉晶体管关断。
本公开至少一实施例所述的显示触控装置包括栅极驱动电路和信号提供单元50，所述栅极驱动电路包括多级栅极驱动单元；
如图6所示，所述栅极驱动单元包括下拉控制电路51、第一控制电压端Vo、第二控制电压端Ve、第一下拉节点P21、第二下拉节点P22、第一下拉电路61和第二下拉电路62；所述显示触控装置的工作周期包括多个切换周期，所述切换周期包括第一切换时间段和第二切换时间段；
所述下拉控制电路51分别与所述第一控制电压端Vo、所述第二控制电压端Ve、所述第一下拉节点P21、所述第二下拉节点P22和上拉节点P1电连接，用于在所述第一控制电压端Vo提供的第一控制电压信号和所述上拉节点P1的电位的控制下，控制所述第一下拉节点P21的电位，并用于在所述第二控制电压端Ve提供的第二控制电压信号和所述上拉节点P1的电位的控制下，控制所述第二下拉节点P22的电位；
所述信号提供单元50分别与第一控制电压端Ve和第二控制电压端Vo电连接，用于在所述第一切换时间段，当所述显示触控装置工作于显示阶段时，控制所述第一控制电压端Vo提供的第一控制电压信号为有效电压信号，并用于在所述第二切换时间段，当所述显示触控装置工作于显示阶段时，控制所述的第二控制电压端Ve提供的第二控制电压信号为有效电压信号，还用于当所述显示触控装置工作于触控阶段时，控制所述第一控制电压信号和所述第二控制电压信号都为无效电压信号；
所述第一下拉电路61包括第一下拉晶体管M8A，所述第二下拉节点62包括第二下拉晶体管M8B；
M8A的栅极与第一下拉节点P21电连接，M8A的漏极与上拉节点P1电连接，M8A的源极与所述第一低电压端电连接；
M8B的栅极与第二下拉节点P22电连接，M8B的漏极与上拉节点P1电连接，M8B的源极与所述第一低电压端电连接；
所述第一低电压端用于提供第一低电压V1。
在图6所示的至少一实施例中，所述下拉电压端为第一低电压端，但不以此为限。
在图6所示的至少一实施例中，M8A和M8B都为NMOS管，但不以此为限。
可选的，所述显示触控装置的工作周期包括多个切换周期，所述切换周期包括第一切换时间段和第二切换时间段，所述信号提供单元还配置为在所述第一切换时间段，当所述显示触控装置工作于显示阶段时，控制所述第一控制电压信号的电位为有效电压，控制第二控制电压信号的电位为无效电压，并配置为在所述第二切换时间段，当所述显示触控装置工作于显示阶段时，控制所述第二控制电压信号的电位为有效电压，控制所述第一控制电压信号的电位为无效电压。
在本公开至少一实施例中，所述栅极驱动单元可以包括两个控制电压端：第一控制电压端和第二控制电压端，所述切换周期包括第一切换时间段和第二切换时间段，此时所述栅极驱动单元中设有第一下拉节点和第二下拉节点；在第一切换时间段中的显示阶段，第一控制电压信号的电位为有效电压，在第二切换时间段中的显示阶段，第二控制电压信号的电位为有效电压；本公开至少一实施例通过采用第一控制电压信号和第二控制电压信号，并使得第一控制电压信号和第二控制电压信号分时有效，能够使得第一下拉节点的电位和第二下拉节点的电位分时有效。
在具体实施时，所述下拉控制电路可以包括第一下拉控制晶体管、第二下拉控制晶体管、第三下拉控制晶体管和第四下拉控制晶体管，其中，
所述第一下拉控制晶体管的控制极与所述第一下拉控制晶体管的第一极 都与所述第一控制电压端电连接，所述第一下拉控制晶体管的第二极与所述第一下拉节点电连接；
所述第二下拉控制晶体管的控制极与所述上拉节点电连接，所述第二下拉控制晶体管的第一极与所述第一下拉节点电连接，所述第二下拉控制晶体管的第二极与所述第一低电压端电连接；
所述第三下拉控制晶体管的控制极与所述第三下拉控制晶体管的第一极都与所述第二控制电压端电连接，所述第三下拉控制晶体管的第二极与所述第二下拉节点电连接；
所述第四下拉控制晶体管的控制极与所述上拉节点电连接，所述第四下拉控制晶体管的第一极与所述第二下拉节点电连接，所述第四下拉控制晶体管的第二极与所述第一低电压端电连接。
如图7所示，在图6所示的至少一实施例的基础上，所述下拉控制电路51包括第一下拉控制晶体管M5A、第二下拉控制晶体管M5B、第三下拉控制晶体管M6A和第四下拉控制晶体管M6B，其中，
所述第一下拉控制晶体管M5A的栅极与所述第一下拉控制晶体管M5A的漏极都与所述第一控制电压端Vo电连接，所述第一下拉控制晶体管M5A的源极与所述第一下拉节点P21电连接；
所述第二下拉控制晶体管M6A的栅极与所述上拉节点P1电连接，所述第二下拉控制晶体管M6A的漏极与所述第一下拉节点P21电连接，所述第二下拉控制晶体管M6A的源极与所述第一低电压端电连接；所述第一低电压端用于提供第一低电压V1；
所述第三下拉控制晶体管M5B的栅极与所述第三下拉控制晶体管M5B的漏极都与所述第二控制电压端Ve电连接，所述第三下拉控制晶体管M5B的源极与所述第二下拉节点P22电连接；
所述第四下拉控制晶体管M6B的栅极与所述上拉节点P1电连接，所述第四下拉控制晶体管M6B的漏极与所述第二下拉节点P22电连接，所述第四下拉控制晶体管M6B的源极与所述第一低电压端电连接。
在图7所示的至少一实施例中，M5A、M5B、M6A和M6B都为NMOS管，有效电压信号为高电压信号，无效电压信号为低电压信号，但不以此为 限。
在本公开至少一实施例中，当各下拉控制晶体管为p型晶体管时，有效电压信号为低电压信号，无效电压信号为高电压信号，但不以此为限。
如图8所示，在图6所示的栅极驱动单元的至少一实施例的基础上，本公开至少一实施例所述的栅极驱动单元还可以包括上拉节点控制电路81、下拉节点控制电路82、栅极驱动信号输出电路83和进位信号输出电路84；
所述上拉节点控制电路81分别与第一复位端R1、帧复位端R0、输入端I1、上拉节点P1和第一低电压端电连接，用于在所述输入端I1提供的输入信号的控制下，控制所述上拉节点P1与所述输入端I1之间连通或断开，并用于在所述第一复位端R1提供的复位信号的控制下，控制所述上拉节点P1与所述第一低电压端之间连通或断开，用于在所述帧复位端R0提供的帧复位信号的控制下，控制所述上拉节点P1与所述第一低电压端之间连通或断开；所述下拉节点控制电路82分别与输入端I1、第一下拉节点P21、第二下拉节点P22和第一低电压端电连接，用于在所述输入端I1提供的输入信号的控制下，控制所述第一下拉节点P21与所述第一低电压端之间连通或断开，并控制所述第二下拉节点P22与所述第一低电压端之间连通或断开；
所述进位信号输出电路84分别与上拉节点P1、第一下拉节点P21、第二下拉节点P22、输出时钟信号端K1、进位信号输出端O1和第一低电压端电连接，用于在所述上拉节点P1的电位的控制下，控制所述进位信号输出端O1与所述输出时钟信号端K1之间连通或断开，并用于在所述第一下拉节点P21的电位的控制下，控制所述进位信号输出端O1与所述第一低电压端之间连通或断开，还用于在所述第二下拉节点P22的电位的控制下，控制所述进位信号输出端O1与所述第一低电压端之间连通或断开；
所述栅极驱动信号输出电路83分别与上拉节点P1、第一下拉节点P21、第二下拉节点P22、第二复位端R2、输出时钟信号端K1、栅极驱动信号输出端G1和第二低电压端电连接，用于在所述上拉节点P1的电位的控制下，控制所述栅极驱动信号输出端G1与所述输出时钟信号端K1之间连通或断开，并用于在所述第一下拉节点P21的电位的控制下，控制所述栅极驱动信号输出端G1与所述第二低电压端之间连通或断开，还用于在所述第二下拉节点 P22的电位的控制下，控制所述栅极驱动信号输出端G1与所述第二低电压端之间连通或断开，并用于在所述第二复位端R2提供的第二复位信号的控制下，控制所述栅极驱动信号输出端G1与所述第二低电压端之间连通或断开；所述第二低电压端用于提供第二低电压V2。
在图8所示的至少一实施例中，进位信号输出端O1用于与相邻上一行栅极驱动单元和相邻下一行栅极驱动单元级联，所述输入端I1可以与相邻上一行栅极驱动单元的进位信号输出端电连接，所述第一复位端R1可以与相邻下一行栅极驱动单元的进位信号输出端，所述栅极驱动信号输出端G1用于提供驱动相应行栅线的栅极驱动信号。
如图9所示，在图8所示的栅极驱动单元的基础上，所述下拉控制电路包括第一下拉控制晶体管M5A、第二下拉控制晶体管M5B、第三下拉控制晶体管M6A和第四下拉控制晶体管M6B，其中，
所述第一下拉控制晶体管M5A的栅极与所述第一下拉控制晶体管M5A的漏极都与所述第一控制电压端Vo电连接，所述第一下拉控制晶体管M5A的源极与所述第一下拉节点P21电连接；
所述第二下拉控制晶体管M6A的栅极与所述上拉节点P1电连接，所述第二下拉控制晶体管M6A的漏极与所述第一下拉节点P21电连接，所述第二下拉控制晶体管M6A的源极与所述第一低电压端电连接；所述第一低电压端用于提供第一低电压V1；
所述第三下拉控制晶体管M5B的栅极与所述第三下拉控制晶体管M5B的漏极都与所述第二控制电压端Ve电连接，所述第三下拉控制晶体管M5B的源极与所述第二下拉节点P22电连接；
所述第四下拉控制晶体管M6B的栅极与所述上拉节点P1电连接，所述第四下拉控制晶体管M6B的漏极与所述第二下拉节点P22电连接，所述第四下拉控制晶体管M6B的源极与所述第一低电压端电连接；
所述下拉控制电路包括第一下拉节点控制晶体管M7A和第二下拉节点控制晶体管M7B；
M7A的栅极与输入端I1电连接，M7A的漏极与第一下拉节点P21电连接，M7A的源极与所述第一低电压端电连接；
M7B的栅极与输入端I1电连接，M7B的漏极与第二下拉节点P22电连接，M7B的源极与所述第一低电压端电连接；
所述上拉节点控制电路包括输入晶体管M1、复位晶体管M2和帧复位晶体管M15；所述第一下拉电路包括第一下拉晶体管M8A，所述第二下拉电路包括第二下拉晶体管M8B；
M1的栅极和M1的漏极都与输入端I1电连接，M1的源极与上拉节点P1电连接；
M2的栅极与第一复位端R1电连接，M2的漏极与上拉节点P1电连接，M2的源极与所述第一低电压端电连接；
M8A的栅极与第一下拉节点P21电连接，M8A的漏极与上拉节点P1电连接，M8A的源极与所述第一低电压端电连接；
M8B的栅极与第二下拉节点P22电连接，M8B的漏极与上拉节点P1电连接，M8B的源极与所述第一低电压端电连接；
M15的栅极与帧复位端R0电连接，M15的漏极与上拉节点P1电连接，M15的源极与所述第一低电压端电连接；
所述进位信号输出电路84包括第一进位输出晶体管M11、第二进位输出晶体管M12A和第三进位输出晶体管M12B；
所述栅极驱动信号输出电路83包括第一栅极驱动输出晶体管M3、第二栅极驱动输出晶体管M13A、第三栅极驱动输出晶体管M13B、第四栅极驱动输出晶体管M4和输出电容C1，其中，
M11的栅极与上拉节点P1电连接，M11的漏极与输出时钟信号端K1电连接，M11的源极与进位信号输出端O1电连接；
M12A的栅极与第一下拉节点P21电连接，M12A的漏极与进位信号输出端O1电连接，M12A的源极与第一低电压端电连接；
M12B的栅极与第二下拉节点P22电连接，M12B的漏极与进位信号输出端O1电连接，M12B的源极与所述第一低电压端电连接；
M3的栅极与上拉节点P1电连接，M3的漏极与输出时钟信号端K1电连接，M3的源极与栅极驱动信号输出端G1电连接；
M13A的栅极与第一下拉节点P21电连接，M13A的漏极与栅极驱动信 号输出端G1电连接，M13A的源极与第二低电压端电连接，所述第二低电压端用于提供第二低电压V2；
M13B的栅极与第二下拉节点P22电连接，M13B的漏极与栅极驱动信号输出端G1电连接，M13B的源极与所述第二低电压端电连接；
M4的栅极与第二复位端R2电连接，M4的漏极与所述栅极驱动信号输出端G1电连接，M4的源极与所述第二低电压端电连接；
C1的第一端与所述上拉节点P1电连接，C1的第二端与所述栅极驱动信号输出端G1电连接。
在图9所示的栅极驱动单元的至少一实施例中，所有的晶体管都为NMOS管，但不以此为限。
在图9所示的栅极驱动单元的至少一实施例中，第二复位端R2可以与相邻下一级栅极驱动单元的栅极驱动信号输出端电连接，但不以此为限。
本公开至少一实施例所提供的显示触控装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示触控功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (14)

  1. 一种驱动方法，应用于显示触控装置中的栅极驱动单元，所述栅极驱动单元包括至少一个下拉电路；所述下拉电路分别与上拉节点和下拉电压端连接，配置为控制所述上拉节点所述下拉电压端之间连通或断开；一帧画面显示时间包括交替设置的显示阶段和触控阶段，至少一所述触控阶段设置于相邻的两所述显示阶段之间；
    所述驱动方法包括：
    在所述触控阶段，所述下拉电路控制所述上拉节点与所述下拉电压端之间断开。
  2. 如权利要求1所述的驱动方法，其中，所述下拉电路控制所述上拉节点与所述下拉电压端之间断开的时间，大于或等于所述触控阶段持续的时间。
  3. 如权利要求1所述的驱动方法，其中，所述栅极驱动单元包括一个下拉节点和一个下拉电路；所述下拉电路包括下拉晶体管，所述下拉晶体管的控制极与所述下拉节点电连接，所述下拉晶体管的第一极与所述上拉节点电连接，所述下拉晶体管的第二极与所述下拉电压端电连接；
    所述驱动方法包括：
    在所述触控阶段，通过控制所述下拉节点的电位，以使得所述下拉晶体管关断；
    所述下拉晶体管的关断时间大于或等于所述触控阶段持续的时间。
  4. 如权利要求3所述的驱动方法，其中，所述栅极驱动单元还包括一个控制电压端和下拉控制电路；所述下拉控制电路分别与所述控制电压端、所述上拉节点和所述下拉节点电连接，配置为根据所述控制电压端提供的控制电压信号和所述上拉节点的电位，控制所述下拉节点的电位；所述驱动方法包括：
    在所述触控阶段，通过控制所述控制电压信号的电位为无效电压，所述下拉控制电路控制所述下拉节点的电位，从而使得所述下拉晶体管关断。
  5. 如权利要求4所述的驱动方法，其中，还包括：
    当所述显示触控装置工作于显示阶段时，控制所述控制电压端提供的控制电压信号的电位为有效电压。
  6. 如权利要求1所述的驱动方法，其中，所述栅极驱动单元包括第一下拉节点、第二下拉节点、第一下拉电路和第二下拉电路；所述第一下拉电路包括第一下拉晶体管，所述第二下拉电路包括第二下拉晶体管，所述第一下拉晶体管的控制极与所述第一下拉节点电连接，所述第一下拉晶体管的第一极与所述上拉节点电连接，所述第一下拉晶体管的第二极与所述下拉电压端电连接；所述第二下拉晶体管的控制极与所述第二下拉节点电连接，所述第二下拉晶体管的第一极与所述上拉节点电连接，所述第二下拉晶体管的第二极与所述下拉电压端电连接；
    所述驱动方法包括：
    在所述触控阶段，通过控制所述第一下拉节点的电位和所述第二下拉节点的电位，以使得所述第一下拉晶体管和所述第二下拉晶体管关断；
    所述第一下拉晶体管的关断时间大于所述触控阶段持续的时间，所述第二下拉晶体管的关断时间大于或等于所述触控阶段持续的时间。
  7. 如权利要求6所述的驱动方法，其中，所述栅极驱动单元还包括第一控制电压端、第二控制电压端和下拉控制电路；所述下拉控制电路与所述第一控制电压端、所述第二控制电压端、所述上拉节点、所述第一下拉节点和所述第二下拉节点电连接，配置为根据所述第一控制电压端提供的第一控制电压信号和所述上拉节点的电位，控制所述第一下拉节点的电位，并根据所述第二控制电压端提供的第二控制电压信号和所述上拉节点的电位，控制所述第二下拉节点的电位；所述驱动方法包括：
    在所述触控阶段，通过控制所述第一控制电压端提供的第一控制电压信号的电位为无效电压，所述下拉控制电路控制所述第一下拉节点的电位，从而使得所述第一下拉晶体管关断；
    在所述触控阶段，通过控制所述第二控制电压端提供的第二控制电压信号的电位为无效电压，所述下拉控制电路控制所述第二下拉节点的电位，从而使得所述第二下拉晶体管关断。
  8. 如权利要求7所述的驱动方法，其中，所述显示触控装置的工作周期包括多个切换周期，所述切换周期包括第一切换时间段和第二切换时间段，所述驱动方法还包括：
    在所述第一切换时间段，当所述显示触控装置工作于显示阶段时，控制所述第一控制电压信号的电位为有效电压，控制第二控制电压信号的电位为无效电压；
    在所述第二切换时间段，当所述显示触控装置工作于显示阶段时，控制所述第二控制电压信号的电位为有效电压，控制所述第一控制电压信号的电位为无效电压。
  9. 如权利要求8所述的驱动方法，其中，所述第一切换时间段持续的时间和所述第二切换时间段持续的时间分别为一帧画面显示时间；或者，
    所述第一切换时间段持续的时间和所述第二切换时间段持续的时间分别大于或等于N帧画面显示时间；N为大于或等于1的整数。
  10. 一种栅极驱动单元，包括至少一个下拉电路；所述下拉电路分别与上拉节点和下拉电压端连接，配置为控制所述上拉节点所述下拉电压端之间连通或断开；一帧画面显示时间包括交替设置的显示阶段和触控阶段，至少一所述触控阶段设置于相邻的两所述显示阶段之间；
    所述下拉电路配置为在所述触控阶段，控制所述上拉节点与所述下拉电压端之间断开。
  11. 一种显示触控装置，包括栅极驱动电路，所述栅极驱动电路包括多级如权利要求10所述的栅极驱动单元。
  12. 如权利要求11所述的显示触控装置，其中，所述栅极驱动单元包括下拉控制电路、一个下拉节点、一个下拉电路和一个控制电压端；所述显示控制装置还包括信号提供单元；
    所述下拉电路包括下拉晶体管，所述下拉晶体管的控制极与所述下拉节点电连接，所述下拉晶体管的第一极与所述上拉节点电连接，所述下拉晶体管的第二极与所述下拉电压端电连接；
    所述下拉控制电路分别与所述控制电压端、所述上拉节点和所述下拉节点电连接，配置为根据所述控制电压端提供的控制电压信号和所述上拉节点的电位，控制所述下拉节点的电位；
    所述信号提供单元配置为在所述触控阶段，通过控制所述控制电压信号的电位为无效电压，以使得所述下拉控制电路控制所述下拉节点的电位，从 而控制所述下拉晶体管关断。
  13. 如权利要求11所述的显示触控装置，其中，所述栅极驱动单元包括第一下拉节点、第二下拉节点、第一下拉电路和第二下拉电路；所述第一下拉电路包括第一下拉晶体管，所述第二下拉电路包括第二下拉晶体管，所述第一下拉晶体管的控制极与所述第一下拉节点电连接，所述第一下拉晶体管的第一极与所述上拉节点电连接，所述第一下拉晶体管的第二极与所述下拉电压端电连接；所述第二下拉晶体管的控制极与所述第二下拉节点电连接，所述第二下拉晶体管的第一极与所述上拉节点电连接，所述第二下拉晶体管的第二极与所述下拉电压端电连接；
    所述栅极驱动单元还包括第一控制电压端、第二控制电压端和下拉控制电路；所述下拉控制电路与所述第一控制电压端、所述第二控制电压端、所述上拉节点、所述第一下拉节点和所述第二下拉节点电连接，配置为根据所述第一控制电压端提供的第一控制电压信号和所述上拉节点的电位，控制所述第一下拉节点的电位，并根据所述第二控制电压端提供的第二控制电压信号和所述上拉节点的电位，控制所述第二下拉节点的电位；
    所述信号提供单元配置为在所述触控阶段，通过控制所述第一控制电压端提供的第一控制电压信号的电位为无效电压，以使得所述下拉控制电路控制所述第一下拉节点的电位，从而控制所述第一下拉晶体管关断，还配置为在所述触控阶段，通过控制所述第二控制电压端提供的第二控制电压信号的电位为无效电压，以使得所述下拉控制电路控制所述第二下拉节点的电位，从而控制所述第二下拉晶体管关断。
  14. 如权利要求13所述的显示触控装置，其中，所述显示触控装置的工作周期包括多个切换周期，所述切换周期包括第一切换时间段和第二切换时间段，所述信号提供单元还配置为在所述第一切换时间段，当所述显示触控装置工作于显示阶段时，控制所述第一控制电压信号的电位为有效电压，控制第二控制电压信号的电位为无效电压，并配置为在所述第二切换时间段，当所述显示触控装置工作于显示阶段时，控制所述第二控制电压信号的电位为有效电压，控制所述第一控制电压信号的电位为无效电压。
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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116027931B (zh) * 2023-03-28 2023-07-07 惠科股份有限公司 触控显示驱动电路、驱动方法及触控显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1705042A (zh) * 2004-05-31 2005-12-07 Lg.菲利浦Lcd株式会社 移位寄存器
US20160378232A1 (en) * 2015-06-25 2016-12-29 Innolux Corporation Image display systems and gate driving circuits
WO2017006815A1 (ja) * 2015-07-09 2017-01-12 シャープ株式会社 シフトレジスタ、それを備えた表示装置、およびシフトレジスタの駆動方法
CN107452425A (zh) * 2017-08-16 2017-12-08 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN108319385A (zh) * 2016-12-23 2018-07-24 鸿富锦精密工业（深圳）有限公司 移位寄存器及具有移位寄存器的触控显示装置
CN109491533A (zh) * 2017-09-11 2019-03-19 夏普株式会社 显示装置

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101953250B1 (ko) 2012-07-12 2019-02-28 엘지디스플레이 주식회사 터치 스크린 일체형 표시장치 및 그 구동 방법
KR102156767B1 (ko) 2013-12-23 2020-09-16 엘지디스플레이 주식회사 터치 센서를 갖는 표시장치
CN103996370B (zh) 2014-05-30 2017-01-25 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
KR102223438B1 (ko) * 2014-07-03 2021-03-05 엘지디스플레이 주식회사 터치스크린 패널 일체형 표시장치 및 표시패널
KR102225185B1 (ko) 2014-11-14 2021-03-09 엘지디스플레이 주식회사 게이트구동부 및 이를 포함하는 터치표시장치
CN104392699B (zh) * 2014-12-15 2018-05-01 合肥鑫晟光电科技有限公司 像素电路及其驱动方法、显示面板和显示装置
US9477345B2 (en) 2015-01-30 2016-10-25 Lg Display Co., Ltd. Display device, and device and method for driving the same
US9734783B2 (en) * 2015-03-19 2017-08-15 Apple Inc. Displays with high impedance gate driver circuitry
TWI563483B (en) * 2015-06-12 2016-12-21 Au Optronics Corp Touch display apparatus and shift register thereof
US10488961B2 (en) * 2015-07-17 2019-11-26 Innolux Corporation Gate driving circuit for driving a pixel array having a trigger circuit for receiving a touch sensing signal
CN105206237B (zh) * 2015-10-10 2018-04-27 武汉华星光电技术有限公司 应用于In Cell型触控显示面板的GOA电路
CN105206244B (zh) * 2015-10-29 2017-10-17 武汉华星光电技术有限公司 一种goa电路及液晶显示器
CN105427830A (zh) * 2016-01-12 2016-03-23 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN105589604B (zh) * 2016-03-08 2018-06-01 京东方科技集团股份有限公司 复位电路及其驱动方法、移位寄存器单元、栅极扫描电路
KR102563969B1 (ko) * 2016-05-30 2023-08-07 엘지디스플레이 주식회사 표시장치와 그 게이트 구동 회로
KR102539856B1 (ko) * 2016-07-28 2023-06-08 엘지디스플레이 주식회사 표시장치와 그 게이트 구동 회로
KR102490159B1 (ko) * 2016-10-31 2023-01-20 엘지디스플레이 주식회사 게이트 구동 회로와 이를 이용한 인셀 터치 센서를 갖는 표시장치
KR102586365B1 (ko) * 2016-11-30 2023-10-06 엘지디스플레이 주식회사 쉬프트 레지스터, 이를 포함한 영상 표시장치 및 그 구동방법
CN106531052A (zh) 2017-01-03 2017-03-22 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
CN106951123B (zh) * 2017-03-21 2019-08-20 京东方科技集团股份有限公司 触控驱动单元及其驱动方法、触控驱动电路、显示装置
CN109656397B (zh) * 2017-10-12 2022-04-12 群创光电股份有限公司 触控显示装置
KR102381884B1 (ko) * 2017-10-18 2022-03-31 엘지디스플레이 주식회사 디스플레이 장치
CN107731170B (zh) * 2017-10-31 2020-03-17 京东方科技集团股份有限公司 补偿模块、栅极驱动单元、电路及其驱动方法和显示装置
US10599242B2 (en) * 2017-10-31 2020-03-24 Wuhan China Star Optoelectronics Technology Co., Ltd. Single-type GOA circuit and display apparatus
KR102435943B1 (ko) * 2017-11-08 2022-08-23 엘지디스플레이 주식회사 게이트 구동회로 및 이를 포함하는 표시장치
KR102381885B1 (ko) * 2017-11-22 2022-03-31 엘지디스플레이 주식회사 디스플레이 장치
US10339887B1 (en) * 2017-12-08 2019-07-02 Wuhan China Star Optoelectronics Technology Co., Ltd. Gate driver on array circuit
CN108269541B (zh) * 2017-12-27 2019-09-20 南京中电熊猫平板显示科技有限公司 栅极扫描驱动电路
CN109256171B (zh) * 2018-11-22 2021-02-26 合肥京东方光电科技有限公司 移位寄存器单元、驱动方法、电路、显示面板及装置
CN109710113B (zh) 2019-03-07 2021-01-26 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动电路及其驱动方法、显示装置
CN109859670A (zh) 2019-03-28 2019-06-07 京东方科技集团股份有限公司 一种移位寄存器单元及其驱动方法、栅极驱动电路
CN111312177B (zh) * 2020-03-03 2021-04-02 武汉华星光电技术有限公司 Goa驱动电路、显示面板及显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1705042A (zh) * 2004-05-31 2005-12-07 Lg.菲利浦Lcd株式会社 移位寄存器
US20160378232A1 (en) * 2015-06-25 2016-12-29 Innolux Corporation Image display systems and gate driving circuits
WO2017006815A1 (ja) * 2015-07-09 2017-01-12 シャープ株式会社 シフトレジスタ、それを備えた表示装置、およびシフトレジスタの駆動方法
CN108319385A (zh) * 2016-12-23 2018-07-24 鸿富锦精密工业（深圳）有限公司 移位寄存器及具有移位寄存器的触控显示装置
CN107452425A (zh) * 2017-08-16 2017-12-08 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN107452425B (zh) * 2017-08-16 2021-02-26 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN109491533A (zh) * 2017-09-11 2019-03-19 夏普株式会社 显示装置

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