WO2022104558A1

WO2022104558A1 - Novel segmented word line and bit line scheme for 3d pcm to improve line integrity and prevent line toppling

Info

Publication number: WO2022104558A1
Application number: PCT/CN2020/129606
Authority: WO
Inventors: Jun Liu
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2020-11-18
Filing date: 2020-11-18
Publication date: 2022-05-27
Also published as: CN112543977A

Abstract

A three-dimensional memory structure including a plurality of memory cells (700, 900) is provided. The memory structure includes a plurality of bit lines coupled to the plurality of memory cells (700, 900). The plurality of memory cells (700, 900) are arranged in one or more cell arrays. Each of the plurality of bit lines includes multiple segments (610, 620). The memory structure further includes one or more connectors (630) electrically connecting the multiple segments (610, 620) of each respective bit line (600) of the plurality of bit lines such that the multiple segments (610, 620) extend through a length of a respective cell array of the plurality of cell arrays. Additionally or alternatively, the memory structure may further comprise word lines, and each of the word lines includes multiple segments (810, 820).

Description

[Title established by the ISA under Rule 37.2] NOVEL SEGMENTED WORD LINE AND BIT LINE SCHEME FOR 3D PCM TO IMPROVE LINE INTEGRITY AND PREVENT LINE TOPPLING

TECHNICAL FIELD

The present disclosure generally relates to three-dimensional electronic memories, and more particularly, to three-dimensional crosspoint memories with improved structural integrity and mechanical stability.

BACKGROUND

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As such, memory density for planar memory cells approaches an upper limit. A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells.

Phase-change memory (PCM) is a non-volatile solid-state memory technology that exploits reversible, thermally-assisted switching of phase-change materials like chalcogenide compounds such as GST (Germanium-Antimony-Tellurium) , between states with different electrical resistance. The fundamental storage unit (the “cell” ) can be programmed into a number of different states, or levels, which exhibit different resistance characteristics. Programmable cell-states can be used to represent different data values, permitting storage of information.

As memory cell size scales down and memory density scales up, aspect ratios of features tend to increase and free-standing dimensions tend to decrease. Fabrication of such free-standing, high aspect ratio structures may be challenging, and may also result in structures that lack structural integrity or are mechanically fragile. Thus, there is still a need for memory cells with structurally and mechanically strong features despite the small dimensions.

SUMMARY

The presently disclosed three-dimensional memory and method solves the problems of current state of the art, and provides many more benefits. In accordance with an aspect, disclosed and shown is a novel segmented bit line and/or word line scheme to improve line integrity and prevent line toppling. In the proposed novel segmented bit line and/or word line scheme, the narrow lines are broken into two equal segments, and connected through contacts to a metal strap in order to form an electrically connected single bit line and/or word line. Accordingly, the line length can be effectively reduced to one half and thus improve its integrity and reduce the possibility for line wiggling, bending or toppling.

In another aspect, a plurality of memory cells is arranged in one or more cell arrays. A plurality of bit lines are coupled to the plurality of memory cells, each bit line of the plurality of bit lines includes multiple segments. One or more connectors are electrically connecting the multiple segments of each respective bit line of the plurality of bit lines such that the multiple segments extend through a length of a respective cell array of the plurality of cell arrays.

In yet another aspect, a plurality of memory cells is arranged in one or more cell arrays. A plurality of word lines are coupled to the plurality of memory cells, each word line of the plurality of word lines includes multiple segments. One or more connectors are electrically connecting the multiple segments of each respective word line of the plurality of word lines such that the multiple segments extend through a width of a respective cell array of the plurality of cell arrays.

In still another aspect, a method of forming three-dimensional memory comprises providing a plurality of memory cells arranged in one or more cell arrays; providing a plurality of bit lines coupled to the plurality of memory cells, each bit line of the plurality of bit lines includes multiple bit line segments; and providing one or more bit line connectors electrically connecting the multiple bit line segments of each respective bit line such that the multiple bit line segments extend through a length of a respective cell array of the plurality of cell arrays.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects, features and advantages of the present disclosure will be further appreciated when considered with reference to the following description of exemplary embodiments and accompanying drawings, wherein like reference numerals represent like elements. In describing the exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be used for the sake of clarity. However, the aspects of the present disclosure are not intended to be limited to the specific terms used.

FIG. 1 is an isometric view of a section of three-dimensional crosspoint memory.

FIG. 2 is a plan view of section of a prior three-dimensional crosspoint memory.

FIGS. 3A and 3B are plan views of a section of prior three-dimensional crosspoint memory.

FIGS. 4A and 4B are plan views of a section of prior three-dimensional crosspoint memory.

FIGS. 5A and 5B are cross-sectional views of a section of prior three-dimensional crosspoint memory.

FIG. 6 is a plan view of a section of three-dimensional crosspoint memory according to an embodiment.

FIG. 7 is a cross-sectional view of the section of three-dimensional crosspoint memory according to the embodiment of FIG. 6.

FIG. 8 is a plan view of a section of three-dimensional crosspoint memory according to another embodiment.

FIG. 9 is a cross-sectional view of the section of three-dimensional crosspoint memory according to the embodiment of FIG. 8.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

It is noted that references in the specification to “one embodiment, ” “an embodiment, ” “an example embodiment, ” “some embodiments, ” and the like, merely indicate that the embodiment described may include a particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context.

It should be readily understood that the meaning of “on, ” “above, ” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer there between, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer there between (i.e., directly on something) .

Further, spatially relative terms, such as “beneath, ” “below, ” “lower, ” “above, ” “upper, ” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element (s) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The term “substrate” as used herein may refer to any workpiece on which formation or treatment of material layers is desired. Non-limiting examples include silicon, germanium, silica, sapphire, zinc oxide, silicon carbide, aluminum nitride, gallium nitride, Spinel, silicon on oxide, silicon carbide on oxide, glass, gallium nitride, indium nitride, aluminum nitride, glasses, combinations or alloys thereof, and other solid materials. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpattern. Furthermore, the substrate can include a wide array of semiconductor materials, including but not limited to silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

The term “horizontal” as used herein will be understood to be defined as a plane parallel to the plane or surface of the substrate, regardless of the orientation of the substrate. The term “vertical” will refer to a direction perpendicular to the horizontal as previously defined. Terms such as “above” , “below” , “bottom” , “top” , “side” (e.g. sidewall) , “higher” , “lower” , “upper” , “over” , and “under” , are defined with respect to the horizontal plane. The term “on” means there is direct contact between the elements. The term “above” will allow for intervening elements.

As used herein, a material (e.g. a dielectric material or an electrode material) will be considered to be “crystalline” if it exhibits greater than or equal to 30%crystallinity as measured by a technique such as x-ray diffraction (XRD) . Amorphous material is considered non-crystalline.

As used herein, the terms “first, ” “second, ” and other ordinals will be understood to provide differentiation only, rather than imposing any specific spatial or temporal order.

As used herein, the term “oxide” (of an element) will be understood to include additional components besides the element and oxygen, including but not limited to a dopant or alloy. As used herein, the term “nitride” (of an element) will be understood to include additional components besides the element and nitrogen, including but not limited to a dopant or alloy.

The present technology is applied in the field of three-dimensional memory. A generalized example of a three-dimensional (3D) memory is shown in FIG. 1. In particular, FIG. 1 is an isometric view of a section of three-dimensional crosspoint memory. The memory includes a first layer of memory cells 5 and a second layer of memory cells 10. Between the first layer of memory cells 5 and the second layer of memory cells 10 is a number of word lines 15 extending in a horizontal (X) direction. Above the first layer of memory cells 5 in a depth (Z) direction are a number of first bit lines 20 extending along a vertical (Y) direction, and below the second layer of memory cells 10 is a number of second bit lines 25 extending along the Y direction.

Further as shown in FIG. 1, the sequential structure of bit line, memory cell, word line, memory cell may be repeated along the Z direction to create a stacked configuration. In the example of FIG. 1, a first layer of the stack may include the first layer of memory cells 5, bit lines 20, and word lines 15, while a second layer of the stack may include the second layer of memory cells 10, the bit lines 25, and word lines 15. Thus, while the first layer of memory cells 5 and the second layer of memory cells 10 each have its respective set of

bit lines

20 and 25, the first layer of memory cells 5 and the second layer of memory cells 10 may share a same set of word lines 15. Although the example of FIG. 1 shows a 4-layer stack configuration, in other examples, the stacked configuration may include any number of memory cell layers and other elements. In any event, an individual memory cell in the structure may be accessed by selectively activating the word line and bit line corresponding to the cell.

In order to selectively activate the word lines and bit lines, the memory includes word line decoders and bit line decoders (not shown) . The word line decoders are coupled to the word lines by word line contacts (not shown) and are used to decode word line addresses such that a particular word line is activated when it is addressed. Similarly, the bit line decoders are coupled to the bit lines by bit line contacts (not shown) and are used to decode bit line addresses such that a particular bit line is activated when it is addressed. Thus, the stack configuration of memory may further include bit line contacts and decoders, and word line contacts and decoders for selectively activating the bit lines and word lines in the stack. For instance, the stack configuration may be arranged as arrays of elements, where each array includes a set of memory cells, and corresponding sets of bit lines, word lines, bit line and word line contacts, and bit line and word line decoders. The positioning of the word line decoders and contacts, and the bit line decoders and contacts are shown and discussed further in reference to FIG. 2.

FIG. 2 is a plan view of section of three-dimensional crosspoint memory of a prior configuration. The figure depicts the section as viewed along the Z (depth) direction. In this example, the stacked configuration is a 2-layer stack. The stacked configuration includes multiple arrays or blocks of memory cells, including two

top cell arrays

60 and 61 and two

bottom cell arrays

65 and 66. Although individual memory cells are not shown in FIG. 2, they are illustrated by FIG. 1, for example in the top arrays the memory cells may be arranged as the first layer of memory cells 5 shown in FIG. 1 and in the bottom arrays the memory cells may be arranged as the second layer of memory cells 10 shown in FIG. 1.

The section includes word lines and bit lines, word line and bit line contacts and word line and bit line decoders corresponding to the top cells and bottom cells. As shown, a number of word lines, e.g. word lines 30, extend in the X (horizontal) direction and corresponding to both the top cells and bottom cells. The section further includes a number of top cell bit lines, e.g., bit lines 35, extending along the Y (vertical) direction and corresponding to the top cell array of memory cells 60, and a number of bottom cell bit lines, e.g., bit lines 40, extending along the vertical direction and corresponding to the bottom cell array of memory cells 65. The word lines, top cell bit lines, and bottom cell bit lines are typically formed of a 20 nm /20 nm Line /Space (L/S) pattern and are formed on a silicon substrate. Moreover, the memory may employ complementary metal-oxide semiconductor (CMOS) technology.

The memory section of FIG. 2 includes a word line contact area 45, a top cell bit line contact area 50, and a bottom cell bit line contact area 55. The word line contact area 45 is elongated along the vertical direction, while the top cell bit line contact area 50 and bottom cell contact area 55 are elongated along the horizontal direction. The word line contact area 45 includes a multiple of word line contacts, e.g., contact 45a, shown as dots enclosed by the word line contact area 45. The top cell bit line contact area 50 includes a multiple of word line contacts, e.g., contact 50a, shown as dots enclosed by top cell bit line contact area 50. The bottom cell bit line contact area 55 includes a multiple of bottom cell bit line contacts, e.g., contact 55a, shown as dots enclosed by bottom cell bit line contact area 55. The word line contacts and bit line contacts are connected to the middle of the respective word lines and bit lines. Thus as shown, word line contact area 45 is positioned in the horizontal middle of word lines 40, bottom cell bit line contact area 55 is positioned in the vertical middle of the bottom cell bit lines 40, and top cell bit line contact area 50 is positioned in the vertical middle of the top cell bit lines 35.

The word line contact area 45 also includes a multiple of word line decoders (not shown) . The word line decoders generally conform to the word line contact area and generally extend along the vertical direction. The word line decoders couple to the word lines through the word line contacts. The top cell bit line contact area 50 also includes a multiple of top cell bit line decoders (not shown) . The top cell bit line decoders generally conform to the top cell bit line contact area 50 and generally extend along the horizontal direction. The top cell bit line decoders’ couple to the top cell bit lines through the top cell bit line contacts. The bottom cell bit line contact area 55 also includes a multiple of bottom cell bit line decoders (not shown) . The bottom cell bit line decoders generally conform to the bottom cell bit line contact area 55 and generally extend along the horizontal direction. The bottom cell bit line decoders’ couple to the bottom cell bit lines through the bottom cell bit line contacts.

FIGS. 3A and 3B further illustrate the relative positions of the word lines, bit lines, word line contacts, bit line contacts, word line decoders, and bit line decoders in a section of three-dimensional crosspoint memory of a prior configuration, such as the configuration of FIG. 2. FIG. 3A is a plan view of a section of a prior three-dimensional crosspoint memory. The figure depicts the section as viewed along the depth or Z direction. This example is a 2-layer stack configuration. The figure highlights a top cell array 60 extending from a top edge 70 to a bottom edge 71 and from a left edge 72 to a right edge 73, and a bottom cell array 65 extending from a top edge 74 to a bottom edge 75 and from left edge 76 to a right edge 77. Further as shown, top cell bit lines extend between the top edge 70 and the bottom edge 71, bottom cell bit lines extend between the top edge 74 and the bottom edge 75. Word lines extend between the left edge 72 and the right edge 73 for the top cell array 60, and between the

left edge

76 and 77 for the bottom cell array 65.

FIG. 3A further shows that the memory section includes a word line decoder section 80 that is arranged in a vertical stripe of area extending along the Y direction from the top edge 74 of the bottom cell array 65 to the bottom edge 75 of the bottom cell array 65. The word line decoder section 80 is positioned along a horizontal middle of the bottom cell array 65. The memory section also includes a top cell bit line decoder section 85 of the top cell array 60 that is split into two

portions

85a and 85b along the horizontal or X direction, and a bottom cell bit line decoder section 90 of the bottom cell array 65 that are split into two

portions

90a and 90b along the horizontal or X direction. The top cell bit line decoder section 85 is positioned along a vertical middle of the top cell array 60, while the bottom bit line decoder section 90 is positioned along a vertical middle of the bottom cell array 65.

FIG. 3B is the same plan view of the prior three-dimensional crosspoint memory as FIG. 3A with the exception that FIG. 3B is zoomed-in to enlarge portions of bottom cell array 60 and bottom cell array 65, and to highlight areas where contacts for word line and bit lines are provided. For instance, FIG. 3B shows that word line contact area 45 is positioned generally in the same area as the word line decoder section 80 along the vertical middle of the bottom cell array 65. Further, top cell bit line contact area 50 is positioned generally in the same area as the top cell bit line decoder section 85, and the bottom cell bit line contact area 55 is positioned generally in the same area as the bottom cell bit line decoder section 90. For purposes of clarity of presentation FIGS. 3A and 3B were described only with respect to the portions pertaining to the top cell array 60 and the bottom cell array 65, with the understanding that such discussion can be readily applied to the other portions of the figure, such as other cell arrays that were not highlighted/labeled.

FIGS. 4A and 4B illustrate example dimensions of bit lines or word lines in a section of three-dimensional crosspoint memory of a prior configuration, such as the configurations of FIGS. 2-3B. While FIG. 4A shows a schematic, FIG. 4B shows an example microscopy image of a fabricated structure. FIGS. 4A and 4B are plan views depicting bit lines or word lines as viewed along the depth (Z) direction. For instance, FIGS. 4A and 4B may show example bit lines from the memory section of FIGS. 3A-3B, since bit lines are shown extending along the vertical (Y) direction in FIGS. 3A-3B. The bit lines may be bottom cell bit lines or top cell bit lines. Word lines in the memory section of FIGS. 3A-3B may have similar configurations as the bit lines of FIGS. 4A and 4B.

Referring to FIG. 4A, in the schematic, bit lines 400 are each shown with a width “W” along the horizontal (X) direction and a length “L” along the vertical (Y) direction. For example, the length L may be a length of a cell array such as from top edge 74 to bottom edge 75 of bottom cell array 65. Further as shown, to decrease memory size and increase memory density, the aspect ratio (L/W) of the bit lines may be very large. The bit lines are spaced in tight pitch, with small spacing “d” between the bit lines 400. FIG. 4B shows an example transmission electron microscopy (TEM) image of fabricated bit lines 450. To increase memory density, features of FIG. 4B have dimensions on the order of nanometers. The example bit lines 450 have high aspect ratios, with length L’ much larger than width W’, and with spacing d’ between the fabricated bit lines 450. However, in practical situations, bit lines 450 may be fabricated using deposition techniques that involve depositing layers of materials on a substrate in sequence, and in some instance may also involve lithography techniques that etch patterns in materials using masks and photoresistive materials. As such, the fabricated bit lines 450 may not have substantially uniform width as the bit lines 400 in the schematic of FIG. 4A, and may not have substantially uniform spacing between them. Rather, due to the high aspect ratio and the small dimensions, the fabricated bit lines 450 have width W’ that vary in the range of 15nm-20nm, with spacing d’ between them that likewise vary within a range. These variations may affect the structural integrity and mechanical stability of the structures, which are further illustrated in FIGS. 5A and 5B.

FIGS. 5A and 5B further illustrate example dimensions of bit lines and word lines in a section of three-dimensional crosspoint memory of a prior configuration, such as the configuration of FIGS. 2-4B. While FIG. 5A shows a schematic, FIG. 5B shows an example TEM image of a fabricated structure. FIGS. 5A and 5B are cross-sectional views depicting bit lines and word lines as viewed along the horizontal (X) direction. For instance, FIGS. 5A and 5B may show example bit lines extending along the vertical (Y) direction, and word lines extending along the X direction. The bit lines and word lines may be configured similarly, as such, only one view along the horizontal direction is shown. Thus it may be understood that, if rotated to a view along the Y direction, FIGS. 5A and 5B may appear the same, except the structures labeled as bit lines would be word lines, and vice versa. Moreover, while the features described are particularly advantageous for multi-level cells, these features can also be applied to advantage in single-level cells in some embodiments.

Referring to FIG. 5A, bit lines, word lines, memory cells, and other features in a bottom cell may be formed as a stacked structure by depositing of layers of materials on a substrate. The stacked structure includes multiple stacks, such as stacks labeled as “A” and “B, ” arranged in an array. Each stack may include a respective bit line, a line of memory cells, and other features as described below. For instance, bit lines 400 extending along the Y direction (into the page) may be formed in a layer 501. Example materials for the layer 501 may include metal nitrides such as TiN, TiAlN, TaN, BN, metal oxide nitrides such as TiON, metal silicides such as PtSi, semiconductors such as silicon or germanium (with and without doping) , reduced metal oxides such as TiOx (x<2 indicates reduction) , metals such as W, Ni, Co, or carbon based materials.

Memory cells 500 may be formed in a different layer 503 below the bit lines 400 in the stacked structure. For example, a plurality of phase change memory (PCM) cells may be formed in the layer 503. Layer 503 may be made of phase-change materials like chalcogenide compounds, such as GST (Germanium-Antimony-Tellurium) . Further as shown, the memory cells 500 may be disposed between layers of

electrodes

502 and 504 or a-C layers in the stacked structure. The electrodes can be formed of any convenient electrically-conductive material, typically a metallic material (e.g. a pure metal or a metal compound, alloy or other mixture) or a doped semiconductor material such as silicon. Depending on the embodiment the electrode may be a carbon electrode or any other electrode know to one skilled in the art. Further as shown, a selector or ovonic threshold switch may be formed in a layer 505 disposed between

electrode layers

504 and 506 in the stacked structure.

Also shown in the stacked structure, layer 507 may be made of a material that functions as a conductor among other things. For example, layer 507 may be a tungsten based compound, or cobalt based compound. Depending on the embodiment, the conductor may be made of other materials that have conductive properties. Layer 507 may be configured to be connected to contacts, such as

bit line contacts

531, 532, 533. The bit line contacts 531-533 may be positioned within layer 508 in the stacked structure, which may be a substrate or may be a layer that includes word lines extending along the X direction.

FIG. 5A further illustrates that the stacked structure including bit lines, memory cells, electrodes, contacts, etc. are formed as stacks with a narrow width W. These narrow stacks are formed free-standing on the layer 508, with spacing d between them. Because of the narrow width W, the stacked structures may be more likely to wiggle, bend, or topple over, for instance, due to a vibration, movement, or mechanical stress/strain, etc. Thus as shown, when the stack A topples over, the connection with the contacts 533 may be broken or compromised, which may result in damage to the memory structure. Further because of the narrow width W, the surface areas that connect the free-standing structures with the bit contacts 531-533 are also small. The stacked structure thus leaves little room for error with respect to the relative positioning of each stack and the respective bit line contacts. Thus as shown for the stack B, inaccurate positioning of the stack B relative to the bit line contacts 532 may cause the bit line of the stack B to miss one or more connections to one or more bit line contacts, making some of the memory cells in stack B unusable.

FIG. 5B shows an example TEM image of a fabricated stacked structure. FIG. 5B highlights the bottom cell array 65. Within the bottom cell 65, fabricated bit lines 450 and fabricated PCM memory cells 550, as well as fabricated electrodes, selectors, contacts, etc. disposed in different layers. FIG. 5B further illustrates that, in practical conditions where the stacked structure is fabricated using techniques such as deposition and lithography, the width W’ of each stack may have variations, such as from 13 nm-22 nm as shown. As such, due to the small scale, a width of 13 nm instead of the desired 20 nm may correspond to almost a 50%variation. Likewise, spacing d’ in practical conditions may vary from 11 nm-59 nm as shown, a spacing of 59 nm instead of the desired 20 nm may correspond to a 300%variation. These variations may exacerbate the problems illustrated in FIG. 5A. For example, because a stack may be thinner in the middle along the length, the stack may be more likely to wiggle, bend, or topple over.

Thus, it has been recognized by the developers of the present technology that the prior configuration as exemplified in FIGS. 4A-5B lack structural integrity and mechanical stability as the feature size decreases. The developers thus provide the present technology in light of the drawbacks of the prior configuration.

FIGS. 6 and 7 illustrate example bit line structures in a section of three-dimensional crosspoint memory according to an embodiment. While FIG. 6 shows a plan view depicting bit line structures in a cell array as viewed along the depth (Z) direction, FIG. 7 shows a cross-sectional view depicting bit line structures as viewed along the horizontal (X) direction. In a multi-level memory structure, the bit lines may be in any level for activating memory cells in the respective level. Although not every feature in the memory may be shown in FIGS. 6 and 7, it may be understood that, unless otherwise described, the memory may include similar features as described with reference to FIGS. 1-5B, including bit line and word line decoders. The differences, such as those that improve the structural integrity and mechanical stability, are described further below.

Referring to FIG. 6, bit lines, such as bit line 600, are shown extending along the vertical (Y) direction. Further as shown, the bit lines each have a width W, with spacing d between them. However, instead of bit lines that extend through an entire length L, which may be the length of a cell array (such as from top edge 74 to bottom edge 75 of bottom cell array 65) ; the bit lines in FIG. 6 are segmented. Thus as shown, each bit line includes two segments, for example bit line 600 includes a first segment 610 and a second segment 620 extending end-to-end. The first segment 610 may have a length L1 smaller than L, and the second segment 620 may have a length L2 also smaller than L. Thus, bit lines in a cell array may be formed with segments extending only partially through the length of the cell array. The two

segments

610 and 620 may have lengths L1+L2 adding up to the length L, or may have lengths L1+L2 shorter than L. Thus, although a gap is shown between the

segments

610 and 620, in other examples there may not be a spacing or any gap between the

segments

610 and 620 may be minimal.

The

segments

610 and 620 are shown to have roughly equal dimensions. As such, both segments are reduced in length as compared to L by at least half, which may reduce the amount of stress/strain acting on each individual segment. Further as described below, where the segments are equal in length, bit line contacts may still be positioned along the middle of the bit lines. Positioning bit line contacts and/or bit line decoders equidistance from both ends of a corresponding bit line may increase data speed and energy efficiency, since neither end has a longer distance that requires more time for signals to travel. In other examples the

segments

610 and 620 may have different dimensions. For example, L1 of segment 610 may be smaller or greater than L2 of segment 620. The dimensions of the

segments

610 and 620 may be adjusted, for instance to accommodate different arrangements of bit line contacts, bit line decoders, word lines, word line contacts, word line decoders, etc. in the cell array.

The segments of each bit line are connected by a respective connector. For instance, the two

segments

610 and 620 of bit line 600 are electrically connected by a connector 630. For example, the connector 630 may be a conductive material, such as a metallic or alloy. With the electrical connection, the connector 630 effectively allows a bit line of length L to be formed from two

segments

610 and 620 each with a length smaller than L. In this regard, the connector 630 allow bit lines to be formed as segments each with a smaller aspect ratio as the aspect ratio of the resulting bit line. Since each bit line segment has a smaller aspect ratio, the segments are likely to have smaller variations in width W, thereby having greater structural integrity, and are subject to less stress/strain. As a result of the greater structural integrity and less strain/stress, the bit line segments are less likely to wiggle, bend, or topple over, and thus have greater mechanical stability. Further, the resulting bit line 600 still has a total length of L, thus the memory density of the memory cell array is not decreased as a result of shorter segments.

As shown, the connector 630 may have a length L3. In this example, the length L3 is shown to be larger than the space between the first segment 610 and the second segment 620. This allows there to be some overlapping regions 640 along the length in the Y direction between the connector 630 and the adjacent ends of the segments 610 and/or 620. The

segments

610 and 620 may be connected to the connector 630 at these overlapping regions 640. The length L3 may be adjusted, for example increasing L3 and the overlapping regions 640 may provide greater area for connecting to the

segments

610 and 620 and thus providing greater mechanical support to the

segments

610 and 620. On the other hand, decreasing length L3 and the overlapping regions 640 may save space and materials to further decrease memory size and increase memory density. Although L3 is shown as smaller than L, in other examples L3 may be equal or larger than L. Further, although the connector 630 is shown with same width W as the

bit line segments

610 and 620, in other examples the connector 630 may have different a different width as W, for instance a greater width to provide more mechanical support, or a smaller width to save space and materials.

Further as shown, the connectors are positioned between two ends of the respective bit lines. Where the first segment 610 and the second segment 620 are equal in length as shown, the connector 630 may be positioned along a vertical middle of the bit line 600. Where the first segment 610 and the second segment 620 are different in length, the connector 630 may be positioned offset from the vertical middle of the bit line 600. Positioning bit line contacts and/or bit line decoders equidistance from both ends of a corresponding bit line may increase data speed and energy efficiency, since neither end has a longer distance that requires more time for signals to travel. Nonetheless, the segments may be configured with different length, with the connector offset to provide more flexibility in design, such as for accommodating word lines, word line decoders, bit line decoders, etc.

In addition to increased structural integrity and mechanical stability, forming bit lines as segments may also allow memory size to be decreased or memory density to be increased. For instance, width W of the

bit line segments

610 and 620 may be reduced, but the

segments

610 and 620 may still have smaller aspect ratio than in the prior configuration of FIG. 5A. As an example, if L1 and L2 are each approximately 1/2*L, then as long as

segments

610 and 620 have widths that are more than 1/2*W,

segments

610 and 620 would have aspect ratios smaller than L/W. Thus, in some instances forming bit lines as shorter segments may allow the bit lines to have smaller widths, which may be spaced in even tighter pitch, resulting in decreased memory cell size and increased memory density.

Referring to FIG. 7, bit line 600 is shown extending along the vertical (Y) direction. This cross-sectional view further shows that the segmented bit lines according to the embodiment of FIG. 6 may be formed in a stacked structure. The stacked structure includes multiple stacks arranged in an array; each stack may include a respective bit line, a line of memory cells, and other features. As such, FIG. 7 shows a horizontal (X) cross-section of one such stack. In this stack, bit line 600 is formed in a layer 701; memory cells 700 may be formed in a different layer 703 and may be coupled to the bit line 600 to be activated. Further as shown, the stacked structure may include layers of electrodes, selectors/switches, contacts, etc., such as electrode layers 702, 704, 706, selector or switch layer 705, conductive layer 707, and a substrate layer 708. The layers 701-708 may be made of any appropriate material as described above for layers 501-508 with reference to FIG. 5A.

FIG. 7 further illustrates the segmented configuration of the bit line 600. As shown, bit line 600 is formed by the first segment 610 with length L1 and the second segment 620 with length L2, each smaller than total length L of bit line 600. Not only the bit lines are formed as segments, optionally other features in the stacked structure may also be formed in segmented sections. Accordingly, the memory cells 700 are formed in segmented sections corresponding to the

bit line segments

610 and 620. Likewise, the electrodes, selectors/switches, conductors, etc. are also formed in segmented sections in each of layers 702-707. As such, the entire free-standing stacked structure of FIG. 7 has smaller aspect ratio as compared to the free-standing stacked structure of FIG. 5A. The segmented configuration thus not only improves structural integrity and mechanical stability of the bit lines, but also other features in the stacked structure.

FIG. 7 illustrates how the

bit line segments

610 and 620 are connected by the connector 630. As shown, the connector 630 may be provided in the substrate layer 708. However, instead of one bit line contact for the bit line 600, each bit line segment may have a respective bit line contact. For example, the first segment 610 is connected by a first bit line contact 710 to the connector 630, and the second segment 620 is connected by a second bit line contact 720 to the connector 630. Although the first bit line contact 710 is shown connected near an end of the first segment 610 and the second bit line contact 720 is shown to be connected near an end of the second segment 620 adjacent to the first segment 610, in other examples the

bit line contacts

710 and 720 may be connected farther away from the ends of the segments. Further, although the connector 630 is shown to be disposed in a plane below the

bit line contacts

710 and 720, in other examples the connector 630 may be disposed between the

bit line contacts

710 and 720 in the same plane.

Still other variations are possible. For instance, although the example bit lines of FIGS. 6 and 7 each include two segments, in other examples the bit lines may each include more than two segments. For example, each bit line may have three segments connected to two connectors, where the first segment may have a first bit line contact connected to a first connector, the second segment may have a second bit line contact connected to the first connector and a third bit line contact connected to a second connector, and the third segment may have a fourth bit line contact connected to the second connector. Further, although the example shows one connector connecting two segments, in other examples one connector may connect multiple segments, or multiple connectors may be provided between two segments, etc.

FIGS. 8 and 9 illustrate example word line structures in a section of three-dimensional crosspoint memory of according to an embodiment. Word lines in the memory section of FIGS. 8 and 9 may have similar configurations as the bit lines of FIGS. 6 and 7. While FIG. 8 shows a plan view depicting word line structures as viewed along the depth (Z) direction, FIG. 9 shows a cross-sectional view depicting word line structures as viewed along the vertical (Y) direction. In a multi-level memory structure, the word lines may be in any layer for activating a respective layer of memory cells. Although not every feature in the memory may be shown in FIGS. 8 and 9, it may be understood that, unless otherwise described, the memory may include similar features as described with reference to FIGS. 1-5B, including bit line and word line decoders. The differences, such as those that improve the structural integrity and mechanical stability, are described further below.

Referring to FIG. 8, word lines, such as word line 800, are shown extending along the horizontal (X) direction. Further as shown, the word lines each have a width W5, with spacing d5 between them. However, instead of word lines that extend through an entire length L5, which may be the width of a cell array (such as from left edge 76 to right edge 77 of bottom cell array 65) , the word lines are segmented. Thus as shown, each word line includes two segments, for example word line 800 includes a first segment 810 and a second segment 820 extending end-to-end. The first segment 810 may have a length L6 smaller than L5, and the second segment 820 may have a length L7 also smaller than L5. Thus, word lines in a cell array may be formed with segments extending only partially through the width of the cell array. The two

segments

810 and 820 may have lengths L6+L7 adding up to the length L5, or may have lengths L6+L7 shorter than L5. Thus, although a gap is shown between the

segments

810 and 820, in other examples there may not be a spacing or any gap between the

segments

810 and 820 may be minimal.

Further, the

segments

810 and 820 are shown to have roughly equal dimensions. As such, both segments are reduced in length as compared to L5 by at least half, which may reduce the amount of stress/strain acting on each individual segment. Further as described below, word line contacts may still be positioned along the middle of the word lines. Positioning word line contacts and/or word line decoders equidistance from both ends of a corresponding word line may increase data speed and energy efficiency, since neither end has a longer distance that requires more time for signals to travel. In other examples the

segments

810 and 820 may have different dimensions. For example, L6 of segment 810 may be greater or smaller than L7 of segment 820. Dimensions of the

segments

810 and 820 may be adjusted, for instance to accommodate different arrangements of bit line contacts, bit line decoders, word line decoders, etc. in the cell array.

The segments of each word line are connected by a respective connector. For instance, the two

segments

810 and 820 of word line 800 are electrically connected by a connector 830. For example, the connector 830 may be a conductive material, such as a metallic or alloy. With the electrical connection, the connector 830 effectively allows a word line of length L5 to be formed from two

segments

810 and 820 each with a length smaller than L5. In this regard, the connector 830 allows word lines to be formed as segments each with a smaller aspect ratio as the aspect ratio of the resulting word line. Since each word line segment has a smaller aspect ratio, the segments are likely to have smaller variations in width W5, thereby having greater structural integrity, and are subject to less stress/strain. As a result of the greater structural integrity and less strain/stress, the word line segments are less likely to wiggle, bend, or topple over, and thus have greater mechanical stability. Further, the resulting word line 800 still has a total length of L5, thus the memory density of the memory cell array is not decreased as a result of shorter segments.

As shown, the connector 830 may have a length L8. In this example, the length L8 is shown to be larger than the space between the first segment 810 and the second segment 820. This allows there to be some overlapping regions 840 along the length in the X direction between the connector 830 and the adjacent ends of the segments 810 and/or 820. The

segments

810 and 820 may be connected to the connector 830 at these overlapping regions 840. The length L8 may be adjusted, for example increasing L8 and the overlapping regions 840 may provide greater area for connecting to the

segments

810 and 820 and thus providing greater mechanical support to the

segments

810 and 820. On the other hand, decreasing length L8 and the overlapping regions 840 may save space and materials to further decrease memory size and increase memory density. Although L8 is shown as smaller than L5, in other examples L8 may be equal or larger than L5. Further, although the connector 830 is shown with same width W5 as the

word line segments

810 and 820, in other examples the connector 830 may have a width different from W5, for instance a greater width to provide more mechanical support, or a smaller width to save space and materials.

Further as shown, the connectors are positioned between two ends of the respective word lines. Where the first segment 810 and the second segment 820 are equal in length as shown, the connector 830 is positioned along a horizontal middle of the word line 800. Where the first segment 810 and the second segment 820 are different in length, the connector 830 may be positioned offset from the horizontal middle of the word line 800. Positioning word line contacts and/or word line decoders equidistance from both ends of a corresponding word line may increase data speed and energy efficiency, since neither end has a longer distance that requires more time for signals to travel. Nonetheless, the segments may be configured with different length, with the connector offset to provide more flexibility in design, such as for accommodating bit lines, bit line decoders, word line decoders, etc.

In addition to increased structural integrity and mechanical stability, forming word lines as segments may also allow memory size to be decreased or memory density to be increased. For instance, width W5 of the

word line segments

810 and 820 may be reduced, but the

segments

810 and 820 may still have smaller aspect ratio than in the prior configuration of FIG. 5A. As an example, if L6 and L7 are each approximately 1/2*L5, then as long as

segments

810 and 820 have widths that are more than 1/2*W5,

segments

810 and 820 would have aspect ratios smaller than L5/W5. Thus, in some instances forming word lines as shorter segments may allow the word lines to have smaller widths, which may be spaced in even tighter pitch, resulting in decreased memory cell size and increased memory density.

Referring to FIG. 9, word line 800 is shown extending along the horizontal (X) direction. This cross-sectional view further shows that the segmented word lines according to the embodiment of FIG. 8 may be formed in a stacked structure. The stacked structure includes multiple stacks arranged in an array; each stack may include a respective word line, a line of memory cells, and other features. As such, FIG. 9 shows a vertical (Y) cross-section of one such stack. In this stack, word line 800 is formed in a layer 901; memory cells 900 may be formed in a different layer 903 and may be coupled to the word line 800 to be activated. Further as shown, the stacked structure may include layers of electrodes, selectors/switches, contacts, etc., such as electrode layers 802, 804, 806, selector or switch layer 805, conductive layer 807, and a substrate layer 808. The layers 801-808 may be made of any appropriate material as described above for layers 501-508 with reference to FIG. 5A.

FIG. 9 further illustrates the segmented configuration of the word line 800. As shown, word line 800 is formed by the first segment 810 with length L6 and the second segment 820 with length L7, each smaller than total length L5 of word line 800. Not only the word lines are formed as segments, other features in the stacked structure may also be formed into segmented sections. Accordingly, the memory cells 900 are formed in segmented sections corresponding to the

word line segments

810 and 820. Likewise, the electrodes, selectors/switches, conductors, etc. are also formed in segmented sections in each of layers 802-807. As such, the entire free-standing stacked structure of FIG. 9 has smaller aspect ratio as compared to the free-standing stacked structure of FIG. 5A. The segmented configuration thus not only improves structural integrity and mechanical stability of the word lines, but also other features in the stacked structure.

FIG. 9 illustrates how the

word line segments

810 and 820 are connected by the connector 830. As shown, the connector 830 may be provided in the substrate layer 808. However, instead of one word line contact for the word line 800, each word line segment may have a respective word line contact. For example, the first segment 810 is connected by a first word line contact 910 to the connector 830, and the second segment 820 is connected by a second word line contact 920 to the connector 830. Although the first word line contact 910 is shown connected near an end of the first segment 810 and the second word line contact 920 is shown to be connected near an end of the second segment 820 adjacent to the first segment 810, in other examples the

word line contacts

910 and 920 may be connected farther away from the ends of the segments. Further, although the connector 830 is shown to be disposed in a plane below the

word line contacts

910 and 920, in other examples the connector 830 may be disposed between the

word line contacts

810 and 820 in the same plane.

Still other variations are possible. For instance, although the example word lines of FIGS. 8 and 9 each include two segments, in other examples the word lines may each include more than two segments. For example, each word line may have three segments connected to two connectors, where the first segment may have a first word line contact connected to a first connector, the second segment may have a second word line contact connected to the first connector and a third word line contact connected to a second connector, and the third segment may have a fourth word line contact connected to the second connector. Further, although the example shows one connector connecting two segments, in other examples one connector may connect multiple segments, or multiple connectors may be provided between two segments, etc.

Although the embodiment of FIGS. 6 and 7 and the embodiment of FIGS. 8 and 9 are shown as separate, any combination may be possible. As some examples, a memory structure may be formed with only the bit lines being segmented; only the word lines are segmented, or both the word lines and bit lines being segmented. Further, a memory structure may have bit lines and word lines segmented in a similar way, or the bit lines and word lines may be segmented in different ways. As some examples, the bit lines may be segmented into equal length segments, but the word lines may be segmented into segments of different lengths, the bit lines may be segmented into two segments, the word lines may be segmented into three segments, etc. Still further, in a multi-level memory structure bit lines and/or word lines may be segmented in some levels, but not segmented in other levels, or may be segmented in different manners in the different levels.

Most of the foregoing alternative examples are not mutually exclusive, but may be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features discussed above may be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined by the claims. As an example, the preceding operations do not have to be performed in the precise order described above. Rather, various steps can be handled in a different order, such as reversed, or simultaneously. Steps can also be omitted unless otherwise stated. In addition, the provision of the examples described herein, as well as clauses phrased as "such as, " "including" and the like, should not be interpreted as limiting the subject matter of the claims to the specific examples; rather, the examples are intended to illustrate only one of many possible embodiments. Further, the same reference numbers in different drawings may identify the same or similar elements.

Although the present disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

A three-dimensional memory comprising:

a plurality of memory cells arranged in one or more cell arrays;

a plurality of bit lines coupled to the plurality of memory cells, each bit line of the plurality of bit lines includes multiple segments; and

one or more connectors electrically connecting the multiple segments of each respective bit line of the plurality of bit lines such that the multiple segments extend through a length of a respective cell array of the plurality of cell arrays.
The three-dimensional memory according to claim 1, further comprising:

at least one bit line contact connecting each respective segment of a respective bit line to the one more connectors.
The three-dimensional memory according to claim 1, wherein the plurality of memory cells are arranged in segmented sections corresponding to the multiple segments of the plurality of bit lines.
The three-dimensional memory according to claim 1, wherein each of the plurality of bit lines includes a first segment and a second segment electrically connected to each other by one connector.
The three-dimensional memory according to claim 4, wherein the first segment is connected to the connector via a first bit line contact and the second segment is connected to the connector via a second bit line contact, and wherein the connector, the first bit line contact, and the second bit line contact are positioned along a middle of a respective bit line.
A method of forming a three-dimensional memory comprising:

providing a plurality of memory cells arranged in one or more cell arrays;

providing a plurality of bit lines coupled to the plurality of memory cells, each bit line of the plurality of bit lines includes multiple bit line segments; and

providing one or more bit line connectors electrically connecting the multiple bit line segments of each respective bit line wherein the multiple bit line segments extend through a length of a respective cell array of the plurality of cell arrays.
The method according to claim 6, further comprising:

providing at least one bit line contact connecting each respective bit line segment of a respective bit line to the one more bit line connectors.
The method according to claim 6, further comprising:

arranging the plurality of memory cells in segmented sections corresponding to the multiple bit line segments of the plurality of bit lines.
The method according to claim 6, further comprising:

providing a plurality of word lines coupled to the plurality of memory cells, each word line of the plurality of word lines includes multiple word line segments; and

providing one or more word line connectors electrically connecting the multiple word line segments of each respective word line such that the multiple word line segments extend through a width of a respective cell array of the plurality of cell arrays.
The method according to claim 9, further comprising:

providing at least one word line contact connecting each respective word line segment of a respective word line to the one more word line connectors.
A three-dimensional memory comprising:

a plurality of memory cells arranged in one or more cell arrays;

a plurality of word lines coupled to the plurality of memory cells, each word line of the plurality of word lines includes multiple segments; and

one or more connectors electrically connecting the multiple segments of each respective word line of the plurality of word lines such that the multiple segments extend through a length of a respective cell array of the plurality of cell arrays.
The three-dimensional memory according to claim 11, further comprising:

at least one word line contact connecting each respective segment of a respective word line to the one more connectors.
The three-dimensional memory according to claim 11, wherein the plurality of memory cells are arranged in segmented sections corresponding to the multiple segments of the plurality of word lines.
The three-dimensional memory according to claim 11, wherein each of the plurality of word lines includes a first segment and a second segment electrically connected to each other by one connector.
The three-dimensional memory according to claim 14, wherein the first segment is connected to the connector via a first word line contact and the second segment is connected to the connector via a second word line contact, and wherein the connector, the first word line contact, and the second word line contact are positioned along a middle of a respective word line.