WO2022144781A1

WO2022144781A1 - Compact layout of a plurality of field effect transistor logic cells

Info

Publication number: WO2022144781A1
Application number: PCT/IB2021/062401
Authority: WO
Inventors: Lior Dagan
Original assignee: Lior Dagan
Priority date: 2020-12-30
Filing date: 2021-12-28
Publication date: 2022-07-07

Abstract

A layout of a plurality of logic cells is provided. The layout of plurality of logic cells includes a first logic cell having at least an input and an output, the first logic cell having at least an N-type field effect transistor (FET) and at least a P-type FET; a second logic cell having at least one input and an output, the second logic cell having at least an N-type FET and at least a P-type FET, wherein the at least one input of the second logic cell is electrically connected to the output of the first logic cell; and a separation circuit adapted to operate at an off condition to provide a separation between the first logic cell and the second logic cell, and having a drain port of the separation circuit electrically connected to the output of the first logic circuit.

Description

COMPACT LAYOUT OF A PLURALITY OF FIELD EFFECT TRANSISTOR LOGIC CELLS

CROSS-REFERENCE TO RELATED APPLICATIONS

[001] This application claims the benefit of U.S. Provisional Application No. 63/131 ,947 filed on December 30, 2020, the contents of which are hereby incorporated by reference.

TECHNICAL FIELD

[002] The present disclosure generally relates to semiconductor integrated circuits (ICs) and more particularly to compact designs of certain logic circuit building blocks that includes such ICs.

BACKGROUND

[003] Modem semiconductor integrated circuits (ICs) of very large-scale integration (VLSI) employ advanced manufacturing technologies. Most of the advance is in the reduction of feature size of gate width of the metal-oxide semiconductor field-effect transistor (MOSFET) gate down from the micron to the nanometer range, and fin field-effect transistor (FinFET). While feature size can be driven smaller, gaps between different circuits need to be maintained to avoid electrical impacts on the integrity of the structure. That is because as the feature size decreases, the electrical field increase. Even with a reduction in voltage, it is far from the reduction achieved in the feature size. As a result, the requirement of a gap or an exclusion zone impacts the overall size of a logic circuit, and in particular when certain combinations of logic gates are necessary.

[004] Fig. 1 shows a schematic diagram of a first conventional logic circuit 100 having a NAND gate 110 connected to a NOT gate 120. This circuit may be implemented in a variety of manufacturing technologies including planar MOSFET as well as FinFET. A first conventional layout 200 in a FinFET technology of such a first logic circuit 100, is shown in Fig. 2.

[005] The first layout 200 is partitioned into two areas, an N-area 210 and a P-area 220. In the N-area 210 FinFETs that are NMOSTs (i.e., N-type FETs) are implemented, while in the P-area 220, FinFETs that are PMOSTs (i.e., P-type FETs) are implemented. The input A of the NAND gate 110 includes the gate 240-1 (of an N-type FinFET) and the gate 270-

1 (of a P-type FinFET). These two gates are electrically connected (not shown), for example, by a metal connecting layer. Similarly, the input B of the NAND gate 110 includes the gate 240-2 (of an N-type FinFET) and the gate 270-2 (of a P-type FinFET). These two gates are electrically connected (not shown), for example, by a metal connecting layer.

[006] In the example shown in Fig. 2, the gate A 240-1 for the N-type FinFET extends over a diffusion area that extends between 250-1 and 250-2, while the gate A 270-1 for the P- type FinFET extends over a diffusion area that extends between 280-1 and 280-2. The gate B 240-2 for the N-type FinFET extends over a diffusion area that extends between 250-2 and 250-3, while the gate B 270-2 for the P-type FinFET extends over a diffusion area that extends between 280-2 and 280-3. Dummy gates 230-1 , 230-2, 260-1 , and 260-

2 bound the NAND gate 110 according to the design rules of the FinFET technology thereby providing separation from other logic circuits. A metal path connects the drains 280-2 of the P-Type transistors to the drain 250-3 of the N-type transistor formed by the gate B. The metal connector 290-1 is then used to connect to the input of the NOT gate (or inverter) 120.

[007] The NOT gate 120, also implemented according to the principals of the FinFET technology includes an N-type FinFET formed by gate 240-3 that extends over a diffusion layer that extends from 250-4 to 250-5. The NOT gate 120 includes a P-type FinFET formed by gate 270-3 that extends over a diffusion layer that extends from 280-4 to 280- 5. Dummy gates 230-3, 230-4, 260-3, and 260-4 bound the NOT gate 120 according to the design rules of the FinFET technology thereby providing separation from other logic circuits.

[008] The gates 240-3 and 270-3 are connected by a metal connection 290-1 that connects the NOT gate 120 to the output of the NAND gate 110. The diffusion 250-5 and 280-5 are electrically connected by metal connector 290-2 that also forms the output of the NOT gate 120. According to the design rules of the FinFET technology a minimum GAP between the NAND gate 110 and the NOT gate 120 is required. The requirement for the dummy gates 230 in FinFET technology is described, for example, in Figure 3 of Choi et al. “14 nm FinFET Stress Engineering with Epitaxial SiGe Source/Drain” published in 2012 International Silicon-Germanium Technology and Device Meeting (ISTDM).

[009] In yet another example, a schematic diagram of a second conventional logic circuit 500 is shown in Fig. 5. A NAND gate 510 having inputs A and B has its output connected to an input of a NOR gate 520. The NOR gate 520 further has another input C. The output of the NOR gate 520 is connected to the input of a NOT gate 530. The second conventional logic circuit 500 may be commonly found and requires a third layout 600 shown in Fig. 6.

[0010] The NAND gate 510 includes dummy gates 630-1 and 630-2 for the N-type gates 640- 1 (input A) and 640-2 (input B) formed over a diffusion layer that extends from 650-1 through 650-2 to 650-3. The NAND gate 510 further includes dummy gates 660-1 and 660-2 for the P-type gates 670-1 (input A) and 670-2 (input B) formed over a diffusion layer that extends from 680-1 through 680-2 to 680-3. An electrical connection 690-1 connects the serially connected N-gates 640-1 and 640-2 to the parallelly connected gates 670-1 and 670-2 extending the electrical connection to gates 640-3 and 670-3 of the NOR gate 520. All N-type gates are formed in the N-area 610 and all the P-type gates are formed in the P-area 620. The NOR gate 520 includes of dummy gates 630-3 and 630-4 between which gates of N-type transistors 640-3 and 640-4 (input C) are formed over a diffusion layer that extends from 650-4 through 650-5 and 650-6.

[0011] Similarly, in the P-area 620, the p-type transistors are formed for the NOR gate 520 between dummy gates 660-3 and 660-4. Therebetween gates of P-type transistors 670- 3 and 670-4 (input C) are formed over a diffusion layer that extends from 680-4 through 680-5 and 680-6. An electrical connection 690-2 connects the parallelly connected N- gates 640-3 and 640-4 to the serially connected gates 670-3 and 670-4 extending the electrical connection to gates 640-5 and 670-5 of the NOT gate 530.

[0012] The NOT gate 530 includes dummy gates 630-5 and 630-6 formed in the N-Area 610, therebetween is formed the gate 640-5, which is the input of NOT gate 530, and formed over a diffusion layer extending from 650-7 through 650-8. Furthermore, the NOT gate 530 includes dummy gate 660-5 and 660-6 formed in the P-Area 620, therebetween is formed the gate 670-5, which is the input of NOT gate 530, and formed over a diffusion layer extending from 680-7 through 680-8. An electrical connection 690-3 connects the diffusion 650-8 and 680-8 as the output of the NOT 530. It has been identified that in addition to the gates in the logic circuit, there is a required GAP area between the NAND gate 510 and the NOR gate 520 and between the NOR gate 520 and the NOT gate 530 that further increases the area of this particular configuration of cells in a FinFET implementation. The diffusion areas 650-1 , 650-4, 650-6 and 650-7 are electrically connected to a voltage source source (VSS). Further the diffusion areas 680-1 , 680-3, 680-4 and 680-7 are electrically connected to a voltage drain drain (VDD). In the case of a planar MOS implementation, the dummy gates 630 and 660 may be eliminated. It should be noted that not all connections are shown herein, for example gates 640-1 (input A) and gate 670-1 (input A) are electrically connected, however this is not shown herein as it is not necessary for appreciating the operation of the prior art. This is true for similar other connections.

[0013] It should be noted that other than the dummy gates 230 and 260 shown in Fig. 2 as well as dummy gates 630 and 660 shown in Fig. 6, a planar MOSFET technology would use practically the same layout principals. That is, in the planar MOSFET, no dummy gates are needed, but the minimum GAP is nevertheless required. To this end, there is a significant overhead in at least certain circuit designs that commonly appear in the design of logic circuits that cause these circuits to consume a larger area due to at least the requirement of the GAP (e.g., in planar MOSFET and FinFET technologies) and the use of dummy gates (e.g., in the case of the FinFET technology).

[0014] It would therefore be advantageous to provide solutions that over comes the limitations noted above.

SUMMARY

[0015] A summary of several example embodiments of the disclosure follows. This summary is provided for the convenience of the reader to provide a basic understanding of such embodiments and does not wholly define the breadth of the disclosure. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later. For convenience, the term “some embodiments” or “certain embodiments” may be used herein to refer to a single embodiment or multiple embodiments of the disclosure.

[0016] Certain embodiments disclosed herein include a layout of a plurality of logic cells. The layout of plurality of logic cells comprises: a first logic cell having at least an input and an output, the first logic cell having at least an N-type field effect transistor (FET) and at least a P-type FET; a second logic cell having at least one input and an output, the second logic cell having at least an N-type FET and at least a P-type FET, wherein the at least one input of the second logic cell is electrically connected to the output of the first logic cell; and a separation circuit adapted to operate at an off condition to provide a separation between the first logic cell and the second logic cell, and having a drain port of the separation circuit electrically connected to the output of the first logic circuit.

[0017] Certain embodiments disclosed herein also include an integrated circuit, comprising: a first logic cell having at least an input and an output, the first logic cell having at least an N-type field effect transistor (FET) and at least a P-type FET ; a second logic cell having at least one input and an output, the second logic cell having at least an N-type FET and at least a P-type FET, wherein the at least one input of the second logic cell is electrically connected to the output of the first logic cell; and a separation circuit adapted to operate at an off condition to provide a separation between the first logic cell and the second logic cell, and having a drain port of the separation circuit electrically connected to the output of the first logic circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The subject matter disclosed herein is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the disclosed embodiments will be apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0019] Figure 1 is a schematic diagram of a first conventional logic circuit of a NAND gate connected to a NOT gate.

[0020] Figure 2 is a schematic diagram of a first conventional layout of a fin field-effect transistor (FinFET) implementation of the first logic circuit. [0021] Figure 3 is a schematic diagram of a second layout of a FinFET implementation of the first logic circuit according to an embodiment.

[0022] Figure 4 is a schematic diagram of an equivalent circuit of the first logic circuit according to an embodiment.

[0023] Figure 5 is a schematic diagram of a second conventional logic circuit including a NAND gate connected to an input of a NOR gate, which is connected to a NOT gate.

[0024] Figure 6 is a schematic diagram of a third conventional layout of a FinFET implementation of the second logic circuit.

[0025] Figure 7 is a schematic diagram of a fourth layout of a FinFET implementation of the second logic circuit according to an embodiment.

DETAILED DESCRIPTION

[0026] The embodiments disclosed by the disclosure are only examples of the many possible advantageous uses and implementations of the innovative teachings presented herein. In general, statements made in the specification of the present application do not necessarily limit any of the various claimed disclosures. Moreover, some statements may apply to some inventive features but not to others. In general, unless otherwise indicated, singular elements may be in plural and vice versa with no loss of generality. In the drawings, like numerals refer to like parts through several views.

[0027] Advantages of small feature sizes available in today’s semiconductor technologies cannot be taken into full advantage. The reason for that is that there are minimum separation requirements that must be adhered to according to various chip design rules. This is of particular interest when separation, or exclusion zones, of very large-scale integration (VLSI) circuits, and specifically logic gates, are concerned. By employing a separation circuit comprising properly configured gates between logic cells, such gates being of PMOS and NMOS type gates, it is possible to take advantage of their small feature sizes (e.g., 12-18 nanometers) and thereby reducing the area of the logic cell without compromising the performance of the logic cell, as well as the circuits it is part of. The separation circuit is added instead of gaps or exclusion zones thereby providing a reduced size for certain logic circuits, and in particular when such logic circuits are integrated into an integrated circuit (IC) device. [0028] Fig. 3 is an example layout 300 of a FinFET implementation of the logic circuit 100 (Fig. 1) of a NAND gate 110 connected to a NOT gate 120 according to an embodiment. In order to properly appreciate the teachings herein further reference is made to Fig. 4 that depicts an example equivalent circuit 400 of the layout of the logic circuit 300 of the NAND gate 110 connected to the NOT gate 120. In an embodiment, dummy gates 230- 2, 230-3, 260-2 and 260-3, as well as the GAP are replaced by a separation circuit 410 (see Fig. 4) that may include: a) an N-type FET that includes gate X 340-3 that extends over diffusion 350-3 through 350-4; and b) a P-type FET that includes gate Y 370-3 that extends over diffusion 380-3 through 380-4.

[0029] The diffusion area 350-4 is electrically connected to VSS (not shown), while diffusion areas 380-3 and 380-4 are electrically connected to VDD (not shown). The gate X 340-3 is connected to VSS, and the gate Y 370-3 is connected to VDD. As a result, in comparison to the equivalent circuit in the conventional FinFET technology shown in Fig. 2, the area of two dummy gates, e.g., dummy gates 230-3 and 260-3, one for each polarity, and the GAP area required between the layout of the NAND gate 110 and the NOT gate 120 are saved. More particularly, elimination of such circuit features may allow reduction of overall size of the logic circuit. In an embodiment, supplies to the gate X 340- 3 and gate Y 370-3 may be configured such that ensures that the respective FETs are in their OFF position. While VSS and VDD are suggested respectively, this is not required, and in some embodiments, these gates may be connected through a desired supply circuit as long as the desired result of the state of the FET is achieved.

[0030] Fig. 7 depicts an example fourth layout 700 of a FinFET implementation of the second logic circuit 500 (Fig. 5) according to an embodiment. In an embodiment, the fourth layout 700 may be implemented as an equivalent circuit or an integrated circuit. According to principles of the disclosed embodiment a diffusion layer 750 (750-1 through 750-7) extends within the N-area 710 between two dummy gates 730-1 and 730-2. Over the diffusion layer 750 there are provided gate 740-1 (input A) and gate 740-2 (input B) forming the N-type transistors of NAND 510.

[0031] Further, over the diffusion layer 750. there are provided gate 740-4 (connecting the output of NAND 510 to an input of NOR 520) and gate 740-5 (input C) forming the N-type transistors of NOR 520. Gate 740-6 extending over diffusion area 750 forms the N-type transistor of NOT 530. Likewise, P-type transistors of the NAND 510, NOR 520 and NOT 530 are formed over the diffusion area 780 (780-1 through 780-7), within the P-area 720 and between dummy gates 760-1 and 760-2. Over the diffusion layer 780 there are provided gate 770-1 (input A) and gate 770-2 (input B) forming the P-type transistors of NAND 510. Further, over the diffusion layer 780 there are provided gate 770-4 (connecting the output of NAND 510 to an input of NOR 520) and gate 770-3 (input C) forming the P-type transistors of NOR 520. Gate 770-6 extending over diffusion area 780 forms the P-type transistor of NOT 530. In order to provide the required separation for proper operation of the series of logic gates 510, 520, and 530, a first separation gate X 740-3 is formed over diffusion layer 750 and is always OFF, i.e. , connected to ground or VSS.

[0032] A second separation gate Y 770-5 is formed over diffusion later 780 and is always OFF, i.e., connected to supply or VDD. These gates are needed to stop conduction through the respective diffusion layers. Diffusion areas 750-1 , 750-4, and 750-6 are connected to VSS. Diffusion areas 780-1 , 780-3 and 780-6 are connected to VDD. An electrical connection 790-1 (typically a metal layer) connects in series N-type transistors 740-1 and 740-2 from diffusion layer 750-3, and further connects P-type transistors 770- 1 and 770-2 in parallel from diffusion layer 780-2.

[0033] The electrical connection 790-1 extends to gates 740-4 and 770-4 to connect the output of NAND 510 to an input of NOR 520. A second electrical connection 790-2 connects in parallel gates 740-4 and 740-5 and connects in series gates 770-3 and 770- 4 thereby forming the NOR 520 and connects its output to the input of NOT 530 that includes gates 740-6 and 770-6. A third metal connection 790-3 connects diffusions 750- 7 and 780-7 to form the output of the NOT 530. It should be noted that not all connections are shown herein, for example gates 740-1 (input A) and gate 770-1 (input A) are electrically connected however, this is not shown herein as it is not necessary for appreciating the operation and novelty of the disclosed embodiments. Such is true for similar other connections. According to the disclosed embodiments, as presented in the example layout of 700, provides a notable saving of the circuit area and size.

[0034] According to the disclosed embodiments, with respect to a planar MOSFET technology, the GAP area required between the layout of the NAND gate 110 and the NOT gate 120 minus the area used for the separation circuit 410 is saved. In either case, a measurable advantage is provided over the prior art without sacrificing circuit performance. Depending on the manufacturing technology, such area advantages may range between 20 and 15 % for technologies having a feature size in the range of 12-18 nanometers. A further advantage of the smaller area is the shorter metal interconnect, critical for FinFET technology, which results in less capacitive and resistive load. Moreover, smaller die area translates to high manufacturing yields as well as lower cost and lower overall interconnect delay, also associated with improved performance.

[0035] It should be appreciated that the advantages described herein may be also equally employed to silicon on insulator (SOI) technology. It should be further appreciated that though the layout shown herein is not a full layout, that is performed for purely pedagogical reasons and ease of explanation and an ordinary skill in the art can add the full layers required without undue burden whatsoever.

[0036] Further multi-stage logic circuits can also avoid the GAP spacing as well as dummy gates when chaining a plurality of logic gates. In an embodiment, the logic cells and the separation cells are adapted to be cells of a standard cell library. These are typically designed, so that one standard cell may be abutted to another standard cell using fully automatic or partially automatic layout and/or placement programs. In some embodiments, there will be no need for adding a full gate (e.g., gate 340-3 or gate 370- 3), instead a highly doped N+ as P-type transistor separation (i.e. , instead of gate 370-3), or a highly doped P+ as a separation as N-type transistor (i.e., instead of gate 340-3). By not having a full gate, this means No Polysilicon on the gate, or maybe no Oxide. Such embodiments should be considered within the scope of the embodiments disclosed herein.

[0037] As noted herein the disclosed embodiments, though described in greater detail for FinFET technology, may also apply to the like of planar FET and vertical FET technologies without departing from the scope as disclosed. Furthermore, technologies such as, but not limited to, nanowire transistors, nano slab transistors, nanosheet transistors, and like three-dimensional transistor technologies may be adapted according to the principals described herein and without departing from the scope of the disclosed embodiments. [0038] An embodiment of a layout of a plurality of logic cells may therefore comprise of: a first logic cell having at least an input and an output, the first logic cell comprising of at least an N-type FET and at least a P-type FET; a second logic cell having at least an input and an output, the second logic cell comprising of at least an N-type FET and at least a P-type FET, wherein the at least an input of the second logic cell is electrically connected to the output of the first logic cell; a separation circuit adapted to operate at the OFF condition to provide a separation between the first logic cell and the second logic cell, and having a port of the separation circuit electrically connected to the output of the first logic circuit. The logic cells may be, but are not limited to, NOT gate, NOR gate, OR gate, AND gate, NAND gate, XOR gate. Furthermore, various combinations of basic logic cells may benefit from the teachings herein, including, but not limited to, the layout of flip-flops (FFs) and static random-access memory (SRAM) cells, which may be implemented using one of a plurality of manufacturing technologies described herein.

[0039] All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the disclosed embodiment and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosed embodiments, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

[0040] It should be understood that any reference to an element herein using a designation such as “first,” “second,” and so forth does not generally limit the quantity or order of those elements. Rather, these designations are generally used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements may be employed there or that the first element must precede the second element in some manner. Also, unless stated otherwise, a set of elements comprises one or more elements. [0041] As used herein, the phrase “at least one of” followed by a listing of items means that any of the listed items can be utilized individually, or any combination of two or more of the listed items can be utilized. For example, if a system is described as including “at least one of A, B, and C,” the system can include A alone; B alone; C alone; 2A; 2B; 2C; 3A; A and B in combination; B and C in combination; A and C in combination; A, B, and C in combination; 2A and C in combination; A, 3B, and 2C in combination; and the like.

Claims

CLAIMS What is claimed is:

1 . A layout of a plurality of logic cells, comprising: a first logic cell having at least an input and an output, the first logic cell having at least an N-type field effect transistor (FET) and at least a P-type FET; a second logic cell having at least one input and an output, the second logic cell having at least an N-type FET and at least a P-type FET, wherein the at least one input of the second logic cell is electrically connected to the output of the first logic cell; and a separation circuit adapted to operate at an off condition to provide a separation between the first logic cell and the second logic cell, and having a drain port of the separation circuit electrically connected to the output of the first logic circuit.

2. The layout of a plurality of logic cells of claim 1 , wherein the separation circuit comprises: at least a FET having the drain port, a source port, and a gate port, wherein the source port is electrically connected to the gate port.

3. The layout of a plurality of logic cells of claim 2, wherein the at least a FET of the separation circuit is an N-Type.

4. The layout of a plurality of logic cells of claim 3, wherein the source port is connected to a first reference voltage.

5. The layout of a plurality of logic cells of claim 4, wherein the first reference voltage is ground.

6. The layout of a plurality of logic cells of claim 2, wherein the at least a FET of the separation circuit is a P-Type.

7. The layout of a plurality of logic cells of claim 6, wherein the source port is connected to a second reference voltage.

8. The layout of a plurality of logic cells of claim 7, wherein the second reference voltage is a power source having a voltage higher than ground.

9. The layout of a plurality of logic cells of claim 1 , wherein the plurality of logic cells are implemented using silicon over insulator (SOI) manufacturing technology.

10. The layout of a plurality of logic cells of claim 1 , wherein the plurality of logic cells are implemented using FinFET manufacturing technology.

11 . The layout of a plurality of logic cells of claim 1 , wherein the plurality of logic cells are implemented using vertical FET manufacturing technology.

12. The layout of a plurality of logic cells of claim 1 , wherein the plurality of logic cells are implemented using planar metal-oxide-semiconductor (MOS) manufacturing technology.

13. The layout of a plurality of logic cells of claim 1 , wherein the plurality of logic cells are implemented using nanowire manufacturing technology.

14. The layout of a plurality of logic cells of claim 1 , wherein the plurality of logic cells are implemented using a nano slab manufacturing technology.

15. The layout of a plurality of logic cells of claim 1 , wherein the plurality of logic cells are implemented using nanosheet manufacturing technology.

16. The layout of a plurality of logic cells of claim 1 , wherein each of the first logic cell, the second logic cell, and the separation circuit is further adapted to correspond to a standard cell of a standard cell library.

17. The layout plurality of logic cells of claim 1 , wherein the separation circuit comprises: at least a highly doped separation area formed over a diffusion layer.

18. The layout plurality of logic cells of claim 17, wherein the at least a highly doped separation area is a P+ doping.

19. The layout plurality of logic cells of claim 17, wherein the at least a highly doped separation area is an N+ doping.

20. The layout plurality of logic cells of claim 1 , wherein a logic cell of the plurality of logic cells is one of: a NOT gate, a NOR gate, an OR gate, an AND gate, a NAND gate, and a XOR gate.

21. The layout plurality of logic cells of claim 1 , wherein the plurality of logic cell includes a flip-flop (FF) cell.

22. The layout plurality of logic cells of claim 1 , wherein the plurality of logic cell includes a static random-access memory (SRAM) cell.

23. An integrated circuit, comprising: a first logic cell having at least an input and an output, the first logic cell having at least an N-type field effect transistor (FET) and at least a P-type FET; a second logic cell having at least one input and an output, the second logic cell having at least an N-type FET and at least a P-type FET, wherein the at least one input of the second logic cell is electrically connected to the output of the first logic cell; and a separation circuit adapted to operate at an off condition to provide a separation between the first logic cell and the second logic cell, and having a drain port of the separation circuit electrically connected to the output of the first logic circuit.

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