WO2022143151A1 - 驱动方法、驱动装置和显示设备 - Google Patents
驱动方法、驱动装置和显示设备 Download PDFInfo
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- 238000004891 communication Methods 0.000 description 5
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- the present disclosure relates to the field of display driving, and in particular, to a driving method, a driving device and a display device.
- the present disclosure proposes a driving method, a driving apparatus and a display device.
- an embodiment of the present disclosure provides a driving method, including:
- each timing control chip is coupled to some source driver chips in the N source driver chips;
- Each timing control chip sends a display signal and an indication signal to the source driver chip coupled thereto according to the input signal, where the indication signal is used to indicate the odd-even frame state of the display signal.
- the indication signal is a polarity conversion signal POL; when POL is at a high level, it indicates that the display signal is an odd-numbered frame, and when POL is at a low level, it indicates that the display signal is an even-numbered frame;
- POL when POL is at a low level, it indicates that the display signal is an odd-numbered frame; when POL is at a high level, it indicates that the display signal is an even-numbered frame.
- the indication signal includes a frame control instruction packet:
- the value of the frame control instruction packet when the value of the frame control instruction packet is low, it indicates that the display signal is an odd-numbered frame; when the value of the frame control instruction packet is high, it indicates that the display signal is an even-numbered frame.
- the driving method further includes:
- the timing control chip sends the display data of the even-numbered lines to the source driver chip coupled thereto through the timing control chip.
- an embodiment of the present disclosure provides a driving device, including:
- a first processing module configured to receive input signals synchronously through at least two timing control chips, wherein each timing control chip is coupled to some source driver chips in the N source driver chips;
- the second processing module is configured to make each timing control chip send a display signal and an indication signal to the source driver chip coupled to it according to the input signal, where the indication signal is used to indicate the parity frame state of the display signal.
- the second processing module includes a first processing sub-module, configured to: if the indication signal is the polarity conversion signal POL:
- POL When POL is at a high level, it indicates that the display signal is an odd-numbered frame; when POL is at a low level, it indicates that the display signal is an even-numbered frame;
- POL when POL is at a low level, it indicates that the display signal is an odd-numbered frame; when POL is at a high level, it indicates that the display signal is an even-numbered frame.
- the second processing module further includes a second processing sub-module for:
- the value of the frame control instruction packet included in the indication signal When the value of the frame control instruction packet included in the indication signal is high, it indicates that the display signal is an odd-numbered frame; when the value of the frame control instruction packet is low, it indicates that the display signal is an even frame frame;
- the value of the frame control instruction packet when the value of the frame control instruction packet is low, it indicates that the display signal is an odd-numbered frame; when the value of the frame control instruction packet is high, it indicates that the display signal is an even-numbered frame.
- the driving device further includes:
- a third processing module configured to send display data of odd-numbered rows to the source driver chip coupled thereto through the timing control chip when the display signal is an odd-numbered frame;
- the fourth processing module is used for sending even-numbered lines of display data to the source driver chip coupled thereto through the timing control chip when the display signal is an even-numbered frame.
- an embodiment of the present disclosure provides a display device, including a memory, a processor, and a program stored on the memory and executable on the processor, the processor being configured to read data stored in the memory
- the program implements the steps in the driving method according to any one of the embodiments of the present disclosure.
- an embodiment of the present disclosure provides a readable storage medium for storing a program, and when the program is executed by a processor, the program implements the steps in any one of the driving methods provided by the embodiment of the present disclosure.
- FIG. 1 is a flowchart of a driving method provided by an embodiment of the present disclosure
- FIG. 2 is a schematic structural diagram of a driving circuit to which a driving method according to an embodiment of the present disclosure can be applied;
- FIG. 3 is a timing diagram of a driving circuit to which a driving method according to an embodiment of the present disclosure can be applied;
- Fig. 4 is the timing chart of the internal monitoring of the odd-even frame state of the drive circuit
- Fig. 5 is the timing diagram of frame state mismatch caused by the influence of asynchronous power-on reset signal
- FIG. 6 is a timing diagram of the frame state mismatch caused by the electrostatic interference of the source driver chip
- FIG. 7 is a timing diagram of applying a driving method according to an embodiment of the present disclosure to a driving circuit
- FIG. 8 is a timing diagram of applying a driving method according to an embodiment of the present disclosure to a driving circuit
- FIG. 9 is a schematic structural diagram of a driving device according to an embodiment of the present disclosure.
- FIG. 10 is a schematic structural diagram of a driving device according to an embodiment of the present disclosure.
- FIG. 11 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
- 11-sequence control chip 1 12-sequence control chip 2, 13-source drive module, 14-gate drive module, 15-display screen.
- first, second, etc. in the description and claims of the present disclosure are used to distinguish similar objects, and are not used to describe a specific order or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances so that embodiments of the present disclosure can be practiced in sequences other than those illustrated or described herein, and distinguished by "first,” “second,” etc.
- the objects are usually of one type, and the number of objects is not limited.
- the first object may be one or more than one.
- “and/or” in the description and claims indicates at least one of the connected objects, and the character “/" generally indicates that the associated objects are in an "or” relationship.
- a flowchart of a driving method is provided in an embodiment of the present disclosure, and the method includes:
- Step 101 receiving input signals synchronously through at least two timing control chips, wherein each timing control chip is coupled to some source driver chips in the N source driver chips;
- each timing control chip sends a display signal and an indication signal to the source driver chip coupled to it according to the input signal, where the indication signal is used to indicate the parity frame state of the display signal.
- the driving method provided by the present disclosure sends a signal for indicating the odd-even frame state of the display signal to the source driver chip coupled to it through the timing control chip, so that the source driver chip, the timing control chip, and the different source driver chips It can synchronously recognize the odd-even frame status of the current display signal, so as to ensure that the display screen controlled by the multi-sequence control chip and the multi-source driver chip does not display abnormality when displaying the picture.
- the current display signal in the state of odd or even frames will not be transmitted to SDIC. Therefore, usually by receiving the gate enable signal GSP (Gate start pulse), the information of this signal is stored in the internal counter to judge the status of each frame.
- GSP Gate start pulse
- the driving method provided by the present disclosure can be applied to a driving circuit with a source driving chip.
- the size of the display screen is 8K, 7680*4320.
- source driver chips 1301-1324 of which the specifications of timing control chip 1 and timing control chip 2 are both 8K 60Hz, and 12 source driver chips 1301-1312 are controlled by timing control chip 1 and controlled by timing control chip 2.
- the other 12 source driver chips 1313-1324, SDIC1 in Figure 2 is the source driver chip connected to the timing control chip 1
- SDIC2 is the source driver chip connected to the timing control chip 2
- the timing control chip Chip 1 realizes the display control of 3840 columns of RGB pixels on the left side of the display screen by controlling 12 SDIC1s
- timing control chip 2 realizes the control of 3840 columns of RGB pixels on the right side of the display screen by controlling 12 SDIC2s.
- FIG. 3 is a timing diagram corresponding to the driving circuit shown in FIG. 2 .
- the specification of the input signal is 3Gbps dual-lane (3G-2lane), and the source output enable signal SOE (Source output enable) is falling
- SOE Source output enable
- the source driver chip starts to charge and output, and the output terminal SDOUT of the source driver chip can be seen from Figure 2 that it remains unchanged after being fully charged until SOE is at a high level again.
- GSP Gate start pulse
- G1, G2, G3, G4 are the horizontal scanning signal of the first row to the fourth row of the horizontal scanning signal output by the gate drive module, in odd frames, such as in the first row In the frame and the third frame, the odd-numbered lines (G1, G3) are output, and the even-numbered frames have no output information; in the even-numbered frames, such as the second and fourth frames, the even-numbered lines (G2, G4) are output, while the odd-numbered frames are output. No output information.
- the process of recording the state of the odd-numbered frame or the even-numbered frame of the display signal through the gate control (enable) signal GSP is as follows:
- 3GSP signal triggers frame counter.
- the source driver chip 2 After the GSP rise is triggered, the source driver chip 2 cannot update the counter data.
- electrostatic ESD interference causes the source driver chip to be in a frame state of cognitive error, refer to Figure 6:
- the source driver chip SDIC1 controlled by the timing control chip 1 and the source driver chip controlled by the timing control chip 2 will be caused.
- the frame status of the driver chip SDIC2 does not match.
- This mismatch will cause the source driver chips coupled by different timing control chips to fail to receive correct display data, thus causing the display panel to fail to display images correctly.
- the left side of the display screen displays odd-numbered frames. Image, the right side shows an even frame image, resulting in image flickering or left-right mismatch, and various other display issues.
- step 101 the multiple timing control chips receive the input signal synchronously, so the frame state cognition between each timing control chip is consistent.
- each timing control chip sends a display signal and an indication signal to the source driver chip coupled thereto according to the input signal, and the indication signal is used to indicate the parity frame state of the display signal.
- the timing control chip additionally sends an indication signal for indicating the odd-even frame state of the display signal to the source driver chip coupled to it according to the input signal, so this method can be used to ensure the timing control chip and the source driver chip, and Frame state awareness synchronization between different source driver chips ensures that the display panel displays the correct image.
- the indication signal is a polarity conversion signal POL (polarity conversion signal); when POL is at a high level, it indicates that the display signal is an odd-numbered frame, and when POL is at a low level, it indicates that the display signal is an even-numbered frame frame;
- POL polarity conversion signal
- POL when POL is at a low level, it indicates that the display signal is an odd-numbered frame; when POL is at a high level, it indicates that the display signal is an even-numbered frame.
- the communication protocol used by the current driving circuit already contains a signal with frame rate change, such as a polarity switching signal (POL), it usually appears in a display system using column inversion.
- POL polarity switching signal
- the parity frame state of the display signal can be determined directly by defining the POL signal.
- the Chopper signal used for the offset cancel function can also be used to indicate the status of odd and even frames.
- the indication signal includes a frame control instruction packet:
- the value of the frame control instruction packet when the value of the frame control instruction packet is low, it indicates that the display signal is an odd-numbered frame; when the value of the frame control instruction packet is high, it indicates that the display signal is an even-numbered frame.
- the driving method further includes:
- the timing control chip sends the display data of the even-numbered lines to the source driver chip coupled thereto through the timing control chip.
- the source driver chip when running, it only receives the odd-numbered line information of the frame image sent by the timing control chip connected to it in odd-numbered frames, and only receives the frame sent by the timing control chip connected to it in even-numbered frames.
- the even-numbered lines of the image can greatly reduce the bandwidth pressure. For example, to achieve 8K 120Hz image display through a single TCON, 48 high-speed transmission signal pairs are usually required.
- the TCON When receiving 3Gbps dual-channel signals, the TCON also supports 3Gbps dual-channel communication. , and after adopting the above method, only the TCON needs to support 1.53Gbps dual-channel signal.
- the driving method provided by the present disclosure can send a signal for indicating the odd-even frame state of the display signal to the source driver chip coupled thereto through the timing control chip, so that the source driver chip and the timing control chip, as well as different
- the source driver chips of the two devices can synchronously recognize the parity frame status of the current display signal, so as to ensure that the display screen controlled by the multi-sequence control chip and the multi-source driver chip does not display abnormality when displaying the picture.
- an embodiment of the present disclosure provides a driving device 90, including:
- the first processing module 901 is configured to receive input signals synchronously through at least two timing control chips, wherein each timing control chip is coupled to some source driver chips in the N source driver chips;
- the second processing module 902 is configured to make each timing control chip send a display signal and an indication signal to the source driver chip coupled to it according to the input signal, where the indication signal is used to indicate the parity frame state of the display signal .
- the second processing module 902 includes a first processing sub-module 9021 for: if the indication signal is the polarity conversion signal POL:
- POL When POL is at a high level, it indicates that the display signal is an odd-numbered frame; when POL is at a low level, it indicates that the display signal is an even-numbered frame;
- POL when POL is at a low level, it indicates that the display signal is an odd-numbered frame; when POL is at a high level, it indicates that the display signal is an even-numbered frame.
- the second processing module 902 further includes a second processing sub-module 9022, for when the indication signal includes a frame control instruction packet:
- the value of the frame control instruction packet when the value of the frame control instruction packet is low, it indicates that the display signal is an odd-numbered frame; when the value of the frame control instruction packet is high, it indicates that the display signal is an even-numbered frame.
- the driving device 90 further includes:
- the 3rd processing module 903, is used for when described display signal is odd-numbered frame, sends the display data of odd-numbered row by timing control chip to the source driver chip coupled to it;
- the fourth processing module 904 is configured to send display data of even-numbered lines to the source driver chip coupled thereto through the timing control chip when the display signal is an even-numbered frame.
- the driving device can send a signal for indicating the parity frame state of the display signal to the source driver chip coupled thereto through a plurality of timing control chips, so that the source driver chip and the timing control chip, as well as different sources
- the driver chips can synchronously recognize the parity frame status of the current display signal, so as to ensure that the display screen controlled by the multi-sequence control chip and the multi-source driver chip does not display abnormality when displaying the picture.
- an embodiment of the present disclosure further provides a display device 1100 , including a processor 1101 , a memory 1102 , and a computer program stored in the memory 1102 and executed on the processor 1101 , the computer program being executed by the processor
- a display device 1100 including a processor 1101 , a memory 1102 , and a computer program stored in the memory 1102 and executed on the processor 1101 , the computer program being executed by the processor
- 1101 is executed, each process of the embodiment of the above driving method is implemented, and the same technical effect can be achieved. In order to avoid repetition, details are not repeated here.
- Embodiments of the present disclosure further provide a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, each process of the foregoing driving method embodiment can be implemented, and can achieve the same In order to avoid repetition, the technical effect will not be repeated here.
- the computer-readable storage medium such as read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk, etc.
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Abstract
本公开提供一种驱动方法、驱动装置和显示设备。本公开提供的驱动方法通过至少两个时序控制芯片分别向与其耦接的源极驱动芯片发送用于指示显示信号的奇偶帧状态的指示信号，使源极驱动芯片和时序控制芯片、以及不同的源极驱动芯片之间都能够同步认知当前显示信号的奇偶帧状态。
Description
相关申请的交叉引用
本申请要求于2020年12月30日在中国国家知识产权局递交的中国专利申请No.202011608213.4的优先权，其全部公开内容通过引用并入于此。
本公开涉及显示驱动领域，尤其涉及一种驱动方法、驱动装置和显示设备。
随着显示技术的进步，消费者体验的需求也日渐升高，增加显示设备的解析度和降低响应时间可以为消费者提供更好的体验。然而，随着显示装置需要越来越短的反应时间，以及越来越高的解析度的需求，使得显示驱动芯片必须在更短的时间内对更大的负载电容进行充放电，这给驱动芯片设计带来很大难度。
为了维持生产成本，终端屏幕制造商提出一些系统解决方案放宽驱动芯片规格的设计，如通过低于8K 120Hz的时序控制芯片TCON(Time Control IC)，来达到近似8K 120Hz的规格效果，为了提供充足的充电时间，通常源极驱动芯片SDIC(Source Driver IC)无法在每一条栅极线上更新资料。
发明内容
本公开提出了一种驱动方法、驱动装置和显示设备。
一方面，本公开实施例提供了一种驱动方法，包括：
通过至少2个时序控制芯片同步接收输入信号，其中，每个时序控制芯片与N个源极驱动芯片中的部分源极驱动芯片耦接；
每个时序控制芯片根据所述输入信号向与其耦接的源极驱动芯片发送显示信号和指示信号，所述指示信号用于指示所述显示信号的奇偶帧状态。
可选的，所述指示信号为极性转换信号POL；当POL为高电平，指示所述显示信号为奇数帧，当POL为低电平，指示所述显示信号为偶数帧；
或者，当POL为低电平，指示所述显示信号为奇数帧；当POL为高电平，指示所述显示信号为偶数帧。
可选的，所述指示信号包括帧控制指令包：
当所述帧控制指令包的值为高电平时，指示所述显示信号为奇数帧；当所述帧控制指令包的值为低电平，指示所述显示信号为偶数帧；
或者，当所述帧控制指令包的值为低电平时，指示所述显示信号为奇数帧；当所述帧控制指令包的值为高电平，指示所述显示信号为偶数帧。
可选的，所述驱动方法还包括：
当所述显示信号为奇数帧时，通过时序控制芯片向与其耦接的源极驱动芯片发送奇数行的显示数据；
当所述显示信号为偶数帧时，通过时序控制芯片向与其耦接的源极驱动芯片发送偶数行的显示数据。
一方面，本公开实施例提供了一种驱动装置，包括：
第一处理模块，用于通过至少2个时序控制芯片同步接收输入信号，其中，每个时序控制芯片与N个源极驱动芯片中的部分源极驱动芯片耦接；
第二处理模块，用于使每个时序控制芯片根据所述输入信号向与其耦接的源极驱动芯片发送显示信号和指示信号，所述指示信号用于指示所述显示信号的奇偶帧状态。
可选的，所述第二处理模块包括第一处理子模块，用于若所述指示信号为极性转换信号POL时：
当POL为高电平，指示所述显示信号为奇数帧；当POL为低电平，指示所述显示信号为偶数帧；
或者，当POL为低电平，指示所述显示信号为奇数帧；当POL为高电平，指示所述显示信号为偶数帧。
可选的，所述第二处理模块还包括第二处理子模块，用于：
当包括在所述指示信号中的帧控制指令包的值为高电平时，指示所述显示信号为奇数帧；当所述帧控制指令包的值为低电平，指示所述显示信号为偶数 帧；
或者，当所述帧控制指令包的值为低电平时，指示所述显示信号为奇数帧；当所述帧控制指令包的值为高电平，指示所述显示信号为偶数帧。
可选的，所述驱动装置还包括：
第三处理模块，用于当所述显示信号为奇数帧时，通过时序控制芯片向与其耦接的源极驱动芯片发送奇数行的显示数据；
第四处理模块，用于当所述显示信号为偶数帧时，通过时序控制芯片向与其耦接的源极驱动芯片发送偶数行的显示数据。
一方面，本公开实施例提供了一种显示设备，包括存储器、处理器及存储在所述存储器上并可在所述处理器上运行的程序，所述处理器，用于读取存储器中的程序实现如本公开实施例提供的任一项所述的驱动方法中的步骤。
一方面，本公开实施例提供了一种可读存储介质，用于存储程序，所述程序被处理器执行时实现如本公开实施例提供的任一项所述的驱动方法中的步骤。
图1为本公开实施例提供的一种驱动方法的流程图；
图2为本公开实施例提供的一种驱动方法可应用的驱动电路的结构示意图；
图3为本公开实施例提供的一种驱动方法可应用的驱动电路的时序图；
图4为驱动电路的奇偶帧状态的内部监控的时序图；
图5为非同步的上电复位信号影响导致帧状态不匹配的时序图；
图6为源极驱动芯片受到静电干扰导致的帧状态不匹配的时序图；
图7为本公开实施例提供的一种驱动方法应用于驱动电路的时序图；
图8为本公开实施例提供的一种驱动方法应用于驱动电路的时序图；
图9为本公开实施例提供的一种驱动装置结构示意图；
图10为本公开实施例提供的一种驱动装置结构示意图；
图11为本公开实施例提供的一种显示设备结构示意图。
附图标记说明：
11-时序控制芯片1、12-时序控制芯片2、13-源极驱动模块、14-栅极驱动模块、15-显示屏。
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开的保护范围。
本公开的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便本公开的实施例能够以除了在这里图示或描述的那些以外的顺序实施，且“第一”、“第二”等所区分的对象通常为一类，并不限定对象的个数，例如第一对象可以是一个，也可以是多个。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
此外，下面所描述的本公开不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
参考图1，为本公开实施例提供了一种驱动方法的流程图，所述方法包括：
步骤101，通过至少2个时序控制芯片同步接收输入信号，其中，每个时序控制芯片与N个源极驱动芯片中的部分源极驱动芯片耦接；
步骤102，每个时序控制芯片根据所述输入信号向与其耦接的源极驱动芯片发送显示信号和指示信号，所述指示信号用于指示所述显示信号的奇偶帧状态。
本公开提供的驱动方法通过时序控制芯片向与其耦接的源极驱动芯片发送用于指示显示信号的奇偶帧状态的信号，使源极驱动芯片和时序控制芯片、以及不同的源极驱动芯片之间都能够同步认知当前显示信号的奇偶帧状态，从而保证通过多时序控制芯片与多源极驱动芯片控制的显示屏在显示画面时不出现异常。
具体的，现有的被广泛使用在时序控制芯片TCON与源极驱动芯片SDIC的高速通信协议里，当前显示信号处于奇数帧或偶数帧的状态是不会被传递给SDIC的。所以，通常是通过接收栅极使能信号GSP(Gate start pulse)，将此信号的信息存入内部计数器之中，用来判断每帧的状态。
具体的，本公开提供的驱动方法可以应用到具有源极驱动芯片的驱动电路中，以图2示出的驱动电路为例，显示屏的尺寸为8K，7680*4320，源极驱动模块13中共有24个源极驱动芯片1301-1324，其中时序控制芯片1与时序控制芯片2的规格都为8K 60Hz，通过时序控制芯片1控制12个源极驱动芯片1301-1312，通过时序控制芯片2控制另外12个源极驱动芯片1313-1324，图2中的SDIC1为与时序控制芯片1连接的源极驱动芯片，SDIC2为与时序控制芯片2连接的源极驱动芯片，在显示过程中，时序控制芯片1通过控制12颗SDIC1来实现对显示屏左边3840列RGB像素的显示控制，时序控制芯片2通过控制12颗SDIC2来实现对显示屏右边3840列RGB像素的控制。
具体的，参考图3为图2示出的驱动电路对应的时序图，此时输入信号的规格为3Gbps双通道(3G-2lane)，源极输出使能信号SOE(Source output enable)，在下降沿时，源极驱动芯片开始充电并输出，源极驱动芯片输出端SDOUT从图2中可知充满电后直到SOE再次处于高电平时保持不变。GSP(Gate start pulse)为栅极使能信号，G1、G2、G3、G4分别为栅极驱动模块输出的第1行水平扫描信号至第4行水平扫描信号，在奇数帧，如在第一帧、第三帧时，输出奇数行(G1、G3)，而偶数帧没有输出信息；在偶数帧，如在第二帧、第四帧时，输出偶数行(G2、G4)，而奇数帧没有输出信息。
参考图4，通过栅极控制(使能)信号GSP对显示信号的奇数帧或偶数帧的状态进行记录的过程如下：
①高压电源VDDA和低压电源VDDD准备好。
②内部上电复位信号POR(Power On Reset),当侦测到POR信号处于下降沿，驱动芯片即将开始运作。
③GSP信号触发帧计数器。
④当最低有效位(LSB)的值等于1时，表示帧的状态为奇数帧。
⑤GSP信号电位抬升，再次触发计数器。
⑥当最低有效位(LSB)的值等于0时，表示帧的状态为偶数帧。
上述操作过程，在实际应用中会产生一些问题。
具体的，非同步的POR复位信号触发时间会导致如图5示出的问题：
51-不同的电源抬升时间，会导致源极驱动芯片产生不同POR复位的脉冲位置。
52-在GSP抬升触发后，源极驱动芯片2无法更新计数器资料。
53-最后，导致两组源极驱动芯片的计数状态不匹配。
具体的，静电ESD干扰造成源极驱动芯片处于认知错误的帧状态，参考图6：
61-ESD干扰产生计数器重置。
62-在GSP抬升触发后，两组源极驱动芯片帧率状态是不匹配的。
具体的，如图2中示出的驱动电路，两组源极驱动芯片帧率状态不匹配的情况会导致由时序控制芯片1控制的源极驱动芯片SDIC1与由时序控制芯片2控制的源极驱动芯片SDIC2的帧状态不匹配。这种不匹配会导致由不同时序控制芯片耦接的源极驱动芯片无法接收正确的显示数据，从而导致显示面板无法正确的显示图像，比如，图2中会出现显示屏左侧显示了奇数帧图像，右侧显示偶数帧图像，导致图像闪烁或左右不匹配，以及其他各种显示问题。
在步骤101中，多个时序控制芯片是同步接收到输入信号，因此每个时序控制芯片之间的帧状态认知是一致的。
在步骤102中，每个时序控制芯片根据所述输入信号向与其耦接的源极驱动芯片发送显示信号和指示信号，指示信号用于指示显示信号的奇偶帧状态。通过时序控制芯片根据输入信号向与其耦接的源极驱动芯片额外发送一个用于指示显示信号的奇偶帧状态的指示信号，因此能够通过这种方法来保证时序控制芯片与源极驱动芯片，以及不同源极驱动芯片之间的帧状态认知同步，从而保证显示面板显示正确的图像。
可选的，所述指示信号为极性转换信号POL(polarity conversion signal)；当POL为高电平，指示所述显示信号为奇数帧，当POL为低电平，指示所述显示信号为偶数帧；
或者，当POL为低电平，指示所述显示信号为奇数帧；当POL为高电平，指示所述显示信号为偶数帧。
具体的，如果当前驱动电路使用的通信协议中已经含有帧率变化的讯号存在，如极性转换信号(POL)在使用列反转的显示系统中通常会出现，当使用的显示系统中存在POL信号时，可以直接通过对POL信号进行定义来确定显示信号的奇偶帧状态。
示例性的，参考图7，定义POL＝H(高电平)时，显示信号为奇数帧；定义POL＝L(低电平)时，显示信号为偶数帧；所以源极驱动芯片SDIC可以由POL的状态来认知目前的帧状态。
此外，除了POL这个信号外，用于偏移抵消功能(offset cancel function)的斩波(Chopper)信号也能用来表示奇数偶数帧的状态。
可选的，所述指示信号包括帧控制指令包：
当所述帧控制指令包的值为高电平时，指示所述显示信号为奇数帧；当所述帧控制指令包的值为低电平，指示所述显示信号为偶数帧；
或者，当所述帧控制指令包的值为低电平时，指示所述显示信号为奇数帧；当所述帧控制指令包的值为高电平，指示所述显示信号为偶数帧。
当前驱动电路使用的通信协议中没有含有帧率变化的讯号存在，则可以通过在通信协议中加入额外的寄存器位元，奇数偶数帧状态需被更新到每一帧里，因此，额外的寄存器位元应该被加入帧控制指令包(Control frame command)中。
示例性的，参考图8，定义帧控制指令包Packet Odd＝H(高电平)时，所述显示信号为奇数帧；Packet Odd＝L(低电平)时，所述显示信号为偶数帧。
可选的，所述驱动方法还包括：
当所述显示信号为奇数帧时，通过时序控制芯片向与其耦接的源极驱动芯片发送奇数行的显示数据；
当所述显示信号为偶数帧时，通过时序控制芯片向与其耦接的源极驱动芯片发送偶数行的显示数据。
具体的，源极驱动芯片在运行过程时，在奇数帧只接收到与其连接的时序控制芯片发送的该帧图像的奇数行信息，在偶数帧只接收到与其连接的时序控 制芯片发送的该帧图像的偶数行信息，能够极大的降低带宽压力，例如：通过单个TCON要实现8K 120Hz的图像显示，通常需要48个高速传输信号对，接收3Gbps双通道信号时需要TCON也支持3Gbps双通道通讯，而采用上述方法后，只需要TCON支持1.53Gbps双通道信号即可。
综上所述，本公开提供的驱动方法能够通过时序控制芯片向与其耦接的源极驱动芯片发送用于指示显示信号的奇偶帧状态的信号，使源极驱动芯片和时序控制芯片、以及不同的源极驱动芯片之间都能够同步认知当前显示信号的奇偶帧状态，从而保证通过多时序控制芯片与多源极驱动芯片控制的显示屏在显示画面时不出现异常。
参考图9，一方面，本公开实施例提供了一种驱动装置90，包括：
第一处理模块901，用于通过至少2个时序控制芯片同步接收输入信号，其中，每个时序控制芯片与N个源极驱动芯片中的部分源极驱动芯片耦接；
第二处理模块902，用于使每个时序控制芯片根据所述输入信号向与其耦接的源极驱动芯片发送显示信号和指示信号，所述指示信号用于指示所述显示信号的奇偶帧状态。
可选的，参考图10，所述第二处理模块902包括第一处理子模块9021，用于若所述指示信号为极性转换信号POL时：
当POL为高电平，指示所述显示信号为奇数帧；当POL为低电平，指示所述显示信号为偶数帧；
或者，当POL为低电平，指示所述显示信号为奇数帧；当POL为高电平，指示所述显示信号为偶数帧。
可选的，参考图10，所述第二处理模块902还包括第二处理子模块9022，用于当所述指示信号包括帧控制指令包时：
当所述帧控制指令包的值为高电平时，指示所述显示信号为奇数帧；当所述帧控制指令包的值为低电平，指示所述显示信号为偶数帧；
或者，当所述帧控制指令包的值为低电平时，指示所述显示信号为奇数帧；当所述帧控制指令包的值为高电平，指示所述显示信号为偶数帧。
可选的，参考图10，所述驱动装置90还包括：
第三处理模块903，用于当所述显示信号为奇数帧时，通过时序控制芯片 向与其耦接的源极驱动芯片发送奇数行的显示数据；
第四处理模块904，用于当所述显示信号为偶数帧时，通过时序控制芯片向与其耦接的源极驱动芯片发送偶数行的显示数据。
本公开提供的驱动装置能够通过多个时序控制芯片向与其耦接的源极驱动芯片发送用于指示显示信号的奇偶帧状态的信号，使源极驱动芯片和时序控制芯片、以及不同的源极驱动芯片之间都能够同步认知当前显示信号的奇偶帧状态，从而保证通过多时序控制芯片与多源极驱动芯片控制的显示屏在显示画面时不出现异常。
请参考图11，本公开实施例还提供一种显示设备1100，包括处理器1101，存储器1102，存储在存储器1102上并可在所述处理器1101上运行的计算机程序，该计算机程序被处理器1101执行时实现上述驱动方法的实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
本公开实施例还提供一种计算机可读存储介质，所述计算机可读存储介质上存储计算机程序，所述计算机程序被处理器执行时实现上述驱动方法的实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。其中，所述的计算机可读存储介质，如只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端(可以是手机，计算机，服务器，空调器，或者 网络设备等)执行本公开各个实施例所述的方法。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本公开创造的保护范围之中。
Claims (10)
- 一种驱动方法，包括：通过至少2个时序控制芯片同步接收输入信号，其中，每个时序控制芯片与N个源极驱动芯片中的部分源极驱动芯片耦接；每个时序控制芯片根据所述输入信号向与其耦接的源极驱动芯片发送显示信号和指示信号，所述指示信号用于指示所述显示信号的奇偶帧状态。
- 根据权利要求1所述的驱动方法，其中，所述指示信号为极性转换信号POL；当POL为高电平，指示所述显示信号为奇数帧，当POL为低电平，指示所述显示信号为偶数帧；或者，当POL为低电平，指示所述显示信号为奇数帧；当POL为高电平，指示所述显示信号为偶数帧。
- 根据权利要求1所述的驱动方法，其中，所述指示信号包括帧控制指令包：当所述帧控制指令包的值为高电平时，指示所述显示信号为奇数帧；当所述帧控制指令包的值为低电平，指示所述显示信号为偶数帧；或者，当所述帧控制指令包的值为低电平时，指示所述显示信号为奇数帧；当所述帧控制指令包的值为高电平，指示所述显示信号为偶数帧。
- 根据权利要求2或3所述的驱动方法，其中，所述驱动方法还包括：当所述显示信号为奇数帧时，通过时序控制芯片向与其耦接的源极驱动芯片发送奇数行的显示数据；当所述显示信号为偶数帧时，通过时序控制芯片向与其耦接的源极驱动芯片发送偶数行的显示数据。
- 一种驱动装置，所述驱动装置包括：第一处理模块，用于通过至少2个时序控制芯片同步接收输入信号，其中，每个时序控制芯片与N个源极驱动芯片中的部分源极驱动芯片耦接；第二处理模块，用于使每个时序控制芯片根据所述输入信号向与其耦接的源极驱动芯片发送显示信号和指示信号，所述指示信号用于指示所述显示信号的奇偶帧状态。
- 根据权利要求5所述的驱动装置，其中，所述第二处理模块包括第一 处理子模块，用于若所述指示信号为极性转换信号POL时：当POL为高电平，指示所述显示信号为奇数帧；当POL为低电平，指示所述显示信号为偶数帧；或者，当POL为低电平，指示所述显示信号为奇数帧；当POL为高电平，指示所述显示信号为偶数帧。
- 根据权利要求5所述的驱动装置，其中，所述第二处理模块还包括第二处理子模块，用于：当包括在所述指示信号中的帧控制指令包的值为高电平时，指示所述显示信号为奇数帧；当所述帧控制指令包的值为低电平，指示所述显示信号为偶数帧；或者，当所述帧控制指令包的值为低电平时，指示所述显示信号为奇数帧；当所述帧控制指令包的值为高电平，指示所述显示信号为偶数帧。
- 根据权利要求7所述的驱动装置，其中，所述驱动装置还包括：第三处理模块，用于当所述显示信号为奇数帧时，通过时序控制芯片向与其耦接的源极驱动芯片发送奇数行的显示数据；第四处理模块，用于当所述显示信号为偶数帧时，通过时序控制芯片向与其耦接的源极驱动芯片发送偶数行的显示数据。
- 一种显示设备，包括存储器、处理器及存储在所述存储器上并可在所述处理器上运行的程序；其中，所述处理器，用于读取存储器中的程序以实现如权利要求1至4中任一项所述的驱动方法中的步骤。
- 一种可读存储介质，用于存储程序，其中，所述程序被处理器执行时实现如权利要求1至4中任一项所述的驱动方法中的步骤。
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| WO2023065338A1 (zh) * | 2021-10-22 | 2023-04-27 | 京东方科技集团股份有限公司 | 源极驱动电路、源极驱动方法、显示装置及显示驱动方法 |
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