WO2022024657A1 - Voltage detection device - Google Patents

Abstract

A voltage detection device (30) comprises a first voltage divider circuit (40), a detection circuit (50), and an electric potential stabilization circuit (80). The first voltage divider circuit divides, at two different voltage division ratios, a voltage applied to a system and outputs the divided voltages to input terminals. The voltage division ratios in the first voltage divider circuit are set to have values that differ in a stepwise manner for respective input terminals, which are output destinations, so that input signals to be input to the input terminals are in the order corresponding to the electric potential order. Withstand voltage securing channels which are a plurality of input channels (CH4, CH5) are provided between a high potential side input terminal (V3) and a low potential side input terminal (S6). The electric potential stabilization circuit outputs, to any of input terminals included in the withstand voltage securing channels, a signal having an electric potential between the electric potential of an input signal which is input into the high potential side input terminal and the electric potential of an input signal which is input into the low potential side input terminal.

Description

Voltage detector Cross-reference of related applications

This application is based on Japanese Application No. 2020-127393 filed on July 28, 2020, and the contents of the description are incorporated herein by reference.

This disclosure relates to a voltage detection device that performs voltage detection.

In recent years, in electric vehicles, a power supply system has been configured in which the function group is divided into a plurality of systems (systems) and the total voltage (voltage between terminals) of the in-vehicle assembled battery is selectively applied to each system by a system relay. ing. In such a power supply system, in order to detect whether or not a voltage is appropriately applied in the selected system, the total voltage applied to the selected system (hereinafter referred to as applied voltage) is detected. There is a need. At that time, it is desirable to enable detection by a common circuit from the viewpoint of cost, and since the total voltage of the in-vehicle assembled battery is generally as high as several hundreds of volts, the applied voltage is divided and detected. It is desirable to do.

Therefore, a method of dividing and detecting the voltage applied to the voltage dividing circuit as shown in Patent Document 1 and a method of measuring the divided voltage via a differential amplifier circuit as shown in Patent Document 2 are adopted. Was supposed.

However, in the method of Patent Document 1, the amount of current flowing through the bus bar, which is the detection reference of the applied voltage, is different for each selected circuit, and the potential in each bus bar is different. Then, when the voltage divider voltage is detected by the common circuit, one of the bus bars is used as a reference, which causes a problem that the detection accuracy deteriorates. Further, the method of Patent Document 2 solves the problem that the potentials in each bus bar are different, but in addition to the resistance error of the voltage dividing circuit, the gain error of the differential amplifier circuit overlaps and the detection accuracy is poor. occured. Therefore, the methods shown in Patent Documents 1 and 2 cannot be adopted as they are.

By the way, as shown in Patent Document 3, the monitoring IC that detects each voltage of the battery cells constituting the assembled battery integrates the differential amplifier circuit and the AD conversion device in the monitoring IC, and calibrates or corrects the total error. It is known that the detection accuracy is good because it is suppressed. Therefore, next, it has been considered to divert this monitoring IC to detect each applied voltage.

Japanese Unexamined Patent Publication No. 2013-162639 Japanese Unexamined Patent Publication No. 2009-236711 Japanese Patent No. 5783197

However, this monitoring IC has been developed specifically for measuring the voltage of each battery cell connected in series. Specifically, it is assumed that a voltage (input signal) is applied to each input channel of the monitoring IC in order of the magnitude of the potential, and it is assumed that the voltage of the same potential is input. Not. Therefore, when the monitoring IC detects a plurality of applied voltages having the same potential, the current wraps around through the protection diodes provided inside and outside the monitoring IC, the value fluctuates, and the detection accuracy deteriorates. Has occurred.

The present disclosure has been made in view of the above circumstances, and its main purpose is to provide a voltage detection device capable of accurately detecting a plurality of applied voltages.

The means for solving the above problems is applied to a power supply system including a storage battery and a plurality of systems connected in parallel to the storage battery and to which a voltage between terminals of the storage battery is applied. The voltage detection device is provided with a first voltage dividing circuit that divides the applied voltage of each system and a plurality of input channels, and two inputs input from the first voltage dividing circuit via the input channel. Each of the input channels includes a detection circuit that detects the applied voltage applied to each system based on the potential difference of the signal, and a potential stabilization circuit that outputs a signal to the detection circuit. It has a pair of input terminals, the potential order of the input signals is preset in each of the input terminals, and the first voltage dividing circuit divides the applied voltage of the system by two different voltage dividing ratios. , The voltage division voltage is configured to be output as the input signal to the input terminal of the input channel associated with the system, and each voltage division ratio in the first voltage division circuit is set to each input terminal. Different values are set stepwise for each of the output destination input terminals so that the input signals are in the order corresponding to the potential order, and the first system among the plurality of systems is used. The high-potential side input terminal of the associated input channel and the input terminal to which an input signal having a higher potential than the high-potential side input terminal in the potential order is input, which is the second of the plurality of systems. Between the low potential side input terminal of the input channel associated with the system, a withstand voltage securing channel, which is a plurality of input channels to which the input signal from the first voltage dividing circuit is not input, is provided. The potential stabilization circuit has the potential of the input signal input to the high potential side input terminal associated with the first system with respect to any input terminal of the withstand voltage securing channel, and the first. A signal having a potential between the potential of the input signal input to the low potential side input terminal associated with the system of 2 and the potential of the input signal is output as the input signal.

In the above means, each voltage dividing ratio in the first voltage dividing circuit has a value that is stepwise different for each input terminal to be output so that the input signals input to each input terminal are in the order corresponding to the potential order. It is set. As a result, even if the applied voltage of each system is substantially the same, the input signal input to each input terminal can be gradually increased by the first voltage dividing circuit. Therefore, it is possible to prevent the generation of wraparound current and detect the voltage with high accuracy.

By the way, when the input signal is gradually increased in this way, when the energization from the assembled battery is cut off and the applied voltage of any system becomes zero, the potential difference between the input terminals is the withstand voltage of the detection circuit. There is a risk that it will grow beyond the range of.

Therefore, in the above means, the input terminal on the high potential side of the input channel associated with the first system and the input terminal on which an input signal having a higher potential than the input terminal on the high potential side in the order of potential is input. , A withstand voltage securing channel, which is a plurality of input channels to which an input signal from the first voltage dividing circuit is not input, is provided between the input channel on the low potential side of the input channel associated with the second system. There is. As a result, the range of withstand voltage is increased and the potential difference of the input signal between the input terminals is increased as compared with the case where the withstand voltage securing channel is not provided or when there is only one withstand voltage securing channel. Even so, the failure can be suppressed.

Further, the potential stabilizing circuit of the above means obtains a signal that is a potential between the potential of the input signal input to the high potential side input terminal and the potential of the input signal input to the low potential side input terminal. It is output as an input signal to any of the input terminals of the withstand voltage securing channel. As a result, even if there is a bias in impedance or the like in a plurality of input channels that are channels for ensuring withstand voltage, it is possible to control the potential difference in each input channel that is for ensuring withstand voltage within the range of withstand voltage. It becomes.

The above objectives and other objectives, features and advantages of the present disclosure will be further clarified by the following detailed description with reference to the accompanying drawings. The drawing is
FIG. 1 is a circuit diagram showing an outline of a power supply system. FIG. 2 is a circuit diagram showing an outline of the monitoring IC. FIG. 3 is a circuit diagram showing an outline of a conventional monitoring IC. FIG. 4 is a circuit diagram showing a wraparound current. FIG. 5 is a circuit diagram showing a current flow. FIG. 6 is a circuit diagram showing a current flow. FIG. 7 is a circuit diagram showing a current flow. FIG. 8 is a circuit diagram showing a current flow. FIG. 9 is a circuit diagram showing a current flow. FIG. 10 is a circuit diagram showing a comparative example of a power supply system. FIG. 11 is a diagram showing the relationship between the input signal (input voltage) to the monitoring IC and the voltage between the terminals of the assembled battery in the comparative example. FIG. 12 is a circuit diagram showing a comparative example of a power supply system. FIG. 13 is a diagram showing the relationship between the input signal (input voltage) to the monitoring IC and the voltage between the terminals of the assembled battery in the comparative example. 14A is a diagram showing a time transition of an input signal, and FIG. 14B is a diagram showing a time transition of a potential difference. 15A is a diagram showing a time transition of an input signal, and FIG. 15B is a diagram showing a time transition of a potential difference. 16A is a diagram showing a time transition of an input signal, and FIG. 16B is a diagram showing a time transition of a potential difference. FIG. 17 is a circuit diagram showing a current flow.

Hereinafter, each embodiment that embodies the "voltage detection device" according to the present disclosure will be described with reference to the drawings. In each of the following embodiments, the parts that are the same or equal to each other are designated by the same reference numerals, and the description thereof will be used for the parts having the same reference numerals. Further, in the description of each embodiment and the modified example, not only the combination of the configurations specified clearly but also each embodiment and the modified example can be combined as long as the combination does not cause any trouble.

As shown in FIG. 1, the power supply system applied to a vehicle such as an electric vehicle includes an assembled battery 10 as a storage battery, a plurality of systems 21 and 22 configured by grouping functional groups, an assembled battery 10 and each system. Relay switches SN1, SP1, SN2, SP2 as system switch units that switch between energization and de-energization of the power supply paths 23 and 24 between 21 and 22, and voltage detection that detects the voltage applied to each system 21 and 22 The device 30 is provided.

The assembled battery 10 is a series connection of a plurality of battery cells, and the voltage between the terminals between the positive electrode side terminal 10a and the negative electrode side terminal 10b of the assembled battery 10 is, for example, a high voltage of 100 V or more. The assembled battery 10 serves as a power source for an electric load such as a rotary machine (motor generator), and stores electric power generated by regenerative control of the motor generator. In this embodiment, a lithium ion secondary battery is used as the battery cell.

Each system 21 and 22 is connected in parallel to the assembled battery 10, and the voltage between the terminals of the assembled battery 10 is applied to each. Examples of the systems 21 and 22 include a drive system including an inverter and a motor, a charging system including a power generation device, and the like. The system 21 corresponds to the first system, and the system 22 corresponds to the second system.

Power supply paths 23 and 24 are provided for each system 21 and 22. The power supply paths 23 and 24 include positive electrode side power supply paths 23a and 24a connected to the positive electrode side terminal 10a of the assembled battery 10 and negative electrode side power supply paths 23b and 24b connected to the negative electrode side terminal 10b of the assembled battery 10. Is included.

Further, the positive electrode side power supply path 11a is connected to the positive electrode side terminal 10a of the assembled battery 10, and the negative electrode side power supply path 11b is connected to the negative electrode side terminal 10b of the assembled battery 10. Each power supply path 11, 23, 24 is composed of, for example, a bus bar or the like.

Relay switches SN1, SP1, SN2, SP2 are provided for each system 21 and 22. The relay switches SN1, SP1, SN2, and SP2 switch between the relay switches SP1 and SP2 on the positive electrode side for switching the energization and de-energization of the positive electrode side power supply paths 23a and 24a and the energization and de-energization of the negative electrode side power supply paths 23b and 24b. The relay switches SN1 and SN2 on the negative electrode side are included.

When the relay switches SN1 and SP1 are turned off, the power supply between the system 21 and the assembled battery 10 is cut off, and when the relay switches SN1 and SP1 are turned on, the space between the system 21 and the assembled battery 10 is cut off. Is energized. Similarly, when the relay switches SN2 and SP2 are turned off, the energization between the system 22 and the assembled battery 10 is cut off, and when the relay switches SN2 and SP2 are turned on, the system 22 and the assembled battery 10 are turned on. The space between and is energized.

Further, resistors R61 and R62 of about several MΩ are connected in parallel to the relay switches SN1 and SN2 on the negative electrode side, respectively. These resistances R61 and R62 correspond to the connection circuit 70.

The voltage detection device 30 is a first voltage divider circuit 40 that divides the voltage between the terminals of the assembled battery 10 and the applied voltage of each system 21 and 22 at two different voltage divider ratios, and an input channel from the first voltage divider circuit 40. Separately from the monitoring IC 50 as a detection circuit that detects the applied voltage based on the difference between the two voltage dividers (input signals) input via CH1, CH3, and CH6, and the first voltage divider circuit 40. A second voltage dividing circuit 60 for dividing the voltage between terminals of the assembled battery 10 and a potential stabilizing circuit 80 are provided.

The first voltage divider circuit 40 includes a first series connection body composed of a switch SW0 and resistors R10, R20, R30, a second series connection body composed of a switch SW1 and resistors R11, R21, R31, and a switch SW2. And a third series connector composed of resistors R12, R22, R32.

The first series connection body is provided between the positive electrode side power supply path 11a and the negative electrode side power supply path 11b, and is connected in series from the positive electrode side power supply path 11a in the order of switch SW0, resistor R10, resistor R20, and resistor R30. It is connected. The connection point P11 between the resistance R20 and the resistance R30 is connected to the low potential side input terminal S1 of the input channel CH1 of the monitoring IC50, and the connection point P12 between the resistance R10 and the resistance R20 is the monitoring IC50. It is connected to the high potential side input terminal V1 of the input channel CH1.

In the following, the low potential side input terminal Sx of the input channel CHx (“x” is an integer of 1 to 6, the same applies hereinafter) may be simply referred to as an input terminal Sx. Similarly, the high potential side input terminal Vx of the input channel CHx may be simply referred to as an input terminal Vx.

As a result, when the switch SW0 is turned on, the voltage between the terminals is divided by the first voltage dividing ratio (R30 / (R10 + R20 + R30)) and input to the input terminal S1. When the switch SW0 is turned on, the voltage between the terminals is divided by the second voltage dividing ratio ((R30 + R20) / (R10 + R20 + R30)) and input to the input terminal V1. The voltage divider voltage obtained by dividing the terminal voltage by the first voltage divider ratio is referred to as the voltage divider voltage DS1, and the voltage divider voltage obtained by dividing the terminal voltage by the second voltage divider ratio is referred to as the voltage divider voltage. It may be indicated as DV1.

Further, as shown in FIG. 2, a protection element or a filter is provided between the electric path between the connection point P11 and the input terminal S1 and the electric path between the connection point P12 and the input terminal V1. Has been done. For example, a Zener diode D11 is provided that allows the flow of current from the low potential side input terminal S1 side to the input terminal V1 side and limits the applied voltage between the input terminal V1 and the input terminal S1.

The second series connection body is provided between the positive electrode side power supply path 23a and the negative electrode side power supply path 23b of the system 21, and the switch SW1, the resistor R11, the resistor R21, and the resistor R31 are in this order from the positive electrode side power supply path 23a. It is connected in series with. The connection point P13 between the resistance R21 and the resistance R31 is connected to the low potential side input terminal S3 of the input channel CH3 of the monitoring IC50, and the connection point P14 between the resistance R11 and the resistance R21 is the monitoring IC50. It is connected to the high potential side input terminal V3 of the input channel CH3.

As a result, when the relay switches SN1 and SP1 and the switch SW1 are turned on, the voltage applied to the system 21 is divided by the third voltage dividing ratio (R31 / (R11 + R21 + R31)) and input to the input terminal S3. When the relay switches SN1 and SP1 and the switch SW1 are turned on, the voltage applied to the system 21 is divided by the fourth voltage dividing ratio ((R31 + R21) / (R11 + R21 + R31)) and input to the input terminal V3. ..

The voltage applied to the system 21 is the potential difference (voltage) actually generated between the positive electrode side power supply path 23a and the negative electrode side power supply path 23b due to the application of the voltage between the terminals of the assembled battery 10. That is. Further, the voltage divider voltage obtained by dividing the voltage applied to the system 21 by the third voltage divider ratio is referred to as the voltage divider voltage DS3, and the voltage applied to the system 21 is divided by the fourth voltage divider ratio. The voltage may be referred to as a voltage divider voltage DV3.

Further, as shown in FIG. 2, a protection element or a filter is provided between the electric path between the connection point P13 and the input terminal S3 and the electric path between the connection point P14 and the input terminal V3. Has been done. For example, a Zener diode D13 is provided that allows the flow of current from the input terminal S3 side to the input terminal V3 side and limits the applied voltage between the input terminal V3 and the input terminal S3.

The third series connection body is provided between the positive electrode side power supply path 24a and the negative electrode side power supply path 24b of the system 22, and the switch SW2, the resistor R12, the resistor R22, and the resistor R32 are in this order from the positive electrode side power supply path 24a. It is connected in series with. The connection point P15 between the resistance R22 and the resistance R32 is connected to the low potential side input terminal S6 of the input channel CH6 of the monitoring IC50, and the connection point P16 between the resistance R12 and the resistance R22 is the monitoring IC50. It is connected to the high potential side input terminal V6 of the input channel CH6.

As a result, when the relay switches SN2 and SP2 and the switch SW2 are turned on, the voltage applied to the system 22 is divided by the fifth voltage dividing ratio (R32 / (R12 + R22 + R32)) and input to the input terminal S6. When the relay switches SN2 and SP2 and the switch SW2 are turned on, the voltage applied to the system 22 is divided by the sixth voltage dividing ratio ((R32 + R22) / (R12 + R22 + R32)) and input to the input terminal V6. ..

The voltage applied to the system 22 is the potential difference (voltage) actually generated between the positive electrode side power supply path 24a and the negative electrode side power supply path 24b due to the application of the voltage between the terminals of the assembled battery 10. That is. Further, the voltage divider voltage obtained by dividing the voltage applied to the system 22 by the fifth voltage divider ratio is referred to as the voltage divider voltage DS6, and the voltage applied to the system 22 is divided by the sixth voltage divider ratio. The voltage may be referred to as a voltage divider voltage DV6.

Further, as shown in FIG. 2, a protective element or a filter is provided between the electric path between the connection point P15 and the input terminal S6 and the electric path between the connection point P16 and the input terminal V6. Has been done. For example, a Zener diode D16 is provided that allows the flow of current from the input terminal S6 side to the input terminal V6 side and limits the applied voltage between the input terminal V6 and the input terminal S6.

As shown in FIG. 2, the monitoring IC50 uses one having at least six input channels CH1 to CH6. However, the input channel CH beyond that including the input channel CH6 has the input terminal short-circuited and is not used for the voltage detection this time. Therefore, in the following description, the range of input channels CH1 to CH6 will be described. Each input channel CH1 to CH6 has a pair of input terminals (pin terminals) S1 to S6 and V1 to V6, respectively. The pair of input terminals S1 to S6 and V1 to V6 have high potential side input terminals V1 to V6 and low potential side input terminals S1 to S6. The input channels CH1 to CH6 are arranged in order from the one with the smallest number, that is, in the order of CH1 → CH2 → ... → CH6. Further, in each input channel CH1 to CH6, the low potential side input terminals S1 to S6 → the high potential side input terminals V1 to V6 are arranged in this order. Therefore, the input terminals S1 to S6 and V1 to V6 are arranged in the order of S1 → V1 → S2 → V2 → ... → S6 → V6.

The monitoring IC 50 includes a multiplexer 51, a differential amplifier circuit 52, an AD converter 53, and semiconductor switches SW51 to SW56 such as MOSFETs. The input terminals S1 to S6 and V1 to V6 are connected to the differential amplifier circuit 52 via the multiplexer 51. Specifically, each input terminal V1 to V6 is connected to the non-inverting input terminal side of the differential amplifier circuit 52 via the multiplexer 51, and each input terminal S1 to S6 is connected to the differential amplifier circuit 52 via the multiplexer 51. The inverting input terminal side of is connected.

The multiplexer 51 outputs the voltage input to the input terminals S1 to S6 and V1 to V6 of the input channels CH1 to CH6 selected from the input channels CH1 to CH6 to the differential amplifier circuit 52.

The differential amplifier circuit 52 detects the voltage (potential difference) between the non-inverting input terminal and the inverting input terminal and outputs it as an analog signal to the AD converter 53. The AD converter 53 converts the analog signal into a digital signal and outputs it to the arithmetic unit 54 included in the monitoring IC 50. The arithmetic unit 54 calculates the voltage between the terminals of the assembled battery 10 and the voltage applied to each system 21 and 22 based on the input potential difference (digital signal).

Specifically, the arithmetic unit 54 has a first voltage divider ratio (R30 / (R10 + R20 + R30)), a second voltage divider ratio ((R30 + R20) / (R10 + R20 + R30)) of the first voltage divider circuit 40 to the voltage between terminals, and The voltage between terminals is calculated based on the potential difference between the voltage divider voltage DS1 and the voltage divider voltage DV1. In the monitoring IC 50 of the present embodiment, the differential amplifier circuit 52 and the AD converter 53 are integrated in the monitoring IC 50, and the total error is suppressed by calibration or correction. Therefore, the voltage between terminals can be calculated accurately.

Similarly, the arithmetic unit 54 has a third voltage divider ratio (R31 / (R11 + R21 + R31)), a fourth voltage divider ratio ((R31 + R21) / (R11 + R21 + R31)) of the first voltage divider circuit 40 with respect to the voltage applied to the system 21. And the voltage applied to the system 21 is calculated based on the potential difference between the voltage dividing voltage DS3 and the voltage dividing voltage DV3. The same applies to the calculation of the voltage applied to the system 22. It is not necessary to provide the arithmetic unit 54 in the monitoring IC 50, and the arithmetic unit 54 may be provided in the external device.

The semiconductor switches SW51 to SW56 are provided so as to be able to switch between energization and energization cutoff between adjacent input terminals S1 to S6, respectively. For example, the semiconductor switch SW51 is provided between the input terminal S1 and the input terminal S2, and is configured to be able to switch between energization and energization cutoff between the terminals. The same applies to the semiconductor switches SW52 to SW56.

Further, diodes D51 to D56 are connected in parallel to the semiconductor switches SW51 to SW56, respectively. The diodes D51 to D56 may be parasitic diodes of the semiconductor switches SW51 to SW56. Each diode D51 is arranged so as to allow current to flow from the input terminal S1 having a small number to the input terminal S2 having a large number. The same applies to the diodes D52 to D56.

The arithmetic unit 54 is configured to be able to control the switching of the semiconductor switches SW51 to SW56 and the selection of the input channels CH1 to CH6 by the multiplexer 51 in addition to the above-mentioned arithmetic.

As shown in FIG. 1, in the second voltage dividing circuit 60, the switch SW3, the resistor R42, and the resistor R52 are connected in series in this order between the positive electrode side power supply path 11a and the negative electrode side power supply path 11b. Further, one end of the series connection body of the resistance R41, the resistance R55 and the resistance R51 is connected between the switch SW3 and the resistance R42 so as to be in parallel with the resistance R42 and the resistance R52, and the other end is the negative electrode side power supply path. It is connected to 11b.

The connection point P21 between the resistor R55 and the resistor R51 is connected to the connection point P13 between the resistor R21 and the resistor R31 of the first voltage dividing circuit 40 via the diode D1. The diode D1 is connected so as to allow the flow of current from the side of the second voltage divider circuit 60 to the side of the first voltage divider circuit 40. That is, when the switch SW3 is turned on, the voltage between the terminals of the assembled battery 10 is divided by the seventh voltage dividing ratio (R51 / (R41 + R55 + R51)) based on the resistors R41, R55, R51, and is connected via the diode D1. It is configured to be applicable to the point P13. The voltage divider voltage obtained by dividing the voltage between the terminals by the seventh voltage divider ratio may be referred to as a voltage divider voltage DS3min. The voltage dividing voltage DS3min is an input signal input to the input terminal S3 when the energization of the system 21 is cut off.

The connection point P22 between the resistor R42 and the resistor R52 is connected to the connection point P15 between the resistor R22 and the resistor R32 of the first voltage dividing circuit 40 via the diode D2. The diode D2 is connected so as to allow the flow of current from the side of the second voltage divider circuit 60 to the side of the first voltage divider circuit 40. That is, when the switch SW3 is turned on, the voltage between the terminals of the assembled battery 10 is divided by the eighth voltage dividing ratio (R52 / (R42 + R52)) based on the resistors R42 and R52, and the connection point P15 is divided via the diode D2. It is configured to be applicable to. The voltage divider voltage obtained by dividing the voltage between the terminals by the eighth voltage divider ratio may be referred to as a voltage divider voltage DS6min. The voltage dividing voltage DS6min is an input signal input to the input terminal S6 when the energization of the system 22 is cut off.

The potential stabilization circuit 80 is composed of a series connector of a resistor R53 and a resistor R54, one end of which is connected to the second voltage dividing circuit 60 and the other end of which is connected to the input terminal V3. More specifically, one end of the potential stabilization circuit 80 is connected between the resistance R41 and the resistance R55 in the second voltage divider circuit 60, and the other end is the resistance R11 and the resistance R21 of the first voltage divider circuit 40. It is connected to the connection point P14 between. Further, the connection point P17 between the resistance R53 and the resistance R54 is connected to the input terminal S5 of the input channel CH5 of the monitoring IC50.

By the way, as shown in FIG. 3, the monitoring IC50 is originally used to detect the voltage of each battery cell C11 to C15 constituting the assembled battery. The semiconductor switches SW51 to SW55 are provided for equalization discharge of the battery cells C11 to C15. That is, the monitoring IC50 has been developed on the premise of detecting the voltage of the battery cells C11 to C15 connected in series. Therefore, for example, the circuit configuration is set on the premise that the potential is gradually increased for each of the input channels CH1 to CH5. Specifically, the potential input in the order of input terminal S1 → input terminal V1, S2 → input terminal V2, S3 → input terminal V3, S4 → input terminal V4, S5 → input terminal V5 gradually increases. Is assumed.

Therefore, when trying to detect a voltage having the same potential, for example, as shown in FIG. 4, the voltage between the terminals of the assembled battery 10 and the applied voltage of the systems 21 and 22 are set to each input channel via a voltage dividing circuit. When inputting to CH1, CH3, CH5, there are the following problems. That is, when the voltages input to the input channels CH1, CH3, and CH5 are substantially the same, the diodes D11 to D15 provided outside the monitoring IC50, or the monitoring IC50, as shown by the broken line arrow shown in FIG. A wraparound current may be generated via the diodes D51 to D56 of the semiconductor switches SW51 to SW56 inside.

Further, when the input voltage to the input channel CH1 is larger than the input voltage to the input channels CH3 and CH5, a wraparound current may be generated inside the monitoring IC50. Further, even when the applied voltage of any of the systems 21 and 22 becomes zero by turning off the relay switches SN1, SP1, SN2 and SP2, a wraparound current is similarly generated inside the monitoring IC50. there is a possibility. This causes a problem that a voltage detection error occurs.

Therefore, a first voltage dividing circuit 40 and a second voltage dividing circuit 60 are provided, and each voltage dividing ratio is set as described below. Hereinafter, it will be described in detail. As described above, the monitoring IC 50 is provided with a plurality of input channels CH1 to CH6, and the potential order of the input signals is preset in the input terminals S1 to S6 and V1 to V6 of the input channels CH1 to CH6. ing. The potential order is the order of the potentials of the input signals in which an unintended wraparound current is prevented between the input channels CH1 and CH6, at least inside the monitoring IC50. The unintended wraparound current is, for example, a current flowing through the diodes D51 to D56 and the like.

In this embodiment, the potential order of the input signals is in the order of input terminal S1 → input terminal V1, S2 → input terminal V2, S3 → input terminal V3, S4 → input terminal V4, S5 → input terminal V5, S6 → input terminal V6. Is stipulated. That is, the potential order is determined so that the potential increases stepwise for each of the input channels CH1 to CH6. The potential order does not have to be reversed, and for example, input signals having the same potential may be input at the input terminals V3 and S4 and the input terminal V4. This is because even in such a case, an unintended wraparound current is prevented.

Then, as shown in FIGS. 1 and 2, the input channels CH1, CH3, and CH6 are associated with the assembled battery 10, the system 21, and 22, respectively. The first voltage dividing circuit 40 divides the voltage between the terminals of the assembled battery 10 at two different voltage dividing ratios, and outputs the voltage to the input terminals S1 and V1 of the input channel CH1 associated with the assembled battery 10, respectively. Similarly, the first voltage divider circuit 40 divides the voltage applied to the system 21 by two different voltage dividing ratios when the relay switches SP1 and SN1 are turned on, and the input channel CH3 associated with the system 21 Is output to each of the input terminals S3 and V3. Similarly, the first voltage divider circuit 40 divides the voltage applied to the system 22 by two different voltage dividing ratios when the relay switches SP2 and SN2 are turned on, and the input channel CH6 associated with the system 22 is used. Output to the input terminals S6 and V6 of.

Then, the first voltage dividing circuit 40 divides the voltage for each input terminal S1, V1, S3, V3, S6, V6 of the input channels CH1, CH3, CH6 at a stepwise different voltage dividing ratio, and outputs the voltage. I try to do it. More specifically, the potential of the input signal (voltage dividing voltage) to be input is gradually increased in the order of input terminal S1 → input terminal V1 → input terminal S3 → input terminal V3 → input terminal S6 → input terminal V6. Each voltage dividing ratio of the first voltage dividing circuit 40 is set.

Specifically, in the first voltage divider circuit 40, the second voltage divider ratio of the voltage divider voltage DV1 that can be input to the high potential side input terminal V1 of the input channel CH1 is the low potential side input terminal of the input channel CH1. The voltage dividing voltage that can be input to S1 is set to be larger than the first voltage dividing ratio of DS1. Similarly, in the input channels CH3 and CH5, the fourth voltage division ratio is set to be one step larger than the third voltage division ratio, and the sixth voltage division ratio is set to be larger than the fifth voltage division ratio. ..

Further, among the input channels CH1, CH3, and CH6 used for voltage detection, between the input channel CH1 and the input channel CH3 having different ranks in the potential order, and between the input channel CH3 and the input channel CH6 in advance. The voltage division ratio is set stepwise so that a potential difference of more than a predetermined value is generated. That is, in the first voltage divider circuit 40, the third voltage divider ratio of the voltage divider voltage DS3 that can be input to the low potential side input terminal S3 of the input channel CH3 can be input to the high potential side input terminal V1 of the input channel CH1. The voltage dividing voltage is set to be larger than the second voltage dividing ratio of DV1. Similarly, the fifth voltage division ratio is set to be larger than the fourth voltage division ratio.

That is, the first pressure division ratio (R30 / (R10 + R20 + R30)) <second pressure division ratio (R (30 + R20) / (R10 + R20 + R30)) <third pressure division ratio (R31 / (R11 + R21 + R31)) <fourth pressure division ratio ( (R31 + R21) / (R11 + R21 + R31)) <Fifth voltage division ratio (R32 / (R12 + R22 + R32)) <Sixth voltage division ratio ((R32 + R22) / (R12 + R22 + R32)) There is. Then, the values of the resistors R10, R20, R30, R11, R21, R31, R12, R22, and R32 are set so that the voltage division ratios are set stepwise.

Further, a voltage drop occurs depending on the current flowing in each negative electrode side power supply path 11b, 23b, 24b. For example, when charging the assembled battery 10, a voltage drop occurs due to the charging current. Therefore, the first voltage dividing ratio, the third voltage dividing ratio, and the fifth voltage dividing ratio in the first voltage dividing circuit 40 are voltage drops calculated based on the current amounts and impedances of the negative electrode side power supply paths 11b, 23b, and 24b. It is set in consideration of the amount.

Specifically, the maximum drop amounts N0max, N1max, and N2max from the circuit reference (ground terminal N0) of the monitoring IC50 are calculated from the impedance with the current amounts of the negative electrode side power supply paths 11b, 23b, and 24b, respectively. Then, the first voltage dividing ratio is set so that the maximum drop amount N0max <voltage dividing voltage DS1. Similarly, the third voltage dividing ratio is set so that the maximum drop amount N1max <voltage dividing voltage DS3. Similarly, the fifth voltage dividing ratio is set so that the maximum drop amount N2max <voltage dividing voltage DS6.

Further, the second voltage dividing circuit 60 is configured to divide the voltage between terminals at a stepwise different voltage dividing ratio for each of the systems 21 and 22. Specifically, the seventh voltage divider ratio (R51 / (R41 + R55 + R51)) of the voltage divider DS3 min is smaller than the third voltage divider ratio (R31 / (R11 + R21 + R31)) of the voltage divider DS3, and the first voltage divider circuit. In 40, it is set larger than the second voltage dividing ratio ((R30 + R20) / (R10 + R20 + R30)) which is one step smaller than the third voltage dividing ratio.

Further, the eighth voltage dividing ratio (R52 / (R42 + R52)) of the voltage dividing voltage DS6min is smaller than the fifth voltage dividing ratio (R32 / (R12 + R22 + R32)) of the voltage dividing voltage DS6, and the first voltage dividing circuit 40 Is set larger than the fourth voltage dividing ratio ((R31 + R21) / (R11 + R21 + R31)), which is one step smaller than the fifth voltage dividing ratio.

Then, the second voltage dividing circuit 60 is set for the systems 21 and 22 in the presence of the systems 21 and 22 in which the energization with the assembled battery 10 is cut off by the relay switches SN1, SP1, SN2 and SP2. The voltage dividing voltages DS3min and DS6min are configured to be output to the low potential side input terminals S3 and S6 of the input channels CH3 and CH6.

Specifically, the connection point P21 between the resistor R55 and the resistor R51 is connected to the connection point P13 between the resistor R21 and the resistor R31 of the first voltage dividing circuit 40 via the diode D1. Therefore, when the applied voltage of the system 21 becomes zero, the second voltage divider circuit 60 also has the voltage divider voltage DS3 zero, so that the voltage divider voltage DS3min is output to the input terminal S3 via the diode D1. It will be. At that time, the voltage dividing voltage DS3min is also input to the input terminals V3, S4, and V4 via the diodes D13 and D53.

Since the voltage dividing voltage DS3min is input via the diode D1, the voltage actually input to the input terminals S3, V3, S4, and V4 is the voltage dividing voltage DS3min in consideration of the forward voltage drop due to the diode D1. -The voltage drop is Vf. However, in the present embodiment, the voltage is small enough not to affect the disclosure. Therefore, for convenience of explanation, the voltage drop Vf among the voltages input to the input terminals S3, V3, S4, and V4 is described below. The description of is omitted.

Similarly, the connection point P22 between the resistor R42 and the resistor R52 is connected to the connection point P15 between the resistor R22 and the resistor R32 of the first voltage dividing circuit 40 via the diode D2. Therefore, when the applied voltage of the system 22 becomes zero, the second voltage dividing circuit 60 outputs the voltage dividing voltage DS6min to the input terminal S6 via the diode D2. At that time, the voltage dividing voltage DS6min is also input to the input terminal V6 via the diodes D16 and D56.

Since the voltage dividing voltage DS6min is input via the diode D2, the voltage actually input to the input terminals S6 and V6 is the voltage dividing voltage DS6min-voltage drop Vf in consideration of the voltage drop due to the diode D2. ing. However, in the present embodiment, since it is small enough not to affect the disclosure, the description of the voltage drop Vf among the voltages input to the input terminals S6 and V6 is omitted below for convenience of explanation. do.

As described above, the second voltage divider circuit 60 divides the voltage between terminals with respect to the input channels CH3 and CH6 associated with the systems 21 and 22 in which the energization with the assembled battery 10 is cut off. DS3min and DS6min are output as input signals. The seventh voltage dividing ratio in the second voltage dividing circuit 60 is such that the input signals input to the input terminal S3 of the input channel CH3 to be output are in the order corresponding to the potential order. It is set to be equal to or less than the third voltage dividing ratio set by the first voltage dividing circuit 40 in order to generate an input signal to the input terminal S3. That is, the seventh voltage division ratio is larger than the second voltage division ratio and equal to or less than the third voltage division ratio.

Similarly, the eighth voltage dividing ratio in the second voltage dividing circuit 60 is a voltage dividing ratio such that the input signals input to the input terminal S6 of the input channel CH6 as the output destination are in the order corresponding to the order of potential. It is set to be equal to or less than the fifth voltage dividing ratio set in the first voltage dividing circuit 40 in order to generate an input signal to the input terminal S6. That is, the eighth voltage division ratio is larger than the fourth voltage division ratio and equal to or less than the fifth voltage division ratio.

Next, the operation of the voltage detection device 30 will be described with reference to FIGS. 5 to 9. FIG. 5 is a diagram showing the operation of the voltage detection device 30 and the current flow when the relay switches SN1, SP1, SN2, and SP2 are turned on. In FIG. 5, the broken line indicates the current flow.

As shown in FIG. 5, a voltage divider voltage DS1 in which the voltage between the terminals is divided by the first voltage divider ratio is input to the input terminal S1. The voltage dividing voltage DV1 in which the voltage between the terminals is divided by the second voltage dividing ratio is input to the input terminal V1. The voltage divider DS3, in which the voltage applied to the system 21 is divided by the third voltage divider ratio, is input to the input terminal S3. The voltage divider voltage DV3, in which the voltage applied to the system 21 is divided by the fourth voltage divider ratio, is input to the input terminal V3. A voltage divider DS6 in which the voltage applied to the system 22 is divided by the fifth voltage divider ratio is input to the input terminal S6. The voltage dividing voltage DV6 in which the voltage applied to the system 22 is divided by the sixth voltage dividing ratio is input to the input terminal V6. The magnitude relationship of each voltage dividing voltage is DS1 <DV1 <DS3 <DV3 <DS6 <DV6.

As a result, the potential of the input signal (voltage division voltage) that is input stepwise in the order of input terminal S1 → input terminal V1 → input terminal S3 → input terminal V3 → input terminal S6 → input terminal V6 increases. That is, the order is according to the potential order of the input signals. Therefore, it is possible to prevent the current from wrapping around through the diodes D11, D13, D16, D51, D53, and D56.

Therefore, the monitoring IC 50 can accurately detect the voltage between the terminals based on the two voltage dividing voltages DS1 and DV1 input to the input terminals S1 and V1. Similarly, the monitoring IC 50 can accurately detect the voltage applied to the system 21 based on the two voltage dividing voltages DS3 and DV3 input to the input terminals S3 and V3. The voltage applied to the system 22 can be detected with high accuracy as well.

The seventh voltage dividing ratio in the second voltage dividing circuit 60 is smaller than the third voltage dividing ratio in the first voltage dividing circuit 40, and the voltage between terminals and the voltage applied to the system 21 are almost the same. Therefore, the voltage dividing voltage DS3min obtained by dividing the voltage between terminals at the seventh voltage dividing ratio is smaller than the voltage dividing voltage DS3 obtained by dividing the voltage applied to the system 21 at the third voltage dividing ratio. Therefore, the voltage dividing voltage DS3min from the second voltage dividing circuit 60 is not input to the input terminal S3 (the voltage dividing voltage DS3min does not appear as an input signal), and the voltage dividing voltage DS3 from the first voltage dividing circuit 40 is used. , Is input to the input terminal S3.

Similarly, the eighth voltage dividing ratio in the second voltage dividing circuit 60 is smaller than the fifth voltage dividing ratio in the first voltage dividing circuit 40, and the voltage between terminals and the voltage applied to the system 22 are almost the same. Therefore, the voltage dividing voltage DS6min obtained by dividing the voltage between terminals at the eighth voltage dividing ratio is smaller than the voltage dividing voltage DS6 obtained by dividing the voltage applied to the system 22 at the fifth voltage dividing ratio. Therefore, the voltage dividing voltage DS6min from the second voltage dividing circuit 60 is not input to the input terminal S6 (the voltage dividing voltage DS6min does not appear as an input signal), and the voltage dividing voltage DS6 from the first voltage dividing circuit 40 is used. , Is input to the input terminal S6.

FIG. 6 is a diagram showing the operation of the voltage detection device 30 and the current flow when the relay switches SN1 and SP1 are turned off and the relay switches SN2 and SP2 are turned on. In FIG. 6, the broken line indicates the current in the first voltage divider circuit 40. Further, the current in the second voltage dividing circuit 60 is shown by the alternate long and short dash line.

As shown in FIG. 6, a voltage divider voltage DS1 in which the voltage between the terminals is divided by the first voltage divider ratio is input to the input terminal S1. The voltage dividing voltage DV1 in which the voltage between the terminals is divided by the second voltage dividing ratio is input to the input terminal V1. A voltage divider DS6 in which the voltage applied to the system 22 is divided by the fifth voltage divider ratio is input to the input terminal S6. The voltage dividing voltage DV6 in which the voltage applied to the system 22 is divided by the sixth voltage dividing ratio is input to the input terminal V6.

On the other hand, since the energization from the assembled battery 10 to the system 21 is cut off by the premise, the applied voltage to the system 21 is 0V. Therefore, the voltage dividing voltage from the first voltage dividing circuit 40 to the input terminal S3 is also 0V. Since the voltage divider DS3min by the second voltage divider circuit 60 is higher than 0V, as shown by the one-point chain line, the positive electrode side terminal 10a of the assembled battery 10 → switch SW3 → resistor R41 → resistor R55 → diode D1 → resistor. A current flows through the path of R31 → resistor R61 → negative electrode side terminal 10b of the assembled battery 10.

As a result, the voltage divider voltage DS3min in which the voltage between the terminals is divided by the seventh voltage divider ratio is input to the input terminal S3. The voltage dividing voltage DS3min is input to the input terminals V3, S4, and V4 via the resistor R21 and the like. The magnitude relationship of each voltage dividing voltage is DS1 <DV1 <DS3min <DS6 <DV6.

As a result, the voltage dividing voltage that is input stepwise in the order of input terminal S1 → input terminal V1 → input terminal S3, V3, S4, V4 → input terminal S6 → input terminal V6 increases. That is, the input signal is input according to the potential order. Therefore, it is possible to prevent the current from wrapping around through the diodes D11, D13, D16, D51, D53, D56 and the like. Therefore, the monitoring IC 50 can accurately detect the voltage between terminals and the voltage applied to the system 22.

FIG. 7 is a diagram showing the operation of the voltage detection device 30 and the current flow when the relay switches SN2 and SP2 are turned off and the relay switches SN1 and SP1 are turned on. In FIG. 7, the broken line indicates the current in the first voltage divider circuit 40. Further, the current in the second voltage dividing circuit 60 is shown by the alternate long and short dash line.

As shown in FIG. 7, a voltage divider voltage DS1 in which the voltage between the terminals is divided by the first voltage divider ratio is input to the input terminal S1. The voltage dividing voltage DV1 in which the voltage between the terminals is divided by the second voltage dividing ratio is input to the input terminal V1. The voltage divider DS3, in which the voltage applied to the system 21 is divided by the third voltage divider ratio, is input to the input terminal S3. The voltage divider voltage DV3, in which the voltage applied to the system 21 is divided by the fourth voltage divider ratio, is input to the input terminal V3.

On the other hand, since the energization from the assembled battery 10 to the system 22 is cut off by the premise, the voltage between the terminals S6 and V6 of the input terminals S6 and V6 is divided by the eighth voltage division ratio for the same reason as described in FIG. The divided voltage division voltage DS6min is input. The magnitude relationship of each voltage dividing voltage is DS1 <DV1 <DS3 <DV3 <DS6min.

As a result, the potential of the voltage dividing voltage that is input stepwise in the order of input terminal S1 → input terminal V1 → input terminal S3 → input terminal V3 → input terminals S6 and V6 increases. That is, the input signal is input according to the potential order. Therefore, it is possible to prevent the current from wrapping around through the diodes D11, D13, D16, D51, D53, D56 and the like. Therefore, the monitoring IC 50 can accurately detect the voltage between terminals and the voltage applied to the system 22.

FIG. 8 is a diagram showing the operation of the voltage detection device 30 and the current flow when the relay switches SN1, SP1, SN2, and SP2 are turned on and the switch SW0 is stuck off (cannot be turned on). In FIG. 8, the broken line indicates the current flow.

As shown in FIG. 8, the voltage dividing voltage DS3 in which the voltage applied to the system 21 is divided by the third voltage dividing ratio is input to the input terminal S3. The voltage divider voltage DV3, in which the voltage applied to the system 21 is divided by the fourth voltage divider ratio, is input to the input terminal V3. A voltage divider DS6 in which the voltage applied to the system 22 is divided by the fifth voltage divider ratio is input to the input terminal S6. The voltage dividing voltage DV6 in which the voltage applied to the system 22 is divided by the sixth voltage dividing ratio is input to the input terminal V6. On the other hand, since the switch SW0 cannot be turned on, the input terminals S1 and V1 have the same potential as the negative electrode side power supply path 11b, that is, 0V.

As a result, the voltage dividing voltage that is input stepwise in the order of input terminal S1, V1 → input terminal S3 → input terminal V3 → input terminal S6 → input terminal V6 increases. That is, the input signal is input according to the potential order. Therefore, it is possible to prevent the current from wrapping around through the diodes D11, D13, D16, D51, D53, and D56. Therefore, the monitoring IC 50 can accurately detect the voltage applied to the systems 21 and 22. Further, the monitoring IC 50 can detect a failure of the switch SW0.

FIG. 9 is a diagram showing the operation of the voltage detection device 30 and the current flow when the relay switches SN1, SP1, SN2, and SP2 are turned off. In FIG. 9, the current in the second voltage dividing circuit 60 is shown by the alternate long and short dash line.

As shown in FIG. 9, a voltage divider voltage DS1 in which the voltage between the terminals is divided by the first voltage divider ratio is input to the input terminal S1. The voltage dividing voltage DV1 in which the voltage between the terminals is divided by the second voltage dividing ratio is input to the input terminal V1.

On the other hand, since the energization from the assembled battery 10 to the systems 21 and 22 is cut off by the premise, the voltage between the terminals S3, V3, S4 and V4 has a seventh voltage for the same reason as described above. The voltage dividing voltage DS3min divided by the voltage dividing ratio is input. Further, the voltage dividing voltage DS6min in which the voltage between the terminals is divided by the eighth voltage dividing ratio is input to the input terminals S6 and V6. The magnitude relationship of each voltage dividing voltage is DS1 <DV1 <DS3min <DS6min.

As a result, the voltage dividing voltage that is input stepwise in the order of input terminal S1 → input terminal V1 → input terminal S3, V3, S4, V4 → input terminal S6, V6 increases. That is, the input signal is input according to the potential order. Therefore, it is possible to prevent the current from wrapping around through the diodes D11, D13, D16, D51, D53, D56 and the like. Therefore, the monitoring IC 50 can accurately detect the voltage between terminals.

As described above, since the voltage detection device 30 operates, the monitoring IC 50 can accurately detect the voltage between terminals and the applied voltage.

By the way, the monitoring IC 50 has a withstand voltage. Specifically, when a potential difference of a predetermined value or more occurs between the input channels CH1 to CH6, the semiconductor switches SW51 to SW56 and the like fail. The withstand voltage of each input channel CH1 to CH6 is predetermined by the withstand voltage of a circuit element provided between each input channel CH1 to CH6 such as semiconductor switches SW51 to SW56.

Therefore, the first voltage dividing circuit 40 and the second voltage dividing circuit 60 are set to the input terminals S1 to S6 so as to be within the withstand voltage range of each input channel CH1 to CH6 (so that a large potential difference does not occur). It is necessary to input an appropriate input signal (voltage dividing voltage) for each of V1 to V6. However, in the voltage detection device 30 as shown in the comparative example of FIG. 10, the potential difference may increase and exceed the withstand voltage range depending on the on / off state of the relay switches SN1, SP1, SN2, SP2.

In the voltage detection device 30 shown in the comparative example of FIG. 10, the potential stabilization circuit 80 does not exist, the input channel CH5 is associated with the system 22, and the voltage dividing voltages DS6 and DV6 are connected to the input terminals S5 and V5. It has the same configuration as the voltage detection device 30 of FIG. 1 except that it is input. In the comparative example of FIG. 10, since the input channel CH5 is associated with the system 22, the input channel CH5 associated with the system 22 and the input channel CH3 associated with the system 21 are separated from each other. Only the input channel CH4 will be present.

Explain in detail the situation where the pressure resistance range is exceeded. For example, in the voltage detection device 30 shown in the comparative example, when the relay switches SN1, SP1, SN2, and SP2 are turned on, each voltage dividing voltage is as shown in FIG. 11A. In FIG. 11, the horizontal axis is the magnitude of the voltage between terminals of the assembled battery 10, and the vertical axis is the potential of the input signal (monitoring IC input voltage). In this case, by appropriately setting the voltage dividing ratio in the first voltage dividing circuit 40, the potential differences of the input signals that differ by one in the potential order can be set within the range of withstand voltage.

Specifically, by appropriately setting the voltage dividing ratio in the first voltage dividing circuit 40, the withstand voltage of the potential difference DV6-DS6, the potential difference DS6-DV3, the potential difference DV3-DS3, the potential difference DS3-DV1, and the potential difference DV1-DS1 are respectively. Can be within the range of.

Further, when the relay switches SN2 and SP2 are turned off and the relay switches SN1 and SP1 are turned on, each voltage dividing voltage is as shown in FIG. 11 (b). In this case, the input signal input to the input terminals V5 and S5 has a voltage dividing voltage of DS6min, but the potential difference DS6min-DV3 has a smaller difference than the potential difference DS6-DV3. Can be within range.

On the other hand, when the relay switches SN1 and SP1 are turned off and the relay switches SN2 and SP2 are turned on, each voltage dividing voltage is as shown in FIG. 11 (c). In this case, the input signal input to the input terminals V3 and S3 has a voltage dividing voltage of DS3min. Therefore, the potential difference applied to the input channel CH4 changes from the potential difference DS6-DV3 to the potential difference DS6-DS3min, and the potential difference becomes large.

Similarly, when all the relay switches SN1, SP1, SN2, and SP2 are turned off, each voltage dividing voltage is as shown in FIG. 11 (d). In this case, the input signal input to the input terminals V3 and S3 has a voltage dividing voltage DS3min, and the input signal input to the input terminals V5 and S5 has a voltage dividing voltage DS6min. Therefore, the potential difference applied to the input channel CH4 changes from the potential difference DS6-DV3 to the potential difference DS6min-DS3min, and the potential difference becomes large.

As described above, when the relay switches SN1 and SP1 are turned off, the potential difference of the input signal increases, and depending on the magnitude of the voltage between the terminals of the assembled battery 10, the withstand voltage of the monitoring IC 50 may be exceeded.

As a first method for avoiding this, the resistances of the first voltage dividing circuit 40 and the second voltage dividing circuit 60 are all increased, and the voltage dividing voltage itself applied to the monitoring IC 50 is decreased. It is conceivable to reduce the potential difference. However, this method has a problem that the dynamic range of voltage detection becomes small, the influence of an error becomes large, and the detection accuracy deteriorates.

Further, as a second method, as shown in FIG. 12, a Zener diode D14 is provided between the input terminal S5 and the input terminal V3, and when a potential difference of a predetermined value or more occurs, it is shown by a broken line. , A method of suppressing the potential difference by passing a current from the input terminal S5 to the input terminal V3 can be considered. However, in this method, a wraparound current from the input channel CH5 to the input channel CH3 is allowed to be generated, and the detection accuracy of the applied voltage of the system 22 is deteriorated.

Further, as a third method, as shown in FIG. 13, the voltage division ratio is adjusted without changing the circuit configuration, and each potential difference of the potential difference DS6-DS6min, the potential difference DS6min-DV3, the potential difference DS3-DS3min, and the potential difference DS3min-DV1. It is conceivable to make it as small as possible. In this case, as shown in FIG. 13B, even if the relay switches SN1 and SP1 are turned off and the potential difference DS6-DV3 becomes the potential difference DS6-DS3min (or the potential difference DS6min-DS3min), the potential difference is not increased. Can be.

However, in order to reduce the potential differences of the potential difference DS6-DS6min, the potential difference DS6min-DV3, the potential difference DS3-DS3min, and the potential difference DS3min-DV1 as much as possible, the potentials of DV1 <DS3min <DS3 and DV3 <DS6min <DS6 are affected by the circuit tolerance. It is difficult to maintain the order.

Therefore, in the present embodiment, as shown in FIG. 1, as a first device, the input terminal V3 of the input channel CH3 associated with the system 21 and the input of the input channel CH6 associated with the system 22 A plurality of input channels CH4 and CH5 from which the input signal from the first voltage dividing circuit 40 is not input are provided between the terminal S6 and the input channels CH4 and CH5 as read-abandoned channels (channels for ensuring withstand voltage). That is, the range of withstand voltage is simply increased by setting a plurality of input channels between the input terminals where the potential difference becomes large and increasing the number of intervening circuit elements. That is, it is not used for voltage detection, and is provided with an input channel for ensuring withstand voltage against a large potential difference.

However, the following problems may occur with the first device alone. That is, there is a problem that a uniform potential difference does not always occur in each input channel CH4 and CH5 due to a difference (bias) in the characteristics of circuit elements such as impedance and resistance in each input channel CH4 and CH5. That is, even if the potential difference between the input terminal V3 and the input terminal S6 is within the range of the total withstand voltage between the input channels CH4 and CH5, the potential difference is within the range of the withstand voltage of each of the input channels CH4 and CH5. It did not always occur evenly. That is, the potential difference applied to the input channel CH4 and the potential difference applied to the input channel CH5 are significantly different, and may exceed the withstand voltage of one of the input channels.

Therefore, in the present embodiment, as shown in FIG. 1, a potential stabilization circuit 80 is provided as a second device. The potential stabilization circuit 80 is between the potential of the input signal input to the input terminal V3 and the potential of the input signal input to the input terminal S6 with respect to the input terminal S5 of the input channel CH5 which is the read-off channel. The signal that becomes the potential of is output as an input signal. At that time, in the potential stabilization circuit 80, the potential difference between the input terminal S5 and the input terminal S6 and the potential difference between the input terminal S5 and the input terminal V3 are within the withstand voltage range of the monitoring IC 50, respectively. , Outputs a predetermined input signal to the input terminal S5.

More specifically, the second voltage divider circuit 60 divides the voltage between terminals by the resistors R41, R55, and R51, and generates a voltage divider voltage DS6_2 between the resistors R41 and R55. The voltage divider ratio of the second voltage divider circuit 60 is set so that the voltage divider voltage DS6_2 has a voltage similar to that of the voltage divider voltage DS6 input to the input terminal S6. That is, the voltage between the terminals is divided at the same voltage dividing ratio as the fifth voltage dividing ratio in the first voltage dividing circuit 40 to generate the divided voltage DS6_2.

And, as described above, the potential stabilization circuit 80 is a series connection body of the resistances R53 and R54, and one end thereof is connected to the connection point between the resistances R41 and R55. The voltage divider voltage DS6_2 is applied (input) to the potential stabilization circuit 80 from one end thereof.

On the other hand, the other end of the potential stabilization circuit 80 is connected to the connection point P14 between the resistance R11 and the resistance R21 of the first voltage dividing circuit 40. That is, the other end of the potential stabilization circuit 80 is equivalent to being connected to the input terminal V3. Therefore, when the system 21 is energized, the voltage dividing voltage DV3 is applied to the other end of the potential stabilization circuit 80. Therefore, when the system 21 is energized, the potential stabilizing circuit 80 applies a voltage between the voltage dividing voltage DS6_2 and the voltage dividing voltage DV3 to the input terminal S5. At this time, the potential of the input signal input to the input terminal S5 is set by the voltage dividing voltage DS6_2, the voltage dividing voltage DV3, and the resistors R53 and R54.

Further, when the energization to the system 21 is cut off, the voltage dividing voltage DS3min is input to the other end of the potential stabilization circuit 80 via the resistor R21. Therefore, the potential stabilization circuit 80 applies a voltage between the voltage dividing voltage DS6_2 and the voltage dividing voltage DS3min to the input terminal S5 when the energization to the system 21 is cut off. When the energization to the system 21 is cut off, the voltage dividing voltage DS3min is also an input signal input to the input terminal V3. At this time, the potential of the input signal input to the input terminal S5 is set by the voltage dividing voltage DS6_2, the voltage dividing voltage DS3min, and the resistors R21, R53, and R54.

In the resistors R53 and R54 of the potential stabilization circuit 80, the potential difference between the input terminal S5 and the input terminal S6 is within the withstand voltage range between the input terminal S5 and the input terminal S6, and the input terminal S5 The potential difference between the input terminal V3 and the input terminal V3 is set to be within the range of the withstand voltage between the input terminal S5 and the input terminal V3. That is, the resistances R53 and R54 of the potential stabilization circuit 80 are set so that each potential difference is within the range of the withstand voltage of the input channel CH5 and within the range of the withstand voltage of the input channel CH4.

As a result, in the potential stabilization circuit 80, the potential difference between the input terminal S5 and the input terminal S6 and the potential difference between the input terminal S5 and the input terminal V3 are within the withstand voltage range of the monitoring IC 50, respectively. A voltage is generated and output to the input terminal S5 as an input signal. Hereinafter, the voltage input from the potential stabilizing circuit 80 to the input terminal S5 when the power to the system 21 is energized is referred to as a voltage DS5_1, and is input to the input terminal S5 from the potential stabilizing circuit 80 when the energization to the system 21 is cut off. The voltage is referred to as voltage DS5_2.

Next, the operation of providing the potential stabilization circuit 80 in this way will be described. FIG. 14A shows the potential (monitoring IC input voltage) of each input signal when the relay switches SN1 and SP1 are turned off at the time point T1 from the state where the relay switches SN1, SP1, SN2 and SP2 are all turned on. It is a figure which shows the time transition. FIG. 14 (b) is a diagram showing the time transition of the potential difference in FIG. 14 (a).

As shown in FIG. 14A, when all the relay switches SN1, SP1, SN2 and SP2 are turned on, the voltage dividing voltage DS1 is input to the input terminal S1 and the voltage dividing voltage DS1 is input to the input terminals V1, S2 and V2. , The voltage divider voltage DV1 is input. The voltage dividing voltage DS3 is input to the input terminal S3, and the voltage dividing voltage DV3 is input to the input terminals V3, S4, and V4. Further, the voltage DS5_1 is input to the input terminals S5 and V5. The voltage dividing voltage DS6 is input to the input terminal S6, and the voltage dividing voltage DV6 is input to the input terminal V6.

The magnitude relationship of each input signal is DS1 <DV1 <DS3 <DV3 <DS5_1 <DS6 <DV6. As a result, the input signals are input to the input terminals in the order corresponding to the potential order. Further, as shown in FIG. 14B, the potential difference DV6-DS6, the potential difference DS6-DS5_1, the potential difference DS5_1-DV3, the potential difference DV3-DS3, the potential difference DS3-DV1, and the potential difference DV1-DS1 are also within the withstand voltage range. There is.

In FIG. 14A, when the time point T1 has passed and the relay switches SN1 and SP1 are turned off, the input signals of the input terminals S3, V3, S4 and V4 become the voltage dividing voltage DS3min. Further, the input signals of the input terminals S5 and V5 have a voltage DS5_2.

In this case, the magnitude relationship of each input signal is DS1 <DV1 <DS3min <DS5_1 <DS6 <DV6. As a result, the input signals are input to the input terminals in the order corresponding to the potential order. Further, as shown in FIG. 14B, the potential difference DV6-DS6, the potential difference DS6-DS5_2, the potential difference DS5_2-DS3min, the potential difference DS3min-DV1, and the potential difference DV1-DS1 are also within the withstand voltage range.

In particular, the input signal input to the input terminal V3 drops from the voltage dividing voltage DV3 to the voltage dividing voltage DS3min, and in accordance with this, the input signal input from the potential stabilizing circuit 80 to the input terminal S5 The potential also drops from the voltage DS5_1 to the voltage DS5_1. Therefore, it is possible to suppress the expansion of the potential difference.

Next, a description will be given based on FIG. FIG. 15A shows the potential (monitoring IC input voltage) of each input signal when the relay switches SN2 and SP2 are turned off at the time point T2 from the state where the relay switches SN1, SP1, SN2 and SP2 are all turned on. It is a figure which shows the time transition. FIG. 15B is a diagram showing the time transition of the potential difference in FIG. 15A. As shown in FIG. 15A, it is the same as in FIG. 14 up to the time point T2, so the description thereof will be omitted.

In FIG. 15A, when the time point T2 has passed and the relay switches SN2 and SP2 are turned off, the input signal of the input terminals S6 and V6 becomes the voltage dividing voltage DS6min. In this case, the magnitude relationship of each input signal is DS1 <DV1 <DS3 <DV3 <DS5-1 <DS6min. As a result, the input signals are input to the input terminals in the order corresponding to the potential order. Further, as shown in FIG. 15B, the potential difference DV6-DS6, the potential difference DS6min-DS5_1, the potential difference DS5_1-DV3, the potential difference DV3-DS3, the potential difference DS3-DV1, and the potential difference DV1-DS1 are also within the withstand voltage range.

Next, a description will be given based on FIG. FIG. 16A shows the potential (monitoring) of each input signal when the relay switches SN1, SP1, SN2, and SP2 are all turned off at the time point T3 from the state where the relay switches SN1, SP1, SN2, and SP2 are all turned on. It is a figure which shows the time transition of (IC input voltage). 16 (b) is a diagram showing the time transition of the potential difference in FIG. 16 (a). As shown in FIG. 16A, up to the time point T3 is the same as in FIG. 14, so the description thereof will be omitted.

In FIG. 16A, when the time point T3 has passed and all the relay switches SN1, SP1, SN2, and SP2 are turned off, the input signal of the input terminals S3, V3, S4, and V4 becomes the voltage dividing voltage DS3min. Further, the input signals of the input terminals S5 and V5 have a voltage DS5_2. Further, the input signals of the input terminals S6 and V6 have a voltage dividing voltage of DS6min.

In this case, the magnitude relationship of each input signal is DS1 <DV1 <DS3min <DS5_2 <DS6min. As a result, the input signals are input to the input terminals in the order corresponding to the potential order. Further, as shown in FIG. 16B, the potential difference DS6min-DS5_2, the potential difference DS5_2-DS3min, the potential difference DS3min-DV1, and the potential difference DV1-DS1 are also within the withstand voltage range.

In particular, the input signal input to the input terminal V3 drops from the voltage dividing voltage DV3 to the voltage dividing voltage DS3min, and in accordance with this, the input signal input from the potential stabilizing circuit 80 to the input terminal S5 The potential also drops from the voltage DS5_1 to the voltage DS5_1. Therefore, it is possible to suppress the expansion of the potential difference.

According to the configuration of the first embodiment, the following effects can be obtained.

In the first voltage dividing circuit 40, the input terminals S1, V1, S3, V3, S6, and V6 have different voltage dividing ratios (first voltage dividing ratio to sixth voltage dividing ratio) stepwise according to the potential order. The voltage or the applied voltage of the systems 21 and 22 is divided and output. That is, each voltage dividing ratio in the first voltage dividing circuit 40 is the input terminals S1 and V1 that are output destinations so that the input signals input to the input terminals S1 to S6 and V1 to V6 are in the order corresponding to the potential order. , S3, V3, S6, V6 are set to different values in stages. As a result, even if the voltage between the terminals and the applied voltage of each system 21 and 22 are almost the same, the voltage dividing voltage input to each input terminal S1 to S6 and V1 to V6 by the first voltage dividing circuit 40 is stepped. It is possible to increase the voltage. Therefore, it is possible to prevent the generation of wraparound current and detect the voltage with high accuracy.

Further, between the input terminal V3 of the input channel CH3 and the input terminal S6 of the input channel CH6, a read-off channel (withstand voltage) which is a plurality of input channels CH4 and CH5 in which the input signal from the first voltage dividing circuit 40 is not input. (Securing channel) is provided. As a result, the range of withstand voltage can be increased as compared with the case where the read / discard channel is not provided between the input terminal V3 and the input terminal S6, or when there is only one read / discard channel.

The input terminal V3 is a high potential side input terminal of the input channel CH3 associated with the system 21. Further, the input terminal S6 is an input terminal to which an input signal having a higher potential than the input terminal V3 is input in the order of potential, and is a low potential side input terminal of the input channel associated with the system 22.

Further, the potential stabilization circuit 80 outputs a signal that is a potential between the potential of the input signal input to the input terminal V3 and the potential of the input signal input to the input terminal S6 to the input terminal S5 as an input signal. do. The input terminal S5 is one of the input terminals belonging to the read-through channel.

By inputting a signal that is a potential between the potential of the input signal of the input terminal V3 and the potential of the input signal of the input terminal S6 to the input terminal S5, the input channels CH4 and CH5, which are the read-off channels, are used for impedance and the like. Even if there is a bias, it is possible to control the potential difference in each of the input channels CH4 and CH5 so as to be within the range of withstand voltage.

When the energization of the systems 21 and 22 is cut off, the second voltage divider circuit 60 outputs the divided voltage DS3min and DS6min to the input channels CH3 and CH6 associated with the systems 21 and 22 whose energization is cut off. do. More specifically, in the second voltage dividing circuit 60, when the energization to the systems 21 and 22 is cut off, the input terminals S3 and CH6 of the input channels CH3 and CH6 associated with the systems 21 and 22 whose energization is cut off Input the voltage dividing voltages DS3min and DS6min to S6. Along with this, the voltage dividing voltages DS3min and DS6min are input from the input terminals S3 and S6 to the input terminals V3, S4, V4 and V6 via the diodes D53 and D56, respectively.

Then, the second voltage divider circuit 60 divides the voltage between the terminals at stepwise different voltage divider ratios (seventh voltage divider ratio and eighth voltage divider ratio) for each of the systems 21 and 22. More specifically, the voltage dividing ratio (seventh voltage dividing ratio and the eighth voltage dividing ratio) in the second voltage dividing circuit 60 is an input signal input to the input terminals S3 and S6 of the input channels CH3 and CH6 to be output destinations (7th voltage dividing ratio and the eighth voltage dividing ratio). The voltage dividing ratio is such that DS3min, DS6min) are in the order corresponding to the order of potential, and is set by the first voltage dividing circuit 40 in order to generate an input signal (DS3, DS6) to the input terminals S3 and S6. It is a voltage dividing ratio equal to or less than the voltage dividing ratio (third voltage dividing ratio, fifth voltage dividing ratio).

Specifically, the seventh voltage dividing ratio by the second voltage dividing circuit 60 is smaller than the third voltage dividing ratio by the first voltage dividing circuit 40, and is one step smaller than the third voltage dividing ratio. It is set larger than the voltage dividing ratio of 2. As a result, the magnitude relationship of the voltage dividing voltage becomes DV1 <DS3min <DS3. Therefore, as shown in FIG. 6, the voltage dividing voltage DS3min is input to the input terminals S3 and V3 only when the relay switches SN1 and SP1 are turned off. Further, in this case, since the voltage dividing voltage DS3min input to the input terminal S3 is larger than the voltage dividing voltage DV1 input to the input terminal V1, a wraparound current from the input terminal V1 to the input terminal S3 is generated. Can be prevented from doing so. Further, since DS3min <DS6 and the voltage dividing voltage DS6 input to the input terminal S6 is larger than the voltage dividing voltage DS3min input to the input terminals S3 and V3, the voltage divided voltage DS6 input from the input terminals S3 and V3 to the input terminal S6. It is possible to prevent the generation of wraparound current. That is, it is possible to prevent the wraparound current from the input channel CH3 to the input channel CH6 from being generated.

Similarly, as shown in FIG. 7, the wraparound current can be prevented even when the relay switches SN2 and SP2 are turned off. Further, since DS3min <DS6min, as shown in FIG. 9, even when all the relay switches SN1, SP1, SN2, and SP2 are off, the current wraps around from the input channel CH1 to the input channels CH3 and CH6. Can be prevented.

Then, the potential stabilization circuit 80 lowers the potential of the input signal to the monitoring IC 50 when the energization to the system 21 is cut off. That is, the potential stabilization circuit 80 lowers the voltage DS5_1 from the voltage DS5_1. As a result, even if the input signal input to the input terminal V3 is reduced from the voltage dividing voltage DV3 to the voltage dividing voltage DS3min by the second voltage dividing circuit 60, it is possible to suppress the expansion of the potential difference by following the voltage dividing circuit 60.

By the way, like the resistance element shown by the broken line in FIG. 17, when one end of the potential stabilization circuit 80 is connected to the input terminal S6 of the input channel CH6 and the other end is connected to the input terminal V3, it becomes a two-dot chain wire. As shown, a wraparound current is generated from the input channel CH6 via the potential stabilization circuit 80, and the detection accuracy of the applied voltage is lowered.

Therefore, one end of the potential stabilization circuit 80 was connected to the second voltage dividing circuit 60, and the other end was connected to the input terminal V3. Further, the connection point P17 of the resistors R53 and R54 was connected to the input terminal S5 of the monitoring IC50. That is, the current path is independent between the potential stabilization circuit 80 and the input channel CH6. Therefore, it is possible to prevent a wraparound current from being generated from the input channel CH6 via the potential stabilization circuit 80. Therefore, the detection accuracy of the applied voltage can be improved.

The second voltage divider circuit 60 divides the voltage between the terminals of the assembled battery 10 by the voltage divider ratio for generating the input signal having the input channel CH6 associated with the system 22 as the output destination, that is, the voltage divider voltage DS6. The voltage dividing voltage DS6_2 generated by pressure is output to one end of the potential stabilizing circuit 80. Then, the potential stabilization circuit 80 generates the voltage DS5_1 and the voltage DS5_2 based on the voltage divider DS6_2 and the voltage divider DV3 (or the voltage divider DS3min). Therefore, it is not necessary to input the voltage dividing voltage DS6 from the first voltage dividing circuit 40, and it is possible to prevent the wraparound current from the input channel CH6 from being generated.

The input terminal S5 to which the input signal from the potential stabilization circuit 80 is input is a system rather than the side of the input channel CH3 associated with the system 21 in the order of potential among the input channels CH4 and CH5 which are read-down channels. It is an input terminal of the input channel CH5 set on the side of the input channel CH6 associated with 22. That is, the input terminal S5 is set closer to the input terminal S6 than the input terminal V3.

As a result, the withstand voltage range can be increased by one input channel as compared with the case where the input signal from the potential stabilization circuit 80 is input to the input terminals S4 and V4 near the input terminal V3. .. In particular, since the input signal input to the input terminal V3 may drop from the voltage dividing voltage DV3 to the voltage dividing voltage DS3min and the potential difference may increase, it can be an effective measure for ensuring the withstand voltage.

The third voltage dividing ratio and the fifth voltage dividing ratio in the first voltage dividing circuit 40 are set in consideration of the amount of voltage drop. Specifically, the third voltage dividing ratio is set so that the maximum drop amount N1max <voltage dividing voltage DS3, and the fifth voltage dividing ratio is set so that the maximum drop amount N2max <voltage dividing voltage DS6. ing. As a result, even if a voltage drop occurs, no negative voltage is generated, and the voltage dividing voltage input to each input terminal S1, V1, S3, V3, S6, V6 can be gradually increased, resulting in wraparound. The current can be prevented.

Further, the first voltage divider circuit 40 divides the voltage between terminals by two different voltage divider ratios, and the monitoring IC 50 has two voltage dividers DS1 via the input channel CH1 set for the assembled battery 10. DV1 is input, and the voltage between terminals is detected based on the difference between the divided voltages DS1 and DV1. Therefore, the applied voltage and the circuit for detecting the voltage between terminals can be shared. Further, as shown in FIG. 8, it is possible to detect the off sticking of the switch SW0.

Since the voltage dividing voltage is input to the monitoring IC 50, the withstand voltage can be reduced and the size can be reduced. Further, since the differential amplifier circuit 52 and the AD converter 53 are integrated inside the monitoring IC 50 and the arithmetic unit 54 corrects the error, the detection accuracy can be improved. Further, since the monitoring IC50 used for voltage detection of the battery cell of the assembled battery can be adopted as it is, the development cost can be suppressed.

The first division pressure ratio to the sixth division pressure ratio are set in stages. Further, the seventh pressure division ratio is set between the second pressure division ratio and the third pressure division ratio, and the eighth pressure division ratio is between the fourth pressure division ratio and the fifth pressure division ratio. Is set to. Further, the voltage DS5_1 output from the potential stabilization circuit 80 is a potential (voltage) between the voltage divider voltage DV3 and the voltage divider voltage DS6_1. Further, the voltage DS5_2 output from the potential stabilizing circuit 80 is a potential (voltage) between the voltage dividing voltage DS3min and the voltage dividing voltage DS6_2. Further, the voltage dividing voltage DS6_2 has substantially the same potential as the voltage dividing voltage DS6.

As a result, as shown in FIGS. 14 to 16, the potential of the input signal input to each input terminal gradually increases regardless of how the relay switches SN1, SP1, SN2, and SP2 are turned on and off. Therefore, it is possible to surely prevent the generation of wraparound current and suppress the deterioration of the detection accuracy.

(Modified example of the embodiment)
The configuration of the above embodiment may be changed as follows. Hereinafter, the differences from the configurations described in the above embodiment will be described.

-In the above embodiment, the monitoring IC 50 does not have to detect the voltage between the terminals of the assembled battery 10.

-In the above embodiment, the number of discarded channels is two, but it may be three or more.

-In the above embodiment, the number of systems that detect the applied voltage may be arbitrarily changed. In this case, similarly to the systems 21 and 22, the high potential side input terminal of the input channel associated with the first system and the input signal having a higher potential than the high potential side input terminal in the potential order are input. It is desirable that a plurality of read-through channels are set between the input terminal and the low potential side input terminal of the input channel associated with the second system.

Then, the potential stabilization circuit 80 receives the potential of the input signal input to the high potential side input terminal and the input signal input to the low potential side input terminal to any of the input terminals belonging to the read-off channel. It is desirable to output an input signal that becomes a potential between the potential.

-In the above embodiment, the voltage between the terminals of the assembled battery 10 is detected in the input channel CH1, but the input channel for detecting the voltage between the terminals may be changed.

The second voltage divider circuit 60 generated the voltage divider voltage DS6_2 using the resistors R41, R55, and R51, but a voltage divider circuit (series connection of resistors) was provided in parallel with the resistors R42 and R52. Thereby, the voltage dividing voltage DS6_2 may be generated.

Although the present disclosure has been described in accordance with the examples, it is understood that the present disclosure is not limited to the examples and structures. The present disclosure also includes various variations and variations within a uniform range. In addition, various combinations and forms, as well as other combinations and forms that include only one element, more, or less, are within the scope and scope of the present disclosure.

Claims (6)

1. Voltage detection applied to a power supply system comprising a storage battery (10) and a plurality of systems (21, 22) connected in parallel to the storage battery and to which a voltage between the terminals of the storage battery is applied, respectively. In the device (30)
   The first voltage divider circuit (40) that divides the applied voltage of each system and
   A plurality of input channels (CH1 to CH6) are provided, and the applied voltage applied to each of the systems is based on the potential difference between the two input signals input from the first voltage divider circuit via the input channels. The detection circuit (50) that detects each of
   A potential stabilizing circuit (80) that outputs a signal to the detection circuit is provided.
   Each of the input channels has a pair of input terminals (S1 to S6, V1 to V6), and the potential order of the input signals is preset in each of the input terminals.
   The first voltage divider circuit divides the applied voltage of the system by two different voltage dividing ratios, and outputs the voltage divided voltage as the input signal to the input terminal of the input channel associated with the system. It is composed and
   Each voltage dividing ratio in the first voltage dividing circuit is a value that is stepwise different for each of the input terminals to be output destinations so that the input signals input to the input terminals are in the order corresponding to the potential order. Is set,
   Among the plurality of systems, the high potential side input terminal (V3) of the input channel associated with the first system (21) and the input signal having a higher potential than the high potential side input terminal in the potential order are input. From the first voltage dividing circuit, the input terminal is connected to the low potential side input terminal (S6) of the input channel associated with the second system (22) among the plurality of systems. A withstand voltage securing channel, which is a plurality of input channels (CH4, CH5) in which the input signal of the above is not input, is provided.
   The potential stabilization circuit has the potential of an input signal input to the high potential side input terminal associated with the first system with respect to any input terminal of the withstand voltage securing channel, and the potential of the input signal. A voltage detection device that outputs a signal having a potential between the potential of the input signal input to the low potential side input terminal associated with the second system as the input signal.
2. A second voltage divider circuit that outputs a voltage divider obtained by dividing the voltage between the terminals of the storage battery as an input signal to the input channel associated with the system in which the energization with the storage battery is cut off. With (60)
   The voltage division ratio in the second voltage division circuit is a voltage division ratio such that the input signals input to the low potential side input terminal of the input channel to be output are in the order corresponding to the potential order, and the low voltage ratio. The voltage detection device according to claim 1, wherein the voltage division ratio is equal to or less than the voltage division ratio set in the first voltage division circuit for generating an input signal to the potential side input terminal.
3. The voltage detection device according to claim 2, wherein the potential stabilizing circuit reduces the potential of an input signal to the detection circuit when the energization of the first system is cut off.
4. The potential stabilization circuit is configured by connecting a plurality of resistance elements in series.
   One end thereof is connected to the second voltage divider circuit.
   The connection point between the plurality of resistance elements is connected to the input terminal of the detection circuit.
   The voltage detection device according to claim 3, wherein the other end is connected to the high potential side input terminal of the first system.
5. The second voltage divider circuit is a voltage divider ratio for generating an input signal whose output destination is the low potential side input terminal of the input channel associated with the second system, and is a voltage between terminals of the storage battery. The voltage detection device according to claim 4, wherein the voltage is divided and output to one end of the potential stabilization circuit.
6. The input terminal to which the input signal from the potential stabilization circuit is input is the side of the input terminal of the input channel associated with the first system in the potential order among the input terminals belonging to the withstand voltage securing channel. The voltage detection device according to any one of claims 2 to 5, which is set on the side of the input terminal of the input channel associated with the second system.

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