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WO2022002106A1 - 中断处理方法、中断管理器、电子设备、计算机可读存储介质 - Google Patents

中断处理方法、中断管理器、电子设备、计算机可读存储介质 Download PDF

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Publication number
WO2022002106A1
WO2022002106A1 PCT/CN2021/103404 CN2021103404W WO2022002106A1 WO 2022002106 A1 WO2022002106 A1 WO 2022002106A1 CN 2021103404 W CN2021103404 W CN 2021103404W WO 2022002106 A1 WO2022002106 A1 WO 2022002106A1
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Prior art keywords
ipi
interrupt
vcpu
request
request information
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PCT/CN2021/103404
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English (en)
French (fr)
Inventor
李翌
刘熠
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中兴通讯股份有限公司
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Publication of WO2022002106A1 publication Critical patent/WO2022002106A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G06F2009/45575—Starting, stopping, suspending or resuming virtual machine instances

Definitions

  • the present disclosure relates to the field of communication technologies, and in particular, to an interrupt processing method, an interrupt manager, an electronic device, and a computer-readable storage medium.
  • Virtualization enables one physical host to run multiple logical hosts (virtual machines), thereby obtaining features such as secure isolation and high utilization.
  • a virtual machine can have multiple virtual central processing units (vCPUs) to provide better performance.
  • vCPUs virtual central processing units
  • the operating system needs to provide an Inter-Processor Interrupts (IPI, Inter-Processor Interrupts) mechanism for virtualization.
  • IPI Inter-Processor Interrupts
  • the IPI mechanism allows one vCPU to send interrupts to multiple vCPUs. It can generally perform operations such as address translation buffer (TLB, Translation Lookaside Buffer) refresh and cross-CPU function calls. It is an important operating mechanism for the operating system.
  • an embodiment of the present disclosure provides an interrupt processing method, including:
  • the storage space of the manager includes at least one of the IPI request information areas, the IPI request information areas correspond to virtual machines, and the IPI request information areas are mapped to the corresponding virtual machines through memory mapping input and output MMIO; and
  • the predetermined interrupt request is sent to an interrupt controller, so that the interrupt controller sends the predetermined interrupt request to each of the target vCPUs.
  • an interrupt processing method including:
  • the IPI request information is written into the IPI request information area in the storage space of the interrupt manager corresponding to the virtual machine to which the vCPU that initiates the IPI request belongs, and the IPI request information carries the identifier of at least one target vCPU, wherein , the storage space of the interrupt manager includes at least one of the IPI request information area, and the physical address of the IPI request information area is mapped to the corresponding virtual machine through MMIO; And
  • the IPI processing operation is invoked to process the predetermined interrupt request.
  • an interrupt manager including:
  • processors one or more processors
  • a storage device on which one or more computer programs are stored, and when the one or more computer programs are executed by the one or more processors, causes the one or more processors to implement the first embodiment of the present disclosure
  • the interrupt handling method provided on the one hand.
  • an electronic device including:
  • processors one or more processors
  • a storage device on which one or more computer programs are stored, and when the one or more computer programs are executed by the one or more processors, causes the one or more processors to implement the first embodiment of the present disclosure
  • One or more I/O interfaces are connected between the processor and the storage device, and are configured to realize information interaction between the processor and the storage device.
  • an embodiment of the present disclosure provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, implements the interrupt processing method provided in the first aspect of the embodiment of the present disclosure, and/or The interrupt processing method provided by the second aspect.
  • FIG. 1 is a schematic diagram of IPI virtualization in the related art
  • FIG. 2 is a flowchart of an interrupt processing method in an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of IPI virtualization in an embodiment of the present disclosure.
  • FIG. 6 is a flowchart of some steps in an interrupt processing method in an embodiment of the present disclosure.
  • FIG. 7 is a flowchart of some steps in an interrupt processing method in an embodiment of the present disclosure.
  • FIG. 8 is a flowchart of some steps in an interrupt processing method in an embodiment of the present disclosure.
  • FIG. 9 is a flowchart of an interrupt processing method in an embodiment of the present disclosure.
  • FIG. 11 is a flowchart of some steps in the interrupt processing method in the embodiment of the present disclosure.
  • FIG. 13 is a flowchart of some steps in an interrupt processing method in an embodiment of the present disclosure.
  • FIG. 15 is a flowchart of some steps in an interrupt processing method in an embodiment of the present disclosure
  • 16 is a schematic diagram of a storage space of an IPI interrupt manager in an embodiment of the present disclosure.
  • FIG. 17 is a schematic diagram of IPI virtualization in an embodiment of the present disclosure.
  • FIG. 19 is a block diagram of an electronic device in an embodiment of the disclosure.
  • FIG. 20 is a block diagram of the composition of a computer-readable storage medium in an embodiment of the disclosure.
  • FIG. 1 is a schematic diagram of IPI virtualization in the related art.
  • the vCPU when the vCPU sends an IPI interrupt, it can directly operate the interrupt controller; it can also notify the virtual machine manager (VMM, Virtual Machine Manager) through the VP method, and then the VMM checks the target vCPU of the IPI interrupt, and Send IPI interrupts one by one. After research, it is found that the above methods of sending IPI interrupts will cause the virtual machine (VM, Virtual Machine) to exit the Guest mode and switch to the host mode.
  • VMM virtual machine manager
  • IPI virtualization technology when the vCPU sends an IPI interrupt, it notifies the host of multiple IPI interrupt information of the virtual machine at one time.
  • an embodiment of the present disclosure provides an interrupt processing method, including the following steps S110 and S120.
  • step S110 when the inter-processor interrupt (IPI) request information is written in the IPI request information area, a predetermined interrupt request is generated according to the IPI request information, and the IPI request information carries at least one target virtual central processing unit (vCPU) , the storage space of the current IPI interrupt manager includes at least one of the IPI request information area, the IPI request information area corresponds to a virtual machine, and the IPI request information area is mapped to the corresponding through memory mapping input output (MMIO). virtual machine.
  • IPI inter-processor interrupt
  • step S120 the predetermined interrupt request is sent to an interrupt controller, so that the interrupt controller sends the predetermined interrupt request to each of the target vCPUs.
  • an embodiment of the present disclosure provides an IPI interrupt manager.
  • the storage space of the IPI interrupt manager is divided into multiple IPI request information areas, and each IPI request information area corresponds to a virtual machine for storing IPI interrupt request information sent by the vCPU of the virtual machine.
  • the IPI interrupt manager triggers the IPI processing action by monitoring the write operation of the virtual machine to the corresponding IPI request information area.
  • the IPI request information area is mapped to the corresponding virtual machine through memory-mapped IO (MMIO, Memory-mapped I/O).
  • MMIO is part of the Peripheral Component Interconnect (PCI, Peripheral Component Interconnect) specification. I/O devices are placed in the memory space instead of the I/O space. After the MMIO mapping is completed, the CPU can use the access memory instructions to access I/O devices.
  • PCI Peripheral Component Interconnect
  • the physical address of the IPI request information area is mapped to the corresponding virtual machine through MMIO, and the MMIO mapping between the IPI request information area and the corresponding virtual machine is completed, and the vCPU of the virtual machine can use the instruction of the CPU to access the memory to
  • the IPI interrupt request information is written into the corresponding IPI request information area. Therefore, during the notification process of the IPI interruption, the virtual machine does not need to exit the Guest state.
  • the IPI interrupt manager may be implemented based on hardware or based on software.
  • the embodiments of the present disclosure do not make special limitations.
  • the predetermined interrupt request generated according to the IPI request information written in the IPI request information area can be directly injected into the target vCPU without causing the target vCPU to exit the Guest state.
  • the predetermined interrupt is an external interrupt, for example, Message Signaled Interrupts (MSI, Message Signaled Interrupts).
  • the IPI interrupt can be directly injected into the target vCPU, and the target vCPU does not need to exit the Guest state.
  • the IPI interrupt can be directly processed by the virtual machine based on the VT-D (Virtualization Technology for Direct I/O) mechanism; on the ARM architecture, the external interrupts are directly processed by the virtual machine based on the vGSI mechanism.
  • the virtual machine by converting the IPI interrupt request into a predetermined interrupt request that can be directly injected into the target vCPU without causing the target vCPU to exit the Guest state, the virtual machine does not need to exit the Guest state when injecting the IPI interrupt into the target vCPU.
  • an IPI interrupt manager is provided.
  • the IPI request information area in the storage space of the IPI interrupt manager is mapped to the corresponding virtual machine through memory mapping input and output (MMIO).
  • MMIO memory mapping input and output
  • the IPI interrupt manager converts the IPI interrupt to be able to be directly injected into the target vCPU without causing the target vCPU
  • the scheduled interrupt for exiting the Guest state based on the hardware interrupt virtualization function provided by the CPU, can realize the direct injection of IPI interrupts into the target vCPU, and the target vCPU does not need to exit the Guest state.
  • the virtual machine in the process of sending the IPI interrupt request information by the vCPU and injecting the IPI interrupt into the target vCPU, the virtual machine does not need to exit the Guest state, which reduces the performance loss caused by the virtualization exit and improves the virtualization operation efficiency.
  • the MSI interrupt is injected into the target vCPU based on the VT-D mechanism, so that the virtual machine can respond to the interrupt without exiting the guest state.
  • the interrupt controller is an Advanced Programmable Interrupt Controller (APIC, Advanced Programmable Interrupt Controller), including IO-APIC and Local-APIC.
  • IO-APIC is unique in the system and is used to manage the forwarding of external MSI interrupts to Local-APIC; each CPU has a Local-APIC, which is used to manage the sending of MSI interrupts routed from IO-APIC to the corresponding CPU, and also manages IPI interrupted transmission.
  • the IO-APIC supports a remapping method (reMapping), and the IO-APIC manages the interrupt remapping table, which includes the interrupt remapping of multiple physical central processing units (pCPUs). table entry.
  • reMapping remapping method
  • pCPUs physical central processing units
  • the corresponding interrupt remapping table entry in the interrupt remapping table is searched according to the information carried in the MSI interrupt, and the MSI is determined. Interrupt the corresponding notification vector (Notify Vector), and then send the interrupt to the Local-APIC. If the corresponding target vCPU has been scheduled, the Local-APIC will directly send an interrupt to the target vCPU, and if the corresponding target vCPU is not scheduled, it will notify the VMM for processing.
  • the IPI interrupt is converted into an MSI interrupt, and the type of the MSI interrupt is a Posted Interrupt (Posted Interrupt) in a remapping (Remapping) manner, so as to realize the virtual reality when the IPI interrupt is injected into the target vCPU The machine does not need to exit the Guest state.
  • the type of the MSI interrupt is a Posted Interrupt (Posted Interrupt) in a remapping (Remapping) manner, so as to realize the virtual reality when the IPI interrupt is injected into the target vCPU The machine does not need to exit the Guest state.
  • step S110 includes:
  • Step S111 Generate a message signal interrupt (MSI) request as the predetermined interrupt request according to the IPI request information, where the type of the MSI request is Posted-Interrupt in a remapping manner.
  • MSI message signal interrupt
  • an MSI configuration register in the configuration space of the IPI interrupt manager. By setting the content of the MSI configuration register, the type of the MSI generated in the IPI interrupt manager can be configured to The release type of the mapping method is broken.
  • the Posted-Interrupt attribute is configured by the VMM for the IPI Interrupt Manager. That is, by writing configuration content into the MSI configuration register of the IPI interrupt manager, the Posted-Interrupt attribute is configured for the IPI interrupt manager, so that the type of the MSI generated in the IPI interrupt manager is a post-type interrupt in the remapping mode.
  • an interrupt remapping table entry (IRTE, Interrupt Remap Table Entry) is allocated to each pCPU by the VMM, that is, the interrupt remapping table entry of the pCPU in the interrupt remapping table managed by the IO-APIC.
  • the storage space of the IPI interrupt manager further includes a pCPU information area, where the pCPU ID and the IRTE index corresponding to the pCPU are stored in the pCPU information area.
  • the MSI request is generated according to the IRTE index corresponding to the target vCPU and the IPI vector to be sent, and the MSI request is sent to the IO-APIC, so that the IO-APIC searches the interrupt remapping table by searching , the interrupt is sent to the corresponding Local-APIC, and further injected into the target vCPU that has been scheduled.
  • the storage space of the IPI interrupt manager includes multiple vCPU scheduling information areas, the multiple vCPU scheduling information areas are in one-to-one correspondence with the multiple vCPUs, and the vCPU scheduling information area stores pCPUs that schedule the corresponding vCPUs 's identification.
  • the IPI interrupt request information is written in the IPI interrupt request information area, according to the identifier of the target vCPU, the identifier of the pCPU that schedules the target vCPU is read from the vCPU scheduling information area corresponding to the target vCPU.
  • the IPI request information carries the interrupt number vector
  • step S111 includes:
  • Step S111a read the identifier of the target pCPU stored in the vCPU scheduling information area corresponding to the target vCPU, the target pCPU is the pCPU that schedules the target vCPU, and the storage space of the current IPI interrupt manager includes multiple vCPU scheduling information area, the multiple vCPU scheduling information areas are in one-to-one correspondence with multiple vCPUs, and the vCPU scheduling information area stores the identifier of the pCPU that schedules the corresponding vCPU;
  • Step S111b read the interrupt remapping table entry index corresponding to the target pCPU from the pCPU information area according to the identifier of the target pCPU, and the pCPU information area in the storage space of the current IPI interrupt manager stores multiple pCPU identifiers and interrupt remaps. mapping table entry index correspondence;
  • Step S111c the MSI request is generated according to the interrupt remapping table entry index corresponding to each target pCPU and the vector carried by the IPI request information.
  • the IPI interrupt manager when the target vCPU is scheduled, the IPI interrupt manager generates a predetermined interrupt request, and directly sends the predetermined interrupt to the target vCPU through the interrupt controller; when the target vCPU is not scheduled, the IPI interrupt manager then Notifies the VMM to handle the IPI request.
  • the interrupt processing method when the inter-processor interrupt (IPI) request information is written in the IPI request information area, before step S110, the interrupt processing method further includes:
  • Step S130 determining the scheduling state of the target vCPU according to the identifier of the target vCPU;
  • step S110 is executed.
  • the IPI interrupt manager of the embodiment of the present disclosure further includes a data area of the to-be-sent IPI request vCPU set for storing the to-be-sent IPI request vCPU set, and a to-be-sent IPI request vCPU set data area for storing the VM set to which the to-be-sent IPI request vCPU belongs.
  • the vCPU set to send the IPI request refers to the set of vCPUs that initiate the IPI request
  • the VM set to which the vCPU to send the IPI request belongs refers to the set of VMs to which the vCPU that initiates the IPI request belongs.
  • the IPI interrupt manager When it is necessary to notify the VMM to process the IPI request, the IPI interrupt manager writes the identification information of the vCPU with the IPI request to be sent into the vCPU set data area of the IPI request to be sent, and writes the identification information of the virtual machine to which the vCPU with the IPI request to be sent belongs. Enter the VM set data area of the IPI request to be sent, and send the VMM notification interrupt, the VMM notification interrupt can wake up the VMM to process the IPI request.
  • the interrupt processing method includes:
  • Step S141 write the identification information of the vCPU that initiates the IPI request into the IPI request vCPU set data area to be sent in the storage space of the current IPI interrupt manager;
  • Step S142 write the identification information of the virtual machine to which the vCPU that initiates the IPI request belongs to the IPI request VM set data area to be sent in the storage space of the current IPI interrupt manager;
  • Step S143 sending the VMM notification interruption according to the preset virtual machine manager (VMM) notification interruption vector.
  • VMM virtual machine manager
  • the vCPU that initiates the IPI request writes the IPI request information to the vCPU in the IPI request information area.
  • the vCPU can be scheduled in most cases, so as to ensure that the virtual machine does not need to exit the Guest during the notification process of the IPI request in most cases. state.
  • the bits in the data area of the vCPU set of the IPI request to be sent correspond one-to-one with the vCPUs, and the bit position in the data area of the vCPU set of the IPI request to be sent indicates that the corresponding vCPU has an IPI request to be sent;
  • the bits of the VM set data area of the IPI request to be sent correspond to the virtual machines one-to-one, and the bit position of the VM set data area of the IPI request to be sent indicates that the vCPU in the corresponding virtual machine has an IPI request to be sent.
  • step S141 includes:
  • Step S141a with the identifier of the vCPU that initiates the IPI request as an offset, set the corresponding bits in the vCPU set data area of the IPI request to be sent;
  • Step S142 includes:
  • Step S142a according to the identifier of the virtual machine to which the vCPU that initiates the IPI request belongs, set the corresponding bit in the data area of the VM set of the to-be-sent IPI request.
  • the VMM acquires the physical first address of the storage space of the IPI interrupt manager during initialization, and applies for the IPI request information area to the IPI interrupt manager when creating a virtual machine.
  • the IPI interrupt manager allocates the IPI request information area to the virtual machine, and returns the index number of the allocated IPI request information area. Through the index number and the physical first address of the storage space of the IPI interrupt manager obtained by the VMM during initialization, you can Determine the address of the IPI request information area corresponding to the virtual machine.
  • the interrupt processing method further includes:
  • Step S151 in response to the message of applying for the IPI request information area, allocate the IPI request information area for the target virtual machine;
  • Step S152 the index number of the IPI request information area allocated to the target virtual machine is returned.
  • an embodiment of the present disclosure provides an interrupt processing method, including:
  • Step S210 when the vCPU initiates an IPI request, write the IPI request information into the IPI request information area in the storage space of the IPI interrupt manager corresponding to the virtual machine to which the vCPU belongs, where the IPI request information carries the identifier of at least one target vCPU , the storage space of the IPI interrupt manager includes at least one of the IPI request information area, and the physical address of the IPI request information area is mapped to the corresponding virtual machine through MMIO; And
  • Step S220 when the target vCPU receives a predetermined interrupt request, invokes an IPI processing operation to process the predetermined interrupt request.
  • step S210 is performed by the host Host when any virtual machine initiates an IPI request
  • step S220 is performed by the host Host when any virtual machine receives a predetermined interrupt request.
  • An embodiment of the present disclosure provides an IPI interrupt manager, where the storage space of the IPI interrupt manager is divided into multiple IPI request information areas, each IPI request information area corresponds to a virtual machine, and is used to store the data sent by the vCPU of the virtual machine. IPI interrupt request information.
  • the IPI interrupt manager triggers the IPI processing action by monitoring the write operation of the virtual machine to the corresponding IPI request information area.
  • the IPI request information area is mapped to the corresponding virtual machine through memory-mapped IO (MMIO, Memory-mapped I/O). After the MMIO mapping is done, the CPU can access the I/O devices using instructions that access memory.
  • the physical address of the IPI request information area is mapped to the corresponding virtual machine through MMIO, and the MMIO mapping between the IPI request information area and the corresponding virtual machine is completed, and the vCPU of the virtual machine can use the instruction of the CPU to access the memory to
  • the IPI interrupt request information is written into the corresponding IPI request information area. Therefore, during the notification process of the IPI interruption, the virtual machine does not need to exit the Guest state.
  • the predetermined interrupt request described in step S220 can be directly injected into the target vCPU without causing the target vCPU to exit the Guest state.
  • the predetermined interrupt request is an MSI request, and the type of the MSI request is a Posted-Interrupt in a remapping manner.
  • the predetermined interrupt request received by the vCPU is processed as an IPI interrupt, that is, in step S220, when a predetermined interrupt request is received, an IPI processing operation is invoked to process the predetermined interrupt request.
  • the predetermined interrupt request received by the target vCPU is directly injected into the target vCPU based on the hardware interrupt virtualization function provided by the CPU, and the target vCPU does not need to exit the Guest state. Therefore, in the embodiment of the present disclosure, the current vCPU does not need to exit the Guest state when receiving the IPI interrupt.
  • an IPI interrupt manager is provided.
  • the IPI request information area in the storage space of the IPI interrupt manager is mapped to the corresponding virtual machine through memory mapping input and output (MMIO).
  • MMIO memory mapping input and output
  • the IPI interrupt manager converts the IPI interrupt to be able to be directly injected into the target vCPU without causing the target vCPU
  • the scheduled interrupt to exit the Guest state based on the hardware interrupt virtualization function provided by the CPU, can realize the direct injection of IPI interrupts into the target vCPU, and the target vCPU does not need to exit the Guest state when receiving the IPI interrupt.
  • the virtual machine does not need to exit the Guest state, which reduces the performance loss caused by the virtualization exit, and improves the virtualization operation efficiency.
  • the IPI request information area in the storage space of the IPI interrupt manager is further divided to obtain multiple IPI request information memory blocks corresponding to the vCPUs one-to-one.
  • the vCPU sends an IPI request, it writes the IPI request information into the corresponding IPI request information memory block.
  • step S210 includes:
  • Step S211 write the IPI request information into the IPI request information memory block corresponding to the vCPU that initiates the IPI request, the IPI request information area corresponding to each virtual machine includes a plurality of the IPI request information memory blocks, the IPI request information Memory blocks correspond one-to-one with vCPUs in a virtual machine.
  • the virtual machine is created by the VMM.
  • the VMM When creating a virtual machine, the VMM will apply to the IPI interrupt manager for the IPI request information area corresponding to the virtual machine to be created, and after the virtual machine is created, complete the MMIO mapping between the virtual machine and the corresponding IPI request information area.
  • the IPI interrupt manager allocates the IPI request information area to the virtual machine, and returns the index number of the allocated IPI request information area. Through the index number and the physical first address of the storage space of the IPI interrupt manager obtained by the VMM during initialization, you can Determine the physical address of the IPI request information area corresponding to the virtual machine. In some implementations, the index number is used as the identifier of the virtual machine to be created.
  • the interrupt processing method before step S210, the interrupt processing method further includes:
  • Step S230 sending a message for applying for an IPI request information area to the IPI interrupt manager
  • Step S240 creating a target virtual machine, the identifier of the target virtual machine is the index number of the IPI request information area allocated to the target virtual machine returned by the IPI interrupt manager;
  • Step S250 Map the IPI request information area allocated to the target virtual machine to the target virtual machine through MMIO.
  • the IPI interrupt manager in the embodiments of the present disclosure exists as a PCI device.
  • a virtual PCI device is created corresponding to an IPI interrupt manager existing as a PCI device, and the base address register of the virtual PCI device stores the physical first address of the IPI request information area allocated to the virtual machine as the base address .
  • the virtual machine writes the IPI request information into the IPI request information area in the IPI interrupt manager by communicating with the virtual PCI device.
  • step S250 includes:
  • Step S251 according to the index number of the received IPI request information area and the storage space physical address of the described IPI interrupt manager assigned to the target virtual machine, determine the IPI request information area assigned to the target virtual machine. physical address;
  • Step S252 create a virtual PCI device, and the base address register (BAR) of the virtual PCI device stores the physical first address assigned to the IPI request information area of the target virtual machine;
  • Step S253 creating a virtual PCI device driver.
  • the IPI interrupt manager converts the IPI interrupt into an MSI interrupt, and the type of the MSI interrupt is a release type interrupt in a remapping manner, so that the virtual machine does not need to exit the Guest state when the IPI interrupt is injected into the target vCPU .
  • the Posted-Interrupt attribute is configured by the VMM for the IPI Interrupt Manager. That is, by writing configuration content into the MSI configuration register of the IPI interrupt manager, the Posted-Interrupt attribute is configured for the IPI interrupt manager, so that the type of the MSI generated in the IPI interrupt manager is a post-type interrupt in the remapping mode.
  • an interrupt remapping table entry (IRTE, Interrupt Remap Table Entry) is allocated to each pCPU by the VMM, that is, the interrupt remapping table entry of the pCPU in the interrupt remapping table managed by the IO-APIC.
  • the storage space of the IPI interrupt manager further includes a pCPU information area, where the pCPU ID and the IRTE index corresponding to the pCPU are stored in the pCPU information area.
  • the interrupt processing method before step S210, the interrupt processing method further includes:
  • Step S260 assigning an interrupt remapping table entry IRTE to each physical central processing unit pCPU;
  • Step S270 configure Posted Interrupt attribute for described IPI interrupt manager
  • Step S280 Write the identifier of the pCPU and the IRTE index corresponding to the pCPU into the pCPU information area in the storage space of the IPI interrupt manager.
  • the storage space of the IPI interrupt manager includes multiple vCPU scheduling information areas, the multiple vCPU scheduling information areas are in one-to-one correspondence with multiple vCPUs, and the vCPU scheduling information area stores pCPUs that schedule the corresponding vCPUs 's identification.
  • the scheduling information of the vCPU is written into the corresponding vCPU scheduling information area by the VMM.
  • the interrupt processing method further includes:
  • Step S290 when scheduling the vCPU, write the identifier of the pCPU that schedules the vCPU into the vCPU scheduling information area corresponding to the scheduled vCPU, the storage space of the IPI interrupt manager includes multiple vCPU scheduling information areas, and the multiple vCPU scheduling information areas are Each vCPU scheduling information area is in one-to-one correspondence with multiple vCPUs.
  • the vCPU scheduling information area is mapped into the host memory, so that it can be directly accessed by the VMM.
  • the IPI interrupt manager when the target vCPU is scheduled, the IPI interrupt manager generates a predetermined interrupt request, and directly sends the predetermined interrupt to the target vCPU through the interrupt controller; when the target vCPU is not scheduled, the IPI interrupt manager then Notifies the VMM to handle the IPI request.
  • the IPI interrupt manager of the embodiment of the present disclosure further includes a data area of the to-be-sent IPI request vCPU set for storing the to-be-sent IPI request vCPU set, and a to-be-sent IPI request vCPU set data area for storing the VM set to which the to-be-sent IPI request vCPU belongs.
  • the vCPU set to send the IPI request refers to the set of vCPUs that initiate the IPI request
  • the VM set to which the vCPU to send the IPI request belongs refers to the set of virtual machines to which the vCPU that initiates the IPI request belongs.
  • the IPI interrupt manager When it is necessary to notify the VMM to process the IPI request, the IPI interrupt manager writes the identification information of the vCPU with the IPI request to be sent into the vCPU set data area of the IPI request to be sent, and writes the identification information of the virtual machine to which the vCPU with the IPI request to be sent belongs. Enter the VM set data area of the IPI request to be sent, and send the VMM notification interrupt, the VMM notification interrupt can wake up the VMM to process the IPI request.
  • the VMM determines the virtual machine to which the vCPU that has the IPI request to be sent belongs by reading the data area of the VM set of the IPI request to be sent, and determines the vCPU that has the IPI request to be sent by reading the data area of the vCPU set of the IPI request to be sent. Then, the corresponding IPI request information is read from the IPI request information area corresponding to the vCPU that has the IPI request to be sent, and the IPI interrupt transmission is completed.
  • the interrupt processing method further includes:
  • Step S310 in response to the interruption of the VMM notification sent by the IPI interrupt manager, read the VM set data area of the IPI request to be sent in the storage space of the IPI interrupt manager, and determine the virtual machine to which the vCPU of the IPI request to be sent belongs. identification;
  • Step S320 read the vCPU set data area of the IPI request to be sent in the storage space of the IPI interrupt manager, and determine the identifier of the vCPU to be sent the IPI request;
  • Step S330 according to the identity of the virtual machine to which the vCPU to send the IPI request belongs and the identity of the vCPU to which the IPI request is to be sent, read the IPI request information memory block corresponding to the vCPU to which the IPI request is to be sent, and obtain the IPI request information;
  • Step S340 sending an IPI request according to the acquired IPI request information.
  • the bits in the data area of the vCPU set of the IPI request to be sent correspond one-to-one with the vCPUs, and the bit position in the data area of the vCPU set of the IPI request to be sent indicates that the corresponding vCPU has an IPI request to be sent;
  • the bits of the VM set data area of the IPI request to be sent correspond to the VMs one-to-one, and the bit position of the VM set data area of the IPI request to be sent indicates that the vCPU in the corresponding VM has an IPI request to be sent.
  • the VMM determines the virtual machine to which the vCPU for which the IPI request is to be sent belongs by reading the bits in the data area of the VM set of the IPI request to be sent. Sent vCPUs.
  • the VMM after the VMM completes sending the IPI interrupt, it further includes:
  • FIG. 16 is a schematic diagram of the storage space of the IPI interrupt manager according to the embodiment of the disclosure.
  • each IPI interrupt information storage space includes:
  • the IPI interrupt request information area is 4K page aligned.
  • Each IPI interrupt request information area is divided into multiple IPI request information memory blocks, and the multiple IPI request information memory blocks correspond to each vCPU in the VM one-to-one.
  • each IPI request information memory block is 32 bits, including 16-bit IPI target vCPU information and 16-bit IPI interrupt vector number, the IPI interrupt request information area is mapped to the corresponding VM through MMIO, and can be directly written by the vCPU;
  • the vCPU status information area includes the vCPU scheduling information area and the vCPU set data area of the IPI request to be sent.
  • the vCPU scheduling information area stores the corresponding relationship between vCPU and pCPU;
  • the vCPU set data area of the IPI request to be sent stores the vCPU ID waiting to send the IPI, and the vCPU status
  • the information area is mapped into the Host memory and can be directly accessed by the VMM;
  • the pCPU information data area includes the pCPU ID and the assigned index idx of the IRTE corresponding to the Posted Interrupt;
  • the VMM notification interrupt vector data area is used to store the interrupt number of the VMM notification interrupt.
  • the data area of the VM set of the IPI request to be sent indicating in bit mode the VM to which the vCPU whose IPI information is to be sent belongs.
  • the pCPU information data area, the VMM notification interrupt vector data area, and the to-be-sent IPI request VM set data area can only be accessed by the host VMM.
  • This example provides the initialization process of the host VMM, including:
  • the VMM When the VMM is initialized, it reads the PCI control information, obtains the physical first address of the storage space of the IPI interrupt manager, and completes the MMIO mapping;
  • the VMM assignment sets the VMM notification interrupt, and the IPI interrupt manager can wake up the VMM by sending the VMM notification interrupt;
  • VMM sets the Posted Interrupt interrupt, and its setting method is:
  • This instance provides the VM creation process, including:
  • VMM After VMM receives the virtual machine creation command, it applies for a new virtual machine IPI request information area from the IPI interrupt manager;
  • the VMM creates the VM and creates an IPI virtual PCI device whose BAR address space is set to the newly allocated IPI request information area address;
  • the virtual machine When the virtual machine is started, it creates an IPI driver, obtains the address of the IPI request information area corresponding to the virtual machine from the virtual PCI device, and completes the MMIO mapping, which is actually mapped to the corresponding IPI request information area. Subsequently, the IPI driver can directly write through the virtual address space GVA to complete the IPI interrupt request. Since each VM can only map its corresponding IPI request information area, the IPI requests of different VMs will not affect other VMs, which supports the security isolation feature.
  • VM ID and vCPU ID locate the corresponding vCPU scheduling information area
  • this example provides an IPI interrupt sending and processing flow, including:
  • the vCPU calls the IPI driver to send an IPI interrupt, the IPI driver obtains the vCPU ID, determines the IPI request information area corresponding to the vCPU, and writes the IPI destination vCPU and IPI vector into the IPI request information area;
  • the write operation of the IPI request information area triggers the IPI interrupt manager, and the IPI interrupt manager analyzes the IPI request information written into the IPI request information area, determines the target vCPU set of the IPI interrupt, and checks the vCPU status information area to determine the target vCPU schedule. state;
  • the IRTE idx of the posted int. and the IPI vector to be sent will be obtained according to the pCPU information corresponding to the target vCPU, assembled into interrupt request information, and a predetermined interrupt request will be sent to the interrupt controller.
  • the request has been set to Posted Interrupt Remapping, it will be sent directly to the corresponding target pCPU to complete the interrupt transmission;
  • the IPI interrupt manager sets the corresponding bit in the data area of the vCPU set of the IPI request to be sent with the corresponding vCPU ID as the offset, and uses the VM ID to set the corresponding bit in the data area of the VM set of the IPI request to be sent.
  • send VMM notification interrupt VMM will read the VM set data area of the IPI request to be sent, obtain the corresponding VM ID, and then read the vCPU set data area of the corresponding VM to be sent IPI request, for which bit, read the IPI request information area corresponding to the vCPU, obtain the IPI request information, and then complete the IPI interrupt transmission one by one.
  • an IPI interrupt manager which includes:
  • processors 101 one or more processors 101;
  • a memory 102 having stored thereon one or more computer programs that, when executed by the one or more processors 101, cause the one or more processors 101 to implement the present disclosure Example of the interrupt handling method provided in the first aspect;
  • One or more I/O interfaces 103 are connected between the processor 101 and the memory 102 , and are configured to implement information interaction between the processor 101 and the memory 102 .
  • the processor 101 is a device with data processing capabilities, including but not limited to a central processing unit (CPU), etc.; the memory 102 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM) , DDR, etc.), read-only memory (ROM), electrified erasable programmable read-only memory (EEPROM), flash memory (FLASH); I/O interface (read-write interface) 103 is connected between the processor 101 and the memory 102, and can The information interaction between the processor 101 and the memory 102 is implemented, which includes but is not limited to a data bus (Bus) and the like.
  • Buss data bus
  • processor 101, memory 102, and I/O interface 103 are interconnected by bus 104, and in turn are connected to other components of the computing device.
  • an electronic device which includes:
  • processors 201 one or more processors 201;
  • a memory 202 having stored thereon one or more computer programs that, when executed by the one or more processors 201, cause the one or more processors 201 to implement the present disclosure
  • the interrupt processing method provided by the first aspect and/or the interrupt processing method provided by the second aspect;
  • One or more I/O interfaces 203 are connected between the processor 201 and the memory 202 , and are configured to implement information interaction between the processor 201 and the memory 202 .
  • the processor 201 is a device with data processing capabilities, including but not limited to a central processing unit (CPU), etc.; the memory 202 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM) , DDR, etc.), read-only memory (ROM), electrified erasable programmable read-only memory (EEPROM), flash memory (FLASH); I/O interface (read-write interface) 203 is connected between the processor 201 and the memory 202, and can The information interaction between the processor 201 and the memory 202 is implemented, including but not limited to a data bus (Bus) and the like.
  • a data bus Buss
  • processor 201, memory 202, and I/O interface 203 are interconnected by bus 204, and in turn are connected to other components of the computing device.
  • an embodiment of the present disclosure provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, implements the interrupt processing method provided in the first aspect of the embodiment of the present disclosure , and/or the interrupt processing method provided by the second aspect.
  • Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).
  • computer storage media includes both volatile and nonvolatile implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules or other data flexible, removable and non-removable media.
  • Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, magnetic tape, magnetic disk storage or other magnetic storage devices, or may Any other medium used to store desired information and that can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and can include any information delivery media, as is well known to those of ordinary skill in the art .
  • Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should only be construed in a general descriptive sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics described in connection with other embodiments unless expressly stated otherwise and/or components used in combination. It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the present disclosure as set forth in the appended claims.

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Abstract

本公开提供一种中断处理方法，包括：当处理器间中断(IPI)请求信息区写入IPI请求信息时，根据所述IPI请求信息生成预定中断请求，所述IPI请求信息携带至少一个目标虚拟中央处理器(vCPU)的标识，当前IPI中断管理器的存储空间包括至少一个所述IPI请求信息区，所述IPI请求信息区对应有虚拟机，所述IPI请求信息区的物理地址通过内存映射输入输出MMIO映射到对应的虚拟机；以及将所述预定中断请求发送到中断控制器，以使所述中断控制器将所述预定中断请求发送到各个所述目标vCPU。本公开还提供一种中断管理器、一种电子设备、和一种计算机可读存储介质。

Description

中断处理方法、中断管理器、电子设备、计算机可读存储介质
相关申请的交叉引用
本申请要求于2020年7月1日提交的中国专利申请NO.202010625104.7的优先权，该中国专利申请的内容通过引用的方式整体合并于此。
技术领域
本公开涉及通信技术领域，特别涉及中断处理方法、中断管理器、电子设备、和计算机可读存储介质。
背景技术
虚拟化支持一个物理主机运行多个逻辑主机(虚拟机)，从而可以获得安全隔离和高利用率等特性。虚拟机可以有多个虚拟中央处理器(vCPU)，以提供更好的运行性能。为了支持多个vCPU间的同步，操作系统需要虚拟化提供处理器间中断(IPI，Inter-Processor Interrupts)机制。IPI机制允许一个vCPU向多个vCPU发送中断，一般可执行地址转换缓存器(TLB，Translation Lookaside Buffer)刷新、跨CPU函数调用等操作，是操作系统的重要运行机制。
但是，IPI虚拟化的运行效率较低。
公开内容
第一方面，本公开实施例提供一种中断处理方法，包括：
当IPI请求信息区写入处理器间中断(IPI)请求信息时，根据所述IPI请求信息生成预定中断请求，所述IPI请求信息携带至少一个目标虚拟中央处理器(vCPU)的标识，当前中断管理器的存储空间包括至少一个所述IPI请求信息区，所述IPI请求信息区对应有虚拟机，所述IPI请求信息区通过内存映射输入输出MMIO映射到对应的 虚拟机；以及
将所述预定中断请求发送到中断控制器，以使所述中断控制器将所述预定中断请求发送到各个所述目标vCPU。
第二方面，本公开实施例提供一种中断处理方法，包括：
当vCPU发起IPI请求时，将IPI请求信息写入发起IPI请求的vCPU所属虚拟机对应的中断管理器的存储空间中的IPI请求信息区，所述IPI请求信息携带至少一个目标vCPU的标识，其中，所述中断管理器的存储空间包括至少一个所述IPI请求信息区，所述IPI请求信息区的物理地址通过MMIO映射到对应的虚拟机；以及
当目标vCPU接收到预定中断请求时，调用IPI处理操作处理所述预定中断请求。
第三方面，本公开实施例提供一种中断管理器，包括：
一个或多个处理器；
存储装置，其上存储有一个或多个计算机程序，当所述一个或多个计算机程序被所述一个或多个处理器执行时，使得所述一个或多个处理器实现本公开实施例第一方面提供的中断处理方法。
第四方面，本公开实施例提供一种电子设备，包括：
一个或多个处理器；
存储装置，其上存储有一个或多个计算机程序，当所述一个或多个计算机程序被所述一个或多个处理器执行时，使得所述一个或多个处理器实现本公开实施例第一方面提供的中断处理方法、和/或第二方面提供的中断处理方法；
一个或多个I/O接口，连接在所述处理器与所述存储装置之间，配置为实现所述处理器与所述存储装置的信息交互。
第五方面，本公开实施例提供一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现本公开实施例第一方面提供的中断处理方法、和/或第二方面提供的中断处理方法。
附图说明
图1为相关技术中IPI虚拟化示意图；
图2为本公开实施例中的中断处理方法的流程图；
图3为本公开实施例中的IPI虚拟化示意图；
图4为本公开实施例中的中断处理方法中部分步骤的流程图；
图5为本公开实施例中的中断处理方法中部分步骤的流程图；
图6为本公开实施例中的中断处理方法中部分步骤的流程图；
图7为本公开实施例中的中断处理方法中部分步骤的流程图；
图8为本公开实施例中的中断处理方法中部分步骤的流程图；
图9为本公开实施例中的中断处理方法的流程图；
图10为本公开实施例中的中断处理方法中部分步骤的流程图；
图11为本公开实施例中的中断处理方法中部分步骤的流程图；
图12为本公开实施例中的中断处理方法中部分步骤的流程图；
图13为本公开实施例中的中断处理方法中部分步骤的流程图；
图14为本公开实施例中的中断处理方法中部分步骤的流程图；
图15为本公开实施例中的中断处理方法中部分步骤的流程图
图16为本公开实施例中的IPI中断管理器的存储空间的示意图；
图17为本公开实施例中的IPI虚拟化示意图；
图18为本公开实施例中的IPI中断管理器的组成框图；
图19为本公开实施例中的电子设备的组成框图；以及
图20为本公开实施例中的计算机可读存储介质的组成框图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的中断处理方法、中断管理器、电子设备、计算机可读存储介质进行详细描述。
在下文中将参考附图更充分地描述示例实施例，但是所述示例实施例可以以不同形式来体现且不应当被解释为限于本文阐述的实施例。提供这些实施例的目的在于使本公开更加透彻和完整，并使本领域技术人员充分理解本公开的范围。
在不冲突的情况下，本公开各实施例及实施例中的各特征可相 互组合。
如本文所使用的，术语“和/或”包括一个或多个相关列举条目的任何和所有组合。
本文所使用的术语仅用于描述特定实施例，且不意欲限制本公开。如本文所使用的，单数形式“一个”和“该”也意欲包括复数形式，除非上下文另外清楚指出。还将理解的是，当本说明书中使用术语“包括”和/或“由……制成”时，指定存在特定特征、整体、步骤、操作、元件和/或组件，但不排除存在或可添加一个或多个其它特征、整体、步骤、操作、元件、组件和/或其群组。
除非另外限定，否则本文所用的所有术语(包括技术术语和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本文明确如此限定。
图1为相关技术中IPI虚拟化的示意图。如图1所示，当vCPU发送IPI中断时，可以直接操作中断控制器；也可以通过VP方式，通知虚拟机管理器(VMM，Virtual Machine Manager)，再由VMM检查IPI中断的目标vCPU，并一一发送IPI中断。经研究发现，上述发送IPI中断的方式都将使得虚拟机(VM，Virtual Machine)退出Guest模式，切换到主机Host模式。
在另一种IPI虚拟化技术中，当vCPU发送IPI中断时，一次性将虚拟机的多次IPI中断信息通知主机Host。经研究发现，在此种IPI虚拟化技术中，虽然减少了VM的退出Guest状态的次数，但在通知过程中，还是有至少一次退出Guest状态。
虚拟机退出Guest状态时需要进行大量的状态保存和切换工作，再次进入虚拟化状态还需要恢复保存的状态，因此，相关技术中的IPI虚拟化技术性能损耗较大。
有鉴于此，第一方面，参照图2，本公开实施例提供一种中断处理方法，包括以下步骤S110和S120。
在步骤S110中，当IPI请求信息区写入处理器间中断(IPI) 请求信息时，根据所述IPI请求信息生成预定中断请求，所述IPI请求信息携带至少一个目标虚拟中央处理器(vCPU)的标识，当前IPI中断管理器的存储空间包括至少一个所述IPI请求信息区，所述IPI请求信息区对应有虚拟机，所述IPI请求信息区通过内存映射输入输出(MMIO)映射到对应的虚拟机。
在步骤S120中，将所述预定中断请求发送到中断控制器，以使所述中断控制器将所述预定中断请求发送到各个所述目标vCPU。
如图3所示，本公开实施例提供一种IPI中断管理器，所述IPI中断管理器的存储空间划分为多个IPI请求信息区，每个IPI请求信息区对应一个虚拟机，用于存储虚拟机的vCPU发送的IPI中断请求信息。IPI中断管理器通过监控虚拟机向对应的IPI请求信息区的写操作，触发IPI处理动作。
在本公开实施例中，通过内存映射IO(MMIO，Memory-mapped I/O)将IPI请求信息区映射到对应的虚拟机中。需要说明的是，MMIO是外设部件互连标准(PCI，Peripheral Component Interconnect)规范的一部分，I/O设备被放置在内存空间而不是I/O空间，完成MMIO映射后，CPU可以使用访问内存的指令访问I/O设备。在本公开实施例中，将IPI请求信息区的物理地址通过MMIO映射到对应的虚拟机，完成IPI请求信息区与对应的虚拟机的MMIO映射，虚拟机的vCPU可以使用CPU访问内存的指令将IPI中断请求信息写入对应的IPI请求信息区。因此，在IPI中断的通知过程中，虚拟机不需要退出Guest状态。
需要说明的是，在本公开实施例中，所述IPI中断管理器可以基于硬件实现，也可以基于软件实现。本公开实施例不做特殊限定。
在步骤S110中，根据写入IPI请求信息区的IPI请求信息生成的预定中断请求能够直接注入到目标vCPU而无需使目标vCPU退出Guest状态。在一些实施方式中，所述预定中断为外部中断，例如，消息信号中断(MSI，Message Signaled Interrupts)。
在本公开实施例中，基于CPU提供的硬件中断虚拟化功能，可以实现IPI中断直接注入目标vCPU，而目标vCPU无需退出Guest状 态。例如，在X86架构上，基于VT-D(Virtualization Technology for Direct I/O)机制实现外部中断直接由虚拟机处理；在ARM架构上，基于vGSI机制实现外部中断直接由虚拟机处理。因此，在本公开实施例中，通过将IPI中断请求转换为能够直接注入到目标vCPU而无需使目标vCPU退出Guest状态的预定中断请求，实现将IPI中断注入目标vCPU时虚拟机无需退出Guest状态。
本公开实施例提供的中断处理方法中，提供了一种IPI中断管理器，IPI中断管理器的存储空间中的IPI请求信息区通过内存映射输入输出(MMIO)映射到对应的虚拟机，当vCPU发送IPI中断时，vCPU能够直接将IPI中断请求信息写入对应的IPI请求信息区，而无需退出Guest状态；所述IPI中断管理器将IPI中断转换为能够直接注入到目标vCPU而无需使目标vCPU退出Guest状态的预定中断，基于CPU提供的硬件中断虚拟化功能，可以实现IPI中断直接注入目标vCPU，而目标vCPU无需退出Guest状态。因此，本公开实施例中，在vCPU发送IPI中断请求信息和将IPI中断注入目标vCPU的过程中，虚拟机都无需退出Guest状态，降低了虚拟化退出造成的性能损耗，提升了虚拟化运行效率。
在一些实施方式中，在X86架构上，基于VT-D机制将MSI中断注入目标vCPU，从而使虚拟机无需退出Guest状态就可以响应中断。
在X86架构上，中断控制器为高级可编程中断控制器(APIC，Advanced Programmable Interrupt Controller)，包括IO-APIC和Local-APIC两部分。IO-APIC为系统唯一，用于管理外部MSI中断到Local-APIC的转发；每个CPU有一个Local-APIC，用于管理从IO-APIC路由的MSI中断到对应CPU的发送，同时也管理IPI中断的发送。在中断虚拟化场景中，IO-APIC支持重映射方式(reMapping)，在IO-APIC中管理中断重映射表，所述中断重映射表中包括多个物理中央处理器(pCPU)的中断重映射表项。如果识别到设备发送的MSI中断为重映射方式、且为发布类型中断(Posted-Interrupt)时，根据该MSI中断中携带的信息查找中断重映射表中对应的中断重映射表项，确定该MSI中断对应的通知向量(Notify Vector)，然后将 中断发送到Local-APIC中。如果对应的目标vCPU已被调度，则Local-APIC会直接发送中断到目标vCPU上，如果对应的目标vCPU未调度，则会通知VMM处理。
在一些实施方式中，步骤S110中将IPI中断转换为MSI中断，且所述MSI中断的类型为重映射(Remapping)方式的发布类型中断(Posted Interrupt)，从而实现将IPI中断注入目标vCPU时虚拟机无需退出Guest状态。
相应地，参照图4，在一些实施方式中，步骤S110包括：
步骤S111，根据所述IPI请求信息生成作为所述预定中断请求的消息信号中断(MSI)请求，所述MSI请求的类型为重映射方式的发布类型中断(Posted-Interrupt)。
需要说明的是，在本公开实施例中，在IPI中断管理器的配置空间中有MSI配置寄存器，通过设置该MSI配置寄存器的内容，可以将IPI中断管理器中生成的MSI的类型配置为重映射方式的发布类型中断。
在一些实施方式中，由VMM为所述IPI中断管理器配置Posted-Interrupt属性。即，通过向IPI中断管理器的MSI配置寄存器中写入配置内容，为IPI中断管理器配置Posted-Interrupt属性，从而使得IPI中断管理器中生成的MSI的类型为重映射方式的发布类型中断。
在本公开实施例中，由VMM为每个pCPU分配一个中断重映射表项(IRTE，Interrupt Remap Table Entry)，即IO-APIC管理的中断重映射表中的pCPU的中断重映射表项。在本公开实施例中，IPI中断管理器的存储空间还包括pCPU信息区，所述pCPU信息区中存储pCPU ID和pCPU对应的IRTE索引。在通过步骤S111生成MSI请求信息时，根据目标vCPU对应的IRTE索引和待发送IPI vector，生成所述MSI请求，并将MSI请求发送到IO-APIC，以使得IO-APIC通过查找中断重映射表，将中断发送到对应的Local-APIC，并进一步注入已被调度的目标vCPU。
在本公开实施例中，IPI中断管理器的存储空间包括多个vCPU 调度信息区，所述多个vCPU调度信息区与多个vCPU一一对应，所述vCPU调度信息区存储调度对应vCPU的pCPU的标识。在IPI中断请求信息区写入IPI中断请求信息后，根据目标vCPU的标识，从目标vCPU对应的vCPU调度信息区读取调度所述目标vCPU的pCPU的标识。
相应地，参照图5，在一些实施方式中，所述IPI请求信息携带中断号vector，步骤S111包括：
步骤S111a，读取所述目标vCPU对应的vCPU调度信息区中存储的目标pCPU的标识，所述目标pCPU为调度所述目标vCPU的pCPU，当前IPI中断管理器的存储空间包括多个vCPU调度信息区，所述多个vCPU调度信息区与多个vCPU一一对应，所述vCPU调度信息区存储调度对应vCPU的pCPU的标识；
步骤S111b，根据所述目标pCPU的标识从pCPU信息区读取所述目标pCPU对应的中断重映射表项索引，当前IPI中断管理器的存储空间中的pCPU信息区存储多个pCPU标识与中断重映射表项索引的对应关系；以及
步骤S111c，根据各个目标pCPU对应的中断重映射表项索引和所述IPI请求信息携带的vector生成所述MSI请求。
在本公开实施例中，当目标vCPU被调度时，IPI中断管理器生成预定中断请求，并通过中断控制器直接将预定中断发送到目标vCPU；当目标vCPU未被调度时，IPI中断管理器则通知VMM处理IPI请求。
相应地，参照图6，在一些实施方式中，当IPI请求信息区写入处理器间中断(IPI)请求信息时，在步骤S110之前，所述中断处理方法还包括：
步骤S130，根据所述目标vCPU的标识确定所述目标vCPU的调度状态；
当所述目标vCPU被调度时，执行步骤S110。
在本公开实施例的IPI中断管理器的存储空间中，还包括用于存储待发送IPI请求vCPU集的待发送IPI请求vCPU集数据区、和用于存储待发送IPI请求vCPU所属VM集的待发送IPI请求VM集数据 区。待发送IPI请求vCPU集是指发起IPI请求的vCPU的集合，待发送IPI请求vCPU所属VM集是指发起IPI请求的vCPU所属VM的集合。
当需要通知VMM处理IPI请求时，IPI中断管理器将有IPI请求待发送的vCPU的标识信息写入待发送IPI请求vCPU集数据区，将有IPI请求待发送的vCPU所属虚拟机的标识信息写入待发送IPI请求VM集数据区，并发送VMM通知中断，所述VMM通知中断能够唤醒VMM处理IPI请求。
相应地，参照图6，当所述目标vCPU未被调度时，所述中断处理方法包括：
步骤S141，将发起IPI请求的vCPU的标识信息写入当前IPI中断管理器的存储空间中的待发送IPI请求vCPU集数据区；
步骤S142，将发起IPI请求的vCPU所属虚拟机的标识信息写入当前IPI中断管理器的存储空间中的待发送IPI请求VM集数据区；以及
步骤S143，根据预设虚拟机管理器(VMM)通知中断的vector发送VMM通知中断。
需要说明的是，发起IPI请求的vCPU即将IPI请求信息写入IPI请求信息区的vCPU。
需要说明的是，在本公开实施例中，通过将vCPU和pCPU绑定等方式，使得vCPU大部分情况下能被调度，从而确保大部分情况下在IPI请求的通知过程中虚拟机无需退出Guest状态。
在本公开实施例中，所述待发送IPI请求vCPU集数据区的比特位与vCPU一一对应，所述待发送IPI请求vCPU集数据区的比特位置位表示对应的vCPU有待发送的IPI请求；所述待发送IPI请求VM集数据区的比特位与虚拟机一一对应，所述待发送IPI请求VM集数据区的比特位置位表示对应的虚拟机中的vCPU有待发送的IPI请求。
相应地，参照图7，在一些实施方式中，步骤S141包括：
步骤S141a，以发起IPI请求的vCPU的标识为偏移，设置所述待发送IPI请求vCPU集数据区的对应比特位；
步骤S142包括：
步骤S142a，根据发起IPI请求的vCPU所属虚拟机的标识设置所述待发送IPI请求VM集数据区的对应比特位。
在本公开实施例中，VMM在初始化时会获取IPI中断管理器的存储空间的物理首地址，并在创建虚拟机时向IPI中断管理器申请IPI请求信息区。IPI中断管理器为虚拟机分配IPI请求信息区，并返回分配的IPI请求信息区的索引号，通过该索引号和VMM在初始化时获取的IPI中断管理器的存储空间的物理首地址，即可确定虚拟机对应的IPI请求信息区的地址。
相应地，参照图8，在一些实施方式中，所述中断处理方法还包括：
步骤S151，响应于申请IPI请求信息区的消息，为目标虚拟机分配IPI请求信息区；以及
步骤S152，返回分配给所述目标虚拟机的IPI请求信息区的索引号。
第二方面，参照图9，本公开实施例提供一种中断处理方法，包括：
步骤S210，当vCPU发起IPI请求时，将IPI请求信息写入所述vCPU所属虚拟机对应的IPI中断管理器的存储空间中的IPI请求信息区，所述IPI请求信息携带至少一个目标vCPU的标识，所述IPI中断管理器的存储空间包括至少一个所述IPI请求信息区，所述IPI请求信息区的物理地址通过MMIO映射到对应的虚拟机；以及
步骤S220，当目标vCPU接收到预定中断请求时，调用IPI处理操作处理所述预定中断请求。
需要说明的是，步骤S210是主机Host在任意一个虚拟机发起IPI请求时执行的，步骤S220是主机Host在任意一个虚拟机接收到预定中断请求时执行的。
本公开实施例提供一种IPI中断管理器，所述IPI中断管理器的存储空间划分为多个IPI请求信息区，每个IPI请求信息区对应一个虚拟机，用于存储虚拟机的vCPU发送的IPI中断请求信息。IPI中断管理器通过监控虚拟机向对应的IPI请求信息区的写操作，触发 IPI处理动作。
在本公开实施例中，通过内存映射IO(MMIO，Memory-mapped I/O)将IPI请求信息区映射到对应的虚拟机中。完成MMIO映射后，CPU可以使用访问内存的指令访问I/O设备。在本公开实施例中，将IPI请求信息区的物理地址通过MMIO映射到对应的虚拟机，完成IPI请求信息区与对应的虚拟机的MMIO映射，虚拟机的vCPU可以使用CPU访问内存的指令将IPI中断请求信息写入对应的IPI请求信息区。因此，在IPI中断的通知过程中，虚拟机不需要退出Guest状态。
需要说明的是，步骤S220中所述的预定中断请求能够直接注入到目标vCPU而无需使目标vCPU退出Guest状态。在一些实施方式中，所述预定中断请求为MSI请求，所述MSI请求的类型为重映射方式的发布类型中断(Posted-Interrupt)。
在本公开实施例中，将vCPU接收到的预定中断请求当做IPI中断进行处理，即在步骤S220中，当接收到预定中断请求时，调用IPI处理操作处理所述预定中断请求。
需要说明的是，目标vCPU接收到的预定中断请求，是基于CPU提供的硬件中断虚拟化功能，直接注入到目标vCPU，目标vCPU无需退出Guest状态。因此，在本公开实施例中，当前vCPU在接收IPI中断时，也无需退出Guest状态。
本公开实施例提供的中断处理方法中，提供了一种IPI中断管理器，IPI中断管理器的存储空间中的IPI请求信息区通过内存映射输入输出(MMIO)映射到对应的虚拟机，当vCPU发送IPI中断时，vCPU能够直接将IPI中断请求信息写入对应的IPI请求信息区，而无需退出Guest状态；所述IPI中断管理器将IPI中断转换为能够直接注入到目标vCPU而无需使目标vCPU退出Guest状态的预定中断，基于CPU提供的硬件中断虚拟化功能，可以实现IPI中断直接注入目标vCPU，目标vCPU在接收IPI中断时也无需退出Guest状态。因此，本公开实施例中在vCPU发送IPI中断请求信息和将IPI中断注入目标vCPU的过程中，虚拟机都无需退出Guest状态，降低了虚拟化退出造成的性能损耗，提升了虚拟化运行效率。
在本公开实施例中，对应于虚拟机的多个vCPU，将IPI中断管理器的存储空间中的IPI请求信息区进一步划分，得到与vCPU一一对应的多个IPI请求信息内存块。当vCPU发送IPI请求时，将IPI请求信息写入对应的IPI请求信息内存块中。
相应地，参照图10，在一些实施方式中，步骤S210包括：
步骤S211，将IPI请求信息写入发起IPI请求的vCPU对应的IPI请求信息内存块，每一个虚拟机对应的所述IPI请求信息区包括多个所述IPI请求信息内存块，所述IPI请求信息内存块与虚拟机中的vCPU一一对应。
在本公开实施例中，由VMM创建虚拟机。在创建虚拟机时，VMM会向IPI中断管理器申请待创建虚拟机对应的IPI请求信息区，并在创建虚拟机后，完成虚拟机与对应的IPI请求信息区的MMIO映射。IPI中断管理器为虚拟机分配IPI请求信息区，并返回分配的IPI请求信息区的索引号，通过该索引号和VMM在初始化时获取的IPI中断管理器的存储空间的物理首地址，即可确定虚拟机对应的IPI请求信息区的物理地址。在一些实施方式中，将该索引号作为待创建的虚拟机的标识。
相应地，参照图11，在一些实施方式中，在步骤S210之前，所述中断处理方法还包括：
步骤S230，向所述IPI中断管理器发送申请IPI请求信息区的消息；
步骤S240，创建目标虚拟机，所述目标虚拟机的标识为所述IPI中断管理器返回的分配给所述目标虚拟机的IPI请求信息区的索引号；以及
步骤S250，通过MMIO将分配给所述目标虚拟机的IPI请求信息区映射到所述目标虚拟机。
在一些实施方式中，本公开实施例中的IPI中断管理器以PCI设备存在。在本公开实施例中，对应于以PCI设备存在的IPI中断管理器，创建虚拟PCI设备，该虚拟PCI设备的基地址寄存器中存放分配给虚拟机的IPI请求信息区的物理首地址作为基地址。虚拟机通过 与该虚拟PCI设备进行通信将IPI请求信息写入IPI中断管理器中的IPI请求信息区。
相应地，参照图12，在一些实施方式中，步骤S250包括：
步骤S251，根据接收到的分配给所述目标虚拟机的IPI请求信息区的索引号和所述IPI中断管理器的存储空间物理首地址，确定分配给所述目标虚拟机的IPI请求信息区的物理地址；
步骤S252，创建虚拟PCI设备，所述虚拟PCI设备的基地址寄存器(BAR)存放分配给所述目标虚拟机的IPI请求信息区的物理首地址；以及
步骤S253，创建虚拟PCI设备驱动。
在本公开实施例中，IPI中断管理器将IPI中断转换为MSI中断，且所述MSI中断的类型为重映射方式的发布类型中断，从而实现将IPI中断注入目标vCPU时虚拟机无需退出Guest状态。需要说明的是，在本公开实施例中，在IPI中断管理器的配置空间中有MSI配置寄存器，通过设置该MSI配置寄存器的内容，可以将IPI中断管理器中生成的MSI的类型配置为重映射方式的发布类型中断。
在一些实施方式中，由VMM为所述IPI中断管理器配置Posted-Interrupt属性。即，通过向IPI中断管理器的MSI配置寄存器中写入配置内容，为IPI中断管理器配置Posted-Interrupt属性，从而使得IPI中断管理器中生成的MSI的类型为重映射方式的发布类型中断。
在本公开实施例中，由VMM为每个pCPU分配一个中断重映射表项(IRTE，Interrupt Remap Table Entry)，即IO-APIC管理的中断重映射表中的pCPU的中断重映射表项。在本公开实施例中，IPI中断管理器的存储空间还包括pCPU信息区，所述pCPU信息区中存储pCPU ID和pCPU对应的IRTE索引。
相应地，参照图13，在一些实施方式中，在步骤S210之前，所述中断处理方法还包括：
步骤S260，为各个物理中央处理器pCPU分配中断重映射表项IRTE；
步骤S270，为所述IPI中断管理器配置Posted Interrupt属性；以及
步骤S280，将pCPU的标识和所述pCPU对应的IRTE索引写入所述IPI中断管理器的存储空间中的pCPU信息区。
在本公开实施例中，IPI中断管理器的存储空间包括多个vCPU调度信息区，所述多个vCPU调度信息区与多个vCPU一一对应，所述vCPU调度信息区存储调度对应vCPU的pCPU的标识。在本公开实施例中，由VMM将vCPU的调度信息写入对应的vCPU调度信息区。
相应地，参照图14，在一些实施方式中，所述中断处理方法还包括：
步骤S290，当调度vCPU时，将调度所述vCPU的pCPU的标识写入被调度的vCPU对应的vCPU调度信息区，所述IPI中断管理器的存储空间包括多个vCPU调度信息区，所述多个vCPU调度信息区与多个vCPU一一对应。
需要说明的是，在本公开实施例中，vCPU调度信息区被映射入主机Host内存，从而可以被VMM直接访问。
在本公开实施例中，当目标vCPU被调度时，IPI中断管理器生成预定中断请求，并通过中断控制器直接将预定中断发送到目标vCPU；当目标vCPU未被调度时，IPI中断管理器则通知VMM处理IPI请求。
在本公开实施例的IPI中断管理器的存储空间中，还包括用于存储待发送IPI请求vCPU集的待发送IPI请求vCPU集数据区、和用于存储待发送IPI请求vCPU所属VM集的待发送IPI请求VM集数据区。待发送IPI请求vCPU集是指发起IPI请求的vCPU的集合，待发送IPI请求vCPU所属VM集是指发起IPI请求的vCPU所属虚拟机的集合。
当需要通知VMM处理IPI请求时，IPI中断管理器将有IPI请求待发送的vCPU的标识信息写入待发送IPI请求vCPU集数据区，将有IPI请求待发送的vCPU所属虚拟机的标识信息写入待发送IPI请求VM集数据区，并发送VMM通知中断，所述VMM通知中断能够唤醒VMM 处理IPI请求。VMM通过读取待发送IPI请求VM集数据区确定有IPI请求待发送的vCPU所属虚拟机，并通过读取待发送IPI请求vCPU集数据区确定有IPI请求待发送的vCPU。然后从有IPI请求待发送的vCPU对应的IPI请求信息区读取相应的IPI请求信息，并完成IPI中断发送。
相应地，参照图15，在一些实施方式中，所述中断处理方法还包括：
步骤S310，响应于所述IPI中断管理器发送的VMM通知中断，读取所述IPI中断管理器的存储空间中的待发送IPI请求VM集数据区，确定待发送IPI请求的vCPU所属虚拟机的标识；
步骤S320，读取所述IPI中断管理器的存储空间中的待发送IPI请求vCPU集数据区，确定待发送IPI请求的vCPU的标识；
步骤S330，根据待发送IPI请求的vCPU所属虚拟机的标识和待发送IPI请求的vCPU的标识，读取待发送IPI请求的vCPU对应的IPI请求信息内存块，获取IPI请求信息；以及
步骤S340，根据获取的IPI请求信息发送IPI请求。
在本公开实施例中，所述待发送IPI请求vCPU集数据区的比特位与vCPU一一对应，所述待发送IPI请求vCPU集数据区的比特位置位表示对应的vCPU有待发送的IPI请求；所述待发送IPI请求VM集数据区的比特位与VM一一对应，所述待发送IPI请求VM集数据区的比特位置位表示对应的VM中的vCPU有待发送的IPI请求。相应地，VMM通过读取待发送IPI请求VM集数据区的比特位确定有IPI请求待发送的vCPU所属虚拟机，通过读取待发送IPI请求vCPU集数据区的比特位，确定有IPI请求待发送的vCPU。
相应地，在本公开实施例中，VMM完成IPI中断发送后，还包括：
将所述待发送IPI请求VM集数据区中的比特位还原为初始状态；以及
将所述待发送IPI请求vCPU集数据区中的比特位还原为初始状态。
为了使本领域技术人员能够更清楚地理解本公开实施例提供的 技术方案，下面通过具体的实例，对本公开实施例提供的技术方案进行详细说明：
实例一
图16为本公开实施例中所述IPI中断管理器的存储空间的示意图。
如图16所示，在IPI中断管理器的存储空间中，不同虚拟机分别具有独立的IPI中断信息存储空间，每个IPI中断信息存储空间包括：
IPI中断请求信息区，为4K页面对齐。每个IPI中断请求信息区划分为多个IPI请求信息内存块，多个IPI请求信息内存块与VM中的各个vCPU一一对应，在本实例中，每个IPI请求信息内存块为32bit，包括16bit的IPI目标vCPU信息和16bit的IPI中断vector号，IPI中断请求信息区通过MMIO映射到对应的VM中，可被vCPU直接写入；
vCPU状态信息区，包括vCPU调度信息区和待发送IPI请求vCPU集数据区，vCPU调度信息区存储vCPU和pCPU的对应关系；待发送IPI请求vCPU集数据区存储等待发送IPI的vCPU ID，vCPU状态信息区被映射入Host内存，可以被VMM直接访问；
pCPU信息数据区，包括pCPU ID和分配的对应Posted Interrupt的IRTE的索引idx；
VMM通知中断vector数据区，用于存储VMM通知中断的中断号；以及
待发送IPI请求VM集数据区，以bit方式表示有IPI信息待发送的vCPU所属VM。
在本实例中，pCPU信息数据区、VMM通知中断vector数据区、待发送IPI请求VM集数据区只能被主机VMM访问。
实例二
本实例提供主机VMM的初始化流程，包括：
VMM初始化时，读取PCI控制信息，获取IPI中断管理器的存储空间物理首地址，并完成MMIO映射；
VMM分配设置VMM通知中断，IPI中断管理器可以通过发送VMM通知中断唤醒VMM；以及
VMM设置Posted Interrupt中断，其设置方法为：
遍历所有的pCPU；
为每个pCPU分配一个IRTE，并设置为Posted Interrupt的属性，设置其投递目标pCPU；以及
将该pCPU ID和对应的IRTE索引写入IPI中断管理器的pCPU信息区中。
实例三
本实例提供VM的创建流程，包括：
VMM接收到虚拟机创建命令后，从IPI中断管理器申请一个新的虚拟机IPI请求信息区；
VMM创建VM，并创建IPI虚拟PCI设备，该虚拟PCI设备的BAR地址空间设置为新分配的IPI请求信息区地址；以及
虚拟机在启动时，创建IPI驱动，从虚拟PCI设备中获取到该虚拟机对应的IPI请求信息区地址，并完成MMIO映射，该映射实际映射到对应的IPI请求信息区。后续，IPI驱动可以直接通过虚拟地址空间GVA进行写入，以完成IPI中断请求。由于每个VM只能映射各自对应的IPI请求信息区，因此不同的VM的IPI请求不会影响到其它的VM，支持了安全隔离特性。
实例四
参照图17，当VMM调度VM的vCPU运行时，进行如下操作：
根据VM ID和vCPU ID，定位到对应的vCPU调度信息区；
将vCPU将调度运行的pCPU ID写入对应的vCPU调度信息区；以及
当vCPU调出时，在对应的vCPU调度信息区写入值-1。
实例五
参照图17，本实例提供IPI中断发送和处理流程，包括：
vCPU调用IPI驱动发送IPI中断，IPI驱动获取vCPU ID，并确定对应vCPU的IPI请求信息区，将IPI的目的vCPU和IPI vector 写入该IPI请求信息区；
IPI请求信息区的写入操作触发IPI中断管理器，IPI中断管理器分析写入IPI请求信息区的IPI请求信息，确定IPI中断的目标vCPU集合，并检查vCPU状态信息区，确定目标vCPU的调度状态；
如果所有目标vCPU都处于调度状态，将按照目标vCPU对应的pCPU信息，获取posted int.的IRTE idx与待发送的IPI vector，组装成中断请求信息，并向中断控制器发送预定中断请求，该中断请求已经设置为Remapping的Posted Interrupt，会直接发送到对应的目标pCPU中，完成中断发送；以及
如果存在未调度的vCPU，IPI中断管理器以对应vCPU ID为偏移设置待发送IPI请求vCPU集数据区的对应bit位，并使用VM ID设置待发送IPI请求VM集数据区的对应bit位，并根据设置的VMM通知中断vector，发送VMM通知中断；VMM会读取待发送IPI请求VM集数据区，获取对应的VM ID，再读取对应VM的待发送IPI请求vCPU集数据区，对于其中的bit位，读取vCPU对应的IPI请求信息区，获取IPI请求信息，再一一完成IPI中断发送。
第三方面，参照图18，本公开实施例提供一种IPI中断管理器，其包括：
一个或多个处理器101；
存储器102，其上存储有一个或多个计算机程序，当所述一个或多个计算机程序被所述一个或多个处理器101执行时，使得所述一个或多个处理器101实现本公开实施例第一方面提供的中断处理方法；
一个或多个I/O接口103，连接在所述处理器101与所述存储器102之间，配置为实现所述处理器101与所述存储器102的信息交互。
处理器101为具有数据处理能力的器件，其包括但不限于中央处理器(CPU)等；存储器102为具有数据存储能力的器件，其包括但不限于随机存取存储器(RAM，更具体如SDRAM、DDR等)、只读存储器(ROM)、带电可擦可编程只读存储器(EEPROM)、闪存(FLASH)；I/O接口(读写接口)103连接在处理器101与存储器102间，能实现处理器101与存储器102的信息交互，其包括但不限于数据总线 (Bus)等。
在一些实施方式中，处理器101、存储器102和I/O接口103通过总线104相互连接，进而与计算设备的其它组件连接。
上文已经对本公开实施例第一方面提供的中断处理方法进行了详细描述，此处不再赘述。
第四方面，参照图19，本公开实施例提供一种电子设备，其包括：
一个或多个处理器201；
存储器202，其上存储有一个或多个计算机程序，当所述一个或多个计算机程序被所述一个或多个处理器201执行时，使得所述一个或多个处理器201实现本公开实施例第一方面提供的中断处理方法、和/或第二方面提供的中断处理方法；
一个或多个I/O接口203，连接在所述处理器201与所述存储器202之间，配置为实现所述处理器201与所述存储器202的信息交互。
处理器201为具有数据处理能力的器件，其包括但不限于中央处理器(CPU)等；存储器202为具有数据存储能力的器件，其包括但不限于随机存取存储器(RAM，更具体如SDRAM、DDR等)、只读存储器(ROM)、带电可擦可编程只读存储器(EEPROM)、闪存(FLASH)；I/O接口(读写接口)203连接在处理器201与存储器202间，能实现处理器201与存储器202的信息交互，其包括但不限于数据总线(Bus)等。
在一些实施方式中，处理器201、存储器202和I/O接口203通过总线204相互连接，进而与计算设备的其它组件连接。
上文已经对本公开实施例第一方面提供的中断处理方法、第二方面提供的中断处理方法进行了详细的描述，此处不再赘述。
第五方面，参照图20，本公开实施例提供一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现本公开实施例第一方面提供的中断处理方法、和/或第二方面提供的中断处理方法。
上文已经对本公开实施例第一方面提供的中断处理方法、第二 方面提供的中断处理方法进行了详细的描述，此处不再赘述。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些物理组件或所有物理组件可以被实施为由处理器(如中央处理器、数字信号处理器或微处理器)执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其它数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其它存储器技术、CD-ROM、数字多功能盘(DVD)或其它光盘存储、磁盒、磁带、磁盘存储或其它磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其它的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其它传输机制之类的调制数据信号中的其它数据，并且可包括任何信息递送介质。
本文已经公开了示例实施例，并且虽然采用了具体术语，但它们仅用于并仅应当被解释为一般说明性含义，并且不用于限制的目的。在一些实例中，对本领域技术人员显而易见的是，除非另外明确指出，否则与特定实施例相结合描述的特征、特性和/或元素可单独使用，或可与结合其它实施例描述的特征、特性和/或元件组合使用。本领域技术人员将理解，在不脱离由所附的权利要求阐明的本公开的范围的情况下，可进行各种形式和细节上的改变。

Claims (17)

  1. 一种中断处理方法，包括：
    当处理器间中断(IPI)请求信息区写入IPI请求信息时，根据所述IPI请求信息生成预定中断请求，所述IPI请求信息携带至少一个目标虚拟中央处理器(vCPU)的标识，其中，当前IPI中断管理器的存储空间包括至少一个所述IPI请求信息区，所述IPI请求信息区对应有虚拟机，所述IPI请求信息区通过内存映射输入输出MMIO映射到对应的虚拟机；以及
    将所述预定中断请求发送到中断控制器，以使所述中断控制器将所述预定中断请求发送到各个所述目标vCPU。
  2. 根据权利要求1所述的中断处理方法，其中，根据所述IPI请求信息生成预定中断请求包括：
    根据所述IPI请求信息生成作为所述预定中断请求的消息信号中断MSI请求，所述MSI请求的类型为重映射方式的发布类型中断(Posted-Interrupt)。
  3. 根据权利要求2所述的中断处理方法，其中，所述IPI请求信息携带中断号vector，根据所述IPI请求信息生成消息信号中断MSI请求包括：
    读取所述目标vCPU对应的vCPU调度信息区中存储的目标物理中央处理器pCPU的标识，所述目标pCPU为调度所述目标vCPU的pCPU，其中，当前IPI中断管理器的存储空间包括多个vCPU调度信息区，所述多个vCPU调度信息区与多个vCPU一一对应，所述vCPU调度信息区存储调度对应vCPU的pCPU的标识；
    根据所述目标pCPU的标识从pCPU信息区读取所述目标pCPU对应的中断重映射表项索引，其中，当前IPI中断管理器的存储空间中的pCPU信息区存储多个pCPU标识与中断重映射表项索引的对应关系；以及
    根据各个目标pCPU对应的中断重映射表项索引和所述IPI请求信息携带的vector生成所述MSI请求。
  4. 根据权利要求1至3中任意一项所述的中断处理方法，其中，当IPI请求信息区写入IPI请求信息时，根据所述IPI请求信息生成预定中断请求之前，所述中断处理方法还包括：
    根据所述目标vCPU的标识确定所述目标vCPU的调度状态；以及
    当所述目标vCPU被调度时，执行根据所述IPI请求信息生成预定中断请求的步骤。
  5. 根据权利要求4所述的中断处理方法，其中，当所述目标vCPU未被调度时，所述中断处理方法包括：
    将发起IPI请求的vCPU的标识信息写入当前IPI中断管理器的存储空间中的待发送IPI请求vCPU集数据区；
    将发起IPI请求的vCPU所属虚拟机的标识信息写入当前IPI中断管理器的存储空间中的待发送IPI请求VM集数据区；以及
    根据预设虚拟机管理器VMM通知中断的vector发送VMM通知中断。
  6. 根据权利要求5所述的中断处理方法，其中，将发起IPI请求的vCPU的标识信息写入当前IPI中断管理器的存储空间中的待发送IPI请求vCPU集数据区包括：
    以发起IPI请求的vCPU的标识为偏移，设置所述待发送IPI请求vCPU集数据区的对应比特位，其中，所述待发送IPI请求vCPU集数据区的比特位与vCPU一一对应，所述待发送IPI请求vCPU集数据区的比特位置位表示对应的vCPU有待发送的IPI请求；
    将发起IPI请求的vCPU所属虚拟机的标识信息写入当前IPI中断管理器的存储空间中的待发送IPI请求VM集数据区包括：
    根据发起IPI请求的vCPU所属虚拟机的标识设置所述待发送 IPI请求VM集数据区的对应比特位，其中，所述待发送IPI请求VM集数据区的比特位与虚拟机一一对应，所述待发送IPI请求VM集数据区的比特位置位表示对应的虚拟机中的vCPU有待发送的IPI请求。
  7. 根据权利要求1至3中任意一项所述的中断处理方法，还包括：
    响应于申请IPI请求信息区的消息，为目标虚拟机分配IPI请求信息区；以及
    返回分配给所述目标虚拟机的IPI请求信息区的索引号。
  8. 一种中断处理方法，包括：
    当vCPU发起IPI请求时，将IPI请求信息写入发起IPI请求的vCPU所属虚拟机对应的IPI中断管理器的存储空间中的IPI请求信息区，所述IPI请求信息携带至少一个目标vCPU的标识，其中，所述IPI中断管理器的存储空间包括至少一个所述IPI请求信息区，所述IPI请求信息区的物理地址通过MMIO映射到对应的虚拟机；以及
    当目标vCPU接收到预定中断请求时，调用IPI处理操作处理所述预定中断请求。
  9. 根据权利要求8所述的中断处理方法，其中，将IPI请求信息写入发起IPI请求的vCPU所属虚拟机对应的IPI中断管理器的存储空间中的IPI请求信息区包括：
    将IPI请求信息写入发起IPI请求的vCPU对应的IPI请求信息内存块，其中，每一个虚拟机对应的所述IPI请求信息区包括多个IPI请求信息内存块，所述IPI请求信息内存块与虚拟机中的vCPU一一对应。
  10. 根据权利要求8或9所述的中断处理方法，其中，将IPI请求信息写入发起IPI请求的vCPU所属虚拟机对应的IPI中断管理器的存储空间中的IPI请求信息区之前，所述中断处理方法还包括：
    向所述IPI中断管理器发送申请IPI请求信息区的消息；
    创建目标虚拟机，所述目标虚拟机的标识为所述IPI中断管理器返回的分配给所述目标虚拟机的IPI请求信息区的索引号；以及
    通过MMIO将分配给所述目标虚拟机的IPI请求信息区映射到所述目标虚拟机。
  11. 根据权利要求10所述的中断处理方法，其中，通过MMIO将分配给所述目标虚拟机的IPI请求信息区映射到所述目标虚拟机包括：
    根据接收到的分配给所述目标虚拟机的IPI请求信息区的索引号和所述IPI中断管理器的存储空间物理首地址，确定分配给所述目标虚拟机的IPI请求信息区的物理首地址；
    创建虚拟外设组件互连标准PCI设备，所述虚拟PCI设备的基地址寄存器BAR存放分配给所述目标虚拟机的IPI请求信息区的物理首地址；以及
    创建虚拟PCI设备驱动。
  12. 根据权利要求8或9所述的中断处理方法，还包括：
    为各个物理中央处理器pCPU分配中断重映射表项IRTE；
    为所述IPI中断管理器配置Posted-Interrupt属性；以及
    将pCPU的标识和所述pCPU对应的IRTE索引写入所述IPI中断管理器的存储空间中的pCPU信息区。
  13. 根据权利要求8或9所述的中断处理方法，还包括：
    当调度vCPU时，将调度所述vCPU的pCPU的标识写入被调度的vCPU对应的vCPU调度信息区，其中，所述IPI中断管理器的存储空间包括多个vCPU调度信息区，所述多个vCPU调度信息区与多个vCPU一一对应。
  14. 根据权利要求8所述的中断处理方法，还包括：
    响应于所述IPI中断管理器发送的VMM通知中断，读取所述IPI中断管理器的存储空间中的待发送IPI请求VM集数据区，确定发起IPI请求的vCPU所属虚拟机的标识；
    读取所述IPI中断管理器的存储空间中的待发送IPI请求vCPU集数据区，确定发起IPI请求的vCPU的标识；
    根据发起IPI请求的vCPU所属虚拟机的标识和发起IPI请求的vCPU的标识，读取发起IPI请求的vCPU对应的IPI请求信息内存块，获取IPI请求信息；以及
    根据获取的IPI请求信息发送IPI请求。
  15. 一种中断管理器，包括：
    一个或多个处理器；以及
    存储装置，其上存储有一个或多个计算机程序，当所述一个或多个计算机程序被所述一个或多个处理器执行时，使得所述一个或多个处理器实现根据权利要求1至7中任意一项所述的中断处理方法。
  16. 一种电子设备，包括：
    一个或多个处理器；
    存储装置，其上存储有一个或多个计算机程序，当所述一个或多个计算机程序被所述一个或多个处理器执行时，使得所述一个或多个处理器实现根据权利要求1至7中任意一项所述的中断处理方法、和/或权利要求8至14中任意一项所述的中断处理方法；以及
    一个或多个I/O接口，连接在所述处理器与所述存储器之间，配置为实现所述处理器与所述存储器的信息交互。
  17. 一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现根据权利要求1至7中任意一项所述的中断处理方法、和/或权利要求8至14中任意一项所述的中断处理方法。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116521324A (zh) * 2023-06-30 2023-08-01 深圳中安辰鸿技术有限公司 中断虚拟化处理方法、装置及电子设备
WO2023174220A1 (zh) * 2022-03-17 2023-09-21 北京有竹居网络技术有限公司 数据处理方法、装置、可读介质以及计算设备

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112783600A (zh) * 2020-07-01 2021-05-11 中兴通讯股份有限公司 中断处理方法、中断管理器、电子设备、计算机可读介质
CN113391881B (zh) * 2021-06-28 2023-07-14 元心信息科技集团有限公司 中断的管理方法、装置、电子设备及计算机存储介质
CN114003363B (zh) 2021-11-01 2022-07-22 支付宝(杭州)信息技术有限公司 线程间中断信号发送方法及装置
CN114265800B (zh) * 2022-03-02 2022-06-07 山东云海国创云计算装备产业创新中心有限公司 中断消息处理方法、装置、电子设备及可读存储介质
CN116954830B (zh) * 2023-09-18 2023-12-26 麒麟软件有限公司 jailhouse下使虚拟机实现msi/x中断的方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090100250A1 (en) * 2004-04-21 2009-04-16 Xiaoxin Chen Switching between multiple software entities using different operating modes of a processor
CN103559087A (zh) * 2013-10-31 2014-02-05 华为技术有限公司 一种虚拟处理器之间的中断的实现方法、相关装置和系统
CN110609730A (zh) * 2018-06-14 2019-12-24 阿里巴巴集团控股有限公司 一种实现虚拟处理器间中断透传的方法及设备
CN112783600A (zh) * 2020-07-01 2021-05-11 中兴通讯股份有限公司 中断处理方法、中断管理器、电子设备、计算机可读介质

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100527098C (zh) * 2007-11-27 2009-08-12 北京大学 一种虚拟机管理器的动态内存映射方法
US10049064B2 (en) * 2015-01-29 2018-08-14 Red Hat Israel, Ltd. Transmitting inter-processor interrupt messages by privileged virtual machine functions
CN109144679B (zh) * 2017-06-27 2022-03-29 华为技术有限公司 中断请求的处理方法、装置及虚拟化设备
CN111158863B (zh) * 2019-12-31 2024-03-08 龙芯中科技术股份有限公司 中断控制器的处理方法、装置及电子设备

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090100250A1 (en) * 2004-04-21 2009-04-16 Xiaoxin Chen Switching between multiple software entities using different operating modes of a processor
CN103559087A (zh) * 2013-10-31 2014-02-05 华为技术有限公司 一种虚拟处理器之间的中断的实现方法、相关装置和系统
CN110609730A (zh) * 2018-06-14 2019-12-24 阿里巴巴集团控股有限公司 一种实现虚拟处理器间中断透传的方法及设备
CN112783600A (zh) * 2020-07-01 2021-05-11 中兴通讯股份有限公司 中断处理方法、中断管理器、电子设备、计算机可读介质

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023174220A1 (zh) * 2022-03-17 2023-09-21 北京有竹居网络技术有限公司 数据处理方法、装置、可读介质以及计算设备
CN116521324A (zh) * 2023-06-30 2023-08-01 深圳中安辰鸿技术有限公司 中断虚拟化处理方法、装置及电子设备
CN116521324B (zh) * 2023-06-30 2024-04-12 深圳中安辰鸿技术有限公司 中断虚拟化处理方法、装置及电子设备

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