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WO2022087817A1 - 栅极驱动单元、栅极驱动电路、栅极驱动方法和显示装置 - Google Patents

栅极驱动单元、栅极驱动电路、栅极驱动方法和显示装置 Download PDF

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Publication number
WO2022087817A1
WO2022087817A1 PCT/CN2020/123954 CN2020123954W WO2022087817A1 WO 2022087817 A1 WO2022087817 A1 WO 2022087817A1 CN 2020123954 W CN2020123954 W CN 2020123954W WO 2022087817 A1 WO2022087817 A1 WO 2022087817A1
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WIPO (PCT)
Prior art keywords
node
electrically connected
control
terminal
clock signal
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Application number
PCT/CN2020/123954
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English (en)
French (fr)
Inventor
郑灿
冯宇
商广良
刘利宾
史世明
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/426,949 priority Critical patent/US11574597B2/en
Priority to CN202080002486.6A priority patent/CN114930437A/zh
Priority to PCT/CN2020/123954 priority patent/WO2022087817A1/zh
Publication of WO2022087817A1 publication Critical patent/WO2022087817A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a gate driving unit, a gate driving circuit, a gate driving method and a display device.
  • Oxide TFT thin film transistor
  • LTPS low temperature polysilicon
  • OLED Organic Light Emitting Diode
  • the gate drive circuit that provides the control signal has become one of the key technologies of LTPO (Low Temperature Polycrystalline Oxide, low temperature polycrystalline oxide) technology.
  • an embodiment of the present disclosure provides a gate driving unit, including a first output circuit and a second output circuit; the second output circuit includes a first output sub-circuit;
  • the first output circuit is electrically connected to the first node, the second node and the first gate drive signal output terminal respectively, and is used for controlling the potential of the first node and the potential of the second node under the control of the potential of the first node and the potential of the second node.
  • the first gate driving signal output terminal outputs a first gate driving signal
  • the first output sub-circuit is electrically connected to the first node, the second gate driving signal output terminal and the first clock signal terminal, respectively, and is used for controlling the first node under the control of the potential of the first node.
  • the two gate driving signal output terminals are communicated with the first clock signal terminal.
  • the first output sub-circuit includes a first output transistor
  • the control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the first clock signal terminal, and the second electrode of the first output transistor is electrically connected to the first clock signal terminal.
  • the second gate driving signal output terminal is electrically connected.
  • the second output circuit further includes a second output sub-circuit and a third node control sub-circuit;
  • the second output sub-circuit is respectively electrically connected to the third node, the second gate driving signal output terminal and the first voltage terminal, and is used for controlling the first voltage terminal under the control of the potential of the third node.
  • a first voltage signal provided by a voltage terminal is written into the second gate driving signal output terminal;
  • the third node control sub-circuit is respectively electrically connected to the first gate driving signal output terminal, the second clock signal terminal, the third clock signal terminal, the first voltage terminal and the second voltage terminal, and is used for the Under the control of the first gate driving signal output by the first gate driving signal output terminal, the second clock signal provided by the second clock signal terminal, and the third clock signal provided by the third clock signal terminal, the control system is controlled. the potential of the third node.
  • the second output sub-circuit includes a second output transistor
  • the control electrode of the second output transistor is electrically connected to the third node, the first electrode of the second output transistor is electrically connected to the output terminal of the second gate driving signal, and the first electrode of the second output transistor is electrically connected to the output terminal of the second gate driving signal.
  • the diode is electrically connected to the first voltage terminal.
  • the third node control sub-circuit is specifically configured to control the writing of the second voltage signal provided by the second voltage terminal into the third node under the control of the first gate driving signal, Under the control of the second clock signal, the first voltage signal is controlled to be written into the third node, and used to control the potential of the third node according to the third clock signal.
  • the third node control sub-circuit includes a first control transistor, a second control transistor and a first control capacitor, wherein,
  • the control electrode of the first control transistor is electrically connected to the first gate drive signal output terminal, the first electrode of the first control transistor is electrically connected to the second voltage terminal, and the first control transistor is electrically connected to the second voltage terminal.
  • the second pole is electrically connected to the third node;
  • the control electrode of the second control transistor is electrically connected to the second clock signal terminal, the first electrode of the second control transistor is electrically connected to the third node, and the second electrode of the second control transistor is electrically connected to the third node.
  • the first voltage terminal is electrically connected;
  • the first end of the first control capacitor is electrically connected to the third node, and the second end of the first control capacitor is electrically connected to the third clock signal end.
  • the third node control sub-circuit includes a third isolated node control unit circuit and a third node control unit circuit, wherein,
  • the third isolation node control unit circuit is respectively connected with the first gate drive signal output terminal, the second voltage terminal, the third isolation node, the second clock signal terminal, the third clock signal terminal and
  • the first voltage terminal is electrically connected for controlling the writing of the second voltage signal into the third isolation node under the control of the first gate driving signal, and under the control of the second clock signal next, controlling to write the first voltage signal into the third isolation node, and for controlling the potential of the third isolation node according to the third clock signal;
  • the third node control unit circuit is respectively electrically connected with the first gate driving signal output terminal, the third isolation node, the second voltage terminal and the third node, and is used for the first gate driving signal output terminal, the third isolation node, the second voltage terminal and the third node Under the control of the gate drive signal, a second voltage signal is written into the third node, and is used to control the relationship between the third node and the third isolation node under the control of the potential of the third isolation node. connected between them and used to maintain the potential of the third node.
  • the third isolated node control unit circuit includes a first control transistor, a second control transistor and a first control capacitor, wherein,
  • the control electrode of the first control transistor is electrically connected to the first gate drive signal output terminal, the first electrode of the first control transistor is electrically connected to the second voltage terminal, and the first control transistor is electrically connected to the second voltage terminal.
  • the second pole is electrically connected to the third isolation node;
  • the control electrode of the second control transistor is electrically connected to the second clock signal terminal, the first electrode of the second control transistor is electrically connected to the third isolation node, and the second electrode of the second control transistor is electrically connected electrically connected to the first voltage terminal;
  • the first end of the first control capacitor is electrically connected to the third isolation node, and the second end of the first control capacitor is electrically connected to the third clock signal end.
  • the third node control unit circuit includes a third control transistor, a fourth control transistor and a first storage capacitor, wherein,
  • the control electrode of the third control transistor is electrically connected to the first gate driving signal terminal, the first electrode of the third control transistor is electrically connected to the second voltage terminal, and the first electrode of the third control transistor is electrically connected to the second voltage terminal.
  • a diode is electrically connected to the third node;
  • control electrode of the fourth control transistor and the first electrode of the fourth control transistor are both electrically connected to the third isolation node, and the second electrode of the fourth control transistor is electrically connected to the third node;
  • the first terminal of the first storage capacitor is electrically connected to the third node, and the second terminal of the first storage capacitor is electrically connected to the first voltage terminal.
  • the first output circuit includes a first node control sub-circuit and an energy storage sub-circuit;
  • the first node control sub-circuit is respectively electrically connected to the third clock signal terminal, the input terminal, the second voltage terminal, the second node and the first node, for providing a third clock signal at the third clock signal terminal Under the control of the input terminal, the input signal provided by the input terminal is written into the first node, and used to write the second voltage signal provided by the second voltage terminal under the control of the potential of the second node. the first node;
  • the first end of the energy storage sub-circuit is electrically connected to the first node
  • the second end of the energy storage sub-circuit is electrically connected to the first gate drive signal output end
  • the energy storage sub-circuit is used for to store electrical energy
  • the first node control sub-circuit includes a fifth control transistor and a sixth control transistor, wherein,
  • the control pole of the fifth control transistor is electrically connected to the third clock signal terminal, the first pole of the fifth control transistor is electrically connected to the input terminal, and the second pole of the fifth control transistor is electrically connected to the input terminal.
  • the first node is electrically connected;
  • the control electrode of the sixth control transistor is electrically connected to the second node, the first electrode of the sixth control transistor is electrically connected to the second voltage terminal, and the second electrode of the sixth control transistor is electrically connected to the second node. the first node is electrically connected;
  • the energy storage sub-circuit includes a second storage capacitor
  • the first end of the second storage capacitor is electrically connected to the first node, and the second end of the second storage capacitor is electrically connected to the first gate driving signal output end.
  • the first node control subcircuit includes a first control unit circuit, a second control unit circuit, a third control unit circuit, a fourth control unit circuit, a fifth control unit circuit, and a sixth control unit circuit, wherein ,
  • the first control unit circuit is electrically connected to the third clock signal terminal, the input terminal and the fourth node respectively, and is used for writing the input signal into the fourth node under the control of the third clock signal node;
  • the second control unit circuit is respectively electrically connected to the third clock signal terminal, the fourth node and the first node, and is used for controlling the fourth node under the control of the third clock signal communicating with the first node;
  • the third control unit circuit is respectively electrically connected to the first gate driving signal output terminal, the fourth clock signal terminal and the fourth node, and is used for the first gate driving signal output terminal to provide the first gate driving signal output terminal. Under the control of a gate driving signal, the fourth clock signal provided by the fourth clock signal terminal is written into the fourth node;
  • the fourth control unit circuit is respectively electrically connected to the second node, the second voltage terminal and the fifth node, and is used for applying the second voltage provided by the second voltage terminal under the control of the potential of the second node writing a signal to the fifth node;
  • the fifth control unit circuit is electrically connected to the second node, the fifth node and the first node respectively, and is used for controlling the fifth node and the first node under the control of the potential of the second node. communication between the first nodes;
  • the sixth control unit circuit is respectively electrically connected to the first node, the fifth node and the first voltage terminal, and is used for, under the control of the potential of the first node, the first voltage terminal provided by the first voltage terminal. A voltage signal is written into the fifth node.
  • the first control unit circuit includes a fifth control transistor
  • the second control unit circuit includes a seventh control transistor
  • the third control unit circuit includes an eighth control transistor
  • the fourth control unit circuit including a sixth control transistor
  • the fifth control unit circuit includes a ninth control transistor
  • the sixth control unit circuit includes a tenth control transistor
  • the control pole of the fifth control transistor is electrically connected to the third clock signal terminal, the first pole of the fifth control transistor is electrically connected to the input terminal, and the second pole of the fifth control transistor is electrically connected to the input terminal.
  • the fourth node is electrically connected;
  • the control electrode of the seventh control transistor is electrically connected to the third clock signal terminal, the first electrode of the seventh control transistor is electrically connected to the fourth node, and the second electrode of the seventh control transistor is electrically connected to the fourth node. the first node is electrically connected;
  • the control electrode of the eighth control transistor is electrically connected to the output terminal of the first gate driving signal, the first electrode of the eighth control transistor is electrically connected to the fourth clock signal terminal, and the first electrode of the eighth control transistor is electrically connected to the fourth clock signal terminal.
  • a diode is electrically connected to the fourth node;
  • the control electrode of the sixth control transistor is electrically connected to the second node, the first electrode of the sixth control transistor is electrically connected to the second voltage terminal, and the second electrode of the sixth control transistor is electrically connected to the second node.
  • the fifth node is electrically connected;
  • the control electrode of the ninth control transistor is electrically connected to the second node, the first electrode of the ninth control transistor is electrically connected to the fifth node, and the second electrode of the ninth control transistor is electrically connected to the fifth node. the first node is electrically connected;
  • the control electrode of the tenth control transistor is electrically connected to the first node, the first electrode of the tenth control transistor is electrically connected to the fifth node, and the second electrode of the tenth control transistor is electrically connected to the fifth node.
  • the first voltage terminal is electrically connected.
  • the first output circuit further includes a second node control sub-circuit and a third output sub-circuit;
  • the second node control sub-circuit is respectively electrically connected to the second node, the input terminal, the second clock signal terminal, the first voltage terminal and the second voltage terminal, and is used to control the first voltage terminal under the control of the input signal.
  • the second voltage signal provided by the two voltage terminals is written into the second node, and the first voltage signal provided by the first voltage terminal is written under the control of the second clock signal provided by the second clock signal terminal.
  • the second node for maintaining the potential of the second node;
  • the third output sub-circuit is respectively electrically connected to the second node, the second voltage terminal, the first gate driving signal output terminal, the first node and the fourth clock signal terminal, and is used for the Under the control of the potential of the first node, the fourth clock signal provided by the fourth clock signal terminal is written into the first gate driving signal output terminal, and under the control of the potential of the second node, the fourth clock signal is written into the first gate driving signal output terminal. Two voltage signals are written into the first gate driving signal output terminal.
  • the second node control sub-circuit includes a seventh control transistor, an eighth control transistor and a second control capacitor;
  • the control electrode of the seventh control transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh control transistor is electrically connected to the second node, and the second electrode of the seventh control transistor is electrically connected to the first node
  • the voltage terminal is electrically connected;
  • the control electrode of the eighth control transistor is electrically connected to the input terminal, the first electrode of the eighth control transistor is electrically connected to the second voltage terminal, and the second electrode of the eighth control transistor is electrically connected to the second voltage terminal.
  • the second node is electrically connected;
  • the first terminal of the second control capacitor is electrically connected to the second node, and the second terminal of the second control capacitor is electrically connected to the second voltage terminal.
  • the third output sub-circuit includes a third output transistor and a fourth output transistor, wherein,
  • the control electrode of the third output transistor is electrically connected to the second node, the first electrode of the third output transistor is electrically connected to the second voltage terminal, and the second electrode of the third output transistor is electrically connected to the second voltage terminal.
  • the first gate driving signal output terminal is electrically connected;
  • the control electrode of the fourth output transistor is electrically connected to the first node, the first electrode of the fourth output transistor is electrically connected to the output terminal of the first gate driving signal, and the first electrode of the fourth output transistor is electrically connected to the first gate driving signal output terminal.
  • the diode is electrically connected to the fourth clock signal terminal.
  • an embodiment of the present disclosure further provides a gate driving circuit, including the above gate driving unit.
  • the gate driving circuit further includes a first clock signal input terminal, a second clock signal input terminal, a third clock signal input terminal, a first first clock signal terminal, a first clock signal input terminal, and a first clock signal input terminal. two first clock signal terminals and a third first clock signal terminal;
  • the input terminal of the gate driving unit is electrically connected to the first gate driving signal output terminal of the adjacent upper-stage gate driving unit;
  • the third clock signal terminal of the 3n-2 stage gate driving unit is electrically connected to the first clock signal input terminal, and the fourth clock signal terminal of the 3n-2 stage gate driving unit is electrically connected to the second clock signal input terminal,
  • the second clock signal terminal of the 3n-2 stage gate driving unit is electrically connected to the third clock signal input terminal;
  • the first clock signal terminal of the 3n-2 gate driving unit is electrically connected to the second first clock signal terminal ;
  • the third clock signal terminal of the 3n-1 stage gate driving unit is electrically connected to the second clock signal input terminal
  • the fourth clock signal terminal of the 3n-1 stage gate driving unit is electrically connected to the third clock signal input terminal
  • the second clock signal terminal of the 3n-1 stage gate driving unit is electrically connected to the first clock signal input terminal
  • the first clock signal terminal of the 3n-1 gate driving unit is electrically connected to the third first clock signal terminal ;
  • the third clock signal terminal of the 3n-stage gate driving unit is electrically connected to the third clock signal input terminal
  • the fourth clock signal terminal of the 3n-stage gate driving unit is electrically connected to the first clock signal input terminal
  • the 3n-stage gate driving unit is electrically connected to the first clock signal input terminal.
  • the second clock signal terminal of the gate driving unit is electrically connected to the second clock signal input terminal
  • the first clock signal terminal of the 3nth gate driving unit is electrically connected to the first first clock signal terminal;
  • n is a positive integer.
  • an embodiment of the present disclosure further provides a gate driving method, which is applied to the above gate driving circuit, and the gate driving method includes:
  • the first output circuit controls the first gate drive signal output terminal to output the first gate drive signal under the control of the potential of the first node and the potential of the second node;
  • the first output sub-circuit controls the communication between the second gate driving signal output terminal and the first clock signal terminal under the control of the potential of the first node.
  • an embodiment of the present disclosure further provides a display device including the above gate driving circuit.
  • FIG. 1 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure
  • 3A is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure.
  • 3B is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure.
  • FIG. 4 is a structural diagram of a gate driving unit according to at least one embodiment of the present disclosure.
  • FIG. 5 is a structural diagram of at least one embodiment of the first output circuit in the gate driving unit according to the present disclosure
  • FIG. 6 is a structural diagram of at least one embodiment of a first output circuit in the gate driving unit according to the present disclosure
  • FIG. 7 is a structural diagram of at least one embodiment of a first output circuit in the gate driving unit according to the present disclosure.
  • FIG. 8 is a circuit diagram of a gate driving unit according to at least one embodiment of the present disclosure.
  • FIG. 9 is an operation timing diagram of at least one embodiment of the gate driving unit shown in FIG. 8 of the present disclosure.
  • FIG. 10 is a structural diagram of a gate driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 11 is an operation timing diagram of the gate driving circuit according to at least one embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors, field effect transistors, or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • control electrode when the transistor is a triode, the control electrode may be the base electrode, the first electrode may be the collector electrode, and the second electrode may be the emitter electrode; or the control electrode may be the base electrode electrode, the first electrode can be an emitter electrode, and the second electrode can be a collector electrode.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode;
  • the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the gate driving unit includes a first output circuit 11 and a second output circuit; the second output circuit includes a first output sub-circuit 121 ;
  • the first output circuit 11 is respectively electrically connected to the first node N1, the second node N2 and the first gate driving signal output terminal OUT_P, for the potential of the first node N1 and the voltage of the second node N2. Under the control of the potential, the first gate driving signal output terminal OUT_P is controlled to output the first gate driving signal;
  • the first output sub-circuit 121 is electrically connected to the first node N1, the second gate driving signal output terminal OUT_N and the first clock signal terminal respectively, and is used for, under the control of the potential of the first node N1, controlling the communication between the second gate driving signal output terminal OUT_N and the first clock signal terminal;
  • the first clock signal terminal is used for providing the first clock signal GCKO.
  • the gate driving unit may provide a first gate driving signal and a second gate driving signal, the first gate driving signal is used to control a p-type transistor, and the second gate driving signal
  • the driving signal is used to control the n-type transistor
  • the gate driving unit described in at least one embodiment of the present disclosure may be applicable to an LTPO (Low Temperature Polycrystalline Oxide, low temperature polycrystalline oxide) pixel circuit.
  • LTPO Low Temperature Polycrystalline Oxide, low temperature polycrystalline oxide
  • the first output sub-circuit 121 controls the second gate driving signal output terminal OUT_N and the first clock signal at the potential of the first node N1 connected between the terminals, because the potential of the first node N1 is pulled down by the bootstrap during the output period, the transistors included in the first output sub-circuit 121 can be fully turned on, and there will be no threshold voltage loss, so that the OUT_N
  • the outputted second gate driving signal descends without steps, and the first output sub-circuit 121 is electrically connected to the first clock signal terminal, and the waveform of the first clock signal GCKO in the output stage is the same as the waveform of the gate driving signal output by OUT_N same.
  • an LTPS (low temperature polysilicon) TFT (thin film transistor) device and an Oxide (oxide) TFT device are integrated in an LTPO pixel, wherein the LTPS TFT device is a p-type transistor, and the Oxide TFT device is an n-type transistor transistor.
  • the first output sub-circuit may include a first output transistor
  • the control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the first clock signal terminal, and the second electrode of the first output transistor is electrically connected to the first clock signal terminal.
  • the second gate driving signal output terminal is electrically connected.
  • the first output transistor may be a p-type transistor, but is not limited thereto.
  • the second output circuit further includes a second output sub-circuit 122 and a third node control sub-circuit 123 ;
  • the second output sub-circuit 122 is electrically connected to the third node N3, the second gate driving signal output terminal OUT_N and the first voltage terminal V1 respectively, for controlling the potential of the third node N3 Next, control to write the first voltage signal provided by the first voltage terminal V1 into the second gate driving signal output terminal OUT_N;
  • the third node control sub-circuit 123 is respectively connected to the first gate driving signal output terminal OUT_P, the second clock signal terminal, the third clock signal terminal, the first voltage terminal V1 and the second voltage terminal V2 Electrically connected for the first gate driving signal output from the first gate driving signal output terminal OUT_P, the second clock signal GCK3 provided by the second clock signal terminal, and the third clock signal terminal provided by the third clock signal terminal. Under the control of the third clock signal GCK1, the potential of the third node N3 is controlled.
  • the first voltage terminal V1 may be a low voltage terminal
  • the second voltage terminal V2 may be a high voltage terminal, but not limited thereto.
  • the second output sub-circuit 122 controls OUT_N to output a first voltage signal under the control of the potential of the third node N3; the third The node control sub-circuit 123 controls the potential of N3 under the control of the first gate driving signal, the second clock signal GCK3 and the third clock signal GCK1.
  • the second output sub-circuit includes a second output transistor
  • the control electrode of the second output transistor is electrically connected to the third node, the first electrode of the second output transistor is electrically connected to the output terminal of the second gate driving signal, and the first electrode of the second output transistor is electrically connected to the output terminal of the second gate driving signal.
  • the diode is electrically connected to the first voltage terminal.
  • the third node control sub-circuit 123 is specifically configured to control writing the second voltage signal into the third node N3 under the control of the first gate driving signal , under the control of the second clock signal GCK3, the first voltage signal is controlled to be written into the third node N3, and used to control the potential of the third node N3 according to the third clock signal GCK1.
  • the third node control sub-circuit includes a first control transistor, a second control transistor and a first control capacitor, wherein,
  • the control electrode of the first control transistor is electrically connected to the first gate drive signal output terminal, the first electrode of the first control transistor is electrically connected to the second voltage terminal, and the first control transistor is electrically connected to the second voltage terminal.
  • the second pole is electrically connected to the third node;
  • the control electrode of the second control transistor is electrically connected to the second clock signal terminal, the first electrode of the second control transistor is electrically connected to the third node, and the second electrode of the second control transistor is electrically connected to the third node.
  • the first voltage terminal is electrically connected;
  • the first end of the first control capacitor is electrically connected to the third node, and the second end of the first control capacitor is electrically connected to the third clock signal end.
  • the third node control sub-circuit 123 may include a first control transistor M11 , a second control transistor M12 and a first control transistor M12 .
  • control capacitor C3 where,
  • the gate of the first control transistor M11 is electrically connected to the first gate driving signal output terminal OUT_P, the source of the first control transistor M11 is electrically connected to the high voltage terminal, and the first control transistor M11 is electrically connected to the high voltage terminal.
  • the drain is electrically connected to the third node N3;
  • the gate of the second control transistor M12 is electrically connected to the second clock signal terminal, the source of the second control transistor M12 is electrically connected to the third node N3, and the drain of the second control transistor M12 is electrically connected
  • the pole is electrically connected to the low voltage terminal; the second clock signal terminal is used to provide the second clock signal GCK3;
  • the first end of the first control capacitor C3 is electrically connected to the third node N3, the second end of the first control capacitor C3 is electrically connected to the third clock signal end; the third clock signal end Used to provide the third clock signal GCK1.
  • M11 and M12 are p-type thin film transistors, but not limited thereto.
  • the third node control sub-circuit may include a third isolated node control unit circuit 31 and a third node control unit circuit 32, of which,
  • the third isolation node control unit circuit 31 is respectively connected to the first gate driving signal output terminal OUT_P, the second voltage terminal V2, the third isolation node N03, the second clock signal terminal, the third The clock signal terminal is electrically connected to the first voltage terminal V1, and is used to control the writing of the second voltage signal into the third isolation node N03 under the control of the first gate driving signal provided by OUT_P. Under the control of the second clock signal GCK3, the first voltage signal is controlled to be written into the third isolation node N03, and used to control the potential of the third isolation node N03 according to the third clock signal GCK1;
  • the third node control unit circuit 32 is respectively electrically connected to the first gate driving signal output terminal OUT_P, the third isolation node N03, the second voltage terminal V2 and the third node N3, for Under the control of the first gate driving signal, a second voltage signal is written into the third node N3 and used to control the third node N3 under the control of the potential of the third isolation node N03 It communicates with the third isolation node N03 and is used to maintain the potential of the third node N3.
  • the third isolated node control unit circuit includes a first control transistor, a second control transistor and a first control capacitor, wherein,
  • the control electrode of the first control transistor is electrically connected to the first gate drive signal output terminal, the first electrode of the first control transistor is electrically connected to the second voltage terminal, and the first control transistor is electrically connected to the second voltage terminal.
  • the second pole is electrically connected to the third isolation node;
  • the control electrode of the second control transistor is electrically connected to the second clock signal terminal, the first electrode of the second control transistor is electrically connected to the third isolation node, and the second electrode of the second control transistor is electrically connected electrically connected to the first voltage terminal;
  • the first end of the first control capacitor is electrically connected to the third isolation node, and the second end of the first control capacitor is electrically connected to the third clock signal end.
  • the third node control unit circuit may include a third control transistor, a fourth control transistor, and a first storage capacitor, wherein,
  • the control electrode of the third control transistor is electrically connected to the first gate driving signal terminal, the first electrode of the third control transistor is electrically connected to the second voltage terminal, and the first electrode of the third control transistor is electrically connected to the second voltage terminal.
  • a diode is electrically connected to the third node;
  • control electrode of the fourth control transistor and the first electrode of the fourth control transistor are both electrically connected to the third isolation node, and the second electrode of the fourth control transistor is electrically connected to the third node;
  • the first terminal of the first storage capacitor is electrically connected to the third node, and the second terminal of the first storage capacitor is electrically connected to the first voltage terminal.
  • the third isolated node control unit circuit 31 includes a first control transistor M11, a second control transistor M12 and a first control capacitor C3, wherein,
  • the gate of the first control transistor M11 is electrically connected to the first gate driving signal output terminal OUT_P, the source of the first control transistor M11 is electrically connected to the high voltage terminal, and the first control transistor M11 is electrically connected to the high voltage terminal.
  • the drain is electrically connected to the third isolation node N03; the high voltage terminal is used to provide a high voltage VGH;
  • the gate of the second control transistor M12 is electrically connected to the second clock signal terminal, the source of the second control transistor M12 is electrically connected to the third isolation node N03, and the second control transistor M12 is the drain is electrically connected to the low voltage terminal; the low voltage terminal is used for providing the low voltage VGL; the second clock signal terminal is used for providing the second clock signal GCK3;
  • the first terminal of the first control capacitor C3 is electrically connected to the third isolation node N03, and the second terminal of the first control capacitor C3 is electrically connected to the third clock signal terminal; the third clock signal The terminal is used to provide the third clock signal GCK1;
  • the third node control unit circuit 32 includes a third control transistor M14, a fourth control transistor M13 and a first storage capacitor C4, wherein,
  • the gate of the third control transistor M14 is electrically connected to the first gate driving signal terminal OUT_P, the source of the third control transistor M14 is electrically connected to the high voltage terminal, and the drain of the third control transistor M14 is electrically connected The pole is electrically connected to the third node N3;
  • the gate of the fourth control transistor M13 and the source of the fourth control transistor M13 are both electrically connected to the third isolation node N03, and the drain of the fourth control transistor M13 is electrically connected to the third node N3 electrical connection;
  • the first end of the first storage capacitor C4 is electrically connected to the third node N3, and the second end of the first storage capacitor C3 is electrically connected to the low voltage end;
  • the high voltage terminal is used for providing the high voltage VGH, and the low voltage terminal is used for providing the low voltage VGL.
  • all the transistors are p-type thin film transistors, but not limited thereto.
  • the gate driving unit shown in FIG. 4 of the present disclosure if M13 is not used, since the potential of GCK1 is constantly switched between high voltage and low voltage, the potential of N3 cannot always be kept low enough The potential of the second output sub-circuit cannot fully open the second output transistor included in the second output sub-circuit, resulting in poor low-voltage output effect;
  • While at least one embodiment of the gate driving unit shown in FIG. 4 of the present disclosure adopts M13, when GCK1 increases the potential of N03, M13 is turned off, so that the status of N3 can be maintained at a sufficiently low potential, so that the potential of N3 can be maintained at a low enough potential. Guarantees the effect of low voltage output.
  • the first output circuit may include a first node control sub-circuit 51 and an energy storage sub-circuit 52;
  • the first node control sub-circuit 51 is respectively electrically connected to the third clock signal terminal, the input terminal GSTV, the second voltage terminal V2, the second node N2 and the first node N1, and is used to provide the third clock signal terminal Under the control of the third clock signal GCK1, the input signal provided by the input terminal GSTV is written into the first node N1, and is used to write the second voltage under the control of the potential of the second node N2 The second voltage signal provided by the terminal V2 is written into the first node N1;
  • the first end of the energy storage sub-circuit 52 is electrically connected to the first node N1
  • the second end of the energy storage sub-circuit 52 is electrically connected to the first gate driving signal output terminal OUT_P
  • the storage sub-circuit 52 is electrically connected to the first gate driving signal output terminal OUT_P.
  • the energy subcircuit 52 is used to store electrical energy.
  • the first node control sub-circuit includes a fifth control transistor and a sixth control transistor, wherein,
  • the control pole of the fifth control transistor is electrically connected to the third clock signal terminal, the first pole of the fifth control transistor is electrically connected to the input terminal, and the second pole of the fifth control transistor is electrically connected to the input terminal.
  • the first node is electrically connected;
  • the control electrode of the sixth control transistor is electrically connected to the second node, the first electrode of the sixth control transistor is electrically connected to the second voltage terminal, and the second electrode of the sixth control transistor is electrically connected to the second node. the first node is electrically connected;
  • the energy storage sub-circuit includes a second storage capacitor
  • the first end of the second storage capacitor is electrically connected to the first node, and the second end of the second storage capacitor is electrically connected to the first gate driving signal output end.
  • the first node control subcircuit may include a first control unit circuit, a second control unit circuit, a third control unit circuit, a fourth control unit circuit, a fifth control unit circuit, and a third control unit circuit.
  • the first control unit circuit is electrically connected to the third clock signal terminal, the input terminal and the fourth node respectively, and is used for writing the input signal into the fourth node under the control of the third clock signal node;
  • the second control unit circuit is respectively electrically connected to the third clock signal terminal, the fourth node and the first node, and is used for controlling the fourth node under the control of the third clock signal communicating with the first node;
  • the third control unit circuit is respectively electrically connected to the first gate driving signal output terminal, the fourth clock signal terminal and the fourth node, and is used for the first gate driving signal output terminal to provide the first gate driving signal output terminal. Under the control of a gate driving signal, the fourth clock signal provided by the fourth clock signal terminal is written into the fourth node;
  • the fourth control unit circuit is respectively electrically connected to the second node, the second voltage terminal and the fifth node, and is used for applying the second voltage provided by the second voltage terminal under the control of the potential of the second node writing a signal to the fifth node;
  • the fifth control unit circuit is electrically connected to the second node, the fifth node and the first node respectively, and is used for controlling the fifth node and the first node under the control of the potential of the second node. communication between the first nodes;
  • the sixth control unit circuit is respectively electrically connected to the first node, the fifth node and the first voltage terminal, and is used for providing the first voltage terminal under the control of the potential of the first node The first voltage signal is written into the fifth node.
  • the first node control sub-circuit may include a first control unit circuit, a second control unit circuit, a third control unit circuit, a fourth control unit circuit, a fifth control unit circuit, and a sixth control unit circuit
  • the first control unit circuit is used to write the input signal into the fourth node under the control of the third clock signal
  • the fourth control unit circuit is used to control the potential of the second node
  • the second voltage signal is written into the fifth node
  • the second control unit circuit, the third control unit circuit, the fifth control unit circuit and the sixth control unit circuit are used to prevent leakage current.
  • the first node control sub-circuit 51 includes a first control unit circuit, a second control unit circuit, and a third control unit circuit. unit circuit, fourth control unit circuit, fifth control unit circuit, and sixth control unit circuit, wherein,
  • the first control unit circuit includes a fifth control transistor M1, the second control unit circuit includes a seventh control transistor M2, the third control unit circuit includes an eighth control transistor M10, and the fourth control unit circuit includes The sixth control transistor M6, the fifth control unit circuit includes a ninth control transistor M7, and the sixth control unit circuit includes a tenth control transistor M8, wherein,
  • the gate of M1 is electrically connected to the third clock signal terminal, the source of M1 is electrically connected to the input terminal GSTV, and the drain of M1 is electrically connected to the fourth node N4; the third clock signal terminal provides a third clock signal GCK1;
  • the gate of M2 is electrically connected to the third clock signal terminal, the source of M2 is electrically connected to the fourth node N4, and the drain of M2 is electrically connected to the first node N1;
  • the gate of M10 is electrically connected to the first gate driving signal output terminal OUT_P, the source of M10 is electrically connected to the fourth clock signal terminal, and the drain of M10 is electrically connected to the fourth node N4; the fourth The clock signal terminal is used to provide the fourth clock signal GCK2;
  • the gate of M6 is electrically connected to the second node N2, the source of M6 is electrically connected to the high voltage terminal, and the drain of M6 is electrically connected to the fifth node N5; the high voltage terminal is used to provide a high voltage VGH ;
  • the gate of M7 is electrically connected to the second node N2, the source of M7 is electrically connected to the fifth node N5, and the drain of M7 is electrically connected to the first node N1;
  • the gate of M8 is electrically connected to the first node N1, the source of M8 is electrically connected to the fifth node N5, and the drain of M8 is electrically connected to a low voltage terminal; the low voltage terminal is used to provide a low voltage VGL .
  • all transistors are p-type thin film transistors, but not limited thereto.
  • M1 and M2 constitute a double-gate transistor
  • M6 and M7 constitute a double-gate transistor
  • the leakage current of the double-gate transistor is small
  • M10 is used to control the potential of N4, so that a predetermined time period is used to control the potential of N4.
  • Reduce the drain-source voltage of M1 and the drain-source voltage of M2 to reduce the drain current of M1 and the drain current of M2
  • use M8 to control the potential of N5 to reduce the drain-source voltage of M6 and the drain of M7 in a predetermined period of time source voltage to reduce the leakage current of M6 and the leakage current of M7.
  • the first output circuit further includes a second node control subcircuit and a third output subcircuit
  • the second node control sub-circuit is respectively electrically connected to the second node, the input terminal, the second clock signal terminal, the first voltage terminal and the second voltage terminal, and is used to control the first voltage terminal under the control of the input signal.
  • the second voltage signal provided by the two voltage terminals is written into the second node, and the first voltage signal provided by the first voltage terminal is written under the control of the second clock signal provided by the second clock signal terminal.
  • the second node for maintaining the potential of the second node;
  • the third output sub-circuit is respectively electrically connected to the second node, the second voltage terminal, the first gate driving signal output terminal, the first node and the fourth clock signal terminal, and is used for the Under the control of the potential of the first node, the fourth clock signal provided by the fourth clock signal terminal is written into the first gate driving signal output terminal, and under the control of the potential of the second node, the fourth clock signal is written into the first gate driving signal output terminal. Two voltage signals are written into the first gate driving signal output terminal.
  • the first output circuit further includes a second node control subcircuit 53 and a third output subcircuit 54 ;
  • the second node control sub-circuit 53 is respectively electrically connected to the second node N2, the input terminal GSTV, the second clock signal terminal, the first voltage terminal V1 and the second voltage terminal V2, and is used for the input signal provided by the GSTV Under the control of the second voltage terminal V2, the second voltage signal provided by the second voltage terminal V2 is written into the second node N2, and under the control of the second clock signal GCK3 provided by the second clock signal terminal, the first voltage The first voltage signal provided by the terminal V1 is written into the second node N2 and used to maintain the potential of the second node N2;
  • the third output sub-circuit 54 is electrically connected to the second node N2, the second voltage terminal V2, the first gate driving signal output terminal OUT_P, the first node N1 and the fourth clock signal terminal, respectively, Under the control of the potential of the first node N1, the fourth clock signal GCK2 provided by the fourth clock signal terminal is written into the first gate driving signal output terminal OUT_P, at the second node N2 Under the control of the potential, the second voltage signal is written into the first gate driving signal output terminal OUT_P.
  • the second node control sub-circuit 53 When at least one embodiment of the gate driving unit shown in FIG. 7 is in operation, the second node control sub-circuit 53 writes the second voltage signal into N2 under the control of the input signal, and when the second clock signal GCK3 Under the control of the potential of N1, the first voltage signal is written into N2, and the potential of N2 is maintained; under the control of the potential of N1, the third output sub-circuit controls OUT_P to output GCK2, and under the control of the potential of N2, it controls OUT_P to output the second voltage signal.
  • the second node control sub-circuit includes a seventh control transistor, an eighth control transistor and a second control capacitor;
  • the control electrode of the seventh control transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh control transistor is electrically connected to the second node, and the second electrode of the seventh control transistor is electrically connected to the first node
  • the voltage terminal is electrically connected;
  • the control electrode of the eighth control transistor is electrically connected to the input terminal, the first electrode of the eighth control transistor is electrically connected to the second voltage terminal, and the second electrode of the eighth control transistor is electrically connected to the second voltage terminal.
  • the second node is electrically connected;
  • the first terminal of the second control capacitor is electrically connected to the second node, and the second terminal of the second control capacitor is electrically connected to the second voltage terminal.
  • the third output sub-circuit includes a third output transistor and a fourth output transistor, wherein,
  • the control electrode of the third output transistor is electrically connected to the second node, the first electrode of the third output transistor is electrically connected to the second voltage terminal, and the second electrode of the third output transistor is electrically connected to the second voltage terminal.
  • the first gate driving signal output terminal is electrically connected;
  • the control electrode of the fourth output transistor is electrically connected to the first node, the first electrode of the fourth output transistor is electrically connected to the output terminal of the first gate driving signal, and the first electrode of the fourth output transistor is electrically connected to the first gate driving signal output terminal.
  • the diode is electrically connected to the fourth clock signal terminal.
  • the first output sub-circuit 121 includes a first output transistor M16 ;
  • the second output sub-circuit includes a second output transistor M16 .
  • the first output circuit includes a first node control sub-circuit 51, an energy storage sub-circuit 52, a second node control sub-circuit 53 and a third output sub-circuit 54;
  • the gate of M16 is electrically connected to the first node N1, the source of M16 is electrically connected to the first clock signal terminal, and the drain of M16 is electrically connected to the second gate driving signal output terminal OUT_N; the The first clock signal terminal is used for providing the first clock signal GCKO;
  • the gate of M15 is electrically connected to the third node N3, the source of M15 is electrically connected to the second gate driving signal output terminal OUT_N, and the drain of M15 is electrically connected to the low voltage terminal; To provide low voltage VGL;
  • the first node control sub-circuit 51 includes a first control unit circuit, a second control unit circuit, a third control unit circuit, a fourth control unit circuit, a fifth control unit circuit, and a sixth control unit circuit, wherein,
  • the first control unit circuit includes a fifth control transistor M1, the second control unit circuit includes a seventh control transistor M2, the third control unit circuit includes an eighth control transistor M10, and the fourth control unit circuit includes The sixth control transistor M6, the fifth control unit circuit includes a ninth control transistor M7, and the sixth control unit circuit includes a tenth control transistor M8, wherein,
  • the gate of M1 is electrically connected to the third clock signal terminal, the source of M1 is electrically connected to the input terminal GSTV, and the drain of M1 is electrically connected to the fourth node N4; the third clock signal terminal provides a third clock signal GCK1;
  • the gate of M2 is electrically connected to the third clock signal terminal, the source of M2 is electrically connected to the fourth node N4, and the drain of M2 is electrically connected to the first node N1;
  • the gate of M10 is electrically connected to the first gate driving signal output terminal OUT_P, the source of M10 is electrically connected to the fourth clock signal terminal, and the drain of M10 is electrically connected to the fourth node N4; the fourth The clock signal terminal is used to provide the fourth clock signal terminal GCK2;
  • the gate of M6 is electrically connected to the second node N2, the source of M6 is electrically connected to the high voltage terminal, and the drain of M6 is electrically connected to the fifth node N5; the high voltage terminal is used to provide a high voltage VGH ;
  • the gate of M7 is electrically connected to the second node N2, the source of M7 is electrically connected to the fifth node N5, and the drain of M7 is electrically connected to the first node N1;
  • the gate of M8 is electrically connected to the first node N1, the source of M8 is electrically connected to the fifth node N5, and the drain of M8 is electrically connected to a low voltage terminal; the low voltage terminal is used to provide a low voltage VGL ;
  • the energy storage sub-circuit 52 includes a second storage capacitor C1;
  • the first end of C1 is electrically connected to the first node N1, and the second end of C1 is electrically connected to OUT_P;
  • the second node control sub-circuit 53 includes a seventh control transistor M5, an eighth control transistor M9 and a second control capacitor C2;
  • the gate of M5 is electrically connected to the second clock signal terminal, the source of M5 is electrically connected to the second node N2, and the drain of M5 is electrically connected to the low voltage terminal; the low voltage terminal is used to provide the low voltage VGL;
  • the gate of M9 is electrically connected to the input terminal GSTV, the source of M9 is electrically connected to the high-voltage terminal, and the drain of M9 is electrically connected to the second node N2; the high-voltage terminal is used to provide a high voltage VGH;
  • the first end of the second control capacitor C2 is electrically connected to the second node N2, and the second end of the second control capacitor C2 is electrically connected to the high voltage end;
  • the third output sub-circuit 54 includes a third output transistor M4 and a fourth output transistor M3, wherein,
  • the gate of the third output transistor M4 is electrically connected to the second node N2, the source of the third output transistor M4 is electrically connected to the high voltage terminal, and the drain of the third output transistor M4 is electrically connected to the high voltage terminal.
  • the first gate driving signal output terminal OUT_P is electrically connected;
  • the gate of the fourth output transistor M3 is electrically connected to the first node N1, the source of the fourth output transistor M3 is electrically connected to the first gate driving signal output terminal OUT_P, and the fourth output transistor M3 is electrically connected to the first node N1.
  • the drain of the transistor M3 is electrically connected to the fourth clock signal terminal; the fourth clock signal terminal is used to provide the fourth clock signal GCK2.
  • all the transistors are p-type thin film transistors, but the order is not limited.
  • the size of M1 and M2 are the same, and M1 and M2 are adjacent on the layout, so the threshold voltage of M1 and the threshold voltage of M2 may be the same, but Not limited to this.
  • GSTV provides low voltage
  • GCK1 is low voltage
  • GCK2 is high voltage
  • M1 and M2 are turned on
  • the potential of N1 is pulled to low potential VGL+Vth
  • M3 is turned on
  • OUT_P outputs high voltage
  • both ends of C1 store The voltage is VGL+Vth-VGH; at the same time, M9 is turned on, the potential of N2 is high, and M4 is turned off; among them, Vth is the threshold voltage of M1;
  • GCK2 jumps from a low voltage to a high voltage, because the potential of N1 is still lower than the potential of GCK2, therefore, M3 is turned on, OUTP outputs GCK2, and the OUT_P is realized. Low pulse output;
  • the low potential of N1 turns on M16, and OUT_N outputs GCKO. Because the high pulse width of GCKO is smaller than the low pulse width of GCK2, the pulses of GCKO can all be transmitted to OUT_N, including rising and falling. Part; the low potential of OUT_P turns on M11 and M14, stabilizes the potential of N3 and N03 at a high potential, and turns off M15, which avoids the conflict in the output logic of OUT_N;
  • GCK3 is at a low voltage
  • M5 is turned on
  • the potential of N2 is pulled down to a low potential
  • M4 is turned on
  • OUT_P outputs VGH
  • the low potential of N2 turns on M6 and M7
  • the potential of N1 is pulled high
  • M3 is turned off
  • M12 is turned on
  • the potential of N03 is low.
  • GCK1 is a high voltage
  • the storage potential of C3 is VGL+Vth12-VGH at this time; among them, Vth12 is the threshold voltage of M12;
  • GCK3 In the holding phase S4, GCK3 periodically pulls the potential of N2 to VGL to ensure that M4 is turned on, so that OUT_P can output VGH stably, GCK3 periodically pulls down the power of N03 and the potential of N3, and stores VGL+Vth12-VGH in C3 , At the same time, GCK1 periodically jumps to a low voltage, and the potential of N03 and N3 are pulled to a lower potential through C3 to ensure that M15 is fully turned on, and VGL is output to OUT_N.
  • the duty cycle of GCK1, the duty cycle of GCK2 and the duty cycle of GCK3 can be the same; GCK2 is delayed by a predetermined time from GCK1, and GCK3 is delayed by a predetermined time from GCK2, so that GCK1, GCK2 and GCK3 are not simultaneously Low voltage, but not limited thereto.
  • the duty cycle of GCK1, the duty cycle of GCK2, and the duty cycle of GCK3 may be slightly less than 1/3, or the duty cycle of GCK1, the duty cycle of GCK2, and the duty cycle of GCK3
  • the empty ratio can also be equal to 1/3; but it is not limited thereto.
  • the gate driving circuit includes the above-mentioned gate driving unit.
  • the gate driving circuit further includes a first clock signal input terminal, a second clock signal input terminal, a third clock signal input terminal, a first first clock signal terminal, and a second first clock signal input terminal. a clock signal terminal and a third first clock signal terminal;
  • the input terminal of the gate driving unit is electrically connected to the first gate driving signal output terminal of the adjacent upper-stage gate driving unit;
  • the third clock signal terminal of the 3n-2 stage gate driving unit is electrically connected to the first clock signal input terminal, and the fourth clock signal terminal of the 3n-2 stage gate driving unit is electrically connected to the second clock signal input terminal,
  • the second clock signal terminal of the 3n-2 stage gate driving unit is electrically connected to the third clock signal input terminal;
  • the first clock signal terminal of the 3n-2 gate driving unit is electrically connected to the second first clock signal terminal ;
  • the third clock signal terminal of the 3n-1 stage gate driving unit is electrically connected to the second clock signal input terminal
  • the fourth clock signal terminal of the 3n-1 stage gate driving unit is electrically connected to the third clock signal input terminal
  • the second clock signal terminal of the 3n-1 stage gate driving unit is electrically connected to the first clock signal input terminal
  • the first clock signal terminal of the 3n-1 gate driving unit is electrically connected to the third first clock signal terminal ;
  • the third clock signal terminal of the 3n-stage gate driving unit is electrically connected to the third clock signal input terminal
  • the fourth clock signal terminal of the 3n-stage gate driving unit is electrically connected to the first clock signal input terminal
  • the 3n-stage gate driving unit is electrically connected to the first clock signal input terminal.
  • the second clock signal terminal of the gate driving unit is electrically connected to the second clock signal input terminal
  • the first clock signal terminal of the 3nth gate driving unit is electrically connected to the first first clock signal terminal;
  • n is a positive integer.
  • the first-stage gate driving unit included in the gate driving circuit according to at least one embodiment of the present disclosure is labeled X1
  • the second-stage gate driving unit included in the gate driving circuit is labeled X2
  • the first stage gate driving unit, labeled X3 is the third stage gate driving unit included in the gate drive circuit according to at least one embodiment of the present disclosure
  • the fourth stage gate driving unit included in the gate drive circuit labeled X4
  • the gate driving unit of the first stage, marked X5 is the fifth stage gate driving unit included in the gate driving circuit according to at least one embodiment of the present disclosure
  • the gate driving unit marked X6 is the sixth stage included in the gate driving circuit.
  • Labeled STV is the starting end; labelled OUT_P(1) is the first gate drive signal output end of X1, labelled OUT_N(1) is the second gate drive signal output end of X1; labelled OUT_P( 2) is the first gate drive signal output end of X2, the second gate drive signal output end of X2 is labeled OUT_N(2); the first gate drive signal output end of X3 is labeled OUT_P(3) Output terminal, the second gate drive signal output terminal of X3 marked as OUT_N(3); the first gate drive signal output terminal of X4 marked as OUT_P(4), X4 marked as OUT_N(4)
  • the second gate drive signal output end of X5; the first gate drive signal output end of X5 is labeled OUT_P(5), and the second gate drive signal output end of X5 is labeled OUT_N(5);
  • OUT_P(6) is the first gate drive signal output end of X6, and the label OUT_N(6) is the second gate drive signal output end
  • the one labeled CK1 is the first clock signal input end
  • the one labeled CK2 is the second clock signal input end
  • the one labeled CK3 is the third clock signal input end
  • the one labeled CKO1 is the first first clock signal terminal, the one labeled CKO2 is the second first clock signal terminal, and the one labeled CKO3 is the third first clock signal terminal;
  • the third clock signal terminal of X1 is electrically connected to CK1, the fourth clock signal terminal of X1 is electrically connected to CK2, the second clock signal terminal of X1 is electrically connected to CK3, and the first clock signal terminal of X1 is electrically connected to CKO2;
  • the third clock signal terminal of X2 is electrically connected to CK2, the fourth clock signal terminal of X2 is electrically connected to CK3, the second clock signal terminal of X2 is electrically connected to CK1, and the first clock signal terminal of X1 is electrically connected to CKO3;
  • the third clock signal terminal of X3 is electrically connected to CK3, the fourth clock signal terminal of X3 is electrically connected to CK1, the second clock signal terminal of X1 is electrically connected to CK2, and the first clock signal terminal of X1 is electrically connected to CKO1;
  • the third clock signal terminal of X4 is electrically connected to CK1, the fourth clock signal terminal of X4 is electrically connected to CK2, the second clock signal terminal of X4 is electrically connected to CK3, and the first clock signal terminal of X4 is electrically connected to CKO2;
  • the third clock signal terminal of X5 is electrically connected to CK2, the fourth clock signal terminal of X5 is electrically connected to CK3, the second clock signal terminal of X5 is electrically connected to CK1, and the first clock signal terminal of X5 is electrically connected to CKO3;
  • the third clock signal terminal of X6 is electrically connected to CK3, the fourth clock signal terminal of X6 is electrically connected to CK1, the second clock signal terminal of X6 is electrically connected to CK2, and the first clock signal terminal of X6 is electrically connected to CKO1.
  • FIG. 11 is an operation timing diagram of at least one embodiment of the gate driving circuit in FIG. 10 .
  • the duty cycle of the clock signal provided by CK1, the duty cycle of the clock signal provided by CK2 and the duty cycle of the clock signal provided by CK3 can be the same; the clock signal provided by CK2 is delayed than the clock signal provided by CK1 For a predetermined time, the clock signal provided by CK3 is delayed by a predetermined time from the clock signal provided by CK2, so that the clock signal provided by CK1, the clock signal provided by CK2 and the clock signal provided by CK3 are not low voltages at the same time, but not limited thereto.
  • the duty cycle of the clock signal provided by CK1, the duty cycle of the clock signal provided by CK2, and the duty cycle of the clock signal provided by CK3 may be slightly less than 1/3, or the duty cycle of the clock signal provided by CK1 may be slightly smaller than 1/3.
  • the duty cycle of the clock signal, the duty cycle of the clock signal provided by CK2, and the duty cycle of the clock signal provided by CK3 may also be equal to 1/3; but not limited thereto.
  • the duty cycle of the first first clock signal provided by CKO1 As shown in FIG. 11 , the duty cycle of the first first clock signal provided by CKO1, the duty cycle of the second first clock signal provided by CKO2, and the duty cycle of the third first clock signal provided by CKO3
  • the duty cycle is smaller than the duty cycle of the clock signal provided by CK1; and, the first first clock signal, the second first clock signal and the third first clock signal are not high voltages at the same time .
  • the gate driving method described in at least one embodiment of the present disclosure is applied to the above-mentioned gate driving circuit, and the gate driving method includes:
  • the first output circuit controls the output terminal of the first gate driving signal to output the first gate driving signal under the control of the potential of the first node and the potential of the second node;
  • the first output sub-circuit controls the communication between the second gate driving signal output terminal and the first clock signal terminal under the control of the potential of the first node.
  • the display device includes the above-mentioned gate driving circuit.
  • the display device provided by at least one embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.

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Abstract

一种栅极驱动单元、栅极驱动电路、栅极驱动方法和显示装置。所述栅极驱动单元包括第一输出电路(11)和第二输出电路；所述第二输出电路包括第一输出子电路（121）；第一输出电路（11）分别与第一节点（N1）、第二节点（N2）和第一栅极驱动信号输出端（OUT_P）电连接，用于在第一节点（N1）的电位和第二节点（N2）的电位的控制下，控制第一栅极驱动信号输出端（OUT_P）输出第一栅极驱动信号；第一输出子电路（121）分别与所述第一节点（N1）、第二栅极驱动信号输出端（OUT_N）和第一时钟信号端电连接，用于在所述第一节点（N1）的电位的控制下，控制第二栅极驱动信号输出端（OUT_N）与所述第一时钟信号端之间连通。

Description

栅极驱动单元、栅极驱动电路、栅极驱动方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种栅极驱动单元、栅极驱动电路、栅极驱动方法和显示装置。
背景技术
随着人们对显示需求的不断提升，高低频显示成为了研究的热门，氧化物TFT(薄膜晶体管)因其漏电比较低，可以实现低频，且可以和LTPS(低温多晶硅)工艺兼容，因此被用到了OLED(有机发光二极管)像素电路里。因氧化物TFT为n型晶体管，为其提供控制信号的栅极驱动电路成为了LTPO(Low Temperature Polycrystalline Oxide，低温多晶氧化物)技术的关键技术之一。
公开内容
在一个方面中，本公开实施例提供了一种栅极驱动单元，包括第一输出电路和第二输出电路；所述第二输出电路包括第一输出子电路；
所述第一输出电路分别与第一节点、第二节点和第一栅极驱动信号输出端电连接，用于在所述第一节点的电位和所述第二节点的电位的控制下，控制所述第一栅极驱动信号输出端输出第一栅极驱动信号；
所述第一输出子电路分别与所述第一节点、第二栅极驱动信号输出端和第一时钟信号端电连接，用于在所述第一节点的电位的控制下，控制所述第二栅极驱动信号输出端与所述第一时钟信号端之间连通。
可选的，第一输出子电路包括第一输出晶体管；
所述第一输出晶体管的控制极与所述第一节点电连接，所述第一输出晶体管的第一极与所述第一时钟信号端电连接，所述第一输出晶体管的第二极与所述第二栅极驱动信号输出端电连接。
可选的，所述第二输出电路还包括第二输出子电路和第三节点控制子电路；
所述第二输出子电路分别与第三节点、所述第二栅极驱动信号输出端和第一电压端电连接，用于在所述第三节点的电位的控制下，控制将所述第一电压端提供的第一电压信号写入所述第二栅极驱动信号输出端；
所述第三节点控制子电路分别与所述第一栅极驱动信号输出端、第二时钟信号端、第三时钟信号端、第一电压端和第二电压端电连接，用于在所述第一栅极驱动信号输出端输出的第一栅极驱动信号、所述第二时钟信号端提供的第二时钟信号和所述第三时钟信号端提供的第三时钟信号的控制下，控制所述第三节点的电位。
可选的，所述第二输出子电路包括第二输出晶体管；
所述第二输出晶体管的控制极与所述第三节点电连接，所述第二输出晶体管的第一极与所述第二栅极驱动信号输出端电连接，所述第二输出晶体管的第二极与所述第一电压端电连接。
可选的，所述第三节点控制子电路具体用于在所述第一栅极驱动信号的控制下，控制将所述第二电压端提供的第二电压信号写入所述第三节点，在所述第二时钟信号的控制下，控制将所述第一电压信号写入所述第三节点，并用于根据所述第三时钟信号控制所述第三节点的电位。
可选的，所述第三节点控制子电路包括第一控制晶体管、第二控制晶体管和第一控制电容，其中，
所述第一控制晶体管的控制极与所述第一栅极驱动信号输出端电连接，所述第一控制晶体管的第一极与所述第二电压端电连接，所述第一控制晶体管的第二极与所述第三节点电连接；
所述第二控制晶体管的控制极与所述第二时钟信号端电连接，所述第二控制晶体管的第一极与所述第三节点电连接，所述第二控制晶体管的第二极与所述第一电压端电连接；
所述第一控制电容的第一端与所述第三节点电连接，所述第一控制电容的第二端与所述第三时钟信号端电连接。
可选的，所述第三节点控制子电路包括第三隔离节点控制单元电路和第三节点控制单元电路，其中，
所述第三隔离节点控制单元电路分别与所述第一栅极驱动信号输出端、 所述第二电压端、第三隔离节点、所述第二时钟信号端、所述第三时钟信号端和所述第一电压端电连接，用于在所述第一栅极驱动信号的控制下，控制将所述第二电压信号写入所述第三隔离节点，在所述第二时钟信号的控制下，控制将所述第一电压信号写入所述第三隔离节点，并用于根据所述第三时钟信号控制所述第三隔离节点的电位；
所述第三节点控制单元电路分别与所述第一栅极驱动信号输出端、所述第三隔离节点、所述第二电压端和所述第三节点电连接，用于在所述第一栅极驱动信号的控制下，将第二电压信号写入所述第三节点，并用于在所述第三隔离节点的电位的控制下，控制所述第三节点与所述第三隔离节点之间连通，并用于维持所述第三节点的电位。
可选的，所述第三隔离节点控制单元电路包括第一控制晶体管、第二控制晶体管和第一控制电容，其中，
所述第一控制晶体管的控制极与所述第一栅极驱动信号输出端电连接，所述第一控制晶体管的第一极与所述第二电压端电连接，所述第一控制晶体管的第二极与所述第三隔离节点电连接；
所述第二控制晶体管的控制极与所述第二时钟信号端电连接，所述第二控制晶体管的第一极与所述第三隔离节点电连接，所述第二控制晶体管的第二极与所述第一电压端电连接；
所述第一控制电容的第一端与所述第三隔离节点电连接，所述第一控制电容的第二端与所述第三时钟信号端电连接。
可选的，所述第三节点控制单元电路包括第三控制晶体管、第四控制晶体管和第一存储电容，其中，
所述第三控制晶体管的控制极与所述第一栅极驱动信号端电连接，所述第三控制晶体管的第一极与所述第二电压端电连接，所述第三控制晶体管的第二极与所述第三节点电连接；
所述第四控制晶体管的控制极和所述第四控制晶体管的第一极都与所述第三隔离节点电连接，所述第四控制晶体管的第二极与所述第三节点电连接；
所述第一存储电容的第一端与所述第三节点电连接，所述第一存储电容的第二端与所述第一电压端电连接。
可选的，所述第一输出电路包括第一节点控制子电路和储能子电路；
所述第一节点控制子电路分别与第三时钟信号端、输入端、第二电压端、第二节点和第一节点电连接，用于在所述第三时钟信号端提供的第三时钟信号的控制下，将所述输入端提供的输入信号写入所述第一节点，并用于在所述第二节点的电位的控制下，将所述第二电压端提供的第二电压信号写入所述第一节点；
所述储能子电路的第一端与所述第一节点电连接，所述储能子电路的第二端与所述第一栅极驱动信号输出端电连接，所述储能子电路用于储存电能。
可选的，所述第一节点控制子电路包括第五控制晶体管和第六控制晶体管，其中，
所述第五控制晶体管的控制极与所述第三时钟信号端电连接，所述第五控制晶体管的第一极与所述输入端电连接，所述第五控制晶体管的第二极与所述第一节点电连接；
所述第六控制晶体管的控制极与所述第二节点电连接，所述第六控制晶体管的第一极与所述第二电压端电连接，所述第六控制晶体管的第二极与所述第一节点电连接；
所述储能子电路包括第二存储电容；
所述第二存储电容的第一端与所述第一节点电连接，所述第二存储电容的第二端与所述第一栅极驱动信号输出端电连接。
可选的，所述第一节点控制子电路包括第一控制单元电路、第二控制单元电路、第三控制单元电路、第四控制单元电路、第五控制单元电路和第六控制单元电路，其中，
所述第一控制单元电路分别与第三时钟信号端、所述输入端和第四节点电连接，用于在所述第三时钟信号的控制下，将所述输入信号写入所述第四节点；
所述第二控制单元电路分别与所述第三时钟信号端、所述第四节点和所述第一节点电连接，用于在所述第三时钟信号的控制下，控制所述第四节点与所述第一节点之间连通；
所述第三控制单元电路分别与所述第一栅极驱动信号输出端、第四时钟 信号端和所述第四节点电连接，用于在所述第一栅极驱动信号输出端提供的第一栅极驱动信号的控制下，将第四时钟信号端提供的第四时钟信号写入所述第四节点；
所述第四控制单元电路分别与所述第二节点、第二电压端和第五节点电连接，用于在所述第二节点的电位的控制下，将第二电压端提供的第二电压信号写入所述第五节点；
所述第五控制单元电路分别与所述第二节点、所述第五节点和所述第一节点电连接，用于在所述第二节点的电位的控制下，控制所述第五节点和所述第一节点之间连通；
所述第六控制单元电路分别与所述第一节点、所述第五节点和第一电压端电连接，用于在所述第一节点的电位的控制下，将第一电压端提供的第一电压信号写入所述第五节点。
可选的，所述第一控制单元电路包括第五控制晶体管，所述第二控制单元电路包括第七控制晶体管，所述第三控制单元电路包括第八控制晶体管，所述第四控制单元电路包括第六控制晶体管、所述第五控制单元电路包括第九控制晶体管，所述第六控制单元电路包括第十控制晶体管，其中，
所述第五控制晶体管的控制极与所述第三时钟信号端电连接，所述第五控制晶体管的第一极与所述输入端电连接，所述第五控制晶体管的第二极与所述第四节点电连接；
所述第七控制晶体管的控制极与所述第三时钟信号端电连接，所述第七控制晶体管的第一极与所述第四节点电连接，所述第七控制晶体管的第二极与所述第一节点电连接；
所述第八控制晶体管的控制极与所述第一栅极驱动信号输出端电连接，所述第八控制晶体管的第一极与第四时钟信号端电连接，所述第八控制晶体管的第二极与所述第四节点电连接；
所述第六控制晶体管的控制极与所述第二节点电连接，所述第六控制晶体管的第一极与所述第二电压端电连接，所述第六控制晶体管的第二极与所述第五节点电连接；
所述第九控制晶体管的控制极与所述第二节点电连接，所述第九控制晶 体管的第一极与所述第五节点电连接，所述第九控制晶体管的第二极与所述第一节点电连接；
所述第十控制晶体管的控制极与所述第一节点电连接，所述第十控制晶体管的第一极与所述第五节点电连接，所述第十控制晶体管的第二极与所述第一电压端电连接。
可选的，所述第一输出电路还包括第二节点控制子电路和第三输出子电路；
所述第二节点控制子电路分别与第二节点、所述输入端、第二时钟信号端、第一电压端和第二电压端电连接，用于在所述输入信号的控制下，将第二电压端提供的第二电压信号写入所述第二节点，在所述第二时钟信号端提供的第二时钟信号的控制下，将所述第一电压端提供的第一电压信号写入所述第二节点，并用于维持所述第二节点的电位；
所述第三输出子电路分别与所述第二节点、所述第二电压端、所述第一栅极驱动信号输出端、第一节点和第四时钟信号端电连接，用于在所述第一节点的电位的控制下，将第四时钟信号端提供的第四时钟信号写入所述第一栅极驱动信号输出端，在所述第二节点的电位的控制下，将所述第二电压信号写入所述第一栅极驱动信号输出端。
可选的，所述第二节点控制子电路包括第七控制晶体管、第八控制晶体管和第二控制电容；
所述第七控制晶体管的控制极与第二时钟信号端电连接，所述第七控制晶体管的第一极与第二节点电连接，所述第七控制晶体管的第二极与所述第一电压端电连接；
所述第八控制晶体管的控制极与所述输入端电连接，所述第八控制晶体管的第一极与所述第二电压端电连接，所述第八控制晶体管的第二极与所述第二节点电连接；
所述第二控制电容的第一端与所述第二节点电连接，所述第二控制电容的第二端与所述第二电压端电连接。
可选的，所述第三输出子电路包括第三输出晶体管和第四输出晶体管，其中，
所述第三输出晶体管的控制极与所述第二节点电连接，所述第三输出晶体管的第一极与所述第二电压端电连接，所述第三输出晶体管的第二极与所述第一栅极驱动信号输出端电连接；
所述第四输出晶体管的控制极与所述第一节点电连接，所述第四输出晶体管的第一极与所述第一栅极驱动信号输出端电连接，所述第四输出晶体管的第二极与所述第四时钟信号端电连接。
在第二个方面中，本公开实施例还提供了一种栅极驱动电路，包括上述的栅极驱动单元。
可选的，本公开至少一实施例所述的栅极驱动电路还包括第一时钟信号输入端、第二时钟信号输入端、第三时钟信号输入端、第一个第一时钟信号端、第二个第一时钟信号端和第三个第一时钟信号端；
所述栅极驱动单元的输入端与相邻上一级栅极驱动单元的第一栅极驱动信号输出端电连接；
第3n-2级栅极驱动单元的第三时钟信号端与第一时钟信号输入端电连接，第3n-2级栅极驱动单元的第四时钟信号端与第二时钟信号输入端电连接，第3n-2级栅极驱动单元的第二时钟信号端与第三时钟信号输入端电连接；第3n-2栅极驱动单元的第一时钟信号端与第二个第一时钟信号端电连接；
第3n-1级栅极驱动单元的第三时钟信号端与第二时钟信号输入端电连接，第3n-1级栅极驱动单元的第四时钟信号端与第三时钟信号输入端电连接，第3n-1级栅极驱动单元的第二时钟信号端与第一时钟信号输入端电连接；第3n-1栅极驱动单元的第一时钟信号端与第三个第一时钟信号端电连接；
第3n级栅极驱动单元的第三时钟信号端与第三时钟信号输入端电连接，第3n级栅极驱动单元的第四时钟信号端与第一时钟信号输入端电连接，第3n级栅极驱动单元的第二时钟信号端与第二时钟信号输入端电连接；第3n栅极驱动单元的第一时钟信号端与第一个第一时钟信号端电连接；
n为正整数。
在第三个方面中，本公开实施例还提供了一种栅极驱动方法，应用于上述的栅极驱动电路，所述栅极驱动方法包括：
第一输出电路在第一节点的电位和第二节点的电位的控制下，控制第一 栅极驱动信号输出端输出第一栅极驱动信号；
第一输出子电路在所述第一节点的电位的控制下，控制第二栅极驱动信号输出端与所述第一时钟信号端之间连通。
在第四个方面中，本公开实施例还提供了一种显示装置，包括上述的栅极驱动电路。
附图说明
图1是本公开至少一实施例所述的栅极驱动单元的结构图；
图2是本公开至少一实施例所述的栅极驱动单元的结构图；
图3A是本公开至少一实施例所述的栅极驱动单元的结构图；
图3B是本公开至少一实施例所述的栅极驱动单元的结构图；
图4是本公开至少一实施例所述的栅极驱动单元的结构图；
图5是本公开所述的栅极驱动单元中的第一输出电路的至少一实施例的结构图；
图6是本公开所述的栅极驱动单元中的第一输出电路的至少一实施例的结构图；
图7是本公开所述的栅极驱动单元中的第一输出电路的至少一实施例的结构图；
图8是本公开至少一实施例所述的栅极驱动单元的电路图；
图9是本公开图8所示的栅极驱动单元的至少一实施例的工作时序图；
图10是本公开至少一实施例所述的栅极驱动电路的结构图；
图11是本公开至少一实施例所述的栅极驱动电路的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效 应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开至少一实施例所述的栅极驱动单元包括第一输出电路11和第二输出电路；所述第二输出电路包括第一输出子电路121；
所述第一输出电路11分别与第一节点N1、第二节点N2和第一栅极驱动信号输出端OUT_P电连接，用于在所述第一节点N1的电位和所述第二节点N2的电位的控制下，控制所述第一栅极驱动信号输出端OUT_P输出第一栅极驱动信号；
所述第一输出子电路121分别与所述第一节点N1、第二栅极驱动信号输出端OUT_N和第一时钟信号端电连接，用于在所述第一节点N1的电位的控制下，控制所述第二栅极驱动信号输出端OUT_N与所述第一时钟信号端之间连通；
所述第一时钟信号端用于提供第一时钟信号GCKO。
本公开至少一实施例所述的栅极驱动单元可以提供第一栅极驱动信号和第二栅极驱动信号，所述第一栅极驱动信号用于控制p型晶体管，所述第二栅极驱动信号用于控制n型晶体管，本公开至少一实施例所述的栅极驱动单元可以适用于LTPO(Low Temperature Polycrystalline Oxide，低温多晶氧化物)像素电路。
在本公开至少一实施例所述的栅极驱动单元中，所述第一输出子电路121在第一节点N1的电位下，控制所述第二栅极驱动信号输出端OUT_N与第一时钟信号端之间连通，由于在输出时间段，所述第一节点N1的电位被自举拉低，可以使得所述第一输出子电路121包括的晶体管完全打开，不会有阈值电压损失，使得OUT_N输出的第二栅极驱动信号下降无台阶，并所述第 一输出子电路121与第一时钟信号端电连接，第一时钟信号GCKO在输出阶段的波形与OUT_N输出的栅极驱动信号的波形相同。
在相关技术中，在相关技术中，LTPO像素中集成了LTPS(低温多晶硅)TFT(薄膜晶体管)器件和Oxide(氧化物)TFT器件，其中LTPS TFT器件为p型晶体管，Oxide TFT器件为n型晶体管。
可选的，第一输出子电路可以包括第一输出晶体管；
所述第一输出晶体管的控制极与所述第一节点电连接，所述第一输出晶体管的第一极与所述第一时钟信号端电连接，所述第一输出晶体管的第二极与所述第二栅极驱动信号输出端电连接。
在本公开至少一实施例中，所述第一输出晶体管可以为p型晶体管，但不以此为限。
如图2所示，在图1所示的栅极驱动单元的至少一实施例的基础上，所述第二输出电路还包括第二输出子电路122和第三节点控制子电路123；
所述第二输出子电路122分别与第三节点N3、所述第二栅极驱动信号输出端OUT_N和所述第一电压端V1电连接，用于在所述第三节点N3的电位的控制下，控制将所述第一电压端V1提供的第一电压信号写入所述第二栅极驱动信号输出端OUT_N；
所述第三节点控制子电路123分别与所述第一栅极驱动信号输出端OUT_P、所述第二时钟信号端、所述第三时钟信号端、第一电压端V1和第二电压端V2电连接，用于在所述第一栅极驱动信号输出端OUT_P输出的第一栅极驱动信号、所述第二时钟信号端提供的第二时钟信号GCK3和所述第三时钟信号端提供的第三时钟信号GCK1的控制下，控制所述第三节点N3的电位。
在本公开至少一实施例中，第一电压端V1可以为低电压端，第二电压端V2可以为高电压端，但不以此为限。
本公开如图2所示的栅极驱动单元的至少一实施例在工作时，所述第二输出子电路122在第三节点N3的电位的控制下，控制OUT_N输出第一电压信号；第三节点控制子电路123在第一栅极驱动信号、第二时钟信号GCK3和第三时钟信号GCK1的控制下，控制N3的电位。
可选的，所述第二输出子电路包括第二输出晶体管；
所述第二输出晶体管的控制极与所述第三节点电连接，所述第二输出晶体管的第一极与所述第二栅极驱动信号输出端电连接，所述第二输出晶体管的第二极与所述第一电压端电连接。
在本公开至少一实施例中，所述第三节点控制子电路123具体用于在所述第一栅极驱动信号的控制下，控制将所述第二电压信号写入所述第三节点N3，在所述第二时钟信号GCK3的控制下，控制将所述第一电压信号写入所述第三节点N3，并用于根据所述第三时钟信号GCK1控制所述第三节点N3的电位。
可选的，所述第三节点控制子电路包括第一控制晶体管、第二控制晶体管和第一控制电容，其中，
所述第一控制晶体管的控制极与所述第一栅极驱动信号输出端电连接，所述第一控制晶体管的第一极与所述第二电压端电连接，所述第一控制晶体管的第二极与所述第三节点电连接；
所述第二控制晶体管的控制极与所述第二时钟信号端电连接，所述第二控制晶体管的第一极与所述第三节点电连接，所述第二控制晶体管的第二极与所述第一电压端电连接；
所述第一控制电容的第一端与所述第三节点电连接，所述第一控制电容的第二端与所述第三时钟信号端电连接。
如图3A所示，在图2所示的栅极驱动单元的至少一实施例的基础上，所述第三节点控制子电路123可以包括第一控制晶体管M11、第二控制晶体管M12和第一控制电容C3，其中，
所述第一控制晶体管M11的栅极与所述第一栅极驱动信号输出端OUT_P电连接，所述第一控制晶体管M11的源极与高电压端电连接，所述第一控制晶体管M11的漏极与所述第三节点N3电连接；
所述第二控制晶体管M12的栅极与所述第二时钟信号端电连接，所述第二控制晶体管M12的源极与所述第三节点N3电连接，所述第二控制晶体管M12的漏极与低电压端电连接；所述第二时钟信号端用于提供第二时钟信号GCK3；
所述第一控制电容C3的第一端与所述第三节点N3电连接，所述第一控制电容C3的第二端与所述第三时钟信号端电连接；所述第三时钟信号端用于提供第三时钟信号GCK1。
在图3A所示的至少一实施例中，M11和M12为p型薄膜晶体管，但不以此为限。
本公开如图3A所示的栅极驱动单元的至少一实施例在工作时，当OUT_P输出低电压信号时，M11打开，当OUT_P输出高电压信号时，M11关闭；当GCK3为低电压时，M12打开，当GCK3为高电压时，M12关闭；C3用于根据GCK1的电位控制N3的电位。
本公开如图3A所示的栅极驱动单元的至少一实施例在工作时，
当GCK3为低电压时，M12打开，将VGL写入N3，此时GCK1为高电压，则C3存储一个负压；
当GCK1由高电压降低为低电压时，N3的电位进一步降低，以使得第二输出子电路包括的第二输出晶体管能够完全打开。
如图3B所示，在图2所示的栅极驱动单元的至少一实施例的基础上，所述第三节点控制子电路可以包括第三隔离节点控制单元电路31和第三节点控制单元电路32，其中，
所述第三隔离节点控制单元电路31分别与所述第一栅极驱动信号输出端OUT_P、所述第二电压端V2、第三隔离节点N03、所述第二时钟信号端、所述第三时钟信号端和所述第一电压端V1电连接，用于在OUT_P提供的第一栅极驱动信号的控制下，控制将所述第二电压信号写入所述第三隔离节点N03，在所述第二时钟信号GCK3的控制下，控制将所述第一电压信号写入所述第三隔离节点N03，并用于根据所述第三时钟信号GCK1控制所述第三隔离节点N03的电位；
所述第三节点控制单元电路32分别与所述第一栅极驱动信号输出端OUT_P、所述第三隔离节点N03、所述第二电压端V2和所述第三节点N3电连接，用于在所述第一栅极驱动信号的控制下，将第二电压信号写入所述第三节点N3，并用于在所述第三隔离节点N03的电位的控制下，控制所述第三节点N3与所述第三隔离节点N03之间连通，并用于维持所述第三节点N3 的电位。
可选的，所述第三隔离节点控制单元电路包括第一控制晶体管、第二控制晶体管和第一控制电容，其中，
所述第一控制晶体管的控制极与所述第一栅极驱动信号输出端电连接，所述第一控制晶体管的第一极与所述第二电压端电连接，所述第一控制晶体管的第二极与所述第三隔离节点电连接；
所述第二控制晶体管的控制极与所述第二时钟信号端电连接，所述第二控制晶体管的第一极与所述第三隔离节点电连接，所述第二控制晶体管的第二极与所述第一电压端电连接；
所述第一控制电容的第一端与所述第三隔离节点电连接，所述第一控制电容的第二端与所述第三时钟信号端电连接。
在本公开至少一实施例中，所述第三节点控制单元电路可以包括第三控制晶体管、第四控制晶体管和第一存储电容，其中，
所述第三控制晶体管的控制极与所述第一栅极驱动信号端电连接，所述第三控制晶体管的第一极与所述第二电压端电连接，所述第三控制晶体管的第二极与所述第三节点电连接；
所述第四控制晶体管的控制极和所述第四控制晶体管的第一极都与所述第三隔离节点电连接，所述第四控制晶体管的第二极与所述第三节点电连接；
所述第一存储电容的第一端与所述第三节点电连接，所述第一存储电容的第二端与所述第一电压端电连接。
如图4所示，在图3B所示的栅极驱动单元的至少一实施例的基础上，
所述第三隔离节点控制单元电路31包括第一控制晶体管M11、第二控制晶体管M12和第一控制电容C3，其中，
所述第一控制晶体管M11的栅极与所述第一栅极驱动信号输出端OUT_P电连接，所述第一控制晶体管M11的源极与高电压端电连接，所述第一控制晶体管M11的漏极与所述第三隔离节点N03电连接；所述高电压端用于提供高电压VGH；
所述第二控制晶体管M12的栅极与所述第二时钟信号端电连接，所述第二控制晶体管M12的源极与所述第三隔离节点N03电连接，所述第二控制晶 体管M12的漏极与低电压端电连接；所述低电压端用于提供低电压VGL；所述第二时钟信号端用于提供第二时钟信号GCK3；
所述第一控制电容C3的第一端与所述第三隔离节点N03电连接，所述第一控制电容C3的第二端与所述第三时钟信号端电连接；所述第三时钟信号端用于提供第三时钟信号GCK1；
所述第三节点控制单元电路32包括第三控制晶体管M14、第四控制晶体管M13和第一存储电容C4，其中，
所述第三控制晶体管M14的栅极与所述第一栅极驱动信号端OUT_P电连接，所述第三控制晶体管M14的源极与高电压端电连接，所述第三控制晶体管M14的漏极与所述第三节点N3电连接；
所述第四控制晶体管M13的栅极和所述第四控制晶体管M13的源极都与所述第三隔离节点N03电连接，所述第四控制晶体管M13的漏极与所述第三节点N3电连接；
所述第一存储电容C4的第一端与所述第三节点N3电连接，所述第一存储电容C3的第二端与低电压端电连接；
所述高电压端用于提供高电压VGH，所述低电压端用于提供低电压VGL。
在图4所示的至少一实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
本公开如图4所示的栅极驱动单元的至少一实施例在工作时，
当GCK3为低电压时，M12打开，将VGL写入N03，此时GCK1为高电压，则C3存储一个负压；
当GCK1由高电压降低为低电压时，N3的电位进一步降低，M13打开，N3的电位被拉低到足够低，以使得第二输出子电路包括的第二输出晶体管能够完全打开。
在本公开如图4所示的栅极驱动单元的至少一实施例中，如果不采用M13，则由于GCK1的电位在高电压与低电压之间不断切换，则N3的电位不能一直维持足够低的电位，不能使得第二输出子电路包括的第二输出晶体管充分打开，从而导致低电压输出效果不好；
而本公开如图4所示的栅极驱动单元的至少一实施例采用了M13，则在 GCK1使得N03的电位升高时，M13关闭，可以使得N3的地位维持为足够低的电位，从而能够保证低电压输出的效果。
如图5所示，所述第一输出电路可以包括第一节点控制子电路51和储能子电路52；
所述第一节点控制子电路51分别与第三时钟信号端、输入端GSTV、第二电压端V2、第二节点N2和第一节点N1电连接，用于在所述第三时钟信号端提供的第三时钟信号GCK1的控制下，将所述输入端GSTV提供的输入信号写入所述第一节点N1，并用于在所述第二节点N2的电位的控制下，将所述第二电压端V2提供的第二电压信号写入所述第一节点N1；
所述储能子电路52的第一端与所述第一节点N1电连接，所述储能子电路52的第二端与所述第一栅极驱动信号输出端OUT_P电连接，所述储能子电路52用于储存电能。
可选的，所述第一节点控制子电路包括第五控制晶体管和第六控制晶体管，其中，
所述第五控制晶体管的控制极与所述第三时钟信号端电连接，所述第五控制晶体管的第一极与所述输入端电连接，所述第五控制晶体管的第二极与所述第一节点电连接；
所述第六控制晶体管的控制极与所述第二节点电连接，所述第六控制晶体管的第一极与所述第二电压端电连接，所述第六控制晶体管的第二极与所述第一节点电连接；
所述储能子电路包括第二存储电容；
所述第二存储电容的第一端与所述第一节点电连接，所述第二存储电容的第二端与所述第一栅极驱动信号输出端电连接。
在本公开至少一实施例中，所述第一节点控制子电路可以包括第一控制单元电路、第二控制单元电路、第三控制单元电路、第四控制单元电路、第五控制单元电路和第六控制单元电路，其中，
所述第一控制单元电路分别与第三时钟信号端、所述输入端和第四节点电连接，用于在所述第三时钟信号的控制下，将所述输入信号写入所述第四节点；
所述第二控制单元电路分别与所述第三时钟信号端、所述第四节点和所述第一节点电连接，用于在所述第三时钟信号的控制下，控制所述第四节点与所述第一节点之间连通；
所述第三控制单元电路分别与所述第一栅极驱动信号输出端、第四时钟信号端和所述第四节点电连接，用于在所述第一栅极驱动信号输出端提供的第一栅极驱动信号的控制下，将第四时钟信号端提供的第四时钟信号写入所述第四节点；
所述第四控制单元电路分别与所述第二节点、第二电压端和第五节点电连接，用于在所述第二节点的电位的控制下，将第二电压端提供的第二电压信号写入所述第五节点；
所述第五控制单元电路分别与所述第二节点、所述第五节点和所述第一节点电连接，用于在所述第二节点的电位的控制下，控制所述第五节点和所述第一节点之间连通；
所述第六控制单元电路分别与所述第一节点、所述第五节点和所述第一电压端电连接，用于在所述第一节点的电位的控制下，将第一电压端提供的第一电压信号写入所述第五节点。
在具体实施时，所述第一节点控制子电路可以包括第一控制单元电路、第二控制单元电路、第三控制单元电路、第四控制单元电路、第五控制单元电路和第六控制单元电路，第一控制单元电路用于在所述第三时钟信号的控制下，将所述输入信号写入所述第四节点，所述第四控制单元电路用于在第二节点的电位的控制下，将第二电压信号写入第五节点，第二控制单元电路、第三控制单元电路、第五控制单元电路和第六控制单元电路用于防止漏电流。
如图6所示，在图5所示的栅极驱动单元的至少一实施例的基础上，所述第一节点控制子电路51包括第一控制单元电路、第二控制单元电路、第三控制单元电路、第四控制单元电路、第五控制单元电路和第六控制单元电路，其中，
所述第一控制单元电路包括第五控制晶体管M1，所述第二控制单元电路包括第七控制晶体管M2，所述第三控制单元电路包括第八控制晶体管M10，所述第四控制单元电路包括第六控制晶体管M6、所述第五控制单元电路包括 第九控制晶体管M7，所述第六控制单元电路包括第十控制晶体管M8，其中，
M1的栅极与所述第三时钟信号端电连接，M1的源极与所述输入端GSTV电连接，M1的漏极与第四节点N4电连接；所述第三时钟信号端提供第三时钟信号GCK1；
M2的栅极与所述第三时钟信号端电连接，M2的源极与所述第四节点N4电连接，M2的漏极与所述第一节点N1电连接；
M10的栅极与所述第一栅极驱动信号输出端OUT_P电连接，M10的源极与第四时钟信号端电连接，M10的漏极与所述第四节点N4电连接；所述第四时钟信号端用于提供第四时钟信号GCK2；
M6的栅极与所述第二节点N2电连接，M6的源极与高电压端电连接，M6的漏极与所述第五节点N5电连接；所述高电压端用于提供高电压VGH；
M7的栅极与所述第二节点N2电连接，M7的源极与所述第五节点N5电连接，M7的漏极与所述第一节点N1电连接；
M8的栅极与所述第一节点N1电连接，M8的源极与所述第五节点N5电连接，M8的漏极与低电压端电连接；所述低电压端用于提供低电压VGL。
在图6所示的至少一实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
在图6所示的至少一实施例中，M1和M2构成双栅晶体管，M6和M7构成双栅晶体管，双栅晶体管的漏电流小，并采用M10来控制N4的电位，以在预定时间段减小M1的漏源电压和M2的漏源电压，以降低M1的漏电流和M2的漏电流；并采用M8控制N5的电位，以在预定时间段减小M6的漏源电压和M7的漏源电压，以降低M6的漏电流和M7的漏电流。
在本公开至少一实施例中，所述第一输出电路还包括第二节点控制子电路和第三输出子电路；
所述第二节点控制子电路分别与第二节点、所述输入端、第二时钟信号端、第一电压端和第二电压端电连接，用于在所述输入信号的控制下，将第二电压端提供的第二电压信号写入所述第二节点，在所述第二时钟信号端提供的第二时钟信号的控制下，将所述第一电压端提供的第一电压信号写入所述第二节点，并用于维持所述第二节点的电位；
所述第三输出子电路分别与所述第二节点、所述第二电压端、所述第一栅极驱动信号输出端、第一节点和第四时钟信号端电连接，用于在所述第一节点的电位的控制下，将第四时钟信号端提供的第四时钟信号写入所述第一栅极驱动信号输出端，在所述第二节点的电位的控制下，将所述第二电压信号写入所述第一栅极驱动信号输出端。
如图7所示，在图5所示的栅极驱动单元的至少一实施例的基础上，所述第一输出电路还包括第二节点控制子电路53和第三输出子电路54；
所述第二节点控制子电路53分别与第二节点N2、所述输入端GSTV、第二时钟信号端、第一电压端V1和第二电压端V2电连接，用于在GSTV提供的输入信号的控制下，将第二电压端V2提供的第二电压信号写入所述第二节点N2，在所述第二时钟信号端提供的第二时钟信号GCK3的控制下，将所述第一电压端V1提供的第一电压信号写入所述第二节点N2，并用于维持所述第二节点N2的电位；
所述第三输出子电路54分别与所述第二节点N2、所述第二电压端V2、所述第一栅极驱动信号输出端OUT_P、第一节点N1和第四时钟信号端电连接，用于在所述第一节点N1的电位的控制下，将第四时钟信号端提供的第四时钟信号GCK2写入所述第一栅极驱动信号输出端OUT_P，在所述第二节点N2的电位的控制下，将所述第二电压信号写入所述第一栅极驱动信号输出端OUT_P。
如图7所示的栅极驱动单元的至少一实施例在工作时，所述第二节点控制子电路53在输入信号的控制下，将第二电压信号写入N2，在第二时钟信号GCK3的控制下，将第一电压信号写入N2，并维持N2的电位；第三输出子电路在N1的电位的控制下，控制OUT_P输出GCK2，在N2的电位的控制将，控制OUT_P输出第二电压信号。
可选的，所述第二节点控制子电路包括第七控制晶体管、第八控制晶体管和第二控制电容；
所述第七控制晶体管的控制极与第二时钟信号端电连接，所述第七控制晶体管的第一极与第二节点电连接，所述第七控制晶体管的第二极与所述第一电压端电连接；
所述第八控制晶体管的控制极与所述输入端电连接，所述第八控制晶体管的第一极与所述第二电压端电连接，所述第八控制晶体管的第二极与所述第二节点电连接；
所述第二控制电容的第一端与所述第二节点电连接，所述第二控制电容的第二端与所述第二电压端电连接。
可选的，所述第三输出子电路包括第三输出晶体管和第四输出晶体管，其中，
所述第三输出晶体管的控制极与所述第二节点电连接，所述第三输出晶体管的第一极与所述第二电压端电连接，所述第三输出晶体管的第二极与所述第一栅极驱动信号输出端电连接；
所述第四输出晶体管的控制极与所述第一节点电连接，所述第四输出晶体管的第一极与所述第一栅极驱动信号输出端电连接，所述第四输出晶体管的第二极与所述第四时钟信号端电连接。
如图8所示，在图4所示的栅极驱动单元的至少一实施例的基础上，所述第一输出子电路121包括第一输出晶体管M16；所述第二输出子电路包括第二输出晶体管M15；所述第一输出电路包括第一节点控制子电路51、储能子电路52、第二节点控制子电路53和第三输出子电路54；
M16的栅极与所述第一节点N1电连接，M16的源极与所述第一时钟信号端电连接，M16的漏极与所述第二栅极驱动信号输出端OUT_N电连接；所述第一时钟信号端用于提供第一时钟信号GCKO；
M15的栅极与所述第三节点N3电连接，M15的源极与所述第二栅极驱动信号输出端OUT_N电连接，M15的漏极与低电压端电连接；所述低电压端用于提供低电压VGL；
所述第一节点控制子电路51第一控制单元电路、第二控制单元电路、第三控制单元电路、第四控制单元电路、第五控制单元电路和第六控制单元电路，其中，
所述第一控制单元电路包括第五控制晶体管M1，所述第二控制单元电路包括第七控制晶体管M2，所述第三控制单元电路包括第八控制晶体管M10，所述第四控制单元电路包括第六控制晶体管M6、所述第五控制单元电路包括 第九控制晶体管M7，所述第六控制单元电路包括第十控制晶体管M8，其中，
M1的栅极与所述第三时钟信号端电连接，M1的源极与所述输入端GSTV电连接，M1的漏极与第四节点N4电连接；所述第三时钟信号端提供第三时钟信号GCK1；
M2的栅极与所述第三时钟信号端电连接，M2的源极与所述第四节点N4电连接，M2的漏极与所述第一节点N1电连接；
M10的栅极与所述第一栅极驱动信号输出端OUT_P电连接，M10的源极与第四时钟信号端电连接，M10的漏极与所述第四节点N4电连接；所述第四时钟信号端用于提供第四时钟信号端GCK2；
M6的栅极与所述第二节点N2电连接，M6的源极与高电压端电连接，M6的漏极与所述第五节点N5电连接；所述高电压端用于提供高电压VGH；
M7的栅极与所述第二节点N2电连接，M7的源极与所述第五节点N5电连接，M7的漏极与所述第一节点N1电连接；
M8的栅极与所述第一节点N1电连接，M8的源极与所述第五节点N5电连接，M8的漏极与低电压端电连接；所述低电压端用于提供低电压VGL；
所述储能子电路52包括第二存储电容C1；
C1的第一端与所述第一节点N1电连接，C1的第二端与OUT_P电连接；
所述第二节点控制子电路53包括第七控制晶体管M5、第八控制晶体管M9和第二控制电容C2；
M5的栅极与第二时钟信号端电连接，M5的源极与第二节点N2电连接，M5的漏极与低电压端电连接；所述低电压端用于提供低电压VGL；
M9的栅极与所述输入端GSTV电连接，M9的源极与高电压端电连接，M9的漏极与所述第二节点N2电连接；所述高电压端用于提供高电压VGH；
所述第二控制电容C2的第一端与所述第二节点N2电连接，所述第二控制电容C2的第二端与所述高电压端电连接；
所述第三输出子电路54包括第三输出晶体管M4和第四输出晶体管M3，其中，
所述第三输出晶体管M4的栅极与所述第二节点N2电连接，所述第三输出晶体管M4源极与所述高电压端电连接，所述第三输出晶体管M4的漏极 与所述第一栅极驱动信号输出端OUT_P电连接；
所述第四输出晶体管M3的栅极与所述第一节点N1电连接，所述第四输出晶体管M3的源极与所述第一栅极驱动信号输出端OUT_P电连接，所述第四输出晶体管M3的漏极与所述第四时钟信号端电连接；所述第四时钟信号端用于提供第四时钟信号GCK2。
在图8所示的栅极驱动单元的至少一实施例中，所有的晶体管都为p型薄膜晶体管，但不依次为限。
在图8所示的栅极驱动单元的至少一实施例中，M1的尺寸和M2的尺寸相同，并M1和M2在版图上相邻，因此M1的阈值电压和M2的阈值电压可以相同，但不以此为限。
如图9所示，本公开如图8所示的栅极驱动单元的至少一实施例在工作时，
在预充阶段S1，GSTV提供低电压，GCK1为低电压，GCK2为高电压，M1和M2打开，N1的电位被拉至低电位VGL+Vth，M3开启，OUT_P输出高电压，C1两端存储的电压为VGL+Vth-VGH；与此同时，M9开启，N2的电位为高电位，M4关断；其中，Vth为M1的阈值电压；
在自举输出阶段S2，GSTV提供高电压，GCK1为高电压，GCK2为低电压，因M3在上一阶段已经打开，所以GCK2的低电压通过M3传输到OUT_P,与此同时，因C1两端电压不能突变，所以N1的电位被举至更低的电位，N1的电位为2VGL+Vth-2VGH，从而使M3更好地打开；
在所述自举输出阶段S2包括的后半段时间段，GCK2由低电压跳变为高电压，因为N1的电位仍低于GCK2的电位，因此，M3打开，OUTP输出GCK2，实现了OUT_P的低脉冲输出；
在所述自举输出阶段S2，N1的低电位将M16打开，OUT_N输出GCKO，因GCKO的高脉冲脉宽小于GCK2的低脉冲脉宽，因此GCKO的脉冲可全部传输到OUT_N，包括上升和下降部分；OUT_P的低电位将M11和M14打开，将N3的电位和N03的电位稳定在高电位，M15关闭，避免了OUT_N输出逻辑上的冲突；
在节点上拉阶段S3，GCK3为低电压，M5打开，N2的电位被拉低至低 电位，M4打开，OUT_P输出VGH；同时，N2的低电位将M6和M7打开，N1的电位被拉高至高电位，M3关断，M12打开，N03的电位为低电位，由于GCK1为高电压，则此时C3存储电位为VGL+Vth12-VGH；其中，Vth12为M12的阈值电压；
在保持阶段S4，GCK3周期性将N2的电位拉至VGL，保证M4开启，使得OUT_P稳定输出VGH，GCK3周期性将N03的电和N3的电位拉低，将VGL+Vth12-VGH存储在C3中，同时，GCK1周期性跳变为低电压，通过C3将N03的电位和N3的电位拉至更低电位，以保证M15充分打开，将VGL输出至OUT_N。
如图9所示，GCK1的占空比、GCK2的占空比和GCK3的占空比可以相同；GCK2比GCK1延迟预定时间，GCK3比GCK2延迟预定时间，以使得GCK1、GCK2和GCK3不同时为低电压，但不以此为限。
在本公开至少一实施例中，GCK1的占空比、GCK2的占空比和GCK3的占空比可以略小于1/3，或者，GCK1的占空比、GCK2的占空比和GCK3的占空比也可以等于1/3；但不以此为限。
本公开至少一实施例所述的栅极驱动电路包括上述的栅极驱动单元。
本公开至少一实施例所述的栅极驱动电路还包括第一时钟信号输入端、第二时钟信号输入端、第三时钟信号输入端、第一个第一时钟信号端、第二个第一时钟信号端和第三个第一时钟信号端；
所述栅极驱动单元的输入端与相邻上一级栅极驱动单元的第一栅极驱动信号输出端电连接；
第3n-2级栅极驱动单元的第三时钟信号端与第一时钟信号输入端电连接，第3n-2级栅极驱动单元的第四时钟信号端与第二时钟信号输入端电连接，第3n-2级栅极驱动单元的第二时钟信号端与第三时钟信号输入端电连接；第3n-2栅极驱动单元的第一时钟信号端与第二个第一时钟信号端电连接；
第3n-1级栅极驱动单元的第三时钟信号端与第二时钟信号输入端电连接，第3n-1级栅极驱动单元的第四时钟信号端与第三时钟信号输入端电连接，第3n-1级栅极驱动单元的第二时钟信号端与第一时钟信号输入端电连接；第3n-1栅极驱动单元的第一时钟信号端与第三个第一时钟信号端电连接；
第3n级栅极驱动单元的第三时钟信号端与第三时钟信号输入端电连接，第3n级栅极驱动单元的第四时钟信号端与第一时钟信号输入端电连接，第3n级栅极驱动单元的第二时钟信号端与第二时钟信号输入端电连接；第3n栅极驱动单元的第一时钟信号端与第一个第一时钟信号端电连接；
n为正整数。
如图10所示，标号为X1的为本公开至少一实施例所述的栅极驱动电路包括的第一级栅极驱动单元，标号为X2的为所述的栅极驱动电路包括的第二级栅极驱动单元，标号为X3的为本公开至少一实施例所述的栅极驱动电路包括的第三级栅极驱动单元，标号为X4的为所述的栅极驱动电路包括的第四级栅极驱动单元，标号为X5的为本公开至少一实施例所述的栅极驱动电路包括的第五级栅极驱动单元，标号为X6的为所述的栅极驱动电路包括的第六级栅极驱动单元；
标号为STV的为起始端；标号为OUT_P(1)的为X1的第一栅极驱动信号输出端，标号为OUT_N(1)的为X1的第二栅极驱动信号输出端；标号为OUT_P(2)的为X2的第一栅极驱动信号输出端，标号为OUT_N(2)的为X2的第二栅极驱动信号输出端；标号为OUT_P(3)的为X3的第一栅极驱动信号输出端，标号为OUT_N(3)的为X3的第二栅极驱动信号输出端；标号为OUT_P(4)的为X4的第一栅极驱动信号输出端，标号为OUT_N(4)的为X4的第二栅极驱动信号输出端；标号为OUT_P(5)的为X5的第一栅极驱动信号输出端，标号为OUT_N(5)的为X5的第二栅极驱动信号输出端；标号为OUT_P(6)的为X6的第一栅极驱动信号输出端，标号为OUT_N(6)的为X6的第二栅极驱动信号输出端；
标号为CK1的为第一时钟信号输入端，标号为CK2的为第二时钟信号输入端，标号为CK3的为第三时钟信号输入端；
标号为CKO1的为第一个第一时钟信号端，标号为CKO2的为第二个第一时钟信号端，标号为CKO3的为第三个第一时钟信号端；
X1的第三时钟信号端与CK1电连接，X1的第四时钟信号端与CK2电连接，X1的第二时钟信号端与CK3电连接，X1的第一时钟信号端与CKO2电连接；
X2的第三时钟信号端与CK2电连接，X2的第四时钟信号端与CK3电连接，X2的第二时钟信号端与CK1电连接，X1的第一时钟信号端与CKO3电连接；
X3的第三时钟信号端与CK3电连接，X3的第四时钟信号端与CK1电连接，X1的第二时钟信号端与CK2电连接，X1的第一时钟信号端与CKO1电连接；
X4的第三时钟信号端与CK1电连接，X4的第四时钟信号端与CK2电连接，X4的第二时钟信号端与CK3电连接，X4的第一时钟信号端与CKO2电连接；
X5的第三时钟信号端与CK2电连接，X5的第四时钟信号端与CK3电连接，X5的第二时钟信号端与CK1电连接，X5的第一时钟信号端与CKO3电连接；
X6的第三时钟信号端与CK3电连接，X6的第四时钟信号端与CK1电连接，X6的第二时钟信号端与CK2电连接，X6的第一时钟信号端与CKO1电连接。
图11是图10中的栅极驱动电路的至少一实施例的工作时序图。
如图11所示，CK1提供的时钟信号的占空比、CK2提供的时钟信号的占空比和CK3提供的时钟信号的占空比可以相同；CK2提供的时钟信号比CK1提供的时钟信号延迟预定时间，CK3提供的时钟信号比CK2提供的时钟信号延迟预定时间，以使得CK1提供的时钟信号、CK2提供的时钟信号和CK3提供的时钟信号不同时为低电压，但不以此为限。
在本公开至少一实施例中，CK1提供的时钟信号的占空比、CK2提供的时钟信号的占空比和CK3提供的时钟信号的占空比可以略小于1/3，或者，CK1提供的时钟信号的占空比、CK2提供的时钟信号的占空比和CK3提供的时钟信号的占空比也可以等于1/3；但不以此为限。
如图11所示，CKO1提供的第一个第一时钟信号的占空比、CKO2提供的第二个第一时钟信号的占空比，以及，CKO3提供的第三个第一时钟信号的占空比都小于CK1提供的时钟信号的占空比；并且，所述第一个第一时钟信号、所述第二个第一时钟信号和所述第三个第一时钟信号不同时为高电压。
本公开至少一实施例所述的栅极驱动方法，应用于上述的栅极驱动电路，所述栅极驱动方法包括：
第一输出电路在第一节点的电位和第二节点的电位的控制下，控制第一栅极驱动信号输出端输出第一栅极驱动信号；
第一输出子电路在所述第一节点的电位的控制下，控制第二栅极驱动信号输出端与所述第一时钟信号端之间连通。
本公开至少一实施例所述的显示装置包括上述的栅极驱动电路。
本公开至少一实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (20)

  1. 一种栅极驱动单元，包括第一输出电路和第二输出电路；所述第二输出电路包括第一输出子电路；
    所述第一输出电路分别与第一节点、第二节点和第一栅极驱动信号输出端电连接，用于在所述第一节点的电位和所述第二节点的电位的控制下，控制所述第一栅极驱动信号输出端输出第一栅极驱动信号；
    所述第一输出子电路分别与所述第一节点、第二栅极驱动信号输出端和第一时钟信号端电连接，用于在所述第一节点的电位的控制下，控制所述第二栅极驱动信号输出端与所述第一时钟信号端之间连通。
  2. 如权利要求1所述的栅极驱动单元，其中，第一输出子电路包括第一输出晶体管；
    所述第一输出晶体管的控制极与所述第一节点电连接，所述第一输出晶体管的第一极与所述第一时钟信号端电连接，所述第一输出晶体管的第二极与所述第二栅极驱动信号输出端电连接。
  3. 如权利要求1所述的栅极驱动单元，其中，所述第二输出电路还包括第二输出子电路和第三节点控制子电路；
    所述第二输出子电路分别与第三节点、所述第二栅极驱动信号输出端和第一电压端电连接，用于在所述第三节点的电位的控制下，控制将所述第一电压端提供的第一电压信号写入所述第二栅极驱动信号输出端；
    所述第三节点控制子电路分别与所述第一栅极驱动信号输出端、第二时钟信号端、第三时钟信号端、第一电压端和第二电压端电连接，用于在所述第一栅极驱动信号输出端输出的第一栅极驱动信号、所述第二时钟信号端提供的第二时钟信号和所述第三时钟信号端提供的第三时钟信号的控制下，控制所述第三节点的电位。
  4. 如权利要求3所述的栅极驱动单元，其中，所述第二输出子电路包括第二输出晶体管；
    所述第二输出晶体管的控制极与所述第三节点电连接，所述第二输出晶体管的第一极与所述第二栅极驱动信号输出端电连接，所述第二输出晶体管 的第二极与所述第一电压端电连接。
  5. 如权利要求3所述的栅极驱动单元，其中，所述第三节点控制子电路具体用于在所述第一栅极驱动信号的控制下，控制将所述第二电压端提供的第二电压信号写入所述第三节点，在所述第二时钟信号的控制下，控制将所述第一电压信号写入所述第三节点，并用于根据所述第三时钟信号控制所述第三节点的电位。
  6. 如权利要求5所述的栅极驱动单元，其中，所述第三节点控制子电路包括第一控制晶体管、第二控制晶体管和第一控制电容，其中，
    所述第一控制晶体管的控制极与所述第一栅极驱动信号输出端电连接，所述第一控制晶体管的第一极与所述第二电压端电连接，所述第一控制晶体管的第二极与所述第三节点电连接；
    所述第二控制晶体管的控制极与所述第二时钟信号端电连接，所述第二控制晶体管的第一极与所述第三节点电连接，所述第二控制晶体管的第二极与所述第一电压端电连接；
    所述第一控制电容的第一端与所述第三节点电连接，所述第一控制电容的第二端与所述第三时钟信号端电连接。
  7. 如权利要求3所述的栅极驱动单元，其中，所述第三节点控制子电路包括第三隔离节点控制单元电路和第三节点控制单元电路，其中，
    所述第三隔离节点控制单元电路分别与所述第一栅极驱动信号输出端、所述第二电压端、第三隔离节点、所述第二时钟信号端、所述第三时钟信号端和所述第一电压端电连接，用于在所述第一栅极驱动信号的控制下，控制将所述第二电压信号写入所述第三隔离节点，在所述第二时钟信号的控制下，控制将所述第一电压信号写入所述第三隔离节点，并用于根据所述第三时钟信号控制所述第三隔离节点的电位；
    所述第三节点控制单元电路分别与所述第一栅极驱动信号输出端、所述第三隔离节点、所述第二电压端和所述第三节点电连接，用于在所述第一栅极驱动信号的控制下，将第二电压信号写入所述第三节点，并用于在所述第三隔离节点的电位的控制下，控制所述第三节点与所述第三隔离节点之间连通，并用于维持所述第三节点的电位。
  8. 如权利要求7所述的栅极驱动单元，其中，所述第三隔离节点控制单元电路包括第一控制晶体管、第二控制晶体管和第一控制电容，其中，
    所述第一控制晶体管的控制极与所述第一栅极驱动信号输出端电连接，所述第一控制晶体管的第一极与所述第二电压端电连接，所述第一控制晶体管的第二极与所述第三隔离节点电连接；
    所述第二控制晶体管的控制极与所述第二时钟信号端电连接，所述第二控制晶体管的第一极与所述第三隔离节点电连接，所述第二控制晶体管的第二极与所述第一电压端电连接；
    所述第一控制电容的第一端与所述第三隔离节点电连接，所述第一控制电容的第二端与所述第三时钟信号端电连接。
  9. 如权利要求7所述的栅极驱动单元，其中，所述第三节点控制单元电路包括第三控制晶体管、第四控制晶体管和第一存储电容，其中，
    所述第三控制晶体管的控制极与所述第一栅极驱动信号端电连接，所述第三控制晶体管的第一极与所述第二电压端电连接，所述第三控制晶体管的第二极与所述第三节点电连接；
    所述第四控制晶体管的控制极和所述第四控制晶体管的第一极都与所述第三隔离节点电连接，所述第四控制晶体管的第二极与所述第三节点电连接；
    所述第一存储电容的第一端与所述第三节点电连接，所述第一存储电容的第二端与所述第一电压端电连接。
  10. 如权利要求1至9中任一权利要求所述的栅极驱动单元，其中，所述第一输出电路包括第一节点控制子电路和储能子电路；
    所述第一节点控制子电路分别与第三时钟信号端、输入端、第二电压端、第二节点和第一节点电连接，用于在所述第三时钟信号端提供的第三时钟信号的控制下，将所述输入端提供的输入信号写入所述第一节点，并用于在所述第二节点的电位的控制下，将所述第二电压端提供的第二电压信号写入所述第一节点；
    所述储能子电路的第一端与所述第一节点电连接，所述储能子电路的第二端与所述第一栅极驱动信号输出端电连接，所述储能子电路用于储存电能。
  11. 如权利要求10所述的栅极驱动单元，其中，所述第一节点控制子电 路包括第五控制晶体管和第六控制晶体管，其中，
    所述第五控制晶体管的控制极与所述第三时钟信号端电连接，所述第五控制晶体管的第一极与所述输入端电连接，所述第五控制晶体管的第二极与所述第一节点电连接；
    所述第六控制晶体管的控制极与所述第二节点电连接，所述第六控制晶体管的第一极与所述第二电压端电连接，所述第六控制晶体管的第二极与所述第一节点电连接；
    所述储能子电路包括第二存储电容；
    所述第二存储电容的第一端与所述第一节点电连接，所述第二存储电容的第二端与所述第一栅极驱动信号输出端电连接。
  12. 如权利要求10所述的栅极驱动单元，其中，所述第一节点控制子电路包括第一控制单元电路、第二控制单元电路、第三控制单元电路、第四控制单元电路、第五控制单元电路和第六控制单元电路，其中，
    所述第一控制单元电路分别与第三时钟信号端、所述输入端和第四节点电连接，用于在所述第三时钟信号的控制下，将所述输入信号写入所述第四节点；
    所述第二控制单元电路分别与所述第三时钟信号端、所述第四节点和所述第一节点电连接，用于在所述第三时钟信号的控制下，控制所述第四节点与所述第一节点之间连通；
    所述第三控制单元电路分别与所述第一栅极驱动信号输出端、第四时钟信号端和所述第四节点电连接，用于在所述第一栅极驱动信号输出端提供的第一栅极驱动信号的控制下，将第四时钟信号端提供的第四时钟信号写入所述第四节点；
    所述第四控制单元电路分别与所述第二节点、第二电压端和第五节点电连接，用于在所述第二节点的电位的控制下，将第二电压端提供的第二电压信号写入所述第五节点；
    所述第五控制单元电路分别与所述第二节点、所述第五节点和所述第一节点电连接，用于在所述第二节点的电位的控制下，控制所述第五节点和所述第一节点之间连通；
    所述第六控制单元电路分别与所述第一节点、所述第五节点和第一电压端电连接，用于在所述第一节点的电位的控制下，将第一电压端提供的第一电压信号写入所述第五节点。
  13. 如权利要求12所述的栅极驱动单元，其中，所述第一控制单元电路包括第五控制晶体管，所述第二控制单元电路包括第七控制晶体管，所述第三控制单元电路包括第八控制晶体管，所述第四控制单元电路包括第六控制晶体管、所述第五控制单元电路包括第九控制晶体管，所述第六控制单元电路包括第十控制晶体管，其中，
    所述第五控制晶体管的控制极与所述第三时钟信号端电连接，所述第五控制晶体管的第一极与所述输入端电连接，所述第五控制晶体管的第二极与所述第四节点电连接；
    所述第七控制晶体管的控制极与所述第三时钟信号端电连接，所述第七控制晶体管的第一极与所述第四节点电连接，所述第七控制晶体管的第二极与所述第一节点电连接；
    所述第八控制晶体管的控制极与所述第一栅极驱动信号输出端电连接，所述第八控制晶体管的第一极与第四时钟信号端电连接，所述第八控制晶体管的第二极与所述第四节点电连接；
    所述第六控制晶体管的控制极与所述第二节点电连接，所述第六控制晶体管的第一极与所述第二电压端电连接，所述第六控制晶体管的第二极与所述第五节点电连接；
    所述第九控制晶体管的控制极与所述第二节点电连接，所述第九控制晶体管的第一极与所述第五节点电连接，所述第九控制晶体管的第二极与所述第一节点电连接；
    所述第十控制晶体管的控制极与所述第一节点电连接，所述第十控制晶体管的第一极与所述第五节点电连接，所述第十控制晶体管的第二极与所述第一电压端电连接。
  14. 如权利要求10所述的栅极驱动单元，其中，所述第一输出电路还包括第二节点控制子电路和第三输出子电路；
    所述第二节点控制子电路分别与第二节点、所述输入端、第二时钟信号 端、第一电压端和第二电压端电连接，用于在所述输入信号的控制下，将第二电压端提供的第二电压信号写入所述第二节点，在所述第二时钟信号端提供的第二时钟信号的控制下，将所述第一电压端提供的第一电压信号写入所述第二节点，并用于维持所述第二节点的电位；
    所述第三输出子电路分别与所述第二节点、所述第二电压端、所述第一栅极驱动信号输出端、第一节点和第四时钟信号端电连接，用于在所述第一节点的电位的控制下，将第四时钟信号端提供的第四时钟信号写入所述第一栅极驱动信号输出端，在所述第二节点的电位的控制下，将所述第二电压信号写入所述第一栅极驱动信号输出端。
  15. 如权利要求14所述的栅极驱动单元，其中，所述第二节点控制子电路包括第七控制晶体管、第八控制晶体管和第二控制电容；
    所述第七控制晶体管的控制极与第二时钟信号端电连接，所述第七控制晶体管的第一极与第二节点电连接，所述第七控制晶体管的第二极与所述第一电压端电连接；
    所述第八控制晶体管的控制极与所述输入端电连接，所述第八控制晶体管的第一极与所述第二电压端电连接，所述第八控制晶体管的第二极与所述第二节点电连接；
    所述第二控制电容的第一端与所述第二节点电连接，所述第二控制电容的第二端与所述第二电压端电连接。
  16. 如权利要求14所述的栅极驱动单元，其中，所述第三输出子电路包括第三输出晶体管和第四输出晶体管，其中，
    所述第三输出晶体管的控制极与所述第二节点电连接，所述第三输出晶体管的第一极与所述第二电压端电连接，所述第三输出晶体管的第二极与所述第一栅极驱动信号输出端电连接；
    所述第四输出晶体管的控制极与所述第一节点电连接，所述第四输出晶体管的第一极与所述第一栅极驱动信号输出端电连接，所述第四输出晶体管的第二极与所述第四时钟信号端电连接。
  17. 一种栅极驱动电路，包括如权利要求1至16中任一权利要求所述的栅极驱动单元。
  18. 如权利要求17所述的栅极驱动电路，其中，还包括第一时钟信号输入端、第二时钟信号输入端、第三时钟信号输入端、第一个第一时钟信号端、第二个第一时钟信号端和第三个第一时钟信号端；
    所述栅极驱动单元的输入端与相邻上一级栅极驱动单元的第一栅极驱动信号输出端电连接；
    第3n-2级栅极驱动单元的第三时钟信号端与第一时钟信号输入端电连接，第3n-2级栅极驱动单元的第四时钟信号端与第二时钟信号输入端电连接，第3n-2级栅极驱动单元的第二时钟信号端与第三时钟信号输入端电连接；第3n-2栅极驱动单元的第一时钟信号端与第二个第一时钟信号端电连接；
    第3n-1级栅极驱动单元的第三时钟信号端与第二时钟信号输入端电连接，第3n-1级栅极驱动单元的第四时钟信号端与第三时钟信号输入端电连接，第3n-1级栅极驱动单元的第二时钟信号端与第一时钟信号输入端电连接；第3n-1栅极驱动单元的第一时钟信号端与第三个第一时钟信号端电连接；
    第3n级栅极驱动单元的第三时钟信号端与第三时钟信号输入端电连接，第3n级栅极驱动单元的第四时钟信号端与第一时钟信号输入端电连接，第3n级栅极驱动单元的第二时钟信号端与第二时钟信号输入端电连接；第3n栅极驱动单元的第一时钟信号端与第一个第一时钟信号端电连接；
    n为正整数。
  19. 一种栅极驱动方法，应用于如权利要求1至16中任一权利要求所述的栅极驱动电路，所述栅极驱动方法包括：
    第一输出电路在第一节点的电位和第二节点的电位的控制下，控制第一栅极驱动信号输出端输出第一栅极驱动信号；
    第一输出子电路在所述第一节点的电位的控制下，控制第二栅极驱动信号输出端与所述第一时钟信号端之间连通。
  20. 一种显示装置，包括如权利要求17或18所述的栅极驱动电路。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120139962A1 (en) * 2010-12-06 2012-06-07 Bo-Yong Chung Display device, scan driver for a display device, and a driving method thereof
CN104299590A (zh) * 2014-10-30 2015-01-21 京东方科技集团股份有限公司 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置
CN205282054U (zh) * 2016-01-05 2016-06-01 北京京东方显示技术有限公司 一种移位寄存器单元、栅极驱动电路及显示面板
CN106782284A (zh) * 2017-03-02 2017-05-31 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置以及显示装置
CN111179813A (zh) * 2020-03-18 2020-05-19 合肥京东方卓印科技有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI360094B (en) * 2007-04-25 2012-03-11 Wintek Corp Shift register and liquid crystal display
KR101022092B1 (ko) * 2009-01-12 2011-03-17 삼성모바일디스플레이주식회사 쉬프트 레지스터 및 이를 이용한 유기전계발광 표시장치
KR20130003250A (ko) 2011-06-30 2013-01-09 삼성디스플레이 주식회사 스테이지 회로 및 이를 이용한 주사 구동부
KR102084716B1 (ko) 2013-03-13 2020-03-05 삼성디스플레이 주식회사 표시 패널
CN103489423A (zh) 2013-09-27 2014-01-01 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器、阵列基板及显示装置
CN203644373U (zh) 2013-12-05 2014-06-11 华南理工大学 栅极驱动单元及栅极扫描驱动器
US20170194162A1 (en) 2016-01-05 2017-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor manufacturing equipment and method for treating wafer
CN106057119B (zh) 2016-07-29 2023-02-10 华南理工大学 一种行扫描驱动单元、行扫描驱动系统及其驱动方法
KR102615273B1 (ko) 2016-11-02 2023-12-18 삼성디스플레이 주식회사 게이트 구동회로 및 이를 포함하는 표시 장치
KR102707009B1 (ko) * 2016-12-19 2024-09-12 엘지디스플레이 주식회사 게이트 구동회로
CN107134246B (zh) 2017-05-18 2023-09-26 华南理工大学 一种栅极驱动单元及行栅极扫描驱动器及其驱动方法
KR20190021985A (ko) 2017-08-24 2019-03-06 엘지디스플레이 주식회사 유기발광 표시장치
CN108257550A (zh) 2018-03-30 2018-07-06 京东方科技集团股份有限公司 像素电路及其驱动方法、阵列基板、显示面板
CN108648718B (zh) * 2018-08-01 2020-07-14 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN110176204B (zh) * 2018-08-24 2021-01-26 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN113196368B (zh) * 2019-09-25 2023-05-23 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120139962A1 (en) * 2010-12-06 2012-06-07 Bo-Yong Chung Display device, scan driver for a display device, and a driving method thereof
CN104299590A (zh) * 2014-10-30 2015-01-21 京东方科技集团股份有限公司 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置
CN205282054U (zh) * 2016-01-05 2016-06-01 北京京东方显示技术有限公司 一种移位寄存器单元、栅极驱动电路及显示面板
CN106782284A (zh) * 2017-03-02 2017-05-31 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置以及显示装置
CN111179813A (zh) * 2020-03-18 2020-05-19 合肥京东方卓印科技有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置

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