WO2021232806A1

WO2021232806A1 - Trench gate metal oxide semiconductor field effect transistor and manufacturing method therefor

Info

Publication number: WO2021232806A1
Application number: PCT/CN2020/140301
Authority: WO
Inventors: 方冬; 肖魁
Original assignee: 华润微电子（重庆）有限公司
Priority date: 2020-05-18
Filing date: 2020-12-28
Publication date: 2021-11-25
Also published as: CN114361248A

Abstract

A trench gate metal oxide semiconductor field effect transistor and a manufacturing method therefor. The trench gate metal oxide semiconductor field effect transistor comprises: a first conductive type drift region (100), formed on a semiconductor substrate; a second conductive type body region (110), formed in the drift region (100); a first conductive type source region (111), formed in the body region (110), the source region (111) being provided with a trench penetrating through the source region (111) and the body region (110) and extending into the drift region (100); a first conductive structure (130) and a second conductive structure (140) which fills the trench and are separated from each other, and an oxide layer (120) formed between the first conductive structure (130) and an inner wall of the trench and between the second conductive structure (140) and the inner wall of the trench, the depth of the bottom of the first conductive structure (130) being greater than the depth of the bottom of the second conductive structure (140); a second conductive type extension region (160), formed below the trench and surrounding the bottom of the trench; a source lead structure (310), connected to the source region (111); and a gate lead structure, connected to the second conductive structure (140).

Description

Trench gate metal oxide semiconductor field effect tube and preparation method thereof

Cross-references to related applications

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on May 18, 2020, the application number is 202010418880X, and the invention title is "Trench Gate Metal Oxide Semiconductor Field Effect Transistor and Its Preparation Method", and its entire contents Incorporated in this application by reference.

Technical field

This application relates to the field of semiconductors, and in particular to a trench gate metal oxide semiconductor field effect transistor and a preparation method thereof.

Background technique

The statements here only provide background information related to this application, and do not necessarily constitute prior art.

In MOS (Metal Oxide Semiconductor Field Effect Transistor, MOSFET), a conduction channel is formed between the source and drain. The existence of the conduction channel makes the MOS field effect transistor have a certain conduction. On-resistance, the greater the on-resistance, the greater the power consumption. Therefore, it is necessary to reduce the on-resistance as much as possible. At present, metal oxide semiconductor field effect transistors with a trench gate structure are usually used to form a trench gate structure. The conduction channel is changed from the horizontal to the vertical, which greatly increases the cell density and reduces the on-resistance. However, on the basis of the trench gate metal oxide semiconductor field effect transistor, if you want to further reduce the on-resistance, you need to increase The doping concentration of the drift region, and increasing the doping concentration will weaken the withstand voltage capability of the device. Therefore, due to the limitation of the withstand voltage capability, it becomes difficult to further reduce the on-resistance of the trench gate metal oxide semiconductor field effect transistor. .

Summary of the invention

Based on this, it is necessary to propose a new metal oxide semiconductor field effect transistor and its manufacturing method in view of the current technical problem that the trench gate metal oxide semiconductor field effect transistor is difficult to further reduce the on-resistance.

A trench gate metal oxide semiconductor field effect transistor, including:

The drift region has the first conductivity type and is formed on the semiconductor substrate;

A body region having the second conductivity type and formed in the drift region;

A source region having a first conductivity type and formed in the body region, the source region being provided with a trench penetrating the source region and the body region and extending into the drift region;

The filling structure includes a first conductive structure and a second conductive structure filled in the trench and isolated from each other, and the second conductive structure formed between the first conductive structure and the sidewall of the trench Between the oxide layer and the sidewall of the trench, the bottom depth of the first conductive structure is greater than the bottom depth of the second conductive structure;

An extension area having the second conductivity type, formed under the trench and surrounding the bottom of the trench;

The source lead structure is connected to the source region; and

The gate lead structure is connected to the second conductive structure.

A method for preparing a trench gate metal oxide semiconductor field effect transistor includes:

A semiconductor substrate is provided and a drift region with a first conductivity type is formed on the semiconductor substrate, a trench is opened on the drift region, and an extension with a second conductivity type is formed in the drift region below the trench Area, the expansion area surrounds the bottom of the trench;

An oxide layer is formed on the sidewall of the trench, and a first conductive structure and a second conductive structure isolated from each other are filled in the trench, and the bottom of the first conductive structure is deeper than the bottom of the second conductive structure depth;

Doping the drift region to form a body region with a second conductivity type, the body region is in contact with the sidewall of the trench, and the depth of the body region is less than the depth of the trench;

Doping the body region to form a source region having the first conductivity type, the source region being in contact with the sidewall of the trench; and

A source lead-out structure connected to the source region is formed, and a gate lead-out structure connected to the second conductive structure is formed.

In order to more clearly describe the technical solutions in the embodiments or exemplary technologies of the present application, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments or exemplary technologies. Obviously, the accompanying drawings in the following description are merely These are some embodiments of the present application. For those of ordinary skill in the art, without creative work, the drawings of other embodiments can also be obtained based on these drawings.

Description of the drawings

FIG. 1a is a partial side cross-sectional view of a trench gate metal oxide semiconductor field effect transistor cell region in an embodiment of the application; FIG.

1b is a partial side cross-sectional view of a trench gate metal oxide semiconductor field effect transistor cell region in an embodiment of the application;

2a is a schematic structural view of a trench gate metal oxide semiconductor field effect transistor filling structure in an embodiment of the application;

2b is another structural schematic diagram of the trench gate metal oxide semiconductor field effect transistor filling structure in an embodiment of the application;

FIG. 3 is a flowchart of steps of a method for manufacturing a trench gate metal oxide semiconductor field effect transistor in an embodiment of the application;

4a to 4f are structural cross-sectional views corresponding to relevant steps of a method for manufacturing a trench gate metal oxide semiconductor field effect transistor in an embodiment of the application;

5a to 5d are cross-sectional views of the structure corresponding to the decomposition step of step S310 in an embodiment of the application;

6a to 6d are cross-sectional views of the structure corresponding to the decomposition step of step S310 in another embodiment of the application.

Label description

100 drift region; 101 first epitaxial layer; 102 second epitaxial layer; 110 body region; 111 source region; 112 heavily doped region; 120 oxide layer; 130 first conductive structure; 140 second conductive structure; 150 isolation structure; 160 expansion area; 200 interlayer dielectric layer; 310 source lead structure.

Detailed ways

As shown in conjunction with FIG. 1a, the trench gate metal oxide semiconductor field effect transistor includes a drift region 100 formed on a semiconductor substrate, and the drift region 100 may specifically be formed by epitaxial growth of a semiconductor substrate. A body region 110 is formed on the upper surface of the drift region 100, and an active region 111 is formed on the upper surface of the body region 110.

The source region 111 is provided with a trench that penetrates the source region 111 and the body region 110 and extends into the drift region 100, that is, the bottom end of the trench is located in the drift region 100. The trench is filled with a first conductive structure 130 and a second conductive structure 140 that are isolated from each other, and both the first conductive structure 130 and the second conductive structure 140 can be polysilicon. An oxide layer 120 is formed between the first conductive structure 130 and the sidewall of the trench, and between the second conductive structure 140 and the sidewall of the trench. The oxide layer 120 is formed between the first conductive structure 130 and the sidewall of the trench. The layer is an isolation oxide layer, the oxide layer located between the second conductive structure 140 and the sidewall of the trench is a gate oxide layer, the oxide layer 120 filled in the trench and the first conductive structure 130 and the second conductive structure 130 and the second conductive structure are isolated from each other. The structures 140 collectively constitute a filling structure. In the same trench, the depth of the first conductive structure 130 is greater than the depth of the second conductive structure 140, that is, the distance between the first conductive structure 130 and the bottom of the trench is smaller than the distance between the second conductive structure 140 and the bottom of the trench. An expansion region 160 is also formed in the drift region 100, and the expansion region 160 is located below the trench and surrounds the bottom of the trench.

The trench gate metal oxide semiconductor field effect transistor also includes a source lead-out structure 310 and a gate lead-out structure (not shown in the figure). The source lead-out structure 310 and the gate lead-out structure can be metal pillars, specifically tungsten metal . Wherein, the source lead-out structure 310 is connected to the aforementioned source region 111, and the gate lead-out structure is connected to the second conductive structure 140 in the trench.

The drift region 100 and the source region 111 have the first conductivity type, and the body region 110 and the extension region 160 have the second conductivity type. Wherein, the first conductivity type is N type, and the second conductivity type is P type; or, the first conductivity type is P type, and the second conductivity type is N type. It is understandable that the front side of the trench gate metal oxide semiconductor field effect transistor should also have a source metal layer and a gate metal layer that are isolated from each other. The source extraction structure 310 is connected to the source metal layer. The lead structures are all connected with the gate metal layer, and a drain metal layer is also formed on the back of the trench gate metal oxide semiconductor field effect transistor.

On the one hand, the source region 111 on the top of the trench gate metal oxide semiconductor field effect transistor is connected to the source metal layer through the source extraction structure 310, and the drift region 100 at the bottom is used as the drain region to connect to the drain metal layer. The trench penetrates the body region 110 and extends into the drift region 100. There is an oxide layer 120 and a second conductive structure 140 in the trench. The second conductive structure 140 is connected to the gate metal layer through the gate lead structure, namely the trench and The internal gate oxide layer and the second conductive structure 140 constitute a trench gate structure, and a channel region is formed in the body region 110 in the middle, thereby forming a trench gate metal oxide semiconductor field effect transistor.

On the other hand, a first conductive structure 130 is also formed at the bottom of the trench. An isolation oxide layer is formed between the first conductive structure 130 and the sidewall of the trench. The layers constitute the inner field plate, and the electric field distribution inside the drift region 100 can be adjusted so that the drift region in contact with the inner field plate forms a depletion zone. In addition, an expansion region 160 is also formed in the drift region 100. The expansion region 160 surrounds the bottom of the trench and has a conductivity type opposite to that of the drift region 100. The expansion region 160 and the drift region 100 form a reverse PN junction, so that the drift region in contact with the expansion region 160 It also forms a depletion zone. Therefore, in the present application, there is both an inner field plate depletion region and a PN junction depletion region in the drift region 100. Under the combined action of the inner field plate and the PN junction, the depletion of the drift region 100 is greatly improved. Compared with ordinary trench gate metal oxide semiconductor field effect transistors, the trench gate metal oxide semiconductor field effect transistors in this application have a higher breakdown voltage, that is, when the metal oxide semiconductor field effect transistors are positive When conducting, under the condition of ensuring the same breakdown voltage, the drift region 100 of the trench gate metal oxide semiconductor field effect transistor in the present application can have a higher doping concentration. Therefore, the trench gate in the present application The metal oxide semiconductor field effect transistor also has a lower on-resistance. Secondly, when the device is in reverse withstand voltage, the breakdown position is located at the junction interface between the expansion region 160 and the drift region, and the breakdown is more stable. Third, when the metal oxide semiconductor field effect transistor changes from the on state to the off state, the extended region 160 recombines with the remaining carriers in the drift region 100 to accelerate the switching speed. At the same time, in the trench, the first conductive structure 130 is closer to the bottom of the trench than the second conductive structure 140, so that the parasitic capacitance between the gate and drain can be reduced, and the device has better characteristics.

In one embodiment, as shown in FIG. 1a, an interlayer dielectric layer 200 is also formed on the source region 111 and the trench. The interlayer dielectric layer 200 may specifically be silicon oxide, and the source extraction structure 310 penetrates the interlayer dielectric. The layer 200 and the source region 111 extend into the body region 110 to be connected to the source region 111 and the body region 110. The gate lead structure is formed directly above the trench, which penetrates the interlayer dielectric layer 200 and is connected to the second conductive structure 140 in the trench. Further, the gate lead-out structure and the source lead-out structure are staggered so as to be connected to the gate metal layer and the source metal layer respectively.

In one embodiment, as shown in FIG. 1a, a heavily doped region 112 is also formed in the body region 110. The heavily doped region 112 has the second conductivity type, and the doping concentration of the heavily doped region 112 is higher than that of the body region. The doping concentration of the region 110, the heavily doped region 112 is specifically located below the source region 111 and spaced apart from the trench, the source extraction structure 310 penetrates the source region 111 and extends into the heavily doped region 112, the source extraction structure 310 It is connected to the source region 111, and its bottom is surrounded by the heavily doped region 112, thereby reducing the contact resistance between the source lead-out structure 310 and the body region 110.

In this application, the design of the first conductive structure 130 has various forms. The first conductive structure 130 may be an uncharged floating structure, or may be electrically connected to the source to obtain the source potential. In one embodiment, outside the cell area, the first conductive structure 130 is drawn from the end of the trench, that is, at the end of the trench, the first conductive structure 130 extends to the top of the trench, and is connected to the trench through a source connection structure. The source electrode is electrically connected to obtain the source electrode potential, thereby enhancing the ability of the inner field plate to adjust the electric field. In another embodiment, the first conductive structure 130 is a floating structure, the first conductive structure 130 is drawn from the end of the trench, the first conductive structure 130 is not in contact with the source connection structure, and there is a certain thickness between the two However, the first conductive structure 130 can obtain the induced potential of the source to charge the first conductive structure 130, and since it is electrically connected to the source through induction, it can cut off the source, The leakage path of the first conductive structure avoids source leakage. In another embodiment, the first conductive structure 130 is a floating structure, the first conductive structure 130 is not drawn from the trench, and is not electrically connected to the source, and cannot obtain the potential of the source. Therefore, the first conductive structure 130 is not charged.

In this application, the design of the oxide layer in the trench also has various forms. In one embodiment, as shown in FIG. 1a, the sidewall and bottom wall of the trench are both formed with an oxide layer 120, that is, an oxide layer 120 is formed on the inner wall of the trench, so that the first conductive structure 130 is separated from the expansion region 160. At this time, no matter whether the first conductive structure 130 is charged or not, the expansion region 120 is not charged, thereby avoiding current leakage. In another embodiment, as shown in FIG. 1b, the oxide layer 120 is formed only on the sidewall of the trench, and no oxide layer is formed at the bottom of the trench, so that the first conductive structure 130 is in contact with the extension region 160, and the extension region 160 It has the same charging condition as the first conductive structure 130.

The distribution of the first conductive structure 130 and the second conductive structure 140 of the trench 120 has various designs. In one embodiment, as shown in FIG. 1a, in the trench, the first conductive structure 130 is distributed at the bottom of the trench, the second conductive structure 140 is distributed at the top of the trench, and the first conductive structure 130 and the second conductive structure 130 are distributed on the top of the trench. The conductive structures 140 are isolated by the isolation structure 150, wherein an oxide layer 120 is formed between the first conductive structure 130 and the inner wall of the trench and between the second conductive structure 140 and the inner wall of the trench. Specifically, the isolation structure 150 is silicon oxide. In this embodiment, the first conductive structure 130 at the bottom of the trench can not only adjust the electric field of the drift region, enhance the depletion of the drift region, but also reduce the parasitic capacitance between the gate and drain, and improve the performance of the device. Further, as shown in FIG. 1a, in the trench, the top surface of the first conductive structure 130 and the bottom surface of the second conductive structure 140 are approximately flat surfaces. In another embodiment, as shown in FIG. 2a, in the trench, the middle part of the top surface of the first conductive structure 130 is convex outward, and the middle part of the bottom surface of the second conductive structure 140 is concave inward, so as to interact with the first conductive structure. The protrusion of 130 adapts.

In one embodiment, as shown in FIG. 2b, in the trench, the first conductive structure 130 extends from the top of the trench to the bottom of the trench, and an oxide layer 120 is formed between the first conductive structure 130 and the inner wall of the trench. The second conductive structure 140 is formed in the oxide layer 120 on both sides of the first conductive structure 130, the first conductive structure 130 and the second conductive structure 140 are separated by the oxide layer 120, and the first conductive structure 130 extends to the depth of the trench bottom It is greater than the depth of the second conductive structure 140 extending toward the bottom of the trench. In this embodiment, the second conductive structure 140 is provided in the oxide layer 120 to increase the thickness of the oxide layer 120, thereby enhancing the withstand voltage of the device.

This application also relates to a method for manufacturing a trench gate metal oxide semiconductor field effect transistor. As shown in FIG. 3, the manufacturing method includes the following steps:

Step S310: Provide a semiconductor substrate and form a drift region with a first conductivity type on the semiconductor substrate, open a trench on the drift region, and form an extension region with a second conductivity type below the trench , The expansion area surrounds the bottom of the trench.

Specifically, step S310 can be implemented in the first implementation manner:

Step S311: forming a drift region with the first conductivity type on the semiconductor substrate, and opening a trench on the drift region.

Step S312: implanting dopant ions having the second conductivity type into the drift region under the trench through the trench to form the extension region.

As shown in FIG. 4a, the drift region 100 is formed by doping the semiconductor substrate with the first conductivity type. Specifically, the epitaxial layer on the semiconductor substrate may be doped to form the drift region 100 on the epitaxial layer. Through photolithography and etching processes, trenches are formed in the drift region 100. As shown in FIG. 4b, through the ion implantation process, dopant ions having the second conductivity type are implanted into the drift region below the trench through the trench to form an expansion region 160 that surrounds the bottom of the trench.

Specifically, step S310 can also be implemented in the second implementation manner:

Step S313: epitaxially grow a first epitaxial layer on the semiconductor substrate.

Step S314: Doping the first epitaxial layer to form the extension region having the second conductivity type.

Step S315: continue to epitaxially grow a second epitaxial layer on the first epitaxial layer and the expansion region, and the drift region includes the first epitaxial layer and the second epitaxial layer.

Step S316: etching the second epitaxial layer above the expansion area to form the trench, and the bottom of the trench extends into the expansion area.

As shown in FIGS. 5a to 5d, a first epitaxial layer 101 is epitaxially grown on a semiconductor substrate, the first epitaxial layer 101 is doped to form an expansion region 160, and the first epitaxial layer 101 and the expansion region 160 are continuously epitaxially grown on the first epitaxial layer 101 and the expansion region 160. The two epitaxial layers 102, the first epitaxial layer 101 and the second epitaxial layer 102 constitute the drift region 100, and the expansion region 160 is located in the drift region 100. The drift region above the expansion region 160 is etched by photolithography and etching processes to form a trench extending into the expansion region 160.

Specifically, step S310 can also be implemented in a third implementation manner:

Step S317: forming a drift region having the first conductivity type on the semiconductor substrate, and opening a deep groove on the drift region.

Step S318: filling the deep groove to form a filling area with the second conductivity type.

Step S319: Etching a part of the filling area at the top of the deep groove, leaving the filling area at the bottom of the deep groove, the remaining filling area being the expansion area, and the deep groove located above the expansion area being the Groove.

As shown in FIGS. 6a to 6d, a drift region 100 is formed on a semiconductor substrate, a deep groove is opened on the drift region 100 through photolithography and etching processes, and the deep groove is filled to form a filling part, and the etching is located at the upper end of the deep groove Part of the filling area of the deep groove is reserved for the filling area at the bottom of the deep groove, and the reserved filling area is the expansion area 160, and the deep groove located above the expansion area 160 is the above-mentioned groove.

Step S320: An oxide layer is formed on the sidewall of the trench, and the first conductive structure and the second conductive structure isolated from each other are filled in the trench, and the bottom depth of the first conductive structure is greater than that of the second conductive structure. The depth of the bottom of the conductive structure.

After step S310, the trench is filled with a filling structure. Since the structures of the first conductive structure 130 and the second conductive structure 140 in the trench have various forms, correspondingly, the step of forming the first conductive structure 130 and the second conductive structure 140 in the trench also has various embodiments. In a specific embodiment, step S320 may include the following steps:

Step S321: forming an oxide layer on the sidewall of the trench.

Step S322: Fill the trench with a first conductive structure.

Step S323: etch the first conductive structure and the oxide layer on the top of the trench, and retain the first conductive structure and the oxide layer at the bottom of the trench.

Step S324: forming an isolation structure in the trench, the isolation structure covering the first conductive structure at the bottom of the trench and not filling the trench.

Step S325: forming an oxide layer on the sidewall of the trench above the isolation structure and filling the trench with a second conductive structure.

Wherein, in step S321, an oxide layer is formed on the sidewall of the trench, which is divided into two embodiments:

The first embodiment: an oxide layer is formed on the inner wall of the trench. As shown in FIG. 4c, an oxide layer 120 is formed on the inner wall of the trench. Specifically, the oxide layer 120 may be formed by thermal oxidation.

The second embodiment: an oxide layer is formed on the inner wall of the trench, the oxide layer at the bottom of the trench is etched, the oxide layer on the sidewall of the trench is retained, and the expansion area is exposed through the trench.

After the oxide layer is formed, the trench is filled with the first conductive structure. Specifically, the above-mentioned first conductive structure can be formed by a deposition process. The first conductive structure and the oxide layer on the top of the trench are etched, and the first conductive structure 130 at the bottom of the trench and the oxide layer 120 between the first conductive structure 130 and the sidewall of the trench are retained. As shown in FIG. 4d, through a deposition process, a layer of isolation structure 150 is deposited in the trench. The isolation structure 150 may specifically be silicon oxide. The isolation structure 150 covers the first conductive structure 130 and does not fill the trench. . An oxide layer is formed on the sidewall of the trench above the isolation structure 150 and the second conductive structure 140 is filled in the trench. The second conductive structure 140 is isolated from the inner wall of the trench by the oxide layer 120, and the second conductive structure 140 passes through The isolation structure 150 is isolated from the first conductive structure 130. In the filling structure formed through the above steps S321 to S325, the first conductive structure 130 and the oxide layer 120 at the bottom of the trench constitute an internal field plate structure.

Step S330: Doping the drift region to form a body region with a second conductivity type, the body region is in contact with the sidewall of the trench, and the depth of the body region is less than the depth of the trench, The body region is doped to form a source region having the first conductivity type, and the source region is in contact with the sidewall of the trench.

As shown in FIG. 4e, the upper surface layer of the drift region 100 is doped to form a body region 110 of the second conductivity type in contact with the sidewall of the trench. The depth of the body region 110 is less than the depth of the trench, that is, the depth of the trench The bottom is still located in the drift zone 100. In an embodiment, specifically, the upper surface layer of the drift region 100 is doped to form the body region 110 through a high-temperature well push process, wherein the temperature and time of the high-temperature push well can be adjusted according to the doping depth and doping concentration of the body region. Specifically, the temperature range of the high-temperature trap can be controlled between 900°C and 1200°C, and the time range of the high-temperature trap can be controlled between 10min and 180min. In the high temperature environment of the high temperature pushing process, the expansion zone 160 will also diffuse to increase the extent of the expansion zone. As shown in FIG. 4f, after the body region 110 is formed, the body region 110 is doped to form a source region 111 in contact with the sidewall of the trench.

Step S340: forming a source lead-out structure connected to the source region, and forming a gate lead-out structure connected to the second conductive structure.

As shown in FIG. 4f, a source lead-out structure 310 connected to the source region 111 is formed, and a gate lead-out structure (not shown in the figure) connected to the second conductive structure 140 is formed. In an embodiment, between step S330 and step S340, it further includes forming an interlayer dielectric layer 200 on the source region 111 and the trench. Specifically, the process of forming the source extraction structure is: sequentially etching the interlayer dielectric layer 200, the source region 111 and the body region 110 on both sides of the trench to form a source contact hole, the source contact hole being spaced apart from the trench, The source contact hole is filled with conductive material to form a source lead-out structure; in the same way, the process of forming a gate lead-out structure is: etching the interlayer dielectric layer 200 above the trench to form a gate contact hole, the gate contact hole is directly opposite The trench extends into the second conductive structure 140 in the trench, and the gate contact hole is filled with a conductive material to form a gate lead structure. In one embodiment, after the source contact hole is formed and before the conductive material is filled in the source contact hole, the method further includes implanting dopant ions having the second conductivity type through the source contact hole to form a heavily doped region on the surface of the body region. In step 112, after the source lead-out structure is formed, the bottom of the source lead-out structure 310 is surrounded by the heavily doped region 112, which can reduce the contact resistance between the source lead-out structure 310 and the body region.

The above examples only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the invention patent. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can be made, and these all fall within the protection scope of this application. Therefore, the scope of protection of the patent of this application shall be subject to the appended claims.

Claims

A trench gate metal oxide semiconductor field effect transistor, including:

The drift region has the first conductivity type and is formed on the semiconductor substrate;

A body region having the second conductivity type and formed in the drift region;

The source region has the first conductivity type and is formed in the body region;

A trench that penetrates the source region and the body region in sequence and extends into the drift region;

The filling structure includes a first conductive structure and a second conductive structure filled in the trench and isolated from each other, and the second conductive structure formed between the first conductive structure and the sidewall of the trench Between the oxide layer and the sidewall of the trench, the bottom depth of the first conductive structure is greater than the bottom depth of the second conductive structure;

An extension region, having the second conductivity type, formed in the drift region below the trench and surrounding the bottom of the trench;

The source lead structure is connected to the source region; and

The gate lead structure is connected to the second conductive structure.
The metal oxide semiconductor field effect transistor of claim 1, wherein a heavily doped region having a second conductivity type is formed in the body region, and the doping concentration of the heavily doped region is higher than that of the heavily doped region. The doping concentration of the body region, the heavily doped region is located below the source region and spaced apart from the trench, and the source extraction structure penetrates the source region and extends to the heavily doped region Inside.
3. The metal oxide semiconductor field effect transistor of claim 1, wherein the first conductive structure is an uncharged floating structure.
3. The metal oxide semiconductor field effect transistor of claim 1, wherein the first conductive structure is drawn from an end of the trench and is electrically connected to the source lead structure.
3. The metal oxide semiconductor field effect transistor of claim 1, wherein an oxide layer is not formed on the bottom wall of the trench, and the expansion region is in contact with the first conductive structure.
3. The metal oxide semiconductor field effect transistor of claim 1, wherein an oxide layer is formed on the inner wall of the trench, and the expansion area is isolated from the first conductive structure by the oxide layer.
The metal oxide semiconductor field effect transistor of claim 1, further comprising an interlayer dielectric layer, and the source extraction structure penetrates the interlayer dielectric layer and the source region, and extends to the body The gate extraction structure is formed directly above the trench, and the gate extraction structure penetrates the interlayer dielectric layer and is connected to the trench The second conductive structure in the groove is connected.
The metal oxide semiconductor field effect transistor of claim 1, wherein the first conductive structure is formed at the bottom of the trench, and the second conductive structure is formed at the top of the trench, so An isolation structure for isolating the first conductive structure and the second conductive structure is formed between the first conductive structure and the second conductive structure.
7. The metal oxide semiconductor field effect transistor of claim 1, wherein the first conductive structure extends from the top of the trench to the bottom of the trench, and the first conductive structure and the trench The oxide layer is formed between the sidewalls, and the second conductive structure is formed in the oxide layer on both sides of the first conductive structure.
3. The metal oxide semiconductor field effect transistor of claim 1, wherein the first conductivity type is N type, and the second conductivity type is P type.
A method for preparing a trench gate metal oxide semiconductor field effect transistor includes:

A semiconductor substrate is provided and a drift region with a first conductivity type is formed on the semiconductor substrate, a trench is opened on the drift region, and an extension with a second conductivity type is formed in the drift region below the trench Area, the expansion area surrounds the bottom of the trench;

An oxide layer is formed on the sidewall of the trench, and a first conductive structure and a second conductive structure isolated from each other are filled in the trench, and the bottom of the first conductive structure is deeper than the bottom of the second conductive structure depth;

Doping the drift region to form a body region with a second conductivity type, the body region is in contact with the sidewall of the trench, and the depth of the body region is less than the depth of the trench;

Doping the body region to form a source region having the first conductivity type, the source region being in contact with the sidewall of the trench; and

A source lead-out structure connected to the source region is formed, and a gate lead-out structure connected to the second conductive structure is formed.
The manufacturing method according to claim 11, wherein the drift region having the first conductivity type is formed on the semiconductor substrate, a trench is opened on the drift region, and the The step of forming an extension region with the second conductivity type in the drift region includes:

Forming a drift region having the first conductivity type on the semiconductor substrate, and opening a trench on the drift region; and

Doping ions with the second conductivity type are implanted into the drift region below the trench through the trench to form the extension region.
The manufacturing method according to claim 11, wherein the drift region having the first conductivity type is formed on the semiconductor substrate, a trench is opened on the drift region, and the The step of forming an extension region with the second conductivity type in the drift region includes:

Epitaxially growing a first epitaxial layer on the semiconductor substrate;

Doping the first epitaxial layer to form the extension region having the second conductivity type;

Continue to epitaxially grow a second epitaxial layer on the first epitaxial layer and the expansion region, and the drift region includes the first epitaxial layer and the second epitaxial layer; and

The second epitaxial layer above the expansion area is etched to form the trench, and the bottom of the trench extends into the expansion area.
The manufacturing method according to claim 11, wherein the drift region having the first conductivity type is formed on the semiconductor substrate, a trench is opened on the drift region, and the The step of forming an extension region with the second conductivity type in the drift region includes:

Forming a drift region of the first conductivity type on the semiconductor substrate, and opening a deep groove on the drift region;

Filling the deep groove to form a filling area having the second conductivity type; and

A part of the filling area at the top end of the deep groove is etched, the filling area at the bottom of the deep groove is reserved, the remaining filling area is the expansion area, and the deep groove located above the expansion area is the groove.
The preparation method of claim 11, wherein the oxide layer is formed on the sidewalls of the trench, and the trenches are filled with the first conductive structure and the second conductive structure isolated from each other. The steps include:

Forming the oxide layer on the sidewall of the trench;

Filling the trench with a first conductive structure;

Etching the first conductive structure and the oxide layer at the top of the trench, leaving the first conductive structure and the oxide layer at the bottom of the trench;

Forming an isolation structure in the trench, the isolation structure covering the first conductive structure at the bottom of the trench and not filling the trench;

An oxide layer is formed on the sidewall of the trench above the isolation structure, and a second conductive structure is filled into the trench.