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WO2021223353A1 - 半导体超结器件的制造方法 - Google Patents

半导体超结器件的制造方法 Download PDF

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Publication number
WO2021223353A1
WO2021223353A1 PCT/CN2020/116682 CN2020116682W WO2021223353A1 WO 2021223353 A1 WO2021223353 A1 WO 2021223353A1 CN 2020116682 W CN2020116682 W CN 2020116682W WO 2021223353 A1 WO2021223353 A1 WO 2021223353A1
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Prior art keywords
type
trench
layer
manufacturing
hard mask
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PCT/CN2020/116682
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English (en)
French (fr)
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刘伟
袁愿林
徐真逸
龚轶
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苏州东微半导体股份有限公司
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Application filed by 苏州东微半导体股份有限公司 filed Critical 苏州东微半导体股份有限公司
Priority to JP2021551602A priority Critical patent/JP7175449B2/ja
Priority to US17/440,078 priority patent/US11626480B2/en
Priority to KR1020217042878A priority patent/KR102518360B1/ko
Priority to DE112020003067.9T priority patent/DE112020003067B4/de
Publication of WO2021223353A1 publication Critical patent/WO2021223353A1/zh

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present disclosure relates to the technical field of semiconductor super junction devices, for example, to a method of manufacturing a semiconductor super junction device.
  • semiconductor super-junction devices are based on charge balancing technology, which can reduce on-resistance and parasitic capacitance, so that semiconductor super-junction devices have extremely fast switching characteristics, can reduce switching losses, and achieve higher power conversion efficiency.
  • the main manufacturing process of the related art semiconductor superjunction device includes: first, as shown in FIG. 1, a hard mask layer 11 is formed on the n-type epitaxial layer 10, and then photolithography and etching are performed, in the hard mask layer 11 An opening is formed and a trench 12 is formed in the n-type epitaxial layer 10; next, as shown in FIG. 2, a p-type pillar 13 is formed in the formed trench by an epitaxial process and planarized, after which, as shown in FIG.
  • the gate dielectric layer 14 and the gate electrode 15 are formed through a photolithography process and an etching process, and finally a p-type body region 16 and an n-type source located in the p-type body region 16 are formed in the n-type epitaxial layer 10.
  • District 17. In the related art, whether it is a planar or trench semiconductor super-junction device, a photolithography process is required when forming a p-type pillar, and then a photolithography process is required when forming a gate. The cost of the process is expensive, and there is a risk of alignment deviation, which leads to higher manufacturing costs and manufacturing risks of semiconductor super junction devices.
  • the present disclosure provides a method for manufacturing a semiconductor super junction device to reduce the manufacturing cost of the semiconductor super junction device and reduce the manufacturing risk of the semiconductor super junction device.
  • the present disclosure provides a method for manufacturing a semiconductor super junction device, including:
  • a hard mask layer is formed on the n-type epitaxial layer, the position of the p-type pillar is defined by a photolithography process, and then the hard mask layer is etched to form at least one opening in the hard mask layer, the opening and The position of the p-type column corresponds;
  • the n-type epitaxial layer is etched using the hard mask layer as a mask, and a first trench is formed in the n-type epitaxial layer.
  • the width of the first trench is greater than the width of the corresponding opening, so
  • the first trench includes a p-type pillar region located below the corresponding opening and a gate region located on both sides of the p-type pillar region;
  • the n-type epitaxial layer is etched to form a second trench in the n-type epitaxial layer, and the second trench is located in the corresponding Below the p-type column area;
  • the hard mask layer and the sacrificial dielectric layer are removed, and a gate dielectric layer and a gate are formed in the gate region of the first trench.
  • the manufacturing method of the semiconductor super junction device further includes:
  • An n-type source region is formed in the p-type body region.
  • the hard mask layer is a stack of silicon oxide layer-silicon nitride layer-silicon oxide layer.
  • an etching method combining anisotropic etching and isotropic etching is used.
  • the material of the sacrificial dielectric layer is silicon oxide.
  • the width of the second trench is greater than the width of the region corresponding to the p-type pillar.
  • the second trench is formed by etching
  • an etching method combining anisotropic etching and isotropic etching is used.
  • the p-type pillar before forming the p-type pillar, perform a p-type ion implantation to form a p-type compensation in the n-type epitaxial layer under the second trench or under and on both sides of the second trench Area.
  • the material of the p-type pillar is p-type polysilicon.
  • the method for manufacturing a semiconductor super junction device provided in the present disclosure can form a gate in self-alignment after forming a p-type pillar. Therefore, only one photolithography process is required to form the gate and p-type pillar, which can greatly Reduce the manufacturing cost of semiconductor super junction devices, and reduce the manufacturing risk of semiconductor super junction devices.
  • 1 to 3 are schematic cross-sectional structure diagrams of main structures in a manufacturing process of a semiconductor super junction device in the related art
  • 4 to 11 are schematic cross-sectional structure diagrams of main structures in a manufacturing process of an embodiment of a method for manufacturing a semiconductor super junction device provided by the present disclosure.
  • 4 to 11 are schematic cross-sectional structure diagrams of main structures in a manufacturing process of an embodiment of a method for manufacturing a semiconductor super junction device provided by the present disclosure.
  • a hard mask layer 30 is formed on the n-type epitaxial layer 20 provided.
  • the n-type epitaxial layer 20 is usually silicon
  • the hard mask layer 30 is usually a silicon oxide layer-a silicon nitride layer- Stack of silicon oxide layers.
  • the position of the p-type pillar is defined by a photolithography process, and then the hard mask layer 30 is etched to form at least one opening 31 in the hard mask layer 30.
  • the opening 31 corresponds to the position of the p-type pillar.
  • the number of openings 31 in 30 (that is, the number of p-type pillars) is determined by the specifications of the designed semiconductor superjunction device, and only two openings 31 are exemplarily shown in the embodiment of the present invention.
  • the n-type epitaxial layer 20 is etched using the hard mask layer 30 as a mask, and a first trench 32 is formed in the n-type epitaxial layer 20.
  • the first trench 32 and the hard mask The openings in the film layer 30 correspond one-to-one, and the first trench 32 includes a p-type pillar region 32a located below the corresponding opening and a gate region 32b located on both sides of the p-type pillar region 32a.
  • a combination of anisotropic etching and isotropic etching is selected. For example, an anisotropic etching method is first used to form the p-type pillar region 32a of the first trench 32. Then, an isotropic etching method is used to form the gate region 32b of the first trench 32.
  • a sacrificial dielectric layer 40 is formed in the gate region of the first trench, and the sacrificial dielectric layer 40 is usually silicon oxide.
  • the steps may include: first depositing or oxidizing to form a layer of silicon oxide, and then performing back etching on the deposited silicon oxide.
  • the silicon oxide may fill the entire first trench, or the silicon oxide may not fill the entire first trench, but the silicon oxide should fill the gate area of the first trench.
  • the n-type epitaxial layer 20 is etched using the hard mask layer 30 and the sacrificial dielectric layer 40 as a mask, and a second trench located below the first trench is formed in the n-type epitaxial layer 20. ⁇ 34 ⁇ Groove 34.
  • the width of the second trench 34 may be greater than the width of the corresponding p-type pillar region.
  • anisotropic etching and various An etching method combined with isotropic etching for example, an anisotropic etching method may be used for etching first, and then an isotropic etching method may be used for etching, so as to increase the second trench
  • the width of 34 reduces the width of the n-type epitaxial layer between adjacent second trenches 34.
  • p-type pillars 23 are formed in the p-type pillar region and the second trench, and the hard mask layer and the sacrificial dielectric layer are removed.
  • a pn junction structure is formed between the p-type pillar 23 and the n-type epitaxial layer 20.
  • the material of the p-type pillar 23 may be p-type polysilicon, which is usually formed by an epitaxial process.
  • a p-type ion implantation may be performed first to form a p-type compensation region in the n-type epitaxial layer under the second trench or under and on both sides of the second trench. Achieve better charge balance effect.
  • a gate dielectric layer 21 and a gate 22 are formed in the gate region of the first trench, and the gate 22 is isolated from the p-type pillar 23 by the gate dielectric layer 21.
  • a p-type body region 24 is formed in the n-type epitaxial layer 20, and an n-type source region 25 is formed in the p-type body region 24.
  • structures such as the interlayer dielectric layer and the metal layer are formed according to the conventional process to obtain the semiconductor super junction device.

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Abstract

一种半导体超结器件的制造方法，包括：在n型外延层（20）上形成硬掩膜层（30），在所述硬掩膜层内形成至少一个开口（31），所述开口与所述p型柱（23）的位置对应；以所述硬掩膜层为掩膜刻蚀所述n型外延层，在所述n型外延层内形成第一沟槽（32），所述第一沟槽的宽度大于对应所述开口的宽度；在所述第一沟槽内形成牺牲介质层（40）；以所述硬掩膜层和所述牺牲介质层为掩膜，对所述n型外延层进行刻蚀，在所述n型外延层内形成第二沟槽（34）；在所述p型柱区域和所述第二沟槽内形成p型柱；去除掉所述硬掩膜层和所述牺牲介质层，在所述第一沟槽的栅极区域内形成栅介质层（21）和栅极（22）。

Description

半导体超结器件的制造方法
本申请要求在2020年05月06日提交中国专利局、申请号为202010372056.5的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本公开涉及半导体超结器件技术领域，例如涉及一种半导体超结器件的制造方法。
背景技术
半导体超结器件基于电荷平衡技术，可以降低导通电阻和寄生电容，使得半导体超结器件具有极快的开关特性，可以降低开关损耗，实现更高的功率转换效率。相关技术的半导体超结器件的主要制造工艺包括：首先，如图1所示，在n型外延层10上形成硬掩膜层11，然后进行光刻和刻蚀，在硬掩膜层11中形成开口并在n型外延层10内形成沟槽12；接下来，如图2所示，通过外延工艺在所形成的沟槽内形成p型柱13，并进行平坦化处理，之后，如图3所示，再通过一次光刻工艺和刻蚀工艺形成栅介质层14和栅极15，最后在n型外延层10内形成p型体区16和位于p型体区16内的n型源区17。相关技术中，不论是平面型还是沟槽型的半导体超结器件，在形成p型柱时需要进行一次光刻工艺，然后在形成栅极时，还需要再进行一次光刻工艺，由于光刻工艺的成本昂贵，而且存在对准偏差的风险，导致半导体超结器件的制造成本和制造风险较高。
发明内容
本公开提供了一种半导体超结器件的制造方法，以降低半导体超结器件的制造成本并降低半导体超结器件的制造风险。
本公开提供了一种半导体超结器件的制造方法，包括：
在n型外延层上形成硬掩膜层，通过光刻工艺定义p型柱的位置，然后刻蚀所述硬掩膜层，在所述硬掩膜层内形成至少一个开口，所述开口与所述p型柱的位置对应；
以所述硬掩膜层为掩膜刻蚀所述n型外延层，在所述n型外延层内形成第一沟槽，所述第一沟槽的宽度大于对应所述开口的宽度，所述第一沟槽包括位于对应所述开口下方的p型柱区域和位于所述p型柱区域两侧的栅极区域；
在所述第一沟槽的栅极区域内形成牺牲介质层；
以所述硬掩膜层和所述牺牲介质层为掩膜，对所述n型外延层进行刻蚀，在所述n型外延层内形成第二沟槽，所述第二沟槽位于对应所述p型柱区域的下方；
在所述p型柱区域和所述第二沟槽内形成p型柱，所述p型柱与所述n型外延层之间形成pn结结构；
去除掉所述硬掩膜层和所述牺牲介质层，在所述第一沟槽的栅极区域内形成栅介质层和栅极。
可选的，所述半导体超结器件的制造方法还包括：
在所述n型外延层内形成p型体区；
在所述p型体区内形成n型源区。
可选的，所述硬掩膜层为氧化硅层-氮化硅层-氧化硅层的叠层。
可选的，在刻蚀形成所述第一沟槽时，采用各向异性刻蚀和各向同性刻蚀相结合的刻蚀方法。
可选的，所述牺牲介质层的材料为氧化硅。
可选的，所述第二沟槽的宽度大于对应所述p型柱区域的宽度。
可选的，在刻蚀形成所述第二沟槽时，采用各向异性刻蚀和各向同性刻蚀相结合的刻蚀方法。
可选的，在形成p型柱之前，进行一次p型离子注入，以在所述第二沟槽下方或者所述第二沟槽下方及两侧的所述n型外延层内形成p型补偿区。
可选的，所述p型柱的材料为p型多晶硅。
本公开提供的半导体超结器件的制造方法，在形成p型柱后，可以自对准的形成栅极，因此形成栅极和p型柱时只需要进行一次光刻工艺，这可以极大的降低半导体超结器件的制造成本，并降低半导体超结器件的制造风险。
附图说明
图1至图3是相关技术的半导体超结器件的制造工艺中的主要结构的剖面结构示意图；
图4至图11是本公开提供的半导体超结器件的制造方法的一个实施例的制造工艺中的主要结构的剖面结构示意图。
具体实施方式
以下将结合本发明实施例中的附图，通过具体方式，描述本公开的技术方案。本公开所使用的诸如“具有”、“包含”以及“包括”等术语并不排除一个或多个其它元件或其组合的存在或添加。同时，为说明本公开的具体实施方式，附图中所列示意图，放大了本公开所述的层和区域的厚度，且所列图形大小并不代表实际尺寸。
图4至图11是本公开提供的半导体超结器件的制造方法的一个实施例的制造工艺中的主要结构的剖面结构示意图。
首先，如图4所示，在提供的n型外延层20之上形成硬掩膜层30，n型外延层20通常为硅，硬掩膜层30通常为氧化硅层-氮化硅层-氧化硅层的叠层。通过光刻工艺定义出p型柱的位置，然后对硬掩膜层30进行刻蚀，在硬掩膜层30中形成至少一个开口31，开口31与p型柱的位置对应，硬掩膜层30中的开口31的数量(即p型柱的数量)由所设计的半导体超结器件的规格确定，本发明实施例中仅示例性的示出了两个开口31。
接下来，如图5所示，以硬掩膜层30为掩膜对n型外延层20进行刻蚀，在n型外延层20内形成第一沟槽32，第一沟槽32与硬掩膜层30中的开口一一对应，第一沟槽32包括位于对应开口下方的p型柱区域32a以及位于p型柱区域32a两侧的栅极区域32b。在刻蚀形成第一沟槽32时，选用各向异性刻蚀和各向同性刻蚀相结合的方法，比如先采用各项异性刻蚀的方法形成第一沟槽32的p型柱区域32a，再采用各向同性刻蚀的方法形成第一沟槽32的栅极区域32b。
接下来，如图6所示，在第一沟槽的栅极区域内形成牺牲介质层40，牺牲介质层40通常为氧化硅。步骤可以包括：先淀积或氧化形成一层氧化硅，然后对所淀积的氧化硅进行回刻。在淀积形氧化硅时，可以使氧化硅填满整个第一沟槽，也可以使氧化硅不填满整个第一沟槽，但氧化硅应填满第一沟槽的栅极区域。
接下来，如图7所示，以硬掩膜层30和牺牲介质层40为掩膜对n型外延层20进行刻蚀，在n型外延层20内形成位于第一沟槽下方的第二沟槽34。可选的，如图8所示，第二沟槽34的宽度可以大于对应p型柱区域的宽度，对应的，在刻蚀形成第二沟槽34时，可以采用各向异性刻蚀和各向同性刻蚀相结合的刻蚀方法，示例性的，可以先采用各向异性刻蚀的方法进行刻蚀，再采用各向同性刻蚀的方法进行刻蚀，以此来增加第二沟槽34的宽度，也就减小了相邻的第二沟槽34之间的n型外延层的宽度。
接下来，如图9所示，在p型柱区域和第二沟槽内形成p型柱23，并去除 掉硬掩膜层和牺牲介质层。p型柱23与n型外延层20之间形成pn结结构，p型柱23的材料可以为p型多晶硅，通常通过外延工艺形成。可选的，在形成p型柱23前，可以先进行一次p型离子注入，以在第二沟槽下方或者第二沟槽下方及两侧的n型外延层内形成p型补偿区，以达到更优的电荷平衡效果。
接下来，如图10所示，在第一沟槽的栅极区域内形成栅介质层21和栅极22，栅极22通过栅介质层21与p型柱23隔离。
接下来，如图11所示，在n型外延层20内形成p型体区24，并在p型体区24内形成n型源区25。
之后按照常规工艺形成层间介质层、金属层等结构即可得到半导体超结器件。

Claims (9)

  1. 半导体超结器件的制造方法，包括：
    在n型外延层上形成硬掩膜层，通过光刻工艺定义p型柱的位置，然后刻蚀所述硬掩膜层，在所述硬掩膜层内形成至少一个开口，所述开口与所述p型柱的位置对应；
    以所述硬掩膜层为掩膜刻蚀所述n型外延层，在所述n型外延层内形成第一沟槽，所述第一沟槽的宽度大于对应所述开口的宽度，所述第一沟槽包括位于对应所述开口下方的p型柱区域和位于所述p型柱区域两侧的栅极区域；
    在所述第一沟槽的栅极区域内形成牺牲介质层；
    以所述硬掩膜层和所述牺牲介质层为掩膜，对所述n型外延层进行刻蚀，在所述n型外延层内形成第二沟槽，所述第二沟槽位于对应所述p型柱区域的下方；
    在所述p型柱区域和所述第二沟槽内形成p型柱，所述p型柱与所述n型外延层之间形成pn结结构；
    去除掉所述硬掩膜层和所述牺牲介质层，在所述第一沟槽的栅极区域内形成栅介质层和栅极。
  2. 如权利要求1所述的半导体超结器件的制造方法，还包括：
    在所述n型外延层内形成p型体区；
    在所述p型体区内形成n型源区。
  3. 如权利要求1所述的半导体超结器件的制造方法，其中，所述硬掩膜层为氧化硅层-氮化硅层-氧化硅层的叠层。
  4. 如权利要求1所述的半导体超结器件的制造方法，其中，在刻蚀形成所述第一沟槽时，采用各向异性刻蚀和各向同性刻蚀相结合的刻蚀方法。
  5. 如权利要求1所述的半导体超结器件的制造方法，其中，所述牺牲介质层的材料为氧化硅。
  6. 如权利要求1所述的半导体超结器件的制造方法，其中，所述第二沟槽的宽度大于对应所述p型柱区域的宽度。
  7. 如权利要求6所述的半导体超结器件的制造方法，其中，在刻蚀形成所述第二沟槽时，采用各向异性刻蚀和各向同性刻蚀相结合的刻蚀方法。
  8. 如权利要求1所述的半导体超结器件的制造方法，在形成所述p型柱之前，还包括：
    进行一次p型离子注入，以在所述第二沟槽下方或者所述第二沟槽下方及 两侧的所述n型外延层内形成p型补偿区。
  9. 如权利要求1所述的半导体超结器件的制造方法，其中，所述p型柱的材料为p型多晶硅。
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