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WO2021259361A1 - 薄膜晶体管及其制备方法、阵列基板、显示面板 - Google Patents

薄膜晶体管及其制备方法、阵列基板、显示面板 Download PDF

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Publication number
WO2021259361A1
WO2021259361A1 PCT/CN2021/102108 CN2021102108W WO2021259361A1 WO 2021259361 A1 WO2021259361 A1 WO 2021259361A1 CN 2021102108 W CN2021102108 W CN 2021102108W WO 2021259361 A1 WO2021259361 A1 WO 2021259361A1
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Prior art keywords
substrate
film transistor
guide
guiding
semiconductor
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PCT/CN2021/102108
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English (en)
French (fr)
Inventor
贺家煜
宁策
李正亮
胡合合
黄杰
姚念琦
赵坤
刘雪
王治
关峰
Original Assignee
京东方科技集团股份有限公司
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Priority to US17/772,689 priority Critical patent/US20230036385A1/en
Publication of WO2021259361A1 publication Critical patent/WO2021259361A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present disclosure belongs to the technical field of thin film transistor devices, and in particular relates to a thin film transistor, a method for preparing the thin film transistor, an array substrate, and a display panel.
  • Thin Film Transistors can be used in various electronic devices, such as display panels. Thin Film Transistors can be used to drive light-emitting devices in the display panel, or as a switch unit of the light-emitting devices.
  • the important indicators of thin film transistors include mobility. In related technologies, thin film transistors are limited by the process and structure of the active layer, and the mobility is low, making it difficult to drive the light emitting device with high efficiency.
  • the present disclosure provides thin film transistors, thin film transistor preparation methods, array substrates, and display panels.
  • the thin film transistor includes: a substrate and an active layer disposed on the substrate; wherein the active layer includes a plurality of semiconductor nanowires; the thin film transistor further includes: disposed on the substrate close to the active layer; A plurality of guide protrusions on one side of the layer, the plurality of guide protrusions extend along the first direction and are arranged at intervals, each of the plurality of guide protrusions includes two sides extending in the first direction The wall, the semiconductor nanowire extends along at least one side wall of the guide protrusion.
  • the semiconductor nanowire is a silicon nanowire; and/or the substrate is a glass substrate or a polyimide substrate.
  • the base and the plurality of guiding protrusions are integrally formed.
  • the plurality of guiding protrusions are sequentially arranged along a second direction perpendicular to the first direction at equal intervals; the plurality of semiconductor nanowires are respectively arranged on the same side of the plurality of guiding protrusions Multiple side walls.
  • the plurality of guiding protrusions are sequentially arranged along a second direction perpendicular to the first direction at equal intervals; the plurality of semiconductor nanowires are respectively arranged on all sides of the plurality of guiding protrusions On the wall.
  • the thin film transistor further includes: a source electrode and a drain electrode, the source electrode and the drain electrode are arranged in the same layer, and the source electrode and the drain electrode are arranged on the active layer away from the One side of the substrate; and the source and the drain are respectively connected to both ends of the plurality of semiconductor nanowires.
  • the manufacturing method of the thin film transistor of the present disclosure includes the following steps: fabricating a substrate; fabricating a plurality of guiding protrusions on the substrate, the plurality of guiding protrusions extending in a first direction and arranged at intervals, the plurality of guiding protrusions
  • Each guide protrusion in the part includes two sidewalls extending along the first direction; a plurality of semiconductor nanowires are fabricated on the substrate as an active layer, and the semiconductor nanowires are along at least one of the guide protrusions.
  • the side walls extend.
  • forming a plurality of guide protrusions on the substrate includes: depositing a layer of silicon oxide on a side of the substrate close to the active layer to form a guide protrusion material layer; A plurality of guide protrusions extending along the first direction are formed on the side of the guide protrusion material layer away from the base.
  • forming a plurality of guide protrusions extending in the first direction on the side of the guide protrusion material layer away from the substrate by a patterning process includes: using a nanoimprinting process or a photolithography process, A plurality of guide protrusions extending along the first direction are formed on the side of the guide protrusion material layer away from the base.
  • the material of the substrate and the plurality of guide protrusions includes glass, and fabricating the plurality of guide protrusions on the substrate includes forming an integrated structure of the substrate and the substrate in a single process. The multiple guide protrusions.
  • fabricating a plurality of semiconductor nanowires as an active layer on the substrate includes: fabricating guide particles on one end of at least one side wall of the plurality of guiding protrusions; A layer of semiconductor material is deposited on the side away from the substrate, so that the semiconductor material grows along at least one sidewall of the plurality of guide protrusions under the guidance of the guide particles to form the semiconductor nanowires.
  • making guide particles on one end of at least one side wall of the plurality of guiding protrusions includes depositing a guiding material on one end of the at least one side wall of the plurality of guiding protrusions, wherein the The guiding material and the guiding particles have the same chemical elements; and in the plasma enhanced chemical vapor deposition system, the guiding material is converted into the guiding particles through a plasma treatment process.
  • the guiding material is indium tin oxide, and the guiding particles are indium.
  • a layer of semiconductor material is deposited on the side of the plurality of guiding protrusions away from the substrate, so that the semiconductor material is guided by the guiding particles along the edges of the plurality of guiding protrusions.
  • Growing at least one sidewall to form the semiconductor nanowire includes: depositing a layer of semiconductor material on the side of the plurality of guiding protrusions away from the substrate at a temperature of 180°C to 220°C; Next, at a temperature of 250° C. to 350° C., the semiconductor material is guided by the guide particles to grow along at least one sidewall of the plurality of guide protrusions to form the semiconductor nanowire.
  • the semiconductor material includes amorphous silicon
  • the semiconductor nanowires include silicon nanowires.
  • the preparation method further includes: converting the amorphous silicon into polycrystalline silicon through an annealing process at a temperature of 180°C to 220°C, and then removing the polycrystalline silicon.
  • the preparation method further includes: performing passivation treatment on the semiconductor nanowire.
  • the array substrate of the present disclosure includes a driving circuit, and the driving circuit includes the above-mentioned thin film transistor.
  • the display panel of the present disclosure includes the array substrate as described above.
  • the display panel further includes active matrix organic light emitting diodes or passive matrix organic light emitting diodes.
  • FIG. 1 is a schematic diagram of the structure of a thin film transistor provided by an embodiment of the disclosure (only showing the substrate, the guiding protrusion and the active layer);
  • 2A is a schematic structural diagram of a thin film transistor provided by an embodiment of the disclosure (only showing the substrate, the guiding protrusion, the active layer, and the source and drain);
  • 2B is a schematic structural diagram of a thin film transistor provided by an embodiment of the disclosure (only showing the substrate, the guiding protrusion, the active layer, and the source and drain);
  • FIG. 3 is a schematic diagram of the structure of a thin film transistor (top gate top contact) provided by an embodiment of the disclosure
  • FIG. 4 is a schematic diagram of the structure of a thin film transistor (bottom gate top contact) provided by an embodiment of the disclosure
  • FIG. 5 is a schematic diagram of the structure of a thin film transistor (top gate and bottom contact) provided by an embodiment of the disclosure
  • FIG. 6 is a schematic diagram of the structure of a thin film transistor (bottom gate and bottom contact) provided by an embodiment of the disclosure
  • FIG. 7 is a flowchart of a method for manufacturing a thin film transistor provided by an embodiment of the disclosure.
  • FIG. 8 is a schematic diagram of a manufacturing process of a method for manufacturing a thin film transistor provided by an embodiment of the disclosure.
  • an embodiment of the present disclosure provides a thin film transistor.
  • the thin film transistor includes a substrate 1 and an active layer disposed on the substrate 1.
  • the active layer includes a plurality of semiconductor nanowires 2.
  • the thin film transistor also includes a plurality of guide protrusions 3 (ie, guide layer) disposed on the side of the substrate 1 close to the active layer, the plurality of guide protrusions 3 extend along the first direction S1, and the plurality of guide protrusions 3 are arranged at intervals
  • Each guide protrusion has two sidewalls extending along the first direction S1, the guide protrusion 3 is used to guide the extending direction of the semiconductor nanowire 2, and the semiconductor nanowire 2 is along at least one of the two sidewalls of the guide protrusion 3
  • One side wall extends, that is, the semiconductor nanowire 2 also extends along the first direction S1 like the side wall of the guide protrusion 3 that guides its extension.
  • the two side walls of a guide protrusion 3 may both have the semiconductor nanowires 2 attached, It is also possible to attach the semiconductor nanowire 2 to only any one of the two sidewalls, which can be specifically set as required. In the following description, the semiconductor nanowire 2 is only attached to one sidewall of the guide protrusion 3 as an example.
  • the guide protrusion 3 may be made of various materials, such as silicon oxide.
  • the thin film transistor shown in FIG. 1 includes three guide protrusions 3. However, the present disclosure is not limited to this, and the thin film transistor may include more guide protrusions 3 and may be arranged more densely. The number of guide protrusions 3 and the distance between adjacent guide protrusions 3 can be set according to requirements, which is not limited here.
  • first direction S1 can be any direction, for example, the first direction S1 is the length direction of the substrate 1, and can be specifically set as required.
  • a plurality of guide protrusions 3 are sequentially arranged along a second direction perpendicular to the first direction at equal intervals, and a plurality of semiconductor nanowires 2 may be respectively arranged on the same side of the plurality of guide protrusions On multiple sidewalls (as shown in FIG. 1), the multiple semiconductor nanowires 2 in the thin film transistor of this structure are also arranged at equal intervals.
  • semiconductor nanowires 2 can be provided on both sides of each guide protrusion 3, so that the density of semiconductor nanowires 2 can be further increased, as shown in FIG. 2B.
  • the thin film transistor also includes a source 41, a drain 42, and a gate 5.
  • the orthographic projection of the gate 5 on the substrate 1 overlaps with the orthographic projection of the active layer on the substrate 1.
  • the source 41 and the drain 42 is connected to the active layer, and only the substrate 1 and the active layer are shown in FIG. 1.
  • the channel of carriers increases, so the carrier mobility and carrier concentration of the thin film transistor can be effectively improved , which can improve the performance of thin film transistors.
  • the size of the active layer is also not limited, so that the size of the thin film transistor is not limited, and it can be adapted to various types of display panels.
  • the semiconductor nanowire 2 may be a silicon nanowire, a germanium nanowire, or the like. Silicon nanowires are formed by the arrangement of silicon atoms, and the semiconductor properties of silicon are beneficial to serve as the active layer of thin film transistors. In the following description, the semiconductor nanowire is a silicon nanowire as an example.
  • the substrate 1 may be a rigid substrate such as a glass substrate, or a flexible substrate such as a polyimide substrate, which is not limited in the present disclosure.
  • the base 1 can be integrally formed with a plurality of guide protrusions 3, that is, the guide protrusions 3 and the base 1 are an integrated structure.
  • a plurality of guide protrusions 3 can be directly fabricated on the substrate 1, and then a plurality of semiconductor nanowires 2 are formed along at least one sidewall of each guide protrusion 3 respectively.
  • the base 1 and the guide protrusions 3 can also be made of different materials.
  • the guide protrusions 3 are made by a silicon process
  • a silicon-based material can be provided on the substrate 1 (for example, a glass substrate) to form a guide protrusion material layer.
  • a plurality of guide protrusions 3 are fabricated on the side of the guide protrusion material layer away from the base 1.
  • the source 41 and drain 42 of the thin film transistor provided by the embodiment of the present disclosure are arranged in the same layer, and both the source 41 and the drain 42 are connected to the active layer. Specifically, both Both are connected to the two ends of the plurality of semiconductor nanowires 2 in the active layer, the source 41 and the drain 42 extend along the second direction S2, and the first direction S1 and the second direction S2 are not parallel, for example, the first The one direction S1 and the second direction S2 are approximately perpendicular.
  • the thin film transistor includes a substrate 1, an active layer, a source 41, a drain 42 and a gate 5.
  • the thin film transistor provided in this embodiment can adopt a variety of structures. In different structures, the positional relationship of the active layer, the source 41, the drain 42 and the gate 5 is different. Hereinafter, the description will be made with the top as the top and the bottom as the bottom in FIGS. 3 to 6.
  • the thin film transistor of the embodiment of the present disclosure has a top gate top contact structure. That is, an active layer (ie, a plurality of semiconductor nanowires 2) is provided on the substrate 1, a source 41 and a drain 42 are provided on the top surface of the active layer, and the source 41 and the drain 42 are provided in the same layer, and the gate 5 is arranged on the side of the source 41 and the drain 42 away from the active layer, a gate insulating layer 6 is provided between the gate 5 and the active layer, and a protective layer 7 is arranged on the side of the gate 5 away from the active layer.
  • an active layer ie, a plurality of semiconductor nanowires 2
  • a source 41 and a drain 42 are provided on the top surface of the active layer
  • the source 41 and the drain 42 are provided in the same layer
  • the gate 5 is arranged on the side of the source 41 and the drain 42 away from the active layer
  • a gate insulating layer 6 is provided between the gate 5 and the active layer
  • a protective layer 7 is
  • the thin film transistor of the embodiment of the present disclosure has a bottom gate top contact structure. That is, a gate 5 is provided on the substrate 1, an active layer (ie, a plurality of semiconductor nanowires 2) is provided on the side of the gate 5 away from the substrate, and a gate insulating layer 6 is provided between the gate 5 and the active layer.
  • a source 41 and a drain 42 are arranged on the top surface of the active layer, and the source 41 and the drain 42 are arranged in the same layer, and a protective layer 7 is arranged on the side of the source 41 and the drain 42 away from the active layer.
  • the thin film transistor of the embodiment of the present disclosure has a top gate and bottom contact structure. That is, the source 41 and the drain 42 are arranged on the substrate 1, and the source 41 and the drain 42 are arranged in the same layer, and the active layer (that is, a plurality of semiconductor nanowires 2) is arranged away from the source 41 and the drain 42.
  • the side of the substrate 1, that is, the source 41 and the drain 42 are connected to the active layer through the bottom surface of the active layer.
  • a protective layer 7 is provided on the side of the polar insulating layer 6 and the gate 5 away from the active layer.
  • the thin film transistor of the embodiment of the present disclosure has a bottom gate bottom contact structure. That is, the gate 5 is arranged on the substrate 1, the source 41 and the drain 42 are arranged on the side of the gate 5 away from the substrate 1, and the source 41 and the drain 42 are arranged in the same layer, and the source 41 and the drain 42 are located on the layer A gate insulating layer 6 is arranged between the gate 5 and the gate 5, and the active layer (ie, a plurality of semiconductor nanowires 2) is arranged on the side of the source 41 and the drain 42 away from the substrate 1, that is, the source 41 and the drain 42 The bottom surface of the active layer is connected to the active layer, and a protective layer 7 is provided on the side of the active layer away from the substrate 1.
  • the active layer ie, a plurality of semiconductor nanowires 2
  • the thin film transistor used in the embodiments of the present disclosure can adopt any of the above-mentioned structures.
  • the thin film transistor adopts a top contact (FIG. 3, FIG. 4) structure, that is, the source 41 and the drain 42 are arranged on the active layer away from the structure.
  • the source 41 and the drain 42 are in contact with the active layer through the top surface of the active layer, so that the semiconductor nanowire 2 in the active layer can be avoided when the source 41 and the drain 42 are etched. Damaged.
  • an embodiment of the present disclosure also provides a method for manufacturing a thin film transistor, including the following steps:
  • the substrate 1 may be any type of substrate, such as a rigid substrate such as a glass substrate or a flexible substrate such as a polyimide substrate.
  • the substrate 1 and the guiding layer (including a plurality of guiding protrusions 3) in the active layer can be formed by a single process, that is, the substrate 1 and the guiding layer are an integral structure.
  • both the substrate 1 and the guiding layer are glass.
  • multiple guiding protrusions 3 can be directly fabricated on the substrate 1.
  • a plurality of guide protrusions 3 are made on the substrate 1, and the plurality of guide protrusions 3 extend along the first direction S1 and are arranged at intervals, and each guide protrusion 3 includes two side walls extending along the first direction.
  • the guide protrusion 3 and the base 1 are made of different materials for description, and S2 may include:
  • a guide protrusion material layer is deposited on the substrate 1 to pattern a plurality of guide protrusions 3.
  • various types of substrates 1 can be used.
  • the substrate 1 is a glass substrate or a polyimide substrate
  • a layer of silicon oxide is deposited on the substrate 1, so that a plurality of guiding protrusions 3 can be fabricated using a guiding protrusion material layer formed of silicon oxide. It is ensured that the process accuracy of patterning the plurality of guide protrusions 3 is not affected.
  • a variety of processes can be selected for the patterning process to improve the accuracy of the patterning process.
  • the guide protrusion material layer formed by silicon oxide is the material of the guide protrusion 3. Since silicon oxide facilitates the precise patterning process, silicon oxide is used to form the guide protrusion material layer. The structure of the guide protrusion 3 can be made more precise.
  • a plurality of guide protrusions 3 may be formed by patterning the guide protrusion material layer by a nanoimprinting process or a photolithography process. If a plurality of guide protrusions 3 are produced by the nanoimprinting process, after depositing the material of the guide protrusion layer material (such as silicon oxide), an imprint template is made according to the pattern of the plurality of guide protrusions 3 required, and the imprint template It has a plurality of convex structures, and the concave portions between adjacent convex structures correspond to the guiding convex portions 3 to be formed one-to-one, and the imprinting template is pressed on the guiding convex portion material layer to form corresponding multiple guiding convex portions 3 After that, the glue is removed to form the final guiding layer.
  • the material of the guide protrusion layer material such as silicon oxide
  • the nanoimprinting process is used to produce multiple guide protrusions 3. Compared with other patterning processes, the nanoimprinting process has high patterning accuracy, so the distance between adjacent guide protrusions 3 can be reduced, and the guide protrusions 3 can be improved.
  • the arrangement density reduces the line width of the subsequently formed semiconductor nanowires 2, that is, the width of the semiconductor nanowires 2 along the extending direction parallel to the substrate 1, so that the width of the semiconductor nanowires 2 reaches the nanometer-scale width.
  • the number of semiconductor nanowires 2 in the source layer is significantly increased, thereby increasing the mobility and concentration of carriers, which can effectively improve the efficiency of the thin film transistor.
  • the guiding protrusions 3 and the substrate 1 are made of the same material, the guiding protrusions 3 can be directly fabricated on the side of the substrate 1 close to the active layer, that is, the substrate 1 and the guiding protrusion material layer are formed by a single process.
  • the substrate 1 and the guiding protrusion material layer have the same base structure, such as a glass substrate, and multiple guiding protrusions 3 can be directly fabricated on the side of the glass substrate close to the active layer.
  • Fabricating an active layer on the substrate 1 includes fabricating a plurality of semiconductor nanowires 2, and each semiconductor nanowire 2 of the plurality of semiconductor nanowires 2 extends along at least one sidewall of the guiding protrusion 3.
  • S3 may include: S231, referring to FIGS. 8(a) to 8(c), making guiding particles at one end of the plurality of guiding protrusions 3.
  • the guide material 02 can be deposited on one end of the plurality of guide protrusions 3 through a sputtering process.
  • the plasma enhanced chemical vapor deposition Plasma Enhanced Chemical Vapor Deposition, PECVD
  • the plasma treatment Plasma
  • the guiding material 02 is transformed into nano-level guiding particles 03, which can guide the guiding particles 03 along at least one side wall of the guiding protrusion 3 after contacting the semiconductor material forming the semiconductor nanowire 2 Grow to form semiconductor nanowires 2.
  • the guiding material 02 and the guiding particles 03 have the same chemical elements.
  • the guiding particles 03 may be metal particles such as indium (In), tin (Sn) or bismuth (Bi), and the guiding material 02 may contain guiding particles.
  • the material of the element 03 for example, the guiding material 02 may be indium tin oxide (Indium Tin Oxide, ITO), and the guiding particles 03 are In particles.
  • ITO Indium Tin Oxide
  • the end of the guide protrusion 3 where the guide material 02 is deposited is the starting point of the growth of the semiconductor nanowire 2.
  • a layer of semiconductor material is deposited on the side of the plurality of guide protrusions 3 away from the substrate 1.
  • the semiconductor material is guided by the guide particles 03 along the guide protrusions 3
  • the sidewalls grow to form semiconductor nanowires 2.
  • the temperature of the chemical vapor deposition (CVD) chamber in the PECVD system reaches a temperature in the range of, for example, 180°C to 220°C (for example, 200°C)
  • a layer is deposited on the side of the guide protrusion 3 away from the substrate 1
  • the semiconductor material the semiconductor material is the material that forms the semiconductor nanowire 2.
  • the semiconductor material around the particle 03 thus grows the semiconductor nanowire 2, and the semiconductor nanowire 2 is guided by the guide particle 03 and grows along the sidewalls of the plurality of guide protrusions 3, that is, grows along the first direction S1, As shown in FIG. 8(e), a plurality of semiconductor nanowires 2 extending along the first direction S1 are thus formed.
  • the semiconductor material can be amorphous silicon (a-Si).
  • the a-Si is in contact with In particles (guide particles 02) and grows along the sidewalls of the multiple guiding protrusions 3.
  • a plurality of silicon nanowires are formed, and the growth time of the silicon nanowires is about 30 minutes.
  • the semiconductor material is a-Si
  • the semiconductor nanowires are silicon nanowires as an example, at a temperature in the range of 250°C to 350°C, In
  • the particles are in the state of droplets.
  • In metal droplets can absorb the surrounding a-Si.
  • silicon nuclei (c-Si) will be precipitated, and the silicon nanowires are silicon crystals.
  • the nuclei are arranged in the first direction.
  • the excess semiconductor material can be removed.
  • the semiconductor material as amorphous silicon as an example, after the CVD chamber is cooled to a temperature of, for example, 180°C to 220°C (for example, 200°C), the amorphous silicon can be converted into polysilicon through an Excimer Laser Annealing (ELA) process After cleaning, the surface of the semiconductor nanowire 2 is clean.
  • ELA Excimer Laser Annealing
  • the semiconductor nanowire 2 can also be passivated.
  • a passivation layer may be formed on the semiconductor nanowire 2 to protect the semiconductor nanowire 2 and prevent the semiconductor nanowire 2 from being damaged in subsequent processes.
  • the method for fabricating a thin film transistor provided in this embodiment further includes fabricating a source 41, a drain 42 and a gate 5.
  • the production sequence of the active layer, the source 41, the drain 42 and the gate 5 can be adjusted accordingly. Show) as an example.
  • the active layer ie semiconductor nanowire 2
  • the metal materials of the source 41 and the drain 42 are deposited on the side of the active layer away from the substrate 1, and then etched by a photolithography process The patterns required for the source 41 and the drain 42 are drawn, and the two are connected to the active layer through a punching process.
  • a gate insulating layer 6 is formed on the side of the source 41 and the drain 42 away from the substrate 1, and then A gate 5 is formed on the side of the gate insulating layer 6 away from the substrate 1, and then a protective layer 7 is formed on the side of the gate 5 away from the substrate 1, thereby forming a thin film transistor.
  • the manufacturing process of the thin film transistor can be simplified.
  • the active layer of the thin film transistor includes a plurality of semiconductor nanowires 2 and the number of carrier channels increases, the carrier mobility and carrier concentration of the thin film transistor can be effectively improved, thereby improving the performance of the thin film transistor.
  • the length of the semiconductor nanowire 2 is not limited, the size of the active layer is also not limited, so that the size of the thin film transistor is not limited, and can be adapted to various types of display panels.
  • the embodiments of the present disclosure also provide an array substrate, including the above-mentioned thin film transistor, or including the thin film transistor prepared by the above-mentioned manufacturing method.
  • the array substrate includes a driving circuit.
  • a driving circuit of a light emitting device may include a plurality of thin film transistors, for example, including a switching transistor, a driving transistor, etc., and at least one of these transistors may be a thin film transistor provided in an embodiment of the present disclosure.
  • the embodiment of the present disclosure also provides a display panel including the above-mentioned array substrate.
  • the display panel may include various types of display panels, such as an active matrix organic light emitting diode (Active-matrix OLED, AMOLED) panel, or a passive matrix organic light emitting diode (Passive matrix OLED, PMOLED)
  • AMOLED active matrix organic light emitting diode
  • Passive matrix OLED Passive matrix OLED
  • the board can also be other types of display panels.
  • the size of AMOLED is relatively large.
  • the AMOLED panel can be effectively driven.

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Abstract

本公开提供一种薄膜晶体管、薄膜晶体管的制备方法、阵列基板和显示面板，属于薄膜晶体管器件技术领域。本公开提供的薄膜晶体管包括基底，和设置在基底上的有源层，其中，有源层包括多条半导体纳米线，薄膜晶体管还包括设置在基底上的多条引导凸部，多条引导凸部沿第一方向延伸且间隔设置，每条引导凸部包括两个沿第一方向延伸的侧壁，半导体纳米线沿引导凸部的至少一个侧壁延伸。本公开提供的薄膜晶体管由于使用多条半导体纳米线作为薄膜晶体管的有源层，因此可以有效提高薄膜晶体管的载流子迁移率和载流子浓度，从而能够提高薄膜晶体管的性能，并且由于半导体纳米线的长度不受限制，因此能够使薄膜晶体管的尺寸不受限制。

Description

薄膜晶体管及其制备方法、阵列基板、显示面板
相关申请的相交引用
本申请要求于2020年6月24日在中国知识产权局提交的No.202010590208.9的中国专利申请的优先权，该中国专利申请的全部内容通过引用合并于此。
技术领域
本公开属于薄膜晶体管器件技术领域，具体涉及一种薄膜晶体管、薄膜晶体管的制备方法、阵列基板、显示面板。
背景技术
薄膜晶体管(Thin Film Transistor，TFT)可应用在各种电子设备中，例如应用在显示面板中，薄膜晶体管可用于驱动显示面板中的发光器件，或作为发光器件的开关单元等。而薄膜晶体管的重要指标包括迁移率，在相关技术中，薄膜晶体管受限于有源层的工艺和结构，迁移率较低，难以实现高效率地驱动发光器件。
发明内容
本公开提供了薄膜晶体管、薄膜晶体管的制备方法、阵列基板、显示面板。
所述薄膜晶体管包括：基底和设置在所述基底上的有源层；其中，所述有源层包括多条半导体纳米线；所述薄膜晶体管还包括：设置在所述基底靠近所述有源层一侧的多条引导凸部，所述多条引导凸部沿第一方向延伸且间隔设置，所述多条引导凸部中的每一条引导凸部包括两个沿第一方向延伸的侧壁，所述半导体纳米线沿所述引导凸部的至少一个侧壁延伸。
在一些实施例中，所述半导体纳米线为硅纳米线；和/或所述基底为玻璃基底或聚烯亚胺基底。
在一些实施例中，所述基底与所述多条引导凸部一体成型。
在一些实施例中，所述多条引导凸部以相等间隔沿着与第一方向垂直的第二方向依次设置；所述多条半导体纳米线分别设置在所述多条引导凸部同一侧的多个侧壁上。
在一些实施例中，所述多条引导凸部以相等间隔沿着与第一方向垂直的第二方向依次设置；所述多条半导体纳米线分别设置在所述多条引导凸部的所有侧壁上。
在一些实施例中，所述薄膜晶体管还包括：源极和漏极，所述源极和漏极同层设置，且所述源极和所述漏极设置在所述有源层背离所述基底一侧；以及所述源极和所述漏极分别与所述多条半导体纳米线的两端连接。
本公开的薄膜晶体管的制备方法，包括以下步骤：制作基底；在所述基底上制作多条引导凸部，所述多条引导凸部沿第一方向延伸且间隔设置，所述多条引导凸部中的每条引导凸部包括两个沿第一方向延伸的侧壁；在所述基底上制作多条半导体纳米线作为有源层，所述半导体纳米线沿所述引导凸部的至少一个侧壁延伸。
在一些实施例中，在所述基底上制作多条引导凸部包括：在所述基底靠近所述有源层一侧沉积一层氧化硅以形成引导凸部材料层；通过图案化工艺在所述引导凸部材料层背离所述基底一侧制作多条沿第一方向延伸的引导凸部。
在一些实施例中，通过图案化工艺在所述引导凸部材料层背离所述基底一侧制作多条沿第一方向延伸的引导凸部包括：通过纳米压印工艺或光刻工艺，在所述引导凸部材料层背离所述基底一侧制作多条沿第一方向延伸的引导凸部。
在一些实施例中，所述基底和所述多条引导凸部的材料包括玻璃，以及在所述基底上制作多条引导凸部包括采用一次工艺成型一体结构的所述基底和所述基底上的所述多条引导凸部。
在一些实施例中，在所述基底上制作多条半导体纳米线作为有源层包括：在所述多条引导凸部的至少一个侧壁的一端制作引导颗粒；在所述多条引导凸部背离所述基底一侧沉积一层半导体材料，使得所述半导体材料在所述引导颗粒的引导下，沿着所述多条引导凸部的至少一个侧壁生长，形成所述半导体纳米线。
在一些实施例中，在所述多条引导凸部的至少一个侧壁的一端制作引导颗粒包括：在所述多条引导凸部的至少一个侧壁的一端，沉积引导材料，其中，所述引导材料与所述引导颗粒具有相同的化学元素；以及在等离子体增强化学气相沉积系统中，通过等离子体处理工艺，使所述引导材料转化为所述引导颗粒。
在一些实施例中，所述引导材料为氧化铟锡，所述引导颗粒为铟。
在一些实施例中，在所述多条引导凸部背离所述基底一侧沉积一层半导体材料，使得所述半导体材料在所述引导颗粒的引导下，沿着所述多条引导凸部的至少一个侧壁生长，形成所述半导体纳米线，包括：在180℃至220℃的温度下，在所述多条引导凸部背离所述基底一侧沉积一层半导体材料；在惰性还原气体条件下，在250℃至350℃的温度下，使得所述半导体材料在所述引导颗粒的引导下，沿着所述多条引导凸部的至少一个侧壁生长，形成所述半导体纳米线。
在一些实施例中，所述半导体材料包括非晶硅，所述半导体纳米线包括硅纳米线。
在一些实施例中，在惰性还原气体条件下，在250℃至350℃的温度下，使得所述半导体材料在所述引导颗粒的引导下，沿着所述引导凸部的至少一个侧壁生长，形成所述半导体纳米线之后，所述制备方法还包括：在180℃至220℃的温度下，通过退火工艺将所述非晶硅转换为多晶硅，然后将多晶硅清除。
在一些实施例中，在多晶硅清除之后，所述制备方法还包括：对所述半导体纳米线进行钝化处理。
本公开的阵列基板，包括驱动电路，所述驱动电路包括如上所述的薄膜晶 体管。
本公开的显示面板包括如上所述的阵列基板。
在一些实施例中，所述显示面板还包括有源矩阵有机发光二极管或无源矩阵有机发光二极管。
附图说明
图1为本公开实施例提供的薄膜晶体管的结构示意图(仅示出基底、引导凸部和有源层)；
图2A为本公开实施例提供的薄膜晶体管的结构示意图(仅示出基底、引导凸部、有源层和源漏极)；
图2B为本公开实施例提供的薄膜晶体管的结构示意图(仅示出基底、引导凸部、有源层和源漏极)；
图3为本公开实施例提供的薄膜晶体管的结构示意图(顶栅顶接触)；
图4为本公开实施例提供的薄膜晶体管的结构示意图(底栅顶接触)；
图5为本公开实施例提供的薄膜晶体管的结构示意图(顶栅底接触)；
图6为本公开实施例提供的薄膜晶体管的结构示意图(底栅底接触)；
图7为本公开实施例提供的薄膜晶体管的制备方法的流程图；以及
图8为本公开实施例提供的薄膜晶体管的制备方法的制备过程示意图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开作进一步地详细描述，显然，所描述的实施例仅是本公开的部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本公开的保护范围。
附图中各部件的形状和大小不反映真实比例，目的只是为了便于对本公开实施例的内容的理解。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”、“底”、“顶”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
如图1所示，本公开实施例提供一种薄膜晶体管，该薄膜晶体管包括基底1，和设置在基底1之上的有源层。有源层包括多条半导体纳米线2。薄膜晶体管还包括设置在基底1靠近有源层一侧的多条引导凸部3(即，导向层)，多条引导凸部3沿第一方向S1延伸，且多条引导凸部3间隔设置，每条引导凸部具有两个沿第一方向S1延伸的侧壁，引导凸部3用于引导半导体纳米线2的延伸方向，半导体纳米线2沿引导凸部3两个侧壁中的至少一个侧壁延伸，即半导体纳米线2与引导其延伸的引导凸部3的侧壁一样也沿第一方向S1延伸，一引导凸部3的两个侧壁可以都附着有半导体纳米线2，也可以仅在两个侧壁的任一个侧壁附着有半导体纳米线2，具体的可根据需要设置。以下皆以半导体纳米线2仅附着在引导凸部3的一个侧壁为例进行说明。
需要说明的是，在本公开中，多条半导体纳米线2作为薄膜晶体管的有源层。引导凸部3可以由多种材料制备，例如氧化硅。图1中所示的薄膜晶体管包括三个引导凸部3。但是本公开不限于此，薄膜晶体管可以包括更多条引导凸部3，并且可以排布更密集。引导凸部3的数量和相邻引导凸部3之间的间距可以根据需要设置，在此不做限定。
需要说明的是，第一方向S1可以是任意方向，例如第一方向S1为基底1的长度方向，具体的可以根据需要设置。
在一个实施例中，多条引导凸部3以相等间隔沿着与第一方向垂直的第二方向依次设置，而多条半导体纳米线2可以分别设置在所述多条引导凸部的同一侧的多个侧壁上(如图1所示)，这样结构的薄膜晶体管中的多条半导体纳米线2也是等间距排列的。但是，本公开不限于此，例如，可以在每条引导凸部3两侧均设置半导体纳米线2，这样可以进一步提高半导体纳米线2的密度，如图2B所示。
需要说明的是，薄膜晶体管还包括源极41、漏极42、栅极5，栅极5在基底1上的正投影与有源层在基底1上的正投影重叠，源极41和漏极42与有源层相接，图1中仅示出基底1和有源层。
本公开实施例提供的薄膜晶体管中，由于使用多条半导体纳米线2作为薄膜晶体管的有源层，载流子的通道增多，因此可以有效提高薄膜晶体管的载流子迁移率和载流子浓度，从而能够提高薄膜晶体管的性能。另外，由于半导体纳米线2的长度不受限制，因此有源层的尺寸也不受限制，从而能够使薄膜晶体管的尺寸不受限制，可以适应各个类型的显示面板。
本公开不限定半导体纳米线2的材料。例如，半导体纳米线2可以为硅纳米线、锗纳米线等。硅纳米线为硅原子排列形成，硅的半导体性质有利于作为薄膜晶体管的有源层。以下皆以半导体纳米线为硅纳米线为例进行说明。
可选地，基底1可以为玻璃基底等刚性基底，或聚烯亚胺基底等柔性基底，本公开对此不进行限定。基底1可以与多条引导凸部3一体成型，即引导凸部3与基底1为一体结构。可以直接在基底1之上制作多条引导凸部3，再分别沿各条引导凸部3的至少一个侧壁形成多条半导体纳米线2。基底1也可以与引导凸部3采用不同的材料制成，例如，若采用硅工艺制作引导凸部3，可以在基底1(例如玻璃基底)上设置硅基的材料形成引导凸部材料层，再在引导凸部材料层背离基底1一侧制作出多条引导凸部3。
如图2A和图2B所示，本公开实施例提供的薄膜晶体管的源极41和漏极42同层设置，且源极41和漏极42均与有源层相接，具体的，二者均与有源层中 的多条半导体纳米线2的两端相接，源极41和漏极42沿第二方向S2延伸，第一方向S1和第二方向S2不平行即可，例如，第一方向S1和第二方向S2近似相垂直。
进一步地，如图3至图6所示，薄膜晶体管包括基底1、有源层、源极41、漏极42和栅极5。本实施例提供的薄膜晶体管可以采用多种结构，在不同的结构中，有源层、源极41、漏极42和栅极5的位置关系不同。以下以图3至图6中上为顶、下为底的方式进行说明。
参见图3，本公开实施例的薄膜晶体管为顶栅顶接触结构。即，在基底1上设置有源层(即，多条半导体纳米线2)，有源层的顶面设置源极41和漏极42，且源极41、漏极42同层设置，栅极5设置在源极41和漏极42背离有源层一侧，栅极5和有源层之间具有栅极绝缘层6，栅极5背离有源层一侧设置有保护层7。
参见图4，本公开实施例的薄膜晶体管为底栅顶接触结构。即，在基底1上设置栅极5，有源层(即，多条半导体纳米线2)设置在栅极5背离基底一侧，栅极5和有源层之间具有栅极绝缘层6，有源层的顶面设置源极41和漏极42，且源极41、漏极42同层设置，源极41和漏极42背离有源层一侧设置有保护层7。
参见图5，本公开实施例的薄膜晶体管为顶栅底接触结构。即，在基底1上设置源极41和漏极42，且源极41和漏极42同层设置，有源层(即，多条半导体纳米线2)设置在源极41和漏极42背离基底1一侧，即源极41和漏极42通过有源层的底面与有源层相接，栅极5设置有源层背离基底1一侧，栅极5和有源层之间具有栅极绝缘层6，栅极5背离有源层一侧设置有保护层7。
参见图6，本公开实施例的薄膜晶体管为底栅底接触结构。即，在基底1上设置栅极5，源极41和漏极42设置在栅极5背离基底1一侧，且源极41和漏 极42同层设置，源极41和漏极42所在层与栅极5之间设置有栅极绝缘层6，有源层(即，多条半导体纳米线2)设置在源极41和漏极42背离基底1一侧，即源极41和漏极42通过有源层的底面与有源层相接，有源层背离基底1一侧一侧设置有保护层7。
本公开实施例采用的薄膜晶体管可以采用上述任一种结构，在一些实施例中，薄膜晶体管采用顶接触(图3、图4)结构，即源极41和漏极42设置在有源层背离基底1一侧，源极41、漏极42通过有源层的顶面与有源层接触，从而可以避免在对源极41和漏极42进行刻蚀时使有源层中半导体纳米线2受损。
如图7所示，本公开实施例还提供一种薄膜晶体管的制备方法，包括以下步骤：
S1、制作基底1。
具体地，基底1可以为任意类型的基底，例如玻璃基底等刚性基底或聚烯亚胺基底等柔性基底。在一些实施例中，基底1和有源层中的导向层(包括多条引导凸部3)可以采用一次工艺成型，即基底1和导向层为一体结构。例如，基底1和导向层均为玻璃，在这种情况下，可以直接在基底1上制作多条引导凸部3。
S2、在基底1上制作多条引导凸部3，多条引导凸部3沿第一方向S1延伸且间隔设置，每条引导凸部3包括两个沿第一方向延伸的侧壁。
下面以引导凸部3与基底1采用不同材料为例进行说明，S2可以包括：
S21、在基底1靠近有源层一侧沉积氧化硅(SiO)作为引导凸部材料层。
在基底1上沉积引导凸部材料层来图案化形成多条引导凸部3，相比直接在硅片上制作多条引导凸部3而言，可以采用各种类型的基底1。例如，在基底1为玻璃基底或聚酰亚胺基底的情况下，在基底1上沉积一层氧化硅，从而可以利用氧化硅形成的引导凸部材料层制作多条引导凸部3，从而可以确保图案化多条引导凸部3的工艺精度不受影响。而且，在这种情况下，可以选择多种工艺来进行图案化工艺以提高图案化工艺精度。
S22、在引导凸部材料层背离基底1一侧制作多条沿第一方向S1延伸的引导凸部3。参见图8(a)所示，氧化硅形成的引导凸部材料层即为引导凸部3的材料，由于氧化硅有利于进行精密的图案化工艺，因此用氧化硅形成引导凸部材料层，可以使引导凸部3的结构更精确。
具体地，S22中，可以通过纳米压印工艺或通过光刻工艺来图案化引导凸部材料层来形成多条引导凸部3。若通过纳米压印工艺制作多条引导凸部3，则在沉积引导凸部材料层材料(例如氧化硅)后，根据所需的多条引导凸部3的图案制作压印模板，压印模板具有多个凸起结构，相邻的凸起结构之间的凹部与要形成的引导凸部3一一对应，将压印模板压在引导凸部材料层上形成对应的多条引导凸部3后，再进行去胶，形成最终的导向层。使用纳米压印工艺制作多条引导凸部3，相比其他图案化工艺，由于纳米压印工艺的图案化精度高，因此能够减小相邻的引导凸部3的间距，提高引导凸部3的排布密度，使后续形成的半导体纳米线2的线宽减小，即，半导体纳米线2沿着平行于基底1延伸方向的宽度，使得半导体纳米线2的宽度达到纳米级宽度，从而有源层中的半导体纳米线2的数量显著提高，进而载流子的迁移率和浓度升高，能够有效提升薄膜晶体管的效率。
可选地，若引导凸部3与基底1为同种材料，则可以在基底1靠近有源层一侧直接制作引导凸部3，也即基底1与引导凸部材料层通过一次工艺成型。例如，基底1和引导凸部材料层为同一基底结构，例如玻璃基底，可以直接在玻璃基底靠近有源层一侧制作多条引导凸部3。
S3、在基底1上制作有源层，包括制作多条半导体纳米线2，多条半导体纳米线2中的每一条半导体纳米线2沿引导凸部3的至少一个侧壁延伸。
具体地，S3可以包括：S231、参见图8(a)-图8(c)，在多条引导凸部3的一端制作引导颗粒。
具体地，参见图8(a)-图8(b)，可以先在多条引导凸部3的一端，通过溅射(sputter)工艺沉积引导材料02。参见图8(b)-图8(c)，之后在等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD) 系统中，通过等离子体处理(Plasma)工艺，在氢气环境下，且在温度150℃至300℃下，使引导材料02转化为纳米级的引导颗粒03，引导颗粒03在接触到形成半导体纳米线2的半导体材料后，能够引导其沿着引导凸部3的至少一个侧壁生长，形成半导体纳米线2。
可选地，引导材料02与引导颗粒03具有相同化学元素，例如，引导颗粒03可以为铟(In)、锡(Sn)或铋(Bi)等金属颗粒，引导材料02则可以为含引导颗粒03的元素的材料，例如，引导材料02可以为氧化铟锡(Indium Tin Oxide，ITO)，引导颗粒03为In颗粒。具体地，在引导凸部3的一端沉积ITO后，在PECVD系统中，通过Plasma工艺，利用氢离子将ITO还原为多个纳米级大小的In颗粒。
需要说明的是，引导凸部3沉积有引导材料02的一端，即，设置引导颗粒03的一端为半导体纳米线2生长的起点端。
S32、参见图8(d)-图8(e)，在多条引导凸部3背离基底1一侧沉积一层半导体材料，半导体材料在引导颗粒03的引导下，沿着引导凸部3的侧壁生长，形成半导体纳米线2。
具体地，在PECVD系统中的化学气相沉积(CVD)腔室的温度达到例如180℃至220℃范围内的温度(具体如200℃)时，在引导凸部3背离基底1一侧沉积一层半导体材料，半导体材料即为形成半导体纳米线2的材料。之后在惰性还原气体条件下，在250℃至350℃范围内的温度下，如图8(d)所示，位于引导凸部3的端部的引导颗粒03接触到半导体材料后，能够吸收引导颗粒03周围的半导体材料，从而生长出半导体纳米线2，且半导体纳米线2在引导颗粒03的引导下，沿着多条引导凸部3的侧壁生长，也即沿第一方向S1生长，如图8(e)所示，从而形成多条沿第一方向S1延伸的半导体纳米线2。以半导体纳米线2为硅纳米线为例，半导体材料可以为非晶硅(a-Si)，a-Si在接触In颗粒(引导颗粒02)，沿多条引导凸部3的侧壁生长，形成多条硅纳米线，硅纳米线的生长时间约为30分钟。
进一步地，如图8(d)所述，以引导颗粒03为In颗粒，半导体材料为a-Si， 半导体纳米线为硅纳米线为例，在250℃至350℃范围内的温度下，In颗粒的状态为液滴态，In金属液滴可以吸收周围的a-Si，在In金属液滴中的Si含量饱和时，会析出硅晶核(c-Si),硅纳米线即为硅晶核沿第一方向排列形成，由于a-Si的吉布斯自由能Ea大于c-Si的吉布斯自由能Ec，二者的吉布斯自由能差Eac＝Ea-Ec≈0.12eV，而In金属液滴能够降低a-Si向c-Si的输运能力，也就是说将固体(a-Si)-固体(c-Si)的过程转变为固体-液体-固体的过程，因此在Eac的驱动下，In金属液滴将a-Si析出硅晶核后，In金属液滴继续牵引硅晶核沿引导凸部3的侧壁生长，在生长过程中In金属液滴继续吸收侧壁周围的a-Si并析出硅晶核，最终硅晶核生长形成沿第一方向S1延伸的半导体纳米线2。
可选地，在半导体纳米线2生长完成后，可能存在多余的半导体材料，因此可以清除多余的半导体材料。以半导体材料为非晶硅为例，可以待CVD腔室冷却至例如180℃至220℃的温度(具体如200℃)后，通过退火(Excimer Laser Annealing，ELA)工艺将非晶硅转换为多晶硅后清除，以使半导体纳米线2的表面洁净。
可选地，在清除多余的非晶硅后，还可以对半导体纳米线2进行钝化处理。例如，可以在半导体纳米线2上形成钝化层，以保护半导体纳米线2，避免半导体纳米线2在后续工艺中受损。
可选地，参见图8(f)，本实施例提供的薄膜晶体管的制备方法还包括制作源极41、漏极42和栅极5。根据如上所述的薄膜晶体管的不同结构，有源层、源极41、漏极42和栅极5的制作顺序可以进行相应的调整，以薄膜晶体管采用顶栅顶接触型薄膜晶体管(图3所示)为例，按照上述步骤制作完有源层(即半导体纳米线2)后，在有源层背离基底1一侧沉积源极41和漏极42的金属材料，再通过光刻工艺刻蚀出源极41和漏极42所需的图案，通过打孔工艺使二者与有源层相接，之后在源极41和漏极42背离基底1一侧制作栅极绝缘层6，再在栅极绝缘层6背离基底1一侧制作栅极5，之后在栅极5背离基底1一侧制作保护层7，从而形成薄膜晶体管。
通过上述方法制备薄膜晶体管，可以简化薄膜晶体管的制作工艺。而且， 由于薄膜晶体管的有源层包括多条半导体纳米线2，载流子的通道增多，因此可以有效提高薄膜晶体管的载流子迁移率和载流子浓度，从而能够提高薄膜晶体管的性能，并且由于半导体纳米线2的长度不受限制，因此有源层的尺寸也不受限制，从而能够使薄膜晶体管的尺寸不受限制，可以适应各个类型的显示面板。
本公开实施例还提供一种阵列基板，包括上述的薄膜晶体管，或，包括上述的制备方法所制备的薄膜晶体管。
具体的，阵列基板包括驱动电路。阵列基板用于驱动发光器件时，一个发光器件的驱动电路可以包括多个薄膜晶体管，例如包括开关晶体管、驱动晶体管等，这些晶体管中的至少一个晶体管可以为本公开实施例提供的薄膜晶体管。
本公开实施例还提供一种显示面板，包括上述阵列基板。
可选地，显示面板可以包括各种类型的显示面板，例如有源矩阵有机发光二极管(Active-matrix OLED，AMOLED)面板，也可以是无源矩阵有机电激发光二极管(Passive matrix OLED，PMOLED)板，当然，也可以是其他类型的显示面板。通常AMOLED的尺寸较大，而本公开实施例提供的薄膜晶体管，由于有源层的尺寸不受限制，因此可以有效驱动AMOLED面板。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (20)

  1. 一种薄膜晶体管，包括：基底和设置在所述基底上的有源层；其中，
    所述有源层包括多条半导体纳米线；
    所述薄膜晶体管还包括：
    设置在所述基底靠近所述有源层一侧的多条引导凸部，所述多条引导凸部沿第一方向延伸且间隔设置，所述多条引导凸部中的每一条引导凸部包括两个沿第一方向延伸的侧壁，所述半导体纳米线沿所述引导凸部的至少一个侧壁延伸。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述半导体纳米线为硅纳米线；和/或
    所述基底为玻璃基底或聚烯亚胺基底。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述基底与所述多条引导凸部一体成型。
  4. 根据权利要求1至3中任一项所述的薄膜晶体管，其中，
    所述多条引导凸部以相等间隔沿着与第一方向垂直的第二方向依次设置；
    所述多条半导体纳米线分别设置在所述多条引导凸部同一侧的多个侧壁上。
  5. 根据权利要求1至3中任一项所述的薄膜晶体管，其中，
    所述多条引导凸部以相等间隔沿着与第一方向垂直的第二方向依次设置；
    所述多条半导体纳米线分别设置在所述多条引导凸部的所有侧壁上。
  6. 根据权利要求1至5中任一项所述的薄膜晶体管，还包括：源极和漏极， 所述源极和漏极同层设置，且所述源极和所述漏极设置在所述有源层背离所述基底一侧；以及
    所述源极和所述漏极分别与所述多条半导体纳米线的两端连接。
  7. 一种薄膜晶体管的制备方法，包括以下步骤：
    制作基底；
    在所述基底上制作多条引导凸部，所述多条引导凸部沿第一方向延伸且间隔设置，所述多条引导凸部中的每条引导凸部包括两个沿第一方向延伸的侧壁；
    在所述基底上制作多条半导体纳米线作为有源层，所述半导体纳米线沿所述引导凸部的至少一个侧壁延伸。
  8. 根据权利要求7所述的制备方法，其中，在所述基底上制作多条引导凸部包括：
    在所述基底靠近所述有源层一侧沉积一层氧化硅以形成引导凸部材料层；
    通过图案化工艺在所述引导凸部材料层背离所述基底一侧制作多条沿第一方向延伸的引导凸部。
  9. 根据权利要求8所述的制备方法，其中，通过图案化工艺在所述引导凸部材料层背离所述基底一侧制作多条沿第一方向延伸的引导凸部包括：
    通过纳米压印工艺或光刻工艺，在所述引导凸部材料层背离所述基底一侧制作多条沿第一方向延伸的引导凸部。
  10. 根据权利要求7所述的制备方法，其中，
    所述基底和所述多条引导凸部的材料包括玻璃，以及
    在所述基底上制作多条引导凸部包括采用一次工艺成型一体结构的所述基底和所述基底上的所述多条引导凸部。
  11. 根据权利要求7所述的制备方法，其中，在所述基底上制作多条半导体纳米线作为有源层包括：
    在所述多条引导凸部的至少一个侧壁的一端制作引导颗粒；
    在所述多条引导凸部背离所述基底一侧沉积一层半导体材料，使得所述半导体材料在所述引导颗粒的引导下，沿着所述多条引导凸部的至少一个侧壁生长，形成所述半导体纳米线。
  12. 根据权利要求11所述的制备方法，其中，在所述多条引导凸部的至少一个侧壁的一端制作引导颗粒包括：
    在所述多条引导凸部的至少一个侧壁的一端，沉积引导材料，其中，所述引导材料与所述引导颗粒具有相同的化学元素；以及
    在等离子体增强化学气相沉积系统中，通过等离子体处理工艺，使所述引导材料转化为所述引导颗粒。
  13. 根据权利要求12所述的制备方法，其中，所述引导材料为氧化铟锡，所述引导颗粒为铟。
  14. 根据权利要求11至13中任一项所述的制备方法，其中，在所述多条引导凸部背离所述基底一侧沉积一层半导体材料，使得所述半导体材料在所述引导颗粒的引导下，沿着所述多条引导凸部的至少一个侧壁生长，形成所述半导体纳米线，包括：
    在180℃至220℃的温度下，在所述多条引导凸部背离所述基底一侧沉积一层半导体材料；
    在惰性还原气体条件下，在250℃至350℃的温度下，使得所述半导体材料在所述引导颗粒的引导下，沿着所述多条引导凸部的至少一个侧壁生长，形成所述半导体纳米线。
  15. 根据权利要求11所述的制备方法，其中，所述半导体材料包括非晶硅，所述半导体纳米线包括硅纳米线。
  16. 根据权利要求15所述的制备方法，其中，在惰性还原气体条件下，在250℃至350℃的温度下，使得所述半导体材料在所述引导颗粒的引导下，沿着所述引导凸部的至少一个侧壁生长，形成所述半导体纳米线之后，所述制备方法还包括：在180℃至220℃的温度下，通过退火工艺将所述非晶硅转换为多晶硅，然后将多晶硅清除。
  17. 根据权利要求16所述的制备方法，其中，在多晶硅清除之后，所述制备方法还包括：对所述半导体纳米线进行钝化处理。
  18. 一种阵列基板，包括驱动电路，所述驱动电路包括如权利要求1至6中任一项所述的薄膜晶体管。
  19. 一种显示面板，包括权利要求18所述的阵列基板。
  20. 根据权利要求19所述的显示面板，还包括有源矩阵有机发光二极管或无源矩阵有机发光二极管。
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