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WO2021258911A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2021258911A1
WO2021258911A1 PCT/CN2021/094032 CN2021094032W WO2021258911A1 WO 2021258911 A1 WO2021258911 A1 WO 2021258911A1 CN 2021094032 W CN2021094032 W CN 2021094032W WO 2021258911 A1 WO2021258911 A1 WO 2021258911A1
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WO
WIPO (PCT)
Prior art keywords
light
display area
display
display substrate
area
Prior art date
Application number
PCT/CN2021/094032
Other languages
English (en)
French (fr)
Inventor
黄耀
程羽雕
黄炜赟
龙跃
邱远游
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/772,559 priority Critical patent/US20220376029A1/en
Priority to EP21828244.0A priority patent/EP4053828A4/en
Priority to JP2022533553A priority patent/JP2023531575A/ja
Priority to KR1020227017338A priority patent/KR20230026979A/ko
Publication of WO2021258911A1 publication Critical patent/WO2021258911A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G09F9/335—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes being organic light emitting diodes [OLED]

Definitions

  • the embodiment of the present disclosure relates to a display substrate and a display device.
  • Organic Light-Emitting Diode (OLED) display devices have the characteristics of wide viewing angle, high contrast, fast response speed, wide color gamut, high screen-to-body ratio, self-luminous, thin and light. Due to the above-mentioned characteristics and advantages, organic light-emitting diode (OLED) display devices have gradually received widespread attention and can be applied to mobile phones, displays, notebook computers, smart watches, digital cameras, instrumentation, flexible wearable devices and other display functions. Device. With the further development of display technology, display devices with a high screen-to-body ratio can no longer meet people's needs, and display devices with a full screen have become the development trend of display technology in the future.
  • At least one embodiment of the present disclosure provides a display substrate having a first side for display and a second side opposite to the first side, and including a display area; the display area includes a first display area And a second display area, the second display area at least partially surrounds the first display area, the first display area and the second display area do not overlap each other; the first display area includes at least one first display area Light emitting element, and the first display area allows light from the first side to be at least partially transmitted to the second side; the second display area includes at least one first pixel circuit, the first light emitting element and The first pixel circuit is electrically connected; the display substrate is provided with at least one signal transmission line and at least one first dummy wiring, and the signal transmission line is at least partially located in the first display area and the second display area, The first light-emitting element is connected to the first pixel circuit through the signal transmission line, and the first dummy wiring is at least partially located in the first display area and is connected to the signal transmission line and the first light-emitting circuit.
  • the components are insulated, the signal transmission line and the first dummy trace respectively extend in a first direction, and the orthographic projection of the first dummy trace in a plane parallel to the display substrate is parallel to the signal transmission line
  • the orthographic projection in the plane of the display substrate is at least partially staggered.
  • the first dummy wiring and the signal transmission line are located on the same layer.
  • the first dummy trace and the signal transmission line both extend along a straight line and are parallel to each other.
  • the at least one first dummy trace includes a plurality of first dummy traces, and the plurality of first dummy traces extend along a direction different from the first direction.
  • the display substrate is arranged in the second direction and configured to receive the first voltage signal.
  • the display substrate further includes at least one second dummy trace.
  • the second dummy trace extends along the second direction and is connected to the plurality of first dummy traces.
  • the traces are electrically connected, so that the plurality of first dummy traces are electrically connected to each other to receive the first voltage signal.
  • At least one of the plurality of first dummy traces is electrically connected to the first power line that provides the first voltage signal through a via structure.
  • the second dummy wiring and the first dummy wiring are located on the same layer, or the second dummy wiring and the first dummy wiring are located on the same layer.
  • Different film layers, the different film layers are insulated from each other at positions where no vias are provided.
  • the at least one signal transmission line includes a plurality of signal transmission lines arranged along the second direction, and the plurality of signal transmission lines and the plurality of first dummy traces A wiring array is formed, a signal transmission line is used as a line unit in the wiring array, a first dummy wiring is used as a line unit in the wiring array, and at least one line unit in the wiring array is connected to the second line unit.
  • the distances between adjacent line units in the direction are equal.
  • the first display area includes a middle area and peripheral areas located on both sides of the middle area in the first direction.
  • the central axis is located in the intermediate area, the peripheral area is adjacent to the second display area, and the unit area distribution ratio of the plurality of first dummy traces in the intermediate area is greater than that of the plurality of first dummy traces.
  • the signal transmission line, the first dummy wiring, and the second dummy wiring respectively include transparent conductive wiring.
  • the signal transmission line communicates with the first light-emitting element through a via structure at least penetrating the insulating layer between the signal transmission line and the anode of the first light-emitting element.
  • the anode of the element is electrically connected.
  • the orthographic projection of the via structure in a plane parallel to the display substrate and the at least one first dummy trace are parallel to the display substrate.
  • the orthographic projections in the plane do not overlap each other.
  • the first pixel circuit includes a thin film transistor, the thin film transistor includes a gate, a first electrode, and a second electrode, and the signal transmission line is connected to the thin film transistor.
  • the first pole or the second pole is electrically connected.
  • a display substrate provided by an embodiment of the present disclosure further includes a source and drain metal layer, the first electrode and the second electrode of the thin film transistor are located on the source and drain metal layer, and the anode of the first light-emitting element is located on the On the source and drain metal layer, the film layer where the signal transmission line and the first dummy wiring are located is located between the anode of the first light-emitting element and the source and drain metal layer.
  • the display area further includes a third display area, the third display area at least partially surrounds the second display area, the first display area, the The second display area and the third display area do not overlap each other;
  • the second display area further includes at least one second light-emitting element and at least one second pixel circuit, the second light-emitting element and the second pixel circuit Electrical connection;
  • the third display area includes at least one third light-emitting element and at least one third pixel circuit, and the third light-emitting element is electrically connected to the third pixel circuit.
  • the first light-emitting element, the second light-emitting element, and the third light-emitting element each include an organic light-emitting diode.
  • the at least one first light-emitting element includes a plurality of first light-emitting elements
  • the at least one second light-emitting element includes a plurality of second light-emitting elements
  • the at least one The third light-emitting element includes a plurality of third light-emitting elements
  • the distribution density per unit area of the plurality of first light-emitting elements in the first display area is less than or equal to that of the plurality of second light-emitting elements in the second display area.
  • a distribution density per unit area in the region, where the distribution density per unit area of the plurality of second light-emitting elements in the second display region is smaller than the distribution density per unit area of the plurality of third light-emitting elements in the third display region density.
  • the orthographic projection of the at least one signal transmission line in a plane parallel to the display substrate and the at least one first dummy trace in the first display area is 70%-95%.
  • At least one embodiment of the present disclosure further provides a display device, which includes the display substrate according to any embodiment of the present disclosure.
  • the display device provided by an embodiment of the present disclosure further includes a sensor located on the second side of the display substrate and configured to receive light from the first side of the display substrate.
  • the orthographic projection of the sensor on the display substrate at least partially overlaps the first display area.
  • FIG. 1 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 2A is a schematic plan view of a first display area and a second display area of the display substrate shown in FIG. 1;
  • FIG. 2B is a schematic diagram of the arrangement of light-emitting elements and pixel circuits in the first display area and the second display area shown in FIG. 2A;
  • FIG. 3 is a schematic diagram of an example of the first display area and the second display area of the display substrate shown in FIG. 2A;
  • FIG. 4 is an enlarged view of a partial area REG1 in FIG. 3;
  • FIG. 5 is an enlarged view of a partial area REG2 in FIG. 3;
  • FIG. 6 is a schematic diagram of an example of a portion of a display substrate close to the edge of the display area provided by at least one embodiment of the present disclosure
  • FIG. 7 is a schematic diagram showing the light-transmitting area of the substrate.
  • FIG. 8 is a schematic diagram of a laminated structure of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 9 is an enlarged view of a partial area REG3 of the third display area of the display substrate shown in FIG. 1;
  • FIG. 10 is a schematic block diagram of a display device provided by at least one embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a laminated structure of a display device provided by at least one embodiment of the present disclosure.
  • the distribution density per unit area of the light-emitting elements corresponding to the display area of the under-screen sensors may be smaller than the distribution density per unit area of light-emitting elements in other display regions of the display substrate.
  • the arrangement of the light-emitting elements and corresponding pixel circuits in different regions is different.
  • the light-emitting elements corresponding to the display area of the under-screen sensor need to be electrically connected to corresponding pixel circuits located in other display areas, which makes it difficult to achieve uniform arrangement of the traces in the display area corresponding to the under-screen sensor.
  • This will affect the light transmittance of the display area corresponding to the sensor under the screen, for example, reduce the uniformity of the light passing through the area, which will cause the sensor under the screen to easily have problems such as reflection when receiving light, which is difficult to achieve accurately.
  • Operations such as image shooting, distance perception, and light intensity perception have an adverse effect on the performance of the display device using the display substrate.
  • At least one embodiment of the present disclosure provides a display substrate having a first side for display and a second side opposite to the first side, and including a display area;
  • the display area includes a first display area and a second display Area, the second display area at least partially surrounds the first display area, the first display area and the second display area do not overlap each other;
  • the first display area includes at least one first light-emitting element, and the first display area allows Light is at least partially transmitted to the second side;
  • the second display area includes at least one first pixel circuit, and the first light-emitting element is electrically connected to the first pixel circuit;
  • at least one signal transmission line and at least one first dummy wiring are provided on the display substrate ,
  • the signal transmission line is at least partially located in the first display area and the second display area, the first light-emitting element is connected to the first pixel circuit through the signal transmission line, and the first dummy wiring is at least partially located in the first display area and is connected to the signal transmission line and the second display area
  • a light-emitting element is insulated, the signal transmission line and the first dummy trace respectively extend along the first direction, the orthographic projection of the first dummy trace in a plane parallel to the display substrate and the orthographic projection of the signal transmission line in a plane parallel to the display substrate At least partially staggered.
  • the display substrate provided by at least one embodiment of the present disclosure can optimize the wiring design in the first display area, thereby improving the light transmittance of the first display area, and improving the uniformity and consistency of light passing through the first display area.
  • the first display area may be a display area corresponding to an under-screen sensor (such as a camera), so that the display substrate provided in the above-mentioned embodiments of the present disclosure can reduce or avoid possible light reflections that may occur when the under-screen sensor receives light. This problem helps the under-screen sensor to accurately implement operations such as image capture, distance perception, light intensity perception, etc., thereby helping to improve the performance of a display device (such as a full-screen display device) using the display substrate.
  • FIG. 1 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate 01 includes a display area 10
  • the display area 10 includes a first display area 11 and a second display area 12.
  • the first display area 11 and the second display area 12 do not overlap each other, and the second display area 12 at least partially surrounds (for example, completely surrounds) the first display area 11.
  • the display substrate 01 has a first side for display and a second side opposite to the first side.
  • the first side is the front side of the display substrate 01 (that is, the plane shown in FIG. 1)
  • the second side is the back side of the display substrate.
  • a sensor may be provided at a position corresponding to the first display area 11 on the second side of the display substrate 01, and the sensor may be, for example, an image sensor or an infrared sensor.
  • the sensor is configured to receive light from the first side of the display substrate 01, so that operations such as image shooting, distance sensing, and light intensity sensing can be performed.
  • FIG. 2A is a schematic plan view of the first display area and the second display area of the display substrate shown in FIG. 1, and FIG. 2B is the arrangement of light-emitting elements and pixel circuits in the first display area and the second display area shown in FIG. 2A Schematic.
  • the rectangular frame indicated by the reference number in FIG. 2B is only used to show the light-emitting elements and the pixel circuit. The approximate position of, and does not indicate the specific shape or specific boundary of the light-emitting element and pixel circuit, etc.; and, the rectangular frame in FIG.
  • 2B is only used to illustrate the arrangement of the light-emitting element and the pixel circuit, and does not indicate the first display area
  • the actual number of light-emitting elements and pixel circuits in the second display area, the specific structure of the light-emitting elements and pixel circuits, etc. can refer to conventional designs in the field, and the embodiments of the present disclosure do not limit this.
  • the second display area 12 at least partially surrounds (for example, completely surrounds) the first display area 11.
  • the shape of the first display area 11 may be a circle or an ellipse, and the shape of the second display area 12 may be a rectangle, but the embodiment of the present disclosure is not limited thereto.
  • the shapes of the first display area 11 and the second display area 12 may both be rectangles or other suitable shapes.
  • FIG. 3 is a schematic diagram of an example of the first display area and the second display area of the display substrate shown in FIG. 2A
  • FIG. 4 is an enlarged view of a partial area REG1 of FIG. 3
  • FIG. 5 is an enlarged view of a partial area REG2 of FIG. 3 picture. It should be noted that, in order to clearly and concisely describe the connection relationship between the first light-emitting element and the first pixel circuit, FIG. 5 only shows structures such as the light-emitting element, pixel circuit, signal transmission line, etc., but this does not constitute Restrictions on the embodiments of the present disclosure.
  • the first display area 11 includes at least one (for example, multiple) first light-emitting elements 411.
  • the first display area 11 includes a plurality of first light emitting elements 411 arranged in an array, and the first light emitting elements 411 are configured to emit light.
  • the first display area 11 there is no pixel circuit in the first display area 11, and a pixel circuit for driving the first light-emitting element 411 (that is, the first pixel circuit 412) is disposed in the second display area 12, thereby reducing the amount of the first display area 11.
  • the metal coverage area improves the light transmittance of the first display area 11.
  • the pixel circuit for driving the first light-emitting element 411 will be described below, and will not be repeated here.
  • the plurality of first light-emitting elements 411 may be arranged in a plurality of light-emitting units, and these light-emitting units are arranged in an array.
  • each light emitting unit may include one or more first light emitting elements 411.
  • the multiple first light-emitting elements 411 may emit light of the same color or light of different colors, for example, may emit white light, red light, blue light, green light, etc., which may be determined according to actual needs. No restrictions.
  • the arrangement of the plurality of first light-emitting elements 411 can refer to the conventional arrangement of pixel units, such as GGRB, RGBG, RGB, etc., which is not limited in the embodiment of the present disclosure.
  • the first display area 11 allows light from the first side of the display substrate 01 to be at least partially transmitted to the second side of the display substrate 01.
  • a sensor on the second side of the display substrate 01 and corresponding to the position of the first display area 11. Strong perception and other operations.
  • the second display area 12 includes at least one (for example, multiple) first pixel circuits 412, and the first light-emitting element 411 is electrically connected to the first pixel circuits 412.
  • the first light-emitting elements 411 and the first pixel circuits 412 are electrically connected in a one-to-one correspondence, and the plurality of first pixel circuits 412 are used to drive the plurality of first light-emitting elements 411 in a one-to-one correspondence. That is, one first pixel circuit 412 drives one corresponding first light-emitting element 411, and different first pixel circuits 412 drive different first light-emitting elements 411.
  • a plurality of first pixel circuits 412 may be arranged in a plurality of first pixel driving units. The rectangular frame shown in FIG. The pixel driving units are arranged in an array.
  • the first pixel driving unit may include one or more first pixel circuits 412.
  • the first pixel driving unit also includes a first pixel circuit 412.
  • the first pixel driving unit also includes a plurality of first pixel circuits 412, and the number of first light-emitting elements 411 in each light-emitting unit is, for example, It is equal to the number of first pixel circuits 412 in each first pixel driving unit, thereby achieving one-to-one corresponding driving.
  • the plurality of first light-emitting elements 411 are arranged in an array, and the plurality of first pixel circuits 412 are also arranged in an array.
  • array arrangement can refer to multiple devices being arranged in a group and multiple groups of device arrays, or it can refer to multiple devices themselves being arrayed, which is not limited in the embodiments of the present disclosure.
  • every four first light-emitting elements 411 is a group, and multiple groups of first light-emitting elements 411 are arranged in an array.
  • every fourth light-emitting element 411 is arranged in an array.
  • One pixel circuit 412 is a group, and multiple groups of first pixel circuits 412 are arranged in an array.
  • each first pixel driving unit includes four first pixel circuits 412.
  • At least one (for example, multiple) signal transmission lines 110 and at least one (for example, multiple) first dummy wires 121 are provided on the display substrate 01.
  • the signal transmission line 110 is at least partially located in the first display area 11 and the second display area 12, and the first light-emitting element 411 is connected 412 to the first pixel circuit through the signal transmission line 110.
  • the first end of the signal transmission line 110 is located in the first display area 11 and is electrically connected to the first light emitting element 411
  • the second end of the signal transmission line 110 is located in the second display area 12 and is electrically connected to the first pixel circuit 412
  • the electrical connection between the first light-emitting element 411 and the first pixel circuit 412 is achieved.
  • the first dummy wiring 121 is at least partially located in the first display area 11, for example, it may be located only in the first display area 11, or may extend to the second display area 12, and the first dummy wiring 121 and the signal transmission line 110 are connected to each other.
  • the first light emitting element 411 is insulated.
  • the signal transmission line 110 and the first dummy trace 121 respectively extend along the first direction R1, the orthographic projection of the first dummy trace 121 in a plane parallel to the display substrate 01 and the signal transmission line 110 in a plane parallel to the display substrate 01
  • the orthographic projection inside is at least partially staggered.
  • the wiring 121 and the signal transmission line 110 can respectively cover different areas of the first display area 11, thereby improving the uniformity and consistency of the wiring layout in the first display area 11, thereby improving the light transmittance of the first display area 11.
  • the uniformity and consistency of the light passing through the first display area 11 can also improve the etching uniformity of the display substrate 01 in the first display area 11.
  • the light-transmitting area LR of a display substrate shown in FIG. 7 since the distribution of wiring in the light-transmitting area LR is relatively uneven, the uniformity and consistency of the light passing through the light-transmitting area LR is reduced , which in turn causes the light transmission effect of the light transmission area LR to be seriously adversely affected.
  • the under-screen sensor set corresponding to the light-transmitting area LR is prone to problems such as light reflection when receiving light, which makes it difficult to accurately implement operations such as image shooting, distance sensing, and light intensity sensing.
  • the display substrate 01 provided by the above-mentioned embodiment of the present disclosure has a first dummy path that does not overlap the signal transmission line 110 in a plane parallel to the display substrate 01.
  • the line 121 can optimize the wiring design in the first display area 11, for example, improve the uniformity and consistency of the wiring layout in the first display area 11, thereby improving the uniformity and consistency of the light passing through the first display area 11 Therefore, the light transmittance of the first display area 11 is improved.
  • the display substrate 01 provided by the above-mentioned embodiment of the present disclosure can reduce or avoid problems such as light reflection that may occur when the under-screen sensor receives light, thereby It is helpful for the under-screen sensor to accurately implement operations such as image shooting, distance perception, light intensity perception, etc., thereby helping to improve the performance of the display device (for example, a full-screen display device) using the display substrate 01.
  • the orthographic projection of the signal transmission line 110 in the plane parallel to the display substrate 01 and the orthographic projection of the first dummy trace 121 in the plane parallel to the display substrate 01 in the first display area 11 The ratio of the area of the covered area to the area of the first display area 11 is 70%-95%, further for example 80%-90%, for example 75% or 85%. That is, the signal transmission line 110 and the first dummy wiring 121 as a whole can cover 70%-95% of the total area of the first display area 11 in a plane parallel to the display substrate 01, thereby further improving the first display area 11
  • the uniformity and consistency of the inner wiring layout improves the uniformity and consistency of the light passing through the first display area 11 and improves the light transmission effect of the first display area 11.
  • the first dummy wiring 121 and the signal transmission line 110 may be located on the same layer, thereby simplifying the preparation process of the display substrate 01 and reducing the cost of the display substrate 01. Preparation cost.
  • the first dummy trace and the signal transmission line may also be located in different layers; or, It is also possible that a part of the first dummy wiring is arranged on the same layer as the signal transmission line, and another part of the first dummy wiring is arranged on a layer different from the signal transmission line, which is not limited in the embodiment of the present disclosure.
  • being located on the “same layer” refers to being located on the same film layer.
  • the traces located in the same film layer can be prepared in the same process, for example, the required traces can be formed by one patterning process.
  • the distances between the traces in the same film layer and the base substrate are the same or substantially the same. That is, the distances between the traces in the film layer and the base substrate are the same or substantially the same.
  • the meaning of "located on the same layer" can refer to the above description, and will not be repeated.
  • different layers refer to different film layers, and these different film layers are insulated from each other at positions where no vias are provided.
  • the wires located in different film layers can be electrically connected by providing vias.
  • these different film layers are prepared in different processes.
  • the first process is used to prepare one of these different film layers, and then the second process is used to prepare the other of these different film layers.
  • a third process can also be used to prepare an insulating layer. Insulate each other.
  • the first process, the second process, and the third process may be the same or different.
  • the display substrate 01 includes a base substrate, in a direction perpendicular to the base substrate, different film layers have different distances from the base substrate. That is, among the different film layers, one film layer is closer to the base substrate, and the other film layer is farther from the base substrate.
  • the meaning of "located in a different layer" can refer to the above description, and will not be repeated.
  • the first dummy trace 121 and the signal transmission line 110 both extend along a straight line and are parallel to each other, thereby further benefiting the first dummy trace 121 and the signal transmission line 110.
  • the uniformity and consistency of the layout of the signal transmission line 110 in the first display area 11 can further simplify the process requirements of the display substrate 01, thereby facilitating the preparation of the display substrate 01.
  • the first dummy wiring 121 or the signal transmission line 110 may also be It extends along a curve, a broken line, or other suitable shapes, or the extension line of the first dummy trace 121 and the extension line of the signal transmission line 110 may intersect each other, which is not limited in the embodiment of the present disclosure.
  • the first dummy trace 121 may be configured to receive a first voltage signal (for example, a high-level signal or a low-level signal, the low-level signal is, for example, a ground signal), or may also be configured In order to be in a floating state, the embodiments of the present disclosure do not limit this.
  • the first dummy wiring 121 can also reduce or avoid signal crosstalk between the signal transmission lines 110, thereby improving the uniformity and uniformity of the circuit environment. Stability improves the signal transmission effect of the signal transmission line 110.
  • the plurality of first dummy traces 121 in the first display area 11 are arranged along a second direction R2 that is different from the first direction R1 and are configured to receive the first voltage signal .
  • the display substrate further includes at least one (for example, a plurality of) second dummy traces 122.
  • the second dummy traces 122 extend along the second direction R2 and are electrically connected to the plurality of first dummy traces 121, so that the plurality of first dummy traces
  • the wires 121 are electrically connected to each other to receive the first voltage signal. Therefore, the electrical connection effect between the plurality of first dummy traces 121 can be improved, and the uniformity and stability of the circuit environment can be further improved.
  • the included angle between the first direction R1 and the second direction R2 may be, for example, between 70° and 90°, and includes 70° and 90°.
  • the included angle between the first direction R1 and the second direction R2 is 70°, 75°, 85°, 90°, or 80°, etc.
  • the specific value of the included angle can be set according to actual conditions. This is not restricted.
  • At least one of the plurality of first dummy traces 121 may be electrically connected to the first power line that provides the first voltage signal through the via structure.
  • the first power line may be used to provide the first pixel circuit 412 with The power line for the first voltage signal for display can simplify the wiring layout of the display substrate 01 and optimize the structural design of the display substrate 01.
  • FIG. 6 is a schematic diagram of an example of a portion of a display substrate close to the edge of the display area provided by at least one embodiment of the present disclosure.
  • the portion shown in FIG. 6 may be located in the partial area REG4 shown in FIG. 3.
  • one of the plurality of first dummy traces 121 near the edge of the display substrate 01 in the second direction R2 is electrically connected to the first power line LVDD through the via structure H3 to receive the first voltage Signal, and transmit the received first voltage signal to other first dummy wiring 121 and/or second dummy wiring 122 through a second dummy wiring 122A connected to the first dummy wiring 121A.
  • the shape and position of the first power trace LVDD and the overlapping area with the first dummy trace 121A in FIG. 6 are only schematic illustrations. The specific shape, installation location, etc. are not restricted.
  • the first power trace LVDD may be electrically connected to only one first dummy trace 121A as shown in FIG. 6; while in some other embodiments of the present disclosure, the first power trace The LVDD may also be electrically connected to a plurality of first dummy traces 121A, such as 2, 3, or 4, which is not limited in the embodiment of the present disclosure.
  • the via structure H3 for achieving electrical connection between the first power trace LVDD and the first dummy trace 121A may include only one via as shown in FIG. 6; In some other embodiments, the via structure H3 for electrically connecting the first power trace LVDD and the first dummy trace 121A may also include 2, 3, or 4 vias.
  • the implementation of the present disclosure The example does not restrict this.
  • the second dummy trace 122 may be located on the same layer as the first dummy trace 121 as shown in FIG. 4, thereby simplifying the manufacturing process and reducing the manufacturing cost; or, in some other implementations of the present disclosure
  • the second dummy wiring 122 and the first dummy wiring 121 may also be located on a different layer.
  • the second dummy wiring 122 and the first dummy wiring 121 are located on different layers, and the different layers are not provided before.
  • the positions of the holes are insulated from each other to reduce or avoid signal crosstalk between traces. The embodiment of the present disclosure does not limit this.
  • the plurality of first dummy traces 121 are arranged along the second direction R2
  • the plurality of signal transmission lines 110 are arranged along the second direction R2
  • the plurality of signal transmission lines 110 and the plurality of A dummy wiring 121 constitutes a wiring array
  • a signal transmission line 110 is used as a line unit 140 in the wiring array
  • a first dummy wiring 121 is used as a line unit 140 in the wiring array
  • at least one line unit 140 in the wiring array is connected to The distances between adjacent line units 140 in the second direction R2 are equal.
  • the wiring design in the first display area 11 can be further optimized, and the uniformity and consistency of the wiring layout in the first display area 11 can be further improved, thereby further improving the uniformity of the light passing through the first display area 11 And consistency, and improve the light transmittance of the first display area 11.
  • each signal transmission line 110 is connected to two adjacent traces in the second direction R2 (the two traces may be the first
  • the distance between a dummy trace 121 and/or the signal transmission line 110) is equal, so that the uniformity and consistency of the trace layout in the first display area 11 can be improved, and the uniformity and stability of the circuit environment can also be improved. Thereby, the signal transmission effect of the signal transmission line 110 is improved.
  • the first display area 11 includes a middle area 1101 and a periphery located on both sides of the middle area 1101 in the first direction R1 (for example, completely surrounding the middle area 1101 in the first direction R1) Area 1102, the central axis L11 of the first display area 11 is located in the intermediate area 1101, the peripheral area 1102 is adjacent to the second display area 12, and the unit area distribution ratio of the multiple first dummy traces 121 in the intermediate area 1101 is greater than The distribution ratio per unit area of the first dummy trace 121 in the peripheral area 1102.
  • a plurality of first dummy traces The distribution ratio per unit area of 121 gradually increased. Since the unit area distribution ratio of the plurality of signal transmission lines 110 in the middle area 1101 is smaller than the unit area distribution ratio of the plurality of signal transmission lines 110 in the peripheral area 1102, for example, the area from the peripheral area 1102 to the middle area 1101 in the first display area 11 Direction, the unit area distribution ratio of the multiple signal transmission lines 110 gradually decreases.
  • the first dummy wiring 121 is distributed in the first display area 11 in a manner similar to that of the signal transmission line 110.
  • the distribution method in the first display area 11 is matched, thereby further optimizing the wiring design in the first display area 11, and further improving the uniformity and consistency of the wiring layout in the first display area 11, thereby further improving the transmission
  • the uniformity and consistency of the light in the first display area 11 improves the light transmittance of the first display area 11.
  • the above-mentioned “distribution ratio per unit area” refers to the distribution area of the trace in a unit area, that is, the larger the distribution ratio per unit area, the larger the area covered by the trace in the unit area, for example,
  • the denser the distribution of traces in the corresponding area the greater the number; the smaller the unit area distribution ratio, the smaller the area covered by the traces in the unit area area, for example,
  • the sparser and fewer wires are distributed in the corresponding area.
  • the signal transmission line 110, the first dummy wiring 121, and the second dummy wiring 122 may respectively include transparent conductive wiring, so that the light transmission of the first display area 11 of the display substrate 01 may be further improved. Rate.
  • the transparent conductive trace can be made of, for example, indium tin oxide (ITO) or other suitable transparent conductive materials.
  • the width of the first dummy trace 121 in the second direction R2 is the same as the width of the signal transmission line 110 in the second direction R2, so that the first dummy trace in the first display area 11 can be further improved.
  • the uniformity and consistency of the distribution of the dummy wiring 121 and the signal transmission line 110 can also improve the uniformity and stability of the circuit environment, thereby improving the signal transmission effect of the signal transmission line 110.
  • the signal transmission line 110 passes through a via structure H1 that penetrates at least the insulating layer between the signal transmission line 110 and the anode of the first light emitting element 411 and
  • the anode of the first light-emitting element 411 is electrically connected to provide an electrical signal to the first light-emitting element 411 to drive the first light-emitting element 411 to emit light.
  • the orthographic projection of the via structure H1 in a plane parallel to the display substrate 01 and the orthographic projection of the first dummy trace 121 in a plane parallel to the display substrate 01 do not overlap each other, for example, in a direction perpendicular to the display substrate 01
  • the first dummy wiring 121 is arranged as far as possible to avoid the position of the via structure H1. In this way, the possible interference of the first dummy wiring 121 on the electrical signal provided to the first light-emitting element 411 can be reduced or avoided, thereby improving the stability of the operation of the first light-emitting element 411 and improving the light emission of the first light-emitting element 411 Effect.
  • the via structure H1 can also penetrate through other film layers or structures between the signal transmission line 110 and the anode of the first light-emitting element 411 except the insulating layer to realize the signal transmission line.
  • the electrical connection between 110 and the anode of the first light-emitting element 411 is not limited in the embodiment of the present disclosure.
  • the first pixel circuit 412 includes a thin film transistor
  • the thin film transistor includes a gate, a first electrode, and a second electrode
  • the signal transmission line 110 is electrically connected to the first electrode or the second electrode of the thin film transistor, thereby connecting the first pixel circuit 412
  • the output signal of is provided to the first light emitting element 411.
  • the thin film transistor may be a driving thin film transistor in the first pixel circuit 412, or a light emission control thin film transistor in the first pixel circuit 412, or other types of thin film transistors.
  • FIG. 8 is a schematic diagram of a laminated structure of a display substrate provided by at least one embodiment of the present disclosure.
  • the schematic diagram of the laminated structure mainly schematically shows a part of the structure of the first pixel circuit 412 and the first light-emitting element 411.
  • FIG. 8 may be a schematic diagram showing the cross-sectional structure of the substrate 01 along the line A-A' shown in FIG. 5.
  • the display substrate 01 includes a source and drain metal layer (SD layer) on the base substrate 101, and the first electrode and the second electrode of the thin film transistor 412T of the first pixel circuit 412 ( That is, the source and drain electrodes, such as the source 4123 and the drain 4124, are located on the source and drain metal layer.
  • SD layer source and drain metal layer
  • the first light-emitting element 411 includes an anode 4111, a cathode 4113, and a first light-emitting layer 4112 located between the anode 4111 and the cathode 4113.
  • the anode 4111 of the first light-emitting element 411 is located on the source and drain metal layer.
  • the film layer where the dummy wiring 121 (not shown in FIG. 8) is located is between the anode 4111 of the first light-emitting element 411 and the source and drain metal layers.
  • the anode 4111 is electrically connected to the signal transmission line 110 through the via structure H1, and further is electrically connected to the thin film transistor 412T included in the first pixel circuit 412 through the signal transmission line 110.
  • the anode 4111 may include multiple anode sub-layers, for example, a three-layer structure of ITO/Ag/ITO (not labeled in the figure), etc.
  • the specific form of the anode 4111 is not limited in the embodiment of the present disclosure.
  • the cathode 4113 may be a structure formed on the entire surface of the display substrate 01, and the cathode 4113 may include, for example, metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
  • the cathode 4113 can be formed as a very thin layer, the cathode 4113 has good light transmittance.
  • the thin film transistor 412T includes an active layer 4121, a gate 4122, and source and drain electrodes (ie, a source 4123 and a drain 4124) and other structures.
  • the active layer 4121 is disposed on the base substrate 101
  • the first gate insulating layer 741 is disposed on the side of the active layer 4121 away from the base substrate 101.
  • the gate 4122 is located on the side of the first gate insulating layer 741 away from the base substrate 101, and the side of the gate 4122 away from the base substrate 101 is provided with a second gate insulating layer 742.
  • the source and drain electrodes are arranged on the side of the interlayer insulating layer 743 away from the base substrate 101, and pass through the via holes and the active layer in the first gate insulating layer 741, the second gate insulating layer 742, and the interlayer insulating layer 743. 4121 electrical connection.
  • a planarization layer 744 is provided on the side of the source and drain electrodes away from the base substrate 101 to planarize the first pixel circuit 412.
  • the planarization layer 744 has a via H2, and the drain 4124 (or source 4123) of the thin film transistor 412T is electrically connected to the signal transmission line 110 through the via H2 in the planarization layer 744, and then is connected to the anode 4111 through the signal transmission line 110 Electric connection.
  • the first display area 11 further includes a transparent support layer 78 on the base substrate 101, and the first light-emitting element 411 is located on the side of the transparent support layer 78 away from the base substrate 101. Therefore, with respect to the base substrate 101, the first light-emitting element 411 in the first display area 11 can be combined with the second light-emitting element in the second display area 12 (refer to the following about the second display area 12 and the second light-emitting element).
  • the description of the two light-emitting elements 412) and the third light-emitting element in the third display area are at substantially the same height, so that the display substrate 01 can be improved. The display effect.
  • the display substrate 01 further includes a pixel defining layer 746, an encapsulation layer 747 and other structures.
  • the pixel defining layer 746 is disposed on the anode 4111 (for example, a partial structure of the anode 4111), and includes a plurality of openings to define different pixels or sub-pixels, and the first light-emitting layer 4112 is formed in the openings of the pixel defining layer 746.
  • the encapsulation layer 747 may include a single-layer or multi-layer encapsulation structure, for example, the multilayer encapsulation structure includes a stack of an inorganic encapsulation layer and an organic encapsulation layer, thereby improving the encapsulation effect on the display substrate 01.
  • the base substrate 101 may be a glass substrate, a quartz substrate, a metal substrate, or a resin substrate, etc., and may be a rigid substrate or a flexible substrate.
  • the embodiment of the present disclosure does not limit this.
  • the first gate insulating layer 741, the second gate insulating layer 742, the interlayer insulating layer 743 and the planarization layer 744, the insulating layer 745, the pixel defining layer 746, and the encapsulation layer 747 may include silicon oxide, silicon nitride, Inorganic insulating materials such as silicon oxynitride, or may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenol resin.
  • the embodiments of the present disclosure do not specifically limit the materials of the above-mentioned functional layers.
  • the material of the active layer 4121 may include semiconductor materials such as polysilicon or oxide semiconductor (for example, indium gallium zinc oxide).
  • the part of the active layer 4121 may be conductive through a conductive process such as doping, so as to have higher conductivity.
  • the material of the gate 4122 may include metal materials or alloy materials, such as molybdenum, aluminum, and titanium.
  • the material of the source electrode 4123 and the drain electrode 4124 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, etc.
  • the multi-layer structure is a multi-metal laminated layer, such as Titanium, aluminum, titanium three-layer metal laminate (Ti/Al/Ti), etc.
  • the display area 10 further includes a third display area 13.
  • the third display area 13 at least partially surrounds (eg partially surrounds) the second display area 12, and the first display area 11 , The second display area 12 and the third display area 13 do not overlap each other.
  • the display substrate 01 may further include a peripheral area that at least partially surrounds the third display area 13.
  • the second display area 12 further includes at least one (e.g., multiple) second light-emitting elements 421 and at least one (e.g., multiple) second pixel circuits 422.
  • the second light-emitting elements 421 and The second pixel circuit 422 is electrically connected, for example, in a one-to-one correspondence.
  • the second pixel circuit 422 is used to drive the second light-emitting element 421 to emit light.
  • the rectangular frame indicated by the reference number 422 in FIG. 5 is only used to show the approximate position of the second pixel circuit 422, and does not indicate the specific shape of the second pixel circuit 422 and the specific boundary of the second pixel circuit 422. .
  • a plurality of second light emitting elements 421 are arranged in an array, and a plurality of second pixel circuits 422 are also arranged in an array.
  • at least one second light-emitting element 421 and its corresponding second pixel circuit 422 constitute a second pixel driving unit 42.
  • the second pixel driving unit 42 may include a second pixel circuit 422 and a second light-emitting element 421, or may include a plurality of second pixel circuits 422 and a plurality of second light-emitting elements 421.
  • the second pixel driving unit 42 includes a plurality of second pixel circuits 422 and a plurality of second light-emitting elements 421
  • the number of second pixel circuits 422 in each second pixel driving unit 42 is, for example, equal to that of the second light-emitting elements 421. Quantity, which realizes one-to-one correspondence drive.
  • a plurality of second light emitting elements 421 are arranged in an array, and a plurality of second pixel circuits 422 are also arranged in an array.
  • array arrangement may refer to multiple devices being arranged in a group and multiple sets of device arrays, or it may refer to multiple devices themselves being arrayed, which is not limited in the embodiments of the present disclosure.
  • every four second light-emitting elements 421 form a group, and multiple groups of second light-emitting elements 421 are arranged in an array.
  • every four second pixel circuits 422 are one group. Groups, multiple groups of second pixel circuits 422 are arranged in an array.
  • each second pixel driving unit 42 includes four second pixel circuits 422 and four second light-emitting elements 421.
  • FIG. 9 is an enlarged view of a partial area REG3 of the third display area 13 of the display substrate shown in FIG. 1.
  • the third display area 13 includes at least one (for example, a plurality of) third light-emitting elements 431 and at least one (for example, a plurality of) third pixel circuits 432, the third light-emitting elements 431 and the third pixel circuit 432 is electrically connected, for example, in a one-to-one correspondence, and the third pixel circuit 432 is used to drive the third light-emitting element 431 to emit light.
  • the rectangular frame indicated by the reference number 432 in FIG. 9 is only used to show the approximate position of the third pixel circuit 432, and does not indicate the specific shape of the third pixel circuit 432 and the specific boundary of the third pixel circuit 432. .
  • a plurality of third light emitting elements 431 are arranged in an array, and a plurality of third pixel circuits 432 are also arranged in an array.
  • at least one third light-emitting element 431 and its corresponding third pixel circuit 432 constitute a third pixel driving unit 43.
  • the third pixel driving unit 43 may include a third pixel circuit 432 and a third light-emitting element 431, or may include a plurality of third pixel circuits 432 and a plurality of third light-emitting elements 431.
  • the third pixel driving unit 43 includes a plurality of third pixel circuits 432 and a plurality of third light-emitting elements 431
  • the number of third pixel circuits 432 in each third pixel driving unit 43 is, for example, equal to that of the third light-emitting element 431. Quantity, which realizes one-to-one correspondence drive.
  • a plurality of third light emitting elements 431 are arranged in an array, and a plurality of third pixel circuits 432 are also arranged in an array.
  • array arrangement may refer to multiple devices being arranged in a group and multiple sets of device arrays, or it may refer to multiple devices themselves being arrayed, which is not limited in the embodiments of the present disclosure.
  • every four third light-emitting elements 431 form a group, and multiple groups of third light-emitting elements 431 are arranged in an array.
  • every four third pixel circuits 432 are one group. Groups of third pixel circuits 432 are arranged in an array.
  • each third pixel driving unit 43 includes four third pixel circuits 432 and four third light-emitting elements 431.
  • the distribution density per unit area of the plurality of first light-emitting elements 411 in the first display area 11 is smaller than the distribution density per unit area of the plurality of second light-emitting elements 421 in the second display area 12;
  • the distribution density per unit area of the light emitting element 421 is smaller than the distribution density per unit area of the plurality of third light emitting elements 431 in the third display area 13.
  • the first display area 11 and the second display area 12 may be referred to as a low-resolution area of the display substrate 01, and correspondingly, the third display area 13 may be referred to as a high-resolution area of the display substrate 01.
  • the sum of the pixel light-emitting area of the second display area 12 and the first display area 11 may be 1/8 to 1/2 of the pixel light-emitting area of the third display area 13.
  • the distribution density per unit area of the plurality of first light-emitting elements 411 in the first display area 11 may also be equal to the distribution density per unit area of the plurality of second light-emitting elements 421 in the second display area 12. This may be determined according to actual requirements, and the embodiments of the present disclosure do not limit this.
  • the display substrate 01 By increasing the distribution density per unit area of the light-emitting elements in the first display area 11, the second display area 12, and the third display area 13, it is possible to facilitate the display substrate 01 while ensuring that the three display areas emit light normally to display images.
  • the light on the first side of the first display area 11 passes through the first display area 11 to reach the second side, thereby facilitating the sensor provided on the second side of the display substrate 01 to sense the light.
  • the first light emitting element 411, the second light emitting element 421, and the third light emitting element 431 each include an organic light emitting diode (OLED).
  • OLED organic light emitting diode
  • the embodiments of the present disclosure are not limited thereto.
  • the first light-emitting element 411, the second light-emitting element 421, and the third light-emitting element 431 may also be quantum dot light-emitting diodes (QLEDs) or other applicable light-emitting devices. There is no restriction on this.
  • QLEDs quantum dot light-emitting diodes
  • the display substrate 01 provided by the embodiment of the present disclosure may be an organic light emitting diode (OLED) display substrate or a quantum dot light emitting diode (QLED) display substrate, etc.
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • the embodiment of the present disclosure does not limit the specific type of the display substrate.
  • the light-emitting layer (for example, the aforementioned first light-emitting layer 4112) may include small molecular organic materials or polymer molecular organic materials, may be fluorescent light-emitting materials or phosphorescent light-emitting materials, and may It emits red light, green light, blue light, or white light.
  • the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light-emitting layer may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, and cadmium sulfide quantum dots. , Cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc.
  • the particle size of the quantum dots is, for example, 2nm ⁇ 20nm.
  • At least one embodiment of the present disclosure further provides a display device, which includes the display substrate provided by any embodiment of the present disclosure.
  • FIG. 10 is a schematic block diagram of a display device provided by at least one embodiment of the present disclosure.
  • the display device 30 includes a display substrate 310, and the display substrate 310 may be a display substrate provided by any embodiment of the present disclosure, such as the aforementioned display substrate 01.
  • the display device 30 can be any electronic device with a display function, such as a smart phone, a notebook computer, a tablet computer, a TV, and the like.
  • the smart phone or tablet computer may have a full-screen design, that is, it does not surround, for example, the first display area 11, the second display area 12, or the third display area 13.
  • the surrounding area the smart phone or tablet computer also has an under-screen sensor (such as a camera, an infrared sensor, etc.), which can perform operations such as image shooting, distance sensing, and light intensity sensing.
  • FIG. 11 is a schematic diagram of a laminated structure of a display device provided by at least one embodiment of the present disclosure.
  • the display device 30 includes a display substrate 310, and the display substrate 310 may be a display substrate provided by any embodiment of the present disclosure, such as the aforementioned display substrate 01.
  • the display device 30 further includes a sensor 320.
  • the display substrate 01 includes a first side F1 for display and a second side F2 opposite to the first side F1. That is, the first side F1 is the display side, and the second side F2 is the non-display side.
  • the display substrate 01 is configured to perform a display operation on the first side F1, that is, the first side F1 of the display substrate 01 is the light emitting side of the display substrate 01, and the first side F1 faces the user.
  • the first side F1 and the second side F2 are opposed to each other in the normal direction of the display surface of the display substrate 01.
  • the sensor 320 is disposed on the second side F2 of the display substrate 01, and the sensor 320 is configured to receive light from the first side F1.
  • the sensor 320 and the first display area 11 are overlapped in the normal direction of the display surface of the display substrate 01 (for example, the direction perpendicular to the display substrate 01), and the sensor 320 may receive and process the data passing through the first display area 11.
  • the optical signal may be visible light, infrared light, etc.
  • the first display area 11 allows light from the first side F1 to be at least partially transmitted to the second side F2.
  • the first display area 11 is not provided with a pixel circuit. In this case, the light transmittance of the first display area 11 can be improved.
  • the orthographic projection of the sensor 320 on the display substrate 01 at least partially overlaps the first display area 11.
  • the orthographic projection of the sensor 320 on the display substrate 01 is located in the first display area 11.
  • the orthographic projection of the sensor 320 on the display substrate 01 is the same as that of the first display. Area 11 partially overlaps. At this time, since the light can propagate to the sensor 320 laterally, it is not necessary that the sensor 320 is completely located at a position corresponding to the first display area 11.
  • the first display area 11 can be reduced.
  • the element in the shielding of the light signal incident to the first display area 11 and irradiated to the sensor 320 can improve the signal-to-noise ratio of the image output by the sensor 320.
  • the first display area 11 may be referred to as a high light transmission area of a low resolution area of the display substrate 01.
  • the sensor 320 may be an image sensor, which may be used to collect an image of the external environment facing the light-collecting surface of the sensor 320, and may be, for example, a CMOS image sensor or a CCD image sensor.
  • the sensor 320 may also be an infrared sensor, a distance sensor, or the like.
  • the display device 30 is a mobile terminal such as a mobile phone, a notebook, etc.
  • the sensor 320 can be implemented as a camera of a mobile terminal such as a mobile phone, a notebook, etc., and may also include, for example, a lens, a mirror, or an optical waveguide as required.
  • Optical devices to modulate the optical path may be an image sensor, which may be used to collect an image of the external environment facing the light-collecting surface of the sensor 320, and may be, for example, a CMOS image sensor or a CCD image sensor.
  • the sensor 320 may also be an infrared sensor, a distance sensor, or the like.
  • the sensor 320 may include photosensitive pixels arranged in an array.
  • each photosensitive pixel may include a photosensitive detector (for example, a photodiode, a phototransistor) and a switching transistor (for example, a switching thin film transistor).
  • the photodiode can convert the light signal irradiated on it into an electrical signal
  • the switching transistor can be electrically connected with the photodiode to control whether the photodiode is in the state of collecting the light signal and the time for collecting the light signal.
  • the anode of the first light-emitting element 411 adopts a stacked structure of ITO/Ag/ITO.
  • the first display area 11 only the anode of the first light-emitting element 411 does not transmit light, that is, it is used for
  • the wiring for driving the first light-emitting element 411 (for example, the above-mentioned signal transmission line 110) and the wiring that is insulated from each other with the first light-emitting element 411 (for example, the above-mentioned first dummy wiring 121 or the second dummy wiring 122) are set to be transparent Traces.
  • the light transmittance of the first display area 11 be further improved, but also the uniformity and consistency of the light passing through the first display area 11 can be improved, thereby reducing or avoiding the possibility of the sensor 320 receiving light.
  • the occurrence of problems such as light reflection helps the sensor 320 to accurately implement operations such as image shooting, distance perception, light intensity perception, etc., and helps improve the performance of the display device 30 (for example, a full-screen display device).
  • the display device 30 may further include more components and structures, which are not limited in the embodiments of the present disclosure.
  • the technical effects and detailed description of the display device 30 reference may be made to the above description of the display substrate 01, which will not be repeated here.
  • the above-mentioned display device 30 may be any product or component with a display function, such as a display substrate, a display panel, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • a display function such as a display substrate, a display panel, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • the display device 30 refers to the corresponding content in the display substrate provided in the embodiments of the present disclosure.

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Abstract

一种显示基板及显示装置，该显示基板（01）具有用于显示的第一侧和与第一侧相对的第二侧，且包括显示区域（10）；显示区域（10）包括第一显示区域（11）和第二显示区域（12）；第一显示区域（11）包括第一发光元件（411），且第一显示区域（11）允许来自第一侧的光至少部分透射至第二侧；第二显示区域（12）包括第一像素电路（412），第一发光元件（411）与第一像素电路（412）电连接；显示基板（01）上设有信号传输线（110）和第一虚设走线（121），第一发光元件（411）通过信号传输线（110）与第一像素电路（412）连接，第一虚设走线（121）至少部分位于第一显示区域（11）内，且与信号传输线（110）和第一发光元件（411）绝缘，第一虚设走线（121）在平行于显示基板（01）的平面内的正投影与信号传输线（110）在平行于显示基板（01）的平面内的正投影至少部分错开。该显示基板可以提升从第一侧透射至第二侧的光的均匀性。

Description

显示基板及显示装置
本申请要求于2020年6月22日递交的中国专利申请第202010574224.9号的优先权，该中国专利申请的全文以引入的方式并入以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板及显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示器件具有视角宽、对比度高、响应速度快、色域广、屏占比高、自发光、轻薄等特点。由于具有上述特点和优势，有机发光二极管(OLED)显示器件逐渐受到人们的广泛关注并且可以适用于手机、显示器、笔记本电脑、智能手表、数码相机、仪器仪表、柔性可穿戴装置等具有显示功能的装置。随着显示技术的进一步发展，具有高屏占比的显示装置已经不能满足人们的需求，具有全面屏的显示装置成为未来显示技术的发展趋势。
发明内容
本公开至少一个实施例提供一种显示基板，该显示基板具有用于显示的第一侧和与所述第一侧相对的第二侧，且包括显示区域；所述显示区域包括第一显示区域和第二显示区域，所述第二显示区域至少部分围绕所述第一显示区域，所述第一显示区域和所述第二显示区域互不重叠；所述第一显示区域包括至少一个第一发光元件，且所述第一显示区域允许来自所述第一侧的光至少部分透射至所述第二侧；所述第二显示区域包括至少一个第一像素电路，所述第一发光元件与所述第一像素电路电连接；所述显示基板上设有至少一条信号传输线和至少一条第一虚设走线，所述信号传输线至少部分位于所述第一显示区域和所述第二显示区域，所述第一发光元件通过所述信号传输线与所述第一像素电路连接，所述第一虚设走线至少部分位于所述第一显示区域内，且与所述信号传输线和所述第一发光元件绝缘，所述信号传输线和所述第一虚设走线分别沿第一方向延伸，所述第一虚设走线在平行于所述显示基板的平面内的正投影与所述信号传输线在平行于所述显示基板的平面内的正投影至少部分错开。
例如，在本公开一实施例提供的显示基板中，所述第一虚设走线与所述信号传输线位于同一层。
例如，在本公开一实施例提供的显示基板中，所述第一虚设走线与所述信号传输线均沿直线延伸且彼此平行。
例如，在本公开一实施例提供的显示基板中，所述至少一条第一虚设走线包括多条第一虚设走线，所述多条第一虚设走线沿不同于所述第一方向的第二方向排列且配置为 接收第一电压信号，所述显示基板还包括至少一条第二虚设走线，所述第二虚设走线沿所述第二方向延伸且与所述多条第一虚设走线电连接，以使所述多条第一虚设走线彼此电连接以接收所述第一电压信号。
例如，在本公开一实施例提供的显示基板中，所述多条第一虚设走线中的至少一条通过过孔结构与提供所述第一电压信号的第一电源线电连接。
例如，在本公开一实施例提供的显示基板中，所述第二虚设走线与所述第一虚设走线位于同一层，或所述第二虚设走线与所述第一虚设走线位于不同的膜层，所述不同的膜层在未设置过孔的位置彼此绝缘。
例如，在本公开一实施例提供的显示基板中，所述至少一条信号传输线包括沿所述第二方向排列的多条信号传输线，所述多条信号传输线和所述多条第一虚设走线构成布线阵列，一条信号传输线作为所述布线阵列中的一个线条单元，一条第一虚设走线作为所述布线阵列中的一个线条单元，所述布线阵列中至少一个线条单元与在所述第二方向上相邻的线条单元之间的距离相等。
例如，在本公开一实施例提供的显示基板中，所述第一显示区域包括中间区域和在所述第一方向上位于所述中间区域的两侧的周边区域，所述第一显示区域的中轴线位于所述中间区域内，所述周边区域与所述第二显示区域相邻，所述多条第一虚设走线在所述中间区域内的单位面积分布比大于所述多条第一虚设走线在所述周边区域内的单位面积分布比。
例如，在本公开一实施例提供的显示基板中，所述信号传输线、所述第一虚设走线和所述第二虚设走线分别包括透明导电走线。
例如，在本公开一实施例提供的显示基板中，所述第一虚设走线在不同于所述第一方向的第二方向上的宽度与所述信号传输线在所述第二方向上的宽度相同。
例如，在本公开一实施例提供的显示基板中，所述信号传输线通过至少贯穿位于所述信号传输线和所述第一发光元件的阳极之间的绝缘层的过孔结构与所述第一发光元件的阳极电连接。
例如，在本公开一实施例提供的显示基板中，所述过孔结构在平行于所述显示基板的平面内的正投影与所述至少一条第一虚设走线在平行于所述显示基板的平面内的正投影互不重叠。
例如，在本公开一实施例提供的显示基板中，所述第一像素电路包括薄膜晶体管，所述薄膜晶体管包括栅极、第一极和第二极，所述信号传输线与所述薄膜晶体管的第一极或第二极电连接。
例如，本公开一实施例提供的显示基板还包括源漏极金属层，所述薄膜晶体管的第一极和第二极位于所述源漏极金属层，所述第一发光元件的阳极位于所述源漏极金属层之上，所述信号传输线和所述第一虚设走线所在的膜层位于所述第一发光元件的阳极与所述源漏极金属层之间。
例如，在本公开一实施例提供的显示基板中，所述显示区域还包括第三显示区域， 所述第三显示区域至少部分围绕所述第二显示区域，所述第一显示区域、所述第二显示区域和所述第三显示区域互不重叠；所述第二显示区域还包括至少一个第二发光元件和至少一个第二像素电路，所述第二发光元件与所述第二像素电路电连接；所述第三显示区域包括至少一个第三发光元件和至少一个第三像素电路，所述第三发光元件与所述第三像素电路电连接。
例如，在本公开一实施例提供的显示基板中，所述第一发光元件、所述第二发光元件和所述第三发光元件分别包括有机发光二极管。
例如，在本公开一实施例提供的显示基板中，所述至少一个第一发光元件包括多个第一发光元件，所述至少一个第二发光元件包括多个第二发光元件，所述至少一个第三发光元件包括多个第三发光元件，所述多个第一发光元件在所述第一显示区域内的单位面积分布密度小于或等于所述多个第二发光元件在所述第二显示区域内的单位面积分布密度，所述多个第二发光元件在所述第二显示区域内的单位面积分布密度小于所述多个第三发光元件在所述第三显示区域内的单位面积分布密度。
例如，在本公开一实施例提供的显示基板中，所述第一显示区域中被所述至少一条信号传输线在平行于所述显示基板的平面内的正投影和所述至少一条第一虚设走线在平行于所述显示基板的平面内的正投影覆盖的区域的面积与所述第一显示区域的面积之比为70％～95％。
本公开至少一个实施例还提供一种显示装置，该显示装置包括本公开任一实施例所述的显示基板。
例如，本公开一实施例提供的显示装置还包括传感器，所述传感器位于所述显示基板的第二侧，且配置为接收来自所述显示基板的第一侧的光。
例如，在本公开一实施例提供的显示装置中，所述传感器在所述显示基板上的正投影与所述第一显示区域至少部分重叠。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开至少一个实施例提供的一种显示基板的平面示意图；
图2A为图1所示的显示基板的第一显示区域和第二显示区域的平面示意图；
图2B为图2A所示的第一显示区域和第二显示区域的发光元件和像素电路的排布示意图；
图3为图2A所示的显示基板的第一显示区域和第二显示区域的一个示例的示意图；
图4为图3的部分区域REG1的放大图；
图5为图3的部分区域REG2的放大图；
图6为本公开至少一个实施例提供的一种显示基板的靠近显示区域的边缘的部分的一个示例的示意图；
图7为一种显示基板的透光区域的示意图；
图8为本公开至少一个实施例提供的一种显示基板的叠层结构示意图；
图9为图1所示的显示基板的第三显示区域的部分区域REG3的放大图；
图10为本公开至少一个实施例提供的一种显示装置的示意框图；以及
图11为本公开至少一个实施例提供的一种显示装置的叠层结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
对于当前的具有屏下传感器(例如，摄像头)的显示基板，为了提高显示基板的对应于屏下传感器的显示区域的透光率，对应于屏下传感器的显示区域的发光元件的单位面积分布密度(PPI)可以小于显示基板的其它显示区域的发光元件的单位面积分布密度。
然而，由于显示基板上不同区域的发光元件的单位面积分布密度不同，导致不同区域的发光元件及相应的像素电路的设置方式不同。例如，对应于屏下传感器的显示区域的发光元件需要与位于其他显示区域的相应的像素电路电连接，从而导致对应于屏下传感器的显示区域内的走线难以实现均匀排布。这会影响对应于屏下传感器的显示区域的透光率，例如使透过该区域的光线的均匀性降低，进而导致屏下传感器在接收光线时容易出现例如反光等问题，从而难以准确地实现图像拍摄、距离感知、光强感知等操作，对采用该显示基板的显示装置的性能产生不利影响。
本公开至少一个实施例提供一种显示基板，该显示基板具有用于显示的第一侧和与第一侧相对的第二侧，且包括显示区域；显示区域包括第一显示区域和第二显示区域，第二显示区域至少部分围绕第一显示区域，第一显示区域和第二显示区域互不重叠；第一显示区域包括至少一个第一发光元件，且第一显示区域允许来自第一侧的光至少部分透射至第二侧；第二显示区域包括至少一个第一像素电路，第一发光元件与第一像素电 路电连接；显示基板上设有至少一条信号传输线和至少一条第一虚设走线，信号传输线至少部分位于第一显示区域和第二显示区域，第一发光元件通过信号传输线与第一像素电路连接，第一虚设走线至少部分位于第一显示区域内，且与信号传输线和第一发光元件绝缘，信号传输线和第一虚设走线分别沿第一方向延伸，第一虚设走线在平行于显示基板的平面内的正投影与信号传输线在平行于显示基板的平面内的正投影至少部分错开。
本公开上述至少一个实施例提供的显示基板可以优化第一显示区域内的走线设计，从而改善第一显示区域的透光率，提升透过第一显示区域的光线的均匀性和一致性。例如，该第一显示区域可以为对应于屏下传感器(例如摄像头)的显示区域，由此本公开上述实施例提供的显示基板可以减弱或避免屏下传感器在接收光线时可能出现的例如反光等问题，从而有助于屏下传感器准确地实现图像拍摄、距离感知、光强感知等操作，进而有助于提高采用该显示基板的显示装置(例如全面屏显示装置)的性能。
下面，将参考附图详细地说明本公开的实施例。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
图1为本公开至少一个实施例提供的一种显示基板的平面示意图。如图1所示，该显示基板01包括显示区域10，显示区域10包括第一显示区域11和第二显示区域12。例如，第一显示区域11和第二显示区域12互不重叠，第二显示区域12至少部分围绕(例如，完全围绕)第一显示区域11。
例如，该显示基板01具有用于显示的第一侧和与第一侧相对的第二侧。例如，在一些示例中，如图1所示，第一侧为显示基板01的正侧(也即图1所示的平面)，第二侧为显示基板的背侧。例如，可以在显示基板01的第二侧对应于第一显示区域11的位置设置传感器，该传感器例如为图像传感器或红外传感器等。该传感器配置为接收来自显示基板01的第一侧的光线，从而可以进行图像拍摄、距离感知、光强感知等操作。
图2A为图1所示的显示基板的第一显示区域和第二显示区域的平面示意图，图2B为图2A所示的第一显示区域和第二显示区域的发光元件和像素电路的排布示意图。需要说明的是，为了清楚、简洁地说明第一显示区域和第二显示区域的发光元件和像素电路的排布方式，图2B中标号所指示的矩形框仅用于示出发光元件和像素电路的大概位置，而并不表示发光元件和像素电路的具体形状或具体边界等；并且，图2B中的矩形框仅用于说明发光元件和像素电路的排布方式，并不表示第一显示区域和第二显示区域内的发光元件和像素电路的实际数量，发光元件和像素电路的具体结构等可参考本领域中的常规设计，本公开的实施例对此不作限制。
例如，如图1、图2A和图2B所示，第二显示区域12至少部分围绕(例如，完全围绕)第一显示区域11。
例如，第一显示区域11的形状可以为圆形或椭圆形，第二显示区域12的形状可以为矩形，但本公开的实施例不限于此。又例如，第一显示区域11和第二显示区域12的形状可以均为矩形或者其它适用的形状。
图3为图2A所示的显示基板的第一显示区域和第二显示区域的一个示例的示意图，图4为图3的部分区域REG1的放大图，图5为图3的部分区域REG2的放大图。需要说明的是，为了清楚、简洁地说明第一发光元件与第一像素电路之间的连接关系，图5中仅示出了例如发光元件、像素电路、信号传输线等结构，但这并不构成对本公开实施例的限制。
例如，如图2A-图5所示，第一显示区域11包括至少一个(例如多个)第一发光元件411。需要说明的是，为清楚起见，相关附图使用了第一发光元件411的阳极结构来示意性的示出第一发光元件411。例如，第一显示区域11包括阵列排布的多个第一发光元件411，第一发光元件411被配置为发射光线。例如，第一显示区域11中没有像素电路，用于驱动第一发光元件411的像素电路(也即，第一像素电路412)设置在第二显示区域12中，从而减少第一显示区域11的金属覆盖面积，提高第一显示区域11的透光率。关于驱动第一发光元件411的像素电路，将在下文进行说明，此处不再赘述。
例如，多个第一发光元件411可以设置在多个发光单元中，这些发光单元呈阵列排布。例如，每个发光单元可以包括一个或多个第一发光元件411。例如，多个第一发光元件411可以发射相同颜色的光或不同颜色的光，例如可以发射白光、红光、蓝光、绿光等，这可以根据实际需求而定，本公开的实施例对此不作限制。例如，多个第一发光元件411的排布方式可以参考常规的像素单元排布方式，例如GGRB、RGBG、RGB等，本公开的实施例对此不作限制。
例如，第一显示区域11允许来自显示基板01的第一侧的光至少部分透射至显示基板01的第二侧。通过这种方式，可以便于在显示基板01的第二侧且对应于第一显示区域11的位置处设置传感器，该传感器可以接收来自第一侧的光线，从而可以进行图像拍摄、距离感知、光强感知等操作。
例如，如图2A-图5所示，第二显示区域12包括至少一个(例如多个)第一像素电路412，第一发光元件411与第一像素电路412电连接。例如，第一发光元件411与第一像素电路412一一对应地电连接，多个第一像素电路412用于一一对应地驱动多个第一发光元件411。也即是，一个第一像素电路412驱动一个对应的第一发光元件411，不同的第一像素电路412驱动不同的第一发光元件411。例如，多个第一像素电路412可以设置在多个第一像素驱动单元中，图5所示的矩形框(标号412所指示的黑色边框白色填充区域)表示第一像素驱动单元，这些第一像素驱动单元呈阵列排布。
需要说明的是，在图3、图4和图5中，第一像素驱动单元可以包括一个或多个第一像素电路412。当第一显示区域11中的发光单元包括一个第一发光元件411时，该第一像素驱动单元也包括一个第一像素电路412。当第一显示区域11中的发光单元包括多个第一发光元件411时，该第一像素驱动单元也包括多个第一像素电路412，每个发光单元中的第一发光元件411的数量例如等于每个第一像素驱动单元中的第一像素电路412的数量，由此实现一一对应驱动。
例如，多个第一发光元件411阵列排布，多个第一像素电路412也阵列排布。这里， “阵列排布”可以指多个器件为一组且多组器件阵列排布，也可以指多个器件自身阵列排布，本公开的实施例对此不作限制。例如，在一些示例中，如图3、图4和图5所示，每4个第一发光元件411为一组，多组第一发光元件411呈阵列排布，相应地，每4个第一像素电路412为一组，多组第一像素电路412呈阵列排布，此时，每个第一像素驱动单元中包括4个第一像素电路412。
例如，如图3、图4和图5所示，显示基板01上设有至少一条(例如多条)信号传输线110和至少一条(例如多条)第一虚设走线121。信号传输线110至少部分位于第一显示区域11和第二显示区域12，第一发光元件411通过信号传输线110与第一像素电路连接412。例如，信号传输线110的第一端位于第一显示区域11内且与第一发光元件411电连接，信号传输线110的第二端位于第二显示区域12内且与第一像素电路412电连接，由此实现第一发光元件411与第一像素电路412之间的电连接。第一虚设走线121至少部分位于第一显示区域11内，例如可以仅位于第一显示区域11内，也可以延伸至第二显示区域12内，且第一虚设走线121与信号传输线110和第一发光元件411绝缘。
例如，信号传输线110和第一虚设走线121分别沿第一方向R1延伸，第一虚设走线121在平行于显示基板01的平面内的正投影与信号传输线110在平行于显示基板01的平面内的正投影至少部分错开。例如，第一虚设走线121在平行于显示基板01的平面内的正投影与信号传输线110在平行于显示基板01的平面内的正投影之间没有交叠的部分，由此使第一虚设走线121和信号传输线110能够分别覆盖第一显示区域11的不同区域，进而提升第一显示区域11内走线布局的均匀性和一致性，从而改善第一显示区域11的透光率，提升透过第一显示区域11的光线的均匀性和一致性，并且还可以提升显示基板01在第一显示区域11内的刻蚀均一性。
例如，以图7所示的一种显示基板的透光区域LR为例，由于透光区域LR中走线的分布相对不均匀，透过该透光区域LR的光线的均匀性和一致性降低，进而导致该透光区域LR的透光效果受到严重的不良影响。例如，对应该透光区域LR设置的屏下传感器在接收光线时容易出现例如反光等问题，从而难以准确地实现图像拍摄、距离感知、光强感知等操作。
而相比于图7所示的显示基板的透光区域LR，本公开上述实施例提供的显示基板01通过在平行于显示基板01的平面内设置不与信号传输线110交叠的第一虚设走线121，可以优化第一显示区域11内的走线设计，例如提升第一显示区域11内走线布局的均匀性和一致性，从而提升透过第一显示区域11的光线的均匀性和一致性，进而改善第一显示区域11的透光率。例如，当屏下传感器(例如摄像头)对应设置在第一显示区域11时，本公开上述实施例提供的显示基板01可以减弱或避免屏下传感器在接收光线时可能出现的例如反光等问题，从而有助于屏下传感器准确地实现图像拍摄、距离感知、光强感知等操作，进而有助于提高采用该显示基板01的显示装置(例如全面屏显示装置)的性能。
在本公开的一些实施例中，第一显示区域11中被信号传输线110在平行于显示基板 01的平面内的正投影和第一虚设走线121在平行于显示基板01的平面内的正投影覆盖的区域的面积与第一显示区域11的面积之比为70％～95％，进一步例如80％～90％，例如也可以为75％或85％。也即，信号传输线110和第一虚设走线121整体在平行于显示基板01的平面内可以覆盖第一显示区域11的总面积的70％～95％，由此可以进一步提升第一显示区域11内走线布局的均匀性和一致性，从而提升透过第一显示区域11的光线的均匀性和一致性，改善第一显示区域11的透光效果。
在本公开的一些实施例中，如图3、图4和图5所示，第一虚设走线121与信号传输线110可以位于同一层，从而简化显示基板01的制备工艺，降低显示基板01的制备成本。
在本公开的其他一些实施例中，根据实际需求，例如基于提升信号传输线上的信号传输负载或进一步简化制备工艺等不同需求，第一虚设走线和信号传输线也可以位于不同层中；或者，也可以是一部分第一虚设走线设置在与信号传输线相同的一层，另一部分第一虚设走线设置在与信号传输线不同的一层，本公开的实施例对此不作限制。
需要说明的是，在本公开的说明中，位于“同一层”是指位于同一个膜层。例如，位于同一个膜层中的走线可以在同一个工艺中制备，例如通过一次图案化工艺形成所需要的走线。例如，当该显示基板01包括衬底基板时，在垂直于衬底基板的方向上，位于同一个膜层中的走线距衬底基板的距离相同或基本相同。也即是，该膜层中的走线距离衬底基板的远近程度相同或基本相同。在后文的说明中，位于“同一层”的含义可参考上文描述，不再赘述。
需要说明的是，在本公开的说明中，位于“不同层”是指位于不同的膜层，这些不同的膜层在未设置过孔的位置处彼此绝缘。例如，当需要使位于不同的膜层中的走线彼此电连接时，可以通过设置过孔的方式使位于不同的膜层中的走线实现电连接。例如，这些不同的膜层是在不同的工艺中制备的，例如先采用第一工艺制备这些不同的膜层中的一个膜层，然后再采用第二工艺制备这些不同的膜层中的另一个膜层。例如，在实施第一工艺之后且实施第二工艺之前，还可以采用第三工艺制备绝缘层，该绝缘层位于不同的膜层之间，以使不同的膜层在未设置过孔的位置处彼此绝缘。例如，第一工艺、第二工艺和第三工艺可以相同或不同。例如，当该显示基板01包括衬底基板时，在垂直于衬底基板的方向上，不同的膜层距衬底基板的距离不同。也即是，在不同的膜层中，一个膜层距衬底基板较近，而另一个膜层距衬底基板较远。在后文的说明中，位于“不同层”的含义可参考上文描述，不再赘述。
在本公开的一些实施例中，如图3、图4和图5所示，第一虚设走线121与信号传输线110均沿直线延伸且彼此平行，从而进一步有利于第一虚设走线121与信号传输线110在第一显示区域11内布局的均匀性和一致性，并且还可以进一步简化显示基板01的工艺要求，进而有利于显示基板01的制备。
需要说明的是，在本公开的其他一些实施例中，根据实际需求，例如基于第一显示区域11内发光元件或其他结构、器件的布局设计，第一虚设走线121或信号传输线110 也可以沿曲线型、折线型或其他适合的形状延伸，或者第一虚设走线121的延伸线和信号传输线110的延伸线之间也可以彼此相交，本公开的实施例对此不作限制。
在本公开的一些实施例中，第一虚设走线121可以配置为接收第一电压信号(例如高电平信号或低电平信号，该低电平信号例如为接地信号)，或者也可以配置为处于浮置状态，本公开的实施例对此不作限制。例如，以第一虚设走线121接收高电平信号或低电平信号为例，第一虚设走线121还可以减弱或避免信号传输线110之间的信号串扰，从而提升电路环境的均一性和稳定性，改善信号传输线110的信号传输效果。
例如，如图3、图4和图5所示，第一显示区域11内的多条第一虚设走线121沿不同于第一方向R1的第二方向R2排列且配置为接收第一电压信号。显示基板还包括至少一条(例如多条)第二虚设走线122，第二虚设走线122沿第二方向R2延伸且与多条第一虚设走线121电连接，以使多条第一虚设走线121彼此电连接以接收第一电压信号。由此，可以改善多条第一虚设走线121之间的电连接效果，进一步提升电路环境的均一性和稳定性。
需要说明的是，第一方向R1与第二方向R2的夹角例如可以在70°到90°之间，且包括70°和90°。例如，第一方向R1与第二方向R2的夹角为70°、75°、85°、90°或80°等，该夹角的具体数值可根据实际情况设定，本公开的实施例对此不作限制。
例如，多条第一虚设走线121中的至少一条可以通过过孔结构与提供第一电压信号的第一电源线电连接，例如该第一电源线可以为用于向第一像素电路412提供用于显示的第一电压信号的电源线，由此可以简化显示基板01的走线布局，优化显示基板01的结构设计。
图6为本公开至少一个实施例提供的一种显示基板的靠近显示区域的边缘的部分的一个示例的示意图，例如图6所示的部分可以位于图3中所示的部分区域REG4中。例如，多条第一虚设走线121中在第二方向R2上靠近显示基板01的边缘的一条第一虚设走线121A通过过孔结构H3与第一电源线LVDD电连接，以接收第一电压信号，并通过与该第一虚设走线121A连接的第二虚设走线122A将接收的第一电压信号传输至其他第一虚设走线121和/或第二虚设走线122。
需要说明的是，图6中第一电源走线LVDD的形状、位置、与第一虚设走线121A的交叠面积等仅是示意性说明，本公开的实施例对第一电源走线LVDD的具体形状、设置位置等不作限制。在本公开的一些实施例中，第一电源走线LVDD可以如图6中所示仅与一条第一虚设走线121A电连接；而在本公开的其他一些实施例中，第一电源走线LVDD也可以与例如2条、3条或4条等多条第一虚设走线121A电连接，本公开的实施例对此不作限制。在本公开的一些实施例中，用于实现第一电源走线LVDD与第一虚设走线121A电连接的过孔结构H3可以如图6中所示仅包括一个过孔；而在本公开的其他一些实施例中，用于实现第一电源走线LVDD与第一虚设走线121A电连接的过孔结构H3也可以包括2个、3个或4个等多个过孔，本公开的实施例对此不作限制。
在本公开的一些实施例中，第二虚设走线122可以如图4所示与第一虚设走线121 位于同一层，从而简化制备工艺，降低制备成本；或者，在本公开的其他一些实施例中，第二虚设走线122也可以与第一虚设走线121位于不同层，例如第二虚设走线122与第一虚设走线121位于不同的膜层，不同的膜层在未设置过孔的位置彼此绝缘，从而减弱或避免走线之间的信号串扰。本公开的实施例对此不作限制。
例如，如图3、图4和图5所示，多条第一虚设走线121沿第二方向R2排列，多条信号传输线110沿第二方向R2排列，多条信号传输线110和多条第一虚设走线121构成布线阵列，一条信号传输线110作为布线阵列中的一个线条单元140，一条第一虚设走线121作为布线阵列中的一个线条单元140，布线阵列中至少一个线条单元140与在第二方向R2上相邻的线条单元140之间的距离相等。也即，多条第一虚设走线121和多条信号传输线110中的至少一条第一虚设走线121或信号传输线110与在第二方向R2上相邻(例如在第二方向R2上位于其两侧)的两条走线(这两条走线可以为第一虚设走线121和/或信号传输线110)之间的距离相等。由此，可以进一步优化第一显示区域11内的走线设计，进一步提升第一显示区域11内走线布局的均匀性和一致性，从而进一步提升透过第一显示区域11的光线的均匀性和一致性，改善第一显示区域11的透光率。
例如，如图3、图4和图5所示，在第一显示区域11内，每条信号传输线110与在第二方向R2上相邻的两条走线(这两条走线可以为第一虚设走线121和/或信号传输线110)之间的距离相等，从而既可以提升第一显示区域11内走线布局的均匀性和一致性，还可以提升电路环境的均一性和稳定性，从而改善信号传输线110的信号传输效果。
例如，结合图2A-图5所示，第一显示区域11包括中间区域1101和在第一方向R1上位于中间区域1101的两侧(例如在第一方向R1上完全围绕中间区域1101)的周边区域1102，第一显示区域11的中轴线L11位于中间区域1101内，周边区域1102与第二显示区域12相邻，多条第一虚设走线121在中间区域内1101的单位面积分布比大于多条第一虚设走线121在周边区域1102内的单位面积分布比。例如，在第一显示区域11内沿周边区域1102至中间区域1101的方向(例如从第一显示区域11在第一方向R1上的边缘至中轴线L11的方向)，多条第一虚设走线121的单位面积分布比逐渐增大。由于多条信号传输线110在中间区域1101内的单位面积分布比小于多条信号传输线110在周边区域1102内的单位面积分布比，例如在第一显示区域11内从周边区域1102至中间区域1101的方向，多条信号传输线110的单位面积分布比逐渐减小，因此本公开实施例提供的显示基板01中，第一虚设走线121在第一显示区域11内的分布方式可以与信号传输线110在第一显示区域11内的分布方式相配合，由此进一步优化第一显示区域11内的走线设计，进一步提升第一显示区域11内走线布局的均匀性和一致性，从而进一步提升透过第一显示区域11的光线的均匀性和一致性，改善第一显示区域11的透光率。
需要说明的是，上述“单位面积分布比”是指走线在单位面积内的分布面积，也即单位面积分布比越大，走线在单位面积的区域内所覆盖的面积越大，例如在走线的长度基本相同的情形下，走线在相应区域内的分布越密集、数量越多；单位面积分布比越小，走线在单位面积的区域内所覆盖的面积越小，例如在走线的长度基本相同的情形下，走 线在相应区域内的分布越稀疏、数量越少。
在本公开的一些实施例中，信号传输线110、第一虚设走线121和第二虚设走线122可以分别包括透明导电走线，从而可以进一步提高显示基板01的第一显示区域11的透光率。该透明导电走线可以采用例如氧化铟锡(Indium tin oxide，ITO)或其他适合的透明导电材料制备。
在本公开的一些实施例中，第一虚设走线121在第二方向R2上的宽度与信号传输线110在第二方向R2上的宽度相同，由此可以进一步提升第一显示区域11内第一虚设走线121和信号传输线110分布的均匀性和一致性，并且还可以提升电路环境的均一性和稳定性，从而改善信号传输线110的信号传输效果。
在本公开的一些实施例中，如图3、图4和图5所示，信号传输线110通过至少贯穿位于信号传输线110和第一发光元件411的阳极之间的绝缘层的过孔结构H1与第一发光元件411的阳极电连接，从而向第一发光元件411提供电信号，以驱动第一发光元件411发光。
例如，过孔结构H1在平行于显示基板01的平面内的正投影与第一虚设走线121在平行于显示基板01的平面内的正投影互不重叠，例如在垂直于显示基板01的方向上，第一虚设走线121尽量避开过孔结构H1的位置而设置。由此，可以减弱或避免第一虚设走线121对提供至第一发光元件411的电信号可能产生的干扰，从而提升第一发光元件411的工作的稳定性，改善第一发光元件411的发光效果。
需要说明的是，根据显示基板01的实际结构，过孔结构H1还可以贯穿除绝缘层以外位于信号传输线110和第一发光元件411的阳极之间的其他膜层或结构等，以实现信号传输线110与第一发光元件411的阳极之间的电连接，本公开的实施例对此不作限制。
例如，第一像素电路412包括薄膜晶体管，薄膜晶体管包括栅极、第一极和第二极，信号传输线110与薄膜晶体管的第一极或第二极电连接，由此将第一像素电路412的输出信号提供至第一发光元件411。例如，根据第一像素电路412的电路结构，该薄膜晶体管可以为第一像素电路412中的驱动薄膜晶体管，也可以为第一像素电路412中的发光控制薄膜晶体管，或其他类型的薄膜晶体管。
图8为本公开至少一个实施例提供的一种显示基板的叠层结构示意图，该叠层结构示意图主要示意性地示出了第一像素电路412的部分结构和第一发光元件411。例如，图8可以为显示基板01沿图5中所示的A-A’线的截面结构的示意图。
例如，如图5和图8所示，显示基板01包括位于衬底基板101上的源漏极金属层(SD层)，第一像素电路412的薄膜晶体管412T的第一极和第二极(即源漏电极，例如源极4123和漏极4124)位于源漏极金属层。
第一发光元件411包括阳极4111、阴极4113以及位于阳极4111与阴极4113之间的第一发光层4112，第一发光元件411的阳极4111位于源漏极金属层之上，信号传输线110和第一虚设走线121(图8中未示出)所在的膜层位于第一发光元件411的阳极4111与源漏极金属层之间。阳极4111通过过孔结构H1与信号传输线110电连接，进而通过 信号传输线110与第一像素电路412包括的薄膜晶体管412T电连接。
例如，阳极4111可以包括多个阳极子层，例如包括ITO/Ag/ITO三层结构等(图中未标示)，本公开的实施例对阳极4111的具体形式不做限定。例如，阴极4113可以为显示基板01上整个表面上形成的结构，阴极4113例如可以包括锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。例如，由于阴极4113可以形成为很薄的一层，因此阴极4113具有良好的透光性。
例如，薄膜晶体管412T包括有源层4121、栅极4122和源漏电极(即源极4123和漏极4124)等结构。例如，有源层4121设置在衬底基板101上，有源层4121的远离衬底基板101的一侧设置有第一栅绝缘层741。栅极4122位于第一栅绝缘层741的远离衬底基板101的一侧，栅极4122的远离衬底基板101的一侧设置有第二栅绝缘层742。源漏电极设置在层间绝缘层743的远离衬底基板101的一侧，并通过位于第一栅绝缘层741、第二栅绝缘层742和层间绝缘层743中的过孔与有源层4121电连接。源漏电极的远离衬底基板101的一侧设置有平坦化层744，以平坦化第一像素电路412。
例如，平坦化层744中具有过孔H2，薄膜晶体管412T的漏极4124(或源极4123)通过平坦化层744中的过孔H2与信号传输线110电连接，进而通过信号传输线110与阳极4111电连接。
例如，第一显示区域11还包括位于衬底基板101上的透明支撑层78，第一发光元件411位于透明支撑层78的远离衬底基板101的一侧。由此，相对于衬底基板101来说，第一显示区域11中的第一发光元件411可以与第二显示区域12中的第二发光元件(可参考后文关于第二显示区域12以及第二发光元件412的描述)以及第三显示区域中的第三发光元件(可参考后文关于第三显示区域13以及第三发光元件413的描述)处于基本相同的高度，从而可以提高显示基板01的显示效果。
例如，该显示基板01还包括像素界定层746、封装层747等结构。例如，像素界定层746设置在阳极4111(例如阳极4111的部分结构)上，包括多个开口以界定不同的像素或子像素，第一发光层4112形成在像素界定层746的开口中。例如，封装层747可以包括单层或多层封装结构，多层封装结构例如包括无机封装层和有机封装层的叠层，由此提高对显示基板01的封装效果。
例如，本公开的各个实施例中，衬底基板101可以为玻璃基板、石英基板、金属基板或树脂类基板等，可以是刚性基板或柔性基板。本公开的实施例对此不作限制。
例如，第一栅极绝缘层741、第二栅极绝缘层742、层间绝缘层743以及平坦化层744、绝缘层745、像素界定层746、封装层747可以包括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，或者可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料。本公开的实施例对上述各功能层的材料均不做具体限定。
例如，有源层4121的材料可以包括多晶硅或氧化物半导体(例如，氧化铟镓锌)等半导体材料。例如，有源层4121的部分可以通过掺杂等导体化处理以导体化，从而具有较高的导电性。
例如，栅极4122的材料可以包括金属材料或者合金材料，例如包括钼、铝及钛等。
例如，源极4123和漏极4124的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层，例如钛、铝、钛三层金属叠层(Ti/Al/Ti)等。
在本公开的一些实施例中，如图1所示，显示区域10还包括第三显示区域13，第三显示区域13至少部分围绕(例如部分围绕)第二显示区域12，第一显示区域11、第二显示区域12和第三显示区域13互不重叠。需要说明是，在一些示例中，显示基板01还可以包括周边区域，该周边区域至少部分围绕第三显示区域13。
例如，如图2B和图5所示，第二显示区域12还包括至少一个(例如多个)第二发光元件421和至少一个(例如多个)第二像素电路422，第二发光元件421与第二像素电路422电连接，例如一一对应地电连接，第二像素电路422用于驱动第二发光元件421发光。需要说明的是，图5中标号422所指示的矩形框仅用于示出第二像素电路422的大概位置，而并不表示第二像素电路422的具体形状以及第二像素电路422的具体边界。例如，多个第二发光元件421阵列排布，多个第二像素电路422也阵列排布。例如，至少一个第二发光元件421及其对应的第二像素电路422构成一个第二像素驱动单元42。
需要说明的是，在图5中，第二像素驱动单元42可以包括一个第二像素电路422及一个第二发光元件421，或者可以包括多个第二像素电路422及多个第二发光元件421。当第二像素驱动单元42包括多个第二像素电路422及多个第二发光元件421时，每个第二像素驱动单元42中的第二像素电路422的数量例如等于第二发光元件421的数量，由此实现一一对应驱动。
例如，多个第二发光元件421阵列排布，多个第二像素电路422也阵列排布。这里，“阵列排布”可以指多个器件为一组且多组器件阵列排布，也可以指多个器件自身阵列排布，本公开的实施例对此不作限制。例如，在一些示例中，如图5所示，每4个第二发光元件421为一组，多组第二发光元件421呈阵列排布，相应地，每4个第二像素电路422为一组，多组第二像素电路422呈阵列排布，此时，每个第二像素驱动单元42中包括4个第二像素电路422和4个第二发光元件421。
图9为图1所示的显示基板的第三显示区域13的部分区域REG3的放大图。
例如，如图9所示，第三显示区域13包括至少一个(例如多个)第三发光元件431和至少一个(例如多个)第三像素电路432，第三发光元件431与第三像素电路432电连接，例如一一对应地电连接，第三像素电路432用于驱动第三发光元件431发光。需要说明的是，图9中标号432所指示的矩形框仅用于示出第三像素电路432的大概位置，而并不表示第三像素电路432的具体形状以及第三像素电路432的具体边界。例如，多个第三发光元件431阵列排布，多个第三像素电路432也阵列排布。例如，至少一个第三发光元件431及其对应的第三像素电路432构成一个第三像素驱动单元43。
需要说明的是，在图9中，第三像素驱动单元43可以包括一个第三像素电路432及一个第三发光元件431，或者可以包括多个第三像素电路432及多个第三发光元件431。 当第三像素驱动单元43包括多个第三像素电路432及多个第三发光元件431时，每个第三像素驱动单元43中的第三像素电路432的数量例如等于第三发光元件431的数量，由此实现一一对应驱动。
例如，多个第三发光元件431阵列排布，多个第三像素电路432也阵列排布。这里，“阵列排布”可以指多个器件为一组且多组器件阵列排布，也可以指多个器件自身阵列排布，本公开的实施例对此不作限制。例如，在一些示例中，如图9所示，每4个第三发光元件431为一组，多组第三发光元件431呈阵列排布，相应地，每4个第三像素电路432为一组，多组第三像素电路432呈阵列排布，此时，每个第三像素驱动单元43中包括4个第三像素电路432和4个第三发光元件431。
例如，第一显示区域11中多个第一发光元件411的单位面积分布密度小于第二显示区域12中多个第二发光元件421的单位面积分布密度；第二显示区域12中多个第二发光元件421的单位面积分布密度小于第三显示区域13中多个第三发光元件431的单位面积分布密度。例如，第一显示区域11和第二显示区域12可以被称为显示基板01的低分辨率区域，相应地，第三显示区域13可以被称为显示基板01的高分辨率区域。例如，第二显示区域12与第一显示区域11的像素发光面积之和可以为第三显示区域13的像素发光面积的1/8～1/2。
需要说明的是，在一些示例中，第一显示区域11中多个第一发光元件411的单位面积分布密度也可以等于第二显示区域12中多个第二发光元件421的单位面积分布密度，这可以根据实际需求而定，本公开的实施例对此不作限制。
通过使第一显示区域11、第二显示区域12和第三显示区域13的发光元件的单位面积分布密度依次增大，可以在保证三个显示区域正常发光以显示画面的同时，便于显示基板01的第一侧的光线透过第一显示区域11以到达第二侧，进而便于设置在显示基板01的第二侧的传感器感测光线。
例如，第一发光元件411、第二发光元件421和第三发光元件431分别包括有机发光二极管(OLED)。当然，本公开的实施例不限于此，第一发光元件411、第二发光元件421和第三发光元件431还可以为量子点发光二极管(QLED)或其他适用的发光器件，本公开的实施例对此不作限制。
例如，本公开实施例提供的显示基板01可以为有机发光二极管(OLED)显示基板或者量子点发光二极管(QLED)显示基板等，本公开的实施例对显示基板的具体种类不做限定。
例如，在显示基板为有机发光二极管显示基板的情形，发光层(例如前述的第一发光层4112)可以包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光等。并且，根据实际不同需要，在不同的示例中，发光层还可以进一步包括电子注入层、电子传输层、空穴注入层、空穴传输层等功能层。
例如，在显示基板为量子点发光二极管(QLED)显示基板的情形，发光层(例如 前述的第一发光层4112)可以包括量子点材料，例如，硅量子点、锗量子点、硫化镉量子点、硒化镉量子点、碲化镉量子点、硒化锌量子点、硫化铅量子点、硒化铅量子点、磷化铟量子点和砷化铟量子点等，量子点的粒径例如为2nm～20nm。
本公开至少一个实施例还提供一种显示装置，该显示装置包括本公开任一实施例提供的显示基板。
图10为本公开至少一个实施例提供的一种显示装置的示意框图。例如，如图10所示，该显示装置30包括显示基板310，显示基板310可以为本公开任一实施例提供的显示基板，例如前述的显示基板01。
该显示装置30可以为任何具有显示功能的电子装置，例如智能手机、笔记本电脑、平板电脑、电视等。例如，当显示装置30为智能手机或平板电脑时，该智能手机或平板电脑可以具有全面屏设计，也即是，没有围绕例如第一显示区域11、第二显示区域12或第三显示区域13的周边区域。并且，该智能手机或平板电脑还具有屏下传感器(例如摄像头、红外传感器等)，可以进行图像拍摄、距离感知、光强感知等操作。
需要说明的是，对于该显示基板310和显示装置30的其它组成部分(例如，图像数据编码/解码装置、时钟电路等)可以采用适用的部件，这些均是本领域的普通技术人员所应该理解的，在此不做赘述，也不应作为对本公开实施例的限制。
图11为本公开至少一个实施例提供的一种显示装置的叠层结构示意图。例如，如图11所示，该显示装置30包括显示基板310，显示基板310可以为本公开任一实施例提供的显示基板，例如前述的显示基板01。例如，该显示装置30还包括传感器320。
例如，以显示基板310为前述的显示基板01为例，该显示基板01包括用于显示的第一侧F1和与第一侧F1相对的第二侧F2。也即是，第一侧F1为显示侧，第二侧F2为非显示侧。显示基板01被配置为在第一侧F1执行显示操作，也即，显示基板01的第一侧F1为显示基板01的出光侧，第一侧F1朝向用户。第一侧F1和第二侧F2在显示基板01的显示面的法线方向上对置。
如图11所示，传感器320设置于显示基板01的第二侧F2，并且传感器320配置为接收来自第一侧F1的光。例如，传感器320与第一显示区域11在显示基板01的显示面的法线方向(例如，垂直于显示基板01的方向)上叠置，传感器320可以接收并处理穿过第一显示区域11的光信号，该光信号可以为可见光、红外光等。例如，第一显示区域11允许来自第一侧F1的光至少部分透射至第二侧F2。例如，第一显示区域11未设置像素电路，此种情况下，可以提升第一显示区域11的透光率。
例如，传感器320在显示基板01上的正投影与第一显示区域11至少部分重叠。例如，在一些示例中，当采用直下式设置方式时，传感器320在显示基板01上的正投影位于第一显示区域11内。例如，在另一些示例中，当采用其他导光元件(例如导光板、导光管等)以使光线从侧面入射至传感器320上时，传感器320在显示基板01上的正投影与第一显示区域11部分重叠。此时，由于光线可以横向传播至传感器320，不需要传感器320完全位于对应于第一显示区域11的位置处。
例如，通过使第一像素电路412设置在第二显示区域12，并使传感器320与第一显示区域11在显示基板01的显示面的法线方向上叠置，可以减小第一显示区域11中的元件对入射至第一显示区域11并照射到传感器320的光信号的遮挡，由此可以提升传感器320输出的图像的信噪比。例如，第一显示区域11可以被称为显示基板01的低分辨率区域的高透光区。
例如，传感器320可以是图像传感器，可以用于采集传感器320的集光面面对的外部环境的图像，例如可以为CMOS图像传感器或CCD图像传感器。该传感器320还可以是红外传感器、距离传感器等。例如，在该显示装置30为诸如手机、笔记本等移动终端的情形下，该传感器320可实现为诸如手机、笔记本等移动终端的摄像头，并且根据需要还可以包括例如透镜、反射镜或光波导等光学器件，以对光路进行调制。例如，该传感器320可以包括阵列排布感光像素。例如，每个感光像素可以包括光敏探测器(例如，光电二极管、光电晶体管)和开关晶体管(例如，开关薄膜晶体管)。例如，光电二极管可以将照射到其上的光信号转换为电信号，开关晶体管可以与光电二极管电连接，以控制光电二极管是否处于采集光信号的状态以及采集光信号的时间。
在一些示例中，第一发光元件411的阳极采用ITO/Ag/ITO的叠层结构，则在第一显示区域11中，仅有第一发光元件411的阳极不透光，也即，用于驱动第一发光元件411的走线(例如上述的信号传输线110)、与第一发光元件411彼此绝缘的走线(例如上述的第一虚设走线121或第二虚设走线122)设置为透明走线。此种情况下，不仅可以进一步地提升第一显示区域11的透光率，还可以提升透过第一显示区域11的光线的均匀性和一致性，进而减弱或避免传感器320在接收光线时可能出现的例如反光等问题，从而有助于传感器320准确地实现图像拍摄、距离感知、光强感知等操作，有助于提高显示装置30(例如全面屏显示装置)的性能。
需要说明的是，本公开的实施例中，显示装置30还可以包括更多的部件和结构，本公开的实施例对此不作限制。关于该显示装置30的技术效果和详细说明，可以参考上文中关于显示基板01的描述，此处不再赘述。
例如，上述显示装置30可以为显示基板、显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不作限制。
本公开实施例提供的显示装置30的具体说明及技术效果可以参考本公开实施例提供的显示基板中的相应内容，例如可以参考上述实施例中的显示基板01的相应内容，在此不再赘述。
还有以下几点需要说明：
(1)本公开实施例的附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或第一 基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (21)

  1. 一种显示基板，具有用于显示的第一侧和与所述第一侧相对的第二侧，且包括显示区域；
    其中，所述显示区域包括第一显示区域和第二显示区域，所述第二显示区域至少部分围绕所述第一显示区域，所述第一显示区域和所述第二显示区域互不重叠；
    所述第一显示区域包括至少一个第一发光元件，且所述第一显示区域允许来自所述第一侧的光至少部分透射至所述第二侧；
    所述第二显示区域包括至少一个第一像素电路，所述第一发光元件与所述第一像素电路电连接；
    所述显示基板上设有至少一条信号传输线和至少一条第一虚设走线，
    所述信号传输线至少部分位于所述第一显示区域和所述第二显示区域，所述第一发光元件通过所述信号传输线与所述第一像素电路连接，
    所述第一虚设走线至少部分位于所述第一显示区域内，且与所述信号传输线和所述第一发光元件绝缘，
    所述信号传输线和所述第一虚设走线分别沿第一方向延伸，所述第一虚设走线在平行于所述显示基板的平面内的正投影与所述信号传输线在平行于所述显示基板的平面内的正投影至少部分错开。
  2. 根据权利要求1所述的显示基板，其中，所述第一虚设走线与所述信号传输线位于同一层。
  3. 根据权利要求1或2所述的显示基板，其中，所述第一虚设走线与所述信号传输线均沿直线延伸且彼此平行。
  4. 根据权利要求1-3中任一项所述的显示基板，其中，所述至少一条第一虚设走线包括多条第一虚设走线，所述多条第一虚设走线沿不同于所述第一方向的第二方向排列且配置为接收第一电压信号，
    所述显示基板还包括至少一条第二虚设走线，所述第二虚设走线沿所述第二方向延伸且与所述多条第一虚设走线电连接，以使所述多条第一虚设走线彼此电连接以接收所述第一电压信号。
  5. 根据权利要求4所述的显示基板，其中，所述多条第一虚设走线中的至少一条通过过孔结构与提供所述第一电压信号的第一电源线电连接。
  6. 根据权利要求4或5所述的显示基板，其中，所述第二虚设走线与所述第一虚设走线位于同一层，或
    所述第二虚设走线与所述第一虚设走线位于不同的膜层，所述不同的膜层在未设置过孔的位置彼此绝缘。
  7. 根据权利要求4-6中任一项所述的显示基板，其中，所述至少一条信号传输线包括沿所述第二方向排列的多条信号传输线，
    所述多条信号传输线和所述多条第一虚设走线构成布线阵列，一条信号传输线作为所述布线阵列中的一个线条单元，一条第一虚设走线作为所述布线阵列中的一个线条单元，
    所述布线阵列中至少一个线条单元与在所述第二方向上相邻的线条单元之间的距离相等。
  8. 根据权利要求7所述的显示基板，其中，所述第一显示区域包括中间区域和在所述第一方向上位于所述中间区域的两侧的周边区域，
    所述第一显示区域的中轴线位于所述中间区域内，所述周边区域与所述第二显示区域相邻，
    所述多条第一虚设走线在所述中间区域内的单位面积分布比大于所述多条第一虚设走线在所述周边区域内的单位面积分布比。
  9. 根据权利要求4-8中任一项所述的显示基板，其中，所述信号传输线、所述第一虚设走线和所述第二虚设走线分别包括透明导电走线。
  10. 根据权利要求1-9中任一项所述的显示基板，其中，所述第一虚设走线在不同于所述第一方向的第二方向上的宽度与所述信号传输线在所述第二方向上的宽度相同。
  11. 根据权利要求1-10中任一项所述的显示基板，其中，所述信号传输线通过至少贯穿位于所述信号传输线和所述第一发光元件的阳极之间的绝缘层的过孔结构与所述第一发光元件的阳极电连接。
  12. 根据权利要求11所述的显示基板，其中，所述过孔结构在平行于所述显示基板的平面内的正投影与所述至少一条第一虚设走线在平行于所述显示基板的平面内的正投影互不重叠。
  13. 根据权利要求1-12中任一项所述的显示基板，其中，所述第一像素电路包括薄膜晶体管，所述薄膜晶体管包括栅极、第一极和第二极，
    所述信号传输线与所述薄膜晶体管的第一极或第二极电连接。
  14. 根据权利要求13所述的显示基板，还包括源漏极金属层，
    其中，所述薄膜晶体管的第一极和第二极位于所述源漏极金属层，所述第一发光元件的阳极位于所述源漏极金属层之上，
    所述信号传输线和所述第一虚设走线所在的膜层位于所述第一发光元件的阳极与所述源漏极金属层之间。
  15. 根据权利要求1-14中任一项所述的显示基板，其中，所述显示区域还包括第三显示区域，
    所述第三显示区域至少部分围绕所述第二显示区域，所述第一显示区域、所述第二显示区域和所述第三显示区域互不重叠；
    所述第二显示区域还包括至少一个第二发光元件和至少一个第二像素电路，所述第二发光元件与所述第二像素电路电连接；
    所述第三显示区域包括至少一个第三发光元件和至少一个第三像素电路，所述第三 发光元件与所述第三像素电路电连接。
  16. 根据权利要求15所述的显示基板，其中，所述第一发光元件、所述第二发光元件和所述第三发光元件分别包括有机发光二极管。
  17. 根据权利要求15或16所述的显示基板，其中，所述至少一个第一发光元件包括多个第一发光元件，所述至少一个第二发光元件包括多个第二发光元件，所述至少一个第三发光元件包括多个第三发光元件，
    所述多个第一发光元件在所述第一显示区域内的单位面积分布密度小于或等于所述多个第二发光元件在所述第二显示区域内的单位面积分布密度，
    所述多个第二发光元件在所述第二显示区域内的单位面积分布密度小于所述多个第三发光元件在所述第三显示区域内的单位面积分布密度。
  18. 根据权利要求1-17中任一项所述的显示基板，其中，所述第一显示区域中被所述至少一条信号传输线在平行于所述显示基板的平面内的正投影和所述至少一条第一虚设走线在平行于所述显示基板的平面内的正投影覆盖的区域的面积与所述第一显示区域的面积之比为70％～95％。
  19. 一种显示装置，包括如权利要求1-18任一所述的显示基板。
  20. 根据权利要求19所述的显示装置，还包括传感器，
    其中，所述传感器位于所述显示基板的第二侧，且配置为接收来自所述显示基板的第一侧的光。
  21. 根据权利要求20所述的显示装置，其中，所述传感器在所述显示基板上的正投影与所述第一显示区域至少部分重叠。
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