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WO2021249176A1 - 热载流效应耐受度的测试方法 - Google Patents

热载流效应耐受度的测试方法 Download PDF

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Publication number
WO2021249176A1
WO2021249176A1 PCT/CN2021/095601 CN2021095601W WO2021249176A1 WO 2021249176 A1 WO2021249176 A1 WO 2021249176A1 CN 2021095601 W CN2021095601 W CN 2021095601W WO 2021249176 A1 WO2021249176 A1 WO 2021249176A1
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level
degradation rate
output
input
rate
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PCT/CN2021/095601
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English (en)
French (fr)
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潘宜飞
骆晓东
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长鑫存储技术有限公司
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Priority to US17/437,359 priority Critical patent/US11953542B2/en
Publication of WO2021249176A1 publication Critical patent/WO2021249176A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements
    • G01R31/275—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements for testing individual semiconductor components within integrated circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5002—Characteristic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the embodiments of the present application relate to the field of semiconductors, and in particular to a method for testing the tolerance of the hot-carrying current effect.
  • the embodiment of the present application provides a method for testing the tolerance of the thermal current carrying effect, which can simply and effectively realize the test of the tolerance of the thermal current carrying effect of a semiconductor device.
  • the embodiment of the present application provides a method for testing the tolerance of the hot-carrying current effect, which is applied to the input and output circuit of the memory.
  • the input and output circuit has an output terminal and includes: controlling the output terminal to alternately output the second A level and a second level, the first level is higher than the second level; according to the first level and the second level, the degradation rate of the output performance parameter of the input/output circuit is obtained ; Based on the degradation rate, obtain the hot-carrying current effect tolerance of the input and output circuit.
  • the degradation rate includes at least one of a level maximum degradation rate or a level conversion rate degradation rate.
  • the maximum level degradation rate includes a level peak degradation rate and a level bottom degradation rate.
  • the level conversion rate degradation rate includes a level rising edge conversion rate degradation rate and a level falling edge conversion rate degradation rate.
  • the input and output circuit includes a PMOS tube and an NMOS tube, the output terminal is respectively connected to the drain of the PMOS tube and the drain of the NMOS tube, and the source of the PMOS tube is connected to a working power supply, The source of the NMOS tube is grounded;
  • the controlling the output terminal to alternately output the first level and the second level includes: at the previous moment, controlling the PMOS tube to be turned on and the NMOS tube to be turned off, so that The output terminal outputs the first level; at a later moment, the PMOS transistor is controlled to be turned off and the NMOS transistor is turned on, so that the output terminal outputs the second level.
  • the obtaining the thermal carrying current effect tolerance of the input and output circuit includes: obtaining the first thermal carrying current effect tolerance of the PMOS tube based on the degradation rate, and obtaining the second thermal carrying current effect tolerance of the NMOS tube Thermal current carrying effect tolerance.
  • the degradation rate includes a level peak degradation rate
  • the obtaining the first hot-carrying current effect tolerance of the PMOS tube includes: obtaining the first hot-carrying current based on the level peak degradation rate Effect tolerance.
  • the degradation rate includes a conversion rate degradation rate at a rising edge of a level
  • the obtaining the first thermal carrying current effect tolerance of the PMOS tube includes: obtaining a degradation rate of a conversion rate based on the rising edge of a level. The first thermal current carrying effect tolerance.
  • the degradation rate includes a level valley degradation rate
  • the obtaining the second thermal carrier effect tolerance of the NMOS tube includes: obtaining the second thermal carrier based on the level valley degradation rate Effect tolerance.
  • the degradation rate includes a level falling edge conversion rate degradation rate
  • the obtaining the second heat-carrying current effect tolerance of the NMOS tube includes: obtaining the conversion rate degradation rate based on the level falling edge conversion rate The second thermal current carrying effect tolerance.
  • the operating temperature of the input/output circuit is lower than room temperature.
  • controlling the input and output circuit to alternately output the first level and the second level includes: controlling the memory to perform burst transmission so that the output terminal alternately outputs the first level and the second level Level;
  • the obtaining the degradation rate of the output performance parameter of the input-output circuit includes: taking the burst length of the burst transmission as a detection time unit, and obtaining the output end of the multiple detection time units Output level; according to the output level, the degradation rate of the output performance parameter of the input and output circuit is obtained.
  • the input and output circuits are continuously affected by the hot-carrying effect, eliminating the self-repairing of the input and output circuits in the empty state, and thus according to the output performance of the input and output circuits. Parameters to accurately obtain the tolerance of the hot-carrying current effect of the input and output circuits.
  • the output performance parameters of the input and output circuit at a certain moment are only affected by one of the PMOS tube or the NMOS tube, so it can Through the output performance parameters of the input and output circuits, the thermal carrying current effect tolerance of the PMOS tube and the NMOS tube are obtained respectively.
  • FIG. 1 is an input and output circuit of a memory provided by an embodiment of the application
  • FIG. 2 is a schematic diagram of the change of the peak value of the output terminal level with the test time provided by the embodiment of the application;
  • FIG. 3 is a schematic diagram of the change of the output terminal level conversion rate with the test time provided by the embodiment of the application.
  • the embodiment of the present application provides a test method for the tolerance of the hot-carrying current effect, which is applied to the input and output circuit of the memory, and the input and output circuit is controlled to alternately output the first level and the second level, so that the input and output The circuit is continuously affected by the hot-carrying effect, eliminating the self-repairing of the input and output circuits in the vacant state, so as to accurately obtain the hot-carrying effect tolerance of the input and output circuits according to the output performance parameters of the input and output circuits.
  • the method for testing the tolerance of the hot-carrying current effect is applied to the input/output circuit of the memory.
  • the test method for the tolerance of the hot-carrying current effect will be described in detail below on the basis of an input and output circuit of the memory.
  • FIG. 1 is an input and output circuit of a memory provided by an embodiment of the application.
  • the input and output circuit 10 has an output terminal 11.
  • the input and output circuit 10 includes a PMOS tube 12 and an NMOS tube 13.
  • the output terminal 11 is connected to the drain of the PMOS tube 12 and the drain of the NMOS tube 13, and the source of the PMOS tube 12 is connected to the working
  • the power supply VCC is connected, and the source of the NMOS tube 13 is grounded, that is, connected to the ground terminal GND.
  • the method for testing the tolerance of the thermal current carrying effect includes the following steps:
  • Step 1 Control the output terminal 11 to alternately output the first level and the second level, the first level is higher than the second level.
  • the operating temperature of the input/output circuit 10 is lower than room temperature.
  • room temperature Under the condition of lower than room temperature (hereinafter referred to as low temperature), the atomic vibration of silicon atoms in the channel region of the MOS tube becomes weaker, and the collision of carriers with silicon atoms is reduced when operating in an electric field, so it is easier to obtain more than silicon-
  • the kinetic energy of the barrier height of silicon dioxide enters the gate oxide layer, which in turn causes silicon-silicon dioxide interface damage and oxide traps, that is, under low temperature conditions, the hot-carrying effect is more obvious.
  • testing under the condition of lower than room temperature is beneficial to strengthen the influence of the hot-carrying current effect on the output performance parameters of the input-output circuit 10, and thereby obtain the tolerance of the input-output circuit 10 against the high-intensity hot-carrying effect.
  • the resistance of the input and output circuit 10 under the effect of high-intensity hot-carrying current can meet the preset requirements, and the stability of the input and output circuit 10 at room temperature and above can be guaranteed to meet the preset requirements; in addition, at low temperatures Test under conditions, and then equivalently convert the test results under low temperature conditions to the test results under room temperature or other temperature conditions, which is beneficial to speed up the test progress and improve the test efficiency.
  • the initial operating temperature of the input/output circuit is lower than room temperature.
  • the operating temperature of the input and output circuits may rise due to the heating of the heat-carrying effect.
  • the influence of the heat of the hot-carrying effect on the output performance parameters of the input and output circuit belongs to the marginal effect of the hot-carrying effect, and the influence of the marginal effect of the hot-carrying effect is summarized in the influence of the hot-carrying effect, which is conducive to more accurate Obtain the output performance parameters of the input-output circuit under actual operating conditions, and then accurately obtain the tolerance of the input-output circuit under actual operating conditions.
  • the marginal effect refers to the influence of other physical phenomena formed by the hot-carrying current effect on the output performance parameters of the input and output circuits.
  • Derivative phenomena include but are not limited to heat generation and leakage current.
  • the PMOS tube 12 is controlled to be turned on and the NMOS tube 13 is turned off, so that the output terminal 11 outputs the first level; at the later moment, the PMOS tube 12 is controlled to be turned off and the NMOS tube 13 is turned on.
  • the output terminal 11 is made to output the second level, that is, by controlling the working states of the PMOS tube 12 and the NMOS tube 13 at different moments, the output terminal 11 of the input/output circuit 10 alternately outputs the first level and the second level.
  • burst transmission refers to continuous data transmission in a short period of time.
  • Step 2 Obtain the degradation rate of the output performance parameter of the input/output circuit 10 according to the first level and the second level.
  • the output performance parameter includes at least one of a voltage maximum value parameter or a level conversion rate parameter.
  • the maximum voltage parameters include voltage peak parameters and voltage valley parameters, which correspond to the first level parameter and the second level parameter in this embodiment;
  • the level conversion rate parameters include level rising edge conversion rate degradation rate and level drop The degradation rate of the edge conversion rate.
  • the rising edge of the level refers to the level conversion of the output level rising from the lower second level to the higher first level, and the falling edge of the level refers to the output level changing from the higher level.
  • the level conversion of a high first level falling to a lower second level, and the conversion rate refers to the rate of falling or rising.
  • the hot-carrying effect will damage the gate dielectric layer of the PMOS tube 12 and the NMOS tube 13, which in turn leads to the degradation of the performance parameters of the PMOS tube 12 and the NMOS tube 13; and the PMOS tube 12 and the NMOS tube 13
  • the degradation of performance parameters will also correspondingly cause the output performance parameters of the input-output circuit 10 to be degraded. That is, the output performance parameters of the input-output circuit 10 include the performance parameters of the PMOS tube 12 and the performance parameters of the NMOS tube 13.
  • the first level parameter is only related to the working power supply VCC and the performance parameters of the PMOS tube 12, so the working power supply VCC can be controlled by
  • the voltage stability of the first level ie, the peak level
  • the change in the peak level parameters can be used to characterize the change in the performance parameters of the PMOS tube 12.
  • the second level when the second level is output, since the NMOS tube 13 is grounded, that is, the drain level of the NMOS tube 13 is fixed, the parameters of the second level output by the output terminal 11 are only related to the performance parameters of the NMOS tube 13.
  • the parameter degradation of the two-level ie, level valley
  • the level valley degradation rate can be used to characterize the performance parameter degradation rate of the NMOS tube 13.
  • the level change rate is only related to the conduction rate of the PMOS tube 12. Since the conduction rate of the PMOS tube 12 is related to the damage of the gate dielectric layer of the PMOS tube 12 due to the hot-carrying effect, the greater the damage, the more severe the performance degradation, and the slower the conduction rate of the PMOS tube 12. Therefore, the level rising edge conversion rate can be used to characterize the current performance parameters of the PMOS tube 12, and the level rising edge conversion rate degradation rate can be used to characterize the performance parameter degradation rate of the PMOS tube 12.
  • the NMOS transistor 13 is gradually turned on, and the PMOS transistor 12 is turned off. Since the PMOS tube 12 is turned off, that is, when the gate voltage of the PMOS tube 12 returns to zero, the carriers in the moving state of the channel region will continue to move. Therefore, during a period of time after the PMOS tube 12 is turned off , The output level of the output terminal 11 is not zero, and during this period of time, the output performance change of the output terminal 11 is only related to the conduction rate of the NMOS tube 13.
  • the conduction rate of the NMOS tube 13 is related to the damage of the gate dielectric layer of the NMOS tube 13 by the hot-carrying effect, the greater the damage, the more severe the performance degradation, and the slower the conduction rate of the NMOS tube 13. Therefore, the level falling edge conversion rate can be used to characterize the current performance parameters of the NMOS tube 13 and the level falling edge conversion rate degradation rate can be used to characterize the degradation rate of the performance parameters of the NMOS tube 13.
  • the burst length of the burst transmission may be the time detection unit to obtain the output level of the output terminal 11 of the input and output circuit 10.
  • Step 3 Based on the degradation rate, obtain the thermal-carrying current effect tolerance of the input and output circuits.
  • the thermal-carrying current effect tolerance of the input-output circuit 10 is obtained based on at least one of the level maximum degradation rate or the level conversion rate degradation rate.
  • the voltage peak degradation rate or the level rising edge conversion rate degradation rate can be used to characterize the degradation rate of the PMOS tube 12, and the degradation rate is used to characterize the tolerance of the hot-carrying effect, it can be Obtain the first heat-carrying effect tolerance of the PMOS tube 12 based on at least one of the voltage peak degradation rate or the level rising edge conversion rate degradation rate; similarly, it can be based on the voltage valley degradation rate or the level falling edge conversion At least one of the rate degradation rates obtains the second thermal current carrying effect tolerance of the NMOS tube 13.
  • the second hot-carrying effect tolerance may be different from the first hot-carrying effect tolerance .
  • FIG. 2 is a schematic diagram of the change of output terminal level peak value with test time according to an embodiment of this application; refer to FIG. 3, which is a schematic diagram of the output terminal level conversion rate according to an embodiment of this application changing with test time .
  • the level peak output performance of the input and output circuit 10 is basically no longer affected by the hot-carrying effect. Within 6 hours, the hot-carrying effect will affect the level peak output performance. The impact is less than 5% of the original parameters; according to Figure 3, it can be seen that after 4 hours of testing and 6 hours of testing, there is a period of time for the level conversion rate of the input and output circuit 10 to stabilize, but when the test continues, the level conversion The rate is still degrading continuously.
  • the input-output circuit is continuously affected by the hot-carrying effect, and the situation that the input-output circuit self-repairs in an empty state is eliminated, so as to be based on the output performance of the input-output circuit Parameters to accurately obtain the tolerance of the hot-carrying current effect of the input and output circuits.

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Abstract

一种热载流效应耐受度的测试方法，应用于存储器的输入输出电路(10)，输入输出电路(10)具有输出端(11)，包括：控制输出端(11)交替输出第一电平和第二电平，第一电平高于第二电平；根据第一电平和第二电平，得到输入输出电路(10)的输出性能参数的退化速率；基于退化速率，获取输入输出电路(10)的热载流效应耐受度，能够简单有效地实现半导体器件热载流效应耐受度的测试。

Description

热载流效应耐受度的测试方法
交叉引用
本申请要求于2020年6月8日递交的名称为“热载流效应耐受度的测试方法”、申请号为2020105136696的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及半导体领域，特别涉及一种热载流效应耐受度的测试方法。
背景技术
随着电子设备的普及应用，人们对电子设备的性能也提出了更高的要求，例如，电子设备中半导体器件性能的稳定性。为保证半导体器件能够长期可靠的工作，通常在出厂前对半导体器件进行产品老化等性能测试试验，以保证半导体器件在预设时间内的性能变化处于预设阈值。
目前，缺少一种简单有效的针对半导体器件热载流效应耐受度的测试方法。
发明内容
本申请实施例提供一种热载流效应耐受度的测试方法，能够简单有效地实现半导体器件热载流效应耐受度的测试。
为解决上述问题，本申请实施例提供一种热载流效应耐受度的测试方法，应用于存储器的输入输出电路，所述输入输出电路具有输出端，包括：控制所述输出端交替输出第一电平和第二电平，所述第一电平高于所述第二电平；根据所述第一电平和所述第二电平，得到所述输入输出电路的输出性能参数的退化速率；基于所述退化速率，获取所述输入输出电路的热载流效应耐受度。
另外，所述退化速率包括电平最值退化速率或电平转化速率退化速率中的至少一者。
另外，所述电平最值退化速率包括电平峰值退化速率和电平谷值退化速 率。
另外，所述电平转化速率退化速率包括电平上升沿转化速率退化速率和电平下降沿转化速率退化速率。
另外，所述输入输出电路包括：PMOS管和NMOS管，所述输出端分别与所述PMOS管的漏极和所述NMOS管的漏极连接，所述PMOS管的源极与工作电源连接，所述NMOS管的源极接地；所述控制所述输出端交替输出第一电平和第二电平，包括：在前一时刻，控制所述PMOS管导通和所述NMOS管关断，使所述输出端输出所述第一电平；在后一时刻，控制所述PMOS管关断和所述NMOS管导通，使所述输出端输出所述第二电平。所述获取所述输入输出电路的热载流效应耐受度，包括：基于所述退化速率，获取所述PMOS管的第一热载流效应耐受度，且获取所述NMOS管的第二热载流效应耐受度。
另外，所述退化速率包括电平峰值退化速率；所述获取所述PMOS管的第一热载流效应耐受度，包括：基于所述电平峰值退化速率，获取所述第一热载流效应耐受度。
另外，所述退化速率包括电平上升沿转化速率退化速率；所述获取所述PMOS管的第一热载流效应耐受度，包括：基于所述电平上升沿转化速率退化速率，获取所述第一热载流效应耐受度。
另外，所述退化速率包括电平谷值退化速率；所述获取所述NMOS管的第二热载流效应耐受度，包括：基于所述电平谷值退化速率，获取所述第二热载流效应耐受度。
另外，所述退化速率包括电平下降沿转化速率退化速率；所述获取所述NMOS管的第二热载流效应耐受度，包括：基于所述电平下降沿转化速率退化速率，获取所述第二热载流效应耐受度。
另外，所述输入输出电路的运行温度低于室温。
另外，所述控制所述输入输出电路交替输出第一电平和第二电平，包括：控制所述存储器进行突发传输，以使所述输出端交替输出所述第一电平和所述第二电平；所述得到所述输入输出电路的输出性能参数的退化速率，包括：以所述突发传输的突发长度为检测时间单元，获取多个所述检测时间单元内的所 述输出端的输出电平；根据所述输出电平，获取所述输入输出电路的输出性能参数的退化速率。
与现有技术相比，本申请实施例提供的技术方案具有以下优点：
上述技术方案中，通过交替输出第一电平和第二电平，使得输入输出电路持续受到热载流效应的影响，排除输入输出电路在空置状态自我修复的情况，从而根据输入输出电路的输出性能参数，准确获取输入输出电路的热载流效应耐受度。
另外，由于在同一时刻仅有PMOS管和NMOS管中的一者处于导通状态，因此输入输出电路在某一时刻的输出性能参数仅受PMOS管或NMOS管中的一者的影响，因此可以通过输入输出电路的输出性能参数，分别获取PMOS管和NMOS管的热载流效应耐受度。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为本申请实施例提供的一种存储器的输入输出电路；
图2为本申请实施例提供的输出端电平峰值随测试时间变化的示意图；
图3为本申请实施例提供的输出端电平转化速率随测试时间变化的示意图。
具体实施方式
由背景技术可知，当前需要一种简单有效的测试半导体器件热载流效应耐受度的方法。
为解决上述问题，本申请实施例提供一种热载流效应耐受度的测试方法，应用于存储器的输入输出电路，通过控制输入输出电路交替输出第一电平和第二电平，使得输入输出电路持续受到热载流效应的影响，排除输入输出电路在空置状态自我修复的情况，从而能够根据输入输出电路的输出性能参数，准确获取输入输出电路的热载流效应耐受度。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
本实施例中，热载流效应耐受度的测试方法应用于存储器的输入输出电路中。以下将在存储器的一输入输出电路的基础上详细阐述热载流效应耐受度的测试方法。
参考图1，图1为本申请实施例提供的一种存储器的输入输出电路。
输入输出电路10具有输出端11，输入输出电路10包括PMOS管12和NMOS管13，输出端11分别与PMOS管12的漏极和NMOS管13的漏极连接，PMOS管12的源极与工作电源VCC连接，NMOS管13的源极接地，即与大地端GND连接。
本实施例中，热载流效应耐受度的测试方法包括以下步骤：
步骤一：控制输出端11交替输出第一电平和第二电平，第一电平高于第二电平。
本实施例中，输入输出电路10的运行温度低于室温。在低于室温(以下简称低温)的条件下，MOS管沟道区中硅原子的原子振动变弱，载流子在电场中运行时与硅原子的碰撞减小，因此更容易获得超过硅-二氧化硅的势垒高度的动能而进入栅极氧化层，进而造成硅-二氧化硅的界面损伤和氧化物陷阱，即在低温条件下，热载流效应更加明显。也就是说，在低于室温的条件下进行测试，有利于加强热载流效应对输入输出电路10的输出性能参数的影响，进而获取输入输出电路10针对高强度热载流效应的耐受度。
如此，可通过使得输入输出电路10在高强度热载流效应下的耐受度满足预设要求，保证输入输出电路10在室温及以上温度条件下的稳定性满足预设要求；此外，在低温条件下进行测试，再将低温条件下的测试结果等效转换至室温或其他温度条件下的测试结果，有利于加速测试进度，提高测试效率。
在其他实施例中，输入输出电路的初始运行温度低于室温。在后续运行 过程中，输入输出电路的运行温度可能受到热载流效应发热的影响而升高。热载流效应的发热对输入输出电路输出性能参数的影响属于热载流效应的边际效应，而将热载流效应的边际效应的影响归纳于热载流效应的影响中，有利于更为精确地获取输入输出电路在实际运行条件下的输出性能参数，进而准确获取输入输出电路在实际运行条件下的耐受度。
需要说明的是，边际效应指的热载流效应形成的其他物理现象对输入输出电路的输出性能参数的影响，衍生现象包括但不限于发热和漏电流。
本实施例中，在前一时刻，控制PMOS管12导通和NMOS管13关断，使输出端11输出第一电平；在后一时刻，控制PMOS管12关断和NMOS管13导通，使输出端11输出第二电平，即通过控制PMOS管12和NMOS管13在不同时刻下的工作状态，使得输入输出电路10的输出端11交替输出第一电平和第二电平。
举例来说，可采用控制存储器进行突发传输的方式，使得输出端11交替输出第一电平和第二电平。突发传输指的是在较短的时间内进行连续的数据传输。
步骤二：根据第一电平和第二电平，得到输入输出电路10的输出性能参数的退化速率。
本实施例中，输出性能参数包括电压最值参数或电平转化速率参数中的至少一者。电压最值参数包括电压峰值参数和电压谷值参数，对应本实施例中的第一电平参数和第二电平参数；电平转化速率参数包括电平上升沿转化速率退化速率和电平下降沿转化速率退化速率，电平上升沿指的是输出电平由较低的第二电平上升为较高的第一电平的电平转化，电平下降沿指的是输出电平由较高的第一电平下降为较低的第二电平的电平转化，转化速率指的是下降或上升的速率。
随着测试的进行，热载流效应会对PMOS管12和NMOS管13的栅介质层造成损伤，进而导致PMOS管12和NMOS管13的性能参数出现退化；而PMOS管12和NMOS管13的性能参数发生退化也会相应造成输入输出电路10的输出性能参数发生退化，即输入输出电路10的输出性能参数退化包括PMOS管12的性能参数退化和NMOS管13的性能参数退化。
本实施例中，由于输出第一电平时，PMOS管12导通和NMOS管13关断，第一电平参数仅与工作电源VCC以及PMOS管12的性能参数有关，因此可以通过控制工作电源VCC的电压稳定性，使得第一电平(即电平峰值)的参数变化仅与PMOS管12的性能参数变化有关，换句话说，可采用电平峰值参数的变化表征PMOS管12的性能参数变化。
相应地，在输出第二电平时，由于NMOS管13接地，即NMOS管13漏极电平是固定的，输出端11输出的第二电平的参数仅与NMOS管13的性能参数有关，第二电平(即电平谷值)的参数退化仅与NMOS管13的性能退化有关，换句话说，可采用电平谷值退化速率表征NMOS管13的性能参数退化速率。
本实施例中，在输入输出电路10的输出端11电平由第二电平上升为第一电平的过程中时，PMOS管12逐渐导通，NMOS管13断开，输出端11的输出电平变化速率仅与PMOS管12的导通速率有关。由于PMOS管12的导通速率与PMOS管12栅介质层受到的热载流效应的损伤有关，损伤越大，性能退化越严重，PMOS管12的导通速率越慢。因此，可以用电平上升沿转化速率表征PMOS管12的当前性能参数，用电平上升沿转化速率退化速率表征PMOS管12的性能参数退化速率。
相应地，在输入输出电路10的输出端11电平由第一电平下降至第二电平的过程中，NMOS管13逐渐导通，PMOS管12关断。由于在PMOS管12关断，即PMOS管12的栅极电压归零时，沟道区的部分处于运动状态的载流子依据会继续运动，因此，在PMOS管12关断之后的一段时间内，输出端11的输出电平不为零，且在这一段时间内，输出端11的输出性能变化仅与NMOS管13的导通速率有关。由于NMOS管13的导通速率与NMOS管13栅介质层受到的热载流效应的损伤有关，损伤越大，性能退化越严重，NMOS管13的导通速率越慢。因此，可以用电平下降沿转化速率表征NMOS管13的当前性能参数，用电平下降沿转化速率退化速率表征NMOS管13性能参数的退化速率。
本实施例中，在控制存储器进行突发传输时，可以突发传输的突发长度为时间检测单元，获取输入输出电路10的输出端11的输出电平。
步骤三、基于退化速率，获取输入输出电路的热载流效应耐受度。
本实施例中，基于电平最值退化速率或电平转化速率退化速率中的至少 一者获取输入输出电路10的热载流效应耐受度。
本实施例中，由于电压峰值退化速率或电平上升沿转化速率退化速率中的至少一者可用于表征PMOS管12的退化速率，而退化速率用于表征热载流效应耐受度，因此可基于电压峰值退化速率或电平上升沿转化速率退化速率中的至少一者获取PMOS管12的第一热载流效应耐受度；同理，可基于电压谷值退化速率或电平下降沿转化速率退化速率中的至少一者获取NMOS管13的第二热载流效应耐受度。
需要说明的是，由于NMOS管13中的载流子数量多于PMOS管12中的载流子数量，因此第二热载流效应耐受度与第一热载流效应耐受度可能存在不同。通过本文提供的测试方法，可以准确测得这一不同的具体表现。
参考图2，图2为本申请实施例提供的输出端电平峰值随测试时间变化的示意图；参考图3，图3为本申请实施例提供的输出端电平转化速率随测试时间变化的示意图。
根据图2可知，在测试6小时后，输入输出电路10的电平峰值输出性能基本不再受到热载流效应的影响，在6个小时之内，热载流效应对电平峰值输出性能的影响小于原始参数的5％；根据图3可知，在测试4小时和测试6小时之后，分别有一段时间输入输出电路10的电平转化速率趋于稳定，但是当继续进行测试时，电平转化速率依然在持续发生退化。
本实施例中，通过交替输出第一电平和第二电平，使得输入输出电路持续受到热载流效应的影响，排除输入输出电路在空置状态自我修复的情况，从而根据输入输出电路的输出性能参数，准确获取输入输出电路的热载流效应耐受度。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (11)

  1. 一种热载流效应耐受度的测试方法，应用于存储器的输入输出电路，所述输入输出电路具有输出端，包括：
    控制所述输出端交替输出第一电平和第二电平，所述第一电平高于所述第二电平；
    根据所述第一电平和所述第二电平，得到所述输入输出电路的输出性能参数的退化速率；
    基于所述退化速率，获取所述输入输出电路的热载流效应耐受度。
  2. 根据权利要求1所述的测试方法，其中，所述退化速率包括电平最值退化速率或电平转化速率退化速率中的至少一者。
  3. 根据权利要求2所述的测试方法，其中，所述电平最值退化速率包括电平峰值退化速率和电平谷值退化速率。
  4. 根据权利要求2所述的测试方法，其中，所述电平转化速率退化速率包括电平上升沿转化速率退化速率和电平下降沿转化速率退化速率。
  5. 根据权利要求4所述的测试方法，其中，所述输入输出电路包括：PMOS管和NMOS管，所述输出端分别与所述PMOS管的漏极和所述NMOS管的漏极连接，所述PMOS管的源极与工作电源连接，所述NMOS管的源极接地；控制所述输出端交替输出第一电平和第二电平，包括：
    在前一时刻，控制所述PMOS管导通和所述NMOS管关断，使所述输出端输出所述第一电平；在后一时刻，控制所述PMOS管关断和所述NMOS管导通，使所述输出端输出所述第二电平；
    所述获取所述输入输出电路的热载流效应耐受度，包括：
    基于所述退化速率，获取所述PMOS管的第一热载流效应耐受度，且获取所述NMOS管的第二热载流效应耐受度。
  6. 根据权利要求5所述的测试方法，其中，所述退化速率包括电平峰值退化速率；所述获取所述PMOS管的第一热载流效应耐受度，包括：基于所述电平峰值退化速率，获取所述第一热载流效应耐受度。
  7. 根据权利要求5所述的测试方法，其中，所述退化速率包括电平上升沿转化速率退化速率；所述获取所述PMOS管的第一热载流效应耐受度，包括：基于所述电平上升沿转化速率退化速率，获取所述第一热载流效应耐受度。
  8. 根据权利要求5所述的测试方法，其中，所述退化速率包括电平谷值退化速率；所述获取所述NMOS管的第二热载流效应耐受度，包括：基于所述电平谷值退化速率，获取所述第二热载流效应耐受度。
  9. 根据权利要求5所述的测试方法，其中，所述退化速率包括电平下降沿转化速率退化速率；所述获取所述NMOS管的第二热载流效应耐受度，包括：基于所述电平下降沿转化速率退化速率，获取所述第二热载流效应耐受度。
  10. 根据权利要求1所述的测试方法，其中，所述输入输出电路的运行温度低于室温。
  11. 根据权利要求1所述的测试方法，其中，所述控制所述输入输出电路交替输出第一电平和第二电平，包括：控制所述存储器进行突发传输，以使所述输出端交替输出所述第一电平和所述第二电平；得到所述输入输出电路的输出性能参数的退化速率，包括：以所述突发传输的突发长度为检测时间单元，获取多个所述检测时间单元内的所述输出端的输出电平；根据所述输出电平，获取所述输入输出电路的输出性能参数的退化速率。
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