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WO2021120378A1 - 一种阵列基板及其制作方法 - Google Patents

一种阵列基板及其制作方法 Download PDF

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Publication number
WO2021120378A1
WO2021120378A1 PCT/CN2020/075798 CN2020075798W WO2021120378A1 WO 2021120378 A1 WO2021120378 A1 WO 2021120378A1 CN 2020075798 W CN2020075798 W CN 2020075798W WO 2021120378 A1 WO2021120378 A1 WO 2021120378A1
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WO
WIPO (PCT)
Prior art keywords
layer
buffer layer
doped region
insulating layer
array substrate
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PCT/CN2020/075798
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English (en)
French (fr)
Inventor
罗成志
Original Assignee
武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/756,147 priority Critical patent/US20210408063A1/en
Publication of WO2021120378A1 publication Critical patent/WO2021120378A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Definitions

  • the present invention relates to the field of display technology, in particular to an array substrate of a top-gate thin film transistor and a manufacturing method thereof.
  • the thin film transistor liquid crystal display has the advantages of low power consumption, high contrast, and space saving, and has become the most mainstream display device on the market.
  • LTPS low-temperature polysilicon
  • AMOLED diode
  • the top gate Topic Gate
  • the light shielding layer Light Shield layer, LS
  • Its function is mainly to block the backlight from directly illuminating the array during the panel work.
  • the substrate channel causes photo-generated leakage current.
  • Excessive leakage current will significantly affect the optical display effect of the product, such as crosstalk, flicker, and contrast. Therefore, how to effectively reduce the photo-generated leakage current through the improvement of the device structure on the basis of eliminating the LS mask, reducing the production cycle and reducing the production cost is an important content of the development of low-temperature polysilicon array substrate technology.
  • the gate (Gate) traces can be used as a grid to play the role of a light-shielding layer, so that an LS mask can be saved.
  • the gate line is thicker, the low-temperature polysilicon will break at the ramp of the gate line, thereby affecting the electrical properties.
  • the present invention provides an array substrate and a manufacturing method thereof.
  • a photomask is saved when the array substrate is manufactured, thereby reducing the number of mask plates used, and does not need to fabricate a light shielding layer, simplifying the manufacturing process, and improving
  • the production efficiency is saved, the process time is saved, and the cost is reduced; and the low-temperature polysilicon is prevented from breaking at the climbing position of the gate line, thereby improving the yield.
  • an embodiment of the present invention provides an array substrate, which includes a base substrate, a buffer layer, an active layer, a dielectric insulating layer, and a source and drain layer that are stacked in sequence, wherein the base substrate is adjacent to The surface on one side of the buffer layer is recessed with a groove toward the surface on the opposite side thereof, the array substrate further includes a gate layer, and the gate layer is disposed in the groove of the base substrate.
  • the buffer layer is provided on the base substrate, the buffer layer completely covers the gate layer; the active layer is provided on the buffer layer, and it is provided with a channel region and two channels located in the channel region.
  • the dielectric insulating layer is provided on the active layer, and the source and drain layers are provided on the dielectric insulating layer, which are electrically connected to the doped region.
  • channel region and the gate layer are arranged completely corresponding to each other.
  • the depth of the groove is equal to the thickness of the gate layer ⁇ 20 nm.
  • the doped region includes a first doped region and a second doped region; the first doped region is provided on both sides of the channel region, and the first doped region passes through a high concentration of P ions.
  • the second doped region is formed between the channel region and the first doped region, and the second doped region is fabricated by doping with low-concentration P ions.
  • the buffer layer includes a first buffer layer and a second buffer layer; the first buffer layer is provided on the base substrate, and the first buffer layer completely covers the gate layer; Two buffer layers are provided on the first buffer layer, and the active layer is provided on the second buffer layer.
  • the dielectric insulating layer includes a first insulating layer and a second insulating layer; the first insulating layer is disposed on the buffer layer, and the first insulating layer completely covers the active layer; the The second insulating layer is disposed on the first insulating layer, and the source and drain layers are disposed on the second insulating layer.
  • the present invention also provides a manufacturing method of the array substrate, including the steps:
  • the depth of the groove is equal to the thickness of the prefabricated gate layer ⁇ 20nm;
  • Amorphous silicon is deposited on the buffer layer, the amorphous silicon becomes polycrystalline silicon after laser annealing, and then exposure, development, and etching processes are used to form a pattern of the active layer;
  • a source-drain layer is formed on the dielectric insulating layer, and the source-drain layer is electrically connected to the doped region.
  • making the buffer layer includes the steps:
  • a second buffer layer is made by depositing SiOx on the first buffer layer.
  • step of doping both ends of the active layer includes:
  • a second photomask is used to etch the photoresist layer to form a first doped region, the first doped region is provided on both sides of the active layer, and the first doped region is doped with a high concentration of P ions. miscellaneous;
  • the photoresist layer is etched by a dry etching machine, and the width of the photoresist layer is reduced to form a second doped region.
  • the second doped region is provided in the channel region and the first doped region. Between the impurity regions, the second doped region is doped by low-concentration P ions;
  • the photoresist layer is stripped from the active layer.
  • manufacturing the dielectric insulating layer includes the steps:
  • a second insulating layer is made by depositing SiOx on the first insulating layer.
  • the beneficial effect of the present invention is to provide an array substrate and a manufacturing method thereof.
  • a photomask is saved when the array substrate is manufactured, thereby reducing the number of masks used, and there is no need to manufacture a light-shielding layer.
  • the process is simplified, the production efficiency is improved, the process time is saved, and the cost is reduced; and the low-temperature polysilicon is prevented from breaking at the climbing position of the gate line, thereby increasing the yield.
  • FIG. 1 is a schematic diagram of the structure of an array substrate in an embodiment of the present invention.
  • FIG. 2 is a flowchart of a manufacturing method of an array substrate in an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a semi-finished product structure after the gate layer 2 is fabricated
  • FIG. 5 is a schematic diagram of the semi-finished product structure after the first doped region 421 is completed
  • FIG. 6 is a schematic diagram of the semi-finished product structure after the second doped region 422 is completed
  • FIG. 7 is a flowchart of the step of making the buffer layer in step S4 in FIG. 2;
  • FIG. 8 is a flowchart of the step of doping both ends of the active layer in step S6 of FIG. 2;
  • FIG. 9 is a flowchart of the steps of fabricating the dielectric insulating layer in step S8 in FIG. 2.
  • an array substrate 100 including a base substrate 1, a buffer layer 3, an active layer 4, a dielectric insulating layer 5, and a base substrate 1, a buffer layer 3, an active layer 4, and a dielectric insulating layer 5 stacked in sequence from bottom to top.
  • the array substrate 100 further includes a gate layer 2, the gate layer 2 is disposed in the groove 11 of the base substrate 1, the buffer layer 3 is disposed on the base substrate 1, and the buffer The layer 3 completely covers the gate layer 2; the active layer 4 is provided on the buffer layer 3, which is provided with a channel region 41 and doped regions 42 located on both sides of the channel region 41, so The dielectric insulating layer 5 is disposed on the active layer 4, and the source and drain layer 6 is disposed on the dielectric insulating layer 5, and it is electrically connected to the doped region 42.
  • the gate layer 2 is arranged in the groove 11 of the base substrate 1 to prevent the active layer 4 made of low-temperature polysilicon from being on the gate layer 2. Fracture occurred in the climbing place, thereby increasing the yield rate.
  • the channel region 41 and the gate layer 2 are arranged completely corresponding to each other.
  • the gate layer 2 can serve as a gate and also a light-shielding layer, so that the light-shielding layer can be reduced ( LS), a mask that simplifies the manufacturing process without making a light-shielding layer, thereby reducing the number of masks used and improving production efficiency.
  • the depth of the groove 11 is equal to the thickness of the gate layer 2 ⁇ 20 nm.
  • the depth of the groove 11 is equal to the thickness of the gate layer 2, so that the gate layer 2 completely fill the groove 11, and the upper surface of the gate layer 2 is flush with the upper surface of the base substrate 1, which can effectively prevent the active layer 4 from being disposed on the gate layer 2
  • the occurrence of slope climbing ensures the flatness of the active layer 4 and prevents the active layer 4 from breaking, thereby improving the yield.
  • the doped region 42 includes a first doped region 421 and a second doped region 422; the first doped region 421 is provided on both sides of the channel region 41, and the first doped region
  • the doped region 421 is an N+ doped region, which is made by high-concentration P (phosphorus) ion doping, and the high-concentration P ion doping is lightly doped;
  • the second doped region 422 is provided in the channel region 41 Between the first doped region 421 and the second doped region 422, the second doped region 422 is an N-doped region, which is made by doping with low-concentration P (phosphorus) ions.
  • the source-drain layer 6 includes a source electrode 61 and a drain electrode 62, which are electrically connected to the first doped regions 421 located on both sides of the channel region 41, respectively.
  • the buffer layer 3 includes a first buffer layer 31 and a second buffer layer 32; the first buffer layer 31 is provided on the base substrate 1, and the first buffer layer 31 completely covers all The gate layer 2; the material of the first buffer layer 31 includes SiNx; the second buffer layer 32 is provided on the first buffer layer 31, and the active layer 4 is provided on the second buffer layer 32 on; the material of the second buffer layer 32 includes SiOx.
  • the dielectric insulating layer 5 includes a first insulating layer 51 and a second insulating layer 52; the first insulating layer 51 is disposed on the buffer layer 3, and the first insulating layer 51 completely covers The active layer 4; the material of the first insulating layer 51 includes SiNx; the second insulating layer 52 is disposed on the first insulating layer 51, and the source drain layer 6 is disposed on the second insulating layer. On the insulating layer 52; the material of the second insulating layer 52 includes SiOx.
  • the present invention also provides a manufacturing method of the array substrate 100, which includes the steps:
  • FIG. 1 is a schematic diagram of the semi-finished product structure after the completion of the fabrication of the gate layer 2;
  • FIG. 1 it is a schematic diagram of the structure of the fabricated array substrate 100.
  • the gate layer 2 is arranged in the groove 11 of the base substrate 1 to prevent the active layer 4 made of low-temperature polysilicon from being on the gate layer 2. Fracture occurred in the climbing place, thereby increasing the yield rate.
  • the depth of the groove 11 is equal to the thickness of the gate layer 2, so that the gate layer 2 can completely fill the groove 11, and the upper part of the gate layer 2
  • the surface is flush with the upper surface of the base substrate 1, which can effectively prevent the active layer 4 from climbing on the gate layer 2, ensure the flatness of the active layer 4, and avoid all problems.
  • the active layer 4 is broken, thereby increasing the yield rate.
  • the channel region 41 and the gate layer 2 are arranged completely corresponding to each other.
  • the gate layer 2 can serve as a gate and also a light-shielding layer, so that the light-shielding layer can be reduced ( LS), a mask that simplifies the manufacturing process without making a light-shielding layer, thereby reducing the number of masks used and improving production efficiency.
  • step S4 of this embodiment manufacturing the buffer layer 3 includes the following steps:
  • step S6 of this embodiment the step of doping both ends of the active layer 4 includes:
  • FIG. 5 is a schematic diagram of a semi-finished product structure after the first doped region 421 is completed;
  • FIG. 6 is a schematic diagram of the semi-finished product structure after the second doped region 422 is completed.
  • fabricating the dielectric insulating layer 5 includes the following steps:
  • the beneficial effect of the present invention is to provide an array substrate 100 and a manufacturing method thereof.
  • a photomask is saved when the array substrate 100 is manufactured, thereby reducing the number of masks used, and no manufacturing is required.
  • the light-shielding layer simplifies the manufacturing process, improves the production efficiency, saves the manufacturing time, and reduces the cost; and it prevents the low-temperature polysilicon from breaking at the climbing position of the gate line, thereby increasing the yield.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Thin Film Transistor (AREA)

Abstract

本发明公开了一种阵列基板及其制作方法。阵列基板包括依次层叠设置的衬底基板、缓冲层、有源层、介电绝缘层和源漏极层，其中在衬底基板临近缓冲层一侧的表面向其相反的一侧的表面凹设有凹槽，阵列基板还包括栅极层，栅极层设置于衬底基板的凹槽内，缓冲层设于衬底基板上，缓冲层完全覆盖栅极层。

Description

一种阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种顶栅薄膜晶体管的阵列基板及其制作方法。
 背景技术
薄膜晶体管液晶显示器（TFT-LCD）具有耗电量小、对比度高、节省空间等优点，已成为市场上最主流的显示装置。与传统非晶硅（A-Si）技术相比，低温多晶硅（LTPS）技术具有更高的载流子迁移率，被广泛用于中小尺寸高分辨率的薄膜晶体管液晶显示器和有源矩阵有机发光二极管（AMOLED）面板的制作，但相应的阵列基板制作所需的光罩数量更多，产品制作周期更长。如何有效的降低低温多晶硅阵列基板的制作周期，提升生产产能及降低成本，从而增加公司市场竞争力，是目前面板行业关注的重点，而改善此问题的有效的方法是开发新型低温多晶硅阵列基板结构，减少阵列制作所需的光罩数量。
在传统的低温多晶硅阵列基板技术中，通常采用顶栅（Top Gate）外加遮光层（Light Shield layer，LS）结构，其中遮光层的制备需要新增一道LS光罩，在阵列基板沟道下方形成一块不透光的图案, 其作用主要是在面板工作中，阻挡背光源直接照射到阵列基板沟道从而引起光生漏电流，过大的漏电流将显著影响产品的光学显示效果，如串扰（Crosstalk）、闪烁（flicker）、对比度等。因此如何在省去LS光罩，减少产品制作周期及降低生产成本的基础上，通过器件结构改善来有效降低光生漏电流是低温多晶硅阵列基板技术开发的重要内容。
目前有一种方案是采用底栅（Bottom Gate）结构的阵列基板，栅极（Gate）走线既能当栅极用能起到遮光层的作用，这样就能省一道LS光罩。但由于栅极线较厚，会造成低温多晶硅在栅极线的爬坡处发生断裂，从而影响电性。
因此，确有必要来开发一种新型的阵列基板及其制作方法，来克服现有技术中的缺陷。
 技术问题
本发明提供一种阵列基板及其制作方法，通过采用底栅结构，使得在制作阵列基板时节省一道光罩，从而减少了掩膜板使用的数目，并不需制作遮光层简化了制程，提高了生产效率，节省了制程时间，降低了成本；并且避免了低温多晶硅在栅极线的爬坡处发生断裂，从而提高了良品率。
 技术解决方案
为了实现上述目的，本发明实施例中提供一种阵列基板，包括依次层叠设置的衬底基板、缓冲层、有源层、介电绝缘层和源漏极层，其中在所述衬底基板临近所述缓冲层一侧的表面向其相反的一侧的表面凹设有凹槽，所述阵列基板还包括栅极层，所述栅极层设置于所述衬底基板的凹槽内，述缓冲层设于所述衬底基板上，所述缓冲层完全覆盖所述栅极层；所述有源层设于所述缓冲层上，其设有沟道区和位于所述沟道区两侧的掺杂区，所述介电绝缘层设于所述有源层上，所述源漏极层设于所述介电绝缘层上，其与所述掺杂区电性连接。
进一步地，所述沟道区与所述栅极层完全对应设置。
进一步地，所述凹槽的深度等于所述栅极层的厚度±20nm。
进一步地，所述掺杂区包括第一掺杂区以及第二掺杂区；所述第一掺杂区设于所述沟道区两侧，所述第一掺杂区通过高浓度P离子掺杂的方式制作；所述第二掺杂区设于所述沟道区与所述第一掺杂区之间，所述第二掺杂区通过低浓度P离子掺杂的方式制作。
进一步地，所述缓冲层包括第一缓冲层以及第二缓冲层；所述第一缓冲层设于所述衬底基板上，所述第一缓冲层完全覆盖所述栅极层；所述第二缓冲层设于所述第一缓冲层上，所述有源层设于所述第二缓冲层上。
进一步地，所述介电绝缘层包括第一绝缘层以及第二绝缘层；所述第一绝缘层设于所述缓冲层上，所述第一绝缘层完全覆盖所述有源层；所述第二绝缘层设于所述第一绝缘层上，所述源漏极层设于所述第二绝缘层上。
本发明还提供一种阵列基板的制作方法，包括步骤：
提供一衬底基板，在所述衬底基板上涂布负性光阻，利用第一光罩曝光显影后形成刻蚀通孔图案；
利用干刻蚀工艺直接刻蚀所述衬底基板制作凹槽，所述凹槽的深度等于预制作栅极层的厚度±20nm；
通过物理气相沉积的方式制作栅极层，所述栅极层完全填满所述凹槽；
将所述负性光阻从所述衬底基板上剥离，并在所述衬底基板上制作缓冲层；
在所述缓冲层上沉积非晶硅，经过激光退火后非晶硅变为多晶硅，再利用曝光、显影、刻蚀工艺形成有源层的图案；
对所述有源层的两端进行掺杂形成沟道区和位于所述沟道区两侧的掺杂区；
在所述有源层上制作介电绝缘层；以及
在所述介电绝缘层上制作源漏极层，所述源漏极层与所述掺杂区电性连接。
进一步地，制作所述缓冲层包括步骤：
在所述衬底基板上通过沉积SiNx制作第一缓冲层；以及
在所述第一缓冲层上通过沉积SiOx制作第二缓冲层。
进一步地，对所述有源层的两端进行掺杂的步骤包括：
在所述有源层上制作光阻层；
利用第二光罩蚀刻所述光阻层形成第一掺杂区，所述第一掺杂区设于所述有源层两侧，通过高浓度P离子对所述第一掺杂区进行掺杂；
利用干蚀刻机台对所述光阻层进行蚀刻，减小所述光阻层的宽度形成第二掺杂区，所述第二掺杂区设于所述沟道区与所述第一掺杂区之间，通过低浓度P离子对所述第二掺杂区进行掺杂；以及
从所述有源层上剥离所述光阻层。
进一步地，制作所述介电绝缘层包括步骤：
在所述缓冲层上通过沉积SiNx制作第一绝缘层；以及
在所述第一绝缘层上通过沉积SiOx制作第二绝缘层。
 有益效果
本发明的有益效果在于，提供一种阵列基板及其制作方法，通过采用底栅结构，使得在制作阵列基板时节省一道光罩，从而减少了掩膜板使用的数目，并不需制作遮光层简化了制程，提高了生产效率，节省了制程时间，降低了成本；并且避免了低温多晶硅在栅极线的爬坡处发生断裂，从而提高了良品率。
 附图说明
图1为本发明实施例中一种阵列基板的结构示意图；
图2为本发明实施例中一种阵列基板的制作方法的流程图；
图3为完成制作所述栅极层2后的半成品结构示意图；
图4为完成制作所述有源层4后的半成品结构示意图；
图5为完成制作所述第一掺杂区421后的半成品结构示意图；
图6为完成制作所述第二掺杂区422后的半成品结构示意图；
图7为图2步骤S4中制作所述缓冲层步骤的流程图；
图8为图2步骤S6中对所述有源层的两端进行掺杂步骤的流程图；
图9为图2步骤S8中制作所述介电绝缘层步骤的流程图。
图中部件标识如下：
1、衬底基板，2、栅极层，3、缓冲层，4、有源层，
5、介电绝缘层，6、源漏极层，7、负性光阻，8、光阻层，
11、凹槽，31、第一缓冲层，32、第二缓冲层，41、沟道区，
42、掺杂区，51、第一绝缘层，52、第二绝缘层，61、源电极，
62、漏电极，100、阵列基板，421、第一掺杂区，422、第二掺杂区。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
具体的，请参阅图1所示，本发明实施例中提供一种阵列基板100，包括从下至上依次层叠设置的衬底基板1、缓冲层3、有源层4、介电绝缘层5和源漏极层6，其中，所述衬底基板1为裸玻璃基板，在所述衬底基板1临近所述缓冲层3一侧的表面向其相反的一侧的表面凹设有凹槽11，所述阵列基板100还包括栅极层2，所述栅极层2设置于所述衬底基板1的凹槽11内，述缓冲层3设于所述衬底基板1上，所述缓冲层3完全覆盖所述栅极层2；所述有源层4设于所述缓冲层3上，其设有沟道区41和位于所述沟道区41两侧的掺杂区42，所述介电绝缘层5设于所述有源层4上，所述源漏极层6设于所述介电绝缘层5上，其与所述掺杂区42电性连接。
本实施例通过采用底栅结构，将所述栅极层2设于所述衬底基板1的凹槽11内，避免了低温多晶硅材质的所述有源层4在所述栅极层2上的爬坡处发生断裂，从而提高了良品率。
本实施例中，所述沟道区41与所述栅极层2完全对应设置，所述栅极层2既能作为栅极，也能起到遮光层的作用，这样就能减少遮光层（LS），不需制作遮光层简化了制程的一道掩膜板，从而减少了掩膜板使用的数目，提高了生产效率。
本实施例中，所述凹槽11的深度等于所述栅极层2的厚度±20nm，优选所述凹槽11的深度等于所述栅极层2的厚度，这样能够使得所述栅极层2完全填满所述凹槽11，所述栅极层2的上表面与所述衬底基板1的上表面齐平，能够有效避免所述有源层4设置在所述栅极层2上出现爬坡，保证了所述有源层4的平整，避免了所述有源层4发生断裂，从而提高了良品率。
本实施例中，所述掺杂区42包括第一掺杂区421以及第二掺杂区422；所述第一掺杂区421设于所述沟道区41两侧，所述第一掺杂区421为N+掺杂区，通过高浓度P(磷)离子掺杂的方式制作，高浓度P离子掺杂为轻掺杂；所述第二掺杂区422设于所述沟道区41与所述第一掺杂区421之间，所述第二掺杂区422为N-掺杂区，通过低浓度P（磷）离子掺杂的方式制作。
具体的，所述源漏极层6包括源电极61和漏电极62，分别与位于所述沟道区41两侧的第一掺杂区421电性连接。
本实施例中，所述缓冲层3包括第一缓冲层31以及第二缓冲层32；所述第一缓冲层31设于所述衬底基板1上，所述第一缓冲层31完全覆盖所述栅极层2；所述第一缓冲层31的材质包括SiNx；所述第二缓冲层32设于所述第一缓冲层31上，所述有源层4设于所述第二缓冲层32上；所述第二缓冲层32的材质包括SiOx。
本实施例中，所述介电绝缘层5包括第一绝缘层51以及第二绝缘层52；所述第一绝缘层51设于所述缓冲层3上，所述第一绝缘层51完全覆盖所述有源层4；所述第一绝缘层51的材质包括SiNx；所述第二绝缘层52设于所述第一绝缘层51上，所述源漏极层6设于所述第二绝缘层52上；所述第二绝缘层52的材质包括SiOx。
请参阅图2所示，本发明还提供一种阵列基板100的制作方法，包括步骤：
S1、提供一衬底基板1，在所述衬底基板1上涂布负性光阻7，利用第一光罩曝光显影后形成刻蚀通孔图案；由于负性光阻7的特性，会产生底切结构；其中所述刻蚀通孔的横截面呈矩形或倒梯形，便于后续通过物理气相沉积的方式制作栅极层2；
S2、利用干刻蚀工艺直接刻蚀所述衬底基板1制作凹槽11，所述凹槽11的深度等于预制作栅极层2的厚度±20nm；
S3、通过物理气相沉积的方式制作栅极层2，所述栅极层2完全填满所述凹槽11，使所述栅极层2的上表面与所述衬底基板1的上表面齐平；图3为完成制作所述栅极层2后的半成品结构示意图；
S4、将所述负性光阻7从所述衬底基板1上剥离，并在所述衬底基板1上制作缓冲层3；
S5、在所述缓冲层3上沉积非晶硅，经过激光退火后非晶硅变为多晶硅，再利用曝光、显影、刻蚀工艺形成有源层4的图案；图4为完成制作所述有源层4后的半成品结构示意图；
S6、对所述有源层4的两端进行掺杂形成沟道区41和位于所述沟道区41两侧的掺杂区42；其过程如图5、图6所示；
S7、在所述有源层4上制作介电绝缘层5；以及
S8、在所述介电绝缘层5上制作源漏极层6，所述源漏极层6与所述掺杂区42电性连接。
如图1所示，为制作完成的所述阵列基板100的结构示意图。
本实施例通过采用底栅结构，将所述栅极层2设于所述衬底基板1的凹槽11内，避免了低温多晶硅材质的所述有源层4在所述栅极层2上的爬坡处发生断裂，从而提高了良品率。并且，在步骤S2中优选所述凹槽11的深度等于所述栅极层2的厚度，这样能够使得所述栅极层2完全填满所述凹槽11，所述栅极层2的上表面与所述衬底基板1的上表面齐平，能够有效避免所述有源层4设置在所述栅极层2上出现爬坡，保证了所述有源层4的平整，避免了所述有源层4发生断裂，从而提高了良品率。
本实施例中，所述沟道区41与所述栅极层2完全对应设置，所述栅极层2既能作为栅极，也能起到遮光层的作用，这样就能减少遮光层（LS），不需制作遮光层简化了制程的一道掩膜板，从而减少了掩膜板使用的数目，提高了生产效率。
请参阅图7所示，本实施例步骤S4中，制作所述缓冲层3包括步骤：
S41、在所述衬底基板1上通过沉积SiNx制作第一缓冲层31；以及
S42、在所述第一缓冲层31上通过沉积SiOx制作第二缓冲层32。
请参阅图8所示，本实施例步骤S6中，对所述有源层4的两端进行掺杂的步骤包括：
S61、在所述有源层4上制作光阻层8；
S62、利用第二光罩蚀刻所述光阻层8形成第一掺杂区421，所述第一掺杂区421设于所述有源层4两侧，通过高浓度P离子对所述第一掺杂区421进行掺杂，掺杂后的所述第一掺杂区421为N+掺杂区；图5为完成制作所述第一掺杂区421后的半成品结构示意图；
S63、利用干蚀刻机台对所述光阻层8进行蚀刻，减小所述光阻层8的宽度形成第二掺杂区422，所述第二掺杂区422设于所述沟道区41与所述第一掺杂区421之间，通过低浓度P离子对所述第二掺杂区422进行掺杂，掺杂后的所述第二掺杂区422为N-掺杂区；图6为完成制作所述第二掺杂区422后的半成品结构示意图；以及
S64、从所述有源层4上剥离所述光阻层8。
请参阅图9所示，本实施例步骤S8中，制作所述介电绝缘层5包括步骤：
S81、在所述缓冲层3上通过沉积SiNx制作第一绝缘层51；以及
S82、在所述第一绝缘层51上通过沉积SiOx制作第二绝缘层52。
本发明的有益效果在于，提供一种阵列基板100及其制作方法，通过采用底栅结构，使得在制作阵列基板100时节省一道光罩，从而减少了掩膜板使用的数目，并不需制作遮光层简化了制程，提高了生产效率，节省了制程时间，降低了成本；并且避免了低温多晶硅在栅极线的爬坡处发生断裂，从而提高了良品率。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种阵列基板，其包括依次层叠设置的衬底基板，缓冲层，有源层，介电绝缘层和源漏极层，其中：
    在所述衬底基板临近所述缓冲层一侧的表面向其相反的一侧的表面凹设有凹槽，所述阵列基板还包括栅极层，所述栅极层设置于所述衬底基板的凹槽内，所述缓冲层设于所述衬底基板上，所述缓冲层完全覆盖所述栅极层；
    所述有源层设于所述缓冲层上，其设有沟道区和位于所述沟道区两侧的掺杂区，所述介电绝缘层设于所述有源层上，所述源漏极层设于所述介电绝缘层上，其与所述掺杂区电性连接。
  2. 根据权利要求1所述的阵列基板，其中，所述沟道区与所述栅极层对应设置。
  3. 根据权利要求1所述的阵列基板，其中，所述凹槽的深度等于所述栅极层的厚度±20nm。
  4. 根据权利要求1所述的阵列基板，其中，所述掺杂区包括：
    第一掺杂区，设于所述沟道区两侧，所述第一掺杂区通过高浓度P离子掺杂的方式制作；以及
    第二掺杂区，设于所述沟道区与所述第一掺杂区之间，所述第二掺杂区通过低浓度P离子掺杂的方式制作。
  5. 根据权利要求1所述的阵列基板，其中，所述缓冲层包括：
    第一缓冲层，设于所述衬底基板上，所述第一缓冲层完全覆盖所述栅极层；以及
    第二缓冲层，设于所述第一缓冲层上，所述有源层设于所述第二缓冲层上。
  6. 根据权利要求1所述的阵列基板，其中，所述介电绝缘层包括：
    第一绝缘层，设于所述缓冲层上，所述第一绝缘层完全覆盖所述有源层；以及
    第二绝缘层，设于所述第一绝缘层上，所述源漏极层设于所述第二绝缘层上。
  7. 一种阵列基板的制作方法，其中，包括步骤：
    提供一衬底基板，在所述衬底基板上涂布负性光阻，利用第一光罩曝光显影后形成刻蚀通孔图案；
    利用干刻蚀工艺直接刻蚀所述衬底基板制作凹槽，所述凹槽的深度等于预制作栅极层的厚度±20nm；
    通过物理气相沉积的方式制作栅极层，所述栅极层完全填满所述凹槽；
    将所述负性光阻从所述衬底基板上剥离，并在所述衬底基板上制作缓冲层；
    在所述缓冲层上沉积非晶硅，经过激光退火后非晶硅变为多晶硅，再利用曝光、显影、刻蚀工艺形成有源层的图案；
    对所述有源层的两端进行掺杂形成沟道区和位于所述沟道区两侧的掺杂区；
    在所述有源层上制作介电绝缘层；以及
    在所述介电绝缘层上制作源漏极层，所述源漏极层与所述掺杂区电性连接。
  8. 根据权利要求7所述的阵列基板的制作方法，其中，制作所述缓冲层包括步骤：
    在所述衬底基板上通过沉积SiNx制作第一缓冲层；以及
    在所述第一缓冲层上通过沉积SiOx制作第二缓冲层。
  9. 根据权利要求7所述的阵列基板的制作方法，其中，对所述有源层的两端进行掺杂的步骤包括：
    在所述有源层上制作光阻层；
    利用第二光罩蚀刻所述光阻层形成第一掺杂区，所述第一掺杂区设于所述有源层两侧，通过高浓度P离子对所述第一掺杂区进行掺杂；
    利用干蚀刻机台对所述光阻层进行蚀刻，减小所述光阻层的宽度形成第二掺杂区，所述第二掺杂区设于所述沟道区与所述第一掺杂区之间，通过低浓度P离子对所述第二掺杂区进行掺杂；以及
    从所述有源层上剥离所述光阻层。
  10. 根据权利要求7所述的阵列基板的制作方法，其中，制作所述介电绝缘层包括步骤：
    在所述缓冲层上通过沉积SiNx制作第一绝缘层；以及
    在所述第一绝缘层上通过沉积SiOx制作第二绝缘层。
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