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WO2021104311A1 - 一种功放合路装置及功放电路 - Google Patents

一种功放合路装置及功放电路 Download PDF

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Publication number
WO2021104311A1
WO2021104311A1 PCT/CN2020/131513 CN2020131513W WO2021104311A1 WO 2021104311 A1 WO2021104311 A1 WO 2021104311A1 CN 2020131513 W CN2020131513 W CN 2020131513W WO 2021104311 A1 WO2021104311 A1 WO 2021104311A1
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Prior art keywords
power amplifier
power
unit
threshold
units
Prior art date
Application number
PCT/CN2020/131513
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English (en)
French (fr)
Inventor
曾志雄
孙捷
Original Assignee
华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20891763.3A priority Critical patent/EP4044430A4/en
Publication of WO2021104311A1 publication Critical patent/WO2021104311A1/zh
Priority to US17/744,033 priority patent/US20220271716A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/04—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in discharge-tube amplifiers
    • H03F1/06—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in discharge-tube amplifiers to raise the efficiency of amplifying modulated radio frequency waves; to raise the efficiency of amplifiers acting also as modulators
    • H03F1/07—Doherty-type amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0277—Selecting one or more amplifiers from a plurality of amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0294—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using vector summing of two or more constant amplitude phase-modulated signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/387—A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H03F2203/21109—An input signal being distributed by switching to a plurality of paralleled power amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H03F2203/21142—Output signals of a plurality of power amplifiers are parallel combined to a common output
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H03F2203/21154—An output signal of a power amplifier being controlled by controlling voltage signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H03F2203/21196—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers the supply voltage of a power amplifier being switchable controlled

Definitions

  • the embodiment of the present invention relates to the technical field of electronic circuits, in particular to a power amplifier combining device and a power amplifier circuit.
  • multiple power amplifier units can be connected in parallel, that is, the inputs of multiple power amplifier units are connected together, the outputs of multiple power amplifier units are connected together, and the bias voltages of the multiple power amplifier units are set to the same value.
  • the output power of the multiple power amplifier units in parallel is the sum of the output power of each power amplifier unit in the multiple power amplifier units, so that the output power can be increased.
  • the output power of each power amplifier unit is less than the maximum output power of a single power amplifier unit, which reduces the conversion efficiency of the power amplifier unit, resulting in higher power consumption of the power amplifier unit.
  • the embodiment of the invention discloses a power amplifier combining device and a power amplifier circuit, which are used for reducing the power consumption of the power amplifier unit.
  • the first aspect discloses a power amplifier combining device, which includes a signal processing unit and n power amplifier units.
  • the signal processing unit is respectively coupled to the input ends of the n power amplifier units, and the output ends of the n power amplifier units are respectively coupled to the load, and the signal processing unit is used
  • the first power amplifier unit is controlled to work, and when the output power is greater than or equal to the ith threshold and less than the i+1 threshold, the first power amplifier unit is controlled to The i+1th power amplifier unit works, and when the output power is greater than or equal to the n-1th threshold, the n power amplifier units are controlled to work.
  • n is an integer greater than 1.
  • the first threshold,..., the n-1th threshold increase sequentially. Because when the required output power is small, a smaller number of power amplifier units can provide the required output power. When the required output power is large, the number of working power amplifier units can be increased to provide the additional required output power. . Therefore, as the required output power increases, increasing the number of work of the power amplifier unit can increase the conversion efficiency of the power amplifier unit, thereby reducing the power consumption of the power amplifier unit.
  • the output ends of the n power amplifier units are respectively coupled to the load through a matching network, so as to ensure impedance matching.
  • the signal processing unit is further configured to provide radio frequency excitation signals for n power amplifier units.
  • the amplitude and phase of the RF excitation signal can be controlled within a very small power level. Therefore, the signal processing unit has a wider bandwidth and lower power consumption.
  • the signal processing unit is also used to provide bias voltages for n power amplifier units, which can improve the control power of the signal processing unit.
  • the bias voltages of the first power amplifier unit,..., And the nth power amplifier unit are sequentially reduced.
  • This configuration of the bias voltage, in conjunction with the signal processing unit to output the corresponding radio frequency excitation signal, can realize the gradual operation of n power amplifier units as the output power of the power amplifier combining device increases, thereby reducing the power consumption of the power amplifier unit.
  • the bias voltages of the first power amplifier unit,..., And the nth power amplifier unit remain unchanged. Since there is no need to adjust the bias state of the power amplifier unit according to the envelope change of the input signal of the power amplifier combining device, even if the size of the power tube in the power amplifier unit is large and the parasitic parameters are large, the signal processing unit will not increase. Additional power consumption, so there is no strict requirement on the size and type of the power tube.
  • the first threshold is the maximum output power of the first power amplifier unit
  • a second aspect discloses a power amplifier circuit.
  • the power amplifier circuit may include two power amplifier branches, and at least one of the two power amplifier branches is the power amplifier combination disclosed in the first aspect or any one of the first aspects. Device.
  • the power amplifier circuit can be a Doherty power amplifier, a Chireix power amplifier, an outphasing power amplifier, or other power amplifiers with the same function. Circuit.
  • Fig. 1 is a schematic structural diagram of a power amplifier combining device disclosed in an embodiment of the present invention
  • FIG. 2 is a schematic diagram of the output power of a power amplifier combining device corresponding to the operation of different numbers of power amplifier units disclosed in an embodiment of the present invention
  • Fig. 3 is a schematic structural diagram of another power amplifier combining device disclosed in an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of radio frequency excitation signals and bias voltages provided by a signal processing unit for n power amplifier units according to an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of another power amplifier combining device disclosed in an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of the output power of another power amplifier combining device corresponding to the operation of a different number of power amplifier units disclosed in an embodiment of the present invention
  • FIG. 7 is a schematic diagram of the output power of a power amplifier combining device and the impedance of a power amplifier unit disclosed in an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of the output power of a power amplifier combining device and the output power and drain efficiency of a power amplifier unit according to an embodiment of the present invention
  • FIG. 9 is a schematic diagram of the amplitude difference and the phase difference between the output power of a power amplifier combining device and the RF excitation signal of the power amplifier unit disclosed in an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of output power and impedance of a power amplifier combining device disclosed in an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of a load pulling path of a power amplifier unit in a Smith chart disclosed in an embodiment of the present invention
  • Fig. 12 is a schematic structural diagram of a power amplifier circuit disclosed in an embodiment of the present invention.
  • FIG. 13 is a schematic structural diagram of a traditional Doherty power amplifier disclosed in an embodiment of the present invention.
  • FIG. 14 is a schematic structural diagram of a new type of Doherty power amplifier disclosed in an embodiment of the present invention.
  • 15 is a schematic diagram of output power, gain, and drain efficiency of a new type of Doherty power amplifier and a traditional Doherty power amplifier disclosed in an embodiment of the present invention
  • 16 is a schematic diagram of output power and gain and PAE of a new type of Doherty power amplifier and a traditional Doherty power amplifier disclosed in an embodiment of the present invention
  • 17 is a schematic diagram of the output power of a new type of Doherty power amplifier and the traditional Doherty power amplifier and the output power and drain efficiency of the power amplifier unit disclosed in the embodiment of the present invention;
  • 18 is a schematic diagram of the output power of a new type of Doherty power amplifier and a traditional Doherty power amplifier disclosed in an embodiment of the present invention and the impedance of the junction point and the power amplifier unit;
  • 19 is a schematic diagram of the load pulling path of the power amplifier unit of a new type of Doherty power amplifier and a traditional Doherty power amplifier in a Smith chart disclosed in an embodiment of the present invention
  • 20 is a schematic diagram of the amplitude difference and the phase difference of the RF excitation signal of the power amplifier unit of a new type of Doherty power amplifier and a traditional Doherty power amplifier disclosed in an embodiment of the present invention.
  • the embodiment of the invention discloses a power amplifier combining device and a power amplifier circuit, which are used for reducing the power consumption of the power amplifier unit. Detailed descriptions are given below.
  • FIG. 1 is a schematic structural diagram of a power amplifier combining device disclosed in an embodiment of the present invention.
  • n power amplifier units namely, power amplifier unit T 1 , power amplifier unit T 2 , ..., power amplifier unit T n
  • the inputs of n power amplifier units can be connected together, and these n
  • the impedance of the load is R opt
  • the maximum output power of the power amplifier combining device is P opt .
  • n is an integer greater than 1.
  • FIG. 2 is a schematic diagram of the output power of a power amplifier combining device corresponding to different numbers of power amplifier units working according to an embodiment of the present invention.
  • the power amplifier combining device Although different numbers of power amplifier units can work to achieve the same output power, the fewer power amplifier units work, the greater the output power of each power amplifier unit, and the higher the peak efficiency. That is, the higher the conversion efficiency, the lower the power consumption. Therefore, when the power amplifier combining device includes a certain number of power amplifier units, how to improve the conversion efficiency of the power amplifier unit so as to reduce the power consumption of the power amplifier unit has become an urgent technical problem to be solved.
  • FIG. 3 is a schematic structural diagram of another power amplifier combining device disclosed in an embodiment of the present invention.
  • the power amplifier combining device may include a signal processing unit and n power amplifier units, where n is an integer greater than 1, where:
  • the signal processing unit is respectively coupled to the input ends of the n power amplifier units, and the output ends of the n power amplifier units are respectively coupled to the load;
  • the signal processing unit is used to control the operation of the first power amplifier unit T 1 when the output power of the power amplifier combining device is less than the first threshold.
  • the output power of the power amplifier combining device is greater than or equal to the ith threshold and less than the i+th threshold
  • the n power amplifier units T 1 , T 2 , ..., T n are not connected in parallel, and the signal processing unit can control the operation or non-operation of the n power amplifier units.
  • the first power amplifier unit T 1 can provide the output power required by the power amplifier combining device by working, therefore, the first power amplifier unit T 1 can be controlled to work, and Control other power amplifier units not to work.
  • the first power amplifier unit T 1 to the (i+1)th power amplifier unit T i+1 work can provide the power amplifier combination
  • the output power required by the device therefore, the first power amplifier unit T 1 to the i+1 th power amplifier unit T i+1 can be controlled to work, and the remaining power amplifier units can be controlled not to work.
  • the output power of the power amplifier combining device is greater than or equal to the n-1th threshold, all n power amplifier units are required to work to provide the output power required by the power amplifier combining device. Therefore, n power amplifier units can be controlled to work.
  • the output power of the power amplifier combining device is greater than or equal to the first threshold and less than the second threshold, the first power amplifier unit T 1 and the second power amplifier unit T 2 can be controlled to work, and the third power amplifier unit T 3 and the third power amplifier unit T 3 can be controlled to work.
  • the fourth power amplifier unit T 4 does not work.
  • the power amplifier unit can be a power amplifier device, such as a metal oxide semiconductor (MOS) tube, or a unit with a power amplifier function composed of multiple devices.
  • the output power of the power amplifier combining device is the RF output power of the power amplifier combining device.
  • the output ends of the n power amplifier units are respectively coupled to the load through a matching network, that is, the matching network is respectively coupled to the output ends and the load of the n power amplifier units.
  • the output ends of the n power amplifier units are first connected together and then connected with the matching network, that is, the output ends of the n power amplifier units are connected together, so that the output power of the power amplifier combining device is equal to the n power amplifier units The sum of the output power.
  • the matching network can ensure impedance matching.
  • the signal processing unit is further used to provide radio frequency excitation signals for n power amplifier units.
  • the signal processing unit may provide radio frequency excitation signals for n power amplifier units, and the radio frequency excitation signals of the n power amplifier units may all be the same, or all may be different, or may be partly the same and partly different, which is not limited herein.
  • the signal processing unit may include m control channels, and the m control channels may be independent of each other, that is, the m control channels are mutually independent. There is no connection between them, and each control channel generates a radio frequency excitation signal.
  • One radio frequency excitation signal can be used as the radio frequency excitation signal of one power amplifier unit, or can be used as the radio frequency excitation signal of multiple power amplifier units, which is not limited here.
  • the signal processing unit may also include a control path, but this control path may include m branches, and each branch generates a radio frequency excitation signal.
  • m is an integer greater than 1 and less than or equal to n.
  • the signal processing unit is also used to provide bias voltages for n power amplifier units.
  • the signal processing unit may also provide bias voltages for n power amplifier units.
  • the bias voltages of the n power amplifier units may all be the same, or all may be different, and may also be partly the same and partly different, which is not limited here.
  • the signal processing unit may include m control paths, and the m control paths may be independent of each other, that is, the m control paths are mutually independent. There is no connection between them, and each control channel generates a bias voltage.
  • a bias voltage can be used as the bias voltage of one power amplifier unit or as the bias voltage of multiple power amplifier units, which is not limited here.
  • the signal processing unit may also include a control path, but this control path may include m branches, and each branch generates a bias voltage.
  • the bias voltages of the first power amplifier unit,..., And the nth power amplifier unit are sequentially reduced.
  • the bias voltages of the first power amplifier unit,..., And the nth power amplifier unit remain unchanged.
  • FIG. 4 is a schematic diagram of a radio frequency excitation signal and bias voltage provided by a signal processing unit for n power amplifier units according to an embodiment of the present invention.
  • a first amplifier unit T bias voltage V g1 4 1 the second power amplifier unit T of the bias voltage V g2 2, ..., n n-th unit T amplifier bias voltage V gn successively lowered, n
  • the radio frequency excitation signals of the power amplifier units are the same, and when the amplitude of the radio frequency excitation signal is within different threshold ranges, the number of working power amplifier units is different.
  • the bias voltage of the power amplifier unit may not change with the change of the RF excitation signal.
  • the first threshold is the maximum output power of the first power amplifier unit
  • the maximum output power of each power amplifier unit that is, the maximum RF output power
  • the maximum output power of the n power amplifier units may all be the same, or all may be different, and may also be partly the same and partly different, which is not limited here.
  • the first threshold may be the maximum output power of the first power amplifier unit
  • the second threshold may be the sum of the first threshold and the maximum output power of the second power amplifier unit
  • the n-1th threshold is the n-2th threshold and the nth -1 The sum of the maximum output power of the power amplifier unit.
  • the first power amplifier unit can be the power amplifier unit with the largest maximum output power among the maximum output powers of the n power amplifier units, or n power amplifier units
  • the power amplifier unit with the smallest maximum output power among the maximum output powers may also be other power amplifier units, which are not limited here.
  • the signal processing unit controls the first power amplifier unit to work when the output power of the power amplifier combining device is less than the first threshold, and controls the first power amplifier unit when the output power is greater than or equal to the ith threshold and less than the (i+1)th threshold.
  • One power amplifier unit to the i+1th power amplifier unit work, and when the output power is greater than or equal to the n-1th threshold, the n power amplifier units are controlled to work, that is, when the input power of the power amplifier combining device is less than the first threshold and A
  • the first power amplifier unit is controlled to work, and when the input power of the power amplifier combining device is greater than or equal to the ratio of the i-th threshold to A and less than the ratio of the i+1th threshold to A, the first power amplifier unit is controlled Until the (i+1)th power amplifier unit works, when the input power of the power amplifier combining device is greater than or equal to the ratio of the n-1th threshold to A, the n power amplifier units are controlled to work.
  • A is the gain of the power amplifier combining device.
  • FIG. 5 is a schematic structural diagram of another power amplifier combining device disclosed in an embodiment of the present invention.
  • the power amplifier combining device may include two power amplifier units, and the bias voltages of the two power amplifier units are different.
  • FIG. 6 is a schematic diagram of the output power of another power amplifier combining device corresponding to the operation of different numbers of power amplifier units disclosed in an embodiment of the present invention. 6 when the input signal amplitude is small combiner amplifier means, the amplifier is in working condition. 1 unit T, the smaller the RF excitation signal amplifier unit T 2, T power amplifier unit 2 in the inoperative state, i.e., closed state , Or in a state where the output power is very small.
  • FIG. 7 is a schematic diagram of the output power and the impedance of the power amplifier unit of a power amplifier combining device disclosed in an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of the output power of a power amplifier combining device and the output power and drain efficiency of the power amplifier unit according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of the amplitude difference and the phase difference between the output power of a power amplifier combining device and the RF excitation signal of the power amplifier unit disclosed in an embodiment of the present invention.
  • the phase difference between the two power amplifier units in the power amplifier combining device corresponding to the present invention is fixed, that is, it does not change with the output power of the power amplifier combining device.
  • the corresponding power amplifier combining device of the present invention The amplitude difference of the RF excitation signals of the two power amplifier units in the device increases with the increase of the output power of the power amplifier combining device.
  • the amplitude difference and phase difference of the two power amplifier units are fixed, that is, they do not change with the output power of the power amplifier combining device.
  • FIG. 10 is a schematic diagram of output power and impedance of a power amplifier combining device disclosed in an embodiment of the present invention. As shown in FIG.
  • the impedance of the combining point of the two power amplifier units and the combining point of the class AB power amplifier in the power amplifier combining device corresponding to the present invention does not change with the change of the output power of the power amplifier combining device.
  • the output power of the corresponding power amplifier combining device in the present invention is less than 33 dBm, only the power amplifier unit T 1 works, and the load draw is 3 dB smaller than the two power amplifier units of the class AB power amplifier, until the power amplifier unit T 2 starts to work after it is greater than 33 dBm
  • the load draw ratio has only begun to become higher, close to the load draw of the class AB power amplifier, while the load draw ratio of the two power amplifier units of the class AB power amplifier has been constant and relatively large. Please refer to FIG.
  • FIG. 11 is a schematic diagram of a load pulling path of a power amplifier unit in a Smith chart disclosed in an embodiment of the present invention.
  • the power amplifier unit according to the present invention the amplifier comprises a combination device 1 is different from the power amplifier unit T T traction load path 1, and is varied, whereas the same load pull class AB power amplifier unit in the two paths and Will not change.
  • FIG. 12 is a schematic structural diagram of a power amplifier circuit disclosed in an embodiment of the present invention.
  • the power amplifier circuit may include two power amplifier branches, namely the first power amplifier branch and the second power amplifier branch.
  • the output ends of these two power amplifier branches are coupled to the load, that is, the two power amplifier branches.
  • the circuits are coupled to the load respectively.
  • At least one of the two power amplifier branches is the power amplifier combining device shown in FIG. 3.
  • the power amplifier circuit can be a Doherty power amplifier, a Chireix power amplifier, an Outphasing power amplifier, or other power amplifiers with equivalent functions.
  • FIG. 13 is a schematic structural diagram of a traditional Doherty power amplifier disclosed in an embodiment of the present invention.
  • the traditional Doherty power amplifier includes two power amplifier branches, a main circuit and a peak circuit.
  • the main circuit includes two power amplifier units, namely, the power amplifier unit m 1 and the power amplifier unit m 2.
  • the bias voltages of the two power amplifier units are the same, and the RF excitation signals of the two power amplifier units are also the same.
  • the auxiliary circuit includes two power amplifier units, namely, the power amplifier unit p 1 and the power amplifier unit p 2.
  • the RF excitation signals of the two power amplifier units are the same, and the bias voltages of the two power amplifier units are also the same.
  • FIG. 14 is a schematic structural diagram of a new type of Doherty power amplifier disclosed in an embodiment of the present invention. As shown in Figure 14, the main circuit of the Doherty power amplifier is replaced by the power amplifier combining device shown in Figure 4. The two power amplifier units of the replaced main circuit have different RF excitation signals, and the two power amplifier units of the replaced main circuit The bias voltage is also different.
  • FIG. 15 is a schematic diagram of output power, gain, and drain efficiency of a novel Doherty power amplifier and a traditional Doherty power amplifier disclosed in an embodiment of the present invention. Please refer to FIG.
  • FIG. 16 is a schematic diagram of output power, gain, and power added efficiency (PAE) of a new type of Doherty power amplifier and a traditional Doherty power amplifier disclosed in an embodiment of the present invention.
  • the new Doherty power amplifier can achieve a higher fallback efficiency compared with the traditional Doherty power amplifier. Before normalization, its efficiency can be increased by 10% when the fallback is 8dB, and the PAE is also 7% better. Improved, normalized according to the back-off rate, higher drain efficiency and PAE can be obtained. Please refer to FIG.
  • FIG. 17 is a schematic diagram of the output power of a new type of Doherty power amplifier and the traditional Doherty power amplifier and the output power and drain efficiency of the power amplifier unit disclosed in an embodiment of the present invention.
  • the main circuit of the new Doherty power amplifier has only one power amplifier unit m 1 working.
  • the load traction of the power amplifier unit in the new Doherty power amplifier is more than AB
  • the load draw ratio of the analog power amplifier unit is 3dB lower.
  • the drain efficiency of the power amplifier unit in the new Doherty power amplifier is about 10-15% higher than that in the traditional Doherty power amplifier, but it is caused by the access of the main power amplifier unit m 2
  • the combined efficiency of the new Doherty power amplifier is only about 7-10% higher than that of the traditional Doherty power amplifier.
  • the output power of the main power amplifier unit m 1 of the new Doherty power amplifier is the sum of the output power of the main two power amplifier units of the traditional Doherty power amplifier.
  • the load pull of the main power amplifier unit m 1 of the new Doherty power amplifier is smaller than that of the two main power amplifier units of the traditional Doherty power amplifier, so the drain efficiency is higher. Please refer to FIG. 18.
  • FIG. 18 Please refer to FIG. 18.
  • FIG. 18 is a schematic diagram of the output power, the junction point and the impedance of the power amplifier unit of a novel Doherty power amplifier and a traditional Doherty power amplifier disclosed in an embodiment of the present invention. As shown in Figure 18, the load at the junction point of the new Doherty power amplifier is the same as that of the traditional Doherty power amplifier.
  • the load traction ratio is compared with the main The two power amplifier units of the road are 3dB smaller, until it is greater than 33dBm, the load pull ratio of the main power amplifier unit m 2 of the new Doherty power amplifier starts to work, and it is close to the traditional Doherty power amplifier when the output power is 34dBm.
  • the load pull ratio of the two power amplifier units of the main circuit of the traditional Doherty power amplifier is always constant when it is less than 34dBm. Please refer to FIG. 19.
  • FIG. 19 FIG.
  • FIG. 19 is a schematic diagram of a load pulling path of a power amplifier unit of a new Doherty power amplifier and a traditional Doherty power amplifier in a Smith chart disclosed in an embodiment of the present invention.
  • the load pulling paths of the two power amplifier units of the main circuit of the traditional Doherty power amplifier are the same, and the load pulling paths of the two power amplifier units of the auxiliary circuit of the traditional Doherty power amplifier are the same.
  • the main power amplifier unit m 1 and the power amplifier unit m 2 of the new Doherty power amplifier have different load pulling paths, and the load pulling paths of the two power amplifier units of the auxiliary circuit of the new Doherty power amplifier are the same. Please refer to FIG. 20.
  • FIG. 20 Please refer to FIG. 20.
  • FIG. 20 is a schematic diagram of the amplitude difference and the phase difference of the radio frequency excitation signal of the power amplifier unit of a new Doherty power amplifier and a traditional Doherty power amplifier disclosed in an embodiment of the present invention.
  • the phase difference of the RF excitation signal of the power amplifier unit of the new Doherty power amplifier does not change with the change of output power.
  • the signal amplitude difference of the power amplifier unit of the new Doherty power amplifier is similar to the class B or C gain.
  • the amplitude difference and phase difference of the RF excitation signal of the power amplifier unit of the Doherty power amplifier do not change with the change of the output power.

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Abstract

本发明实施例公开一种功放合路装置及功放电路，该功放合路装置包括信号处理单元和n个功放单元，n为大于1的整数，其中：信号处理单元分别耦合n个功放单元的输入端，n个功放单元的输出端分别耦合负载；信号处理单元，用于在功放合路装置的输出功率小于第一阈值的情况下，控制第一功放单元工作，在输出功率大于或等于第i阈值且小于第i+1阈值的情况下，控制第一功放单元至第i+1功放单元工作，在输出功率大于或等于第n-1阈值的情况下，控制n个功放单元工作，i＝1,…,n-2，第一阈值、…、第n-1阈值依次增加。本发明实施例，可以降低功放单元的功耗。

Description

一种功放合路装置及功放电路
本申请要求于2019年11月28日提交中国专利局、申请号为201911195514.6、申请名称为“一种功放合路装置及功放电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明实施例涉及电子电路技术领域，尤其涉及一种功放合路装置及功放电路。
背景技术
为了提高输出功率，可以将多个功放单元并联连接，即将多个功放单元的输入连接在一起、将多个功放单元的输出连接在一起以及将多个功放单元的偏置电压设置为同一值。多个功放单元并联后的输出功率为多个功放单元中每个功放单元的输出功率之和，从而可以提高输出功率。然而，在所需输出功率较小的情况下，每个功放单元的输出功率小于单个功放单元的最大输出功率，降低了功放单元的转换效率，以致功放单元的功耗较大。
发明内容
本发明实施例公开了一种功放合路装置及功放电路，用于降低功放单元的功耗。
第一方面公开一种功放合路装置，包括信号处理单元和n个功放单元，信号处理单元分别耦合n个功放单元的输入端，n个功放单元的输出端分别耦合负载，信号处理单元，用于在功放合路装置的输出功率小于第一阈值的情况下，控制第一功放单元工作，在输出功率大于或等于第i阈值且小于第i+1阈值的情况下，控制第一功放单元至第i+1功放单元工作，在输出功率大于或等于第n-1阈值的情况下，控制n个功放单元工作。n为大于1的整数。i＝1,…,n-2，第一阈值、…、第n-1阈值依次增加。由于在所需输出功率较小时，较少数量的功放单元就可以提供所需输出功率，在所需输出功率较大时，增加工作的功放单元的数量，以便可以提供多出来的所需输出功率。因此，随着所需输出功率的增大，增加功放单元工作的数量，可以提高功放单元的转换效率，从而可以降低功放单元的功耗。
作为一种可能的实施方式，n个功放单元的输出端分别通过匹配网络耦合负载，以便可以保证阻抗匹配。
作为一种可能的实施方式，信号处理单元还用于为n个功放单元提供射频激励信号。可以在很小的功率等级内控制射频激励信号的幅度和相位，因此，信号处理单元的带宽较宽，且功耗较低。
作为一种可能的实施方式，信号处理单元还用于为n个功放单元提供偏置电压，可以提高信号处理单元的控制力。
作为一种可能的实施方式，第一功放单元、…、第n功放单元的偏置电压依次降低。这种偏置电压的配置，配合信号处理单元输出相应的射频激励信号，可以实现随着功放合路装置的输出功率的增加n个功放单元逐渐工作，从而可以降低功放单元的功耗。
作为一种可能的实施方式，第一功放单元、…、第n功放单元的偏置电压保持不变。由 于不需要根据功放合路装置的输入信号的包络变化而调整功放单元的偏置状态，因此，即使功放单元中的功率管的尺寸较大以及寄生参数较大也不会导致信号处理单元增加额外的功耗，从而对功率管的尺寸和类型无严格要求。
作为一种可能的实施方式，第一阈值为第一功放单元的最大输出功率，第j阈值为第j-1阈值与第j功放单元的最大输出功率的和，j＝2,…,n-1。
第二方面公开一种功放电路，该功放电路可以包括两个功放支路，这两个功放支路中的至少一个功放支路为第一方面或第一方面任一实施方式公开的功放合路装置。
作为一种可能的实施方式，该功放电路可以为多尔蒂(Doherty)功放，也可以为希雷(Chireix)功放，还可以为异相(Outphasing)功放，还可以为其它具有同等功能的功放电路。
附图说明
图1是本发明实施例公开的一种功放合路装置的结构示意图；
图2是本发明实施例公开的一种不同数量功放单元工作对应的功放合路装置的输出功率的示意图；
图3是本发明实施例公开的另一种功放合路装置的结构示意图；
图4是本发明实施例公开的一种信号处理单元为n个功放单元提供的射频激励信号与偏置电压的示意图；
图5是本发明实施例公开的又一种功放合路装置的结构示意图；
图6是本发明实施例公开的另一种不同数量功放单元工作对应的功放合路装置的输出功率的示意图；
图7是本发明实施例公开的一种功放合路装置的输出功率与功放单元的阻抗的示意图；
图8是本发明实施例公开的一种功放合路装置的输出功率与功放单元的输出功率和漏极效率的示意图；
图9是本发明实施例公开的一种功放合路装置的输出功率与功放单元的射频激励信号的幅度差和相位差的示意图；
图10是本发明实施例公开的一种功放合路装置的输出功率与阻抗的示意图；
图11是本发明实施例公开的一种史密斯圆图中功放单元的负载牵引路径的示意图；
图12是本发明实施例公开的一种功放电路的结构示意图；
图13是本发明实施例公开的一种传统的Doherty功放的结构示意图；
图14是本发明实施例公开的一种新型的Doherty功放的结构示意图；
图15是本发明实施例公开的一种新型的Doherty功放和传统的Doherty功放的输出功率与增益和漏极效率的示意图；
图16是本发明实施例公开的一种新型的Doherty功放和传统的Doherty功放的输出功率与增益和PAE的示意图；
图17是本发明实施例公开的一种新型的Doherty功放和传统的Doherty功放的输出功率与功放单元的输出功率和漏极效率的示意图；
图18是本发明实施例公开的一种新型的Doherty功放和传统的Doherty功放的输出功率 与合路点和功放单元的阻抗的示意图；
图19是本发明实施例公开的一种史密斯圆图中新型的Doherty功放和传统的Doherty功放的功放单元的负载牵引路径的示意图；
图20是本发明实施例公开的一种新型的Doherty功放和传统的Doherty功放的功放单元的射频激励信号的幅度差和相位差的示意图。
具体实施方式
本发明实施例公开了一种功放合路装置及功放电路，用于降低功放单元的功耗。以下分别进行详细说明。
为了更好地理解本发明实施例公开的一种功放合路装置及功放电路，下面先对本发明实施例的应用场景进行描述。请参阅图1，图1是本发明实施例公开的一种功放合路装置的结构示意图。如图1所示，为了实现输出功率更大的功放，可以将n个功放单元，即功放单元T 1、功放单元T 2、…、功放单元T n，的输入连接在一起，可以将这n个功放单元的输出连接在一起，以及将这n个功放单元的偏置电压设置为同一值，即偏置电压V g1＝V g2＝…＝V gn，即将n个功放单元并联连接。假设负载的阻抗为R opt，功放合路装置的最大输出功率为P opt。n为大于1的整数。功放单元T 1、功放单元T 2、…、功放单元T n中每个功放单元在它们的输出端连接处，即合路点，的阻抗为nR opt。在所需输出功率为P opt/2的情况下，可以是n个功放单元工作，每个功放单元的输出功率为P opt/2n；也可以是n/2个功放单元工作，每个功放单元的输出功率为P opt/n。请参阅图2，图2是本发明实施例公开的一种不同数量功放单元工作对应的功放合路装置的输出功率的示意图。如图2所示，在功放合路装置中不同数量的功放单元工作虽然均可以达到相同的输出功率，但是工作的功放单元越少，每个功放单元的输出功率越大，峰值效率越高，即转换效率越高，功耗越低。因此，在功放合路装置包括的功放单元数量一定的情况下，如何提高功放单元的转换效率，以便降低功放单元的功耗已成为一个亟待解决的技术问题。
请参阅图3，图3是本发明实施例公开的另一种功放合路装置的结构示意图。如图3所示，该功放合路装置可以包括信号处理单元和n个功放单元，n为大于1的整数，其中：
信号处理单元分别耦合n个功放单元的输入端，n个功放单元的输出端分别耦合负载；
信号处理单元，用于在功放合路装置的输出功率小于第一阈值的情况下，控制第一功放单元T 1工作，在功放合路装置的输出功率大于或等于第i阈值且小于第i+1阈值的情况下，控制第一功放单元T 1至第i+1功放单元T i+1工作，在功放合路装置的输出功率大于或等于第n-1阈值的情况下，控制n个功放单元T 1、T 2、…、T n工作，i＝1,…,n-2，第一阈值、…、第n-1阈值依次增加。
如图3所示，n个功放单元T 1、T 2、…、T n并没有并联连接，信号处理单元可以控制n个功放单元的工作或不工作。在该功放合路装置的输出功率小于第一阈值的情况下，第一功放单元T 1工作就能够提供该功放合路装置所需输出功率，因此，可以控制第一功放单元T 1工作，以及控制其余功放单元不工作。在该功放合路装置的输出功率大于或等于第i阈值且 小于第i+1阈值的情况下，第一功放单元T 1至第i+1功放单元T i+1工作能够提供该功放合路装置所需输出功率，因此，可以控制第一功放单元T 1至第i+1功放单元T i+1工作，以及控制其余功放单元不工作。在该功放合路装置的输出功率大于或等于第n-1阈值的情况下，需要n个功放单元全部工作才能提供该功放合路装置所需输出功率，因此，可以控制n个功放单元工作。例如，n＝4时，在该功放合路装置的输出功率小于第一阈值的情况下，可以控制第一功放单元T 1工作，以及控制第二功放单元T 2、第三功放单元T 3和第四功放单元T 4不工作。在该功放合路装置的输出功率大于或等于第一阈值且小于第二阈值的情况下，可以控制第一功放单元T 1和第二功放单元T 2工作，以及控制第三功放单元T 3和第四功放单元T 4不工作。在该功放合路装置的输出功率大于或等于第二阈值且小于第三阈值的情况下，可以控制第一功放单元T 1、第二功放单元T 2和第三功放单元T 3工作，以及控制第四功放单元T 4不工作。在该功放合路装置的输出功率大于或等于第三阈值的情况下，可以控制第一功放单元T 1、第二功放单元T 2、第三功放单元T 3和第四功放单元T 4工作。功放单元可以是一个功率放大器件，如金属氧化物半导体(metal oxide semiconductor，MOS)管，也可以是由多个器件组成的具有功率放大功能的单元。功放合路装置的输出功率即功放合路装置的射频输出功率。
在一个实施例中，n个功放单元的输出端分别通过匹配网络耦合负载，即匹配网络分别耦合n个功放单元的输出端和负载。n个功放单元的输出端是先连接在一起之后再与匹配网络进行连接的，即n个功放单元的输出端是连接在一起的，以便该功放合路装置的输出功率等于这n个功放单元的输出功率之和。匹配网络可以保证阻抗匹配。
在一个实施例中，信号处理单元还用于为n个功放单元提供射频激励信号。
信号处理单元可以为n个功放单元提供射频激励信号，这n个功放单元的射频激励信号可以均相同，也可以均不同，还可以部分相同部分不同，在此不加限定。在n个功放单元的射频激励信号包括m个不同的射频激励信号的情况下，信号处理单元可以包括m个控制通路，这m个控制通路可以是相互独立的，即这m个控制通路相互之间无连接，每个控制通路分别生成一个射频激励信号，一个射频激励信号可以作为一个功放单元的射频激励信号，也可以作为多个功放单元的射频激励信号，在此不加限定。信号处理单元也可以包括一路控制通路，但这路控制通路可以包括m个支路，每个支路生成一个射频激励信号。m为大于1且小于或等于n的整数。
在一个实施例中，信号处理单元，还用于为n个功放单元提供偏置电压。
信号处理单元还可以为n个功放单元提供偏置电压，这n个功放单元的偏置电压可以均相同，也可以均不同，还可以部分相同部分不同，在此不加限定。在n个功放单元的偏置电压包括m个不同的偏置电压的情况下，信号处理单元可以包括m个控制通路，这m个控制通路可以是相互独立的，即这m个控制通路相互之间无连接，每个控制通路分别生成一个偏置电压，一个偏置电压可以作为一个功放单元的偏置电压，也可以作为多个功放单元的偏置电压，在此不加限定。信号处理单元也可以包括一路控制通路，但这路控制通路可以包括m个支路，每个支路生成一个偏置电压。
在一个实施例中，第一功放单元、…、第n功放单元的偏置电压依次降低。
在一个实施例中，第一功放单元、…、第n功放单元的偏置电压保持不变。
在n个功放单元的射频激励信号均相同的情况下，为了保证n个功放单元分别在不同的阈值范围内工作，n个功放单元的偏置电压均不同。请参阅图4，图4是本发明实施例公开的一种信号处理单元为n个功放单元提供的射频激励信号与偏置电压的示意图。如图4所示，第一功放单元T 1的偏置电压V g1、第二功放单元T 2的偏置电压V g2、…、第n功放单元T n的偏置电压V gn依次降低，n个功放单元的射频激励信号相同，射频激励信号的幅度处于不同阈值范围内时，工作的功放单元的数量不同。此外，功放单元的偏置电压可以不随射频激励信号的变化而变化。
在一个实施例中，第一阈值为第一功放单元的最大输出功率，第j阈值为第j-1阈值与第j功放单元的最大输出功率的和，j＝2,…,n-1。
每个功放单元的最大输出功率，即最大射频输出功率，是固定不变的，不会随着使用场景的不同发生变化。n个功放单元的最大输出功率可以均相同，也可以均不同，还可以部分相同部分不同，在此不加限定。第一阈值可以为第一功放单元的最大输出功率，第二阈值可以为第一阈值与第二功放单元的最大输出功率的和，…，第n-1阈值为第n-2阈值与第n-1功放单元的最大输出功率的和。n个功放单元的最大输出功率包括m个不同的最大输出功率的情况下，第一功放单元可以是n个功放单元的最大输出功率中最大输出功率最大的功放单元，也可以是n个功放单元的最大输出功率中最大输出功率最小的功放单元，还可以是其它功放单元，在此不加限定。
由于功放合路装置的输出功率与功放合路装置的输入功率的比值为功放合路装置的增益。因此，信号处理单元在功放合路装置的输出功率小于第一阈值的情况下，控制第一功放单元工作，在输出功率大于或等于第i阈值且小于第i+1阈值的情况下，控制第一功放单元至第i+1功放单元工作，在输出功率大于或等于第n-1阈值的情况下，控制n个功放单元工作，即在功放合路装置的输入功率小于第一阈值与A的比值的情况下，控制第一功放单元工作，在功放合路装置的输入功率大于或等于第i阈值与A的比值且小于第i+1阈值与A的比值的情况下，控制第一功放单元至第i+1功放单元工作，在功放合路装置的输入功率大于或等于第n-1阈值与A的比值的情况下，控制n个功放单元工作。A为功放合路装置的增益。
请参阅图5，图5是本发明实施例公开的又一种功放合路装置的结构示意图。如图5所示，该功放合路装置可以包括两个功放单元，这两个功放单元的偏置电压不同。请参阅图6，图6是本发明实施例公开的另一种不同数量功放单元工作对应的功放合路装置的输出功率的示意图。如图6所示，当功放合路装置的输入信号的幅度较小时，功放单元T 1处于工作状态，功放单元T 2的射频激励信号较小，功放单元T 2处于非工作状态，即关闭状态，或处于输出功率很小的状态。随着功放合路装置的输入信号的幅度增大，功放单元T 2的射频激励信号逐渐增大，直至功放单元T 2的输出功率不再增加，在功放单元T 1与功放单元T 2完全相同的情况下，即直至功放单元T 2的输出功率与功放单元T 1的输出功率相同。可见，图5对应的功放合路装置，即本发明，与AB类功放相比，在保持最大输出功率的同时，回退效率可以平均提升5％以上。请参阅图7，图7是本发明实施例公开的一种功放合路装置的输出功率与功放单元的阻抗的示意图。如图7所示，当功放合路装置的输入信号的幅度较小时，功放单元T 1工作，功放单元T 2不工作，功放单元T 1的阻抗较小，功放单元T 2的阻抗很大，随着功放 合路装置的输入信号的幅度增大，功放单元T 1和功放单元T 2均工作，功放单元T 1的阻抗变大，功放单元T 2的阻抗变小。请参阅图8，图8是本发明实施例公开的一种功放合路装置的输出功率与功放单元的输出功率和漏极效率的示意图。如图8所示，在功放合路装置的输出功率小于33dBm时，本发明只有功放单元T 1有输出功率，此时本发明对应的功放合路装置的负载牵引比相对于AB类功放的负载牵引比小3dB，本发明对应的功放合路装置中功放单元的漏极效率比AB类功放的漏极效率高。请参阅图9，图9是本发明实施例公开的一种功放合路装置的输出功率与功放单元的射频激励信号的幅度差和相位差的示意图。如图9所示，本发明对应的功放合路装置中的两个功放单元的相位差是固定不变的，即不随功放合路装置的输出功率的变化而变化，本发明对应的功放合路装置中的两个功放单元的射频激励信号的幅度差随着功放合路装置的输出功率的增大而增大。AB类功放中，两个功放单元的幅度差和相位差是固定不变的，即不随功放合路装置的输出功率的变化而变化。请参阅图10，图10是本发明实施例公开的一种功放合路装置的输出功率与阻抗的示意图。如图10所示，本发明对应的功放合路装置中两个功放单元的合路点与AB类功放的合路点的阻抗均不随功放合路装置的输出功率的变化而变化。本发明中对应的功放合路装置的输出功率小于33dBm时，只有功放单元T 1工作，负载牵引比相比AB类功放的两个功放单元小3dB，直到大于33dBm后功放单元T 2开始工作时负载牵引比才开始变高，接近于AB类功放的负载牵引，而AB类功放的两个功放单元的负载牵引比则一直恒定，且相对较大。请参阅图11，图11是本发明实施例公开的一种史密斯圆图中功放单元的负载牵引路径的示意图。如图11所示，本发明中功放合路装置包括的功放单元T 1与功放单元T 1的负载牵引路径不同，且是变化的，而AB类功放中两个功放单元的负载牵引路径相同且不会变化。
请参阅图12，图12是本发明实施例公开的一种功放电路的结构示意图。如图12所示，该功放电路可以包括两个功放支路，即第一功放支路和第二功放支路，这两个功放支路的输出端连接之后耦合负载，即这两个功放支路分别耦合负载。这两个功放支路中的至少一个功放支路为图3所示的功放合路装置。该功放电路可以为Doherty功放，也可以为Chireix功放，还可以为Outphasing功放，还可以为其它具有同等功能的功放。
请参阅图13，图13是本发明实施例公开的一种传统的Doherty功放的结构示意图。如图13所示，传统的Doherty功放包括主(main)路和辅(peak)路两个功放支路。主路包括两个功放单元，即功放单元m 1和功放单元m 2，这两个功放单元的偏置电压相同，这两个功放单元的射频激励信号也相同。辅路包括两个功放单元，即功放单元p 1和功放单元p 2，这两个功放单元的射频激励信号相同，这两个功放单元的偏置电压也相同。主路通过λ/4连接线分别与辅路和负载耦合。请参阅图14，图14是本发明实施例公开的一种新型的Doherty功放的结构示意图。如图14所示，该Doherty功放的主路由图4所示的功放合路装置替换得到，替换后的主路的两个功放单元的射频激励信号不同，替换后的主路的两个功放单元的偏置电压也不同。请参阅图15，图15是本发明实施例公开的一种新型的Doherty功放和传统的Doherty功放的输出功率与增益和漏极效率的示意图。请参阅图16，图16是本发明实施例公开的一种新型的Doherty功放和传统的Doherty功放的输出功率与增益和功率附加效率(power added efficiency，PAE)的示意图。如图15和图16所示，新型的Doherty功放与传统 的Doherty功放相比可以获得更高的回退效率，归一化之前其在回退8dB时效率可以提升10％，PAE也有7％的提升，按照回退率归一化后可以获得更高的漏极效率和PAE。请参阅图17，图17是本发明实施例公开的一种新型的Doherty功放和传统的Doherty功放的输出功率与功放单元的输出功率和漏极效率的示意图。如图17所示，在Doherty功放的输出功率小于33dBm时，新型的Doherty功放的主路只有一个功放单元m 1工作，此时新型的Doherty功放中功放单元的负载牵引比传统的Doherty功放中AB类功放单元的负载牵引比小3dB，新型的Doherty功放中功放单元的漏极效率比传统的Doherty功放中漏极效率约高10～15％，但是由于主路的功放单元m 2的接入造成的损耗，新型的Doherty功放的合路效率只比传统的Doherty功放的合路效率约高7～10％。新型的Doherty功放的主路的功放单元m 1的输出功率为传统的Doherty功放的主路两个功放单元的输出功率之和。新型的Doherty功放的主路的功放单元m 1的负载牵引比相比传统的Doherty功放的主路的两个功放单元更小，因此，漏极效率更高。请参阅图18，图18是本发明实施例公开的一种新型的Doherty功放和传统的Doherty功放的输出功率与合路点和功放单元的阻抗的示意图。如图18所示，新型的Doherty功放和传统的Doherty功放的合路点的负载相同，新型的Doherty功放的主路的功放单元m 1在小于33dBm时负载牵引比相比传统的Doherty功放的主路的两个功放单元小3dB，直到大于33dBm，新型的Doherty功放的主路的功放单元m 2开始工作时负载牵引比才开始变高，在输出功率为34dBm时接近于传统的Doherty功放，而传统的Doherty功放的主路的两个功放单元的负载牵引比在小于34dBm时一直恒定不变。请参阅图19，图19是本发明实施例公开的一种史密斯圆图中新型的Doherty功放和传统的Doherty功放的功放单元的负载牵引路径的示意图。如图19所示，传统的Doherty功放的主路的两个功放单元的负载牵引路径相同，传统的Doherty功放的辅路的两个功放单元的负载牵引路径相同。新型的Doherty功放的主路的功放单元m 1和功放单元m 2的负载牵引路径不同，新型的Doherty功放的辅路的两个功放单元的负载牵引路径相同。请参阅图20，图20是本发明实施例公开的一种新型的Doherty功放和传统的Doherty功放的功放单元的射频激励信号的幅度差和相位差的示意图。如图20所示，新型的Doherty功放的功放单元的射频激励信号的相位差不随输出功率的变化而变化，新型的Doherty功放的功放单元的信号幅度差类似于B类或者C类的增益，传统的Doherty功放的功放单元的射频激励信号的幅度差和相位差均不随输出功率的变化而变化。
以上所述的具体实施方式，对本申请的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本申请的具体实施方式而已，并不用于限定本申请的保护范围，凡在本申请的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本申请的保护范围之内。

Claims (8)

  1. 一种功放合路装置，其特征在于，包括信号处理单元和n个功放单元，所述n为大于1的整数，其中：
    所述信号处理单元分别耦合所述n个功放单元的输入端，所述n个功放单元的输出端分别耦合负载；
    所述信号处理单元，用于在所述功放合路装置的输出功率小于第一阈值的情况下，控制第一功放单元工作，在所述输出功率大于或等于第i阈值且小于第i+1阈值的情况下，控制所述第一功放单元至第i+1功放单元工作，在所述输出功率大于或等于第n-1阈值的情况下，控制所述n个功放单元工作，所述i＝1,…,n-2，所述第一阈值、…、所述第n-1阈值依次增加。
  2. 根据权利要求1所述的装置，其特征在于，所述n个功放单元的输出端分别耦合负载包括：
    所述n个功放单元的输出端分别通过匹配网络耦合负载。
  3. 根据权利要求1或2所述的装置，其特征在于，所述信号处理单元，还用于为所述n个功放单元提供射频激励信号。
  4. 根据权利要求1-3任一项所述的装置，其特征在于，所述信号处理单元，还用于为所述n个功放单元提供偏置电压。
  5. 根据权利要求4所述的装置，其特征在于，所述第一功放单元、…、第n功放单元的偏置电压依次降低。
  6. 根据权利要求5所述的装置，其特征在于，所述第一功放单元、…、所述第n功放单元的偏置电压保持不变。
  7. 根据权利要求1-6任一项所述的装置，其特征在于，所述第一阈值为所述第一功放单元的最大输出功率，所述第j阈值为第j-1阈值与第j功放单元的最大输出功率的和，所述j＝2,…,n-1。
  8. 一种功放电路，其特征在于，所述功放电路包括两个功放支路，所述两个功放支路中的至少一个功放支路为如权利要求1-7任一项所述的功放合路装置。
PCT/CN2020/131513 2019-11-28 2020-11-25 一种功放合路装置及功放电路 WO2021104311A1 (zh)

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