WO2021100417A1 - Electric circuit - Google Patents
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- WO2021100417A1 WO2021100417A1 PCT/JP2020/040218 JP2020040218W WO2021100417A1 WO 2021100417 A1 WO2021100417 A1 WO 2021100417A1 JP 2020040218 W JP2020040218 W JP 2020040218W WO 2021100417 A1 WO2021100417 A1 WO 2021100417A1
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- 239000002887 superconductor Substances 0.000 claims description 5
- 238000004364 calculation method Methods 0.000 abstract description 35
- 101000655352 Homo sapiens Telomerase reverse transcriptase Proteins 0.000 abstract description 22
- 102100032938 Telomerase reverse transcriptase Human genes 0.000 abstract description 22
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- 238000010586 diagram Methods 0.000 description 15
- 239000002245 particle Substances 0.000 description 14
- 241000121629 Majorana Species 0.000 description 10
- 235000021028 berry Nutrition 0.000 description 7
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- 238000005481 NMR spectroscopy Methods 0.000 description 1
- 238000009954 braiding Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
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- 229910052734 helium Inorganic materials 0.000 description 1
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- 238000005040 ion trap Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
Definitions
- the present invention relates to an electric circuit.
- Quantum computing is attracting attention as a technology that breaks through the limits of Moore's Law regarding semiconductor integration.
- the calculation is performed using the bits of 0 and 1
- the quantum calculation is performed using the qubit by superposition of 0 and 1.
- qubits By using qubits, it is expected that the calculation speed will be exponentially improved.
- various quantum calculation methods are in the research stage.
- quantum dots, superconducting qubits, photon computers, nuclear magnetic resonance, ion traps, cavities QED (Quantum Electrodynamics), topological superconductors (Non-Patent Document 1), etc. have been studied. However, none of them have reached the practical stage.
- Non-Patent Document 1 As one method for solving this problem, topological quantum calculation is known in which quantum calculation is performed by braiding the Majorana particles in a topological superconductor (Non-Patent Document 1).
- a method for controlling Majorana particles has not been established, and superconductivity cannot be realized at room temperature. Therefore, a large amount of helium is required for cooling, and it is difficult to make an inexpensive and compact device. Furthermore, there is no prospect of finely integrating superconducting quantum circuits.
- the present invention provides an electric circuit that operates at room temperature, can be finely integrated, and can perform calculations equivalent to topological quantum calculations.
- the electric circuit includes a plurality of unit circuits including at least four endpoints and a topological phase operation circuit having adjustable impedance, and the alternating current at one of the four endpoints and the said.
- the circuit Laplacian which represents the proportional relationship with the AC voltage of the end point adjacent to the end point, is configured to correspond to the Hamiltonian of the quantum system, and the impedance of the topological phase operation circuit corresponds to the parameters contained in the Hamiltonian. It has a topological phase in a given area of parameters.
- the circuit Laplacian is configured to correspond to the Hamiltonian of a quantum system having a topological phase in a predetermined parameter region, thereby creating an edge state between the topological phase and the topologically obvious phase.
- a corresponding voltage state can be created, and a calculation equivalent to a topological quantum calculation can be performed by manipulating the voltage state with a blade.
- it since it is a normal electric circuit, it operates at room temperature and can be finely integrated.
- the plurality of unit circuits include a first circuit corresponding to an electronic band and a second circuit corresponding to a hall band, respectively, and the phase of the AC voltage of the first circuit and the phase of the AC voltage of the second circuit are set. They may be opposite to each other.
- a voltage state corresponding to electrons and holes can be created, and a voltage state corresponding to Majorana particles can be created between the topological phase and the topologically trivial phase.
- the plurality of unit circuits may include a phase operation circuit that connects the first circuit and the second circuit and changes the phase of the AC voltage.
- a parameter corresponding to the superconducting phase can be realized.
- the topological phase operation circuit may include a switch that connects the first circuit or the second circuit to the ground and switches the impedance.
- the lengths of the topological phase and the topologically trivial phase can be arbitrarily adjusted, and various blade operations related to the edge state can be realized.
- the plurality of unit circuits may be connected in a T shape including a branch connection.
- the plurality of unit circuits may include a branch connection and may be connected in a cross shape.
- the Hamiltonian may be a superconductor Hamiltonian described in the Bogoliubov-de Gennes format having electron-hole symmetry, or a Hamiltonian having chiral symmetry.
- the AC voltage at the end point of the unit circuit located at the end may correspond to the edge state of the Hamiltonian.
- a voltage state corresponding to an edge state can be created between a topological phase and a topologically trivial phase, and a calculation equivalent to a topological quantum calculation can be performed by manipulating the voltage state in a blade. Can be done.
- an electric circuit that operates at room temperature, can be finely integrated, and can perform calculations equivalent to topological quantum calculations.
- the blade operation of non-commutative anyon is used as the quantum gate.
- a particle whose phase change of the wave function becomes 0 or ⁇ due to particle exchange and whose phase change becomes 0 is called a boson
- a particle whose phase change becomes ⁇ is called a fermion. ..
- particles called anyon can be realized in which the phase change of the wave function becomes an arbitrary value by exchanging the particles.
- non-commutative anyon is realized as an edge state of a one-dimensional superconducting wire.
- Kitaev model of the following mathematical formula (1) is known.
- ⁇ k ⁇ t cosk ⁇
- t the hopping amplitude
- ⁇ the chemical potential
- ⁇ the superconducting phase
- ⁇ the gap parameter.
- the Hamiltonian of the equation (1) is a topologically trivial phase when ⁇ is not zero and
- the topological invariants that characterize the topological phase are typically defined by the number of wraps of the map from the momentum space to the Hilbert space, taking only discrete values such as 1, 2, ..., and topologically trivial phase phases.
- the invariant is 0. Inside the topological phase, the phase invariant does not change because the gap ⁇ is finite.
- the gap is closed at the boundary between the topological phase and the topologically trivial phase, a gapless state occurs, and the topological invariant changes. This gapless state is called an edge state.
- Kitaev model of mathematical formula (1) Majorana particles that do not distinguish between electrons and holes (particles and antiparticles) appear as edge states.
- the electric circuit 10 according to the present embodiment has a circuit Laplacian equivalent to the mathematical formula (1), and creates a voltage state corresponding to the edge state of the quantum system. Further, the electric circuit 10 according to the present embodiment can perform a calculation equivalent to the topological quantum calculation by performing a blade operation on the voltage state corresponding to the edge state.
- the Hamiltonian of the equation (1) is a Hamilton of a one-dimensional superconductor described in the Bogoliubov-de Gennes form, and has electron-hole symmetry.
- FIG. 1 is a diagram showing an electric circuit 10 according to an embodiment of the present invention.
- the electrical circuit 10 includes a plurality of unit circuits each including at least four endpoints and a topological phase operating circuit TCS with adjustable impedance.
- TCS topological phase operating circuit
- the circuit Laplacian which represents the proportional relationship between the alternating current of one of the four endpoints and the alternating voltage of the endpoint adjacent to the endpoint, is configured to correspond to the Hamiltonian of the quantum system.
- circuit Laplacian of the electric circuit 10 is represented by the following mathematical formula (2).
- C is the capacitance shown in FIG. 1, and L is the inductance shown in FIG.
- C 0 is the capacitance included in the topological phase operation circuits TCS1 and TCS2 described later
- ⁇ is a parameter corresponding to the superconducting phase.
- ⁇ x , ⁇ y , and ⁇ z are 2 ⁇ 2 Pauli matrices.
- the topological phase operation circuit TCS1, TCS2, inductance L 0 are also included.
- the impedances of the topological phase operation circuits TCS1 and TCS2 correspond to the parameters t and ⁇ included in the Hamiltonian of the equation (1).
- the topological phase and the topologically obvious phase can be obtained by configuring the circuit Laplacian so as to correspond to the Hamiltonian of the quantum system having the topological phase in a predetermined parameter region.
- a voltage state corresponding to the edge state can be created between them, and the same calculation as the topological quantum calculation can be performed by manipulating the voltage state with a blade.
- the electric circuit 10 according to the present embodiment is a normal electric circuit, it is relatively inexpensive, operates at room temperature, and can be finely integrated.
- it simulates topological quantum computation it is not affected by decoherence, and there is no need to increase the scale of the circuit for error correction.
- the plurality of unit circuits U1 and U2 include the first circuit E1 corresponding to the electronic band and the second circuit H1 corresponding to the hall band, respectively, and have the phase of the AC voltage of the first circuit E1 and the AC voltage of the second circuit H1.
- the phases are opposite to each other.
- the plurality of unit circuits U1 and U2 include a phase operation circuit PCS that connects the first circuit E1 and the second circuit H1 and changes the phase of the AC voltage.
- the phase manipulation circuit PCS can realize parameters corresponding to the superconducting phase included in the Hamiltonian of the quantum system.
- the plurality of unit circuits U1 and U2 include a branch connection and are connected in a T shape. As will be described later, by including the T-shaped branch, it is possible to realize an operation of exchanging the positions of the two edge states appearing at both ends of the topological phase.
- the T-shaped branch may be a Y-shaped branch or another branch.
- the AC voltage at the end point of the unit circuit located at the end of the circuits U1 and U2 corresponds to the edge state of the Hamiltonian.
- the end points of the unit circuits located at the ends of the plurality of unit circuits U1 and U2 are in contact with air or an ordinary insulator, and are in contact with a topologically obvious phase.
- a voltage state corresponding to an edge state can be created between a topological phase and a topologically trivial phase, and the voltage state can be manipulated by a blade to perform topological quantum calculation. Equivalent calculations can be performed.
- FIG. 2 is a diagram showing a phase control circuit PCS included in the electric circuit 10 according to the present embodiment.
- the phase control circuit PCS includes an operational amplifier OP, a capacitance C X ⁇ and an inductance L X ⁇ .
- FIG. 3 is a diagram showing a configuration of an operational amplifier OP included in the phase operation circuit PCS according to the present embodiment.
- the operational amplifier OP includes a resistor R ⁇ .
- the figure shows a case where the upper two wires are connected to the end points of the first circuit E1 and the lower two wires are connected to the end points of the second circuit H1.
- the figure shows a case where the upper two wires are connected to the end points of the first circuit E1 and the lower two wires are connected to the end points of the second circuit H1.
- FIG. 6 is a diagram showing a topological phase operation circuit TCS1 included in the electric circuit 10 according to the present embodiment and in the ON state.
- the topological phase operation circuit TCS1 includes a capacitance C 0 and an inductance L 0 .
- the figure shows a case where one upper wire is connected to the ground and one lower wire is connected to the end point of the first circuit E1.
- the topological phase operation circuit TCS1 includes a switch that connects the first circuit E1 or the second circuit H1 to the ground and switches the impedance.
- Topological phase operation circuit TCS1 is in the on state, the end point of the first circuit E1, is connected to the ground via the inductor L 0.
- FIG. 7 is a diagram showing a topological phase operation circuit TCS1 included in the electric circuit 10 according to the present embodiment and in an off state. The figure shows a case where one upper wire is connected to the ground and one lower wire is connected to the end point of the first circuit E1.
- Topological phase operation circuit TCS1 is off state, the end point of the first circuit E1, is connected to the ground via the capacitance C 0.
- the topological phase operation circuit TCS2 connected to the second circuit H2 has the same configuration as the topological phase operation circuit TCS1, but the on / off state is opposite to that of the topological phase operation circuit TCS1. That is, the topological phase operating circuit is in the ON state TCS2 is the end point of the second circuit H1, connected to ground through a capacitance C 0. Furthermore, topological phase operating circuit is off TCS2 is the end point of the second circuit H1, connected to the ground via the inductor L 0.
- the length of the topological phase and the topologically obvious phase can be arbitrarily adjusted.
- FIG. 14 is a diagram showing an example in which a storage circuit is provided in the electric circuit 10 according to the present embodiment.
- the information of the blade operation is obtained by the amplitude and phase of the vibration current or the vibration voltage in the LC resonator R. Can be remembered.
- FIG. 15 is a diagram showing an LC resonator R. As shown in the figure, in the LC resonator R, the capacitance C 0 and the inductance L 0 are connected in parallel, one end thereof is connected to the ground, and the other end is connected to the end point of the first circuit or the second circuit. ..
- FIG. 8 is a diagram schematically showing a blade operation in an edge state in the electric circuit 10 according to the present embodiment.
- the topological phase unit circuit is shown by a relatively thick solid line
- the topologically trivial unit circuit is shown by a relatively thin solid line among a plurality of linearly arranged unit circuits.
- the edge state (voltage state) that appears at the boundary between the topological phase and the topologically trivial phase is indicated by a hatched circle.
- the topological phase two edge states (Majorana similar state) appearing across M A j-1 and M B j-1 position and operation of exchanging the topological into two adjacent members across the trivial phase
- the operation of exchanging the positions of the edge state (Majorana-like state) M B j and M A j + 1 is shown. Details of both operations will be described with reference to FIGS. 9 and 10.
- a calculation equivalent to the quantum calculation is performed by performing a blade operation on the edge states arranged in a straight line.
- the electric circuit 10 generates 2N topologically protected edge states at the boundary by bringing N topological phases and N topologically trivial phases into contact with each other, and exchanges them. Performs the same calculation as the topological quantum calculation by the blade operation.
- FIG. 9 is a diagram schematically showing an operation of exchanging the positions of two edge states appearing at both ends of the topological phase in the electric circuit 10 according to the present embodiment.
- the topological phase unit circuit is shown by a relatively thick solid line
- the topologically obvious phase unit circuit is shown by a relatively thin solid line among a plurality of linearly arranged unit circuits, and appears at both ends of the topological phase.
- the edge state (voltage state) is indicated by a hatched circle.
- Represents the superconducting phase ⁇ ⁇ .
- edge state initially located at the left end is located at the right end, and the edge state initially located at the right end is located at the left end. In this way, the exchange operation of the two edge states can be performed.
- FIG. 10 is a diagram schematically showing an operation of exchanging the positions of two adjacent edge states with a topologically obvious phase in between in the electric circuit 10 according to the present embodiment.
- the topological phase unit circuit is shown by a relatively thick solid line
- the topologically obvious phase unit circuit is shown by a relatively thin solid line among a plurality of linearly arranged unit circuits, and appears at both ends of the topological phase.
- the edge state (voltage state) is indicated by a hatched circle.
- Represents the superconducting phase ⁇ ⁇ .
- edge state that initially appeared at the right end of the topological phase located on the left side is located at the left end of the topological phase located on the right side, and the edge state that initially appeared at the left end of the topological phase located on the right side is It will be located at the right end of the topological phase located on the left side. In this way, it is possible to perform an exchange operation of two edge states adjacent to each other with a topologically obvious phase in between.
- FIG. 11 is a diagram showing a time change of a wave function in an operation of exchanging the positions of two edge states appearing at both ends of the topological phase in the electric circuit 10 according to the present embodiment.
- the place where the wave function is localized is shown so as to correspond to the time evolution of (a) to (i) shown in FIG.
- the wave function can be read as the AC voltage of the electric circuit 10 according to the present embodiment. Therefore, the probability of existence of particles can be read as the square of the amplitude of the AC voltage.
- the wave function is localized at both ends of the T-shaped unit circuit (T junction), indicating that the edge state is formed at both ends of the topological phase.
- the rightmost edge state moves to the center, and in (c), the central edge state moves to the end of the unit circuit located above the T-shaped branch.
- the edge state at the left end moves to the center, and the superconducting phase of the unit circuit located above the T-shaped branch is changed.
- the edge state located at the center in (e) moves to the right end.
- the edge state located at the end of the unit circuit located above the T-shaped branch moves to the center, and in (g), the edge state moved to the center moves to the left end.
- the superconducting phase of the unit circuit located above the T-shaped branch is changed.
- the edge state initially located at the left end is located at the right end, and the edge state initially located at the right end is located at the left end.
- FIG. 12 is a diagram showing the time change of the energy eigenvalue and the Berry phase in the operation of exchanging the positions of the two edge states appearing at both ends of the topological phase in the electric circuit 10 according to the present embodiment.
- the time variation of the energy eigenvalue and the Berry phase is shown so as to correspond to the time evolution of (a) to (i) shown in FIG.
- the energy eigenvalue is read as the admittance of the electric circuit 10 according to the present embodiment
- the Berry phase is read as the phase of the AC voltage.
- the state where the energy eigenvalue is positive remains positive
- the state where the energy eigenvalue is negative remains negative. That is, the energy of the gap mode is never zero, and the gapless edge state is not mixed with the bulk gap mode by the blade operation.
- the Berry phase is changed from 0 to ⁇ / 2 by the operation from (d) to (e). That is, when the positions of the edge states appearing at both ends of the topological phase are exchanged by the operations (a) to (i), the phase of e i ⁇ / 2 is generated. This means that the edge state is non-commutative anyon. It also means that a quantum gate corresponding to i ⁇ x can be realized by the operations (a) to (i). Since the Berry phase is based on the adiabatic approximation, the operations (a) to (i) need to be performed at a speed sufficiently slower than the AC frequency ⁇ .
- the electric circuit 10 it is possible to perform a calculation equivalent to a quantum calculation by a blade operation in a topologically stable edge state.
- the edge state is stable with respect to perturbations, so it is equivalent to topological quantum calculation. It is still possible to calculate.
- FIG. 13 is a diagram schematically showing an operation of exchanging the positions of the edge states appearing at both ends of different topological phases in the electric circuit 10 according to the present embodiment.
- the topological phase unit circuit is shown by a relatively thick solid line
- the topologically obvious phase unit circuit is shown by a relatively thin solid line among a plurality of unit circuits arranged in a grid pattern including a cross-shaped branch.
- the edge states (voltage states) that appear at both ends of the topological phase are indicated by hatched circles.
- Represents the superconducting phase ⁇ ⁇ .
- reference numerals A and B are attached to the two edge states to be exchanged.
- the first edge state A is an edge state located at the left end of the topological phase
- the second edge state B is an edge state located at the right end of a different topological phase.
- the plurality of unit circuits in this example include a branch connection and are connected in a cross shape. As described below, such a configuration can realize an operation of exchanging the positions of two edge states appearing at both ends of different topological phases.
- first edge state A which initially appeared at the left end of the topological phase located at the upper side, is located at the right end of the topological phase located at the lower side and appears at the right end of the topological phase located at the lower side at the beginning.
- the second edge state B is located at the left end of the topological phase located on the upper side.
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Abstract
Provided is an electric circuit that operates at room temperature, can be fine-integrated, and is capable of performing a calculation that is equivalent to topological quantum calculation. An electric circuit 10 is provided with a plurality of unit circuits U1, U2 that include topological phase operation circuits TCS1, TCS2, respectively, in which at least four endpoints and impedance can be adjusted. A circuit Laplacian representing the proportional relationship between an AC current at one of the four endpoints and an AC voltage at an endpoint adjacent to the aforementioned endpoint is configured so as to correspond to the Hamiltonian of a quantum system, and the impedances of the topological phase operation circuits correspond to a parameter included in the Hamiltonian, the Hamiltonian having a topological phase in a prescribed region pertaining to the parameter.
Description
本出願は、2019年11月19日に出願された日本出願番号2019-209011号および2020年5月21日に出願された日本出願番号2020-88598号に基づくもので、ここにその記載内容を援用する。
This application is based on Japanese Application Nos. 2019-209011 filed on November 19, 2019 and Japanese Application Nos. 2020-88598 filed on May 21, 2020. Invite.
本発明は、電気回路に関する。
The present invention relates to an electric circuit.
半導体集積に関するムーアの法則の限界を突破する技術として量子計算が着目を集めている。古典計算が0と1のビットを用いて計算するのに対して量子計算では0と1の重ね合わせによる量子ビットを用いて計算を行う。量子ビットを用いることで、指数関数的な計算速度の向上が期待される。現在、様々な量子計算方法が研究段階にある。
量子計算を行うためのハードウェアとして、量子ドット、超伝導量子ビット、光量子コンピュータ、核磁気共鳴、イオントラップ、キャビティーQED(Quantum Electrodynamics)、トポロジカル超伝導体(非特許文献1)等が研究されているが、いずれも実用段階には達していない。 Quantum computing is attracting attention as a technology that breaks through the limits of Moore's Law regarding semiconductor integration. In the classical calculation, the calculation is performed using the bits of 0 and 1, whereas in the quantum calculation, the calculation is performed using the qubit by superposition of 0 and 1. By using qubits, it is expected that the calculation speed will be exponentially improved. Currently, various quantum calculation methods are in the research stage.
As hardware for performing quantum calculations, quantum dots, superconducting qubits, photon computers, nuclear magnetic resonance, ion traps, cavities QED (Quantum Electrodynamics), topological superconductors (Non-Patent Document 1), etc. have been studied. However, none of them have reached the practical stage.
量子計算を行うためのハードウェアとして、量子ドット、超伝導量子ビット、光量子コンピュータ、核磁気共鳴、イオントラップ、キャビティーQED(Quantum Electrodynamics)、トポロジカル超伝導体(非特許文献1)等が研究されているが、いずれも実用段階には達していない。 Quantum computing is attracting attention as a technology that breaks through the limits of Moore's Law regarding semiconductor integration. In the classical calculation, the calculation is performed using the bits of 0 and 1, whereas in the quantum calculation, the calculation is performed using the qubit by superposition of 0 and 1. By using qubits, it is expected that the calculation speed will be exponentially improved. Currently, various quantum calculation methods are in the research stage.
As hardware for performing quantum calculations, quantum dots, superconducting qubits, photon computers, nuclear magnetic resonance, ion traps, cavities QED (Quantum Electrodynamics), topological superconductors (Non-Patent Document 1), etc. have been studied. However, none of them have reached the practical stage.
現行の量子計算では、量子情報が短時間で喪失してしまうデコヒーレンスにどのように対処するかが重要な課題となっている。デコヒーレンスにより生じるエラーを訂正するためには、エラー訂正のためのキュービットが量子計算に必要なキュービットよりも多く必要になる。また、量子情報を長時間にわたり保持することが困難である。
In the current quantum calculation, how to deal with decoherence in which quantum information is lost in a short time is an important issue. In order to correct the error caused by decoherence, more qubits for error correction are required than the qubits required for quantum computation. Moreover, it is difficult to retain quantum information for a long period of time.
この課題を解決する一つの方法として、トポロジカル超伝導体中のマヨラナ粒子をブレイド操作することによって量子計算を行うトポロジカル量子計算が知られている(非特許文献1)。しかし、現状ではマヨラナ粒子を制御する方法が確立しておらず、室温で超伝導が実現できないため、冷却のために大量のヘリウムを必要とし、安価でコンパクトな装置とすることが困難である。さらに、超伝導量子回路を微細集積化する見通しも立っていない。
As one method for solving this problem, topological quantum calculation is known in which quantum calculation is performed by braiding the Majorana particles in a topological superconductor (Non-Patent Document 1). However, at present, a method for controlling Majorana particles has not been established, and superconductivity cannot be realized at room temperature. Therefore, a large amount of helium is required for cooling, and it is difficult to make an inexpensive and compact device. Furthermore, there is no prospect of finely integrating superconducting quantum circuits.
そこで、本発明は、室温で動作し、微細集積化が可能であり、トポロジカル量子計算と同等の計算を行うことができる電気回路を提供する。
Therefore, the present invention provides an electric circuit that operates at room temperature, can be finely integrated, and can perform calculations equivalent to topological quantum calculations.
本発明の一態様に係る電気回路は、少なくとも4つの端点及びインピーダンスが調整可能なトポロジカル相操作回路をそれぞれ含む複数のユニット回路を備え、4つの端点のうちいずれかの端点の交流電流と、当該端点に隣接する端点の交流電圧との比例関係を表す回路ラプラシアンが、量子系のハミルトニアンに対応するように構成され、トポロジカル相操作回路のインピーダンスは、ハミルトニアンに含まれるパラメータに対応し、ハミルトニアンは、パラメータに関する所定の領域でトポロジカル相を有する。
The electric circuit according to one aspect of the present invention includes a plurality of unit circuits including at least four endpoints and a topological phase operation circuit having adjustable impedance, and the alternating current at one of the four endpoints and the said. The circuit Laplacian, which represents the proportional relationship with the AC voltage of the end point adjacent to the end point, is configured to correspond to the Hamiltonian of the quantum system, and the impedance of the topological phase operation circuit corresponds to the parameters contained in the Hamiltonian. It has a topological phase in a given area of parameters.
この態様によれば、回路ラプラシアンが、所定のパラメータ領域でトポロジカル相を有するような量子系のハミルトニアンに対応するように構成することで、トポロジカル相とトポロジカルに自明な相との間にエッジ状態に相当する電圧状態をつくることができ、その電圧状態をブレイド操作することでトポロジカル量子計算と同等の計算を行うことができる。また、通常の電気回路であるため、室温で動作し、微細集積化が可能である。
According to this aspect, the circuit Laplacian is configured to correspond to the Hamiltonian of a quantum system having a topological phase in a predetermined parameter region, thereby creating an edge state between the topological phase and the topologically obvious phase. A corresponding voltage state can be created, and a calculation equivalent to a topological quantum calculation can be performed by manipulating the voltage state with a blade. Moreover, since it is a normal electric circuit, it operates at room temperature and can be finely integrated.
上記態様において、複数のユニット回路は、電子バンドに対応する第1回路及びホールバンドに対応する第2回路をそれぞれ含み、第1回路の交流電圧の位相及び第2回路の交流電圧の位相は、互いに逆であってもよい。
In the above embodiment, the plurality of unit circuits include a first circuit corresponding to an electronic band and a second circuit corresponding to a hall band, respectively, and the phase of the AC voltage of the first circuit and the phase of the AC voltage of the second circuit are set. They may be opposite to each other.
この態様によれば、電子とホールに相当する電圧状態をつくることができ、トポロジカル相とトポロジカルに自明な相との間にマヨラナ粒子に相当する電圧状態をつくることができる。
According to this aspect, a voltage state corresponding to electrons and holes can be created, and a voltage state corresponding to Majorana particles can be created between the topological phase and the topologically trivial phase.
上記態様において、複数のユニット回路は、第1回路及び第2回路を接続し、交流電圧の位相を変化させる位相操作回路をそれぞれ含んでもよい。
In the above aspect, the plurality of unit circuits may include a phase operation circuit that connects the first circuit and the second circuit and changes the phase of the AC voltage.
この態様によれば、超伝導位相に相当するパラメータを実現することができる。
According to this aspect, a parameter corresponding to the superconducting phase can be realized.
上記態様において、トポロジカル相操作回路は、第1回路又は第2回路とグランドとを接続し、インピーダンスを切り替えるスイッチを含んでもよい。
In the above aspect, the topological phase operation circuit may include a switch that connects the first circuit or the second circuit to the ground and switches the impedance.
この態様によれば、トポロジカル相とトポロジカルに自明な相の長さを任意に調整することができるようになり、エッジ状態に関する多様なブレイド操作を実現することができる。
According to this aspect, the lengths of the topological phase and the topologically trivial phase can be arbitrarily adjusted, and various blade operations related to the edge state can be realized.
上記態様において、複数のユニット回路は、分岐接続を含み、T字型に接続されていてもよい。
In the above aspect, the plurality of unit circuits may be connected in a T shape including a branch connection.
この態様によれば、トポロジカル相の両端に現れる2つのエッジ状態の位置を交換する操作を実現することができる。
According to this aspect, it is possible to realize an operation of exchanging the positions of two edge states appearing at both ends of the topological phase.
上記態様において、複数のユニット回路は、分岐接続を含み、十字型に接続されていてもよい。
In the above aspect, the plurality of unit circuits may include a branch connection and may be connected in a cross shape.
この態様によれば、異なるトポロジカル相の両端に現れる2つのエッジ状態の位置を交換する操作を実現することができる。
According to this aspect, it is possible to realize an operation of exchanging the positions of two edge states appearing at both ends of different topological phases.
上記態様において、ハミルトニアンは、電子-ホール対称性を有するBogoliubov-de Gennes形式で記述される超伝導体のハミルトニアン、又は、カイラル対称性を有するハミルトニアンでもよい。
In the above aspect, the Hamiltonian may be a superconductor Hamiltonian described in the Bogoliubov-de Gennes format having electron-hole symmetry, or a Hamiltonian having chiral symmetry.
この態様によれば、電子-ホール対称性又はカイラル対称性により安定なマヨラナ粒子に相当する電圧状態をつくることができる。
According to this aspect, it is possible to create a voltage state corresponding to a stable Majorana particle by electron-hole symmetry or chiral symmetry.
上記態様において、複数のユニット回路のうちトポロジカル相に対応するユニット回路と複数のユニット回路のうちトポロジカルに自明な相に対応するユニット回路との境界に位置する端点の交流電圧又は複数のユニット回路のうち端部に位置するユニット回路の端点の交流電圧は、ハミルトニアンのエッジ状態に対応してもよい。
In the above embodiment, the AC voltage at the end point located at the boundary between the unit circuit corresponding to the topological phase of the plurality of unit circuits and the unit circuit corresponding to the topologically obvious phase of the plurality of unit circuits, or the plurality of unit circuits. The AC voltage at the end point of the unit circuit located at the end may correspond to the edge state of the Hamiltonian.
この態様によれば、トポロジカル相とトポロジカルに自明な相との間にエッジ状態に相当する電圧状態をつくることができ、その電圧状態をブレイド操作することでトポロジカル量子計算と同等の計算を行うことができる。
According to this aspect, a voltage state corresponding to an edge state can be created between a topological phase and a topologically trivial phase, and a calculation equivalent to a topological quantum calculation can be performed by manipulating the voltage state in a blade. Can be done.
本発明によれば、室温で動作し、微細集積化が可能であり、トポロジカル量子計算と同等の計算を行うことができる電気回路を提供することができる。
According to the present invention, it is possible to provide an electric circuit that operates at room temperature, can be finely integrated, and can perform calculations equivalent to topological quantum calculations.
添付図面を参照して、本発明の実施形態について説明する。なお、各図において、同一の符号を付したものは、同一又は同様の構成を有する。
An embodiment of the present invention will be described with reference to the accompanying drawings. In each figure, those having the same reference numerals have the same or similar configurations.
トポロジカル量子計算では、非可換エニオンのブレイド操作を量子ゲートとして用いる。空間が3次元である通常の系では、粒子の交換によって波動関数の位相変化が0又はπとなり、位相変化が0となる粒子をボソンと呼び、位相変化がπとなる粒子をフェルミオンと呼ぶ。一方、空間が2次元である系では、粒子の交換によって波動関数の位相変化が任意の値となるエニオンと呼ばれる粒子が実現できる。例えば、非特許文献1では、1次元超伝導ワイヤのエッジ状態として非可換エニオンを実現している。
In topological quantum computation, the blade operation of non-commutative anyon is used as the quantum gate. In a normal system in which the space is three-dimensional, a particle whose phase change of the wave function becomes 0 or π due to particle exchange and whose phase change becomes 0 is called a boson, and a particle whose phase change becomes π is called a fermion. .. On the other hand, in a system in which the space is two-dimensional, particles called anyon can be realized in which the phase change of the wave function becomes an arbitrary value by exchanging the particles. For example, in Non-Patent Document 1, non-commutative anyon is realized as an edge state of a one-dimensional superconducting wire.
1次元超伝導ワイヤを単純化したハミルトニアンとして、以下の数式(1)のキタエフモデルが知られている。
As a Hamiltonian that simplifies the one-dimensional superconducting wire, the Kitaev model of the following mathematical formula (1) is known.
ここで、εk=-t cosk-μであり、tはホッピング振幅、μは化学ポテンシャル、φは超伝導位相、Δはギャップパラメータである。数式(1)のハミルトニアンは、Δがゼロでなく、|μ|>|2t|の場合にトポロジカルに自明な相となり、|μ|<|2t|の場合にトポロジカル相となる。
Here, ε k = −t cosk−μ, t is the hopping amplitude, μ is the chemical potential, φ is the superconducting phase, and Δ is the gap parameter. The Hamiltonian of the equation (1) is a topologically trivial phase when Δ is not zero and | μ |> | 2t |, and is a topological phase when | μ | << | 2t |.
トポロジカル相を特徴付ける位相不変量は、典型的には運動量空間からヒルベルト空間への写像の巻き付き数で定義され、例えば1,2…のような飛び飛びの値しか取らず、トポロジカルに自明な相の位相不変量は0となる。トポロジカル相の内部では、ギャップΔが有限であるため、位相不変量は変化しない。一方、トポロジカルに自明な相の位相不変量は0であるため、トポロジカル相とトポロジカルに自明な相との境界でギャップが閉じ、ギャップレス状態が生じて位相不変量が変化する。このギャップレス状態をエッジ状態と呼ぶ。数式(1)のキタエフモデルでは、エッジ状態として電子とホール(粒子と反粒子)の区別が無いマヨラナ粒子が現れる。
The topological invariants that characterize the topological phase are typically defined by the number of wraps of the map from the momentum space to the Hilbert space, taking only discrete values such as 1, 2, ..., and topologically trivial phase phases. The invariant is 0. Inside the topological phase, the phase invariant does not change because the gap Δ is finite. On the other hand, since the topologically trivial phase invariant is 0, the gap is closed at the boundary between the topological phase and the topologically trivial phase, a gapless state occurs, and the topological invariant changes. This gapless state is called an edge state. In the Kitaev model of mathematical formula (1), Majorana particles that do not distinguish between electrons and holes (particles and antiparticles) appear as edge states.
本実施形態に係る電気回路10は、数式(1)と同等の回路ラプラシアンを有し、量子系のエッジ状態に対応する電圧状態をつくるものである。また、本実施形態に係る電気回路10は、エッジ状態に対応する電圧状態をブレイド操作して、トポロジカル量子計算と同等の計算を行うことができる。
The electric circuit 10 according to the present embodiment has a circuit Laplacian equivalent to the mathematical formula (1), and creates a voltage state corresponding to the edge state of the quantum system. Further, the electric circuit 10 according to the present embodiment can perform a calculation equivalent to the topological quantum calculation by performing a blade operation on the voltage state corresponding to the edge state.
数式(1)のハミルトニアンは、Bogoliubov-de Gennes形式で記述される1次元超伝導体のハミルトンであり、電子-ホール対称性を有する。電子-ホール対称性とは、ハミルトニアンが、電子とホールを交換する演算子ΞについてΞ―1H(k)Ξ=H(-k)を満たす対称性である。このようなハミルトニアンに対応する回路ラプラシアンを有することで、電子-ホール対称性により安定なマヨラナ粒子又はマヨラナ粒子と同様の性質を持つマヨラナ類似状態に相当する電圧状態をつくることができる。
The Hamiltonian of the equation (1) is a Hamilton of a one-dimensional superconductor described in the Bogoliubov-de Gennes form, and has electron-hole symmetry. The electron-hole symmetry is the symmetry in which the Hamiltonian satisfies Ξ-1 H (k) Ξ = H (−k) for the operator Ξ that exchanges electrons and holes. By having a circuit Laplacian corresponding to such a Hamiltonian, it is possible to create a stable Majorana fermion due to electron-hole symmetry or a voltage state corresponding to a Majorana-like state having properties similar to those of Majorana fermion.
また、電子-ホール対称性の代わりにカイラル対称性ΠH(k)+H(k)Π=0を満たす場合にも多重縮退した状態を作ることができる。この場合、多重縮退した状態の位置を交換するブレイド操作により、同様に、トポロジカル量子計算と同等の計算を行うことができる。
Also, when the chiral symmetry ΠH (k) + H (k) Π = 0 is satisfied instead of the electron-hole symmetry, a multiple degenerate state can be created. In this case, the same calculation as the topological quantum calculation can be performed by the blade operation of exchanging the positions of the multiple degenerate states.
図1は、本発明の実施形態に係る電気回路10を示す図である。電気回路10は、少なくとも4つの端点及びインピーダンスが調整可能なトポロジカル相操作回路TCSをそれぞれ含む複数のユニット回路を備える。同図では、隣接するユニット回路U1及びユニット回路U2を示している。
FIG. 1 is a diagram showing an electric circuit 10 according to an embodiment of the present invention. The electrical circuit 10 includes a plurality of unit circuits each including at least four endpoints and a topological phase operating circuit TCS with adjustable impedance. In the figure, the adjacent unit circuit U1 and the unit circuit U2 are shown.
4つの端点のうちいずれかの端点の交流電流と、当該端点に隣接する端点の交流電圧との比例関係を表す回路ラプラシアンは、量子系のハミルトニアンに対応するように構成されている。ここで、回路ラプラシアンJab(ω)は、端点aの交流電流Ia(ω)と、端点bの交流電圧Vb(ω)とについて、Ia(ω)=ΣbJab(ω)Vb(ω)により定義される量である。
The circuit Laplacian, which represents the proportional relationship between the alternating current of one of the four endpoints and the alternating voltage of the endpoint adjacent to the endpoint, is configured to correspond to the Hamiltonian of the quantum system. Here, the circuit Laplacian J ab (ω) has I a (ω) = Σ b J ab (ω) with respect to the AC current I a (ω) at the end point a and the AC voltage V b (ω) at the end point b. It is an quantity defined by V b (ω).
具体的には、本実施形態に係る電気回路10の回路ラプラシアンは、以下の数式(2)で表される。
Specifically, the circuit Laplacian of the electric circuit 10 according to the present embodiment is represented by the following mathematical formula (2).
ここで、Cは、図1に示すキャパシタンスであり、Lは図1に示すインダクタンスである。また、C0は、後に説明するトポロジカル相操作回路TCS1,TCS2に含まれるキャパシタンスであり、CX
φ=CXsinφは、後に説明する位相操作回路PCSに含まれるキャパシタンスであり、Rφ=Rb/cosφは、後に説明する位相操作回路PCSに含まれる抵抗である。ここで、φは、超伝導位相に相当するパラメータである。さらに、σx,σy,σzは、2×2のパウリ行列である。なお、トポロジカル相操作回路TCS1,TCS2には、インダクタンスL0も含まれる。また、位相操作回路PCSには、インダクタンスLX
φ=LX/sinφも含まれる。
Here, C is the capacitance shown in FIG. 1, and L is the inductance shown in FIG. Further, C 0 is the capacitance included in the topological phase operation circuits TCS1 and TCS2 described later, and C X φ = C X sin φ is the capacitance included in the phase operation circuit PCS described later, and R φ = R. b / cosφ is a resistor included in the phase control circuit PCS described later. Here, φ is a parameter corresponding to the superconducting phase. Furthermore, σ x , σ y , and σ z are 2 × 2 Pauli matrices. Note that the topological phase operation circuit TCS1, TCS2, inductance L 0 are also included. The phase control circuit PCS also includes an inductance L X φ = L X / sin φ.
数式(2)の回路ラプラシアンは、ω=1/√(LC)=1/√(L0C0)=1/√(LXCX)である場合に、Jab(ω)=iωHab(ω)の関係で数式(1)のハミルトニアンに対応する。この場合、トポロジカル相操作回路TCS1,TCS2のインピーダンスは、数式(1)のハミルトニアンに含まれるパラメータt,μに対応する。|μ|>|2t|の場合(トポロジカルに自明な相の場合)は、トポロジカル相操作回路TCS1,TCS2がオフ状態の場合に対応し、|μ|<|2t|の場合(トポロジカル相の場合)は、トポロジカル相操作回路TCS1,TCS2がオン状態の場合に対応する。このように、回路ラプラシアンに対応するハミルトニアンは、パラメータに関する所定の領域でトポロジカル相を有し、電気回路10は、トポロジカル相操作回路TCS1,TCS2のインピーダンスを変化させることで、トポロジカル相とトポロジカルに自明な相とを切り替えることができる。
The circuit Laplacian of the formula (2) is J ab (ω) = iωH ab when ω = 1 / √ (LC) = 1 / √ (L 0 C 0 ) = 1 / √ (L X C X ). It corresponds to the Hamiltonian of the mathematical formula (1) in relation to (ω). In this case, the impedances of the topological phase operation circuits TCS1 and TCS2 correspond to the parameters t and μ included in the Hamiltonian of the equation (1). In the case of | μ |> | 2t | (in the case of a topologically obvious phase), it corresponds to the case where the topological phase operation circuits TCS1 and TCS2 are in the off state, and in the case of | μ | << | 2t | (in the case of a topological phase). ) Corresponds to the case where the topological phase operation circuits TCS1 and TCS2 are in the ON state. As described above, the Hamiltonian corresponding to the circuit Laplacian has a topological phase in a predetermined region regarding the parameter, and the electric circuit 10 is topologically self-evident with the topological phase by changing the impedance of the topological phase operation circuits TCS1 and TCS2. You can switch between different phases.
本実施形態に係る電気回路10によれば、所定のパラメータ領域でトポロジカル相を有するような量子系のハミルトニアンに対応するように回路ラプラシアンを構成することで、トポロジカル相とトポロジカルに自明な相との間にエッジ状態に相当する電圧状態をつくることができ、その電圧状態をブレイド操作することでトポロジカル量子計算と同等の計算を行うことができる。また、本実施形態に係る電気回路10は、通常の電気回路であるため、比較的安価であり、室温で動作し、微細集積化が可能である。また、トポロジカル量子計算をシミュレートするため、デコヒーレンスの影響がなく、エラー訂正のために回路を大規模化する必要がない。
According to the electric circuit 10 according to the present embodiment, the topological phase and the topologically obvious phase can be obtained by configuring the circuit Laplacian so as to correspond to the Hamiltonian of the quantum system having the topological phase in a predetermined parameter region. A voltage state corresponding to the edge state can be created between them, and the same calculation as the topological quantum calculation can be performed by manipulating the voltage state with a blade. Further, since the electric circuit 10 according to the present embodiment is a normal electric circuit, it is relatively inexpensive, operates at room temperature, and can be finely integrated. In addition, since it simulates topological quantum computation, it is not affected by decoherence, and there is no need to increase the scale of the circuit for error correction.
複数のユニット回路U1,U2は、電子バンドに対応する第1回路E1及びホールバンドに対応する第2回路H1をそれぞれ含み、第1回路E1の交流電圧の位相及び第2回路H1の交流電圧の位相は、互いに逆である。このような構成とすることで、電子とホールに相当する電圧状態をつくることができ、トポロジカル相とトポロジカルに自明な相との間にマヨラナ粒子又はマヨラナ粒子と同様の性質を持つマヨラナ類似状態に相当する電圧状態をつくることができる。
The plurality of unit circuits U1 and U2 include the first circuit E1 corresponding to the electronic band and the second circuit H1 corresponding to the hall band, respectively, and have the phase of the AC voltage of the first circuit E1 and the AC voltage of the second circuit H1. The phases are opposite to each other. With such a configuration, a voltage state corresponding to electrons and holes can be created, and a Majorana particle or a Majorana-like state having properties similar to those of Majorana particles can be created between the topological phase and the topologically obvious phase. It is possible to create a corresponding voltage state.
複数のユニット回路U1,U2は、第1回路E1及び第2回路H1を接続し、交流電圧の位相を変化させる位相操作回路PCSをそれぞれ含む。位相操作回路PCSによって、量子系のハミルトニアンに含まれる超伝導位相に相当するパラメータを実現することができる。
The plurality of unit circuits U1 and U2 include a phase operation circuit PCS that connects the first circuit E1 and the second circuit H1 and changes the phase of the AC voltage. The phase manipulation circuit PCS can realize parameters corresponding to the superconducting phase included in the Hamiltonian of the quantum system.
複数のユニット回路U1,U2は、分岐接続を含み、T字型に接続されている。後に説明するように、T字型の分岐を含むことで、トポロジカル相の両端に現れる2つのエッジ状態の位置を交換する操作を実現することができる。なお、T字型の分岐は、Y字型であったり、その他の分岐であったりしてもよい。
The plurality of unit circuits U1 and U2 include a branch connection and are connected in a T shape. As will be described later, by including the T-shaped branch, it is possible to realize an operation of exchanging the positions of the two edge states appearing at both ends of the topological phase. The T-shaped branch may be a Y-shaped branch or another branch.
複数のユニット回路U1、U2のうちトポロジカル相に対応するユニット回路と複数のユニット回路U1、U2のうちトポロジカルに自明な相に対応するユニット回路との境界に位置する端点の交流電圧又は複数のユニット回路U1、U2のうち端部に位置するユニット回路の端点の交流電圧は、ハミルトニアンのエッジ状態に対応する。ここで、複数のユニット回路U1、U2のうち端部に位置するユニット回路の端点は、空気又は通常の絶縁体と接しており、トポロジカルに自明な相と接している。本実施形態に係る電気回路10によれば、トポロジカル相とトポロジカルに自明な相との間にエッジ状態に相当する電圧状態をつくることができ、その電圧状態をブレイド操作することでトポロジカル量子計算と同等の計算を行うことができる。
AC voltage or multiple units at the end point located at the boundary between the unit circuit corresponding to the topological phase of the plurality of unit circuits U1 and U2 and the unit circuit corresponding to the topologically obvious phase of the plurality of unit circuits U1 and U2. The AC voltage at the end point of the unit circuit located at the end of the circuits U1 and U2 corresponds to the edge state of the Hamiltonian. Here, the end points of the unit circuits located at the ends of the plurality of unit circuits U1 and U2 are in contact with air or an ordinary insulator, and are in contact with a topologically obvious phase. According to the electric circuit 10 according to the present embodiment, a voltage state corresponding to an edge state can be created between a topological phase and a topologically trivial phase, and the voltage state can be manipulated by a blade to perform topological quantum calculation. Equivalent calculations can be performed.
図2は、本実施形態に係る電気回路10に含まれる位相操作回路PCSを示す図である。同図では、左側の2本の線が第1回路E2の端点に接続され、右側の2本の線が第2回路H2の端点に接続される場合を示している。位相操作回路PCSは、オペアンプOP、キャパシタンスCX
φ及びインダクタンスLX
φを含む。
FIG. 2 is a diagram showing a phase control circuit PCS included in the electric circuit 10 according to the present embodiment. In the figure, the case where the two wires on the left side are connected to the end points of the first circuit E2 and the two wires on the right side are connected to the end points of the second circuit H2 is shown. The phase control circuit PCS includes an operational amplifier OP, a capacitance C X φ and an inductance L X φ .
図3は、本実施形態に係る位相操作回路PCSに含まれるオペアンプOPの構成を示す図である。オペアンプOPは、抵抗Rφを含む。
FIG. 3 is a diagram showing a configuration of an operational amplifier OP included in the phase operation circuit PCS according to the present embodiment. The operational amplifier OP includes a resistor Rφ .
図4は、本実施形態に係る位相操作回路PCSによってφ=0の電子-ホール間相互作用を実現する場合を示す図である。同図では、上側の2本の線が第1回路E1の端点に接続され、下側の2本の線が第2回路H1の端点に接続される場合を示している。
FIG. 4 is a diagram showing a case where the electron-hole interaction of φ = 0 is realized by the phase operation circuit PCS according to the present embodiment. The figure shows a case where the upper two wires are connected to the end points of the first circuit E1 and the lower two wires are connected to the end points of the second circuit H1.
図5は、本実施形態に係る位相操作回路によってφ=πの電子-ホール間相互作用を実現する場合を示す図である。同図では、上側の2本の線が第1回路E1の端点に接続され、下側の2本の線が第2回路H1の端点に接続される場合を示している。
FIG. 5 is a diagram showing a case where the electron-hole interaction of φ = π is realized by the phase manipulation circuit according to the present embodiment. The figure shows a case where the upper two wires are connected to the end points of the first circuit E1 and the lower two wires are connected to the end points of the second circuit H1.
図6は、本実施形態に係る電気回路10に含まれ、オン状態であるトポロジカル相操作回路TCS1を示す図である。トポロジカル相操作回路TCS1は、キャパシタンスC0及びインダクタンスL0を含む。同図では、上側の1本の線がグランドに接続され、下側の1本の線が第1回路E1の端点に接続される場合を示している。
FIG. 6 is a diagram showing a topological phase operation circuit TCS1 included in the electric circuit 10 according to the present embodiment and in the ON state. The topological phase operation circuit TCS1 includes a capacitance C 0 and an inductance L 0 . The figure shows a case where one upper wire is connected to the ground and one lower wire is connected to the end point of the first circuit E1.
トポロジカル相操作回路TCS1は、第1回路E1又は第2回路H1とグランドとを接続し、インピーダンスを切り替えるスイッチを含む。
The topological phase operation circuit TCS1 includes a switch that connects the first circuit E1 or the second circuit H1 to the ground and switches the impedance.
オン状態であるトポロジカル相操作回路TCS1は、第1回路E1の端点を、インダクタンスL0を介してグランドに接続する。
Topological phase operation circuit TCS1 is in the on state, the end point of the first circuit E1, is connected to the ground via the inductor L 0.
図7は、本実施形態に係る電気回路10に含まれ、オフ状態であるトポロジカル相操作回路TCS1を示す図である。同図では、上側の1本の線がグランドに接続され、下側の1本の線が第1回路E1の端点に接続される場合を示している。
FIG. 7 is a diagram showing a topological phase operation circuit TCS1 included in the electric circuit 10 according to the present embodiment and in an off state. The figure shows a case where one upper wire is connected to the ground and one lower wire is connected to the end point of the first circuit E1.
オフ状態であるトポロジカル相操作回路TCS1は、第1回路E1の端点を、キャパシタンスC0を介してグランドに接続する。
Topological phase operation circuit TCS1 is off state, the end point of the first circuit E1, is connected to the ground via the capacitance C 0.
第2回路H2に接続されるトポロジカル相操作回路TCS2は、トポロジカル相操作回路TCS1と同じ構成を有するが、トポロジカル相操作回路TCS1に対してオンオフ状態が逆となる。すなわち、オン状態であるトポロジカル相操作回路TCS2は、第2回路H1の端点を、キャパシタンスC0を介してグランドに接続する。また、オフ状態であるトポロジカル相操作回路TCS2は、第2回路H1の端点を、インダクタンスL0を介してグランドに接続する。
The topological phase operation circuit TCS2 connected to the second circuit H2 has the same configuration as the topological phase operation circuit TCS1, but the on / off state is opposite to that of the topological phase operation circuit TCS1. That is, the topological phase operating circuit is in the ON state TCS2 is the end point of the second circuit H1, connected to ground through a capacitance C 0. Furthermore, topological phase operating circuit is off TCS2 is the end point of the second circuit H1, connected to the ground via the inductor L 0.
直線状に並んだ複数のトポロジカル相操作回路TCS1,TCS2のオンオフ状態を切り替えることで、トポロジカル相とトポロジカルに自明な相の長さを任意に調整することができるようになる。また、以下に説明するように、トポロジカル相とトポロジカルに自明な相の境界に現れるエッジ状態に関する多様なブレイド操作を実現することができる。
By switching the on / off state of a plurality of topological phase operation circuits TCS1 and TCS2 arranged in a straight line, the length of the topological phase and the topologically obvious phase can be arbitrarily adjusted. In addition, as described below, it is possible to realize various blade operations related to the edge state appearing at the boundary between the topological phase and the topologically trivial phase.
図14は、本実施形態に係る電気回路10に記憶回路を設けた一例を示す図である。同図では、各端点において、トポロジカル相操作回路TCS1,TCS2と並列にLC共振器Rを接続することにより、ブレイド操作の情報を、LC共振器R中の振動電流または振動電圧の振幅と位相で記憶することができる。
FIG. 14 is a diagram showing an example in which a storage circuit is provided in the electric circuit 10 according to the present embodiment. In the figure, by connecting the LC resonator R in parallel with the topological phase operation circuits TCS1 and TCS2 at each end point, the information of the blade operation is obtained by the amplitude and phase of the vibration current or the vibration voltage in the LC resonator R. Can be remembered.
図15は、LC共振器Rを示す図である。同図に示すとおり、LC共振器Rは、キャパシタンスC0とインダクタンスL0とが並列に接続され、その一端がグランドに接続され、他端が第1回路又は第2回路の端点に接続される。
FIG. 15 is a diagram showing an LC resonator R. As shown in the figure, in the LC resonator R, the capacitance C 0 and the inductance L 0 are connected in parallel, one end thereof is connected to the ground, and the other end is connected to the end point of the first circuit or the second circuit. ..
図8は、本実施形態に係る電気回路10におけるエッジ状態のブレイド操作を模式的に示す図である。同図では、直線状に並んだ複数のユニット回路のうちトポロジカル相(topological)のユニット回路を比較的太い実線で示し、トポロジカルに自明な相(trivial)のユニット回路を比較的細い実線で示し、トポロジカル相とトポロジカルに自明な相との境界に現れるエッジ状態(電圧状態)を、ハッチングを入れた丸印で示している。
FIG. 8 is a diagram schematically showing a blade operation in an edge state in the electric circuit 10 according to the present embodiment. In the figure, the topological phase unit circuit is shown by a relatively thick solid line, and the topologically trivial unit circuit is shown by a relatively thin solid line among a plurality of linearly arranged unit circuits. The edge state (voltage state) that appears at the boundary between the topological phase and the topologically trivial phase is indicated by a hatched circle.
同図では、トポロジカル相の両端に現れる2つのエッジ状態(マヨラナ類似状態)MA
j-1及びMB
j-1の位置を交換する操作と、トポロジカルに自明な相を挟んで隣接する2つのエッジ状態(マヨラナ類似状態)MB
j及びMA
j+1の位置を交換する操作を示している。両操作の詳細は、図9及び10を用いて説明する。このように、本実施形態に係る電気回路10では、直線状に並んだエッジ状態をブレイド操作することで、量子計算と同等の計算を行う。
In the figure, the topological phase two edge states (Majorana similar state) appearing across M A j-1 and M B j-1 position and operation of exchanging the topological into two adjacent members across the trivial phase The operation of exchanging the positions of the edge state (Majorana-like state) M B j and M A j + 1 is shown. Details of both operations will be described with reference to FIGS. 9 and 10. As described above, in the electric circuit 10 according to the present embodiment, a calculation equivalent to the quantum calculation is performed by performing a blade operation on the edge states arranged in a straight line.
本実施形態に係る電気回路10は、N個のトポロジカル相とN個のトポロジカルに自明な相とを接触させることで、その境界にトポロジカルに保護されたエッジ状態を2N個生成し、それらを交換するブレイド操作によりトポロジカル量子計算と同等の計算を行う。
The electric circuit 10 according to the present embodiment generates 2N topologically protected edge states at the boundary by bringing N topological phases and N topologically trivial phases into contact with each other, and exchanges them. Performs the same calculation as the topological quantum calculation by the blade operation.
図9は、本実施形態に係る電気回路10においてトポロジカル相の両端に現れる2つのエッジ状態の位置を交換する操作を模式的に示す図である。同図では、直線状に並んだ複数のユニット回路のうちトポロジカル相のユニット回路を比較的太い実線で示し、トポロジカルに自明な相のユニット回路を比較的細い実線で示し、トポロジカル相の両端に現れるエッジ状態(電圧状態)を、ハッチングを入れた丸印で示している。また、ユニット回路を表す実線に重ねて記載された左向きの矢印及び上向きの矢印は、超伝導位相φ=0を表し、ユニット回路を表す実線に重ねて記載された右向きの矢印及び下向きの矢印は、超伝導位相φ=πを表す。
FIG. 9 is a diagram schematically showing an operation of exchanging the positions of two edge states appearing at both ends of the topological phase in the electric circuit 10 according to the present embodiment. In the figure, the topological phase unit circuit is shown by a relatively thick solid line, and the topologically obvious phase unit circuit is shown by a relatively thin solid line among a plurality of linearly arranged unit circuits, and appears at both ends of the topological phase. The edge state (voltage state) is indicated by a hatched circle. Further, the left-pointing arrow and the upward arrow overlaid on the solid line representing the unit circuit represent the superconducting phase φ = 0, and the right-pointing arrow and the down-pointing arrow overlaid on the solid line representing the unit circuit represent the superconducting phase φ = 0. , Represents the superconducting phase φ = π.
(a)
トポロジカル相の両端に現れているエッジ状態のうち、右端のエッジ状態を中央に移動させるため、ユニット回路のトポロジカル相操作回路TCS1,TCS2のスイッチを右端側からオフに切り替えていく。以下、ユニット回路のまとまりを、図示のとおり、1番、2番及び3番と呼ぶ。1番、2番及び3番のユニット回路のまとまりは、T字型に分岐している。 (A)
Of the edge states appearing at both ends of the topological phase, in order to move the rightmost edge state to the center, the switches of the topological phase operation circuits TCS1 and TCS2 of the unit circuit are switched off from the right end side. Hereinafter, the unit circuit group will be referred to as No. 1, No. 2, and No. 3 as shown in the figure. The unit circuits of No. 1, No. 2, and No. 3 are branched into a T shape.
トポロジカル相の両端に現れているエッジ状態のうち、右端のエッジ状態を中央に移動させるため、ユニット回路のトポロジカル相操作回路TCS1,TCS2のスイッチを右端側からオフに切り替えていく。以下、ユニット回路のまとまりを、図示のとおり、1番、2番及び3番と呼ぶ。1番、2番及び3番のユニット回路のまとまりは、T字型に分岐している。 (A)
Of the edge states appearing at both ends of the topological phase, in order to move the rightmost edge state to the center, the switches of the topological phase operation circuits TCS1 and TCS2 of the unit circuit are switched off from the right end side. Hereinafter, the unit circuit group will be referred to as No. 1, No. 2, and No. 3 as shown in the figure. The unit circuits of No. 1, No. 2, and No. 3 are branched into a T shape.
(b)
右端のエッジ状態を中央に移動させた後、3番のユニット回路のまとまりにエッジ状態を移動させる。この操作は、3番のユニット回路のまとまりに含まれるトポロジカル相操作回路TCS1,TCS2のスイッチを分岐側からオンに切り替えていくことで行われる。 (B)
After moving the rightmost edge state to the center, the edge state is moved to the unit circuit No. 3. This operation is performed by switching on the switches of the topological phase operation circuits TCS1 and TCS2 included in the unit circuit No. 3 from the branch side.
右端のエッジ状態を中央に移動させた後、3番のユニット回路のまとまりにエッジ状態を移動させる。この操作は、3番のユニット回路のまとまりに含まれるトポロジカル相操作回路TCS1,TCS2のスイッチを分岐側からオンに切り替えていくことで行われる。 (B)
After moving the rightmost edge state to the center, the edge state is moved to the unit circuit No. 3. This operation is performed by switching on the switches of the topological phase operation circuits TCS1 and TCS2 included in the unit circuit No. 3 from the branch side.
(c)
当初右端に位置していたエッジ状態を3番のユニット回路のまとまりの端部に移動させた後、左端に位置しているエッジ状態を中央に移動させるため、ユニット回路のトポロジカル相操作回路TCS1,TCS2のスイッチを左端側からオフに切り替えていく。 (C)
In order to move the edge state located at the right end to the end of the unit circuit No. 3 and then move the edge state located at the left end to the center, the topological phase operation circuit TCS1 of the unit circuit The switch of TCS2 is switched off from the left end side.
当初右端に位置していたエッジ状態を3番のユニット回路のまとまりの端部に移動させた後、左端に位置しているエッジ状態を中央に移動させるため、ユニット回路のトポロジカル相操作回路TCS1,TCS2のスイッチを左端側からオフに切り替えていく。 (C)
In order to move the edge state located at the right end to the end of the unit circuit No. 3 and then move the edge state located at the left end to the center, the topological phase operation circuit TCS1 of the unit circuit The switch of TCS2 is switched off from the left end side.
(d)
左端のエッジ状態を中央に移動させた後、3番のユニット回路のまとまりの超伝導位相をφ=0からφ=πに変化させる。 (D)
After moving the leftmost edge state to the center, the superconducting phase of the unit circuit No. 3 is changed from φ = 0 to φ = π.
左端のエッジ状態を中央に移動させた後、3番のユニット回路のまとまりの超伝導位相をφ=0からφ=πに変化させる。 (D)
After moving the leftmost edge state to the center, the superconducting phase of the unit circuit No. 3 is changed from φ = 0 to φ = π.
(e)
その後、中央に位置していたエッジ状態を右端に移動させる。 (E)
After that, the edge state located in the center is moved to the right end.
その後、中央に位置していたエッジ状態を右端に移動させる。 (E)
After that, the edge state located in the center is moved to the right end.
(f)
3番のユニット回路のまとまりの端部に移動させたエッジ状態を、中央に移動させる。 (F)
The edge state moved to the end of the unit circuit of No. 3 is moved to the center.
3番のユニット回路のまとまりの端部に移動させたエッジ状態を、中央に移動させる。 (F)
The edge state moved to the end of the unit circuit of No. 3 is moved to the center.
(g)
中央に移動させたエッジ状態を、左端に移動させる。 (G)
The edge state moved to the center is moved to the left end.
中央に移動させたエッジ状態を、左端に移動させる。 (G)
The edge state moved to the center is moved to the left end.
(h)
中央に位置していたエッジ状態を左端に移動させた後、3番のユニット回路のまとまりの超伝導位相をφ=πからφ=0に変化させる。 (H)
After moving the edge state located in the center to the left end, the superconducting phase of the unit circuit No. 3 is changed from φ = π to φ = 0.
中央に位置していたエッジ状態を左端に移動させた後、3番のユニット回路のまとまりの超伝導位相をφ=πからφ=0に変化させる。 (H)
After moving the edge state located in the center to the left end, the superconducting phase of the unit circuit No. 3 is changed from φ = π to φ = 0.
(i)
最終的に、当初左端に位置していたエッジ状態は、右端に位置し、当初右端に位置していたエッジ状態は、左端に位置するようになる。このようにして、2つのエッジ状態の交換操作を行うことができる。 (I)
Finally, the edge state initially located at the left end is located at the right end, and the edge state initially located at the right end is located at the left end. In this way, the exchange operation of the two edge states can be performed.
最終的に、当初左端に位置していたエッジ状態は、右端に位置し、当初右端に位置していたエッジ状態は、左端に位置するようになる。このようにして、2つのエッジ状態の交換操作を行うことができる。 (I)
Finally, the edge state initially located at the left end is located at the right end, and the edge state initially located at the right end is located at the left end. In this way, the exchange operation of the two edge states can be performed.
図10は、本実施形態に係る電気回路10においてトポロジカルに自明な相を挟んで隣接する2つのエッジ状態の位置を交換する操作を模式的に示す図である。同図では、直線状に並んだ複数のユニット回路のうちトポロジカル相のユニット回路を比較的太い実線で示し、トポロジカルに自明な相のユニット回路を比較的細い実線で示し、トポロジカル相の両端に現れるエッジ状態(電圧状態)を、ハッチングを入れた丸印で示している。また、ユニット回路を表す実線に重ねて記載された左向きの矢印及び上向きの矢印は、超伝導位相φ=0を表し、ユニット回路を表す実線に重ねて記載された右向きの矢印及び下向きの矢印は、超伝導位相φ=πを表す。
FIG. 10 is a diagram schematically showing an operation of exchanging the positions of two adjacent edge states with a topologically obvious phase in between in the electric circuit 10 according to the present embodiment. In the figure, the topological phase unit circuit is shown by a relatively thick solid line, and the topologically obvious phase unit circuit is shown by a relatively thin solid line among a plurality of linearly arranged unit circuits, and appears at both ends of the topological phase. The edge state (voltage state) is indicated by a hatched circle. Further, the left-pointing arrow and the upward arrow overlaid on the solid line representing the unit circuit represent the superconducting phase φ = 0, and the right-pointing arrow and the down-pointing arrow overlaid on the solid line representing the unit circuit represent the superconducting phase φ = 0. , Represents the superconducting phase φ = π.
(a)
左側に位置するトポロジカル相の右端に現れているエッジ状態を中央に移動させるため、ユニット回路のトポロジカル相操作回路TCS1,TCS2のスイッチをトポロジカルに自明な相の左端側からオンに切り替えていく。 (A)
In order to move the edge state appearing at the right end of the topological phase located on the left side to the center, the switches of the topological phase operation circuits TCS1 and TCS2 of the unit circuit are switched on from the left end side of the topologically trivial phase.
左側に位置するトポロジカル相の右端に現れているエッジ状態を中央に移動させるため、ユニット回路のトポロジカル相操作回路TCS1,TCS2のスイッチをトポロジカルに自明な相の左端側からオンに切り替えていく。 (A)
In order to move the edge state appearing at the right end of the topological phase located on the left side to the center, the switches of the topological phase operation circuits TCS1 and TCS2 of the unit circuit are switched on from the left end side of the topologically trivial phase.
(b)
当初トポロジカルに自明な相の左端に位置していたエッジ状態を中央に移動させた後、T字型分岐の上側に移動させる。 (B)
The edge state, which was initially located at the left end of the topologically trivial phase, is moved to the center and then moved to the upper side of the T-shaped branch.
当初トポロジカルに自明な相の左端に位置していたエッジ状態を中央に移動させた後、T字型分岐の上側に移動させる。 (B)
The edge state, which was initially located at the left end of the topologically trivial phase, is moved to the center and then moved to the upper side of the T-shaped branch.
(c)
右側に位置するトポロジカル相の左端に現れているエッジ状態を中央に移動させるため、ユニット回路のトポロジカル相操作回路TCS1,TCS2のスイッチをトポロジカルに自明な相の右端側からオンに切り替えていく。 (C)
In order to move the edge state appearing at the left end of the topological phase located on the right side to the center, the switches of the topological phase operation circuits TCS1 and TCS2 of the unit circuit are switched on from the right end side of the topologically trivial phase.
右側に位置するトポロジカル相の左端に現れているエッジ状態を中央に移動させるため、ユニット回路のトポロジカル相操作回路TCS1,TCS2のスイッチをトポロジカルに自明な相の右端側からオンに切り替えていく。 (C)
In order to move the edge state appearing at the left end of the topological phase located on the right side to the center, the switches of the topological phase operation circuits TCS1 and TCS2 of the unit circuit are switched on from the right end side of the topologically trivial phase.
(d)
当初トポロジカルに自明な相の右端に位置していたエッジ状態を中央に移動させた後、T字型分岐上側に位置するユニット回路のまとまりの超伝導位相をφ=0からφ=πに変化させる。 (D)
After moving the edge state, which was initially located at the right end of the topologically trivial phase, to the center, the superconducting phase of the unit circuit located above the T-shaped branch is changed from φ = 0 to φ = π. ..
当初トポロジカルに自明な相の右端に位置していたエッジ状態を中央に移動させた後、T字型分岐上側に位置するユニット回路のまとまりの超伝導位相をφ=0からφ=πに変化させる。 (D)
After moving the edge state, which was initially located at the right end of the topologically trivial phase, to the center, the superconducting phase of the unit circuit located above the T-shaped branch is changed from φ = 0 to φ = π. ..
(e)
その後、中央に位置していたエッジ状態を左端に移動させる。 (E)
After that, the edge state located in the center is moved to the left end.
その後、中央に位置していたエッジ状態を左端に移動させる。 (E)
After that, the edge state located in the center is moved to the left end.
(f)
T字型分岐上側に位置するユニット回路のまとまりの端部に移動させたエッジ状態を、中央に移動させる。 (F)
The edge state moved to the end of the unit circuit located above the T-shaped branch is moved to the center.
T字型分岐上側に位置するユニット回路のまとまりの端部に移動させたエッジ状態を、中央に移動させる。 (F)
The edge state moved to the end of the unit circuit located above the T-shaped branch is moved to the center.
(g)
中央に移動させたエッジ状態を、右端に移動させる。 (G)
The edge state moved to the center is moved to the right end.
中央に移動させたエッジ状態を、右端に移動させる。 (G)
The edge state moved to the center is moved to the right end.
(h)
中央に位置していたエッジ状態を右端に移動させた後、T字型分岐上側に位置するユニット回路のまとまりの超伝導位相をφ=πからφ=0に変化させる。 (H)
After moving the edge state located in the center to the right end, the superconducting phase of the unit circuit located above the T-shaped branch is changed from φ = π to φ = 0.
中央に位置していたエッジ状態を右端に移動させた後、T字型分岐上側に位置するユニット回路のまとまりの超伝導位相をφ=πからφ=0に変化させる。 (H)
After moving the edge state located in the center to the right end, the superconducting phase of the unit circuit located above the T-shaped branch is changed from φ = π to φ = 0.
(i)
最終的に、当初左側に位置するトポロジカル相の右端に現れていたエッジ状態は、右側に位置するトポロジカル相の左端に位置し、当初右側に位置するトポロジカル相の左端に現れていたエッジ状態は、左側に位置するトポロジカル相の右端に位置するようになる。このようにして、トポロジカルに自明な相を挟んで隣接する2つのエッジ状態の交換操作を行うことができる。 (I)
Finally, the edge state that initially appeared at the right end of the topological phase located on the left side is located at the left end of the topological phase located on the right side, and the edge state that initially appeared at the left end of the topological phase located on the right side is It will be located at the right end of the topological phase located on the left side. In this way, it is possible to perform an exchange operation of two edge states adjacent to each other with a topologically obvious phase in between.
最終的に、当初左側に位置するトポロジカル相の右端に現れていたエッジ状態は、右側に位置するトポロジカル相の左端に位置し、当初右側に位置するトポロジカル相の左端に現れていたエッジ状態は、左側に位置するトポロジカル相の右端に位置するようになる。このようにして、トポロジカルに自明な相を挟んで隣接する2つのエッジ状態の交換操作を行うことができる。 (I)
Finally, the edge state that initially appeared at the right end of the topological phase located on the left side is located at the left end of the topological phase located on the right side, and the edge state that initially appeared at the left end of the topological phase located on the right side is It will be located at the right end of the topological phase located on the left side. In this way, it is possible to perform an exchange operation of two edge states adjacent to each other with a topologically obvious phase in between.
図11は、本実施形態に係る電気回路10においてトポロジカル相の両端に現れる2つのエッジ状態の位置を交換する操作における波動関数の時間変化を示す図である。同図では、図9に示す(a)から(i)の時間発展に対応するように、波動関数が局在している箇所を示している。なお、波動関数は、本実施形態に係る電気回路10の交流電圧に読み替えられる。そのため、粒子の存在確率は、交流電圧の振幅の2乗に読み替えられる。
FIG. 11 is a diagram showing a time change of a wave function in an operation of exchanging the positions of two edge states appearing at both ends of the topological phase in the electric circuit 10 according to the present embodiment. In the figure, the place where the wave function is localized is shown so as to correspond to the time evolution of (a) to (i) shown in FIG. The wave function can be read as the AC voltage of the electric circuit 10 according to the present embodiment. Therefore, the probability of existence of particles can be read as the square of the amplitude of the AC voltage.
初期状態(a)において、T字型のユニット回路(T junction)の両端に波動関数が局在しており、トポロジカル相の両端にエッジ状態が形成されていることを示している。その後、(b)において右端のエッジ状態が中央に移動し、(c)において中央のエッジ状態がT字型分岐上側に位置するユニット回路のまとまりの端部に移動する。
In the initial state (a), the wave function is localized at both ends of the T-shaped unit circuit (T junction), indicating that the edge state is formed at both ends of the topological phase. After that, in (b), the rightmost edge state moves to the center, and in (c), the central edge state moves to the end of the unit circuit located above the T-shaped branch.
その後、(d)において、左端のエッジ状態が中央に移動し、T字型分岐上側に位置するユニット回路のまとまりの超伝導位相が変更される。(e)において中央に位置していたエッジ状態が右端に移動する。さらに、(f)において、T字型分岐上側に位置するユニット回路のまとまりの端部に位置していたエッジ状態が中央に移動し、(g)において、中央に移動したエッジ状態が左端に移動する。(h)では、T字型分岐上側に位置するユニット回路のまとまりの超伝導位相が変更される。最後に、(i)の状態となり、当初左端に位置していたエッジ状態は、右端に位置し、当初右端に位置していたエッジ状態は、左端に位置するようになる。
After that, in (d), the edge state at the left end moves to the center, and the superconducting phase of the unit circuit located above the T-shaped branch is changed. The edge state located at the center in (e) moves to the right end. Further, in (f), the edge state located at the end of the unit circuit located above the T-shaped branch moves to the center, and in (g), the edge state moved to the center moves to the left end. To do. In (h), the superconducting phase of the unit circuit located above the T-shaped branch is changed. Finally, in the state (i), the edge state initially located at the left end is located at the right end, and the edge state initially located at the right end is located at the left end.
図12は、本実施形態に係る電気回路10においてトポロジカル相の両端に現れる2つのエッジ状態の位置を交換する操作におけるエネルギー固有値とベリー位相の時間変化を示す図である。同図では、図9に示す(a)から(i)の時間発展に対応するように、エネルギー固有値とベリー位相の時間変化を示している。なお、エネルギー固有値は、本実施形態に係る電気回路10のアドミッタンスに読み替えられ、ベリー位相は、交流電圧の位相に読み替えられる。
FIG. 12 is a diagram showing the time change of the energy eigenvalue and the Berry phase in the operation of exchanging the positions of the two edge states appearing at both ends of the topological phase in the electric circuit 10 according to the present embodiment. In the figure, the time variation of the energy eigenvalue and the Berry phase is shown so as to correspond to the time evolution of (a) to (i) shown in FIG. The energy eigenvalue is read as the admittance of the electric circuit 10 according to the present embodiment, and the Berry phase is read as the phase of the AC voltage.
(a)から(i)の操作を行う場合に、エネルギー固有値が正の状態は正のまま、エネルギー固有値が負の状態は負のまま変化している。すなわち、ギャップモードのエネルギーがゼロとなることはなく、ギャップレスのエッジ状態は、ブレイド操作によってバルクのギャップモードと混ざることがない。
When the operations (a) to (i) are performed, the state where the energy eigenvalue is positive remains positive, and the state where the energy eigenvalue is negative remains negative. That is, the energy of the gap mode is never zero, and the gapless edge state is not mixed with the bulk gap mode by the blade operation.
また、ベリー位相は、(d)から(e)の操作で0からπ/2に変化している。すなわち、(a)から(i)の操作によってトポロジカル相の両端に現れているエッジ状態の位置を交換すると、eiπ/2の位相が生じる。このことは、エッジ状態が非可換エニオンとなっていることを意味する。また、(a)から(i)の操作によって、iσxに相当する量子ゲートが実現できることを意味する。なお、ベリー位相は断熱近似に基づくため、(a)から(i)の操作は、交流周波数ωより十分遅い速度で行う必要がある。
Further, the Berry phase is changed from 0 to π / 2 by the operation from (d) to (e). That is, when the positions of the edge states appearing at both ends of the topological phase are exchanged by the operations (a) to (i), the phase of e iπ / 2 is generated. This means that the edge state is non-commutative anyon. It also means that a quantum gate corresponding to iσ x can be realized by the operations (a) to (i). Since the Berry phase is based on the adiabatic approximation, the operations (a) to (i) need to be performed at a speed sufficiently slower than the AC frequency ω.
(a)から(i)の操作を2回続けて行うと、2つのエッジ状態の位置が元に戻る。しかしながら、ベリー位相はeiπ=-1となり、状態の位相が反転する。このようなエニオンは、イジングエニオンと呼ばれており、トポロジカル量子計算の基本的構成要素として知られている。
When the operations (a) to (i) are performed twice in succession, the positions of the two edge states are restored. However, the Berry phase becomes e iπ = -1, and the phase of the state is inverted. Such anyon is called Ising enion and is known as a basic component of topological quantum computing.
(a)から(i)の操作を、隣接するエッジ状態j及びエッジ状態j+1を交換するブレイド操作Uj,j+1と表すとき、以下の数式(3)で表される3つのブレイド関係式を全て満たす。
When the operations (a) to (i) are expressed as blade operations U j, j + 1 that exchange adjacent edge states j and edge states j + 1, all three blade relational expressions represented by the following mathematical formula (3) are used. Fulfill.
このように、本実施形態に係る電気回路10によれば、トポロジカルに安定なエッジ状態のブレイド操作による量子計算と同等の計算を行うことができる。また、現実の電気回路を構成する素子にある程度の乱雑さや熱雑音があって、回路ラプラシアンにノイズが含まれたとしても、エッジ状態は摂動に対して安定であるから、トポロジカル量子計算と同等の計算ができることに変わりない。
As described above, according to the electric circuit 10 according to the present embodiment, it is possible to perform a calculation equivalent to a quantum calculation by a blade operation in a topologically stable edge state. In addition, even if the elements that make up an actual electric circuit have some degree of messiness and thermal noise and the circuit Laplacian contains noise, the edge state is stable with respect to perturbations, so it is equivalent to topological quantum calculation. It is still possible to calculate.
図13は、本実施形態に係る電気回路10において異なるトポロジカル相の両端現れるエッジ状態の位置を交換する操作を模式的に示す図である。同図では、十字型の分岐を含んで格子状に並んだ複数のユニット回路のうちトポロジカル相のユニット回路を比較的太い実線で示し、トポロジカルに自明な相のユニット回路を比較的細い実線で示し、トポロジカル相の両端に現れるエッジ状態(電圧状態)を、ハッチングを入れた丸印で示している。また、ユニット回路を表す実線に重ねて記載された左向きの矢印及び上向きの矢印は、超伝導位相φ=0を表し、ユニット回路を表す実線に重ねて記載された右向きの矢印及び下向きの矢印は、超伝導位相φ=πを表す。同図では、交換対象である2つのエッジ状態に符号A及びBを付している。第1エッジ状態Aは、トポロジカル相の左端に位置するエッジ状態であり、第2エッジ状態Bは、異なるトポロジカル相の右端に位置するエッジ状態である。
FIG. 13 is a diagram schematically showing an operation of exchanging the positions of the edge states appearing at both ends of different topological phases in the electric circuit 10 according to the present embodiment. In the figure, the topological phase unit circuit is shown by a relatively thick solid line, and the topologically obvious phase unit circuit is shown by a relatively thin solid line among a plurality of unit circuits arranged in a grid pattern including a cross-shaped branch. , The edge states (voltage states) that appear at both ends of the topological phase are indicated by hatched circles. Further, the left-pointing arrow and the upward arrow overlaid on the solid line representing the unit circuit represent the superconducting phase φ = 0, and the right-pointing arrow and the down-pointing arrow overlaid on the solid line representing the unit circuit represent the superconducting phase φ = 0. , Represents the superconducting phase φ = π. In the figure, reference numerals A and B are attached to the two edge states to be exchanged. The first edge state A is an edge state located at the left end of the topological phase, and the second edge state B is an edge state located at the right end of a different topological phase.
本例の複数のユニット回路は、分岐接続を含み、十字型に接続されている。以下に説明するように、このような構成によって、異なるトポロジカル相の両端に現れる2つのエッジ状態の位置を交換する操作を実現することができる。
The plurality of unit circuits in this example include a branch connection and are connected in a cross shape. As described below, such a configuration can realize an operation of exchanging the positions of two edge states appearing at both ends of different topological phases.
(a)
はじめに、第1エッジ状態A及びその対となるエッジ状態を、十字型分岐の上側に移動させるとともに、第2エッジ状態B及びその対となるエッジ状態を、十字型分岐の下側に移動させ、(b)の状態とする。 (A)
First, the first edge state A and its paired edge state are moved to the upper side of the cross-shaped branch, and the second edge state B and its paired edge state are moved to the lower side of the cross-shaped branch. The state of (b) is assumed.
はじめに、第1エッジ状態A及びその対となるエッジ状態を、十字型分岐の上側に移動させるとともに、第2エッジ状態B及びその対となるエッジ状態を、十字型分岐の下側に移動させ、(b)の状態とする。 (A)
First, the first edge state A and its paired edge state are moved to the upper side of the cross-shaped branch, and the second edge state B and its paired edge state are moved to the lower side of the cross-shaped branch. The state of (b) is assumed.
(b)
第1エッジ状態A及び第2エッジ状態Bのいずれか一方を十字型分岐の左側又は右側に退避させ、第1エッジ状態A及び第2エッジ状態Bの位置を交換し、(c)の状態とする。 (B)
Either one of the first edge state A and the second edge state B is retracted to the left side or the right side of the cross-shaped branch, and the positions of the first edge state A and the second edge state B are exchanged with the state of (c). To do.
第1エッジ状態A及び第2エッジ状態Bのいずれか一方を十字型分岐の左側又は右側に退避させ、第1エッジ状態A及び第2エッジ状態Bの位置を交換し、(c)の状態とする。 (B)
Either one of the first edge state A and the second edge state B is retracted to the left side or the right side of the cross-shaped branch, and the positions of the first edge state A and the second edge state B are exchanged with the state of (c). To do.
(c)
十字型分岐の下側に位置する第1エッジ状態A及びその対となるエッジ状態を、当初第2エッジ状態Bが位置していた箇所に移動させるとともに、十字型分岐の上側に位置する第2エッジ状態B及びその対となるエッジ状態を、当初第1エッジ状態Aが位置していた箇所に移動させ、(d)の状態とする。 (C)
The first edge state A located below the cross-shaped branch and its paired edge state are moved to the location where the second edge state B was initially located, and the second edge state located above the cross-shaped branch is located. The edge state B and its paired edge state are moved to the position where the first edge state A was initially located to be in the state (d).
十字型分岐の下側に位置する第1エッジ状態A及びその対となるエッジ状態を、当初第2エッジ状態Bが位置していた箇所に移動させるとともに、十字型分岐の上側に位置する第2エッジ状態B及びその対となるエッジ状態を、当初第1エッジ状態Aが位置していた箇所に移動させ、(d)の状態とする。 (C)
The first edge state A located below the cross-shaped branch and its paired edge state are moved to the location where the second edge state B was initially located, and the second edge state located above the cross-shaped branch is located. The edge state B and its paired edge state are moved to the position where the first edge state A was initially located to be in the state (d).
(d)
最終的に、当初上側に位置するトポロジカル相の左端に現れていた第1エッジ状態Aは、下側に位置するトポロジカル相の右端に位置し、当初下側に位置するトポロジカル相の右端に現れていた第2エッジ状態Bは、上側に位置するトポロジカル相の左端に位置するようになる。このようにして、異なるトポロジカル相の両端に現れているエッジ状態の交換操作を行うことができる。 (D)
Finally, the first edge state A, which initially appeared at the left end of the topological phase located at the upper side, is located at the right end of the topological phase located at the lower side and appears at the right end of the topological phase located at the lower side at the beginning. The second edge state B is located at the left end of the topological phase located on the upper side. In this way, it is possible to perform an edge state exchange operation that appears at both ends of different topological phases.
最終的に、当初上側に位置するトポロジカル相の左端に現れていた第1エッジ状態Aは、下側に位置するトポロジカル相の右端に位置し、当初下側に位置するトポロジカル相の右端に現れていた第2エッジ状態Bは、上側に位置するトポロジカル相の左端に位置するようになる。このようにして、異なるトポロジカル相の両端に現れているエッジ状態の交換操作を行うことができる。 (D)
Finally, the first edge state A, which initially appeared at the left end of the topological phase located at the upper side, is located at the right end of the topological phase located at the lower side and appears at the right end of the topological phase located at the lower side at the beginning. The second edge state B is located at the left end of the topological phase located on the upper side. In this way, it is possible to perform an edge state exchange operation that appears at both ends of different topological phases.
以上説明した実施形態は、本発明の理解を容易にするためのものであり、本発明を限定して解釈するためのものではない。実施形態が備える各要素並びにその配置、材料、条件、形状及びサイズ等は、例示したものに限定されるわけではなく適宜変更することができる。また、異なる実施形態で示した構成同士を部分的に置換し又は組み合わせることが可能である。
The embodiments described above are for facilitating the understanding of the present invention, and are not for limiting and interpreting the present invention. Each element included in the embodiment and its arrangement, material, condition, shape, size, and the like are not limited to those exemplified, and can be changed as appropriate. In addition, the configurations shown in different embodiments can be partially replaced or combined.
10…電気回路、E1,E2…第1回路、H1,H2…第2回路、OP…オペアンプ、PCS…位相操作回路、TCS…トポロジカル相操作回路、U1,U2…ユニット回路、R…LC共振器(記憶回路)
10 ... Electric circuit, E1, E2 ... 1st circuit, H1, H2 ... 2nd circuit, OP ... Operator, PCS ... Phase operation circuit, TCS ... Topological phase operation circuit, U1, U2 ... Unit circuit, R ... LC resonator (Memory circuit)
10 ... Electric circuit, E1, E2 ... 1st circuit, H1, H2 ... 2nd circuit, OP ... Operator, PCS ... Phase operation circuit, TCS ... Topological phase operation circuit, U1, U2 ... Unit circuit, R ... LC resonator (Memory circuit)
Claims (8)
- 少なくとも4つの端点及びインピーダンスが調整可能なトポロジカル相操作回路をそれぞれ含む複数のユニット回路を備え、
前記4つの端点のうちいずれかの端点の交流電流と、当該端点に隣接する端点の交流電圧との比例関係を表す回路ラプラシアンが、量子系のハミルトニアンに対応するように構成され、
前記トポロジカル相操作回路の前記インピーダンスは、前記ハミルトニアンに含まれるパラメータに対応し、
前記ハミルトニアンは、前記パラメータに関する所定の領域でトポロジカル相を有する、
電気回路。 It has multiple unit circuits, each containing at least four endpoints and a topological phase manipulation circuit with adjustable impedance.
The circuit Laplacian, which represents the proportional relationship between the AC current at one of the four endpoints and the AC voltage at the endpoint adjacent to the endpoint, is configured to correspond to the Hamiltonian of the quantum system.
The impedance of the topological phase operation circuit corresponds to the parameters contained in the Hamiltonian.
The Hamiltonian has a topological phase in a predetermined region with respect to the parameter.
electric circuit. - 前記複数のユニット回路は、電子バンドに対応する第1回路及びホールバンドに対応する第2回路をそれぞれ含み、
前記第1回路の交流電圧の位相及び前記第2回路の交流電圧の位相は、互いに逆である、
請求項1に記載の電気回路。 The plurality of unit circuits include a first circuit corresponding to an electronic band and a second circuit corresponding to a hole band, respectively.
The phase of the AC voltage of the first circuit and the phase of the AC voltage of the second circuit are opposite to each other.
The electric circuit according to claim 1. - 前記複数のユニット回路は、前記第1回路及び前記第2回路を接続し、交流電圧の位相を変化させる位相操作回路をそれぞれ含む、
請求項2に記載の電気回路。 The plurality of unit circuits include a phase operation circuit that connects the first circuit and the second circuit and changes the phase of the AC voltage.
The electric circuit according to claim 2. - 前記トポロジカル相操作回路は、前記第1回路又は前記第2回路とグランドとを接続し、前記インピーダンスを切り替えるスイッチを含む、
請求項1から3のいずれか一項に記載の電気回路。 The topological phase operation circuit includes a switch that connects the first circuit or the second circuit to the ground and switches the impedance.
The electric circuit according to any one of claims 1 to 3. - 前記複数のユニット回路は、分岐接続を含み、T字型に接続されている、
請求項1から4のいずれか一項に記載の電気回路。 The plurality of unit circuits include a branch connection and are connected in a T shape.
The electric circuit according to any one of claims 1 to 4. - 前記複数のユニット回路は、分岐接続を含み、十字型に接続されている、
請求項1から4のいずれか一項に記載の電気回路。 The plurality of unit circuits include a branch connection and are connected in a cross shape.
The electric circuit according to any one of claims 1 to 4. - 前記ハミルトニアンは、電子-ホール対称性を有するBogoliubov-de Gennes形式で記述される超伝導体のハミルトニアン、又は、カイラル対称性を有するハミルトニアンである、
請求項1から6のいずれか一項に記載の電気回路。 The Hamiltonian is a superconductor Hamiltonian described in the Bogoliubov-de Gennes form having electron-hole symmetry, or a Hamiltonian having chiral symmetry.
The electric circuit according to any one of claims 1 to 6. - 前記複数のユニット回路のうちトポロジカル相に対応するユニット回路と前記複数のユニット回路のうちトポロジカルに自明な相に対応するユニット回路との境界に位置する端点の交流電圧又は前記複数のユニット回路のうち端部に位置するユニット回路の端点の交流電圧は、前記ハミルトニアンのエッジ状態に対応する、
請求項7に記載の電気回路。 Of the plurality of unit circuits, the AC voltage at the end point located at the boundary between the unit circuit corresponding to the topological phase and the unit circuit corresponding to the topologically obvious phase of the plurality of unit circuits, or among the plurality of unit circuits. The AC voltage at the end of the unit circuit located at the end corresponds to the Hamiltonian edge state.
The electric circuit according to claim 7.
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