WO2021163963A1

WO2021163963A1 - Ferroelectric memory and electronic device

Info

Publication number: WO2021163963A1
Application number: PCT/CN2020/076046
Authority: WO
Inventors: 张岩; 杨喜超; 魏侠; 秦健鹰
Original assignee: 华为技术有限公司
Priority date: 2020-02-20
Filing date: 2020-02-20
Publication date: 2021-08-26
Also published as: CN114902416A

Abstract

Provided are a ferroelectric memory (100) and an electronic device. The ferroelectric memory (100) comprises a ferroelectric memory unit (10), a first voltage line (m), and a second voltage line (n), and the ferroelectric memory unit (10) comprises a ferroelectric film layer (101), a first electrode (102), and a second electrode (103); the first electrode (102) is connected to the first voltage line (m), and the second electrode (103) is connected to the second voltage line (n); the first electrode (102) is isolated from the second electrode (103) by the ferroelectric film layer (101); along the thickness direction of the ferroelectric film layer (101), the first electrode (102) comprises a first surface and a second surface, the second electrode (103) comprises a first surface and a second surface, the first surface of the first electrode (102) and the first surface of the second electrode (103) are located on the same side, and the second surface of the first electrode (102) and the second surface of the second electrode (103) are located on the same side; wherein the second surface of the first electrode (102) and the second surface of the second electrode (103) are located on different horizontal planes. As a result, the electrical conductivity of the electric domain wall (104) formed by the ferroelectric film layer (101) between the first electrode (102) and the second electrode (103) can be strengthened, thereby improving the read/write speed of the ferroelectric memory (100).

Description

Ferroelectric memory and electronic equipment

Technical field

The embodiments of the present application relate to the field of data storage, and in particular to ferroelectric memories and electronic devices including ferroelectric memories.

Background technique

With the development of electronic technology, data storage technology has been rapidly improved. Among them, the memory manufactured by using ferroelectric materials to change the polarization direction under the action of an electric field is called Ferroelectric Random Access Memory (Ferroelectric Random Access Memory), or also called "ferroelectric memory". Ferroelectric memory has attracted wide attention based on its fast read and write speed and non-volatile characteristics.

Under the action of an electric field, when two regions of a ferroelectric material have different polarization directions, a ferroelectric domain wall is formed. The two regions are ferroelectric domains; when the ferroelectric material has the same polarization direction, the iron The electrical domain wall disappears. In some ferroelectric materials, ferroelectric domain walls are usually conductive. Ferroelectric memory can store data as logic information ("0" and "1") based on the generation and disappearance of ferroelectric domain walls. The conductivity of the ferroelectric domain wall affects the read and write speed of the formed ferroelectric memory.

In related technologies, specific structures (such as read electrode pair and write electrode pair separated structure, multiphase domain structure, electrode symmetrical structure) are usually used to combine electrodes with ferroelectric materials to form ferroelectric memory to realize the polarization of ferroelectric materials. Reverse. The conductivity of the ferroelectric domain wall is usually related to the electric field direction and the polarization direction of the ferroelectric material. The electric field direction of the above-mentioned specific structure is usually fixed, and the ferroelectric domain wall can only be changed by setting the initial polarization direction of the ferroelectric material. Conductivity. In this way, the conductivity of the ferroelectric domain wall is limited to a certain range. When ferroelectric memory needs to be used in ultra-low power consumption scenarios, it is usually difficult to implement. Therefore, how to flexibly change the conductivity of the ferroelectric domain wall generated in the ferroelectric material becomes a problem.

Summary of the invention

In the ferroelectric memory cell and the ferroelectric memory provided in the present application, by arranging the two electrodes of the electrode unit in the ferroelectric memory cell on different horizontal planes, the extension direction of the formed ferroelectric domain wall can have an inclination angle and avoid The extension direction of the ferroelectric domain wall and the polarization direction of the ferroelectric material are on the same straight line, which improves the conductivity of the ferroelectric domain wall.

In order to achieve the above objectives, this application adopts the following technical solutions:

In a first aspect, an embodiment of the present application provides a ferroelectric memory. The ferroelectric memory includes a ferroelectric storage unit, a plurality of first voltage lines, and a plurality of second voltage lines. Line is connected to one of the second voltage lines, the ferroelectric memory cell includes a ferroelectric thin film layer, a first electrode, and a second electrode; the first electrode is connected to the first voltage line, and the second electrode is connected to The second voltage line is connected; the first electrode and the second electrode are separated by the ferroelectric thin film layer; along the thickness direction of the ferroelectric thin film layer, the first electrode includes a first electrode A surface and a second surface. The second electrode includes a first surface and a second surface. The first surface of the first electrode and the first surface of the second electrode are located on the same side. The second surface and the second surface of the two electrodes are located on the same side; wherein, the second surface of the first electrode and the second surface of the second electrode are located on different horizontal planes.

Here, the first surface and the second surface of the first electrode may be the upper surface and the lower surface respectively, or may be the lower surface and the upper surface respectively; similarly, the first surface and the second surface of the second electrode may be the upper surface respectively And the lower surface can also be the lower surface and the upper surface, respectively.

Generally, when the extension direction of the domain wall formed by the polarization reversal of the ferroelectric material is parallel to the initial polarization direction of the ferroelectric material, the conductivity of the domain wall is the smallest. As the angle between the two increases, the conductivity The rate gradually increases. In this implementation, by setting at least one surface of the first electrode and at least one surface of the second electrode on different horizontal planes, when a voltage is applied between the first electrode and the second electrode to form a ferroelectric domain wall, it is possible to make The formed ferroelectric domain wall has a certain inclination angle. At this time, the initial polarization direction of the ferroelectric material can be multiple directions (for example, horizontal direction, vertical direction, etc.), and the conductivity of the ferroelectric domain wall can be flexibly changed. In addition, the extension direction of the ferroelectric domain wall and the polarization direction of the ferroelectric material can be avoided to be on the same straight line, and the conductivity of the ferroelectric domain wall can be further improved. In this way, data can be written to or read from the ferroelectric memory cell quickly, and the read and write speed of the ferroelectric memory is improved.

In a possible implementation manner, the ferroelectric thin film layer includes a first surface, and the first surface of the ferroelectric thin film layer and the first surface of the first electrode are located on the same side; along the ferroelectric thin film In the layer thickness direction, the first electrode and the second electrode respectively extend from the first surface of the ferroelectric thin film layer to the inside of the ferroelectric thin film layer; the first electrode faces the inside of the ferroelectric thin film layer The extension depth is different from the extension depth of the second electrode into the ferroelectric thin film layer.

In this implementation, the first surface of the ferroelectric thin film layer may be the upper surface or the lower surface.

The above-mentioned first surface of the first electrode and the first surface of the second electrode are on the same side means that they are both located on the side away from the second surface of the ferroelectric thin film layer, the second surface of the first electrode and the second surface of the second electrode Being on the same side means that they are all located on the side close to the second surface of the ferroelectric thin film layer.

In a possible implementation, when the depth that the first electrode extends into the ferroelectric thin film layer is different from the depth that the second electrode extends into the ferroelectric thin film layer, the first electrode The first surface of the electrode, the first surface of the second electrode and the first surface of the ferroelectric thin film layer are located on the same horizontal plane.

In a possible implementation, when the depth that the first electrode extends into the ferroelectric thin film layer is different from the depth that the second electrode extends into the ferroelectric thin film layer, the first electrode The first surface of the electrode and the first surface of the second electrode are located on different horizontal planes, and the first surface of the ferroelectric thin film layer is directed from the first surface of the electrode to the first surface of the second electrode Incline.

In a possible implementation, when the depth that the first electrode extends into the ferroelectric thin film layer is different from the depth that the second electrode extends into the ferroelectric thin film layer, the first electrode The first surface of the electrode and the first surface of the second electrode are located on different horizontal planes, and the first surface of the second electrode and the first surface of the ferroelectric thin film layer are located on the same horizontal plane; wherein, the first electrode The first surface of the second electrode is lower than the first surface of the second electrode.

In this implementation, by arranging the first surface of the second electrode and the first surface of the ferroelectric thin film layer on the same horizontal plane, the first surface of the first electrode and the first surface of the second electrode are arranged on different horizontal planes, By applying a voltage between the first electrode and the second electrode to reverse the polarization of the ferroelectric material between the two, two electrical domain walls (such as the

double domain walls

104 and 105 shown in FIG. 10) can be formed. This can meet the needs of multiple electrical domain wall scenarios.

In a possible implementation manner, an insulating layer may be deposited on the first surface of the first electrode, and the insulating layer includes a first surface away from the first electrode; wherein the first surface of the insulating layer The surface is located on the same horizontal plane as the first surface of the ferroelectric thin film layer.

In a possible implementation manner, along the thickness direction of the ferroelectric thin film layer, the first electrode extends from the first surface of the ferroelectric thin film layer to the inside of the ferroelectric thin film layer, and the second electrode Deposited on the first surface of the ferroelectric thin film layer.

In this implementation manner, by depositing the second electrode on the first surface of the ferroelectric thin film layer, which is equivalent to being externally hung on the outside of the ferroelectric thin film layer, the position of the second electrode can be flexibly adjusted. In this way, the relative position between the first electrode and the second electrode can be adjusted to adjust the inclination angle of the electric domain wall of the ferroelectric thin film layer between the first electrode and the second electrode. The magnitude of the current read by the voltage line m or the voltage line n improves the flexibility of current reading.

In a possible implementation manner, along the thickness direction of the ferroelectric thin film layer, the first electrode penetrates the first surface and the second surface of the ferroelectric thin film layer.

In this implementation, by penetrating the first electrode through the first surface and the second surface of the ferroelectric thin film layer, when the ferroelectric memory cell needs to be connected with the components arranged in the lower layer of the ferroelectric memory cell or with the components arranged in the ferroelectric memory cell When the upper-layer components are connected, the first electrode can be directly connected with the upper-layer components or the lower-layer components provided on the ferroelectric memory cell, and it is not necessary to perforate the ferroelectric film layer to provide the first electrode. Lead wires connected with other components, thereby effectively reducing the size of the ferroelectric memory cell and improving the storage density of the ferroelectric memory. In addition, it can also make the ferroelectric memory easier to integrate.

In a possible implementation manner, along the thickness direction of the ferroelectric thin film layer, the cross-sectional shape of the first electrode and/or the second electrode includes one of the following: a trapezoid and a rectangle.

In a possible implementation manner, the ferroelectric memory includes a plurality of ferroelectric memory cells, and the plurality of ferroelectric memory cells are arranged in an array; wherein, a plurality of the ferroelectric memory cells arranged in the same row or the same column are arranged in an array; The electric storage unit multiplexes the same first electrode.

In a possible implementation manner, the material forming the ferroelectric thin film layer is a single crystal material; the ferroelectric thin film materials forming the ferroelectric thin film layer have the same initial polarization direction.

Specifically, the aforementioned single crystal materials include, but are not limited to: lithium niobate, doped lithium niobate, lithium tantalate, doped lithium tantalate, bismuth ferrite, doped bismuth ferrite, lead zirconium titanate, Doped lead zirconium titanate, barium titanate, doped barium titanate, strontium tantalate, doped strontium tantalate, strontium bismuth tantalate, or doped strontium bismuth tantalate. Wherein, the doped lithium niobate or doped lithium tantalate dopants include at least one of the following: magnesium oxide (MgO), iron (Fe), manganese (Mn), erbium (Er), or titanium (Ti) ).

Specifically, the concentration range of lithium niobate or lithium tantalate doped with MgO is 0-10 mol%.

In a second aspect, an embodiment of the present application provides an electronic device, including the ferroelectric memory described in any implementation manner of the first aspect.

Description of the drawings

In order to explain the technical solutions of the embodiments of the present application more clearly, the following will briefly introduce the drawings that need to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative labor.

FIG. 1 is a schematic diagram of a structure of a ferroelectric memory provided by an embodiment of the present application;

2 is a top view of a ferroelectric memory cell array provided by an embodiment of the present application;

FIG. 3 is a cross-sectional view of a ferroelectric storage unit provided by an embodiment of the present application;

4 is a cross-sectional view of another ferroelectric storage unit provided by an embodiment of the present application;

5 is a cross-sectional view of another ferroelectric storage unit provided by an embodiment of the present application;

FIG. 6 is a cross-sectional view of another ferroelectric storage unit provided by an embodiment of the present application;

FIG. 7 is a cross-sectional view of another ferroelectric storage unit provided by an embodiment of the present application;

FIG. 8 is a cross-sectional view of another ferroelectric storage unit provided by an embodiment of the present application;

FIG. 9 is a cross-sectional view of another ferroelectric storage unit provided by an embodiment of the present application;

10 is a cross-sectional view of another ferroelectric storage unit provided by an embodiment of the present application;

FIG. 11 is a cross-sectional view of another ferroelectric storage unit provided by an embodiment of the present application;

12 is a cross-sectional view of another ferroelectric storage unit provided by an embodiment of the present application;

FIG. 13 is a cross-sectional view of another ferroelectric storage unit provided by an embodiment of the present application;

14 is a cross-sectional view of another ferroelectric storage unit provided by an embodiment of the present application;

FIG. 15 is a top view of another ferroelectric memory cell array provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of them. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of this application.

The "first", "second" and similar words mentioned in this article do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one" or "one" do not mean a quantity limit, but mean that there is at least one. Similar words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect, and are equivalent to coupling or communication in a broad sense.

The "module" mentioned in this article generally refers to a functional structure divided logically. The "module" can be implemented by pure hardware, or a combination of software and hardware. In the implementation of this application, "and/or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and/or B, which can mean: A alone exists, A and B exist at the same time, and B exists alone. three conditions.

In the embodiments of the present application, words such as "exemplary" or "for example" are used as examples, illustrations, or illustrations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be construed as being more preferable or advantageous than other embodiments or design solutions. To be precise, words such as "exemplary" or "for example" are used to present related concepts in a specific manner. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "plurality" means two or more. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be described clearly and completely in conjunction with the accompanying drawings in this application. Obviously, the described embodiments are part of the embodiments of this application. , Not all examples. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of this application.

Please refer to FIG. 1, which shows a schematic structural diagram of a ferroelectric memory provided by an embodiment of the present application.

As shown in FIG. 1, the ferroelectric memory 100 includes a plurality of ferroelectric memory cells 10, a plurality of voltage lines m extending in a first direction x, and a plurality of voltage lines n extending in a second direction y. A plurality of ferroelectric memory cells 10 form a ferroelectric memory cell array. Each row of ferroelectric memory cells 10 is connected to one of the voltage lines m and one of the voltage lines n. Alternatively, each column of ferroelectric memory cells 10 is connected to one of the voltage lines m and one of the voltage lines n. The ferroelectric memory 100 also includes a read-write controller. The read-write controller is connected to the voltage line m and the voltage line n.

In addition, the ferroelectric memory 100 further includes a row address line and a column address line. Each row of ferroelectric memory cells 10 is connected to a row address line, and each column of ferroelectric memory cells 10 is connected to a column address line. The row address line is connected to the external row address decoder, and the column address line is connected to the external column address decoder. Since the address selection process of the ferroelectric memory 100 is not the focus of the embodiment of the present application, the row address line and the column address line are not shown in FIG. 1.

With reference to FIG. 1, the working principle of the ferroelectric memory 100 will be described.

When data needs to be written to the ferroelectric memory 100, the processor used to manage the ferroelectric memory 100 controls the row address decoder and the column address decoder to address based on the location where the data is to be stored, and selects the ferroelectric memory to be operated. For the storage unit 10, for example, the ferroelectric storage unit A in FIG. 1 is selected. Then, the read-write controller applies a first voltage between the voltage line m and the voltage line n connected to the ferroelectric memory cell A to control the generation or disappearance of the ferroelectric domain wall in the ferroelectric memory cell A, thereby transferring the ferroelectric Memory cell A writes "logic 0" or "logic 1". Here, the first voltage may be greater than or equal to the voltage required for the polarization reversal of the ferroelectric material. After applying the first voltage to the voltage line m and the voltage line n, the read-write controller can read the current value flowing on the voltage line m or the voltage line n in real time. When the current value is greater than the preset threshold, it means that a ferroelectric domain wall is generated in the ferroelectric memory cell A. At this time, it can be determined to write "logic 1" to the ferroelectric memory cell A; when the current value is less than the preset threshold, it means The ferroelectric domain wall in the ferroelectric memory cell A disappears, and at this time, it can be determined that "logic 0" is stored in the ferroelectric memory cell A.

When it is necessary to read data from the ferroelectric memory 100, the storage location of the data to be read by the processor used to manage the ferroelectric memory 100 controls the row address decoder and the column address decoder to address, and select the desired operation The ferroelectric memory cell 10, for example, the ferroelectric memory cell A in FIG. 1 is selected. Then, the read-write controller applies a second voltage between the voltage line m and the voltage line n connected to the ferroelectric memory cell A. Here, the second voltage may be less than the voltage required for the polarization reversal of the ferroelectric material. After applying the second voltage to the voltage line m and the voltage line n, the read-write controller can read the current value flowing on the voltage line m or the voltage line n in real time. When the current value is greater than the preset threshold, it can be determined that "logic 1" is read from the ferroelectric memory cell A; when the current value is less than the preset threshold, it can be determined that "logic 0" is read from the ferroelectric memory cell A.

The ferroelectric memory cell array 10 in FIG. 1 may be formed by depositing electrodes on a ferroelectric material.

In the following, the first surface of the first electrode 102 is the upper surface, the second surface of the first electrode 102 is the lower surface, the first surface of the second electrode 103 is the upper surface, and the second surface of the second electrode 102 is the upper surface. As an example, the first surface of the ferroelectric thin film layer 101 is the upper surface and the second surface of the ferroelectric thin film layer 101 is the lower surface. The structure and storage principle of 10 are explained in detail.

Please refer to FIG. 2 and FIG. 3. FIG. 2 is another structural diagram of the ferroelectric memory cell array shown in FIG. 1, and FIG. 3 is a cross-sectional view of the ferroelectric memory cell 10 along aa' shown in FIG.

As shown in FIGS. 2 and 3, each ferroelectric memory cell 10 includes a ferroelectric thin film layer 101, a first electrode 102, and a second electrode 103. The first electrode 102 extends from the upper surface of the ferroelectric thin film layer 101 to the inside of the ferroelectric thin film layer 101, and the second electrode 103 also extends from the upper surface of the ferroelectric thin film layer 101 to the inside of the ferroelectric thin film layer 101. The first electrode Ferroelectric material is filled between 102 and the second electrode 103. The depth that the first electrode 102 extends into the ferroelectric thin film layer 101 is different from the depth that the second electrode 103 extends into the ferroelectric thin film layer 101. For example, the depth that the first electrode 102 extends into the ferroelectric thin film layer 101 is greater than the depth that the second electrode 103 extends into the ferroelectric thin film layer 101; or the depth that the second electrode 103 extends into the ferroelectric thin film layer 101 is greater than that of the first electrode 103. The electrode 102 extends to the depth of the ferroelectric thin film layer 101. FIG. 3 schematically shows that the depth of the first electrode 102 extending into the ferroelectric thin film layer 101 is greater than the depth of the second electrode 103 extending into the ferroelectric thin film layer 101. It can be seen from FIG. 3 that neither the first electrode 102 nor the second electrode 103 extends to the bottom of the ferroelectric thin film layer 101.

In this embodiment, the material forming the ferroelectric thin film layer 101 may be a single crystal material, including but not limited to: lithium niobate, blackened lithium niobate, doped lithium niobate, lithium tantalate, blackened tantalum Lithium oxide, doped lithium tantalate, bismuth ferrite, doped bismuth ferrite, lead zirconium titanate, doped lead zirconium titanate, barium titanate, doped barium titanate, strontium tantalate, doped Mixed strontium tantalate, doped strontium tantalate, strontium bismuth tantalate, doped strontium bismuth tantalate. Among them, the dopant doped with lithium niobate or doped with lithium tantalate includes one or more of MgO (magnesium oxide), Fe (iron), Mn (manganese), Er (erbium), Ti (titanium), etc. kind. Specifically, the concentration range of lithium niobate or lithium tantalate doped with MgO is 0-10 mol%.

In this embodiment, the thickness of the ferroelectric thin film layer 101 ranges from 1 nm to 10 um. Preferably, the thickness of the ferroelectric thin film layer 101 ranges from 1 nm to 300 nm.

In this embodiment, the material for forming the first electrode 102 and the material for forming the second electrode 103 include, but are not limited to: Pt (platinum), Al (aluminum), Cr (chromium), Ti (titanium), Au ( Gold), Cu (copper), W (tungsten), TiN (titanium nitride), polysilicon, a compound of silicon and metal, SrRuO ₃ (strontium ruthenate), Nb:SrTiO ₃ (strontium titanate doped with niobium), One or more of Nb ₂ O ₅ (niobium oxide), Ni (nickel), Co (cobalt), Ru (ruthenium), RuO ₂ (ruthenium dioxide), Ir (iridium), IrO ₂ (iridium dioxide) Kind of stacking.

It can be seen from FIG. 2 that the first electrode 102 and the second electrode 103 in each ferroelectric memory cell 10 are independently arranged.

In this embodiment, the first electrode 102 is connected to the first voltage line m, and the second electrode 103 is connected to the second voltage line n. Hereinafter, taking FIG. 3 as an example, the working principle of the ferroelectric storage unit 10 shown in the embodiment of the present application will be described.

Before writing data to the ferroelectric memory cell 10, the initial polarization direction of the ferroelectric material between the first electrode 102 and the second electrode 103 is P1 (for example, left, right, up, down, etc.). 3 schematically shows that the initial polarization direction of the ferroelectric material between the first electrode 102 and the second electrode 103 is to the left.

A voltage is applied between the first electrode 102 and the second electrode 103 through the voltage line m and the voltage line n. For example, the first electrode 102 can be a positive potential, and the second electrode 103 can be a common ground. At this time, an electric field is formed between the first electrode 102 and the second electrode 103, wherein the direction of the electric field is directed from the first electrode 102 to the second electrode 103. The electric field generates an electric field component in a direction opposite to the polarization direction P1 of the ferroelectric material. When the electric field component reaches a certain intensity, the polarization of the ferroelectric material located between the first electrode 102 and the second electrode 103 is reversed under the action of the electric field, and its polarization direction is P2 (also That is, horizontally to the right). An electrical domain wall 104 as shown in FIG. 4 is formed between the ferroelectric material whose polarization direction has not been reversed and the ferroelectric material whose polarization direction has been reversed.

Generally, the extension direction of the formed electric domain wall 104 is the same as the direction of the electric field. The electrical domain wall 104 has conductivity, and its electrical conductivity is determined by the angle between the extension direction of the electrical domain wall 104 and the polarization direction of the ferroelectric material. When the extension direction of the electric domain wall 104 is parallel to the polarization direction of the ferroelectric material, the electric conductivity of the electric domain wall 104 is the smallest. As the angle between the two increases, the electric conductivity gradually increases. Therefore, the electrical conductivity of the electrical domain wall 104 is related to the direction of the electric field and the polarization direction of the ferroelectric material. When the positions of the first electrode and the second electrode are determined, the direction of the electric field is usually also fixed. In this way, the conductivity of the ferroelectric domain wall can only be changed by setting the initial polarization direction of the ferroelectric material. The initial polarization direction of the ferroelectric material is usually limited by the cutting process, which makes it impossible to flexibly control the above-mentioned included angle.

In this embodiment, since the first electrode 102 and the second electrode 103 extend to the ferroelectric thin film layer 101 at different depths, the electric field between the first electrode 102 and the second electrode 103 does not follow the first electrode 102 and the second electrode 103 shown in FIG. The direction x, but has a certain angle of inclination. Therefore, by using the first electrode 102 and the second electrode 103 with different depths extending on the ferroelectric thin film layer 101, the electric domain wall 104 with a certain inclination angle as shown in FIG. 4 can be formed. When the electric domain wall 104 has a certain inclination angle, the initial polarization direction of the ferroelectric material can be in multiple directions (for example, horizontal direction, vertical direction, etc.), which can reduce the requirements for the cutting process of the ferroelectric material. Therefore, the conductivity of the electrical domain wall 104 can be flexibly changed according to the requirements of the application scenario, so as to meet the requirements of scenarios such as low power consumption. In addition, the electrical conductivity of the electrical domain wall 104 can be increased more easily. Therefore, data can be written to or read from the storage unit 10 quickly, and the read and write speed of the ferroelectric memory can be improved.

It should be noted here that the embodiments of the present application do not limit the initial polarization direction of the ferroelectric material, as long as the initial polarization direction of the ferroelectric material is not perpendicular to the direction of the electric field formed between the first electrode and the second electrode. . It should also be noted that the ferroelectric thin film materials shown in the embodiments of the present application are single crystal materials, and the initial polarization directions of the ferroelectric thin film materials are all the same, that is, the ferroelectric thin film materials are single-phase domain materials.

In the case where the initial polarization direction P1 of the ferroelectric material shown in FIG. 3 is to the left, when writing data to the ferroelectric memory cell, a first voltage is applied between the first electrode 102 and the second electrode 103, resulting in The first electrode 102 is directed to the electric field of the second electrode 103. The applied first voltage is greater than the coercive voltage of the ferroelectric material between the first electrode 102 and the second electrode 103 (that is, the minimum voltage corresponding to the electric field that causes the polarization of the ferroelectric material to be reversed). At this time, the polarization of the ferroelectric material located between the first electrode 102 and the second electrode 103 is reversed, and an electrical domain wall 104 is formed at the boundary between the polarization-reversed ferroelectric material and the non-polarization-reversed ferroelectric material. ,As shown in Figure 4. The electric domain wall 104 has conductivity. Therefore, the read-write controller shown in FIG. 1 can read from the voltage line m or the voltage line n that the current is greater than a preset threshold (the preset threshold is preset based on the conductivity of the electrical domain wall 104). When the voltage applied between the first electrode 102 and the second electrode 103 is removed, the ferroelectric material in the ferroelectric memory cell 10 maintains the polarization direction shown in FIG. 4, and the electrical domain wall 104 will not disappear. At this time, logic “1” is written to the ferroelectric memory cell 10.

In the case where the polarization direction of the ferroelectric material is shown in FIG. 4, a second voltage is applied between the first electrode 102 and the second electrode 103 to generate an electric field directed from the second electrode 103 to the first electrode 102. At this time, the first electrode 102 can be a common ground, and the second electrode 103 can be a positive potential. The second voltage applied is greater than the coercive voltage of the ferroelectric material located between the first electrode 102 and the second electrode 103. At this time, the polarization of the ferroelectric material between the first electrode 102 and the second electrode 103 is reversed, the electrical domain wall 104 disappears, and the polarization direction of the ferroelectric material returns to the initial position shown in FIG. 3. When the voltage applied between the first electrode 102 and the second electrode 103 is removed, the ferroelectric material in the ferroelectric memory cell 10 maintains the polarization direction shown in FIG. 3. At this time, logic “0” is written to the ferroelectric memory cell 10.

When reading data from the ferroelectric memory cell 10, a third voltage is applied between the first electrode 102 and the second electrode 103 to generate an electric field directed to the second electrode 103 by the first electrode 102. The applied third voltage is less than the coercive voltage of the ferroelectric material located between the first electrode 102 and the second electrode 103. Then, the read-write controller shown in FIG. 1 reads the current value from the voltage line m or the voltage line n. When the current value is greater than or equal to the preset threshold value, it indicates that there is an electric domain wall in the ferroelectric memory cell 10, and a logic "1" can be read from the ferroelectric memory cell 10; when the current value is less than the preset threshold value, it indicates that the ferroelectric memory cell 10 There is no electric domain wall in the ferroelectric thin film of the memory cell 10, and a logic “0” can be read from the ferroelectric memory cell 10.

In this embodiment, when reading data from the ferroelectric memory cell 10, the voltage applied between the first electrode 102 and the second electrode 103 is less than the correction of the ferroelectric material located between the first electrode 102 and the second electrode 103. The coercive voltage, after reading data from the ferroelectric memory cell 10, does not destroy the storage state of the ferroelectric memory cell 10, and there is no need to restore the ferroelectric memory cell 10, thereby improving the access efficiency of the ferroelectric memory.

In some optional implementations of this embodiment, the initial polarization direction P1 of the ferroelectric material may also be along the thickness direction of the ferroelectric thin film layer 101, from the lower surface of the ferroelectric thin film layer 101 to the upper surface, or from the ferroelectric thin film layer 101 to the upper surface. The upper surface of the thin film layer 101 points to the lower surface, and FIG. 5 schematically shows that the initial polarization direction P1 of the ferroelectric material is directed from the lower surface of the ferroelectric thin film layer 101 to the upper surface. At this time, when writing data to the ferroelectric memory cell 10, a fourth voltage is applied between the first electrode 102 and the second electrode 103, and an electric field directed from the second electrode 103 to the first electrode 102 is generated. At this time, the second electrode 103 can be made to have a positive potential and the first electrode 102 can be a common ground. The applied fourth voltage is greater than the coercive voltage of the ferroelectric material between the first electrode 102 and the second electrode 103 (that is, the minimum voltage corresponding to the electric field that causes the polarization of the ferroelectric material to be reversed). At this time, the polarization of the ferroelectric material located between the first electrode 102 and the second electrode 103 is reversed (that is, as shown in FIG. 6, the polarization direction P2 is along the thickness direction of the ferroelectric thin film layer 101, The upper surface of the layer 101 points to the lower surface), and an electric domain wall 104 is formed at the boundary between the ferroelectric material with polarization inversion and the ferroelectric material without polarization inversion, as shown in FIG. 6. At this time, logic “1” is written to the ferroelectric memory cell 10.

In the case where the polarization direction in the ferroelectric material is as shown in FIG. 6, a fifth voltage is applied between the first electrode 102 and the second electrode 103 to generate an electric field directed from the first electrode 102 to the second electrode 103. At this time, the first electrode 102 can be at a positive potential and the second electrode 103 can be a common ground. The applied fifth voltage is greater than the coercive voltage of the ferroelectric material between the first electrode 102 and the second electrode 103. At this time, the polarization of the ferroelectric material between the first electrode 102 and the second electrode 103 is reversed, the electrical domain wall 104 disappears, and the polarization direction of the ferroelectric material returns to the initial position shown in FIG. 5. At this time, logic “0” is written to the ferroelectric memory cell 10.

When reading data from the ferroelectric memory cell 10, a sixth voltage is applied between the first electrode 102 and the second electrode 103 to generate an electric field directed to the first electrode 102 by the second electrode 103. The applied sixth voltage is less than the coercive voltage of the ferroelectric material located between the first electrode 102 and the second electrode 103. Then, the read-write controller shown in FIG. 1 reads the current value from the voltage line m or the voltage line n. When the current value is greater than or equal to the preset threshold value, it indicates that there is an electric domain wall in the ferroelectric memory cell 10, and a logic "1" can be read from the ferroelectric memory cell 10; when the current value is less than the preset threshold value, it indicates that the ferroelectric memory cell 10 There is no electric domain wall in the ferroelectric thin film of the memory cell 10, and a logic “0” can be read from the ferroelectric memory cell 10.

In the implementation of the specific process, when etching the ferroelectric thin film layer to deposit the first electrode 102 and the second electrode 103, there are usually ferroelectric materials that are difficult to etch, which results in the etching of the groove formed by the ferroelectric thin film layer. The groove wall is not vertical, and sometimes the angle between the groove wall and the lower surface may be greater than 90 degrees or less than 90 degrees. Based on this, in some possible implementations of this embodiment, the cross-sectional views of the first electrode 102 and the second electrode 103 along the thickness direction of the ferroelectric thin film layer 101 include but are not limited to trapezoidal, rectangular, pentagonal, and the above-mentioned various shapes. Deformation and so on. As shown in FIG. 7, it shows a case where the cross-sectional view of the first electrode 102 is trapezoidal, and the cross-sectional view of the second electrode 103 is trapezoidal along the thickness direction of the ferroelectric thin film layer 101. In addition, the top-view shape of the first electrode 102 and the second electrode 103 may be a rectangle as shown in FIG. The embodiment of the present application does not specifically limit the shapes of the first electrode 102 and the second electrode 103.

In some alternative implementations, the cross-sectional structure of the ferroelectric memory cell 10 may also be as shown in FIG. 8. In Fig. 8, the upper surface of the ferroelectric thin film layer 101 located between the first electrode 102 and the second electrode 103 has a certain inclination. In other words, the upper surface of the ferroelectric thin film layer 101 has an included angle less than 90 degrees with the horizontal plane and with the vertical plane. In a specific implementation, the location area of the first electrode 102 and the second electrode 103 in the ferroelectric memory cell 10 can be determined first, and then the upper surface of the ferroelectric thin film layer 101 between the two areas can be etched to form the one shown in FIG. 8 The upper surface of the ferroelectric thin film layer 101. In this alternative implementation, the first electrode 102 and the second electrode 103 respectively extend from the upper surface of the ferroelectric thin film layer 101 to the inside of the ferroelectric thin film layer 101. Here, the depth to which the first electrode 102 and the second electrode 103 extend into the ferroelectric thin film layer 101 may be the same. In other words, in this alternative implementation, the upper and lower surfaces of the first electrode 102 and the second electrode 103 are both located in different horizontal planes, and the size and shape of the first electrode 102 and the second electrode 103 can be the same. , Can also be different. At this time, when a voltage is applied between the first electrode 102 and the second electrode 103, an electric domain wall with a gradient can also be formed. The data reading and writing method of the ferroelectric storage unit 10 shown in FIG. 8 can refer to the related description of the data reading and writing method of the ferroelectric storage unit 10 shown in FIGS. 3 to 4 or the ferroelectric storage unit 10 shown in FIGS. The description of the data reading method of the storage unit 10 will not be repeated here.

Please continue to refer to FIG. 9, which shows a schematic structural diagram of the ferroelectric memory cell 10 shown in FIG. 2 provided by an embodiment of the present application. Cutaway view.

In FIG. 9, each ferroelectric memory cell 10 includes a ferroelectric thin film layer 101, and a first electrode 102 and a second electrode 103 formed on the ferroelectric thin film layer 101. The first electrode 102 and the second electrode 103 extend from the upper surface of the ferroelectric thin film layer 101 to the inside of the ferroelectric thin film layer 101, but do not penetrate the upper and lower surfaces of the ferroelectric thin film layer 101. It can be seen from FIG. 9 that the upper surface of the first electrode 102 and the upper surface of the second electrode 103 are located on different horizontal planes. However, unlike the ferroelectric memory cell 10 shown in FIG. 8, in FIG. 9, the upper surface of the ferroelectric thin film layer 101 is horizontal or approximately horizontal, and the upper surface of the first electrode 102 is lower than that of the ferroelectric thin film layer 101. On the upper surface, the upper surface of the second electrode 103 and the upper surface of the ferroelectric thin film layer 101 are located in the same horizontal plane. In the specific process, the location area of the first electrode 102 and the second electrode 103 on the ferroelectric thin film layer 101 can be determined first. Then, the ferroelectric thin film layer 101 is etched at the determined location area, where the depth of the etching is different in the two location areas. Then, the first electrode material is deposited on the location area of the first electrode to form the first electrode 102, and the second electrode material is deposited on the location area of the second electrode to form the second electrode 103, wherein the upper surface of the deposited first electrode material Lower than the upper surface of the deposited second electrode material.

In this embodiment, the material of the ferroelectric thin film layer 101, the material of the first electrode 102, the material of the second electrode 103, and the shape of the first electrode 102 and the second electrode 103 may be the same as those shown in any one of FIGS. 3-7. The ferroelectric storage unit 10 is the same. For details, please refer to the relevant description of the embodiment corresponding to any one of FIGS. 3-7, which will not be repeated here.

When the ferroelectric memory cell 10 has a structure as shown in FIG. 9, the initial polarization direction P1 of the ferroelectric material may be a horizontal direction. Assume that the initial polarization direction P1 of the ferroelectric material is horizontally to the left. A first voltage is applied between the first electrode 102 and the second electrode 103 (wherein the first electrode 102 can be a positive potential, and the second electrode 103 can be a common ground) to form a direction from the first electrode 102 to the second electrode 103 electric field. The first voltage applied between the first electrode 102 and the second electrode 103 is greater than the coercive voltage of the ferroelectric material between the first electrode 102 and the second electrode 103 (that is, the polarization of the ferroelectric material in the region is reversed. The minimum voltage corresponding to the electric field). At this time, the polarization of the ferroelectric material located between the first electrode 102 and the second electrode 103 is reversed (that is, the polarization direction is horizontally to the right as shown in FIG. 10). The boundary of the polarized ferroelectric material forms an electric domain wall 104 and an electric domain wall 105, as shown in FIG. 10. At this time, logic “1” is written to the ferroelectric memory cell 10.

Among them, the steps of writing "logic 0" to the ferroelectric memory cell 10 shown in FIG. 10 and the steps of reading data from the ferroelectric memory cell 10 shown in FIG. 10 can refer to the embodiments shown in FIGS. 3-7. The related description of, I won’t repeat it here. It can be seen from FIG. 10 that, different from the foregoing embodiments, the ferroelectric memory cell 10 in this embodiment adopts the structure shown in FIG. 10, when an electric field opposite to the initial polarization direction P1 of the ferroelectric material is applied At this time, the ferroelectric thin film layer 101 located between the first electrode and the second electrode can form two electrical domain walls, so as to meet the needs of multiple electrical domain walls.

In some optional implementations of this embodiment, an insulating material may also be deposited on the upper surface of the first electrode 102 to form an insulating layer 106, as shown in FIG. 11. Wherein, the side of the upper surface of the insulating layer 106 away from the first electrode 102 and the upper surface of the ferroelectric thin film layer 101 are located on the same horizontal plane.

Please continue to refer to FIG. 12, which shows a cross-sectional view of the ferroelectric memory cell 10 shown in FIG. 2 along aa' shown in FIG. 2 provided by an embodiment of the present application.

In FIG. 12, the ferroelectric memory cell 10 includes a ferroelectric thin film layer 101, and a first electrode 102 and a second electrode 103 formed on the ferroelectric thin film layer 101. The first electrode 102 extends from the upper surface of the ferroelectric thin film layer 101 to the inside of the ferroelectric thin film layer 101, but does not penetrate the upper and lower surfaces of the ferroelectric memory cell 10; the second electrode 103 is deposited on the upper surface of the ferroelectric thin film layer 101, In other words, the lower surface of the second electrode 103 is in contact with the upper surface of the ferroelectric thin film layer 101, as shown in FIG. 12. There is a preset distance between the projection area formed by the orthographic projection of the first electrode 102 onto the upper surface of the ferroelectric thin film layer 101 and the projection area formed by the orthographic projection of the second electrode 103 onto the upper surface of the ferroelectric thin film layer 101, So that when an electric field opposite to the initial polarization direction is applied between the first electrode and the second electrode, the ferroelectric thin film layer 101 located between the first electrode 102 and the second electrode 103 forms an electric domain wall 104.

In this embodiment, by disposing the second electrode 103 on the upper surface of the ferroelectric thin film layer 101, which is equivalent to being externally hung on the outside of the ferroelectric thin film layer 101, the gap between the first electrode 102 and the second electrode 103 can be adjusted. To adjust the inclination angle of the electric domain wall of the ferroelectric thin film layer 101 between the first electrode 102 and the second electrode 103, so that the magnitude of the current read on the voltage line m or the voltage line n can be adjusted based on the needs of the scene , Improve the flexibility of current reading.

It can be seen from the cross-sectional structure of the ferroelectric memory cell 10 shown in FIGS. 3 to 12 that neither the first electrode 102 nor the second electrode 103 penetrates the upper and lower surfaces of the ferroelectric thin film layer 101.

In some optional implementation manners, one of the first electrode 102 and the second electrode 103 in any embodiment corresponding to FIGS. 3 to 12 may penetrate the upper and lower surfaces of the ferroelectric thin film layer 101. In this way, when the ferroelectric memory cell 10 needs to be connected to the components arranged on the lower layer of the ferroelectric memory cell 10 or connected with the components arranged on the upper layer of the ferroelectric memory cell 10, the first electrode 102 or the second electrode 103 is directly connected to the components on the upper layer or the lower layer of the ferroelectric memory cell 10, and there is no need to perforate the ferroelectric thin film layer 101 to connect the first electrode 102 or the second electrode 103 with other components. The lead wires connected to the device can effectively reduce the size of the ferroelectric memory cell and increase the storage density of the ferroelectric memory. In addition, it can also make the ferroelectric memory easier to integrate. Among them, the components arranged on the upper layer or the lower layer of the ferroelectric memory cell 10 may include, but are not limited to: logic devices and memory cells.

FIG. 13 and FIG. 14 schematically show a situation in which the first electrode 102 penetrates the upper and lower surfaces of the ferroelectric thin film layer 101 respectively.

Wherein, the second electrode 103 in FIG. 13 extends from the upper surface of the ferroelectric thin film layer 101 to the inside of the ferroelectric thin film layer 101, but does not penetrate the upper and lower surfaces of the ferroelectric memory cell 10. The second electrode 103 in FIG. 14 is provided On the upper surface of the ferroelectric thin film layer 101, it is equivalent to being externally hung on the outside of the ferroelectric thin film layer 101.

The materials and shapes of the ferroelectric thin film layer 101, the first electrode 102, and the second electrode 103 in FIG. 13 and FIG. The materials and shapes of the electrode 102 and the second electrode 103 are the same. For details, please refer to the relevant description of any one of the embodiments in FIGS. 3-12. The data reading and writing modes of the ferroelectric memory cell 10 shown in FIGS. Refer to the related descriptions of the data reading and writing methods of the ferroelectric memory cell 10 shown in FIGS. 3 to 4 or the related descriptions of the data reading methods of the ferroelectric memory cell 10 shown in FIGS. 5 to 6, which will not be repeated here. .

Please continue to refer to FIG. 15, which shows another structural schematic diagram of the ferroelectric memory cell array shown in FIG. 1 provided by an embodiment of the present application.

In FIG. 15, each ferroelectric memory cell 10 includes a ferroelectric thin film layer 101, and a first electrode 102 and a second electrode 103 formed on the ferroelectric thin film layer 101. The first electrode 102 extends from the upper surface of the ferroelectric thin film layer 101 to the inside of the ferroelectric thin film layer 101, and the second electrode 103 also extends from the upper surface of the ferroelectric thin film layer 101 to the inside of the ferroelectric thin film layer 101. The first electrode The depth that 102 extends to the ferroelectric thin film layer 101 is different from the depth that the second electrode 103 extends to the ferroelectric thin film layer 101. The cross-sectional view of the ferroelectric memory cell 10, the material of the ferroelectric thin film layer 101, the material of the first electrode 101, the material of the second electrode 102, and the shape of the first electrode 101 and the second electrode 102 can be the same as any of FIGS. 3-14. The shapes of the first electrode 101 and the second electrode 102 shown in the figures are the same. For details, please refer to the relevant description of the embodiment corresponding to any one of FIGS. 3 to 14, which will not be repeated here.

It can be seen from FIG. 15 that, unlike the ferroelectric memory cell array shown in FIG. 2, in this embodiment, in each column of ferroelectric memory cells 10 along the second direction y, the ferroelectric memory cells in the same column The cells 10 share the same second electrode 103, and the first electrodes in the ferroelectric memory cells 10 in the same column are independent of each other.

In this embodiment, in each column of ferroelectric memory cells 10 along the second direction y, the ferroelectric memory cells 10 located in the same column may also share the same first electrode 102, and the ferroelectric memory cells 10 located in the same column may share the same first electrode 102. The second electrodes 103 are independent of each other, which is not shown in the figure.

The embodiment of the application also provides an electronic device, which can be a portable storage device (such as a U disk, a mobile hard disk), a portable computer (such as a mobile phone), a notebook computer, a wearable electronic device (such as a smart watch), a tablet computer , Augmented reality (AR), virtual reality (VR) equipment or vehicle-mounted equipment, etc. Specifically, the electronic device shown in this application includes the ferroelectric memory shown in any of the foregoing embodiments.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the application, not to limit them; although the application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or equivalently replace some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present application. Scope.

Claims

A ferroelectric memory is characterized in that the ferroelectric memory includes a ferroelectric storage unit, a first voltage line and a second voltage line, the ferroelectric storage unit is connected to the first voltage line and the second voltage line, and The ferroelectric storage unit includes a ferroelectric thin film layer, a first electrode and a second electrode;

The first electrode is connected to the first voltage line, and the second electrode is connected to the second voltage line;

The first electrode and the second electrode are separated by the ferroelectric thin film layer;

Along the thickness direction of the ferroelectric thin film layer, the first electrode includes a first surface and a second surface, the second electrode includes a first surface and a second surface, and the first surface of the first electrode and the The first surface of the second electrode is located on the same side, and the second surface of the first electrode and the second surface of the second electrode are located on the same side;

Wherein, the second surface of the first electrode and the second surface of the second electrode are located on different horizontal planes.
The ferroelectric memory according to claim 1, wherein the ferroelectric thin film layer comprises a first surface, and the first surface of the ferroelectric thin film layer and the first surface of the first electrode are located on the same side;

Along the thickness direction of the ferroelectric thin film layer, the first electrode and the second electrode respectively extend from the first surface of the ferroelectric thin film layer to the inside of the ferroelectric thin film layer;

The depth that the first electrode extends into the ferroelectric thin film layer is different from the depth that the second electrode extends into the ferroelectric thin film layer.
3. The ferroelectric memory according to claim 2, wherein the first surface of the first electrode, the first surface of the second electrode, and the first surface of the ferroelectric thin film layer are located on the same horizontal plane.
The ferroelectric memory according to claim 2, wherein the first surface of the first electrode and the first surface of the second electrode are located on different horizontal planes, and the first surface of the ferroelectric thin film layer is The slope from the first surface of the first electrode to the first surface of the second electrode.
The ferroelectric memory according to claim 2, wherein the first surface of the first electrode and the first surface of the second electrode are located on different levels, and the first surface of the second electrode and the first surface of the second electrode are on different levels. The first surface of the ferroelectric thin film layer is located on the same horizontal plane; among them,

The first surface of the first electrode is lower than the first surface of the second electrode.
The ferroelectric memory according to claim 5, wherein an insulating layer is deposited on the first surface of the first electrode, and the insulating layer includes a first surface away from the first electrode; wherein,

The first surface of the insulating layer and the first surface of the ferroelectric thin film layer are located on the same horizontal plane.
The ferroelectric memory according to claim 1, wherein along the thickness direction of the ferroelectric thin film layer, the first electrode extends from the first surface of the ferroelectric thin film layer to the inside of the ferroelectric thin film layer , The second electrode is deposited on the first surface of the ferroelectric thin film layer.
7. The ferroelectric memory according to any one of claims 1-7, wherein along the thickness direction of the ferroelectric thin film layer, the first electrode penetrates the first surface and the second surface of the ferroelectric thin film layer .
7. The ferroelectric memory according to any one of claims 1-7, wherein along the thickness direction of the ferroelectric thin film layer, the cross-sectional shape of the first electrode or the second electrode includes one of the following: Trapezoid, rectangular.
The ferroelectric memory according to any one of claims 1-9, wherein the ferroelectric memory comprises a plurality of ferroelectric memory cells, and the plurality of ferroelectric memory cells are arranged in an array; wherein,

A plurality of the ferroelectric memory cells arranged in the same row or the same column multiplex the same first electrode.
The ferroelectric memory according to any one of claims 1-10, wherein the material forming the ferroelectric thin film layer is a single crystal material;

The initial polarization directions of the ferroelectric thin film materials forming the ferroelectric thin film layer are the same.
The ferroelectric memory according to claim 11, wherein the single crystal material comprises one of the following:

Lithium niobate, doped lithium niobate, lithium tantalate, doped lithium tantalate, bismuth ferrite, doped bismuth ferrite, lead zirconium titanate, doped lead zirconium titanate, barium titanate, Doped barium titanate, strontium tantalate, doped strontium tantalate, strontium bismuth tantalate, or doped strontium bismuth tantalate;

The doped lithium niobate or the dopant of the doped lithium tantalate includes at least one of the following: magnesium oxide,

Iron, manganese, erbium, or titanium.
An electronic device, characterized by comprising the ferroelectric memory described in any one of 1-12.