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WO2021008301A1 - 访问电子设备中的混合缓存的方法及装置 - Google Patents

访问电子设备中的混合缓存的方法及装置 Download PDF

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Publication number
WO2021008301A1
WO2021008301A1 PCT/CN2020/097274 CN2020097274W WO2021008301A1 WO 2021008301 A1 WO2021008301 A1 WO 2021008301A1 CN 2020097274 W CN2020097274 W CN 2020097274W WO 2021008301 A1 WO2021008301 A1 WO 2021008301A1
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Prior art keywords
data
logical address
index table
accessed
bit
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PCT/CN2020/097274
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English (en)
French (fr)
Inventor
白平昌
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华为技术有限公司
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Publication of WO2021008301A1 publication Critical patent/WO2021008301A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/08—Network architectures or network communication protocols for network security for authentication of entities
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/12—Applying verification of the received information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/20—Network architectures or network communication protocols for network security for managing network security; network security policies in general
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0816—Key establishment, i.e. cryptographic processes or cryptographic protocols whereby a shared secret becomes available to two or more parties, for subsequent use
    • H04L9/0819—Key transport or distribution, i.e. key establishment techniques where one party creates or otherwise obtains a secret value, and securely transfers it to the other(s)
    • H04L9/0822—Key transport or distribution, i.e. key establishment techniques where one party creates or otherwise obtains a secret value, and securely transfers it to the other(s) using key encryption key
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0816—Key establishment, i.e. cryptographic processes or cryptographic protocols whereby a shared secret becomes available to two or more parties, for subsequent use
    • H04L9/0819—Key transport or distribution, i.e. key establishment techniques where one party creates or otherwise obtains a secret value, and securely transfers it to the other(s)
    • H04L9/0825—Key transport or distribution, i.e. key establishment techniques where one party creates or otherwise obtains a secret value, and securely transfers it to the other(s) using asymmetric-key encryption or public key infrastructure [PKI], e.g. key signature or public key certificates

Definitions

  • This application relates to the field of computer storage technology, and in particular to a method and device for accessing a hybrid cache in an electronic device.
  • DRAM dynamic random access memory
  • PCM phase change memory
  • DRAM dynamic random access memory
  • PCM phase change memory
  • DRAM has the advantages of non-volatile, low power consumption and high storage density.
  • DRAM has certain advantages in write delay, so a hybrid cache based on DRAM and PCM can have the advantages of both at the same time. Since the hybrid cache includes two different types of storage media, it is urgent to study a method for accessing the hybrid cache.
  • the index tables of the stored data are respectively set for DRAM and PCM.
  • the processor accesses certain data, it first determines whether the data is stored in the DRAM according to the DRAM index table. If the data is not stored in the DRAM, it is determined whether the data is stored in the PCM according to the index table of the PCM. If this data is stored in the PCM, the data is obtained from the PCM. Based on the above description, when data needs to be accessed in the hybrid cache, it may be necessary to query the index tables corresponding to DRAM and PCM respectively, thereby affecting the speed of accessing the hybrid cache.
  • the present application provides a method and device for accessing a hybrid cache in an electronic device, which can increase the speed of accessing the hybrid cache.
  • the technical solution is as follows:
  • a method for accessing a hybrid cache in an electronic device is provided.
  • the method is applied to the electronic device.
  • the hybrid cache includes a volatile cache and a non-volatile cache.
  • the method includes: receiving a read instruction for the data to be accessed, the read instruction carries the logical address of the data to be accessed; looking up the logical address in an index table, and the index table stores state information corresponding to the logical address of the data stored in the hybrid cache ,
  • the status information is used to indicate whether the data stored in the hybrid cache is stored in the volatile cache or the non-volatile cache; when the logical address of the data to be accessed is found in the index table, the data to be accessed is obtained from the index table.
  • Access data status information read the data to be accessed from the non-volatile cache or volatile cache according to the status information of the data to be accessed.
  • the DRAM index table needs to be searched first, and when the read data is not in the DRAM index table, the PCM index table needs to be searched. In this way, if the read data is not in the DRAM, a process of looking up the PCM index table needs to be performed, which will increase the delay of data reading. Therefore, in the embodiment of the present application, an index can be uniformly set for the hybrid cache.
  • the index table records the logical address of the data stored in the hybrid cache and indicates whether the data corresponding to each logical address is stored in DRAM or In PCM, when reading data in the hybrid cache, no matter whether the data is stored in the DRAM or PCM of the hybrid cache, it only needs to look up the index table once to determine which cache the data is stored in, thereby improving access The efficiency of mixing data in the cache.
  • each logical address in the index table corresponds to a physical address that stores the data corresponding to each logical address; correspondingly, the method further includes: when obtaining the status information of the data to be accessed from the index table, also obtaining The physical address of the data to be accessed.
  • reading the data to be accessed from the non-volatile cache or the volatile cache according to the state information of the data to be accessed includes: from the non-volatile cache or the physical address of the data to be accessed according to the state information of the data to be accessed and the physical address of the data to be accessed. Read the data to be accessed in the volatile cache.
  • each logical address in the index table corresponds to a physical address that stores the data corresponding to each logical address.
  • the physical address of the data to be accessed can also be obtained.
  • the data to be accessed is directly read according to the status information and the physical address, which further improves the efficiency of accessing the data in the hybrid cache.
  • the index table includes a primary index table and a plurality of secondary index tables, and the primary index in the primary index table is the value of the first p bits in the sorting from high to low in the logical address.
  • the 2 ⁇ p bit value combinations obtained by the combination, p is a positive integer
  • each bit value combination corresponds to a secondary index table pointer
  • the secondary index table pointer is used to indicate a secondary index table among multiple secondary index tables
  • the secondary index table is used to store the logical address and the physical address corresponding to each logical address.
  • the stored logical address is the data logical address stored in the hybrid cache, and the first p bits of the stored logical address are the same as the first level
  • the bit values in the bit value combinations corresponding to the pointers of the secondary index table in the index table are the same.
  • Searching the logical address in the index table includes: searching the first-level index for the bit value combination corresponding to the first p bits of the logical address of the data to be accessed; according to the bit value combination corresponding to the second-level index table pointer, from multiple second-level Obtain a secondary index table from the index table; look up the logical address of the data to be accessed in the secondary index table.
  • the index table may include a primary index table and multiple secondary index tables, so that the secondary index table pointer can be configured in the values in the primary index table , In order to be able to quickly find the secondary index table, thereby improving the efficiency of finding the logical address of the data to be accessed.
  • the primary index table of the index table also includes stored state information of the data corresponding to each logical address, specifically: the query result corresponding to each primary index also includes a state information set, and the state information set is used for
  • the storage logical address meets the status information of the data of the corresponding primary index, and the logical address is stored in the secondary index table in order; the status information of the data to be accessed is determined from the status information of each data included in the index table, including: according to the data to be accessed
  • the sorting of logical addresses in the acquired secondary index table determines the status information of the data to be accessed from the status information set included in the query result corresponding to the primary index.
  • the secondary index table of the index table further includes the stored state information of the data corresponding to each logical address.
  • the secondary index table is also used to store the state information of the data corresponding to each logical address;
  • the secondary index table includes Determining the status information of the data to be accessed in the status information of each data includes: determining the status information of the data to be accessed in the obtained secondary index table.
  • the status information of the data corresponding to each logical address stored in the index table can be set in the primary index table or the secondary index table, which improves the flexibility of the index table.
  • the secondary index in the secondary index table is the bit value of q bits in the logical address except p bits, q is a positive integer, and each secondary index in the secondary index table
  • the query result corresponding to the index includes a logical address set.
  • Each logical address in the logical address set corresponds to a physical address, and the logical address included in the logical address set is the logical address in the hybrid cache and satisfies the corresponding primary index and corresponding secondary The logical address of the indexed data.
  • the secondary index table is configured according to the above settings, the number of items included in the secondary index table can be prevented from being excessive, thereby improving the efficiency of searching for information in the secondary index table.
  • the heat record table includes a plurality of heat record sequences Each heat record sequence corresponds to a logical address interval, the logical address of the data to be accessed falls within the logical address interval, and each heat record sequence is used to record the heat of the data corresponding to the logical address interval; update the obtained heat record sequence The recorded heat.
  • each heat record sequence includes a plurality of bits, and each bit corresponds to an update period.
  • updating the heat recorded in the acquired heat record sequence includes: acquiring the update period corresponding to the current time, and updating the bit corresponding to the update period corresponding to the current time to indicate that the data corresponding to the logical address corresponding to the heat record sequence is Identifiers visited.
  • an update period can be configured for the bits.
  • a certain update period only the bits corresponding to the update period need to be updated, so as to quickly determine whether the data is the most recent according to the bits corresponding to each update period.
  • the method further includes: detecting the heat decay instruction; obtaining the bit corresponding to the next update cycle after the update cycle corresponding to the current time among the multiple bits of each heat recording sequence; The bit value on the bit position corresponding to the next update cycle is updated to indicate that the data corresponding to the logical address corresponding to the heat record sequence has not been accessed; the next update cycle in each heat record sequence is determined as the update corresponding to the current time cycle.
  • the bits in the heat record sequence corresponding to these data will be updated to indicate that the data corresponding to the logical address corresponding to the heat record sequence has been accessed. If these data continue to be accessed in the future, then the heat record sequence will not represent the records that these data have been accessed in the most recent period of time. Therefore, in the embodiment of the present application, it is also necessary to perform heat attenuation on the heat record sequence in the heat record table in the above-mentioned manner.
  • a plurality of bits are periodically arranged in a specified order;
  • the heat record table is equipped with a clock and pointers, the clock periodically counts according to the set time after the system is initialized, and the pointers point to the multiple bits when the system is initialized
  • the trigger pointer switches to the next bit position according to the sequence; the bit position corresponding to the update period corresponding to the current time is the bit position pointed to by the current time pointer.
  • detecting the heat decay instruction includes: triggering the heat decay instruction when the current time reaches the update time point of the heat record table, and the heat record table update time point is configured when the system is initialized; and/or, when the heat record table is updated When the proportion of the sequence in all the heat record sequences is greater than the reference ratio, the heat attenuation instruction is triggered.
  • the high bit of the high heat record sequence refers to the heat of the identifier that the data corresponding to the logical address corresponding to the heat record sequence has been accessed.
  • the high-order bits refer to the bits in the multiple bits whose update period is within the reference time period before the current time. That is, heat attenuation can be performed in the above two scenarios, which improves the flexibility of heat attenuation.
  • the method further includes: determining the popularity value of the data stored in the volatile cache according to the heat rate record table; if the popularity value of the data is less than the popularity threshold, eliminating the data to the non-volatile cache. Since a heat record sequence in the heat record table can correspond to a logical address interval, the method of eliminating data provided by the embodiment of this application can take advantage of the spatial locality of the heat data and process a batch of data at the same time, which improves Eliminate the efficiency of hot data.
  • the volatile cache after determining the popularity value of the data stored in the volatile cache according to the popularity record table, it further includes: if the popularity value is less than the popularity threshold, determining the data corresponding to the logical address adjacent to the logical address of the data Heat value; determine the average heat value of the data and the data corresponding to the logical address adjacent to the logical address of the data; if the average heat value is greater than or equal to the heat threshold, keep the data in the volatile cache.
  • the heat value of a certain data is less than the heat threshold, the data is not eagerly eliminated to the non-volatile cache, but the logical address is adjacent to the logical address of the data.
  • the heat value of the data is used to comprehensively determine whether the data needs to be eliminated to the non-volatile cache, which improves the flexibility of eliminating hot data.
  • the method further includes: if the average popularity value is less than the popularity threshold, evict the data to the non-volatile cache.
  • the average heat value is less than the heat threshold, it indicates that most of the data corresponding to the logical address adjacent to the logical address of the data has not been accessed frequently recently. At this time, the data can be eliminated to the non-volatile cache to improve The flexibility of eliminating hot data.
  • the step of determining the heat value of the data stored in the volatile cache according to the heat record table is executed. That is, hot data elimination can be performed in the above two scenarios, which improves the flexibility of eliminating hot data.
  • each bit of the multiple bits is configured with a time weight, and the time weight of each bit is used to indicate how far the update time of the bit value on the corresponding bit is from the current time, among the multiple bits
  • the time weight of the bit to be updated at the current time is the largest; determining the heat value of the data stored in the volatile cache according to the heat record table, including: obtaining the time weight of multiple bits included in each heat record sequence in the heat record table ; According to the time weights of the multiple bits included in each thermal record sequence, the bit values on the multiple bits included in each thermal record sequence are weighted and summed, and the sum obtained is used as the corresponding to each thermal record sequence The popularity value of the data corresponding to the logical address interval.
  • This way of determining the popularity value can enable the determined popularity value to indicate that the data has been accessed within the most recent period of time at the current time. Specifically, the larger the popularity value is, it indicates that the data has been accessed more frequently recently, and the smaller the popularity value is, it indicates that the data has been accessed less frequently.
  • the popularity value is greater than the popularity threshold, then retaining the data of the logical address corresponding to the first popularity record sequence before the volatile cache, and also includes: if the current time reaches the popularity threshold update time point, from the heat record table Randomly select m heat record sequences, m is a positive integer greater than or equal to 1, and the heat threshold update time point is configured when the system is initialized; according to the heat value and volatility of each heat record sequence in the m heat record sequences
  • the expected storage data ratio in the cache determines the popularity threshold.
  • the expected storage data ratio refers to the ratio between the size of the data expected to be stored in the volatile cache and the size of the data expected to be stored in the hybrid cache.
  • the processor can dynamically adjust the hotness threshold periodically, so that the hot data will be eliminated according to the adjusted hotness threshold, so that the volatile cache after the hot data is eliminated
  • the visit hit rate is high.
  • the method further includes: determining an access hit rate of the volatile cache, where the access hit rate is used to indicate the proportion of the accessed data as data in the volatile cache; and determining m according to the access hit rate of the volatile cache.
  • the number of randomly selected heat record sequences is also determined according to the current data access situation in the hybrid cache, so that the hot data will be eliminated according to the adjusted heat threshold, so that the volatile cache after the hot data is eliminated
  • the visit hit rate is high.
  • the method further includes: determining the hotness threshold update time point according to the access hit rate of the volatile cache.
  • the period of periodically dynamically adjusting the hotness threshold can also be determined according to the current data access situation in the hybrid cache, so that the hot data will be eliminated according to the adjusted hotness threshold, so that the access hits of the volatile cache after the hot data is eliminated The rate is higher.
  • a device for accessing a hybrid cache in an electronic device has the function of implementing the behavior of the method for accessing the hybrid cache in an electronic device in the first aspect.
  • the device includes at least one module, and the at least one module is used to implement the method for accessing a hybrid cache in an electronic device provided in the first aspect.
  • an apparatus for accessing a hybrid cache in an electronic device includes a processor and a memory, and the memory is used to store and support the device to execute the hybrid cache in the access electronic device provided in the first aspect.
  • the processor is configured to execute the program stored in the memory.
  • the operating device of the storage device may further include a communication bus, and the communication bus is used to establish a connection between the processor and the memory.
  • a computer-readable storage medium is provided, and instructions are stored in the computer-readable storage medium.
  • the instructions When the instructions are run on a computer, the computer executes the method for accessing a hybrid cache in an electronic device in the first aspect. .
  • a computer program product containing instructions, which when the computer program product runs on a computer, causes the computer to execute the method for accessing data in the hybrid cache as described in the first aspect.
  • FIG. 1 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • Fig. 2 is a schematic diagram of a process for a processor to access data according to an embodiment of the present application
  • FIG. 3 is a flowchart of a method for accessing a hybrid cache in an electronic device according to an embodiment of the present application
  • FIG. 4 is a schematic diagram of an index table provided by an embodiment of the present application.
  • FIG. 5 is a flowchart of a method for recording heat provided by an embodiment of the present application.
  • Fig. 6 is a schematic diagram of a heat record table provided by an embodiment of the present application.
  • FIG. 7 is a flowchart of a heat attenuation method provided by an embodiment of the present application.
  • FIG. 8 is a flowchart of a hot data elimination method provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of an apparatus for accessing a hybrid cache in an electronic device according to an embodiment of the present application.
  • FIG. 10 is a schematic diagram of another apparatus for accessing a hybrid cache in an electronic device according to an embodiment of the present application.
  • FIG. 11 is a schematic diagram of another apparatus for accessing a hybrid cache in an electronic device according to an embodiment of the present application.
  • FIG. 12 is a schematic diagram of another apparatus for accessing a hybrid cache in an electronic device according to an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of an electronic device provided by an embodiment of the present application. As shown in FIG. 1, the electronic device includes at least one processor 101, a bus 102, a hybrid cache 104, an external memory 105, and at least one communication interface 106.
  • the processor 101 may be a general-purpose central processing unit (CPU) or one or more integrated circuits for controlling the execution of the program of the present application.
  • Each processor can be a single-CPU (single-CPU) processor or a multi-core (multi-CPU) processor.
  • the processor here may refer to one or more devices, circuits, and/or processing cores for processing data (for example, computer program instructions).
  • the bus 102 is used to connect the processor 101, the memory 103, the hybrid cache 104 and the external memory 105 to transfer information.
  • the bus 102 may also include a power bus and a control bus.
  • various buses are marked as the bus 102 in the figure.
  • the hybrid cache 104 includes a volatile cache 103 and a non-volatile cache 107, and the volatile cache 103 can be divided into two areas. These two areas are called write data cache 1031 and Read data buffer 1032.
  • the write data cache 1031 is used to provide a cache for the processor 101 to perform write data operations.
  • the data in the write data buffer 1031 is flushed down to the external memory 105 according to a certain algorithm.
  • the embodiment of the present application does not limit the specific implementation manner of downloading the data in the write data cache 1031 to the external memory 105.
  • the read data cache 1032 and the non-volatile cache 107 are used to provide two levels of cache for the processor 101 to perform read data operations.
  • the aforementioned volatile cache 103 may be random access memory (RAM), DRAM, or the like.
  • the non-volatile cache 107 may be a new type of non-volatile storage device such as PCM, ferroelectric memory, or magnetic memory.
  • the external memory 105 can be a read-only memory (read-only memory, ROM) or other types of static storage devices that can store static information and instructions, or it can be an electrically erasable programmable read-only memory (electrically erasable programmable read-only memory).
  • ROM read-only memory
  • EEPROM electrically erasable programmable read-only memory
  • CD-ROM compact disc
  • optical disc storage including compact discs, laser discs, optical discs, digital universal discs, Blu-ray discs, etc.
  • the read data cache 1031 is also used to store program codes for executing the solution of the present application, and the processor 101 controls the execution.
  • One or more software modules can be included in the program code.
  • the communication interface 106 uses any device such as a transceiver to communicate with other devices or communication networks, such as Ethernet, wireless access network (RAN), wireless local area networks (WLAN), etc.
  • a transceiver to communicate with other devices or communication networks, such as Ethernet, wireless access network (RAN), wireless local area networks (WLAN), etc.
  • the aforementioned computer equipment may be a general-purpose computer equipment or a special-purpose computer equipment.
  • the computer device may be a desktop computer, a portable computer, a network server, a PDA (Personal Digital Assistant, PDA), a mobile phone, a tablet computer, a wireless terminal device, a communication device, or an embedded device.
  • PDA Personal Digital Assistant
  • the embodiments of this application do not limit the type of computer equipment.
  • the computer device includes three types of storage media with different functions: a write data cache 1031, a read data cache 1032, a nonvolatile cache 107, and an external memory 105.
  • the processor accesses data, it can access these three types of storage media in a certain order.
  • Fig. 2 is a schematic diagram of a process for a processor to access data according to an embodiment of the present application. As shown in Figure 2, when the processor accesses data, it first accesses the data from the write data cache 1031. If the data does not exist in the write data cache 1031, the data is accessed from the read data cache 1032 and the nonvolatile cache 107. If the data does not exist in the read data buffer 1032 and the nonvolatile buffer 107, the data is accessed from the external storage 105.
  • the read data cache 1032 in FIG. 2 is used to store the index table and hot data of the two-level cache of the read data cache 1032 and the non-volatile cache 107.
  • the index table includes the index of the data stored in the read data cache 1032 and the index of the data stored in the non-volatile cache 107.
  • the non-volatile cache 107 is used to store the warm data eliminated from the read data cache 1032.
  • the embodiment of the present application provides a data popularity recognition algorithm and a data elimination algorithm.
  • the data popularity recognition algorithm is used to identify the popularity of data stored in the read data cache 1032.
  • the data elimination algorithm is used to eliminate the data in the read data cache 1032 to the non-volatile cache 107 according to the heat of the identified data. Subsequent embodiments will explain this in detail and will not be described here.
  • the non-volatile cache 107 can also eliminate the stored data according to a certain strategy, and store the eliminated cold data in the external storage 105.
  • the non-volatile cache 107 can also eliminate the stored data according to a certain strategy, and store the eliminated cold data in the external storage 105.
  • the data is divided into hot data, warm data, and cold data according to the frequency of access.
  • the access frequency is greater than or equal to the first preset value is hot data, the access frequency is less than the first preset value and greater than the second preset value is warm data, and the access frequency is less than or equal to the second preset value is cold data.
  • the hybrid cache accessed in the embodiment of the present application specifically refers to the two-level cache of the read data cache 1032 and the non-volatile cache 107 in FIG. 1 and FIG. 2.
  • the accessed hybrid cache is volatile
  • the sexual cache specifically refers to the read data cache 1032 in FIG. 1 and FIG. 2, and will not be explained one by one in the following.
  • FIG. 3 is a flowchart of a method for accessing a hybrid cache in an electronic device according to an embodiment of the present application. Used in the processor of the electronic device shown in FIG. 1. As shown in Figure 3, the method includes the following steps:
  • Step 301 Receive a read instruction for the data to be accessed, where the read instruction carries the logical address of the data to be accessed.
  • the processor receives a read instruction, it first determines whether the data to be accessed is stored in the write data cache. If the data to be accessed is stored in the write data cache, the data to be accessed is directly read. If the data to be accessed does not exist in the write data cache, it is determined whether the data to be accessed is stored in the two-level hybrid cache of the read data cache and the nonvolatile cache.
  • the method for accessing the hybrid cache in the electronic device provided by the embodiment of the present application can be applied in this scenario.
  • the index table of each cache in the hybrid cache is used to indicate the mapping relationship between the logical address and physical address of the data stored in the cache, then the data is read At this time, the index table of DRAM needs to be searched first. When the read data is not in the index table of DRAM, the index table of PCM needs to be searched.
  • an index table can be uniformly set for the hybrid cache.
  • the index table records the logical address of the data stored in the hybrid cache and indicates whether the data corresponding to each logical address is stored in DRAM or In PCM, when reading data in the hybrid cache, no matter whether the data is stored in the DRAM or PCM of the hybrid cache, it only needs to look up the index table once to determine which cache the data is stored in, thereby improving access The efficiency of mixing data in the cache.
  • Fig. 4 is a schematic diagram of an index table provided by an embodiment of the present application.
  • the index table records the logical address of the data stored in the hybrid cache, the physical address corresponding to each logical address, and the status information of the data corresponding to each logical address.
  • the status information is used to indicate that the data corresponding to the logical address is stored in In DRAM, it is still stored in PCM.
  • the index table may include a primary index table 401 (entry table) and multiple secondary index tables 402 (node tables).
  • primary index table entity table
  • secondary index tables node tables
  • the first-level index may be 2 ⁇ p bit value combinations obtained by combining bit values on p bits in the logical address.
  • p is a positive integer.
  • the p bits may be the first p bits in the order from high to low.
  • the index table in FIG. 4 is used to record the logical address of the data in the mixed buffer, the physical address corresponding to the logical address, and The status information of the data corresponding to each logical address.
  • the primary index table may include 2 ⁇ p items of information. Each item of information includes a primary index and the query result corresponding to the primary index.
  • the query result corresponding to each primary index in the primary index table includes a secondary index table pointer and a state information set.
  • each bit value combination corresponds to a secondary index table pointer and a state information set. In this way, when the data in the hybrid cache changes subsequently, only the query results corresponding to each primary index need to be updated, without changing the structure of the entire primary index table.
  • the state information set in the query result corresponding to the primary index includes the state of the data indicated by the logical address determined in the secondary index indicated by the pointer of the secondary index table information. Since not all the data in the logical address are stored in the hybrid cache, for the state information set corresponding to the first-level index, the state information set only includes the first p bits of the logical address in the hybrid cache and the first-level index State information of data with the same bit value in the corresponding bit value combination. For example, if the number of data with the same bit value in the first p bits of the logical address in the mixed buffer and the bit value combination corresponding to the level 1 index is 1, then the number of state information in the state information set Is one.
  • the number of state information in the state information set is more One. If there is no data with the same bit value in the bit value combination corresponding to the first p bits of the logical address in the mixed buffer, the number of state information in the state information set is zero.
  • the secondary index table pointer in the query result corresponding to the primary index is used to indicate a secondary index table among multiple secondary index tables, that is, Each item of information in the primary index table in FIG. 4 corresponds to a secondary index table.
  • the secondary index table is used to record the logical address and the physical address corresponding to each logical address.
  • the recorded logical address is the data logical address in the hybrid cache whose logical address meets the corresponding primary index.
  • the logical address meets the corresponding primary index means :
  • the bit value on the p bits before the logical address is the same as the bit value in the combination of the p bits indicated by the corresponding first-level index.
  • the stored logical address in the secondary index table is the data logical address stored in the hybrid cache, and the first p bits of the stored logical address are the same as the secondary index table pointer in the primary index table
  • the bit values in the corresponding bit value combinations are the same.
  • the implementation manner of recording the logical address in the secondary index table may be: recording the value of bits other than p bits in the logical address, or recording the bit values of the logical address on all bits.
  • the logical address includes 32 bits, and the upper 10 bits in the logical address can be used as the first-level index of the first-level index table.
  • the first-level index table shown in FIG. 4 includes 2 ⁇ 10 items of information. Each item of information corresponds to a secondary index table. It is assumed that the first-level index included in the first item of information in the first-level index table is 00000000, that is, the bit values of the upper 10 bits are all 0.
  • the state information set in the query result corresponding to the primary index of 0000000000 includes the state information of all data whose bit values on the upper 10 bits of the logical address in the hybrid cache are all 0.
  • the secondary index table indicated by the secondary index table pointer in the query result corresponding to the primary index of 0000000000 is used to record the logical addresses and logical addresses of all data whose bit values on the upper 10 bits of the logical address in the hybrid cache are all 0.
  • the physical address corresponding to each logical address since the secondary index table is the secondary index table corresponding to the primary index of 00000000, it indicates that the bit value of the first p bits of the logical address recorded in the secondary index table is 0000000000. Therefore, the logical address of each data in the hybrid buffer recorded in the secondary index table may only record the bit value of the logical address on the remaining 22 bits.
  • the logical address of each data in the hybrid buffer recorded in the secondary index table may also record the bit value of the logical address in all 32 bits, which is not specifically limited.
  • the state information set in the query result corresponding to the level one index is the state information of each data in the 100 data of data 1, data 2, data 3 to data 100.
  • the secondary index table indicated by the secondary index table pointer in the query result corresponding to the primary index is used to store the logical address of each data in the 100 data.
  • the sorting of the logical addresses of the multiple data stored in the secondary index table corresponds to the sorting of the status information of the multiple data in the status information set.
  • the order of the status information of each data in the status information set may be consistent with the order of the logical addresses of the data in the secondary index table.
  • the consistent sorting means that in the sorting result of the state information and the sorting result of the logical address, the state information and the logical address at the same position correspond to the same data.
  • the state information of the above 100 data is sorted according to the state information of data 1, the state information of data 2, the state information of data 3,..., the state information of data 100.
  • the logical addresses of the 100 data in the secondary index table are also arranged in this way: the logical address of data 1, the logical address of data 2, the logical address of data 3,..., the logical address of data 100. In this way, it can be ensured that in the sorting result of the state information and the sorting result of the logical address, the state information and the logical address at the same position correspond to the same data.
  • the sorting of each state information in the state information set and the sorting of each logical address in the secondary index table are correspondingly set, so that the position of the logical address of a certain data in the secondary index table can be directly obtained from the state information.
  • the status information of the corresponding location in the collection is used as the status information of this data, thereby improving the efficiency of acquiring status information.
  • the secondary indexes in the secondary index table may be bit values on q bits in the logical address.
  • the q bits may be other bits in the logical address except the p bits of the first level index.
  • the first q bits in the logical address can be sorted from low to high.
  • the bit values on the q bits can be combined to obtain 2 ⁇ q different combined bit values, the same reason as the first-level index table, in order to avoid subsequent changes in the data in the mixed buffer, resulting in the second-level index
  • the items in the table need to be deleted or added continuously.
  • the secondary index table indicated by the secondary index table pointer corresponding to the level level index includes 2 ⁇ q Item information, each item of information includes a secondary index and the query result corresponding to the secondary index.
  • the query result corresponding to the secondary index is a logical address set, each logical address in the logical address set corresponds to a physical address, and the logical address included in the logical address set It is the logical address of the data in the hybrid cache that satisfies both the corresponding primary index and the corresponding secondary index.
  • the logical address included in the logical address set not only has the same bit value on the q bits as the bit value indicated by the secondary index, but also the bits on the p bits and the bit value indicated by the secondary index.
  • the bit values indicated by the corresponding primary indexes are the same.
  • the number of logical addresses in the logical address set can be any integer, and the logical address set corresponding to each secondary index in the secondary index table Can be different.
  • the bits in the lower 10 bits of the logical address can be used as the secondary index of the secondary index table.
  • the primary index included in the first item of the primary index table is 0000000000
  • the primary index is The corresponding secondary index table includes 2 ⁇ 10 items of information, and each item of information includes a secondary index and a query result corresponding to the secondary index.
  • the secondary index included in the first item of information in the secondary index table is 00000000.
  • the logical address set indicated by the query result corresponding to the secondary index includes the logical address and each logical address of the data in the hybrid cache that simultaneously satisfy the data whose bit values on the lower 10 bits and upper 10 bits are 0. The corresponding physical address.
  • the primary index table includes 2 ⁇ p items of information, and each item of information corresponds to a secondary index table, and the secondary index table includes 2 ⁇ q items of information.
  • Each piece of information includes a logical address set. Assume that each logical address set includes k logical addresses and k physical addresses corresponding to the k logical addresses one-to-one. Therefore, for the secondary index table indicated by any item of information in the primary index table, the secondary index table includes (2 ⁇ q) ⁇ k logical addresses and the physical address corresponding to each logical address.
  • the state information set in one item of information in the primary index table corresponding to the secondary index table includes (2 ⁇ q) ⁇ k state information. Where k is a positive integer, the above k is only an example of the number of logical addresses included in the logical address set, and does not constitute a limitation on the number of logical addresses included in the logical address set
  • the index table shown in FIG. 4 may be configured first. At this time, the state information set of the primary index table in the index table and the logical address set of the secondary index table may be null at this time. When data is added or deleted later in the hybrid cache, only the state information set in the index table and the specific elements in the logical address set need to be updated, and there is no need to change the structure of the index table.
  • the index table is directly mapped according to the logical address of the data, the physical address corresponding to the logical address, and the state information collection. There is no need to construct the index table through complex hash calculations, which improves the efficiency of building the index table. .
  • both the primary index table and the secondary index table in the index table use some bits in the logical address as indexes, the storage positions of adjacent logical addresses in the index table can be made adjacent.
  • Hot data usually has spatial locality, that is, data in a logical address interval is usually hot data. Therefore, the index table provided in the embodiment of the present application can also make full use of the spatial locality of hot data to facilitate subsequent basis The index table processes the hot data in batches, further improving the flexibility of processing hot data.
  • the index table may be configured as the primary index table and the secondary index table shown in FIG. 4.
  • the configuration method is the same as that shown in Figure 4 above.
  • the configuration method is basically the same.
  • only the first-level index table can be set, which will not be explained here.
  • each status information may use 1 bit to indicate whether the corresponding data is stored in a volatile cache or a nonvolatile cache. For example, when the value of this bit is 1, it indicates that the corresponding data is stored in the volatile buffer. When the value of this bit is 0, it indicates that the corresponding data is stored in the non-volatile buffer.
  • the status information is configured in the primary index table.
  • the status information can also be configured in the secondary index table.
  • the primary index table includes 2 ⁇ p items of information, and each item of information includes a primary index and a query result corresponding to the primary index, and the query result corresponding to the primary index includes A pointer to the secondary index table.
  • the pointer of the secondary index table corresponding to each primary index corresponds to a secondary index table.
  • the secondary index table includes 2 ⁇ q items of information.
  • Each item of information includes a logical address set, and each logical address set includes logical Address, physical address corresponding to each logical address, and status information of data corresponding to each logical address.
  • the status information of the data corresponding to each logical address stored in the index table can be set in the primary index table as shown in FIG. 4, and of course, can also be set in the secondary index table. There is no specific limitation here.
  • the index table shown in FIG. 4 may be stored in a key-value manner.
  • Storing an index table in a key-value manner means that for a primary index table or a secondary index table, the indexes in the table are used as keys, and the query results corresponding to each index are stored as values. Because the data of the key-value structure can be directly located in the index table when querying, the corresponding data can be found without traversing the entire index table. Therefore, storing the index table by key value can improve the efficiency of subsequent data search .
  • Step 302 Look up the logical address in the index table.
  • step 302 can be: look up the bit value combination corresponding to the first p bits of the logical address of the data to be accessed in the primary index; according to the bit value combination corresponding to the secondary
  • the index table pointer obtains a secondary index table from multiple secondary index tables; searches the logical address of the data to be accessed in the secondary index table.
  • the bit value on p bits in the logical address of the data to be accessed can be determined, the bit value on p bits in the logical address of the data to be accessed is used as the first-level index, and the first-level index table is looked up.
  • the query result corresponding to the primary index.
  • the query result includes a pointer to a secondary index table.
  • a secondary index table is obtained from the multiple secondary index tables shown in FIG. 4. Determine the bit value of q bits in the logical address of the data to be accessed, and use the bit value of the q bits in the logical address of the data to be accessed as the secondary index.
  • the query result corresponding to the secondary index is searched from the secondary index table obtained above, and the query result is a logical address set. Then the logical address set is traversed, and if the logical address of the data to be accessed is traversed in the logical address set, it is determined that the logical address of the data to be accessed is stored in the index table.
  • Step 303 When the logical address of the data to be accessed is found in the index table, the status information of the data to be accessed is obtained from the index table.
  • the primary index table or secondary index table of the index table also includes stored state information of data corresponding to each logical address. Therefore, when the logical address of the data to be accessed is found in the secondary index table through step 302, the status information of the data to be accessed can be determined from the status information of each data included in the index table.
  • the primary index table also includes stored status information of the data corresponding to each logical address, as shown in Figure 4, the query result corresponding to each primary index also includes A state information set, the state information set is used to store the state information of the data whose logical address meets the corresponding primary index, and the secondary index table stores the logical address sequence arrangement.
  • the method for determining the status information of the data to be accessed from the status information of the data included in the index table may be: according to the sorting of the logical address of the data to be accessed in the acquired secondary index table, corresponding from the primary index The status information of the data to be accessed is determined from the status information set included in the query result.
  • the order of the status information of each data in the status information set in the primary index table may be consistent with the order of the logical addresses of each data in the secondary index table.
  • the explanation of ordering consistency has been explained in the index table shown in Figure 4 above.
  • the query result corresponding to the secondary index included in each item of information in the secondary index table is a logical address set, and each logical address The set includes 8 logical addresses, which are arranged in order.
  • the secondary index determined according to the logical address of the data to be accessed is the secondary index included in the 26th item of the 50 items of information, and the logical address of the data to be accessed is in the logical address set corresponding to the secondary index
  • the 204th (that is, (26-1)*8+4) state information in the state information set can be used as the state information of the data to be accessed.
  • each state information in the state information set in the first-level index table can also be exactly the opposite of the logical address sorting in the values corresponding to the keys in the second-level index table. In this case, the sorting can also be done accordingly. Obtain the status information of the data to be accessed from the status information collection, which will not be elaborated here.
  • the secondary index table also includes stored state information of data corresponding to each logical address. That is, the secondary index table is also used to store the status information of the data corresponding to each logical address.
  • an implementation manner of determining the state information of the data to be accessed from the state information of each data included in the index table may be: determining the state information of the data to be accessed in the obtained secondary index table.
  • the physical address corresponding to each logical address is also stored in the secondary index table. Therefore, when the logical address of the data to be accessed is found in the secondary index table through step 302 , You can directly obtain the physical address of the data to be accessed.
  • Step 304 Read the data to be accessed from the non-volatile cache or the volatile cache according to the state information of the data to be accessed.
  • step 304 may be: reading the data to be accessed from the non-volatile cache or the volatile cache according to the state information of the data to be accessed and the physical address of the data to be accessed.
  • step 303 after determining the status information of the data to be accessed according to step 303, if the storage location indicated by the status information of the data to be accessed is a volatile cache, access from the volatile cache according to the physical address of the data to be accessed Data to be accessed. If the storage location indicated by the status information of the data to be accessed is a non-volatile cache, the data to be accessed is accessed from the non-volatile cache according to the physical address of the data to be accessed. In addition, after the data to be accessed is accessed through the non-volatile cache, the data to be accessed is copied from the non-volatile cache to the volatile cache, so as to facilitate subsequent direct access to the data to be accessed through the volatile cache.
  • Step 305 When the logical address of the data to be accessed is not found in the index table, read the data to be accessed from the external memory.
  • the index table is an index table configured for the hybrid cache
  • the logical address set can be traversed to the index table to be accessed.
  • the logical address of the data if the data to be accessed is not stored in the hybrid cache, the logical address of the data to be accessed cannot be traversed in the logical address set.
  • the processor determines that the data to be accessed is stored in the external memory, and can then read the data to be accessed from the external memory. After the data to be accessed is accessed through the external memory, the data to be accessed is copied from the external memory to the volatile cache, so that the data to be accessed can be accessed directly through the volatile cache in the future.
  • the hybrid cache provided by the embodiments of the present application includes two different types of cache media, and the volatile cache is used to store hot data, and the non-volatile cache is used to store warm data eliminated from the hot data.
  • a heat record needs to be configured for the data in the volatile cache of the hybrid cache, so as to determine which data in the volatile cache needs to be eliminated as warm data based on the heat record.
  • the heat record is also the data access frequency record.
  • the embodiment of the present application also provides a heat record table.
  • the heat record table includes a plurality of heat record sequences, and each heat record sequence uses a CNT mark.
  • Each heat record sequence corresponds to a logical address interval (not shown).
  • the logical address interval can include one logical address or multiple adjacent logical addresses.
  • the logical addresses in the logical address interval are in the volatile cache. The logical address of the stored hot data.
  • the logical address of the added or deleted data is determined, and In the heat record table shown in Figure 6, the heat record sequence corresponding to the logical address of the added or deleted data is updated to ensure that the heat record table is used to indicate the current time of all data stored in the volatile cache Visit heat.
  • FIG. 6 only shows the thermal recording sequence, and does not show the logical address space corresponding to each thermal recording sequence.
  • each heat record sequence includes a plurality of bits, and each time the data of the logical address in the logical address interval corresponding to the heat record sequence is accessed, the bit of one bit above the plurality of bits is updated Value to realize that the thermal record sequence can indicate the access status of the data in the logical address interval corresponding to the logical address in the most recent period of time.
  • the detailed update method will be described in the following embodiments, and will not be elaborated here.
  • FIG. 5 is a flowchart of a thermal recording method provided by an embodiment of the present application, which is applied to the processor of the electronic device shown in FIG. 1. As shown in Figure 5, the method includes the following steps:
  • Step 501 According to the logical address of the data to be accessed, a heat record sequence corresponding to the logical address of the data to be accessed is obtained from the heat record table.
  • each heat record sequence in the heat record table corresponds to a logical address interval
  • the heat record sequence corresponding to the logical address of the data to be accessed can be directly obtained from the heat record table according to the logical address of the data to be accessed.
  • Step 502 Update the heat recorded in the acquired heat record sequence.
  • an update period can be configured for each bit. In this way, in a certain update period, only the bits corresponding to the update period need to be updated, so that the access heat of the data in the recent period can be quickly determined according to the bits corresponding to each update period.
  • step 502 may be: obtaining the update period corresponding to the current time, and updating the bit corresponding to the update period corresponding to the current time to an identifier indicating that the data corresponding to the logical address corresponding to the heat record sequence has been accessed.
  • the identifier indicating that the data corresponding to the logical address corresponding to the thermal record sequence has been accessed may be the first bit value.
  • the value of the first bit may be 1, which is used to indicate that the data to be accessed is currently accessed.
  • a clock and pointer may be configured for the heat record table.
  • the clock After the computer device is initialized, the clock periodically counts according to the set duration.
  • the multiple bits included in this heat record sequence are periodically arranged in a specified order, and the pointer points to one of the multiple bits during initialization. Bit.
  • the pointer Each time the timing of the clock reaches one cycle, the pointer points to the next bit according to the order of multiple bits.
  • the bit corresponding to the update period corresponding to the current time in step 502 is the bit pointed to by the pointer at the current time.
  • the bit corresponding to the update period corresponding to the current time may also be referred to as the bit to be updated at the current time.
  • the bit value of the bit that is located before the bit to be updated at the current time in the sorting, and the bit closer to the bit to be updated at the current time is used to indicate the time closer to the current time
  • the bit value on the bit farther from the bit to be updated at the current time is used to indicate the data access in the time segment farther from the current time.
  • each heat recording sequence is marked as CNT, and each CNT includes 8 bits. These 8 bits are marked as bit A, bit B, bit C, bit D, bit E, bit F, bit G, and bit H, respectively. Assuming that the configured clock has a timing duration of 1 hour, these 8 bits are in accordance with A, B, C, D, E, F, G, H, A, B, C, D, E, F, G, H,... The sequence of A, B, C, D, E, F, G, and H is arranged periodically. When the system is initialized, the pointer points to bit A. When the timing of the clock reaches 1 hour, the pointer switches from bit A to bit B, and the clock restarts timing.
  • bit pointed to by the current time of the pointer is bit A, then it is determined that bit A is the bit corresponding to the update period corresponding to the current time, and the bit value on bit A is updated to 1 to indicate The data to be accessed has been accessed at the current time.
  • the same time weight as the number of multiple bits is pre-configured, and the time weight can be Indicates the distance to the current time, where the greater the time weight, the closer to the current time, and the smaller the time weight, the farther away from the current time.
  • the multiple bits are sorted, and multiple pre-configured time weights are allocated to the multiple bits after sorting, and the time weight of each bit after sorting is sequentially reduced. In this way, whenever the timing of the clock reaches and the pointer switches to the bit position, the time weight on each bit position is updated, so that the bit position pointed to by the pointer has the largest time weight at any time, and the pointer will point to the next time The time weight of the bit position is the smallest.
  • time weights are pre-configured, which are labeled L0, L1, L2, L3, H0, H1, H2, and H3. These 8 time weights increase sequentially.
  • the 8 bits in Figure 6 are marked as A, B, C, D, E, F, G, and H respectively. And these 8 bits are arranged in a closed ring in the order of A, B, C, D, E, F, G, and H. If the current time pointer points to bit C, then each time weight is allocated to each bit according to the allocation method in Table 1 below.
  • each time weight is allocated to each bit according to the allocation method in Table 2 below.
  • the current time pointer points to bit A, and each time weight is allocated to each bit according to the allocation method in Table 3 below.
  • the pointer points to one of the bits after the 8 bits are periodically arranged in the specified order. Therefore, during the time when the pointer points to a certain bit, the pointer on the bit The bit value may have been updated in the last cycle. At this time, the hot record sequence corresponding to the data will not be able to characterize the access situation of the data in the recent period of time. Therefore, in the embodiment of the present application, it is also necessary to perform heat attenuation on the heat record sequence in the heat record table.
  • Fig. 7 is a flowchart of a heat attenuation method provided by an embodiment of the present application, which is applied to the processor of the electronic device shown in Fig. 1. As shown in Figure 7, the method includes the following steps:
  • Step 701 Detect the heat attenuation command.
  • the processor can detect the heat decay command in the following two scenarios.
  • the first scenario the computer equipment is configured with the update time point of the heat record table when the system is initialized. Therefore, when the current time reaches the point in time when the heat record table is updated, the computer device will automatically trigger the heat attenuation instruction. For example, when the computer equipment system is initialized, it can be configured to update the heat record table every 1 day. Assuming that the computer equipment system is initialized at 0:00, then the heat record table is updated at 0:00 every day.
  • the second scenario When the proportion of the high heat recording sequence in all the heat recording sequences is greater than the reference ratio, at this time, the heat attenuation command can be triggered.
  • the high heat recording sequence refers to a heat recording sequence in which the high order bits are all identifiers indicating that the data corresponding to the logical address corresponding to the heat recording sequence has been accessed.
  • the high-order bits refer to the bits within the reference period of the update period before the current time among the multiple bits, that is, the high-order bits refer to the bits updated in the most recent period before the current time.
  • the high bit can refer to the multiple bits of the heat record sequence with time weight from high to low n Bit position, n is a positive integer greater than or equal to 1.
  • the high bit can be bit D, bit B, bit D, and so on. If the high-order bit is bit D, then the high-heat recording sequence is a thermal recording sequence with bit D being 1, and if the reference ratio is 90%, the proportion of the high-heat recording sequence in all thermal recording sequences is greater than 90% , The heat decay instruction is triggered.
  • Step 702 Obtain the bit corresponding to the next update period after the update period corresponding to the current time among the multiple bits of each heat record sequence.
  • bit H As shown in Table 2, as long as the bit pointed to by the current time pointer is determined, the time weight of each bit of multiple bits can be determined. At this time, the bit with the smallest time weight is the bit corresponding to the next update cycle. Bit. As shown in Figure 6, before the heat decays, the bit corresponding to the next update period is bit H.
  • Step 703 Update the bit corresponding to the next update cycle in each heat record sequence to an identifier indicating that the data corresponding to the logical address corresponding to the heat record sequence has not been accessed.
  • step 702 the bit value on the time weight L0 in all the popularity record sequences can be updated to the second bit value.
  • the second bit value is zero.
  • step 703 is referred to as a reset operation. As shown in Fig. 6, the bit value on the bit H in all the heat recording sequences can be reset to 0.
  • Step 704 Determine the bit position corresponding to the next update period in each heat record sequence as the bit position corresponding to the update period corresponding to the current time.
  • step 703 the pointer can be directly pointed to the bit corresponding to the next update period to determine the bit corresponding to the next update period in each heat record sequence as the bit corresponding to the update period corresponding to the current time. Since the computer device reassigns the time weight to each bit every time the pointer switches to the bit, in step 703, the bit corresponding to the next update period in each heat record sequence is determined as After the bits corresponding to the update period corresponding to the current time, the time weight of each bit is equivalent to a sequential shift.
  • step 704 is referred to as a weight transfer operation.
  • step 703 the time weight on each bit position is as shown in Table 1, then after step 703 is performed, the time weight on each bit position is updated to the situation shown in Table 2.
  • the time weight on each bit position is as shown in Table 3 above, and after the heat decay, the time weight on each bit position is as shown in Table 4 below.
  • the bits corresponding to the same time weight in different thermal recording sequences are stored in a continuous address space.
  • the bits of all the heat recording sequences corresponding to the time weight L0 are stored in a continuous address space
  • the bits of all the heat recording sequences corresponding to the time weight L1 are stored in a continuous address space. Therefore, when the processor executes step 703, since the bits to be updated next time in all the heat record sequences are stored in a continuous address space, at this time, only the bits of the bits in the continuous address space are needed. The value can be reset to 0 uniformly.
  • step 704 it is sufficient to re-allocate time weights for each segment of continuous address space, which is equivalent to only performing a reset operation and a weight transfer operation, and there is no need to perform the above steps 703 and 703 for each heat record sequence. In step 704, the efficiency of performing heat attenuation is improved.
  • the heat record sequence in the heat record table is only for the volatile cache.
  • the hot data in the configuration Since the data in the volatile cache changes dynamically, in the embodiment of the present application, if new data in the volatile cache is detected, the logical address of the newly added data is determined, and shown in FIG. 6 Reset the heat record sequence corresponding to the logical address of the new data in the heat record table of the new data. For example, reset the bit value of the bit pointed to by the current time of the pointer in all bits to 1, and the other bits The bit value is reset to 0.
  • each heat record sequence included in the heat record table is always maintained as a heat record sequence for the data in the volatile cache.
  • the data in the volatile cache of the hybrid cache can be used to record the recent access of the data through the heat recording sequence. Therefore, the present application can record the data according to the heat recording sequence Eliminate the volatile data to achieve the elimination of hot data into warm data.
  • FIG. 8 is a flowchart of a hot data elimination method provided by an embodiment of the present application, which is applied to the processor of the electronic device shown in FIG. 1.
  • the hot data elimination method shown in FIG. 8 is also the hot spot identification elimination algorithm in FIG. 2. As shown in Figure 8, the method includes the following steps:
  • Step 801 Determine the popularity value of the data stored in the volatile cache according to the popularity record table.
  • the method for calculating the popularity value of the data stored in the volatile cache is: determining the logical address interval corresponding to each popularity record sequence according to the bit values on the multiple bits included in each popularity record sequence The popularity value of the corresponding data.
  • the method of determining the popularity value of the data corresponding to the logical address interval corresponding to each thermal recording sequence may be: according to the time weight of the multiple bits included in each thermal recording sequence, the multiple thermal recording sequences include The bit values on each bit position are weighted and summed, and the obtained sum value can be used as the data popularity value corresponding to the logical address interval corresponding to each popularity record sequence.
  • This way of determining the popularity value can enable the determined popularity value to indicate that the data has been accessed within the most recent period of time at the current time. Specifically, the larger the popularity value is, it indicates that the data has been accessed more frequently recently, and the smaller the popularity value is, it indicates that the data has been accessed less frequently.
  • the time weight of each bit included in the heat recording sequence is the time weight shown in Table 2 above.
  • the thermal value of the data corresponding to the logical address interval corresponding to the thermal record sequence can be: bit value on bit A ⁇ H0+bit value on bit B ⁇ H1+on bit C Bit value of bit ⁇ H2 + bit value on bit D ⁇ H3 + bit value on bit E ⁇ L0 + bit value on bit F ⁇ L1 + bit value on bit G ⁇ L2 + bit value on bit H ⁇ L3 .
  • the hot data elimination method provided in the embodiment of FIG. 8 can be executed in the following two scenarios.
  • the first scenario is to detect that the remaining storage capacity of the volatile cache is lower than the threshold.
  • the processor can eliminate hot data in time based on the remaining storage capacity of the volatile cache, so as to avoid the situation that the volatile cache is too full.
  • the second scenario is the detection of the elimination of hot data instructions.
  • the hot data elimination instruction can be triggered by the background manager.
  • the processor can eliminate the hot data according to the user's needs, which improves the flexibility of hot data elimination.
  • Step 802 If the popularity value of the data is less than the popularity threshold, then the data is eliminated to the non-volatile cache.
  • the popularity value of the data is greater than or equal to the popularity threshold, it is kept in the volatile cache. If the popularity value of the data is greater than or equal to the popularity threshold, it indicates that the data has been accessed more frequently in the most recent period of time. At this time, there is no need to eliminate the data in the non-volatile cache, that is, keep the data in Volatile cache.
  • step 802 and step 803 to step 806 in FIG. 8 are two parallel implementations.
  • Step 803 If the popularity value of the data is less than the popularity threshold, determine the popularity value of the data corresponding to the logical address adjacent to the logical address of the data.
  • the heat value of the data is less than the heat threshold, the data is not eagerly eliminated to the non-volatile cache, but combined with the logical address adjacent to it.
  • the heat value of the data is used to comprehensively determine whether the data needs to be eliminated to the non-volatile cache, which improves the flexibility of eliminating hot data.
  • the popularity value of the data corresponding to the logical address adjacent to the logical address of the data is determined to determine whether hot data elimination is required through the following steps 804 to 806.
  • the popularity value of the data corresponding to the adjacent logical address can also be determined according to the data popularity record sequence corresponding to the adjacent logical address. No longer.
  • Step 804 Determine the average popularity value of the data and the data corresponding to the logical address adjacent to the logical address of the data.
  • Step 805 If the average popularity value is greater than or equal to the popularity threshold, keep the data in the volatile cache.
  • the average heat value is greater than or equal to the heat threshold, it indicates that most of the data on the logical address adjacent to the logical address of the data is the data that has been frequently accessed recently. According to the spatial locality of the hot data, the data is very likely Will be frequently visited recently. At this time, if the data is directly eliminated to the non-volatile cache, it is easy to access the data immediately after elimination, resulting in unnecessary elimination. Therefore, in the embodiment of the present application, the data can continue to be kept in the volatile cache. It is equivalent to giving the data a second chance.
  • Step 806 If the average popularity value is less than the popularity threshold, the data is eliminated to the non-volatile cache.
  • the average heat value is less than the heat threshold, it indicates that most of the data on the logical address adjacent to the logical address of the data has not been accessed frequently recently. At this time, the data can be eliminated into the non-volatile cache.
  • the heat threshold in the process of eliminating hot data can be configured by the background manager. At this time, after the heat threshold is configured, the data can be eliminated subsequently according to the fixed heat threshold.
  • the processor may dynamically adjust the heat threshold periodically, so as to subsequently eliminate hot data according to the adjusted heat threshold.
  • the processor periodically dynamically adjusts the heat threshold value specifically as follows: if the current time reaches the heat threshold update time point, randomly select m heat record sequences from the heat record table, and m is greater than or equal to 1. A positive integer. According to the heat value of each heat record sequence in the m heat record sequences and the proportion of expected stored data in the volatile cache, the heat threshold is determined.
  • the expected storage data ratio refers to the ratio between the size of the data expected to be stored in the volatile cache and the size of the data expected to be stored in the hybrid cache.
  • a heat threshold can be determined based on the heat value of each heat record sequence in the 10% and m heat record sequences, so that only those heat record sequences with a heat value greater than 90% of other heat values correspond to The data can be left in DRAM.
  • the number of randomly selected thermal record sequences is also determined according to the current data access situation in the hybrid cache.
  • the access hit rate of the volatile cache can be determined, and the access hit rate is used to indicate the proportion of the accessed data as the data in the volatile cache;
  • the access hit rate of the lossless cache determine m. For example, the higher the access hit rate of the volatile cache is, it indicates that the hotness threshold before adjustment is more accurate, and m can be smaller at this time. If the access hit rate of the volatile cache is low, it indicates that the heat threshold before the adjustment is not very accurate, and m can be larger at this time, so that the heat threshold after the adjustment can be accurate.
  • the accuracy of the heat threshold means that after data is eliminated according to the heat threshold, the data accessed by the processor each time is basically in the volatile cache.
  • the period of regularly dynamically adjusting the popularity threshold can also be determined according to the current data access situation in the hybrid cache.
  • the hotness threshold update time point can be determined according to the access hit rate of the volatile cache. For example, when the access hit rate of the volatile cache is high, it indicates that the heat threshold before adjustment is relatively accurate. At this time, the cycle of the heat threshold update time point is set longer, that is, it is not necessary to frequently update the heat threshold. When the access hit rate of the volatile cache is low, it indicates that the heat threshold before adjustment is not very accurate. At this time, the cycle of the heat threshold update time point is set shorter, that is, the heat threshold needs to be updated frequently to make the adjustment The heat threshold is more accurate.
  • an embodiment of the present application provides an apparatus for accessing a hybrid cache in an electronic device.
  • the apparatus 900 includes:
  • the receiving module 901 is configured to perform step 301 in the embodiment of FIG. 3;
  • the search module 902 is configured to execute step 302 in the embodiment of FIG. 3;
  • the first obtaining module 903 is configured to perform step 303 in the embodiment of FIG. 3;
  • the reading module 904 is configured to execute step 304 in the embodiment of FIG. 3.
  • each logical address in the index table corresponds to a physical address that stores data corresponding to each logical address
  • the first obtaining module is also used to obtain the physical address of the data to be accessed when obtaining the status information of the data to be accessed from the index table; the reading module is specifically used to: according to the status information of the data to be accessed and the physical address of the data to be accessed The address reads the data to be accessed from the non-volatile cache or the volatile cache.
  • the index table includes a primary index table and a plurality of secondary index tables, and the primary index in the primary index table is the value of the first p bits in the sorting from high to low in the logical address.
  • the 2 ⁇ p bit value combinations obtained by the combination, p is a positive integer
  • each bit value combination corresponds to a secondary index table pointer
  • the secondary index table pointer is used to indicate a secondary index table among multiple secondary index tables
  • the secondary index table is used to store the logical address and the physical address corresponding to each logical address.
  • the stored logical address is the data logical address stored in the hybrid cache, and the first p bits of the stored logical address are the same as the first level
  • the bit values in the bit value combinations corresponding to the pointers of the secondary index table in the index table are the same;
  • the search module is specifically used to: search for the bit value combination corresponding to the first p bits of the logical address of the data to be accessed in the primary index; according to the secondary index table pointer corresponding to the bit value combination, from multiple secondary index tables Obtain a secondary index table in the secondary index table; find the logical address of the data to be accessed in the secondary index table.
  • the primary index table of the index table also includes stored state information of the data corresponding to each logical address, specifically: the query result corresponding to each primary index also includes a state information set, and the state information set is used for The storage logical address meets the status information of the data of the corresponding primary index, and the logical address is stored in the secondary index table in order; the first acquisition module is specifically used for: according to the logical address of the data to be accessed Sorting, determining the state information of the data to be accessed from the state information set included in the query result corresponding to the primary index.
  • the secondary index table of the index table further includes the stored state information of the data corresponding to each logical address.
  • the secondary index table is also used to store the state information of the data corresponding to each logical address;
  • the first acquisition module Specifically used for: determining the status information of the data to be accessed in the obtained secondary index table.
  • the secondary index in the secondary index table is the bit value of q bits in the logical address except p bits, q is a positive integer, and each secondary index in the secondary index table
  • the query structure corresponding to the index includes a logical address set, each logical address in the logical address set corresponds to a physical address, and the logical address included in the logical address set is the logical address in the hybrid cache and satisfies the corresponding primary index and corresponding secondary The logical address of the indexed data.
  • the device 900 further includes:
  • the second obtaining module 905 is configured to execute step 501 in the embodiment of FIG. 5;
  • the first update module 906 is configured to execute step 502 in the embodiment of FIG. 5.
  • each heat record sequence includes a plurality of bits, and each bit corresponds to an update period; the first update module is specifically configured to: obtain the update period corresponding to the current time, and associate the update period corresponding to the current time with The bit is updated to indicate that the data corresponding to the logical address corresponding to the heat record sequence has been accessed.
  • the device 900 further includes:
  • the detection module 907 is configured to execute step 701 in the embodiment of FIG. 7;
  • the third acquiring module 908 is configured to execute step 702 in the embodiment of FIG. 7;
  • the second update module 909 is configured to execute step 703 in the embodiment of FIG. 7;
  • the third update module 910 is configured to perform step 704 in the embodiment of FIG. 7.
  • multiple bits are periodically arranged in a specified order
  • the heat record table is equipped with a clock and a pointer.
  • the clock periodically counts according to the set duration after the system is initialized.
  • the pointer points to one of the multiple bits when the system is initialized, and each time the timing of the clock reaches the set duration When, the trigger pointer switches to the next bit position according to the sequence;
  • the bit corresponding to the update period corresponding to the current time is the bit pointed to by the current time pointer.
  • the detection module 907 is specifically configured to:
  • the heat attenuation command is triggered, and the heat record table update time point is configured during system initialization; and/or,
  • the high heat record sequence means that the bit value on the high bit is corresponding to the logical address corresponding to the heat record sequence
  • the heat record sequence of the identifier whose data has been accessed, the high-order bit refers to the bit in the reference period of the update period before the current time among the multiple bits.
  • the device 900 further includes:
  • the first determining module 911 is configured to execute step 801 in the embodiment of FIG. 8;
  • the elimination module 912 is configured to perform step 802 in the embodiment of FIG. 8.
  • the first determining module 911 is further configured to perform step 803 and step 804 in the embodiment of FIG. 8;
  • the device also includes a reservation module for executing step 805 in the embodiment of FIG. 8.
  • the elimination module 912 is also used to perform step 806 in the embodiment of FIG. 8.
  • the first determining module is also used for:
  • the process of determining the heat value of the data stored in the volatile cache according to the heat record table is executed step.
  • each bit of the multiple bits is configured with a time weight, and the time weight of each bit is used to indicate how far the update time of the bit value on the corresponding bit is from the current time, among the multiple bits The time weight of the bit to be updated at the current time is the largest;
  • the first determining module is specifically used for:
  • the bit values on the multiple bits included in each thermal record sequence are weighted and summed, and the obtained sum value is used as the corresponding to each thermal record sequence
  • the popularity value of the data corresponding to the logical address interval is used as the corresponding to each thermal record sequence.
  • the device further includes:
  • the selection module is used to randomly select m heat record sequences from the heat record table if the current time reaches the heat threshold update time point, where m is a positive integer greater than or equal to 1, and the heat threshold update time point is configured during system initialization ;
  • the second determining module is used to determine the heat threshold value according to the heat value of each heat record sequence in the m heat record sequences and the expected stored data ratio in the volatile cache.
  • the expected stored data ratio refers to the expected stored data in the volatile cache The ratio between the size of the data expected to be stored and the size of the data expected to be stored in the hybrid cache.
  • the device further includes:
  • the third determining module is used to determine the access hit rate of the volatile cache, and the access hit rate is used to indicate the proportion of the accessed data as the data in the volatile cache;
  • the fourth determining module is used to determine m according to the access hit rate of the volatile cache.
  • the device further includes:
  • the fifth determining module is used to determine the update time point of the popularity threshold according to the access hit rate of the volatile cache.
  • an index table can be set for the hybrid cache.
  • the index table records the logical address of the data stored in the hybrid cache and the physical address corresponding to the logical address, and indicates Whether the data corresponding to each logical address is stored in DRAM or PCM, when reading data in the hybrid cache, no matter if the data is stored in the DRAM or PCM of the hybrid cache, you only need to look up the index table once. This improves the efficiency of accessing data in the hybrid cache.
  • the device for accessing data in the hybrid cache accesses the data in the hybrid cache
  • only the division of the above-mentioned functional modules is used as an example for illustration. In actual applications, the above-mentioned functions can be changed according to needs.
  • the allocation is completed by different functional modules, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.
  • the device for accessing data in the hybrid cache provided by the foregoing embodiment and the embodiment of the method for accessing data in the hybrid cache belong to the same concept. For the specific implementation process, please refer to the method embodiment, which will not be repeated here.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or a data center integrated with one or more available media.
  • the usable medium can be a magnetic medium (for example: floppy disk, hard disk, tape), optical medium (for example: Digital Versatile Disc (DVD)), or semiconductor medium (for example: Solid State Disk (SSD) )Wait.

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Abstract

本申请公开了一种访问电子设备中的混合缓存的方法及装置，属于计算机存储技术领域。该方法包括：接收针对待访问数据的读指令。当在索引表中查找到待访问数据的逻辑地址时，则从索引表中获取待访问数据的状态信息，进而读取待访问数据。状态信息用于指示数据存储在易失性缓存中还是非易失性缓存中。也即是，本申请为混合缓存统一设置一个索引表，索引表中记录了混合缓存中所存储的数据的逻辑地址，并指示每个逻辑地址对应的数据是存储在DRAM中还是PCM中，这样在混合缓存中读取数据时，不管该数据存储在混合缓存的DRAM中还是PCM中，均仅需查找一次索引表即可确定该数据存储在哪种缓存中，从而提高了访问混合缓存中的数据的效率。

Description

访问电子设备中的混合缓存的方法及装置 技术领域
本申请涉及计算机存储技术领域，特别涉及一种访问电子设备中的混合缓存的方法及装置。
背景技术
随着大数据时代的到来，一种基于动态随机存储器(dynamic random access memory，DRAM)和相变存储器(phase change memory，PCM)的混合缓存逐渐受到人们的青睐。其中，相对于DRAM，PCM具有非易失性、低功耗和存储密度大等优势。但是相对于PCM，DRAM在写延迟上有一定优势，因此基于DRAM和PCM的混合缓存可以同时兼具两者的优点。由于混合缓存中包括两种不同类型的存储介质，因此，亟需研究一种访问混合缓存的方法。
相关技术中，为DRAM和PCM分别设置各自所存储数据的索引表。当处理器访问某个数据时，先根据DRAM的索引表确定DRAM中是否存储有这个数据。如果DRAM中未存储这个数据，则根据PCM的索引表确定PCM中是否存储有这个数据。如果PCM中存储这个数据，则从PCM中获取这个数据。基于上述描述，当需要在混合缓存中访问数据时，可能需要对DRAM和PCM对应的索引表分别进行查询，从而影响访问混合缓存的速度。
发明内容
本申请提供了一种访问电子设备中的混合缓存的方法及装置，可以提高访问混合缓存的速度。所述技术方案如下：
第一方面，提供了一种访问电子设备中的混合缓存的方法，该方法应用于电子设备，混合缓存包括易失性缓存和非易失性缓存。该方法包括：接收针对待访问数据的读指令，读指令中携带待访问数据的逻辑地址；在索引表中查找逻辑地址，索引表中存储有混合缓存中所存储数据的逻辑地址对应的状态信息，状态信息用于指示混合缓存中所存储数据是存储在易失性缓存中还是非易失性缓存中；当在索引表中查找到待访问数据的逻辑地址时，则从索引表中获取待访问数据的状态信息；根据待访问数据的状态信息从非易失性缓存或者易失性缓存中读取待访问数据。
当采用两级混合缓存时，如果DRAM和PCM分别设置各自的索引表，需要先查找DRAM的索引表，当所读取的数据不在DRAM的索引表中时，还需要查找PCM的索引表。这样，如果所读取的数据不在DRAM中时，还需要执行一次查找PCM索引表的过程，这将增加数据读取的时延。因此，在本申请实施例中，可以为混合缓存统一设置一个索引，该索引表中记录了混合缓存中所存储的数据的逻辑地址，并指示每个逻辑地址对应的数据是存储在DRAM中还是PCM中，这样在混合缓存中读取数据时，不管该数据存储在混合缓存的DRAM中还是PCM中，均仅需查找一次索引表即可确定该数据存储在哪种缓存中，从而提高了访问混合缓存中的数据的效率。
可选地，索引表中的每个逻辑地址对应有存储每个逻辑地址对应的数据的物理地址；相应地，该方法还包括：在从索引表中获取待访问数据的状态信息时，还获取待访问数据的物理地址。相应地，根据待访问数据的状态信息从非易失性缓存或者易失性缓存中读取待访问数据包括：根据待访问数据的状态信息及待访问数据的物理地址从非易失性缓存或者易失性缓存中读取待访问数据。
在本申请实施例中，索引表中的每个逻辑地址对应有存储每个逻辑地址对应的数据的物理地址，如此，在确定待访问数据的状态信息时还可以获取待访问数据的物理地址，进而根据状态信息和物理地址直接读取待访问数据，进一步提高了访问混合缓存中的数据的效率。
可选地，索引表包括一级索引表和多个二级索引表，一级索引表中的一级索引为逻辑地址中从高位到低位的排序中的前p个比特位上的比特值进行组合得到的2^p个比特值组合，p为正整数，每个比特值组合对应一个二级索引表指针，二级索引表指针用于指示多个二级索引表中的一个二级索引表，二级索引表用于存储逻辑地址和每个逻辑地址对应的物理地址，存储的逻辑地址为存储在混合缓存中的数据逻辑地址，且所存储的逻辑地址的前p个比特位与一级索引表中的二级索引表指针所对应的比特值组合中的比特值相同。在索引表中查找逻辑地址包括：在一级索引中查找待访问数据的逻辑地址的前p个比特位对应的比特值组合；根据比特值组合对应的二级索引表指针，从多个二级索引表中获取一个二级索引表；在二级索引表中查找待访问数据的逻辑地址。
在本申请实施例中，为了避免索引表的结构过于庞大，索引表可以包括一级索引表和多个二级索引表，这样便可在一级索引表中的值中配置二级索引表指针，以便于能够快速查找到二级索引表，从而提高查找待访问数据的逻辑地址的效率。
可选地，索引表的一级索引表还包括存储的各个逻辑地址对应的数据的状态信息，具体为：每个一级索引所对应的查询结果还包括一个状态信息集合，状态信息集合用于存储逻辑地址满足相应一级索引的数据的状态信息，二级索引表中存储逻辑地址顺序排列；从索引表包括的各个数据的状态信息中确定待访问数据的状态信息，包括：根据待访问数据的逻辑地址在获取的二级索引表中的排序，从一级索引对应的查询结果中包括的状态信息集合中确定待访问数据的状态信息。可选地，索引表的二级索引表还包括存储的各个逻辑地址对应的数据的状态信息具体为：二级索引表还用于存储每个逻辑地址对应的数据的状态信息；从索引表包括的各个数据的状态信息中确定待访问数据的状态信息，包括：在获取的二级索引表中确定待访问数据的状态信息。
在本申请实施例中，索引表中存储的各个逻辑地址对应的数据的状态信息可以设置在一级索引表中，也可以设置在二级索引表中，提高了索引表的灵活性。
可选地，二级索引表中的二级索引为逻辑地址中除p个比特位之外的其他q个比特位上的比特值，q为正整数，二级索引表中的每个二级索引对应的查询结果中包括一个逻辑地址集合，逻辑地址集合中的每个逻辑地址对应一个物理地址，且逻辑地址集合包括的逻辑地址为混合缓存中逻辑地址同时满足相应一级索引和相应二级索引的数据的逻辑地址。
当二级索引表按照上述设置配置时，可以避免二级索引表包括的项的数量过多，从而提高在二级索引表中查找信息的效率。
可选地，读取待访问数据之后，还包括：根据待访问数据的逻辑地址，从热度记录表中获取与待访问数据的逻辑地址对应的热度记录序列，热度记录表包括多个热度记录序列，每个热度记录序列对应一段逻辑地址区间，待访问数据的逻辑地址落在逻辑地址区间内，每个热度记录序列用于记录对应逻辑地址区间对应的数据的热度；更新所获取的热度记录序列所记录的热度。
在本申请实施例中，需要为混合缓存的易失性缓存中的数据配置热度记录，以便于后续根据热度记录确定易失性缓存中的哪些热数据需要淘汰成温数据。
可选地，每个热度记录序列包括多个比特位，每个比特位对应一个更新周期。相应地，更新所获取的热度记录序列所记录的热度，包括：获取当前时间对应的更新周期，将当前时间对应的更新周期对应的比特位更新为表示热度记录序列对应的逻辑地址对应的数据被访问过的标识。
在本申请实施例中，可以为比特位配置更新周期，在某个更新周期内只需更新该更新周期对应的比特位即可，以便于后续快速根据各个更新周期对应的比特位确定数据在最近一段时间内的访问热度。
可选地，该方法还包括：检测热度衰减指令；获取每个热度记录序列多个比特位中位于当前时间对应的更新周期之后的下一个更新周期对应的比特位；将每个热度记录序列中下一个更新周期对应的比特位上的比特值更新为标识热度记录序列对应的逻辑地址对应的数据未被访问过的标识；将每个热度记录序列中下一个更新周期确定为当前时间对应的更新周期。
如果在一段时间内某些数据频繁地被访问，将导致这些数据对应的热度记录序列中的比特位均被更新为表示热度记录序列对应的逻辑地址对应的数据被访问过的标识。后续如果这些数据继续被访问，那么热度记录序列将不能代表这些数据在最近一段时间内被访问的记录。因此，在本申请实施例中，还需通过上述方式对热度记录表中的热度记录序列进行热度衰减。
可选地，多个比特位按照指定顺序周期性地排列；热度记录表配置有时钟和指针，时钟在系统初始化之后按照设置的时长周期性地计时，指针在系统初始化时指向多个比特位中的一个比特位，在每次时钟的计时时长达到设置的时长时，触发指针按照排序切换指向下一个比特位；当前时间对应的更新周期对应的比特位为当前时间指针指向的比特位。通过指针和时钟的配置，可以快速确定多个比特位中各个比特位对应的更新周期。
可选地，检测热度衰减指令，包括：当当前时间到达热度记录表更新时间点时，则触发热度衰减指令，热度记录表更新时间点为系统初始化时配置的；和/或，当高热度记录序列在所有热度记录序列中所占的比例大于参考比例时，则触发热度衰减指令，高热度记录序列指高位比特位均为表示热度记录序列对应的逻辑地址对应的数据被访问过的标识的热度记录序列，高位比特位是指多个比特位中更新周期在当前时间之前参考时长内的比特位。也即是，可以在上述两种场景中进行热度衰减，提高了进行热度衰减的灵活性。
可选地，该方法还包括：根据热度记录表确定易失性缓存中所存储的数据的热度值；如果数据的热度值小于热度阈值，则将该数据淘汰至非易失性缓存中。由于热度记录表中的一个热度记录序列可以对应一段逻辑地址区间，因此，通过本申请实施例提供的淘汰数据的方式，可以利用热数据的空间局部性，同时对一 批数据进行处理，提高了淘汰热数据的效率。
可选地，根据热度记录表确定易失性缓存中所存储的数据的热度值之后，还包括：如果热度值小于热度阈值，则确定与该数据的逻辑地址相邻的逻辑地址对应的数据的热度值；确定数据和与数据的逻辑地址相邻的逻辑地址对应的数据的平均热度值；如果平均热度值大于或等于热度阈值，则保留数据在易失性缓存中。
为了提高由于偶然原因出现淘汰数据出现错误，如果某个数据的热度值小于热度阈值，并不急于将该数据淘汰至非易失性缓存，而是结合逻辑地址与该数据的逻辑地址相邻的数据的热度值，综合判断是否需要将该数据淘汰至非易失性缓存，提高了淘汰热数据的灵活性。
可选地，确定平均热度值之后，还包括：如果平均热度值小于热度阈值，则将数据淘汰至非易失性缓存中。
如果平均热度值小于热度阈值，表明与该数据的逻辑地址相邻的逻辑地址对应的数据大部分最近也没有被频繁地访问，此时，可以将该数据淘汰至非易失性缓存中，提高了淘汰热数据的灵活性。
可选地，根据热度记录表确定易失性缓存中所存储的数据的热度值之前，还包括：当检测到易失性缓存的剩余存储容量低于空闲容量阈值时，和/或，当检测到淘汰热数据指令时，执行根据热度记录表确定易失性缓存中所存储的数据的热度值的步骤。也即是，可以在以上两种场景来进行热数据淘汰，提高了淘汰热数据的灵活性。
可选地，多个比特位中每个比特位配置有一个时间权重，每个比特位的时间权重用于指示相应比特位上的比特值的更新时间距离当前时间的远近，多个比特位中当前时间待更新比特位的时间权重最大；根据热度记录表确定易失性缓存中所存储的数据的热度值，包括：获取热度记录表中每个热度记录序列包括的多个比特位的时间权重；根据每个热度记录序列包括的多个比特位的时间权重，将每个热度记录序列包括的多个比特位上的比特值进行加权求和，得到的求和值作为每个热度记录序列对应的逻辑地址区间对应的数据的热度值。这种确定热度值的方式可以使得确定的热度值能够指示该数据在当前时间最近一段时间内被访问的情况。具体地，热度值越大，表明该数据最近被访问的频率较高，热度值越小，表明该数据最近被访问的频率较低。
可选地，如果热度值大于热度阈值，则保留第一热度记录序列对应的逻辑地址的数据在易失性缓存中之前，还包括：如果当前时间到达热度阈值更新时间点，则从热度记录表中随机选择m个热度记录序列，m为大于或等于1的正整数，热度阈值更新时间点为系统初始化时配置的；根据m个热度记录序列中每个热度记录序列的热度值和易失性缓存中的期望存储数据比例，确定热度阈值，期望存储数据比例是指在易失性缓存中期望存储的数据的大小与在混合缓存中期望存储的数据的大小之间的比例。
为了使得热度阈值能够反映混合缓存中的当前数据访问情况，处理器可以定期动态调整热度阈值，以便于后续根据调整之后的热度阈值进行热数据淘汰，以使热数据淘汰后的易失性缓存的访问命中率较高。
该方法还包括：确定易失性缓存的访问命中率，访问命中率用于指示访问的数据为易失性缓存中的数据的比例；根据易失性缓存的访问命中率，确定m。其 中，随机选择的热度记录序列的个数也是根据当前混合缓存中的数据访问情况确定的，以便于后续根据调整之后的热度阈值进行热数据淘汰，以使热数据淘汰后的易失性缓存的访问命中率较高。
可选地，确定易失性缓存的访问命中率之后，还包括：根据易失性缓存的访问命中率，确定热度阈值更新时间点。另外，定期动态调整热度阈值的周期也可以根据当前混合缓存中的数据访问情况确定，以便于后续根据调整之后的热度阈值进行热数据淘汰，以使热数据淘汰后的易失性缓存的访问命中率较高。
第二方面，提供了一种访问电子设备中的混合缓存的装置，该装置具有实现上述第一方面中访问电子设备中的混合缓存的方法行为的功能。该装置包括至少一个模块，该至少一个模块用于实现上述第一方面所提供的访问电子设备中的混合缓存的方法。
第三方面，提供了一种访问电子设备中的混合缓存的装置，该装置的结构中包括处理器和存储器，存储器用于存储支持该装置执行上述第一方面所提供的访问电子设备中的混合缓存的方法的程序，以及存储用于实现上述第一方面所提供的访问电子设备中的混合缓存的方法所涉及的数据。处理器被配置为用于执行存储器中存储的程序。存储设备的操作装置还可以包括通信总线，该通信总线用于该处理器与存储器之间建立连接。
第四方面，提供了一种计算机可读存储介质，计算机可读存储介质中存储有指令，当该指令在计算机上运行时，使得计算机执行上述第一方面的访问电子设备中的混合缓存的方法。
第五方面，提供了一种包含指令的计算机程序产品，当该计算机程序产品在计算机上运行时，使得计算机执行上述第一方面所述的访问混合缓存中的数据的方法。
上述第二方面、第三方面、第四方面和第五方面所获得的技术效果与第一方面中对应的技术手段获得的技术效果近似，在这里不再赘述。
附图说明
图1是本申请实施例提供的一种电子设备的结构示意图；
图2是本申请实施例提供的一种处理器访问数据的流程示意图；
图3是本申请实施例提供的一种访问电子设备中的混合缓存的方法流程图；
图4是本申请实施例提供的一种索引表的示意图；
图5是本申请实施例提供的一种记录热度的方法流程图；
图6是本申请实施例提供的一种热度记录表的示意图；
图7是本申请实施例提供的一种热度衰减方法流程图；
图8是本申请实施例提供的一种热数据淘汰方法流程图；
图9是本申请实施例提供的一种访问电子设备中的混合缓存的装置示意图；
图10是本申请实施例提供的另一种访问电子设备中的混合缓存的装置示意图；
图11是本申请实施例提供的另一种访问电子设备中的混合缓存的装置示意图；
图12是本申请实施例提供的另一种访问电子设备中的混合缓存的装置示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
图1是本申请实施例提供的一种电子设备的结构示意图。如图1所示，该电子设备包括至少一个处理器101，总线102、混合缓存104、外存105以及至少一个通信接口106。
处理器101可以是一个通用中央处理器(central processing unit，CPU)或一个或多个用于控制本申请方案程序执行的集成电路。每个处理器可以是一个单核(single-CPU)处理器，也可以是一个多核(multi-CPU)处理器。这里的处理器可以指一个或多个设备、电路、和/或用于处理数据(例如计算机程序指令)的处理核。
总线102用于连接处理器101、内存103、混合缓存104以及外存105之间传送信息。该总线102除包括数据总线之外，还可以包括电源总线和控制总线等。但是为了清楚说明起见，在图中将各种总线都标为总线102。
混合缓存104作为电子设备的内存，包括易失性缓存103和非易失性缓存107，且易失性缓存103中可以划分出两个区域，这两个区域分别称之为写数据缓存1031和读数据缓存1032。写数据缓存1031用于为处理器101执行写数据操作提供缓存。写数据缓存1031中的数据按照一定的算法下刷至外存105中。本申请实施例并不限定将写数据缓存1031中的数据下刷至外存105的具体实现方式。
读数据缓存1032和非易失性缓存107用于为处理器101执行读数据操作提供两级的缓存。
上述易失性缓存103可以为随机存取存储器(random access memory，RAM)、DRAM等。非易失性缓存107可以为PCM、铁电存储器、或者磁式存储器等新型的非易失性存储设备。
另外，外存105可以是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其它类型的静态存储设备，也可以是电可擦可编程只读存储器(electrically erasable programmable read-only memory，EEPROM)、只读光盘(compact disc read-only Memory，CD-ROM)或其它光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其它磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其它介质，但不限于此。
另外，读数据缓存1031还用于存储执行本申请方案的程序代码，并由处理器101来控制执行。程序代码中可以包括一个或多个软件模块。
通信接口106，使用任何收发器一类的装置，用于与其它设备或通信网络通信，如以太网，无线接入网(RAN)，无线局域网(wireless local area networks，WLAN)等。
上述的计算机设备可以是一个通用计算机设备或者是一个专用计算机设备。在具体实现中，计算机设备可以是台式机、便携式电脑、网络服务器、掌上电脑(Personal Digital Assistant，PDA)、移动手机、平板电脑、无线终端设备、通信设备或者嵌入式设备。本申请实施例不限定计算机设备的类型。
基于上述图1所示，计算机设备中包括写数据缓存1031、读数据缓存1032和非易失性缓存107、以及外存105这三类不同功能的存储介质。处理器在访问数据时，可以按照一定的顺序依次访问这三类存储介质。图2是本申请实施例提供的一种处理器访问数据的流程示意图。如图2所示，处理器在访问数据时，先从写数据缓存1031中访问该数据。如果写数据缓存1031中不存在该数据，则从读数据缓存1032和非易失性缓存107中访问该数据。如果读数据缓存1032和非易失性缓存107中不存在该数据，则从外存105中访问该数据。
图2中的读数据缓存1032用于存储读数据缓存1032和非易失性缓存107这个两级缓存的索引表及热数据。索引表包括读数据缓存1032中存储的数据的索引，以及非易失性缓存107中存储的数据的索引。
非易失性缓存107用于存储从读数据缓存1032中淘汰下来的温数据。本申请实施例提供了一种数据热度识别算法、及一种数据淘汰算法，数据热度识别算法用于识别读数据缓存1032中所存储数据的热度。数据淘汰算法用于根据所识别的数据的热度将读数据缓存1032中的数据淘汰至非易失性缓存107中，后续实施例将对此进行详细解释说明，在此就先不阐述。
另外，如图2所示，非易失性缓存107也可以按照一定的策略对存储的数据进行淘汰，并将淘汰的冷数据存储至外存105中。关于将非易失性缓存107中的数据淘汰至外存105的解释可以参考现有的缓存淘汰的相关技术，本申请实施例对此不做详细阐述。
本申请实施例中，数据根据被访问的频率划分为热数据、温数据、及冷数据。访问频率大于等于第一预设值的为热数据、访问频率小于第一预设值大于第二预设值的为温数据、访问频率小于等于第二预设值的数据为冷数据。
接下来对本申请实施例提供的访问电子设备中的混合缓存的方法进行解释说明。需要说明的是，本申请实施例中访问的混合缓存具体是指图1和图2中的读数据缓存1032和非易失性缓存107这个两级缓存，其中，访问的混合缓存中的易失性缓存具体是指图1和图2中的读数据缓存1032，后续不再一一解释。
图3是本申请实施例提供的一种访问电子设备中的混合缓存的方法流程图。应用于图1所示的电子设备的处理器中。如图3所示，该方法包括如下步骤：
步骤301：接收针对待访问数据的读指令，读指令中携带待访问数据的逻辑地址。
基于图2所示的处理访问数据的流程可知，当处理器接收到读指令时，先确定写数据缓存中是否存储有该待访问数据。如果写数据缓存中存储有该待访问数 据，则直接读取该待访问数据。如果写数据缓存中不存在该待访问数据，则确定读数据缓存和非易失性缓存这个两级混合缓存中是否存储有该待访问数据。本申请实施例提供的访问电子设备中的混合缓存的方法可以应用于该场景中。
对于混合缓存，如果DRAM和PCM分别设置各自的索引表，混合缓存中每种缓存的索引表用于指示该缓存中的存储的数据的逻辑地址和物理地址之间的映射关系则在读取数据时，需要先查找DRAM的索引表，当所读取的数据不在DRAM的索引表中时，还需要查找PCM的索引表。
这样，如果所读取的数据不在DRAM中时，还需要执行一次查找PCM索引表的过程，这将增加数据读取的时延。因此，在本申请实施例中，可以为混合缓存统一设置一个索引表，索引表中记录了混合缓存中所存储的数据的逻辑地址，并指示每个逻辑地址对应的数据是存储在DRAM中还是PCM中，这样在混合缓存中读取数据时，不管该数据存储在混合缓存的DRAM中还是PCM中，均仅需查找一次索引表即可确定该数据存储在哪种缓存中，从而提高了访问混合缓存中的数据的效率。
为了后续便于说明，在此先对本申请实施例提供的索引表进行解释说明。
图4是本申请实施例提供的一种索引表的示意图。该索引表中记录了混合缓存中存储的数据的逻辑地址、每个逻辑地址对应的物理地址，以及每个逻辑地址对应的数据的状态信息，状态信息用于指示逻辑地址对应的数据是存储在DRAM中，还是存储在PCM中。如图4所示，索引表可以包括一级索引表401(entry table)和多个二级索引表402(node table)。为了后续便于说明，将一级索引表中的索引称为一级索引，将二级索引表中的索引称为二级索引。
一级索引可以为逻辑地址中p个比特位上的比特值进行组合得到的2^p个比特值组合。p为正整数。这p个比特位可以为从高位到低位的排序中的前p个比特位。
由于p个比特位上的比特值可以组合得到2^p个不同的比特值组合，而图4中的索引表中用于记录混合缓存中的数据的逻辑地址、逻辑地址对应的物理地址、以及每个逻辑地址对应的数据的状态信息。虽然不是所有逻辑地址中的数据均存储在混合缓存中，但是为了避免后续在混合缓存中的数据发生变化时，一级索引表中需要频繁地添加或删除某项信息。因此，如图4所示，一级索引表可以包括2^p项信息。每项信息包括一个一级索引和该一级索引所对应的查询结果。一级索引表中每个一级索引所对应的查询结果包括一个二级索引表指针和一个状态信息集合。也即是，每个比特值组合对应一个二级索引表指针和一个状态信息集合。如此，后续当混合缓存中数据发生变化时，只需要更新各个一级索引对应的查询结果即可，而无需更改整个一级索引表的结构。
对于一级索引表中的任一一级索引，该一级索引所对应的查询结果中的状态信息集合包括二级索引表指针所指示的二级索引中所确定的逻辑地址所指示数据的状态信息。由于不是所有逻辑地址中的数据均存储在混合缓存中，因此，对于该一级索引对应的状态信息集合，该状态信息集合中只包括混合缓存中逻辑地址前p个比特位与该一级索引所对应的比特值组合中的比特值相同的数据的状态信息。比如，如果混合缓存中逻辑地址前p个比特位与该一级索引所对应的比特值组合中的比特值相同的数据的个数为1个，那么该状态信息集合中的状态信息的 个数为1个。如果混合缓存中逻辑地址前p个比特位与该一级索引所对应的比特值组合中的比特值相同的数据的个数为多个，那么该状态信息集合中的状态信息的个数为多个。如果混合缓存中不存在逻辑地址前p个比特位与该一级索引所对应的比特值组合中的比特值相同的数据，那么该状态信息集合中的状态信息的个数为0。
对于一级索引表中的任一一级索引，该一级索引所对应的查询结果中的二级索引表指针用于指示多个二级索引表中的一个二级索引表，也即是，图4中一级索引表的每项信息对应一个二级索引表。该二级索引表中用于记录逻辑地址和每个逻辑地址对应的物理地址，记录的逻辑地址为混合缓存中逻辑地址满足相应一级索引的数据逻辑地址，逻辑地址满足相应一级索引是指：逻辑地址前在p个比特位上的比特值与相应一级索引所指示的p个比特位上的比特值组合中的比特值相同。也即是，二级索引表中的存储的逻辑地址为存储在混合缓存中的数据逻辑地址，且所存储的逻辑地址的前p个比特位与一级索引表中的该二级索引表指针所对应的比特值组合中的比特值相同。其中，二级索引表中记录逻辑地址的实现方式可以为：记录逻辑地址中除p个比特位之外的其他位的值，或者，记录逻辑地址在全部比特位上的比特值。
比如，逻辑地址包括32个比特位，可以将逻辑地址中高10位上的比特位作为一级索引表的一级索引，此时，图4所示的一级索引表包括2^10项信息，每项信息对应一个二级索引表。假设一级索引表中第一项信息包括的一级索引为0000000000，也即是，高10位比特位上的比特值均为0。此时，0000000000这个一级索引所对应的查询结果中的状态信息集合包括混合缓存中逻辑地址的高10位上的比特值均为0的所有数据的状态信息。0000000000这个一级索引所对应的查询结果中的二级索引表指针所指示的二级索引表用于记录混合缓存中逻辑地址的高10位上的比特值均为0的所有数据的逻辑地址和每个逻辑地址对应的物理地址。其中，对于该二级索引表，由于该二级索引表是0000000000这个一级索引对应的二级索引表，表明该二级索引表中记录的逻辑地址的前p个比特位上的比特值为0000000000。因此，该二级索引表中记录的混合缓存中的各个数据的逻辑地址可以只记录逻辑地址在剩余22个比特位上的比特值。当然，该二级索引表中记录的混合缓存中的各个数据的逻辑地址也可以记录逻辑地址在全部32个比特位上的比特值，对此不做具体限定。
又比如，对于任一一级索引，假设该一级索引对应的查询结果中的状态信息集合为数据1、数据2、数据3至数据100这100个数据中每个数据的状态信息。那么该一级索引所对应的查询结果中的二级索引表指针指示的二级索引表用于存储这100个数据中每个数据的逻辑地址。
并且，二级索引表中存储的多个数据的逻辑地址的排序和状态信息集合中多个数据的状态信息的排序对应。比如，状态信息集合中的各个数据的状态信息的排序可以和二级索引表中的各个数据的逻辑地址的排序一致。排序一致是指：状态信息的排序结果和逻辑地址的排序结果中，处于同一位置的状态信息和逻辑地址对应同一个数据。比如，上述100个数据的状态信息按照数据1的状态信息、数据2的状态信息、数据3的状态信息、…、数据100的状态信息排序。这100个数据在二级索引表中的逻辑地址也按照数据1的逻辑地址、数据2的逻辑地址、 数据3的逻辑地址、…、数据100的逻辑地址这种方式排列。这样可以保证状态信息的排序结果和逻辑地址的排序结果中，处于同一位置的状态信息和逻辑地址对应同一个数据。
其中，将状态信息集合中各个状态信息的排序和二级索引表中各个逻辑地址的排序对应设置，以便于后续根据某个数据的逻辑地址在二级索引表中的位置，可以直接从状态信息集合中获取对应位置的状态信息作为这个数据的状态信息，从而提高状态信息的获取效率。
另外，为了便于管理二级索引表中的地址，二级索引表中的二级索引可以为逻辑地址中q个比特位上的比特值。这q个比特位可以为逻辑地址中除了一级索引的p个比特位之外的其他比特位。比如，可以为逻辑地址中低位到高位排序中前q个比特位。此时，由于q个比特位上的比特值可以组合得到2^q个不同的组合比特值，和一级索引表同样的原因，为了避免后续由于混合缓存中的数据发生变化，导致二级索引表中的项需要不停地删除或者添加，因此，对于一级索引表中的任一一级索引，该一级索引所对应的二级索引表指针所指示的二级索引表包括2^q项信息，每一项信息包括一个二级索引和该二级索引所对应的查询结果。对于二级索引表中的任一二级索引，该二级索引所对应的查询结果为一个逻辑地址集合，该逻辑地址集合中每个逻辑地址对应一个物理地址，且逻辑地址集合包括的逻辑地址为混合缓存中逻辑地址同时满足相应一级索引和相应二级索引的数据的逻辑地址。也即是，逻辑地址集合包括的逻辑地址不仅在q个比特位上的比特值与该二级索引所指示的比特值相同，还在上述p个比特位上的比特位与该二级索引所对应的一级索引所指示的比特值相同。另外，由于不是所有逻辑地址中的数据均存储在混合缓存中，因此，逻辑地址集合中的逻辑地址的个数可以为任一整数，且二级索引表中各个二级索引对应的逻辑地址集合可以不同。
比如，可以将逻辑地址中低10位上的比特位作为二级索引表的二级索引，此时，假设一级索引表中第一项信息包括的一级索引为0000000000，该一级索引所对应的二级索引表包括2^10项信息，每项信息包括一个二级索引和该二级索引所对应的查询结果。假设该二级索引表中第一项信息包括的二级索引为0000000000。此时，该二级索引所对应的查询结果所指示的逻辑地址集合包括混合缓存中逻辑地址同时满足低10位和高10位上的比特值均为0的数据的逻辑地址和每个逻辑地址对应的物理地址。
也即是，在图4所示的索引表中，一级索引表包括2^p项信息，且每项信息均对应一个二级索引表，该二级索引表中包括2^q项信息，每项信息包括一个逻辑地址集合。假设每个逻辑地址集合中包括k个逻辑地址和与k个逻辑地址一一对应的k个物理地址。因此，对于一级索引表中任一项信息指示的二级索引表，该二级索引表中包括(2^q)×k个逻辑地址和每个逻辑地址对应的物理地址。并且，该二级索引表对应的一级索引表中的一项信息中的状态信息集合中包括(2^q)×k的状态信息。其中，k为正整数，上述k仅仅是对逻辑地址集合中包括的逻辑地址的数量的一种举例说明，并不构成对逻辑地址集合中包括的逻辑地址的数量的限定
在系统初始化时，可以先配置图4所示的索引表，此时索引表中一级索引表的状态信息集合和二级索引表中的逻辑地址集合此时可以为空值。后续当混合缓 存中新增或删除数据时，只需更新索引表中的状态信息集合和逻辑地址集合中的具体元素即可，无需对索引表的结构进行更改。
如图4所示，索引表是直接根据数据的逻辑地址、逻辑地址对应的物理地址和状态信息集合映射而成的，无需通过复杂的哈希计算来构建索引表，提高了构建索引表的效率。另外，由于索引表中的一级索引表和二级索引表均是采用逻辑地址中的部分比特位作为索引的，因此，可以使得相邻的逻辑地址在索引表中的存储位置也相邻。而热数据通常具有空间局部性，也即是，一段逻辑地址区间的数据通常均为热数据，因此，本申请实施例提供的索引表还可以充分利用热数据的空间局部性，以便于后续根据索引表对热数据进行成批处理，进一步提高处理热数据的灵活性。
另外，在本申请实施例中，可以将索引表配置为图4所示的一级索引表和二级索引表。在其他实现方式中，还可以为索引表配置更多级别的索引表，比如，可以在索引表中配置一级索引表、二级索引表和三级索引表，配置方式和上述图4所示的配置方式基本相同。或者，也可以仅仅设置一级索引表，在此就不在一一展开说明。
另外，在图4所示的一级索引表中，每个状态信息可以采用1个比特位来指示对应的数据存储在易失性缓存还是非易失性缓存中。比如，该1个比特位上的值为1时，表明相应数据存储在易失性缓存中。该1个比特位上的值为0时，表明相应数据存储在非易失性缓存中。
在图4所示的索引表中，状态信息是配置在一级索引表中的。具体应用时，也可以将状态信息配置在二级索引表中。此时，在图4所示的索引表中，一级索引表包括2^p项信息，每项信息包括一个一级索引和一级索引对应的查询结果，该一级索引对应的查询结果包括一个二级索引表指针。每个一级索引对应的二级索引表指针均对应一个二级索引表，该二级索引表中包括2^q项信息，每项信息包括一个逻辑地址集合，每个逻辑地址集合中包括逻辑地址、与每个逻辑地址对应的物理地址和每个逻辑地址对应的数据的状态信息。
也即是，在本申请实施例中，索引表中存储的各个逻辑地址对应的数据的状态信息可以如图4所示设置在一级索引表中，当然也可以设置在二级索引表中，在此不做具体限定。
另外，为了进一步提高在索引表中查找数据的效率，图4所示的索引表可以以键值(key-value)的方式存储。以键值的方式存储索引表是指：对于一级索引表或二级索引表，将表中的索引作为键，将每个索引对应的查询结果作为值进行存储。由于键值结构的数据在查询时可以直接在索引表中定位需要查找的数据，而无需遍历整个索引表才能查找到相应数据，因此，通过键值的方式存储索引表可以提高后续查找数据的效率。
步骤302：在索引表中查找该逻辑地址。
基于图4所示的索引表，步骤302的实现方式可以为：在一级索引中查找待访问数据的逻辑地址的前p个比特位对应的比特值组合；根据该比特值组合对应的二级索引表指针，从多个二级索引表中获取一个二级索引表；在该二级索引表中查找待访问数据的逻辑地址。
具体地，可以确定待访问数据的逻辑地址中p个比特位上的比特值，将待访 问数据的逻辑地址中p个比特位上的比特值作为一级索引，从一级索引表中查找该一级索引所对应的查询结果。该查询结果包括一个二级索引表指针。根据该二级索引表指针从图4所示的多个二级索引表中获取一个二级索引表。确定待访问数据的逻辑地址中q个比特位上的比特值，将待访问数据的逻辑地址中q个比特位上的比特值作为二级索引。从前述获取的二级索引表中查找该二级索引所对应的查询结果，该查询结果为一个逻辑地址集合。然后遍历该逻辑地址集合，如果在该逻辑地址集合中遍历到待访问数据的逻辑地址，则确定索引表中存储有待访问数据的逻辑地址。
步骤303：当在索引表中查找到待访问数据的逻辑地址时，则从索引表中获取待访问数据的状态信息。
基于步骤302可知，索引表的一级索引表或二级索引表还包括存储的各个逻辑地址对应的数据的状态信息。因此，在通过步骤302在二级索引表中查找到待访问数据的逻辑地址时，便可从索引表包括的各个数据的状态信息中确定待访问数据的状态信息。
在一种可能的实现方式中，如果是索引表的一级索引表还包括存储的各个逻辑地址对应的数据的状态信息，如图4所示，每个一级索引所对应的查询结果还包括一个状态信息集合，该状态信息集合用于存储逻辑地址满足相应一级索引的数据的状态信息，该二级索引表中存储逻辑地址顺序排列。此时，从索引表包括的各个数据的状态信息中确定待访问数据的状态信息的实现方式可以为：根据待访问数据的逻辑地址在获取的二级索引表中的排序，从一级索引对应的查询结果中包括的状态信息集合中确定待访问数据的状态信息。
比如，一级索引表中的状态信息集合中的各个数据的状态信息的排序可以和二级索引表中的各个数据的逻辑地址排序一致。排序一致的解释已在上述图4所示的索引表中进行了解释。此时，如果根据一级索引查找到的二级索引表中包括50项信息，二级索引表中每项信息包括的二级索引所对应的查询结果为一个逻辑地址集合，且每个逻辑地址集合中包括8个逻辑地址，这8个逻辑地址按照顺序排列。假设根据待访问数据的逻辑地址确定的二级索引是这50个项信息中的第26项信息包括的二级索引，且待访问数据的逻辑地址在该二级索引对应的逻辑地址集合中的排序为第4个，则可以将状态信息集合中第204(也即是，(26-1)*8+4)个状态信息作为待访问数据的状态信息。
当然，一级索引表中的状态信息集合中的各个状态信息的排序也可以和二级索引表中的各个键对应的值中的逻辑地址排序恰好相反，此时，同样可以根据该排序相应地从状态信息集合中获取待访问数据的状态信息，在此不再详细阐述。
在另一种可能的实现方式中，如果是索引表的二级索引表还包括存储的各个逻辑地址对应的数据的状态信息。也即是，二级索引表还用于存储每个逻辑地址对应的数据的状态信息。此时，从索引表包括的各个数据的状态信息中确定待访问数据的状态信息的实现方式可以为：在获取的二级索引表中确定待访问数据的状态信息。
另外，基于上述图4所示的内容可知，二级索引表中还存储有的各个逻辑地址对应的物理地址，因此，在通过步骤302在二级索引表中查找到待访问数据的逻辑地址时，便可直接获取该待访问数据的的物理地址。
步骤304：根据待访问数据的状态信息从非易失性缓存或者易失性缓存中读取待访问数据。
基于步骤303可知，在从索引表中获取待访问数据的状态信息时，还获取待访问数据的物理地址。因此，步骤304的实现方式可以为：根据待访问数据的状态信息及待访问数据的物理地址从非易失性缓存或者易失性缓存中读取待访问数据。
具体地，在根据步骤303确定出待访问数据的状态信息后，如果待访问数据的状态信息所指示的存储位置为易失性缓存，则根据待访问数据的物理地址从易失性缓存中访问待访问数据。如果待访问数据的状态信息所指示的存储位置为非易失性缓存，则根据待访问数据的物理地址从非易失性缓存中访问待访问数据。另外，在通过非易失性缓存中访问待访问数据后将待访问数据从非易失性缓存复制至易失性缓存中，以便于后续直接通过易失性缓存访问待访问数据。
步骤305：当在索引表中没有查找到待访问数据的逻辑地址时，从外存中读取待访问数据。
在步骤302中遍历该逻辑地址集合的过程中，由于索引表是针对混合缓存配置的索引表，因此，如果待访问数据存储在混合缓存中，那么在该逻辑地址集合中是可以遍历到待访问数据的逻辑地址的。相应地，如果待访问数据没有存储在混合缓存中，那么在该逻辑地址集合中是无法遍历到待访问数据的逻辑地址的。这种情况下，处理器确定待访问数据存储在外存中，进而便可从外存中读取该待访问数据。在通过外存访问待访问数据后将待访问数据从外存复制至易失性缓存中，以便于后续直接通过易失性缓存访问待访问数据。
本申请实施例提供的混合缓存中包括两种不同类型的缓存介质，并且易失性缓存中用于存储热数据，非易失性缓存中用于存储从热数据中淘汰下来的温数据。基于该场景，需要为混合缓存的易失性缓存中的数据配置热度记录，以便于后续根据热度记录确定易失性缓存中的哪些数据需要淘汰成温数据。其中，热度记录也即是数据的访问频率记录。
因此，本申请实施例还提供了一种热度记录表，如图6所示，热度记录表包括多个热度记录序列，每个热度记录序列采用CNT标记。每个热度记录序列对应一段逻辑地址区间(图未示)，该逻辑地址区间可以包括一个逻辑地址，也可以包括多个相邻的逻辑地址，逻辑地址区间中的逻辑地址为易失性缓存中存储的热数据的逻辑地址。由于易失性缓存中的数据是动态变化的，因此，在本申请实施例中，如果检测到易失性缓存中新增或删除数据，则确定该新增或删除的数据的逻辑地址，并在图6所示的热度记录表中将该新增或删除数据的逻辑地址对应的热度记录序列进行更新，以保证热度记录表用于指示当前时间易失性缓存中的存储的所有的数据的访问热度。为了方便描述，图6只示出了热度记录序列，没有示出每个热度记录序列对应的逻辑地址空间。
如图6所示，每个热度记录序列包括多个比特位，在每次访问该热度记录序列对应的逻辑地址区间中的逻辑地址的数据时，更新这多个比特位上一个比特位的比特值，以实现该热度记录序列能够指示逻辑地址在对应的逻辑地址区间中的数据在最近一段时间内的访问情况。详细的更新方式将在下述实施例中说明，在 此先不展开阐述。
因此，在步骤303中，访问待访问数据之后，还需通过下述步骤对热度记录表进行更新。图5是本申请实施例提供的一种热度记录方法流程图，应用于图1所示的电子设备的处理器中。如图5所示，该方法包括如下步骤：
步骤501：根据待访问数据的逻辑地址，从热度记录表中获取与待访问数据的逻辑地址对应的热度记录序列。
由于热度记录表中的每个热度记录序列对应一段逻辑地址区间，因此，可以直接根据待访问数据的逻辑地址，从热度记录表中获取与待访问数据的逻辑地址对应的热度记录序列。
步骤502：更新所获取的热度记录序列所记录的热度。
在本申请实施例中，可以为每个比特位配置一个更新周期。如此，在某个更新周期内只需更新该更新周期对应的比特位即可，以便于后续快速根据各个更新周期对应的比特位确定数据在最近一段时间内的访问热度。
此时，步骤502的实现方式可以为：获取当前时间对应的更新周期，将当前时间对应的更新周期对应的比特位更新为表示热度记录序列对应的逻辑地址对应的数据被访问过的标识。表示热度记录序列对应的逻辑地址对应的数据被访问过的标识可以为第一比特值。比如，第一比特值可以为1，用于指示待访问数据当前被访问过。
在本申请实施例中，为了通过热度记录序列指示对应的逻辑地址区间中的逻辑地址对应的数据在最近一段时间内的访问情况，可以为热度记录表配置一个时钟和指针。在计算机设备初始化之后，该时钟按照设置的时长周期性地计时，这个热度记录序列包括的多个比特位按照指定顺序周期性地排列，并在初始化时将指针指向多个比特位中的一个比特位。每次当该时钟的计时达到一个周期时，将该指针按照多个比特位的排序指向下一个比特位。此时，步骤502中当前时间对应的更新周期对应的比特位即为当前时间该指针所指向的比特位。其中，当前时间对应的更新周期对应的比特位也可以称为当前时间待更新比特位。通过这种方式的配置，可以使得排序中位于当前时间待更新比特位之前的比特位中，距离当前时间待更新比特位越近的比特位上的比特值用于指示距离当前时间较近的时间段内数据被访问的情况，距离当前时间待更新比特位越远的比特位上的比特值用于指示距离当前时间较远的时间段内数据被访问的情况。
如图6所示，每个热度记录序列标记为CNT，每个CNT包括8个比特位。这8个比特位分别标记为比特位A、比特位B、比特位C、比特位D、比特位E、比特位F、比特位G、比特位H。假设配置的时钟的计时时长为1小时，这8个比特位按照A、B、C、D、E、F、G、H、A、B、C、D、E、F、G、H、…A、B、C、D、E、F、G、H的顺序周期性地排列。在系统初始化时，指针指向比特位A。当时钟的计时时长达到1小时时，指针从比特位A切换指向比特位B，且时钟重新开始计时。当时钟的计时时长再次达到1小时时，指针从比特位B切换指向比特位C，且时钟重新开始计时。依次类推，假设在某次时钟的计时时长达到1小时时，指针从比特位G切换指向比特位H，且时钟重新开始计时。那么在下次时钟的计时时长达到1小时时，指针从比特位H切换指向比特位A，且时钟重新开始计时。时钟和指针重复上述过程。
如图6所示，指针当前时间指向的比特位为比特位A，则确定比特位A为当前时间对应的更新周期对应的比特位，将比特位A上的比特值更新为1，用于指示待访问数据在当前时间被访问过。
另外，对于图6中的热度记录序列，为了便于记录各个比特位上的比特值的更新时间与当前时间之间的远近，预先配置与多个比特位个数相同的时间权重，该时间权重可以指示距离当前时间的远近，其中时间权重越大距离当前时间越近，时间权重越小距离当前时间越远。在每次指针切换指向一个比特位时，确定多个比特位基于指定顺序排列成一个封闭的环中位于指针指向的比特位的下一个比特位，以下一个比特位为起点，按照该指定顺序对这多个比特位进行排序，将预先配置的多个时间权重分配给排序后的多个比特位，排序后的各个比特位的时间权重依次降低。如此，每当时钟的计时时长到达，指针切换指向的比特位时，便更新各个比特位上的时间权重，以使指针指向的比特位在任何时间的时间权重均最大，且指针下一次即将指向的比特位的时间权重最小。
比如，预先配置了8个时间权重，分别标记为L0、L1、L2、L3、H0、H1、H2与H3。这8个时间权重依次增大。图6中的8个比特位分别标记为A、B、C、D、E、F、G、H。且这8个比特位按照A、B、C、D、E、F、G、H的顺序排列成一个封闭的环。如果当前时间指针指向比特位C，则按照下述表1中的分配方式将各个时间权重分配给各个比特位。
表1
Figure PCTCN2020097274-appb-000001
又比如，如果当前时间指针指向比特位D，则按照下述表2中的分配方式将各个时间权重分配给各个比特位。
表2
Figure PCTCN2020097274-appb-000002
又比如，如图6所示，当前时间指针指向比特位A，则按照下述表3中的分配方式将各个时间权重分配给各个比特位。
表3
Figure PCTCN2020097274-appb-000003
在图6所示的热度记录序列中，指针是按这8个比特位按照指定顺序周期性排列后指向其中一个比特位，因此，在指针指向某个比特位的时间内，该比特位上的比特值可能在上一个循环周期内已经被更新过，此时，将导致这些数据对应的热度记录序列无法表征数据在最近一段时间内的访问情况。因此，在本申请实施例中，还需对热度记录表中的热度记录序列进行热度衰减。
图7是本申请实施例提供的一种热度衰减方法流程图，应用于图1所示的电 子设备的处理器中。图7所示，该方法包括如下步骤：
步骤701：检测热度衰减指令。
处理器可以在以下两种场景中检测到热度衰减指令。
第一种场景：计算机设备在系统初始化时配置有热度记录表更新时间点。因此，当当前时间到达热度记录表更新时间点，此时计算机设备将自动触发热度衰减指令。比如，在计算机设备的系统初始化时，可以配置每隔1天更新热度记录表，假设计算机设备的系统初始化时间点为0:00，那么热度记录表更新时间点为每天的0:00。
第二种场景：当高热度记录序列在所有热度记录序列中所占的比例大于参考比例时，此时，可以触发热度衰减指令。高热度记录序列指高位比特位均为表示热度记录序列对应的逻辑地址对应的数据被访问过的标识的热度记录序列。其中，高位比特位是指多个比特位中更新周期在当前时间之前参考时长内的比特位，也即是，高位比特位是指当前时间之前最近一段内更新的比特位。由于各个比特位可以根据时间权重来确定更新比特位上的比特值的时间距离当前时间的远近，因此，高位比特位可以指热度记录序列的多个比特位中时间权重从高到低的n个比特位，n为大于或等于1的正整数。
假设在当前时间各个比特位上的时间权重如表2所示，则高位比特位可以是比特位D，也可以是比特位B和比特位D等等。如果高位比特位是比特位D，则高热度记录序列为比特位D为1的热度记录序列，如果参考比例是90％，则高热度记录序列在所有热度记录序列中所占的比例大于90％，则触发热度衰减指令。
上述两种场景可以单独使用，可以结合使用，本申请实施例对此不做具体限定。
步骤702：获取每个热度记录序列多个比特位中位于当前时间对应的更新周期之后的下一个更新周期对应的比特位。
如表2所示，只要确定当前时间指针指向的比特位，便可确定多个比特位上每个比特位的时间权重，此时，时间权重最小的比特位便为下一个更新周期对应的比特位。如图6所示，在热度衰减前，下一个更新周期对应的比特位为比特位H。
步骤703：将每个热度记录序列中下一个更新周期对应的比特位更新为表示热度记录序列对应的逻辑地址对应的数据未被访问过的标识。
在步骤702中，则可以将所有热度记录序列中时间权重为L0上的比特值更新为第二比特值，本实施例中，该第二比特值为零。为了后续便于说明，将步骤703称为重置操作。如图6所示，可以将所有热度记录序列中比特位H上的比特值重置为0。
步骤704：将每个热度记录序列中下一个更新周期对应的比特位确定为当前时间对应的更新周期对应的比特位。
在步骤703中，可以将指针直接指向下一个更新周期对应的比特位即可实现将每个热度记录序列中下一个更新周期对应的比特位确定为当前时间对应的更新周期对应的比特位。由于计算机设备在每次指针切换指向的比特位时，均会为各个比特位重新分配时间权重，因此，在步骤703中，在将每个热度记录序列中下一个更新周期对应的比特位确定为当前时间对应的更新周期对应的比特位之后，各个比特位的时间权重相当于进行了顺序转移。为了后续便于说明，将步骤704 称为权重转移操作。
比如，假设执行步骤703之前，各个比特位上的时间权重如表1所示，那么在执行步骤703之后，各个比特位上的时间权重便更新为表2所示的情况。
表4
Figure PCTCN2020097274-appb-000004
又比如，如图6所示，在热度衰减之前，各个比特位上的时间权重如上述表3所示，在热度衰减之后，各个比特位上的时间权重如下述表4所示。
另外，在本申请实施例中，不同的热度记录序列中同一时间权重对应的比特位存储在一段连续的地址空间中。如图6所示，时间权重L0对应的所有热度记录序列的比特位存储在一段连续的地址空间中，时间权重L1对应的所有热度记录序列的比特位存储在一段连续的地址空间中等。因此，处理器在执行步骤703时，由于所有热度记录序列中下一次待更新的比特位存储在一段连续的地址空间中，此时，只需要对这段连续的地址空间中的比特位的比特值统一重置为0即可。处理器在执行步骤704时，也是针对各段连续的地址空间重新分配时间权重即可，相当于只执行一次重置操作和一次权重转移操作，无需针对每个热度记录序列分别执行上述步骤703和步骤704，提高了执行热度衰减的效率。
另外，由于后续需要根据该热度记录表中的热度记录序列对易失性缓存中的热数据进行淘汰，因此，在本申请实施例中，热度记录表中的热度记录序列仅仅针对易失性缓存中的热数据进行配置。由于易失性缓存中的数据是动态变化的，因此，在本申请实施例中，如果检测到易失性缓存中新增数据，则确定该新增数据的逻辑地址，并在图6所示的热度记录表中将该新增数据的逻辑地址对应的热度记录序列进行重置，比如，将全部比特位中指针当前时间指向的比特位上的比特值重置为1，其他比特位上的比特值重置为0。或者如果检测到易失性缓存删除数据时，则确定该新增数据的逻辑地址，并在图6所示的热度记录表中将该删除数据的逻辑地址对应的热度记录序列进行重置，比如，将全部比特位上的比特值重置为0。通过以上对热度记录表的维护，以使热度记录表中包括的各个热度记录序列一直保持为针对易失性缓存中数据的热度记录序列。
通过图5和图7所示的实施例，针对混合缓存的易失性缓存中的数据可以通过热度记录序列来记录该数据最近时间内被访问的情况，因此，本申请可以根据该热度记录序列对易失该数据进行淘汰，以实现将热数据淘汰成温数据。
图8是本申请实施例提供的一种热数据淘汰方法流程图，应用于图1所示的电子设备的处理器中。图8所示的热数据淘汰方法也即是图2中的热点识别淘汰算法。如图8所示，该方法包括如下步骤：
步骤801：根据热度记录表确定易失性缓存中所存储的数据的热度值。
本发明实施例中，计算易失性缓存中所存储数据的热度值的方法为：根据每个热度记录序列包括的多个比特位上的比特值，确定每个热度记录序列对应的逻辑地址区间对应的数据的热度值。
基于图5和图7所示的实施例可知，在任一时间，根据当前时间指针指向的 比特位，便可确定热度记录序列包括的各个比特位中每个比特位的时间权重。因此，确定每个热度记录序列对应的逻辑地址区间对应的数据的热度值的实现方式可以为：根据每个热度记录序列包括的多个比特位的时间权重，将每个热度记录序列包括的多个比特位上的比特值进行加权求和，得到的求和值即可作为每个热度记录序列对应的逻辑地址区间对应的数据热度值。这种确定热度值的方式可以使得确定的热度值能够指示该数据在当前时间最近一段时间内被访问的情况。具体地，热度值越大，表明该数据最近被访问的频率较高，热度值越小，表明该数据最近被访问的频率较低。
比如，热度记录序列包括的各个比特位的时间权重为上述表2所示的时间权重。此时，对于任一热度记录序列，该热度记录序列对应的逻辑地址区间对应的数据的热度值可以为：比特位A上的比特值×H0+比特位B上的比特值×H1+比特位C上的比特值×H2+比特位D上的比特值×H3+比特位E上的比特值×L0+比特位F上的比特值×L1+比特位G上的比特值×L2+比特位H上的比特值×L3。
另外，在本申请实施例中，可以在以下两种场景来执行图8实施例提供的热数据淘汰方法。
第一种场景为检测到易失性缓存的剩余存储容量低于阈值。在第一种场景中，处理器可以根据易失性缓存的剩余存储容量及时进行热数据淘汰，避免出现易失性缓存中存储过满的情况。
第二种场景为检测到淘汰热数据指令。淘汰热数据指令可以由后台管理人员触发，在第二种场景中，处理器可以根据用户的需求来进行热数据淘汰，提高了热数据淘汰的灵活性。
上述两种场景可以单独使用，可以结合使用，本申请实施例对此不做具体限定。
步骤802：如果该数据的热度值小于热度阈值，则将该数据淘汰至非易失性缓存中。
相应地，如果数据的热度值大于或等于热度阈值，则保留在易失性缓存中。如果数据的的热度值大于或等于热度阈值，表明该数据最近一段时间内被访问的频率较高，此时则无需将该数据淘汰至非易失性缓存中，也即是，保留该数据在易失性缓存中。
如果数据的热度值小于热度阈值，表明该数据最近一段时间内被访问的频率较低，此时，在一种可能的实现方式中，可以直接将该数据淘汰至非易失性缓存中。在另一种可能的实现方式中，也可以通过下述步骤803至步骤806对该数据进行淘汰，提高了淘汰热数据的灵活性。也即是，图8中的步骤802和步骤803至步骤806是两种并列的实现方式。
步骤803：如果数据的热度值小于热度阈值，则确定与该数据的逻辑地址相邻的逻辑地址对应的数据的热度值。
在本申请实施例中，为了提高由于偶然原因出现淘汰数据出现错误，如果数据的热度值小于热度阈值，并不急于将该数据淘汰至非易失性缓存，而是结合与其逻辑地址相邻的数据的热度值，综合判断是否需要将该数据淘汰至非易失性缓存，提高了淘汰热数据的灵活性。
因此，如果数据的热度值小于热度阈值，则确定与该数据的逻辑地址相邻的 逻辑地址对应的数据的热度值，以通过下述步骤804至806判断是否需要进行热数据淘汰。其中，确定该数据的逻辑地址相邻的逻辑地址对应的数据的热度值，同样可以根据相邻的逻辑地址对应的数据热度记录序列来确定相邻的逻辑地址对应的数据的热度值，在此不再赘述。
步骤804：确定该数据和与该数据的逻辑地址相邻的逻辑地址对应的数据的平均热度值。
步骤805：如果平均热度值大于或等于热度阈值，则保留该数据在易失性缓存中。
如果平均热度值大于或等于热度阈值，表明与该数据的逻辑地址相邻的逻辑地址上的数据大部分都是最近被频繁访问的数据，根据热数据的空间局部性，可知该数据很有可能最近会被频繁访问。此时如果直接将该数据淘汰至非易失性缓存，在淘汰后很容易出现立马要访问该数据的情况，从而造成不必要的淘汰。因此，在本申请实施例中，可以将该数据继续保留在易失性缓存中。相当于给该数据第二次机会。
步骤806：如果平均热度值小于热度阈值，则将该数据淘汰至非易失性缓存中。
如果平均热度值小于热度阈值，表明与该数据的逻辑地址相邻的逻辑地址上的数据大部分最近也没有被频繁地访问，此时，可以将该数据淘汰至非易失性缓存中。
上述淘汰热数据过程中的热度阈值可以是后台管理人员配置，此时在配置热度阈值之后，后续便可根据该固定的热度阈值来淘汰数据。另外，为了使得热度阈值能够反映混合缓存中的当前数据访问情况，处理器可以定期动态调整热度阈值，以便于后续根据调整之后的热度阈值进行热数据淘汰。
在一种可能的实现方式中，处理器定期动态调整热度阈值具体可以为：如果当前时间到达热度阈值更新时间点，则从热度记录表中随机选择m个热度记录序列，m为大于或等于1的正整数。根据m个热度记录序列中每个热度记录序列的热度值和易失性缓存中的期望存储数据比例，确定热度阈值。期望存储数据比例是指在易失性缓存中期望存储的数据的大小与在混合缓存中期望存储的数据的大小之间的比例。
比如，当混合缓存中存储容量为1太字节(terabyte，TB)，而用作热数据缓存的DRAM空间仅有100千兆字节(gigabyte，GB)，因此易失性缓存中的期望存储数据比例为10％，则可以根据10％和m个热度记录序列中每个热度记录序列的热度值，确定一个热度阈值，以使只有那些热度值大于了其他热度值90％的热度记录序列对应的数据才能够被留在DRAM中。
其中，随机选择的热度记录序列的个数也是根据当前混合缓存中的数据访问情况确定的。在一种可能的实现方式中，在每次调整热度阈值之前，可以确定易失性缓存的访问命中率，访问命中率用于指示访问的数据为易失性缓存中的数据的比例；根据易失性缓存的访问命中率，确定m。示例地，易失性缓存的访问命中率越高，表明调整之前的热度阈值已经比较准确，此时m可以较小。如果易失性缓存的访问命中率较低，表明调整之前的热度阈值不是很准确，此时m可以较大，以使调整之后的热度阈值能够准确。其中，热度阈值的准确是指按照该热度阈值淘汰数据之后，处理器每次访问的数据基本在易失性缓存中。
另外，定期动态调整热度阈值的周期也可以根据当前混合缓存中的数据访问情况确定。在一种可能的实现方式中，可以根据易失性缓存的访问命中率，确定热度阈值更新时间点。示例地，易失性缓存的访问命中率较高时，表明调整之前的热度阈值已经比较准确，此时，热度阈值更新时间点的周期设置较长，也即是没有必要频繁更新热度阈值。易失性缓存的访问命中率较低时，表明调整之前的热度阈值不是很准确，此时，热度阈值更新时间点的周期设置较短，也即是需要频繁更新热度阈值，以使调整之后的热度阈值较为准确。
参见图9，本申请实施例提供了一种访问电子设备中的混合缓存的装置，如图9所示，该装置900包括：
接收模块901，用于执行图3实施例中的步骤301；
查找模块902，用于执行图3实施例中的步骤302；
第一获取模块903，用于执行图3实施例中的步骤303；
读取模块904，用于执行图3实施例中的步骤304。
可选地，索引表中的每个逻辑地址对应有存储每个逻辑地址对应的数据的物理地址；
第一获取模块在从索引表中获取待访问数据的状态信息时，还用于获取待访问数据的物理地址；读取模块，具体用于：根据待访问数据的状态信息及待访问数据的物理地址从非易失性缓存或者易失性缓存中读取待访问数据。
可选地，索引表包括一级索引表和多个二级索引表，一级索引表中的一级索引为逻辑地址中从高位到低位的排序中的前p个比特位上的比特值进行组合得到的2^p个比特值组合，p为正整数，每个比特值组合对应一个二级索引表指针，二级索引表指针用于指示多个二级索引表中的一个二级索引表，二级索引表用于存储逻辑地址和每个逻辑地址对应的物理地址，存储的逻辑地址为存储在混合缓存中的数据逻辑地址，且所存储的逻辑地址的前p个比特位与一级索引表中的二级索引表指针所对应的比特值组合中的比特值相同；
查找模块，具体用于：在一级索引中查找待访问数据的逻辑地址的前p个比特位对应的比特值组合；根据比特值组合对应的二级索引表指针，从多个二级索引表中获取一个二级索引表；在二级索引表中查找待访问数据的逻辑地址。
可选地，索引表的一级索引表还包括存储的各个逻辑地址对应的数据的状态信息，具体为：每个一级索引所对应的查询结果还包括一个状态信息集合，状态信息集合用于存储逻辑地址满足相应一级索引的数据的状态信息，二级索引表中存储逻辑地址顺序排列；第一获取模块，具体用于：根据待访问数据的逻辑地址在获取的二级索引表中的排序，从一级索引对应的查询结果中包括的状态信息集合中确定待访问数据的状态信息。
可选地，索引表的二级索引表还包括存储的各个逻辑地址对应的数据的状态信息具体为：二级索引表还用于存储每个逻辑地址对应的数据的状态信息；第一获取模块，具体用于：在获取的二级索引表中确定待访问数据的状态信息。
可选地，二级索引表中的二级索引为逻辑地址中除p个比特位之外的其他q个比特位上的比特值，q为正整数，二级索引表中的每个二级索引对应的查询结构中包括一个逻辑地址集合，逻辑地址集合中的每个逻辑地址对应一个物理地址，且逻辑地址集合包括的逻辑地址为混合缓存中逻辑地址同时满足相应一级索引和 相应二级索引的数据的逻辑地址。
可选地，如图10所示，该装置900还包括：
第二获取模块905，用于执行图5实施例中的步骤501；
第一更新模块906，用于执行图5实施例中的步骤502。
可选地，每个热度记录序列包括多个比特位，每个比特位对应一个更新周期；第一更新模块，具体用于：获取当前时间对应的更新周期，将当前时间对应的更新周期对应的比特位更新为表示热度记录序列对应的逻辑地址对应的数据被访问过的标识。
可选地，如图11所示，该装置900还包括：
检测模块907，用于执行图7实施例中的步骤701；
第三获取模块908，用于执行图7实施例中的步骤702；
第二更新模块909，用于执行图7实施例中的步骤703；
第三更新模块910，用于执行图7实施例中的步骤704。
可选地，多个比特位按照指定顺序周期性地排列；
热度记录表配置有时钟和指针，时钟在系统初始化之后按照设置的时长周期性地计时，指针在系统初始化时指向多个比特位中的一个比特位，在每次时钟的计时时长达到设置的时长时，触发指针按照排序切换指向下一个比特位；
当前时间对应的更新周期对应的比特位为当前时间指针指向的比特位。
可选地，检测模块907，具体用于：
当当前时间到达热度记录表更新时间点时，则触发热度衰减指令，热度记录表更新时间点为系统初始化时配置的；和/或，
当高热度记录序列在所有热度记录序列中所占的比例大于参考比例时，则触发热度衰减指令，高热度记录序列指高位比特位上的比特值均为表示热度记录序列对应的逻辑地址对应的数据被访问过的标识的热度记录序列，高位比特位是指多个比特位中更新周期在当前时间之前参考时长内的比特位。
可选地，如图12所示，该装置900还包括：
第一确定模块911，用于执行图8实施例中步骤801；
淘汰模块912，用于执行图8实施例中步骤802。
可选地，第一确定模块911还用于执行图8实施例中的步骤803和步骤804；
该装置还包括保留模块，用于执行图8实施例中的步骤805。
可选地，淘汰模块912，还用于执行图8实施例中的步骤806。
可选地，第一确定模块，还用于：
当检测到易失性缓存的剩余存储容量低于空闲容量阈值时，和/或，当检测到淘汰热数据指令时，执行根据热度记录表确定易失性缓存中所存储的数据的热度值的步骤。
可选地，多个比特位中每个比特位配置有一个时间权重，每个比特位的时间权重用于指示相应比特位上的比特值的更新时间距离当前时间的远近，多个比特位中当前时间待更新比特位的时间权重最大；
第一确定模块，具体用于：
获取热度记录表中每个热度记录序列包括的多个比特位的时间权重；
根据每个热度记录序列包括的多个比特位的时间权重，将每个热度记录序列 包括的多个比特位上的比特值进行加权求和，得到的求和值作为每个热度记录序列对应的逻辑地址区间对应的数据的热度值。
可选地，该装置还包括：
选择模块，用于如果当前时间到达热度阈值更新时间点，则从热度记录表中随机选择m个热度记录序列，m为大于或等于1的正整数，热度阈值更新时间点为系统初始化时配置的；
第二确定模块，用于根据m个热度记录序列中每个热度记录序列的热度值和易失性缓存中的期望存储数据比例，确定热度阈值，期望存储数据比例是指在易失性缓存中期望存储的数据的大小与在混合缓存中期望存储的数据的大小之间的比例。
可选地，该装置还包括：
第三确定模块，用于确定易失性缓存的访问命中率，访问命中率用于指示访问的数据为易失性缓存中的数据的比例；
第四确定模块，用于根据易失性缓存的访问命中率，确定m。
可选地，该装置还包括：
第五确定模块，用于根据易失性缓存的访问命中率，确定热度阈值更新时间点。
当缓存采用两级混合缓存时，在本申请实施例中，可以为混合缓存设置一个索引表，索引表中记录了混合缓存中所存储的数据的逻辑地址和逻辑地址对应的物理地址，并指示每个逻辑地址对应的数据是存储在DRAM中还是PCM中，这样在混合缓存中读取数据时，不管该数据存储在混合缓存的DRAM中还是PCM中，均仅需查找一次索引表即可，从而提高了访问混合缓存中的数据的效率。
需要说明的是：上述实施例提供的访问混合缓存中的数据的装置在访问混合缓存中的数据时，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将设备的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。另外，上述实施例提供的访问混合缓存中的数据的装置与访问混合缓存中的数据的方法实施例属于同一构思，其具体实现过程详见方法实施例，这里不再赘述。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意结合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如：同轴电缆、光纤、数据用户线(Digital Subscriber Line，DSL))或无线(例如：红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如：软盘、硬盘、 磁带)、光介质(例如：数字通用光盘(Digital Versatile Disc，DVD))、或者半导体介质(例如：固态硬盘(Solid State Disk，SSD))等。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述为本申请提供的实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (16)

  1. 一种访问电子设备中的混合缓存的方法，其特征在于，所述方法应用于电子设备，所述混合缓存包括易失性缓存及非易失性缓存，所述方法包括：
    接收针对待访问数据的读指令，所述读指令中携带所述待访问数据的逻辑地址；
    在索引表中查找所述逻辑地址，所述索引表中存储有所述混合缓存中所存储数据的逻辑地址对应的状态信息，所述状态信息用于指示所述混合缓存中所存储数据是存储在所述易失性缓存中还是所述非易失性缓存中；
    当在所述索引表中查找到所述待访问数据的逻辑地址时，则从所述索引表中获取所述待访问数据的状态信息；
    根据所述待访问数据的状态信息从所述非易失性缓存或者所述易失性缓存中读取所述待访问数据。
  2. 如权利要求1所述的方法，其特征在于，所述索引表中的每个逻辑地址对应有存储每个逻辑地址对应的数据的物理地址；
    所述方法还包括：
    在从所述索引表中获取所述待访问数据的状态信息时，还获取所述待访问数据的物理地址；
    所述根据所述待访问数据的状态信息从所述非易失性缓存或者所述易失性缓存中读取所述待访问数据，包括：
    根据所述待访问数据的状态信息及所述待访问数据的物理地址从所述非易失性缓存或者所述易失性缓存中读取所述待访问数据。
  3. 如权利要求2所述的方法，其特征在于，所述索引表包括一级索引表和多个二级索引表，所述一级索引表中的一级索引为逻辑地址中从高位到低位的排序中的前p个比特位上的比特值进行组合得到的2^p个比特值组合，所述p为正整数，每个比特值组合对应一个二级索引表指针，所述二级索引表指针用于指示多个二级索引表中的一个二级索引表，所述二级索引表用于存储逻辑地址和每个逻辑地址对应的物理地址，存储的逻辑地址为存储在所述混合缓存中的数据逻辑地址，且所存储的逻辑地址的前p个比特位与所述一级索引表中的所述二级索引表指针所对应的比特值组合中的比特值相同；
    所述在索引表中查找所述逻辑地址，包括：
    在所述一级索引中查找所述待访问数据的逻辑地址的前p个比特位对应的比特值组合；
    根据所述比特值组合对应的二级索引表指针，从所述多个二级索引表中获取一个二级索引表；
    在所述二级索引表中查找所述待访问数据的逻辑地址。
  4. 如权利要求1至3任一所述的方法，其特征在于，在所述读取所述待访问数据之后，所述方法还包括：
    根据所述待访问数据的逻辑地址，从热度记录表中获取与所述待访问数据的逻辑地址对应的热度记录序列，所述热度记录表包括多个热度记录序列，每个热度记录序列对应一段逻辑地址区间，所述待访问数据的逻辑地址落在所述逻辑地址区间内，每个热度记录序列用于记录对应逻辑地址区间对应的数据的热度；
    更新所获取的热度记录序列所记录的热度。
  5. 如权利要求4所述的方法，其特征在于，每个热度记录序列包括多个比特位，每个比特位对应一个更新周期；
    所述更新所获取的热度记录序列所记录的热度，包括：
    获取当前时间对应的更新周期，将当前时间对应的更新周期对应的比特位更新为表示所述热度记录序列对应的逻辑地址对应的数据被访问过的标识。
  6. 如权利要求4所述的方法，其特征在于，所述方法还包括：
    检测热度衰减指令；
    获取每个热度记录序列多个比特位中位于当前时间对应的更新周期之后的下一个更新周期对应的比特位；
    将每个热度记录序列中所述下一个更新周期对应的比特位更新为表示热度记录序列对应的逻辑地址对应的数据未被访问过的标识；
    将每个热度记录序列中所述下一个更新周期对应的比特位确定为当前时间对应的更新周期对应的比特位。
  7. 如权利要求5或6所述的方法，其特征在于，所述多个比特位按照指定顺序周期性地排列；
    所述热度记录表配置有时钟和指针，所述时钟在系统初始化之后按照设置的时长周期性地计时，所述指针在系统初始化时指向所述多个比特位中的一个比特位，在每次所述时钟的计时时长达到所述设置的时长时，触发所述指针按照排序切换指向下一个比特位；
    所述当前时间对应的更新周期对应的比特位为当前时间所述指针指向的比特位。
  8. 如权利要求4所述的方法，其特征在于，所述方法还包括：
    根据所述热度记录表确定易失性缓存中所存储的数据的热度值；
    如果所述数据的热度值小于热度阈值，则将所述数据淘汰至所述非易失性缓存中。
  9. 一种访问电子设备中的混合缓存的装置，其特征在于，所述混合缓存包括易失性缓存及非易失性缓存，所述装置包括：
    接收模块，用于接收针对待访问数据的读指令，所述读指令中携带所述待访问数据的逻辑地址；
    查找模块，用于在索引表中查找所述逻辑地址，所述索引表中存储有所述混合缓存中所存储数据的逻辑地址对应的状态信息，所述状态信息用于指示所述混 合缓存中所存储数据是存储在所述易失性缓存中还是所述非易失性缓存中；
    第一获取模块，用于当在所述索引表中查找到所述待访问数据的逻辑地址时，则从所述索引表中获取所述待访问数据的状态信息；
    读取模块，用于根据所述待访问数据的状态信息从所述非易失性缓存或者所述易失性缓存中读取所述待访问数据。
  10. 如权利要求9所述的装置，其特征在于，所述索引表中的每个逻辑地址对应有存储每个逻辑地址对应的数据的物理地址；
    所述第一获取模块在从所述索引表中获取所述待访问数据的状态信息时，还用于获取所述待访问数据的物理地址；
    所述读取模块，具体用于：根据所述待访问数据的状态信息及所述待访问数据的物理地址从所述非易失性缓存或者所述易失性缓存中读取所述待访问数据。
  11. 如权利要求10所述的装置，其特征在于，所述索引表包括一级索引表和多个二级索引表，所述一级索引表中的一级索引为逻辑地址中从高位到低位的排序中的前p个比特位上的比特值进行组合得到的2^p个比特值组合，所述p为正整数，每个比特值组合对应一个二级索引表指针，所述二级索引表指针用于指示多个二级索引表中的一个二级索引表，所述二级索引表用于存储逻辑地址和每个逻辑地址对应的物理地址，存储的逻辑地址为存储在所述混合缓存中的数据逻辑地址，且所存储的逻辑地址的前p个比特位与所述一级索引表中的所述二级索引表指针所对应的比特值组合中的比特值相同；
    所述查找模块，具体用于：
    在所述一级索引中查找所述待访问数据的逻辑地址的前p个比特位对应的比特值组合；
    根据所述比特值组合对应的二级索引表指针，从所述多个二级索引表中获取一个二级索引表；
    在所述二级索引表中查找所述待访问数据的逻辑地址。
  12. 如权利要求9至11任一所述的装置，其特征在于，所述装置还包括：
    第二获取模块，用于根据所述待访问数据的逻辑地址，从热度记录表中获取与所述待访问数据的逻辑地址对应的热度记录序列，所述热度记录表包括多个热度记录序列，每个热度记录序列对应一段逻辑地址区间，所述待访问数据的逻辑地址落在所述逻辑地址区间内，每个热度记录序列用于记录对应逻辑地址区间对应的数据的热度；
    第一更新模块，用于更新所获取的热度记录序列所记录的热度。
  13. 如权利要求12所述的装置，其特征在于，每个热度记录序列包括多个比特位，每个比特位对应一个更新周期；
    所述第一更新模块，具体用于：获取当前时间对应的更新周期，将当前时间对应的更新周期对应的比特位更新为表示所述热度记录序列对应的逻辑地址对应的数据被访问过的标识。
  14. 如权利要求12所述的装置，其特征在于，所述装置还包括：
    检测模块，用于检测热度衰减指令；
    第三获取模块，用于获取每个热度记录序列多个比特位中位于当前时间对应的更新周期之后的下一个更新周期对应的比特位；
    第二更新模块，用于将每个热度记录序列中所述下一个更新周期对应的比特位更新为表示热度记录序列对应的逻辑地址对应的数据未被访问过的标识；
    第三更新模块，用于将每个热度记录序列中所述下一个更新周期对应的比特位确定为当前时间对应的更新周期对应的比特位。
  15. 如权利要求13或14所述的装置，其特征在于，所述多个比特位按照指定顺序周期性地排列；
    所述热度记录表配置有时钟和指针，所述时钟在系统初始化之后按照设置的时长周期性地计时，所述指针在系统初始化时指向所述多个比特位中的一个比特位，在每次所述时钟的计时时长达到所述设置的时长时，触发所述指针按照排序切换指向下一个比特位；
    所述当前时间对应的更新周期对应的比特位为当前时间所述指针指向的比特位。
  16. 如权利要求12所述的装置，其特征在于，所述装置还包括：
    第一确定模块，用于根据所述热度记录表确定易失性缓存中所存储的数据的热度值；
    淘汰模块，用于如果所述数据的热度值小于热度阈值，则将所述数据淘汰至所述非易失性缓存中。
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