WO2021087531A2

WO2021087531A2 - Spur cancellation in downlink

Info

Publication number: WO2021087531A2
Application number: PCT/US2021/020944
Authority: WO
Inventors: Ryan Tsai; Jifeng Geng
Original assignee: Zeku, Inc.
Priority date: 2021-03-04
Filing date: 2021-03-04
Publication date: 2021-05-06
Also published as: CN117016006A; WO2021087531A3

Abstract

Embodiments of apparatus and method for spur cancellation are disclosed. In an example, an apparatus for controlling a pole magnitude for spur cancellation can include a first signal path connected to a source of an input signal. The apparatus can also include a first bit shifter connected to the first signal path and configured to provide a first intermediate output to a first adder. The first adder can also be connected to the first signal path. The first adder can be configured to provide a first output. The apparatus can also include a second bit shifter connected to the first signal path and configured to provide a second intermediate output to a second adder. The second adder can also be connected to the first output. The second adder can be configured to provide a second output. The second bit shifter can be controlled by a first control bit of a plurality of control bits configured to control a pole magnitude for spur cancellation

Description

SPUR CANCELLATION IN DOWNLINK

BACKGROUND

[0001] Embodiments of the present disclosure relate to apparatuses and methods for wireless communication.

[0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. In wireless communications, there may be various sources of interference. For example, a continuous wave (CW) spur can be a continuous wave spur or otherwise undesired tone that may degrade reception (Rx) signal to noise ratio (SNR) and may appear to due to finite isolation between receiver analog signal paths and clocks within a transceiver chip.

SUMMARY

[0003] Embodiments of apparatus and method for spur cancellation are disclosed herein.

[0004] In one example, a method can include accumulating a plurality of input samples of a reception chain at initialization of spur cancellation to provide an estimate of a spur having an amplitude and phase. The method can also include cancelling a spur in the reception chain based on the estimate.

[0005] In another example, an apparatus for controlling a pole magnitude for spur cancellation can include a first signal path connected to a source of an input signal. The apparatus can also include a first bit shifter connected to the first signal path and configured to provide a first intermediate output to a first adder. The first adder can also be connected to the first signal path. The first adder can be configured to provide a first output. The apparatus can also include a second bit shifter connected to the first signal path and configured to provide a second intermediate output to a second adder. The second adder can also be connected to the first output. The second adder can be configured to provide a second output. The second bit shifter can be controlled by a first control bit of a plurality of control bits configured to control a pole magnitude for spur cancellation. [0006] In a further example, an apparatus for spur cancellation can include a first adder configured to provide an output signal at an output based on an input signal received at a first input and a correction signal received at a second input. The apparatus can also include a correction path configured to provide the correction signal based on the input and output signals. The correction path can be configured to be reconfigurable from an acquisition mode in which a plurality of samples of the input signal are collected in a register before updating the correction signal to a tracking mode in which the correction signal can be updated after every input and output sample. [0007] In yet another example, a method for controlling a pole magnitude for spur cancellation can include receiving an input signal and performing a first bit shifting on the input signal. The method can also include combining a first bit shifting output of the first bit shifting with the input signal to provide a first output signal. The method can further include performing a second bit shifting on the input signal. The method can additionally include combining a second bit shifting output of the second bit shifting with the first output signal to provide a second output signal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0009] FIG. 1 illustrates a system in which certain embodiments of the present disclosure may be implemented.

[0010] FIG. 2 illustrates a three-bit shifter hardware implementation of pole magnitude coefficient, according to certain embodiments of the present disclosure.

[0011] FIG. 3A illustrates an acquisition mode according to certain embodiments of the present disclosure.

[0012] FIG. 3B illustrates a corresponding tracking mode according to certain embodiments of the present disclosure.

[0013] FIG. 4 A illustrates a method for spur cancellation according to certain embodiments of the present disclosure.

[0014] FIG. 4B illustrates a further method for spur cancellation according to certain embodiments of the present disclosure.

[0015] FIG. 5 illustrates a method for controlling a pole magnitude for spur cancellation according to certain embodiments of the present disclosure.

[0016] FIG. 6 illustrates a block diagram of an apparatus including a baseband chip, a radio frequency chip, and a host chip, according to some embodiments of the present disclosure. [0017] FIG. 7 illustrates an example node, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure.

[0018] FIG. 8 illustrates an example wireless network, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure.

[0019] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

[0020] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0021] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0022] In general, terminology may be understood at least in part from usage in context.

For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context. [0023] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system.

[0024] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as GSM. An OFDMA network may implement a RAT, such as Long-Term Evolution (LTE) or New Radio (NR). The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs.

[0025] Certain embodiments of the present disclosure relate to two aspects of the reception of signals in, for example, wireless communication. For example, certain embodiments relate to mechanisms to control notch filter bandwidth with finer resolution and efficient hardware implementation. Additionally, or alternatively, certain embodiments relate to an efficient mechanism to estimate the amplitude and phase of a continuous wave spur during acquisition mode, which significantly reduces settling time during tracking mode.

[0026] Certain embodiments may provide various benefits and/or advantages in addition to the benefit or advantage of effective spur cancellation. For example, certain embodiments may save power consumption at receive power-on because the notch filter can be turned on later. Certain embodiments may also save power during discontinuous reception (DRx) because the notch filter can be turned off. When switching from transmission (Tx) to reception in time division duplex (TDD), when the notch filter cannot be turned on early, the first-symbol signal-to-noise ratio may be improved relative to spur cancellation without the benefit of certain embodiments. Certain embodiments may be implemented with hardware changes to the previous hardware notch filter design.

[0027] Previously, notch control only supported pole magnitudes of 1 — l/2ⁿ, where n =

1, 2, 3, 4, , 2^number °f ^{contro1 blts}. For fast settling, such an approach used a wide notch bandwidth (BW) during acquisition mode before switching to a narrow notch bandwidth for tracking mode. [0028] Pole magnitude step size in this approach is coarse for smaller n. Increasing the number of control bits increases maximum n and allows the pole magnitude to move closer to 1, but does not improve resolution for smaller n.

[0029] Certain embodiments of the present disclosure introduce a new control register coding that yields a finer step size, improves performance across different test configurations, has a monotonic mapping of control bits to pole magnitude, and can be implemented efficiently in hardware. Any desired resolution can be achieved by increasing the number of control bits. By contrast, the resolution in the previous approach does not improve at all by increasing the number of control bits.

[0030] For acquisition mode, using a wide notch bandwidth improves settling time, but when the sampled data is noisy, the more heavily weighted newer samples may throw off the estimate.

[0031] The optimal way to estimate the spur may be to weight all acquisition samples equally, allowing the noise of all samples to average out. Certain embodiments of the present disclosure reconfigure hardware of the notch filter as an accumulator for the purpose of permitting equal weighting of acquisition samples, resulting in faster transient response at the start of tracking. The accumulation can leverage the feedback path on an existing notch filter, adding some of the additional circuits thereto in an efficient hardware implementation. In the previous approach, however, it was not possible to weight all acquisition samples equally.

[0032] Certain embodiments enable fine control of the notch filter transient response and bandwidth. Fine control may enable more optimized settings and better spur cancellation performance across different test configurations that differ by signal strength, resource block (RB) allocation, subcarrier spacing (SCS), sampling rate, spur power, and transient requirement(s). Certain embodiments also provide a new acquisition mode that may improve power consumption and signal quality, as discussed below.

[0033] In certain embodiments, the circuitry may be provided in a spur cancellation block near the end of the receiver digital front-end on a transceiver chip of a user equipment or other network node. Thus, certain embodiments of the present invention may be implemented in hardware in a spur cancellation section of a digital front end circuit of a modem or similar communication equipment.

[0034] FIG. 1 illustrates a system in which certain embodiments of the present disclosure may be implemented. As shown in FIG. 1, radio frequency (RF) signals may be received at RF front end 110 using, for example, antennas. They then may be passed to a digital front end circuit 120, from which they may be subsequently passed to a baseband module 130.

[0035] Within the digital front end circuit 120, the signals may be first processed by an RF transceiver 122, they may then be processed by a digital down-converter 124 and subsequently by spur cancellation 126. Additional modules may be included in addition to those shown, with the illustrated modules being provided to provide a general context for the understanding of spur cancellation 126, without any limitation.

[0036] In certain embodiments, a new control register coding may be applied. In this approach, a pole magnitude may be 1 -

+ b_k®ase-3 *

· where n = 1, 2, 2^{mm (}'^t'^i,iIse), k is the number of control bits, and b_k®ase-x is the control bit at position k — base — x, where k — base — x is non-negative.

[0037] This control register coding may be implemented by bit shifters and adders as every pole coefficient can be the sum of powers of two. For example, when base = k = 4, the pole magnitude may simply be

n may be 1,2, ... ,16. When base = 4 and k = 6, the pole magnitude may be

where n may be 1,2, ... ,16. When base = 3

1 1 1 1 and k = 6, the pole magnitude may be 1 — — + b₂ *

+ b * + b * where n may be

1,2, ... ,8.

[0038] FIG. 2 illustrates a three-bit shifter hardware implementation of pole magnitude coefficient, i.e., k = base + 2, where base may be non-negative, according to certain embodiments of the present disclosure. As shown in FIG. 2, the system may receive an input signal 210 and provide an output signal 250. The input signal 210 may be provided to first bit shifter 220, which may bit shift by n, to second bit shifter 230, which may bit shift by n+2, and to third bit shifter 240, which may bit shift by n+3. An output of first bit shifter 220 may be combined with the input signal 210 using first adder 225.

[0039] Similarly, the output of second bit shifter 230 may be combined with the output of first adder 225 using second adder 235. Likewise, the output of third bit shifter 240 may be combined using the third adder 245 with the output of second adder 235 to yield output signal 250. As shown in FIG. 2, b is the enable bit for the second bit shifter and b₀ is the enable bit for the third bit shifter.

[0040] The resulting output may be some scaled version of the input, where the scaling factor, r, may be less than one but greater than or equal to 0.5.

[0041] It should be understood that this approach may be scaled. For example, removing the third bit shifter 240 and the third adder 245 may correspond to a two-bit shifter case, where k = base + 1 , whereas if a further bit shifter and further adder were included, this could correspond to a four-bit shifter case, where k = base + 3. The three-bit shifter case illustrated is just one example.

[0042] The apparatus shown in FIG. 2 can be considered an apparatus for controlling a pole magnitude for spur cancellation. The apparatus can include a first signal path for communicating input signal 210 connected to a source of the input signal. The apparatus can also include a first bit shifter (for example, first bit shifter 220) connected to the first signal path and configured to provide a first intermediate output to a first adder (see the negative input of first adder 225). The first adder 225 can also be connected to the first signal path (see the positive input of first adder 225). The first adder 225 can be configured to provide a first output. The apparatus can also include a second bit shifter (for example, second bit shifter 230) connected to the first signal path and configured to provide a second intermediate output to a second adder (see the left input of second adder 235). The second adder 235 can also be connected to the first output (see the top input of second adder 235). The second adder 235 can be configured to provide a second output. The second bit shifter can be enabled or disabled by a first control bit of a plurality of control bits configured to control a pole magnitude for spur cancellation (see bit bi controlling second bit shifter 230). [0043] In some embodiments, the apparatus can further include a third bit shifter (see, for example, third bit shifter 240 in FIG. 2) connected to the first signal path and configured to provide a third intermediate output to a third adder (see the left input of third adder 245). The third adder 245 can also be connected to the second output (see the top input of third adder 245). The third adder 245 can be configured to provide a third output. The third bit shifter can be enabled or disabled by a second control bit of the plurality of control bits (see bit bo controlling third bit shifter 240).

[0044] Although not shown in the example illustrated in FIG. 2, the apparatus can also include a fourth bit shifter connected to the first signal path and configured to provide a fourth intermediate output to a fourth adder. The fourth adder can also be connected to the third output. The fourth adder can be configured to provide a fourth output. The fourth bit shifter can be enabled or disabled by a third control bit of the plurality of control bits.

[0045] FIG. 3A illustrates an acquisition mode according to certain embodiments of the present disclosure. FIG 3B illustrates a tracking mode. As shown in FIG. 3 A, the acquisition mode may include accumulating N samples.

[0046] In this example, the input samples are inverted and then accumulated. The accumulation output can be averaged. In the example shown in FIG. 3A, the averaging is accomplished by applying a gain of 1/N to the samples before adding them together, using pre- scaling gain element 310, a process that can also be referred to as pre-scaling. The samples can be rotated in phase using rotational element 320 and saved in delay register 330, which is shown as a delay element. The rotation can be used to align the phases of all the samples to the phase of the spur. The samples can then be added, using first adder 340, to one another until N samples have been collected. The accumulation output is the least-squares estimate of the spur amplitude and phase. This estimate can be provided to cancel the next spur sample using first adder 340.

[0047] As shown in FIG. 3B, after accumulation, a tracking mode can then be used with pole magnitude, r, being applied to cancel a spur at a particular notch frequency, f. Tracking mode can be thought of as sequential estimation, where the estimate of the spur amplitude and phase in delay register 330 is updated after every input sample. In an ideal world, r approaches 1 because as r approaches 1, this sequential estimate approaches the least-squares estimate. However, r can never be 1 because this would mean the feedforward and feedback paths cancel, in which case there is no correction. In the tracking mode, a variable gain element 360, which may be the device shown in FIG. 2, may apply pole magnitude r to scale the output, which can be thought of as the estimation error. The scaled estimation error can be combined with the current sample using a second adder 370. This new estimate can be rotated to the phase of the next input sample using rotational element 320 and saved in delay register 330, where it can then be applied to the next sample with first adder 340.

[0048] The device shown in FIGs. 3A and 3B may be considered an apparatus for spur cancellation and/or notch control. The apparatus can include a first adder 340 configured to provide an output signal, y[n], at an output based on an input signal, x[n], received at a first input and a spur estimate, reg[n], received at a second input. The apparatus can also include a feedback path configured to provide the spur estimate based on the output signal (see the path through variable gain element 360). The feedback path can be configured to be reconfigurable from an acquisition mode (see, for example, FIG. 3A) in which a plurality of samples of the input signal are accumulated and averaged in a register to provide an initial spur estimate to a tracking mode (see, for example, FIG. 3B) in which the spur estimate is updated with every new input sample via second adder 370. In both modes, the spur estimate is applied to the input signal via first adder 340. [0049] As shown in FIG. 3 A, a pre-scaler, such as pre-scaling gain element 310, can be configured to pre-scale the input signal during the acquisition mode. The apparatus can further include a gain element, such as variable gain element 360, configured to scale the output signal by the magnitude of the pole. The gain element can be the device shown in FIG. 2. The apparatus can also include a controller (for example, see FIG. 4B) configured to control the apparatus selectively to operate in the acquisition mode or the tracking mode.

[0050] Certain embodiments of the present disclosure enable fine control of notch filter transient response and bandwidth, which may enable better spur cancellation performance over different test configurations. Any desired resolution can be achieved by increasing the number of control bits. The control bit mapping to pole magnitude may be monotonic, and the coefficient can be efficiently implemented in hardware with only bit shifters and adders. Other alternative implementations, such as multipliers in place of some or all of the bit shifters and adders, are also permitted.

[0051] The new acquisition mode may reduce the tradeoff between low settling time and high steady-state SNR, allowing the reception chain to achieve both.

[0052] In certain embodiments, the SNR of the first downlink (DL) symbol after uplink to downlink (UL-to-DL) transition in time division duplex (TDD) may be improved. In certain embodiments, the notch filter can be enabled or reconfigured at any time, even between adjacent DL symbols, with reduced impact to the SNR of the next symbol. Moreover, in certain embodiments, the notch filter can be enabled or disabled based on the received signal strength indicator (RSSI) of the desired DL signal to improve SNR. In certain embodiments, the notch filter can be disabled during DRx to save power. Additionally, the notch frequency can be re-tuned based on the spur frequency, which may be time-dependent. Furthermore, certain embodiments can save power by delaying the notch filter power on until the symbol boundary. Moreover, certain embodiments of the present disclosure may provide an estimation technique in acquisition mode that may reduce settling time compared to previous techniques. [0053] FIG. 4A illustrates a method for spur cancellation according to certain embodiments of the present disclosure. As shown in FIG. 4A, a method can include accumulating and averaging N input samples of a reception chain at initialization of spur cancellation to generate an initial estimate for the amplitude and phase of the spur. N can be a number greater than 1. For example, N could be 64 or 256. Other numbers of samples are permitted. Thus, for example, N may be a predetermined finite number of samples greater than 1 , such as 8 or more samples, or the like. This accumulating shown at 410 can be performed using the circuit shown by way of example in FIG. 3 A. The accumulating shown at 410 may be initiated at the DL symbol boundary. The averaging at 410 can be done using a pre-scaling gain element 310, as shown in FIG. 3A.

[0054] The accumulating and averaging at 410 can occur when the notch filter is turned on or when the notch filter is reconfigured at 404.

[0055] As mentioned above, the accumulating and averaging at 410 may be triggered by the notch filter being turned on at 404. This may occur, for example, when the reception chain is turned on. The reception chain may be turned on by the operation of software of the user equipment. Other triggers for the notch filter being turned on or reconfigured can include a received signal strength indicator (RSSI) measurement being below a threshold. Thus, for example, software of the user equipment may determine the RSSI and consequently turn on or reconfigure the notch filter at 404. Another trigger may be a determination by software that other devices are turned on, such as other components or sub-components of the user equipment. The RSSI determination may also lead to the software shutting down or otherwise disabling the notch filter at 450. Likewise, the determination regarding other device activation may lead to disabling the notch filter at 450. Similarly, the software or hardware of the user equipment may turn off the reception chain, which may similarly result in disabling the notch filter at 450. Furthermore, the notch filter frequency may be reprogrammed. In short, there may be a variety of triggers for activation or deactivation of the notch filter including a variety of bases upon which the software may decide that notch filtering is desirable or undesirable, needed or not needed. Any time the notch filter is activated or reconfigured, it is possible that the accumulating and averaging at 410 may be performed.

[0056] The enabling or reconfiguring the notch filter at 404 may be performed between adjacent downlink symbols. The disabling the notch filter at 450 may be performed during discontinuous reception. The turning on the notch filter at 404 may be delayed by software until a symbol boundary. Other modifications and variations are also permitted. [0057] As shown in FIG. 4 A, the method can also include, at 430, tracking a spur in the reception chain based on each new input sample (sequential estimation of the spur amplitude and phase). The tracking at 430 can be performed by the circuit shown in FIG. 3B, which can more broadly be known as applying a notch filter to the spur. This can be the steady state configuration of the spur canceller, which means that the spur canceller can remain in this state unless otherwise disturbed. The frequency of the spur may be calculated separately in advance or may otherwise be known.

[0058] From the steady state configuration, or tracking mode at 430, the spur canceller may be disabled at 450 or reconfigured at 404. For example, when software measures oscillator drift, for example, XO drift, during automatic frequency correction (AFC), because the spur frequency may change, the spur canceller may reconfigure the phase rotation element at 320 in FIGs. 3A and 3B. To improve SNR, SW may choose to disable the spur canceller when the RSSI measurement exceeds a preset threshold and then re-enable the spur canceller when the RSSI measurement falls below the threshold. SW may also choose to disable the spur canceller if the conditions for the spur appearing are no longer present; for example, the spur may disappear if SW shuts down other reception or transmission chains in the case of carrier deactivation in carrier aggregation. SW may re-enable the spur canceller when those conditions are present again. SW may also choose to disable the entire reception chain, including the spur canceller, if the chain is not currently needed to receive any signals, and then re-enable when the reception chain is once again needed. For example, this may be done to reduce power consumption during discontinuous reception.

[0059] Determining the RSSI may be performed in the protocol stack of a user equipment and passed back to the physical layer, and specifically to a baseband chip of the transceiver of the user equipment.

[0060] As with information regarding RSSI, information regarding symbol boundaries and discontinuous reception can be provided from other parts of a user equipment to the spur cancellation section.

[0061] Tracking mode at 430 can include controlling a pole magnitude coefficient according to a plurality of control bits. FIG. 2 provides an example circuit for implementing such control.

[0062] FIG. 4B illustrates a further method for spur cancellation according to certain embodiments of the present disclosure. As shown in FIG. 4B, a method can include, at 490, controlling a notch filter using a controller or other circuit or circuits. Various circuitry may be used to perform the control at 490. Control at 490 may be performed consistent with the state diagram of the method shown in FIG. 4A. The control of the notch filter may be based on various factors, such as whether spur conditions are satisfied or unsatisfied at 460, whether a reception chain is on or off at 470, whether RSSI is measured above or below a threshold at 480, and if the notch frequency needs to be reprogrammed at 498. These factors are also illustrated in FIG. 4A. [0063] As further illustrated in FIG. 4B, control can also be based on a symbol boundary as shown at 492. For example, in certain embodiments, turning on the notch filter may be delayed until a symbol boundary. This may be possible because of the speed and reliability of certain embodiments of the present disclosure. Similarly, at 494, control can be determined based on whether reception is discontinuous or not. For example, in certain embodiments, the controller can disable the notch filter during discontinuous reception. This may be possible because of the speed and accuracy of certain embodiments of the present disclosure.

[0064] Likewise, at 496, the controller may control based on a relationship with adjacent downlink symbols. For example, in certain embodiments, the controller may enable or reconfigure the notch filter between adjacent downlink symbols. This may be accomplished using the speed and accuracy of certain embodiments.

[0065] FIG. 5 illustrates a method for controlling a pole magnitude for spur cancellation according to certain embodiments of the present disclosure. As shown in FIG. 5, the method can include, at 510, receiving an input signal and, at 520, performing a first bit shifting on the input signal. The method can also include, at 530, combining a first bit shifting output of the first bit shifting with the input signal to provide a first output signal. The method can further include, at 540, performing a second bit shifting on the input signal. The method can additionally include, at 550, combining a second bit shifting output of the second bit shifting with the first output signal to provide a second output signal.

[0066] The method can also include, at 555, enabling or disabling the second bit shifting according to a first control bit of a plurality of control bits configured to control the pole magnitude. [0067] The method can further include, at, 560, performing a third bit shifting on the input signal. The method can additionally include, at 570, combining a third bit shifting output of the third bit shifting with the second output signal to provide a third output signal. At 575, the third bit shifting can be enabled or disabled by a second control bit. The method of FIG. 5 may be implemented by, for example, the circuit shown in FIG. 2. [0068] The software and hardware methods and systems disclosed herein, such as the methods illustrated in FIGs. 4 and 5, may be implemented by any suitable nodes in a wireless network. For example, FIGs. 6 and 7 illustrate respective apparatuses 600 and 700, and FIG. 8 illustrates an exemplary wireless network 800, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure.

[0069] FIG. 6 illustrates a block diagram of an apparatus 600 including a baseband chip

602, a radio frequency chip 604, and a host chip 606, according to some embodiments of the present disclosure. Apparatus 600 may be an example of any suitable node of wireless network 800 in FIG. 8, such as user equipment 802 or access node 804. As shown in FIG. 6, apparatus 600 may include baseband chip 602, radio frequency chip 604, host chip 606, and one or more antennas 610. Baseband chip 602 may implement baseband module 130 in FIG. 1. Likewise, radio frequency chip 604 and/or baseband chip 602 may implement digital front end circuit 120 and spur cancellation 126 in FIG. 1. In some embodiments, baseband chip 602 is implemented by processor 702 and memory 704, and radio frequency chip 604 is implemented by processor 702, memory 704, and transceiver 706, as described above with respect to FIG. 7. Besides the on-chip memory (also known as “internal memory” or “local memory,” e.g., registers, buffers, or caches) on each chip 602, 604, or 606, apparatus 600 may further include an external memory 608 (e.g., the system memory or main memory) that can be shared by each chip 602, 604, or 606 through the system/main bus. Although baseband chip 602 is illustrated as a standalone SoC in FIG. 6, it is understood that in one example, baseband chip 602 and radio frequency chip 604 may be integrated as one SoC; in another example, baseband chip 602 and host chip 606 may be integrated as one SoC; in still another example, baseband chip 602, radio frequency chip 604, and host chip 606 may be integrated as one SoC, as described above.

[0070] In the uplink, host chip 606 may generate raw data and send it to baseband chip 602 for encoding, modulation, and mapping. Baseband chip 602 may also access the raw data generated by host chip 606 and stored in external memory 608, for example, using the direct memory access (DMA). Baseband chip 602 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi-phase pre-shared key (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 602 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 602 may send the modulated signal to radio frequency chip 604. Radio frequency chip 604, through the transmitter (Tx) (including RF front end 110 in FIG. 1), may convert the modulated signal in the digital form into analog signals, i.e., radio frequency signals, and perform any suitable front-end radio frequency functions, such as filtering, up-conversion, or sample-rate conversion. Antenna 610 (e.g., an antenna array) may transmit the radio frequency signals provided by the transmitter of radio frequency chip 604. [0071] In the downlink, antenna 610 may receive radio frequency signals and pass the radio frequency signals to the receiver (Rx) of radio frequency chip 604. Radio frequency chip 604 may perform any suitable front-end radio frequency functions, such as filtering, down-conversion, or sample-rate conversion, and convert the radio frequency signals into low-frequency digital signals (baseband signals) that can be processed by baseband chip 602. Thus, radio frequency chip 604 may include some of the functions of the RF front end 110 and/or the functions of the digital front end circuit 120 in FIG. 1. For example, radio frequency chip 604 may include the RF transceiver 122, digital down-converter 124, and spur cancellation 126 shown in FIG. 1. In the downlink, baseband chip 602 may demodulate and decode the baseband signals to extract raw data that can be processed by host chip 606. Baseband chip 602 may perform additional functions, such as error checking, de-mapping, channel estimation, descrambling, etc. The raw data provided by baseband chip 602 may be sent to host chip 606 directly or stored in external memory 608.

[0072] As shown in FIG. 7, a node 700 may include a processor 702, a memory 704, a transceiver 706. These components are shown as connected to one another by bus 708, but other connection types are also permitted. When node 700 is user equipment 802, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 700 may be implemented as a blade in a server system when node 700 is configured as core network element 806. Other implementations are also possible.

[0073] Transceiver 706 may include any suitable device for sending and/or receiving data.

Node 700 may include one or more transceivers, although only one transceiver 706 is shown for simplicity of illustration. An antenna 710 is shown as a possible communication mechanism for node 700. Multiple antennas and/or arrays of antennas may be utilized. Additionally, examples of node 700 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 804 may communicate wirelessly to user equipment 802 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 806. Other communication hardware, such as a network interface card (NIC), may be included as well. [0074] As shown in FIG. 7, node 700 may include processor 702. Although only one processor is shown, it is understood that multiple processors can be included. Processor 702 may include microprocessors, microcontrollers, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 702 may be a hardware device having one or many processing cores. Processor 702 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. Processor 702 may be a baseband chip, such as baseband chip 602 in FIG. 6. Node 700 may also include other processors, not shown, such as a central processing unit of the device, a graphics processor, or the like. Processor 702 may include internal memory (also known as local memory, not shown in FIG. 7) that may serve as memory for L2 data. Processor 702 may include a radio frequency chip, for example, integrated into a baseband chip, or a radio frequency chip may be provided separately. Processor 702 may be configured to operate as a modem of node 700, or may be one element or component of a modem. Other arrangements and configurations are also permitted.

[0075] As shown in FIG. 7, node 700 may also include memory 704. Although only one memory is shown, it is understood that multiple memories can be included. Memory 704 can broadly include both memory and storage. For example, memory 704 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferro electric RAM (FRAM), electrically erasable programmable ROM (EEPROM), CD-ROM or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 702. Broadly, memory 704 may be embodied by any computer-readable medium, such as anon-transitory computer-readable medium. The memory 704 can be the external memory 608 in FIG. 6. The memory 704 may be shared by processor 702 and other components of node 700, such as the unillustrated graphic processor or central processing unit.

[0076] As shown in FIG. 8, wireless network 800 may include a network of nodes, such as a UE 802, an access node 804, and a core network element 806. User equipment 802 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Intemet-of-Things (IoT) node. It is understood that user equipment 802 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0077] Access node 804 may be a device that communicates with user equipment 802, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 804 may have a wired connection to user equipment 802, a wireless connection to user equipment 802, or any combination thereof. Access node 804 may be connected to user equipment 802 by multiple connections, and user equipment 802 may be connected to other access nodes in addition to access node 804. Access node 804 may also be connected to other UEs. It is understood that access node 804 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0078] Core network element 806 may serve access node 804 and user equipment 802 to provide core network services. Examples of core network element 806 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 806 includes an access and mobility management function (AMF) device, a session management function (SMF) device, or a user plane function (UPF) device, of a core network for the NR system. It is understood that core network element 806 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0079] Core network element 806 may connect with a large network, such as the Internet

808, or another IP network, to communicate packet data over any distance. In this way, data from user equipment 802 may be communicated to other UEs connected to other access points, including, for example, a computer 810 connected to Internet 808, for example, using a wired connection or a wireless connection, or to a tablet 812 wirelessly connected to Internet 808 via a router 814. Thus, computer 810 and tablet 812 provide additional examples of possible UEs, and router 814 provides an example of another possible access node.

[0080] A generic example of a rack-mounted server is provided as an illustration of core network element 806. However, there may be multiple elements in the core network including database servers, such as a database 816, and security and authentication servers, such as an authentication server 818. Database 816 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 818 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the specific entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 806, authentication server 818, and database 816, may be local connections within a single rack.

[0081] Although the above-description used uplink and downlink processing of a packet in a UE as examples in various discussions, similar techniques may likewise be used for the other direction of processing and for processing in other devices, such as access nodes, and core network nodes. For example, any device that processes packets through a plurality of layers of a protocol stack may benefit some embodiments of the present disclosure, even if not specifically listed above or illustrated in the example network of FIG. 8.

[0082] Each of the elements of FIG. 8 may be considered a node of wireless network 800.

More detail regarding the possible implementation of a node is provided by way of example in the description of a node 700 in FIG. 7 above. Node 700 may be configured as user equipment 802, access node 804, or core network element 806 in FIG. 8. Similarly, node 700 may also be configured as computer 810, router 814, tablet 812, database 816, or authentication server 818 in FIG. 8.

[0083] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 700 in FIG. 7. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, DVD, and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0084] According to one aspect of the present disclosure, a method for spur cancellation can include accumulating a plurality of input samples of a reception chain at initialization of spur cancellation to provide an estimate of a spur having an amplitude and a phase. The method can also include cancelling the spur in the reception chain based on the estimate.

[0085] In some embodiments, the method can further include updating the cancelling the spur based on individual samples following the plurality of input samples.

[0086] In some embodiments, the cancelling the spur comprises applying an inverted estimate of the spur based on the accumulated plurality of input samples.

[0087] In some embodiments, the cancelling the spur can include applying a notch filter to the spur.

[0088] In some embodiments, the method can further include determining a received signal strength indicator for a signal to be received over the reception chain. The method can additionally include selectively enabling or disabling a notch filter based on the received signal strength indicator.

[0089] In some embodiments, the method can also include enabling or reconfiguring the notch filter between adjacent downlink symbols.

[0090] In some embodiments, the method can further include disabling the notch filter during discontinuous reception.

[0091] In some embodiments, the method can additionally include delaying notch filter power on until a symbol boundary.

[0092] In some embodiments, the cancelling can include controlling a pole magnitude coefficient according to a plurality of control bits.

[0093] According to another aspect of the present disclosure, an apparatus for controlling a pole magnitude for spur cancellation can include a first signal path connected to a source of an input signal. The apparatus can also include a first bit shifter connected to the first signal path and configured to provide a first intermediate output to a first adder. The first adder can also be connected to the first signal path. The first adder can be configured to provide a first output. The apparatus can also include a second bit shifter connected to the first signal path and configured to provide a second intermediate output to a second adder. The second adder can also be connected to the first output. The second adder can be configured to provide a second output. The second bit shifter can be controlled by a first control bit of a plurality of control bits configured to control a pole magnitude for spur cancellation.

[0094] In some embodiments, the apparatus can further include a third bit shifter connected to the first signal path and configured to provide a third intermediate output to a third adder. The third adder can also be connected to the second output. The third adder can be configured to provide a third output. The third bit shifter can be controlled by a second control bit of the plurality of control bits.

[0095] In some embodiments, the apparatus can also include a fourth bit shifter connected to the first signal path and configured to provide a fourth intermediate output to a fourth adder. The fourth adder can also be connected to the third output. The fourth adder can be configured to provide a fourth output. The fourth bit shifter can be controlled by a third control bit of the plurality of control bits.

[0096] According to a further aspect of the present disclosure, an apparatus for spur cancellation can include a first adder configured to provide an output signal at an output based on an input signal received at a first input and a correction signal received at a second input. The apparatus can also include a correction path configured to provide the correction signal based on the input signal and the output signal. The correction path can be configured to be reconfigurable from an acquisition mode in which a plurality of samples of the input signal are collected in a register to a tracking mode in which a correction signal is updated after every sample of the input and output signals.

[0097] In some embodiments, the apparatus can further include a pre-scaler configured to pre-scale the input signal during the acquisition mode.

[0098] In some embodiments, the apparatus can further include a gain element configured to scale the output signal according to a pole magnitude.

[0099] In some embodiments, the apparatus can also include a controller configured to control the apparatus selectively to operate in the acquisition mode or the tracking mode. [0100] In some embodiments, the gain element can be controlled with a device. The device can include a first signal path connected to a source of an input signal. The device can also include a first bit shifter connected to the first signal path and configured to provide a first intermediate output to a first adder of the device (which may be different from the first adder of the apparatus). The first adder can also be connected to the first signal path. The first adder of the device can be configured to provide a first output. The device can further include a second bit shifter connected to the first signal path and configured to provide a second intermediate output to a second adder. The second adder can also be connected to the first output. The second adder can be configured to provide a second output. The second bit shifter can be controlled by a first control bit of a plurality of control bits configured to control a pole magnitude for spur cancellation.

[0101] In some embodiments, the device can further include a third bit shifter connected to the first signal path and configured to provide a third intermediate output to a third adder. The third adder can also be connected to the second output. The third adder can be configured to provide a third output. The third bit shifter can be controlled by a second control bit of the plurality of control bits.

[0102] In yet another aspect of the present disclosure, a method for controlling a pole magnitude for spur cancellation can include receiving an input signal and performing a first bit shifting on the input signal. The method can also include combining a first bit shifting output of the first bit shifting with the input signal. The method can further include performing a second bit shifting on the input signal. The method can additionally include combining a second bit shifting output of the second bit shifting with the first output signal.

[0103] In some embodiments, the method can also include controlling the second bit shifting according to a first control bit of a plurality of control bits configured to control the pole magnitude.

[0104] In some embodiments, the method can further include performing a third bit shifting on the input signal, combining a third bit shifting output of the third bit shifting with the second output signal.

[0105] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance. [0106] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. [0107] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0108] Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted.

[0109] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. A method for spur cancellation, comprising: accumulating a plurality of input samples of a reception chain at initialization of spur cancellation to provide an estimate of a spur having an amplitude and a phase; and cancelling a spur in the reception chain based on the estimate.

2. The method of claim 1, further comprising: updating the cancelling the spur based on individual samples following the plurality of input samples.

3. The method of claim 1, wherein the cancelling the spur comprises applying an inverted estimate of the spur based on the accumulated plurality of input samples.

4. The method of claim 1, wherein the cancelling the spur comprises applying a notch filter to the spur.

5. The method of claim 4, further comprising: enabling or reconfiguring the notch filter between adjacent downlink symbols.

6. The method of claim 4, further comprising: disabling the notch filter during discontinuous reception.

7. The method of claim 4, further comprising: delaying notch filter power on until a symbol boundary.

8. The method of claim 1, wherein the cancelling comprises controlling a pole magnitude coefficient according to a plurality of control bits.

9. An apparatus for controlling a pole magnitude for spur cancellation, the apparatus comprising: a first signal path connected to a source of an input signal; a first bit shifter connected to the first signal path and configured to provide a first intermediate output to a first adder, wherein the first adder is also connected to the first signal path, and wherein the first adder is configured to provide a first output; and a second bit shifter connected to the first signal path and configured to provide a second intermediate output to a second adder, wherein the second adder is also connected to the first output, wherein the second adder is configured to provide a second output, and wherein the second bit shifter is controlled by a first control bit of a plurality of control bits configured to control a pole magnitude for spur cancellation.

10. The apparatus of claim 9, further comprising: a third bit shifter connected to the first signal path and configured to provide a third intermediate output to a third adder, wherein the third adder is also connected to the second output, wherein the third adder is configured to provide a third output, and wherein the third bit shifter is controlled by a second control bit of the plurality of control bits.

11. The apparatus of claim 10, further comprising: a fourth bit shifter connected to the first signal path and configured to provide a fourth intermediate output to a fourth adder, wherein the fourth adder is also connected to the third output, wherein the fourth adder is configured to provide a fourth output, and wherein the fourth bit shifter is controlled by a third control bit of the plurality of control bits.

12. An apparatus for spur cancellation, comprising: a first adder configured to provide an output signal at an output based on an input signal received at a first input and a correction signal received at a second input; and a correction path configured to provide the correction signal based on the input and output signals, wherein the correction path is configured to be reconfigurable from an acquisition mode in which a plurality of samples of the input signal are collected in a register to a tracking mode in which a correction signal is updated after every sample of the input and output signals.

13. The apparatus of claim 12, further comprising a pre-scaler configured to pre-scale the input signal during the acquisition mode.

14. The apparatus of claim 12, further comprising a gain element configured to scale the output signal according to a pole magnitude.

15. The apparatus of claim 12, further comprising: a controller configured to control the apparatus selectively to operate in the acquisition mode or the tracking mode.

16. The apparatus of claim 14, wherein the gain element is controlled with a device, the device comprising: a first signal path connected to a source of an input signal having; a first bit shifter connected to the first signal path and configured to provide a first intermediate output to a first adder of the device, wherein the first adder is also connected to the first signal path, and wherein the first adder of the device is configured to provide a first output; and a second bit shifter connected to the first signal path and configured to provide a second intermediate output to a second adder, wherein the second adder is also connected to the first output, wherein the second adder is configured to provide a second output, and wherein the second bit shifter is controlled by a first control bit of a plurality of control bits configured to control a pole magnitude for spur cancellation.

17. The apparatus of claim 16, the device further comprising: a third bit shifter connected to the first signal path and configured to provide a third intermediate output to a third adder, wherein the third adder is also connected to the second output, wherein the third adder is configured to provide a third output, and wherein the third bit shifter is controlled by a second control bit of the plurality of control bits.

18. A method for controlling a pole magnitude for spur cancellation, the method comprising: receiving an input signal; performing a first bit shifting on the input signal; combining a first bit shifting output of the first bit shifting with the input signal; performing a second bit shifting on the input signal; and combining a second bit shifting output of the second bit shifting with the first output signal.

19. The method of claim 18, further comprising: controlling the second bit shifting according to a first control bit of a plurality of control bits configured to control the pole magnitude.

20. The method of claim 18, the method further comprising: performing a third bit shifting on the input signal; and combining a third bit shifting output of the third bit shifting with the second output signal.