WO2021081813A1

WO2021081813A1 - Multi-core processor and scheduling method therefor, device, and storage medium

Info

Publication number: WO2021081813A1
Application number: PCT/CN2019/114383
Authority: WO
Inventors: 陶原; 卢毅军; 宋军; 奉有泉; 赵旭; 陈钢
Original assignee: 阿里巴巴集团控股有限公司
Priority date: 2019-10-30
Filing date: 2019-10-30
Publication date: 2021-05-06

Abstract

A multi-core processor (100) and a scheduling method therefor, a device, and a storage medium. Using a multi-core processor (100), the multi-core processor (100) comprising multiple processing cores (101), and a power consumption management mechanism on at least one of the processing cores (101) being in a disabled state. The processing core (101) supports the power consumption management mechanism, which is conducive to saving the power consumption of the multi-core processor (100); by disabling the power consumption management mechanism on some processing cores (101), tasks that are relatively sensitive to the power consumption management mechanism can be executed on said processing cores (101), ensuring the performance requirements of the tasks. Performance loss can be reduced as much as possible whilst reducing overall power consumption, ensuring the task execution efficiency.

Description

Multi-core processor and its scheduling method, equipment and storage medium

Technical field

This application relates to the technical field of power consumption management, and in particular to a multi-core processor and its scheduling method, device and storage medium.

Background technique

There are many ways to reduce system power consumption, such as Dynamic Power Management (DPM) and Dynamic Voltage and Frequency Scaling (DVFS). Take DVFS as an example. DVFS is essentially a low-power technology. The purpose is to set the operating voltage and clock frequency according to the actual power consumption of the CPU at the time, so as to ensure that the provided power meets the requirements without excessive performance. Thereby power consumption can be reduced.

However, in some application scenarios, the effect of DVFS and other technologies is not very satisfactory. While reducing system power consumption, it will also cause loss of system performance and increase response delay.

Summary of the invention

Various aspects of the present application provide a multi-core processor and its scheduling method, device, and storage medium, which are used to minimize performance loss and ensure task execution efficiency while reducing system power consumption.

An embodiment of the present application provides a multi-core processor, including: a plurality of processor cores; wherein a power consumption management mechanism on at least one processor core is in a disabled state.

The embodiment of the present application also provides a multi-core processor scheduling method, including: receiving a task to be processed; in the case that the task to be processed belongs to the first type of task, allocating the task to be processed to the multi-core processor The power consumption management mechanism is on a processor core in a disabled state; wherein the multi-core processor includes a plurality of processor cores, and the power consumption management mechanism on at least one processor core is in a disabled state.

An embodiment of the present application also provides a computer device, including: a multi-core processor; the multi-core processor includes a plurality of processor cores; wherein the power consumption management mechanism on at least one of the processor cores is in a disabled state.

The embodiment of the present application also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor is caused to implement the steps in the multi-core processor scheduling method provided by the embodiment of the present application. .

In the embodiment of the present application, a multi-core processor is used. The multi-core processor includes multiple processor cores, and the power consumption management mechanism on at least one processor core is disabled. The processor cores in the multi-core processor support power consumption. The management mechanism is conducive to saving the power consumption of multi-core processors; and by disabling the power management mechanism on some processor cores, some tasks that are sensitive to the power management mechanism can be executed on these processor cores, which is beneficial to ensure these The performance requirements of the task. It can be seen that the embodiment of the present application can reduce the performance loss as much as possible while reducing the overall power consumption, and ensure the execution efficiency of the task.

Description of the drawings

The drawings described here are used to provide a further understanding of the application and constitute a part of the application. The exemplary embodiments and descriptions of the application are used to explain the application, and do not constitute an improper limitation of the application. In the attached picture:

FIG. 1a is a schematic structural diagram of a multi-core processor provided by an exemplary embodiment of this application;

FIG. 1b is a schematic structural diagram of another multi-core processor provided by an exemplary embodiment of this application;

FIG. 1c is a schematic diagram of state changes of a power consumption management mechanism on a processor core provided by an exemplary embodiment of this application;

2 is a schematic flowchart of a multi-core processor scheduling method provided by an exemplary embodiment of this application;

FIG. 3 is a schematic flowchart of another multi-core processor scheduling method provided by an exemplary embodiment of this application;

Fig. 4 is a schematic structural diagram of a computer device provided by an exemplary embodiment of this application.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the present application clearer, the technical solutions of the present application will be described clearly and completely in conjunction with specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of this application.

In view of technical problems such as loss of system performance caused by the existing power consumption management mechanism and increased response delay, in some embodiments of the present application, a multi-core processor is used, and the multi-core processor includes multiple processor cores, and at least one processor core The power management mechanism on the CPU is in a disabled state; among them, the processor core supports the power management mechanism, which is conducive to saving the power consumption of multi-core processors; and the power management mechanism on some processor cores is disabled, which can be used in these processor cores. Performing some tasks that are more sensitive to the power management mechanism is conducive to ensuring the performance requirements of these tasks. It can be seen that the embodiment of the present application can reduce the performance loss as much as possible while reducing the overall power consumption, and ensure the execution efficiency of the task.

The technical solutions provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Fig. 1a is a schematic structural diagram of a multi-core processor provided by an exemplary embodiment of this application. As shown in FIG. 1a, the multi-core processor 100 includes a plurality of processor cores (Core) 101. Multiple refers to two or more. The processor core is an important part of a multi-core processor.

In this embodiment, the implementation form of the multi-core processor 100 and the processor core 101 is not limited. According to the different implementation forms of the processor core 101, the multi-core processor 100 will also have different implementation forms. For example, the processor core 101 may be a CPU core, and the multi-core processor 100 may be implemented as a multi-core CPU. For another example, the processor core 101 may be a GPU core, and the multi-core processor 100 may be implemented as a multi-core GPU. Of course, with the development of processor technology, the processor core 101 in this embodiment can also be implemented as other chip cores with information processing and program execution capabilities. Correspondingly, the multi-core processor 100 can also be implemented as a chip with corresponding functions. Multi-core chips.

In this embodiment, the processor core of the multi-core processor 100 supports a power management mechanism; the power management mechanism is a mechanism for power management of the processor core 101, which can dynamically adjust the power consumption of the processor core 101 to achieve savings The purpose of power consumption. According to different implementation forms of the multi-core processor 100, the power management mechanism supported by the processor core 101 will be different. The following is an example of the power management mechanism supported by the processor core 101:

In an optional embodiment, the power management mechanism supported by the processor core 101 includes DVFS and C-state. In another optional embodiment, the power consumption management mechanism supported by the processor core 101 only includes DVFS. In another optional embodiment, the power consumption management mechanism supported by the processor core 101 only includes C-state. DVFS and C-sate belong to the operating system-level power management mechanism and need to run in the kernel mode, which is referred to as the power management mechanism in the kernel mode for short.

Among them, DVFS is a dynamic technology that dynamically adjusts the operating frequency and voltage of the processor core 11 according to the different needs of the computing power of the application program that the processor core 11 runs, so as to achieve the purpose of energy saving. For the same processor core 11, the higher the operating frequency, the higher the required voltage, and the greater the energy consumption; on the contrary, the lower the operating frequency, the lower the required voltage and the lower the energy consumption. However, the frequency adjustment is usually related to the load, and is generally not real-time, and the adjustment speed may be relatively slow.

Among them, C-state is a low-power mechanism that allows the processor core 11 to enter a low-power state when it is idle. The C mode included in C-states starts from C0 to Cn, and C0 is the processor core 11 In normal working mode, the processor core 11 is in a normal operating state; the higher the value of n after C, the deeper the sleep of the processor core 11, the lower the power consumption of the processor core 11, and of course it takes more time to return To C0 mode; where n is a positive integer.

It should be noted that the power management mechanism supported by the processor core 101 may include an operating system-level power management mechanism, and may also include an application-level power management mechanism. In addition, for the same processor core 101, the power consumption management mechanism supported by it may include one or more. For different processor cores 101, the supported power management mechanisms may be completely the same, may also be partially the same, or may be completely different.

In this embodiment, the processor core 101 supports a power management mechanism. When the power management mechanism is enabled, the processor core can be dynamically adjusted according to the computing power demand, load condition, or busyness of the processor core 101. The frequency of 101 or the state of the hardware circuit, etc. (the object of dynamic adjustment may be determined by the specific power consumption management mechanism), which is beneficial to reduce the power consumption of the processor core 101, thereby reducing the overall power consumption of the multi-core processor 100.

However, in practical applications, some tasks have higher performance requirements, and their performance is more sensitive to power management mechanisms such as C-state or DVFS. If these tasks are executed with power management mechanisms such as C-state or DVFS enabled, the performance of these tasks will be reduced or cannot be guaranteed; if all power management mechanisms such as C-state or DVFS are turned off, it means The overall energy consumption will increase. In view of this, in this embodiment, the power management mechanism on at least one processor core 101 is in a disabled state, and the processor cores 101 with these power management mechanisms in a disabled state will always run at the set operating frequency. Will enter the idle state (idle state), here does not enter the idle state actually means that it will not enter the low-power mode or will not run at other frequencies lower than the set operating frequency, so it can provide better performance . Among them, the higher the operating frequency set for the processor core 101, the faster the processing speed of the processor core 101 and the higher the performance. Among them, the operating frequency can be flexibly set for the processor core 101 according to performance requirements. For example, the set operating frequency may be the highest operating frequency of the processor core 101, and when the power management mechanism on the processor core 101 is disabled, the processor core 101 will always run at the highest operating frequency. Advance can bring optimal performance. In addition, the same operating frequency can be set for different processor cores 101, or different operating frequencies can be set for different processor cores 101. Among them, executing these tasks on the processor core 101 in which the power management mechanism is in a disabled state can overcome the adverse effect of the power management mechanism on the performance of these tasks, and is beneficial to satisfy the performance requirements of these tasks.

In the embodiment of the present application, the number of processor cores 101 whose power management mechanism is in a disabled state is not limited, and there may be one or more. In an optional embodiment, at the same time, the power consumption management mechanisms on 2N (ie, even number) processor cores 101 are in a disabled state; N is a positive integer. Of course, at the same moment, the number of processor cores 101 with the power management mechanism in the disabled state may also be an odd number, for example, 1, 3, 5, etc., which is not limited.

In an alternative embodiment, as shown in FIG. 1b, a scheduler 102 runs on multiple processor cores 101 of the multi-core processor 100. Specifically, the scheduler 102 can run on any one or several processor cores 101. Of course, in addition to running the scheduler 102 on the processor core 101 running the scheduler 102, its remaining processing capacity can also be used to perform other tasks. In addition, the scheduler 102 is a software scheduler, which is a program running on multiple processor cores 101 and is mainly responsible for task scheduling on the multiple processor cores 101. The scheduler 102 may be an operating system (OS) level program of the multi-core processor 100, or an application level program (for example, an application program), which is not limited. In FIG. 1b, a program in which the scheduler belongs to the OS level is taken as an example for illustration, but it is not limited to this.

In this embodiment, the scheduler 102 can receive the task to be processed, determine the type of the task to be processed; and in the case of determining that the task to be processed belongs to the first type of task, assign the task to be processed to the power management mechanism is disabled On the processor core 101 in the state, the processor core 101 whose power management mechanism is in the disabled state is responsible for executing tasks to be processed. Because the processor core 101 with the power management mechanism in the disabled state will not enter the idle state, it will run at the set operating frequency, and this type of processor core 101 will perform pending tasks, and will not be generated by the power management mechanism. Delay, can process the task to be processed in time, can ensure that the task to be processed is not affected by the power management mechanism, improve the execution efficiency of the task to be processed, and ensure the performance of the task to be processed.

Among them, the first type of tasks can be tasks that have certain requirements on performance and are more sensitive to power management mechanisms. For example, from the perspective of performance requirements, the first type of tasks can include, but are not limited to: tasks that require high processing delay (for example, require a delay less than the set delay threshold), and have high real-time requirements ( For example, tasks that require response time not to exceed the set response time threshold), and so on. For example, some control tasks may have higher real-time requirements. For another example, some interrupt tasks (such as network interrupt processing tasks) have higher requirements for time delay. In addition, instant analysis tasks, instant query tasks, etc. can be used as examples of the first type of tasks. It should be noted that this embodiment does not limit the first type of tasks, and allows flexible setting according to application scenarios.

In this embodiment, there is no limitation on the allocation manner in which the scheduler 102 allocates to-be-processed tasks to the processor cores 101 whose power management mechanism is in the disabled state. The following is an example of the allocation method:

For example, in one embodiment, the scheduler 102 may compare the utilization rates of the processor cores 101 whose power management mechanism is disabled, and select the utilization rate to be lower than the set utilization threshold value or select the lowest utilization rate among them. The processor core 101 of the processor allocates the task to be processed to the selected processor core 101. Among them, the utilization rate of the processor core 101 is low, indicating that the processor core 101 is relatively easy or has better performance. Among the processor cores 101 with the power management mechanism in the disabled state, the processor core 101 that is relatively easy or has the better performance is executed. Processing tasks, while ensuring task performance, is conducive to further improving the execution efficiency of the tasks to be processed.

For another example, in an embodiment, the scheduler 102 may compare the load of each processor core 101 whose power management mechanism is disabled, and select the load to be lower than the set load threshold or select the load from it. The lowest processor core 101 allocates the task to be processed to the selected processor core 101. Among them, the load of the processor core 101 is relatively low, indicating that the processor core 101 is relatively easy and has sufficient computing resources. The relatively easy processor core 101 among the processor cores 101 whose power management mechanism is disabled performs the tasks to be processed. , Under the condition of ensuring task performance, it is helpful to further improve the execution efficiency of the task to be processed.

Wherein, the load of each processor core 101 can be determined according to the task information being queued in the task queue of each processor core 101. For example, the load of each processor core 101 can be determined according to the number of tasks being queued in the task queue. Generally speaking, the higher the number of tasks being queued, the greater the load of the corresponding processor core 101. For another example, the load of each processor core 101 can also be determined according to the priority of the task being queued in the task queue. Generally speaking, the higher the priority of the task being queued, the greater the load of the corresponding processor core 101. For another example, the load of each processor core 101 can also be determined according to the number and priority of the tasks being queued in the task queue at the same time. Generally speaking, for example, a weighted summation of the number and priority of the tasks being queued can be performed to obtain the load of the corresponding processor core 101; the larger the result of the weighted summation, the greater the load of the processor core 101.

For another example, in an implementation manner, the operating frequencies of the processor cores 101 whose power management mechanism is in a disabled state are not completely the same. Based on this, the scheduler 102 can compare the operating frequencies of the processor cores 101 whose power management mechanism is disabled, and select the processor core 101 whose operating frequency is higher than the set frequency threshold or the highest operating frequency to be processed. Tasks are assigned to the selected processor core 101. Among them, the operating frequency of the processor core 101 is relatively high, indicating that the processing speed of the processor core 101 is relatively fast. Processing tasks, while ensuring task performance, is conducive to further improving the execution efficiency of the tasks to be processed.

For another example, in an implementation manner, the scheduler 102 may use a hash algorithm to allocate the tasks to be processed to each of the processor cores 101 whose power management mechanism is disabled.

It is explained here that in the above-mentioned several implementation manners, in the process of allocating tasks to be processed to the processor cores 101 whose power management mechanism is in a disabled state, it is solely based on the utilization, load, or work of the processor cores 101. frequency. Of course, any two or three of the utilization, load, and operating frequency of the processor core 101 can also be combined simultaneously to determine which processor core 101 whose power management mechanism is in a disabled state to allocate the task to be processed. In addition, in addition to the above three types of information, other indicators or attribute information of the processor core 101 may also be considered. For example, the cache size, bus speed, and/or operating voltage of the processor core 101 may also be considered.

Further, in some embodiments of the present application, the application scenarios of the multi-core processor 100 may be combined to pre-categorize each task into the first type of task and the second type of task according to the performance requirements of each task in the application scenario. Among them, the second type of tasks refer to tasks other than the first type of tasks. For the description of the first type of task, please refer to the above description, which will not be repeated here. Further, the mapping relationship between the identification information of the task and the task type can be maintained. Optionally, the mapping relationship includes the identification information of each task under the first type of task, or includes the identification information of each task under the second type of task, Or include the identification information of each task under the first type of task and the identification information of each task under the second type of task at the same time. Based on this, after receiving the task to be processed, the scheduler 102 can match the identification information of the task to be processed in the mapping relationship between the identification information of the task to be maintained and the task type, and according to the matching result, it is obtained that the task to be processed belongs to The judgment result of the first type of task or the second type of task.

Further optionally, if it is determined that the task to be processed belongs to the second type of task and does not belong to the first type of task, the task to be processed can be allocated to the processor core 101 whose power consumption management mechanism is enabled. The processor core 101 whose management mechanism is in an enabled state is responsible for executing tasks to be processed. With the help of the power consumption management mechanism on the processor core 101, the power consumption of the processor core 101 can be saved while the tasks to be processed are completed.

In the same way, in this embodiment of the present application, the allocation method of allocating tasks to be processed to the processor cores 101 whose power management mechanism is in the enabled state is not limited. The specific allocation method of allocating to-be-processed tasks to the processor cores with the power management mechanism in the enabled state is similar to the allocation method of allocating to-be-processed tasks to the processor cores with the power management mechanism in the disabled state, see The foregoing implementation manners will not be repeated here.

In some embodiments of the present application, the multi-core processor 100 includes multiple processor cores 101. Among the multiple processor cores 101, some of the processor cores 101 have a power management mechanism in a disabled state, and the other part of the processor cores is disabled. The power consumption management mechanism on 101 is in an enabled state, thus forming a heterogeneous multi-core processor. In these embodiments, the number of processor cores 101 with the power management mechanism in the disabled state and the number of processor cores 101 with the power management mechanism in the enabled state are fixed.

For example, suppose a multi-core processor includes 4 processor cores, of which the power management mechanism on 2 processor cores is disabled, and the power management mechanism on these 2 processor cores will always be disabled ; The power management mechanism on the other two processor cores is in the enabled state, and the power management mechanism on the two processor cores will always be in the enabled state.

For another example, a multi-core processor includes 6 processor cores, of which, the power management mechanisms on 3 processor cores are disabled, and the power management mechanisms on these 3 processor cores will always be disabled ; The power management mechanisms on the other three processor cores are in the enabled state, and the power management mechanisms on the three processor cores will always be in the enabled state.

For another example, a multi-core processor includes 4 processor cores, of which, the power management mechanism on one processor core is disabled, and the power management mechanism on this processor core will always be disabled; in addition, The power management mechanisms on the three processor cores are in an enabled state, and the power management mechanisms on the three processor cores will always be in an enabled state.

In some other embodiments of the present application, the multi-core processor 100 includes multiple processor cores 101. Among the multiple processor cores 101, some of the processor cores 101 have a power management mechanism in a disabled state, and some of the processor cores 101 are disabled. The power consumption management mechanism on the core 101 is in an enabled state, thereby forming a heterogeneous multi-core processor. In these embodiments, the number of processor cores 101 whose power management mechanism is in a disabled state can be dynamically changed according to application requirements; accordingly, the number of processor cores 101 whose power management mechanism is in an enabled state will also be dynamically changed according to application requirements. Variety. The application requirements here mainly refer to the requirements generated by the first type of tasks that are more sensitive to the power management mechanism. Based on this, as shown in FIG. 1b, the multi-core processor 100 further includes a manager 103. The manager 103 is mainly used to dynamically adjust the state of the power management mechanism on the multiple processor cores 101 according to application requirements, so as to achieve the purpose of dynamically changing the number of processor cores 101 with the power management mechanism in the disabled state according to the application requirements. Among them, the state of the power management mechanism includes two states: a disabled state and an enabled state. The manager 103 adjusting the state of the power management mechanism on the processor core 101 includes: adjusting the power management mechanism on the processor core 101 from a disabled state to an enabled state, or changing the power management mechanism on the processor core 101 from a disabled state to an enabled state. The enabled state is adjusted to the disabled state.

Among them, the manager 103 is a manager in the form of software, and is a program running on multiple processor cores 101. Specifically, the manager 103 can run on any one or several processor cores 101. Of course, in addition to running the manager 103, the remaining processing capacity of the processor core 101 running the manager 103 can also be used to perform other tasks. In addition, the manager 103 may be an operating system (OS) level program of the multi-core processor 100, or an application level program (for example, an application program), which is not limited. In FIG. 1b, a program of the manager 103 belonging to the OS level is taken as an example for illustration, but it is not limited to this.

In the embodiment of the present application, the implementation manner in which the manager 103 dynamically adjusts the state of the power consumption management mechanism on the multiple processor cores 101 according to application requirements is not limited. The following example illustrates:

For example, in Embodiment A, the manager 103 can monitor the overall processing capacity of the processor cores whose power management mechanism is disabled. When the power management mechanism is disabled, the overall processing capabilities of the processor cores cannot meet application requirements. That is, when the overall processing capacity of the processor core with the power management mechanism in the disabled state is insufficient, select the processor cores to be disabled from the processor cores with the power management mechanism in the enabled state, and set the processor cores on the processor cores to be disabled. The power management mechanism is disabled. Wherein, the number of processor cores to be disabled may be one or more. This can increase the number of processor cores with the power management mechanism in the disabled state, and increase the overall processing capacity of the processor cores with the power management mechanism in the disabled state, so as to meet application requirements.

In this embodiment, the manner in which the manager 103 selects the processor core to be disabled is not limited, and the following manners can be used but not limited to:

Method A1: In method A1, one or more processor cores can be randomly selected as the processor cores to be disabled from among the processor cores in which the power consumption management mechanism is in the enabled state. This method is relatively simple, easy to implement, and highly efficient. This method A1 is suitable for various types of multi-core processors, especially suitable for multi-core processors with exactly the same processor cores, such as X86 processors.

In method A1, the number of processor cores to be disabled that are allowed to be selected each time can be preset. Assuming that the number is preset to 1, 2, or 4, etc., one, 2, or 4 processor cores can be randomly selected from the processor cores in which the power management mechanism is enabled each time. The processor core is to be disabled.

Manner A2: In Manner A2, all processor cores among the processor cores whose power consumption management mechanism is in the enabled state may be used as processor cores to be disabled. This method is relatively simple, easy to implement, and highly efficient. The method A2 is suitable for various types of multi-core processors, both for multi-core processors with identical processor cores, and for multi-core processors with different processor cores.

In method A2, suppose that the multi-core processor contains a total of 6 processor cores, and the power management mechanism on 2 processor cores is currently disabled, and the overall processing capacity of these 2 processor cores does not meet the application requirements ( That is, the overall processing capacity of these 2 processor cores is insufficient), the remaining 4 processor cores can be used as processor cores to be disabled, thereby disabling the power management mechanism on these 4 processor cores, so that 6 processing The processor cores are all processor cores with the power management mechanism in the disabled state, and the overall processing capabilities of the processor cores with the power management mechanism in the disabled state will be greatly improved.

Method A3: In method A3, one or more processor cores can be selected as the to-be-disabled processor cores from the processor cores in the enabled state of the power consumption management mechanism according to the amount of tasks corresponding to the application requirements. This method can more accurately and reasonably determine the number of processor cores to be disabled, avoid disabling the power management mechanism on the processor cores too much, and maximize power savings while meeting application requirements. This method A3 is suitable for various types of multi-core processors, not only for multi-core processors with identical processor cores, but also for multi-core processors with different processor cores.

Optionally, the task amount corresponding to the application demand can be predicted based on the task amount in the historical period. Alternatively, the task volume corresponding to the application demand can also be predicted according to the utilization rate or the load volume of the processor core in the disabled state of the power management mechanism in the recent period of time. Alternatively, the corresponding task amount can also be carried in the application requirements, so that the corresponding task amount can be extracted from the application requirements. The amount of tasks corresponding to application requirements mainly refers to the amount of tasks belonging to the first type of task.

Further optionally, the task amount corresponding to the application requirement can be converted into the target load amount, and the load amount that can be processed by each processor core with the power management mechanism in the enabled state can be calculated, according to the processing of the power management mechanism in the enabled state. The amount of load that the processor core can handle, from which a processor core adapted to the target load amount is selected as the processor core to be disabled.

For example, if there is a load that can be handled by a single processor core that is greater than the target load and is closest to the target load, the processor core can be used as the processor core to be disabled.

For another example, if the load that a single processor core can handle is less than the target load, several processor cores can be selected. The sum of the load that these processor cores can handle is greater than the target load, and is equal to the target load. The load is the closest, and these processor cores are used as the processor cores to be disabled.

Method A4: In method A4, the processing capabilities of the processor cores included in the multi-core processor are not completely the same. Based on this, according to the processing capabilities of the processor cores, one or more processor cores can be selected as the processor cores to be disabled from the processor cores in which the power management mechanism is in the enabled state. This method A4 is suitable for multi-core processors with different processor cores.

Optionally, from among the processor cores in which the power consumption management mechanism is in an enabled state, a processor core with stronger processing capability may be selected as the processor core to be disabled. Of course, it is also possible to preferentially select a processor core with a weaker processing capability as a processor core to be disabled from among the processor cores in which the power management mechanism is in an enabled state.

In an embodiment of the present application, the multi-core processor includes multiple processor cores, and the multiple processor cores are divided into two types, namely the first type of processor core and the second type of processor core. The first type of processor The processing power of the core is stronger than that of the second type of processor core. Optionally, the multi-core processor may be implemented as a multi-core processor of the ARM architecture. The multi-core processor of the ARM architecture includes a big core (big Core) and a small core (LITTLE core), where the big core is equivalent to the first type of processing The small core is equivalent to the second type of processor core.

Optionally, for the above-mentioned multi-core processors including two types of processor cores, when the manager 103 selects the processor cores to be disabled according to the processing capabilities of the processor cores, it may first determine the processor cores whose power management mechanism is in the enabled state. Whether there is a second type of processor core in the, if there is a second type of processor core with the power management mechanism in the enabled state, select the processor core to be disabled from the second type of processor core with the power management mechanism in the enabled state; If there is no second-type processor core with the power management mechanism in the enabled state, select the to-be-disabled processor core from the first-type processor cores with the power management mechanism in the enabled state. In this embodiment, the processor core with lower processing capability has relatively low power consumption, and the power consumption management mechanism on this type of processor core is preferentially disabled, and the increase in power consumption is relatively small. or

Optionally, for the foregoing multi-core processor including two types of processor cores, when the manager 103 selects the processor cores to be disabled according to the processing capabilities of the processor cores, it may also consider the processing capabilities of the processor cores and the corresponding application requirements. The amount of tasks. In the case that the task volume corresponding to the application demand is greater than or equal to the set task volume threshold, select the processor core to be disabled from the first type of processor cores with the power management mechanism in the enabled state; in the task volume corresponding to the application demand If it is less than the set task amount threshold, the processor core to be disabled is selected from the second type of processor cores in which the power consumption management mechanism is in the enabled state. In this embodiment, when the amount of tasks corresponding to the application requirements is relatively small, the power consumption management mechanism on the second type of processor cores with relatively low processing capabilities is preferentially disabled, due to the processing capabilities of this type of processor cores. Relatively low, its power consumption is relatively low, and the increase in power consumption is relatively small.

For another example, in Embodiment B, the manager 103 may monitor the overall processing capability of the processor cores whose power management mechanism is disabled, and the overall processing capabilities of the processor cores whose power management mechanism is disabled meet application requirements and In the case of surplus, select the processor cores to be enabled from the processor cores with the power management mechanism in the disabled state, and re-enable the power management mechanism on the processor cores to be enabled to reduce multi-core processing with the help of the power management mechanism The power consumption of the device 100. The number of processor cores to be activated can be one or more.

In this embodiment, the manner in which the manager 103 selects the processor core to be activated is not limited, and the following manners can be used but not limited to:

Manner B1: In Manner B1, one or more processor cores can be randomly selected as the processor cores to be enabled from the processor cores in which the power management mechanism is in a disabled state. This method is relatively simple, easy to implement, and highly efficient. This method B1 is suitable for various types of multi-core processors, and is especially suitable for multi-core processors with identical processor cores.

In method B1, the number of processor cores to be activated that are allowed to be selected each time can be preset. Assuming that the number is preset to 1, 2, or 4, etc., one, 2, or 4 processor cores can be randomly selected from the processor cores in which the power management mechanism is disabled each time. The processor core is to be enabled.

Method B2: In method B2, one or more processor cores can be selected as the to-be-enabled processor cores from the processor cores whose power consumption management mechanism is in the disabled state according to the amount of tasks corresponding to the application requirements. This method can more accurately and reasonably determine the number of processor cores to be activated, and can avoid excessively enabling the power management mechanism on the processor cores, thus failing to meet the application requirements. It can meet the application requirements while doing as many as possible Enable the power management mechanism on the processor core to save power. This method B2 is suitable for various types of multi-core processors, not only for multi-core processors with identical processor cores, but also for multi-core processors with different processor cores.

Regarding the task amount corresponding to the application requirements, please refer to the description in the aforementioned method A3, which will not be repeated here.

Manner B3: In Manner B3, the processing capabilities of the processor cores included in the multi-core processor are not completely the same. Based on this, one or more processor cores can be selected as the processor cores to be enabled from among the processor cores whose power management mechanism is in a disabled state according to the processing capabilities of the processor cores. This method B3 is suitable for multi-core processors with different processor cores.

Optionally, from among the processor cores in which the power consumption management mechanism is in a disabled state, a processor core with stronger processing capability may be preferentially selected as the processor core to be activated. The processing power of the processor core is stronger, which means that its power consumption is also higher. The power management mechanism on this type of processor core is preferentially enabled, which is conducive to saving power consumption.

In an embodiment of the present application, the multi-core processor includes multiple processor cores, and the multiple processor cores are divided into two types, namely the first type of processor core and the second type of processor core. The first type of processor The processing power of the core is stronger than that of the second type of processor core.

Optionally, for the foregoing multi-core processors including two types of processor cores, when determining the processor cores to be activated, the manager 103 may simultaneously combine the processing capabilities of the processor cores and the amount of tasks corresponding to application requirements. For example, in the case that the task volume corresponding to the application demand is less than or equal to the set lower limit of the task volume, it means that the task volume corresponding to the application demand is relatively small, so the first type of processing can be taken from the power management mechanism in the disabled state. Select the processor core to be enabled in the processor core; in the case that the task volume corresponding to the application demand is greater than the set task volume lower limit, select the processor core to be enabled from the second type of processor core with the power management mechanism in the disabled state器核。 The core. In this embodiment, when the amount of tasks corresponding to the application requirements is relatively small, the power consumption management mechanism on the first type of processor cores with relatively strong processing capabilities is preferentially enabled, due to the processing capabilities of such processor cores. Stronger, its power consumption is relatively high, and priority is given to enabling the power management mechanism on it, which is conducive to saving power consumption.

It is explained here that in the foregoing implementations A and B, the manager 103 needs to monitor the overall processing capabilities of the processor cores whose power management mechanism is in a disabled state. Among them, various indicators or attribute information of each processor core with the power management mechanism in the disabled state can be used to characterize the overall processing capability of the processor core with the power management mechanism in the disabled state.

Optionally, the utilization rate of each processor core whose power management mechanism is disabled can be monitored; according to the utilization rate of each processor core whose power management mechanism is disabled, determine the processor whose power management mechanism is disabled Whether the overall processing capability of the core meets the application requirements, that is, it is determined whether the overall processing capability of the processor core whose power management mechanism is disabled is sufficient.

For example, if the utilization rate of each processor core whose power management mechanism is disabled is greater than or equal to the set utilization threshold, it is determined that the overall processing capacity of the processor core whose power management mechanism is disabled cannot meet the application requirements , That is, the overall processing capacity of the processor cores whose power management mechanism is disabled is insufficient. Conversely, it can be determined that the overall processing capability of the processor core with the power management mechanism in the disabled state can meet the application requirements. Further, if the power management mechanism is in the disabled state of each processor core, the proportion of processor cores whose utilization is less than the set utilization threshold is greater than or equal to the set first proportion threshold, for example, there are more than 2/3 If the utilization of the processor core is less than the set utilization threshold, it can be determined that the processing capacity of the processor core with the power management mechanism in the disabled state can not only meet the application requirements but also far exceed the application requirements, that is, the overall processing capacity is surplus.

For another example, if the proportion of processor cores whose utilization rate is greater than the set utilization threshold value in each processor core is greater than the set second proportion threshold value, for example, the utilization rate of more than 2/3 of the processor cores is greater than the set utilization rate threshold. The utilization threshold determines that the overall processing capability of the processor core whose power management mechanism is disabled cannot meet application requirements, that is, the overall processing capability of the processor core whose power management mechanism is disabled is insufficient. Conversely, it can be determined that the overall processing capability of the processor core with the power management mechanism in the disabled state can meet the application requirements. Further, if the power management mechanism is in the disabled state of each processor core, the proportion of processor cores whose utilization is less than the set utilization threshold is greater than or equal to the set first proportion threshold, for example, there are more than 1/2 If the utilization rate of the processor core is less than the set utilization threshold, it can be determined that the processing capacity of the processor core whose power management mechanism is disabled not only meets the application requirements but also far exceeds the application requirements, that is, the overall processing capacity is surplus. It should be noted that the first ratio threshold may be the same as or different from the second ratio threshold, which is not limited.

Optionally, the load of each processor core with the power management mechanism in the disabled state can be monitored; according to the load of each processor core with the power management mechanism in the disabled state, determine the processor with the power management mechanism in the disabled state Whether the overall processing capability of the core meets the application requirements, that is, it is determined whether the overall processing capability of the processor core whose power management mechanism is disabled is sufficient.

For example, if the load of each processor core with the power management mechanism in the disabled state is greater than or equal to the set load threshold, it is determined that the overall processing capacity of the processor core with the power management mechanism in the disabled state cannot meet the application requirements , That is, the overall processing capacity of the processor cores whose power management mechanism is disabled is insufficient. Conversely, it can be determined that the overall processing capability of the processor core with the power management mechanism in the disabled state can meet the application requirements. Further, if the power management mechanism is in the disabled state of each processor core, the proportion of processor cores whose load is less than the set load threshold is greater than or equal to the set third proportion threshold, for example, more than 2/3 If the load of the processor core is less than the set load threshold, it can be determined that the processing capacity of the processor core with the power management mechanism in the disabled state can not only meet the application requirements but also far exceed the application requirements, that is, the overall processing capacity is surplus.

For another example, if the proportion of processor cores with load greater than the set load threshold in each processor core is greater than the set fourth proportion threshold, for example, more than 2/3 of the processor cores have load greater than the set threshold. The load threshold determines that the overall processing capabilities of the processor cores with the power management mechanism in the disabled state cannot meet application requirements, that is, the overall processing capabilities of the processor cores with the power management mechanism in the disabled state are insufficient. Conversely, it can be determined that the overall processing capability of the processor core with the power management mechanism in the disabled state can meet the application requirements. Further, if the power management mechanism is in the disabled state of each processor core, the proportion of processor cores whose load is less than the set load threshold is greater than or equal to the set third proportion threshold, for example, there are more than 1/2 If the load of the processor core is less than the set load threshold, it can be determined that the processing power of the processor core whose power management mechanism is disabled can not only meet the application requirements but also far exceed the application requirements, that is, the power management mechanism is disabled The overall processing power of the state of the processor core is excessive. It should be noted that the third ratio threshold may be the same as or different from the fourth ratio threshold, which is not limited.

Optionally, the utilization rate and load of each processor core whose power management mechanism is disabled can be monitored at the same time; power management can be determined according to the utilization and load of each processor core whose power management mechanism is disabled Whether the overall processing capacity of the processor core with the mechanism in the disabled state meets the application requirements.

For a detailed implementation of determining whether the overall processing capacity of a processor core with a power management mechanism in a disabled state meets application requirements based on the utilization and load of each processor core with the power management mechanism in the disabled state, please refer to the above implementation The example is similar to the implementation, so I won't repeat it here.

With reference to the state change diagram of the power management mechanism on the processor core shown in FIG. 1c, taking the network interrupt task in the multiqueue network interface card (Network Interface Card, NIC) as an example, the present application The working principle of the multi-core processor provided in the embodiment is described.

The multi-core processor of this embodiment is applied to a multi-queue NIC, and the multi-queue NIC includes multiple processor cores; in the initial state, the power consumption management mechanisms on the two processor cores, such as C-state and DVFS, are disabled; The power management mechanisms on the remaining processor cores, such as C-state and DVFS, are in an enabled state.

For the convenience of description and distinction, considering that the processor cores with the power management mechanism in the disabled state can give priority to ensuring the performance requirements of the task, this type of processor core can be called a performance-type processor core, as shown in Figure 1c. The processor cores in the dotted frame; for the same reason, considering that the processor cores with the power management mechanism in the enabled state have obvious power saving advantages, such processor cores can be called energy-saving processor cores, as shown in the figure The processor core in the solid line box in 1c.

When a network interrupt task arrives, the scheduler prioritizes the performance-based processor core, and can use a hash algorithm to assign the network interrupt task to the performance-based processor core. The performance-based processor core will not enter the idle state, so there is no delay caused by the C-state or DVFS mechanism, and the network interrupt task can be processed in time. Optionally, the performance-based processor core can run at the highest frequency, so that the network interrupt task can be processed with the best performance.

During the operation of the performance-type processor core, the manager can monitor some performance indicators of the performance-type processor core, such as the utilization rate and load of the processor core. If the overall performance index of the current performance-based processor core is greater than or equal to the corresponding index threshold, the manager can remap the network interrupt task to the remaining processor cores; at the same time, the power management mechanism on the remaining processor cores, such as C-state and DVFS will be disabled. This means that some energy-saving processor cores will become performance-based processor cores. It may be that all energy-saving processor cores become performance-based processor cores, or some energy-saving processor cores will become performance-based processor cores. Processor core. Among them, in FIG. 1c, the graying of the dashed box where the performance-based processor core is located indicates that the performance-based processor core exceeds the corresponding indicator threshold. In Fig. 1c, an example is illustrated by taking all energy-saving processor cores into performance processor cores.

Later, during the operation of the performance-based processor core, the manager will continue to monitor some performance indicators of the performance-based processor core, such as the utilization rate and load of the processor core. If the overall performance index of the current performance-based processor core is less than the corresponding indicator threshold, the manager can change some performance-based processor cores back to energy-saving processor cores, and remap network interrupt tasks to the remaining performance-based processor cores on.

It can be seen that the embodiment of the present application provides a multi-core processor with a heterogeneous power management mechanism, which can save the power consumption of the multi-core processor as much as possible while ensuring task performance, and can meet the performance requirements of C-state or DVFS for some tasks. Such as power consumption management mechanism is more sensitive to the needs of task scenarios.

FIG. 2 is a schematic flowchart of a multi-core processor scheduling method provided by an exemplary embodiment of this application. As shown in Figure 2, the method includes:

201. Receive a task to be processed.

202. In a case where the task to be processed belongs to the first type of task, allocate the task to be processed to the processor core of the multi-core processor whose power consumption management mechanism is in a disabled state.

In this embodiment, the multi-core processor includes multiple processor cores, the processor cores support a power consumption management mechanism, and the power consumption management mechanism on at least one processor core is in a disabled state. The power management mechanisms supported by the processor core include, but are not limited to, DVFS and C-state. In this embodiment, the number of processor cores whose power management mechanism is in a disabled state is not limited, and it may be one or multiple. In an optional embodiment, at the same moment, the power consumption management mechanisms on 2N (that is, an even number) of processor cores are in a disabled state; N is a positive integer. Of course, at the same moment, the number of processor cores with the power management mechanism in the disabled state may also be an odd number, for example, 1, 3, 5, etc., which is not limited.

In this embodiment, the first type of tasks may be tasks that have certain requirements on performance and are more sensitive to the power management mechanism. For example, from the perspective of performance requirements, the first type of tasks can include, but are not limited to: tasks that require high processing delay (for example, require a delay less than the set delay threshold), and have high real-time requirements ( For example, tasks that require response time not to exceed the set response time threshold), and so on. For example, some control tasks may have higher real-time requirements. For another example, some interrupt tasks (such as network interrupt processing tasks) have higher requirements for time delay. In addition, real-time scheduling tasks, instant analysis tasks, and instant query tasks can all be used as examples of the first type of tasks. It should be noted that this embodiment does not limit the first type of tasks, and allows flexible setting according to application scenarios.

In this embodiment, the task to be processed is received, and the type of the task to be processed is determined; and when it is determined that the task to be processed belongs to the first type of task, the task to be processed is assigned to the processor whose power management mechanism is disabled On the core, the processor core whose power management mechanism is disabled is responsible for executing tasks to be processed. Because the processor cores with the power management mechanism in the disabled state will not enter the idle state, they will run at the set operating frequency, and such processor cores will perform pending tasks without delay due to the power management mechanism. The task to be processed can be processed in time, which can ensure that the task to be processed is not affected by the power management mechanism, improve the execution efficiency of the task to be processed, and ensure the performance of the task to be processed.

In the foregoing or following embodiments of the present application, the allocation method for allocating to-be-processed tasks to processor cores whose power management mechanism is in a disabled state is not limited. The following is an example of the allocation method:

For example, in an embodiment, the utilization rate of each processor core whose power management mechanism is disabled may be compared, and the utilization rate may be selected from the set utilization threshold value or the processor core with the lowest utilization rate may be selected. , The task to be processed is assigned to the selected processor core. Among them, the low utilization rate of the processor core indicates that the processor core is relatively easy or has better performance. Among the processor cores with the power management mechanism in the disabled state, the processor core that is relatively easy or has the better performance performs the task to be processed. In the case of ensuring task performance, it is beneficial to further improve the execution efficiency of the task to be processed.

For another example, in an embodiment, the load of each processor core whose power management mechanism is disabled can be compared, and the load is lower than the set load threshold, or the processor with the lowest load can be selected from it. Core, the task to be processed is allocated to the selected processor core. Among them, the load of the processor core is relatively low, indicating that the processor core is relatively easy, and the computing resources are sufficient. The relatively easy processor core among the processor cores in the disabled state of the power management mechanism executes the tasks to be processed, and the task is guaranteed. In the case of performance, it is helpful to further improve the execution efficiency of the task to be processed.

Among them, the load of each processor core can be determined according to the task information being queued in the task queue of each processor core. For example, the load of each processor core can be determined according to the number of tasks being queued in the task queue. Generally speaking, the higher the number of tasks being queued, the greater the load on the corresponding processor core. For another example, the load of each processor core can also be determined according to the priority of the task being queued in the task queue. Generally speaking, the higher the priority of the task being queued, the greater the load of the corresponding processor core. For another example, the load of each processor core can also be determined according to the number and priority of the tasks being queued in the task queue at the same time. Generally speaking, for example, you can perform a weighted summation on the number and priority of the tasks being queued to obtain the load of the corresponding processor core; the larger the result of the weighted summation, the greater the load of the processor core.

For another example, in an embodiment, the operating frequencies of the processor cores in the disabled state of the power management mechanism are not completely the same. Based on this, the operating frequency of each processor core whose power management mechanism is disabled can be compared, and the processor core with the operating frequency higher than the set frequency threshold or the highest operating frequency can be selected, and the tasks to be processed can be assigned to the selected Processor cores. Among them, the working frequency of the processor core is relatively high, indicating that the processing speed of the processor core is relatively fast, and the processor core with the faster processing speed among the processor cores in the disabled state of the power management mechanism executes the tasks to be processed. In the case of ensuring task performance, it is beneficial to further improve the execution efficiency of the task to be processed.

For another example, in an implementation manner, a hash algorithm may be used to allocate tasks to be processed to each processor core whose power management mechanism is in a disabled state.

It is explained here that in the above several implementation manners, the process of allocating tasks to be processed to the processor cores with the power management mechanism in the disabled state is solely based on the utilization, load, or operating frequency of the processor cores. Of course, it is also possible to simultaneously combine any two or three of the utilization, load, and operating frequency of the processor cores to determine which processor core with the power management mechanism disabled to allocate the task to be processed. In addition, in addition to the above three types of information, other indicators or attribute information of the processor core may also be considered. For example, the cache size, bus speed, and/or operating voltage of the processor core may also be considered.

FIG. 3 is a schematic flowchart of another multi-core processor scheduling method provided by an embodiment of the application. As shown in Figure 3, the method includes:

301. Receive a task to be processed.

302. Determine whether the task to be processed belongs to the first type of task; if the result of the judgment is yes, it means that the task to be processed belongs to the first type of task, then execute step 303; if the result of the judgment is no, it means that the task to be processed belongs to the second type of task Task, go to step 304.

303. In the case that the task to be processed belongs to the first type of task, the task to be processed is allocated to the processor core of the multi-core processor whose power management mechanism is in the disabled state, and the processor core of the power management mechanism is in the disabled state. Perform pending tasks.

304. In the case that the task to be processed belongs to the second type of task, the task to be processed is allocated to the processor core of the multi-core processor whose power management mechanism is enabled, and the processor core of the power management mechanism is enabled. Perform pending tasks.

In this embodiment, the application scenario of the multi-core processor may be combined, and each task may be pre-classified into the first type of task and the second type of task according to the performance requirements of each task in the application scenario. Among them, the second type of tasks refer to tasks other than the first type of tasks. For the description of the first type of task, please refer to the above description, which will not be repeated here.

Further optionally, the mapping relationship between the identification information of the task and the task type can be maintained. Optionally, the mapping relationship includes the identification information of each task under the first type of task, or includes the identification information of each task under the second type of task. The identification information, or the identification information of each task under the first type of task and the identification information of each task under the second type of task at the same time.

Based on this, after receiving the task to be processed, the identification information of the task to be processed can be matched in the mapping relationship between the identification information of the task to be maintained and the task type. According to the matching result, it is obtained that the task to be processed belongs to the first category. Tasks or judgment results belonging to the second category of tasks.

If it is determined that the task to be processed belongs to the first type of task, the task to be processed can be allocated to the processor cores with the power management mechanism in the disabled state, and the processor cores with the power management mechanism in the disabled state are responsible for executing the tasks to be processed task. With the advantage that these processor cores will not enter the idle state, the tasks to be processed can be processed in time, which is beneficial to ensure the performance of the tasks to be processed.

If it is determined that the task to be processed belongs to the second type of task and not the first type of task, the task to be processed can be allocated to the processor cores with the power management mechanism in the enabled state. The processor core is responsible for executing pending tasks. With the help of the power consumption management mechanism on these processor cores, while completing the tasks to be processed, it is beneficial to save the power consumption of the processor cores.

In the foregoing or following embodiments of the present application, the allocation method for allocating the tasks to be processed to the processor cores with the power management mechanism in the enabled state is not limited either. The specific allocation method of allocating to-be-processed tasks to the processor cores with the power management mechanism in the enabled state is similar to the allocation method of allocating to-be-processed tasks to the processor cores with the power management mechanism in the disabled state, see The foregoing implementation manners will not be repeated here.

In some optional embodiments of the present application, the multi-core processor includes multiple processor cores. Among the multiple processor cores, the power management mechanism on some of the processor cores is disabled, and the power management mechanism on the other part of the processor cores is disabled. The power management mechanism is in an enabled state, thus forming a heterogeneous multi-core processor. In these embodiments, the number of processor cores with the power management mechanism in the disabled state can be dynamically changed according to application requirements; accordingly, the number of processor cores with the power management mechanism in the enabled state will also dynamically change according to the application requirements. Based on this, the method of this embodiment further includes: dynamically adjusting the states of the power management mechanisms on the multiple processor cores according to application requirements, so that the processor cores with different power management mechanisms in different states can meet the application requirements.

In the embodiments of the present application, the implementation manner of dynamically adjusting the states of the power consumption management mechanisms on multiple processor cores according to application requirements is not limited. The following example illustrates:

For example, in Embodiment A, the overall processing capacity of the processor cores with the power management mechanism in the disabled state can be monitored, and the overall processing capabilities of the processor cores with the power management mechanism in the disabled state cannot meet the application requirements. When the overall processing capacity of the processor cores in the disabled state of the mechanism is insufficient, select the processor cores to be disabled from the processor cores with the power management mechanism in the enabled state, and set the power management mechanism on the processor cores to be disabled Disabled. Among them, the number of processor cores to be disabled may be one or more. This can increase the number of processor cores with the power management mechanism in the disabled state, and increase the overall processing capacity of the processor cores with the power management mechanism in the disabled state, so as to meet application requirements.

In this embodiment, the method for selecting the processor core to be disabled is not limited, and the following methods can be used but not limited to:

Method A1: In method A1, one or more processor cores can be randomly selected as the processor cores to be disabled from among the processor cores in which the power consumption management mechanism is in the enabled state.

Manner A2: In Manner A2, all processor cores among the processor cores whose power consumption management mechanism is in the enabled state may be used as processor cores to be disabled.

Method A3: In method A3, one or more processor cores can be selected as the to-be-disabled processor cores from the processor cores in the enabled state of the power consumption management mechanism according to the amount of tasks corresponding to the application requirements.

For another example, in Embodiment B, the overall processing capacity of the processor core with the power management mechanism in the disabled state can be monitored, and the overall processing capacity of the processor core with the power management mechanism in the disabled state meets the application requirements and is in excess. Next, select the processor core to be enabled from the processor cores with the power management mechanism in the disabled state, and re-enable the power management mechanism on the processor core to be enabled. The number of processor cores to be activated can be one or more.

In this embodiment, the method for selecting the processor core to be activated is not limited, and the following methods can be adopted but not limited to:

Manner B1: In Manner B1, one or more processor cores can be randomly selected as the processor cores to be enabled from the processor cores in which the power management mechanism is in a disabled state.

Method B2: In method B2, one or more processor cores can be selected as the to-be-enabled processor cores from the processor cores whose power consumption management mechanism is in the disabled state according to the amount of tasks corresponding to the application requirements.

For detailed descriptions of the modes A1-A4 and B1-B3, please refer to the foregoing embodiment, which will not be repeated here.

It is explained here that in the foregoing implementations A and B, it is necessary to monitor the overall processing capabilities of the processor cores whose power management mechanism is in a disabled state. Among them, various indicators or attribute information of each processor core with the power management mechanism in the disabled state can be used to characterize the overall processing capability of the processor core with the power management mechanism in the disabled state.

Optionally, the utilization rate of each processor core whose power management mechanism is disabled can be monitored; according to the utilization rate of each processor core whose power management mechanism is disabled, determine the processor whose power management mechanism is disabled Whether the overall processing capacity of the core meets the application requirements.

Optionally, the load of each processor core with the power management mechanism in the disabled state can be monitored; according to the load of each processor core with the power management mechanism in the disabled state, determine the processor with the power management mechanism in the disabled state Whether the overall processing capacity of the core meets the application requirements.

In the method embodiment of the present application, a multi-core processor is used, and the multi-core processor includes multiple processor cores, and the power management mechanism on at least one processor core is in a disabled state; wherein the processor core supports the power management mechanism, Conducive to saving the power consumption of multi-core processors; and disabling the power management mechanism on some processor cores can perform some tasks sensitive to the power management mechanism on these processor cores, which is helpful to ensure the performance requirements of these tasks .

It should be noted that the execution subject of each step of the method provided in the foregoing embodiment may be the same device, or different devices may also be the execution subject of the method. For example, the execution subject of step 201 to step 202 may be device A; for another example, the execution subject of step 201 may be device A, and the execution subject of step 202 may be device B; and so on.

In addition, in some of the processes described in the above embodiments and drawings, multiple operations appearing in a specific order are included, but it should be clearly understood that these operations may be performed out of the order in which they appear in this document or performed in parallel. The sequence numbers of operations, such as 201, 202, etc., are only used to distinguish different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed sequentially or in parallel. It should be noted that the descriptions of "first" and "second" in this article are used to distinguish different messages, devices, modules, etc., and do not represent a sequence, nor do they limit the "first" and "second" Are different types.

Fig. 4 is a schematic structural diagram of a computer device provided by an exemplary embodiment of this application. As shown in FIG. 4, the computer device includes: a multi-core processor 41, and the multi-core processor 41 includes a plurality of processor cores 401, wherein the power management mechanism on at least one of the processor cores 401 is disabled.

This embodiment does not limit the number of processor cores 401 whose power management mechanism is in a disabled state, and it may be one or more. In an optional embodiment, at the same time, the power consumption management mechanisms on 2N (ie, an even number) of processor cores 401 are in a disabled state; N is a positive integer. Of course, at the same moment, the number of processor cores 401 whose power management mechanism is in the disabled state may also be an odd number, for example, 1, 3, 5, etc., which is not limited.

Further, as shown in FIG. 4, the computer device further includes: a memory 42 for storing computer programs, and can be configured to store various other data to support operations on the computer device. Examples of such data include instructions for any application or method operated on a computer device, contact data, phone book data, messages, pictures, videos, etc.

The computer program stored in the memory 42 includes a program corresponding to the power consumption management mechanism, and also includes: a program related to task scheduling and a program related to the state adjustment of the power consumption management mechanism. The program related to task scheduling is equivalent to the scheduler in the foregoing embodiment, and may be simply referred to as the scheduler. The program related to the state adjustment of the power consumption management mechanism is equivalent to the manager in the foregoing embodiment, and may be simply referred to as the management program. The scheduler can be an operating system level program or an application level program. Correspondingly, the management program can be an operating system level program or an application level program.

The memory 42 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable and Programmable read only memory (EPROM), programmable read only memory (PROM), read only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

The multi-core processor 41 is coupled with the memory 42 and is used to execute the computer program (mainly referring to the scheduler) in the memory 42 for: receiving the task to be processed; in the case that the task to be processed belongs to the first type of task, the The tasks to be processed are allocated to the processor cores whose power management mechanism is disabled. It should be noted that the actual execution of the scheduler may be one or several processor cores 401 in the multi-core processor 41.

Among them, the first type of tasks can be tasks that have certain requirements on performance and are more sensitive to power management mechanisms. For example, from the perspective of performance requirements, the first type of tasks can include, but are not limited to: tasks that require high processing delay (for example, require a delay less than the set delay threshold), and have high real-time requirements ( For example, tasks that require response time not to exceed the set response time threshold), and so on. For example, some control tasks may have higher real-time requirements. For another example, some interrupt tasks (such as network interrupt processing tasks) have higher requirements for time delay. In addition, real-time scheduling tasks, instant analysis tasks, and instant query tasks can all be used as examples of the first type of tasks. It should be noted that this embodiment does not limit the first type of tasks, and allows flexible setting according to application scenarios.

In an optional embodiment, when the multi-core processor 41 allocates tasks to be processed to the processor cores whose power management mechanism is in the disabled state, it is specifically used to: each processor core whose power management mechanism is in the disabled state The utilization rate of 401 is compared, the utilization rate is lower than the set utilization threshold value or the processor core 401 with the lowest utilization rate is selected from among them, and the task to be processed is allocated to the selected processor core 401.

In another optional embodiment, when the multi-core processor 41 allocates tasks to be processed to the processor cores whose power management mechanism is disabled, it is specifically used to: each processor whose power management mechanism is disabled The load of the cores 401 is compared, and the load is lower than the set load threshold or the processor core 401 with the lowest load is selected, and the task to be processed is allocated to the selected processor core 401.

In yet another optional embodiment, when the multi-core processor 41 allocates tasks to be processed to the processor cores whose power management mechanism is disabled, it is specifically used to: each processor whose power management mechanism is disabled The operating frequencies of the cores 401 are compared, and the processor core 401 whose operating frequency is higher than the set frequency threshold or the highest operating frequency is selected, and the tasks to be processed are allocated to the selected processor core 401.

In another alternative embodiment, when the multi-core processor 41 allocates the task to be processed to the processor core whose power management mechanism is disabled, it is specifically used to: use a hash algorithm to allocate the task to be processed to a certain processor core. The power consumption management mechanism is on each processor core 401 in a disabled state.

In an optional embodiment, the multi-core processor 41 is further configured to: if the task to be processed belongs to the second type of task, allocate the task to be processed to the processor cores whose power management mechanism is in the enabled state. Among them, the second type of tasks refer to tasks other than the first type of tasks.

In some alternative embodiments, among the multiple processor cores 401, the power management mechanism on some of the processor cores 401 is disabled, and the power management mechanism on the other part of the processor cores 401 is enabled, so Form a heterogeneous multi-core processor. In these embodiments, the number of processor cores 401 with the power management mechanism in the disabled state and the number of processor cores 401 with the power management mechanism in the enabled state are fixed.

In other alternative embodiments, among the multiple processor cores 401, the power management mechanism on some of the processor cores 401 is disabled, and the power management mechanism on the other part of the processor cores 401 is enabled. Thus forming a heterogeneous multi-core processor. In these embodiments, the number of processor cores 401 with the power management mechanism in the disabled state can be dynamically changed according to application requirements; accordingly, the number of processor cores 401 with the power management mechanism in the enabled state will also be dynamically changed according to the application requirements. Variety.

Based on the foregoing, the multi-core processor 41 is also used to execute a computer program (mainly refers to a management program) in the memory 42 to dynamically adjust the state of the power consumption management mechanism on the multiple processor cores 401 according to application requirements. It should be noted that the actual execution of the hypervisor may be one or several processor cores 401 in the multi-core processor 41.

Further, when the multi-core processor 41 dynamically adjusts the state of the power management mechanism on the multiple processor cores 401, it is specifically used for: when the overall processing capacity of the processor core whose power management mechanism is disabled cannot meet application requirements In this case, the processor core to be disabled is selected from the processor cores in which the power consumption management mechanism is in the enabled state, and the power consumption management mechanism on the processor core to be disabled is disabled.

Further, when the multi-core processor 41 dynamically adjusts the state of the power management mechanism on the multiple processor cores 401, it is specifically used to: when the power management mechanism is disabled, the overall processing capacity of the processor core meets application requirements and is in excess In the case of, select the processor core to be enabled from the processor cores whose power management mechanism is in a disabled state, and re-enable the power consumption management mechanism on the processor core to be enabled.

Further, the multi-core processor 41 is also used to: monitor the utilization and/or load of each processor core in the disabled state of the power management mechanism; according to the utilization and/or the utilization of each processor core in the disabled state of the power management mechanism Load, to determine whether the overall processing capacity of the processor core with the power management mechanism in the disabled state meets the application requirements.

Optionally, when the multi-core processor 41 selects the processor cores to be disabled, it is specifically used to: randomly select one or more processor cores as the processor cores to be disabled from the processor cores whose power management mechanism is in the enabled state ; Or, use all the processor cores in the processor cores with the power management mechanism in the enabled state as the processor cores to be disabled; or, according to the task volume corresponding to the application requirements, from the processor cores with the power management mechanism in the enabled state Select one or more processor cores as the processor cores to be disabled; or, according to the processing capabilities of the processor cores, select one or more processor cores from the processor cores in which the power management mechanism is enabled. The processor core is to be disabled.

Optionally, when the multi-core processor 41 selects the processor cores to be enabled, it is specifically used to: randomly select one or more processor cores as the processor cores to be enabled from the processor cores whose power management mechanism is in a disabled state ; Or, according to the task volume corresponding to the application requirements, select one or more processor cores from the processor cores in the disabled state of the power management mechanism as the processor cores to be enabled; or, according to the processing capabilities of the processor cores, From the processor cores in which the power management mechanism is in the disabled state, one or more processor cores are selected as the processor cores to be enabled.

For a detailed description of each operation in this embodiment, please refer to the description in the foregoing multi-core processor embodiment and method embodiment, which will not be repeated here.

Further, as shown in FIG. 4, the computer device further includes: a communication component 43, a display 44, a power supply component 45, an audio component 46 and other components. Only some of the components are schematically shown in FIG. 4, which does not mean that the computer device only includes the components shown in FIG. 4. In addition, the components in the dashed box in FIG. 4 are optional components, not mandatory components, and the specifics may depend on the product form of the computer equipment. The computer device in this embodiment can be implemented as a terminal device such as a desktop computer, a notebook computer, a smart phone, or an IOT device, or a server device such as a conventional server, a cloud server, or a server array, and can also be implemented as a network interface card or a network router , Gateways and other network equipment. If the computer device of this embodiment is implemented as a terminal device such as a desktop computer, a notebook computer, a smart phone, etc., it may include the components in the dashed box in FIG. 4; if the computer device of this embodiment is implemented as a conventional server, a cloud server, or a server array, etc. The server device, or implemented as a network device such as a network interface card, a network router, or a gateway, may not include the components in the dashed box in FIG. 4.

The computer device provided in this embodiment adopts a multi-core processor. The multi-core processor includes multiple processor cores, and the power consumption management mechanism on at least one processor core is disabled. The processor cores in the multi-core processor support functions. The power consumption management mechanism is conducive to saving the power consumption of multi-core processors; and by disabling the power management mechanism on some processor cores, some tasks that are sensitive to the power management mechanism can be performed on these processor cores, which is conducive to ensuring The performance requirements of these tasks. It can be seen that the computer device provided in this embodiment can reduce performance loss as much as possible while reducing overall power consumption, and ensure task execution efficiency.

Correspondingly, an embodiment of the present application also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor causes the processor to implement the steps in the foregoing method embodiments. It should be noted that the computer program in this embodiment may be a system-level program, an application-level program, or both a system-level program and an application-level program.

For example, the computer program in this embodiment includes a program corresponding to the power consumption management mechanism, and also includes: a program related to task scheduling and a program related to the state adjustment of the power consumption management mechanism. The program related to task scheduling is equivalent to the scheduler in the foregoing embodiment, and may be simply referred to as the scheduler. The program related to the state adjustment of the power consumption management mechanism is equivalent to the manager in the foregoing embodiment, and may be simply referred to as the management program. The scheduler can be an operating system level program or an application level program. Correspondingly, the management program can be an operating system level program or an application level program.

The above-mentioned communication component in FIG. 4 is configured to facilitate wired or wireless communication between the device where the communication component is located and other devices. The device where the communication component is located can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination of them. In an exemplary embodiment, the communication component receives a broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component may further include a near field communication (NFC) module, radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology Wait.

The above-mentioned display in FIG. 4 includes a screen, and the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, sliding, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure related to the touch or slide operation.

The power supply components in Figure 4 above provide power for various components of the equipment where the power supply components are located. The power supply component may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the device where the power supply component is located.

The audio component in FIG. 4 may be configured to output and/or input audio signals. For example, the audio component includes a microphone (MIC). When the device where the audio component is located is in an operating mode, such as call mode, recording mode, and voice recognition mode, the microphone is configured to receive external audio signals. The received audio signal can be further stored in a memory or sent via a communication component. In some embodiments, the audio component further includes a speaker for outputting audio signals.

Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

The present invention is described with reference to flowcharts and/or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and/or block in the flowchart and/or block diagram, and the combination of processes and/or blocks in the flowchart and/or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing equipment to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing equipment are generated It is a device that realizes the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.

These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing equipment to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction device. The device implements the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.

These computer program instructions can also be loaded on a computer or other programmable data processing equipment, so that a series of operation steps are executed on the computer or other programmable equipment to produce computer-implemented processing, so as to execute on the computer or other programmable equipment. The instructions provide steps for implementing the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.

In a typical configuration, the computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include non-permanent memory in a computer readable medium, random access memory (RAM) and/or non-volatile memory, such as read-only memory (ROM) or flash memory (flash RAM). Memory is an example of computer readable media.

Computer-readable media include permanent and non-permanent, removable and non-removable media, and information storage can be realized by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disc (DVD) or other optical storage, Magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media can be used to store information that can be accessed by computing devices. According to the definition in this article, computer-readable media does not include transitory media, such as modulated data signals and carrier waves.

It should also be noted that the terms "include", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or equipment including a series of elements not only includes those elements, but also includes Other elements that are not explicitly listed, or they also include elements inherent to such processes, methods, commodities, or equipment. If there are no more restrictions, the element defined by the sentence "including a..." does not exclude the existence of other identical elements in the process, method, commodity, or equipment that includes the element.

The foregoing descriptions are only examples of the present application, and are not used to limit the present application. For those skilled in the art, this application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included in the scope of the claims of this application.

Claims

A multi-core processor is characterized by comprising: a plurality of processor cores; wherein the power consumption management mechanism on at least one of the processor cores is in a disabled state.
The multi-core processor according to claim 1, wherein the power consumption management mechanism on the 2N processor cores is in a disabled state; N is a positive integer.
The multi-core processor according to claim 1, wherein a scheduler runs on the multiple processor cores;

The scheduler is configured to receive the to-be-processed task, and when the to-be-processed task belongs to the first type of task, allocate the to-be-processed task to the processor core whose power consumption management mechanism is in a disabled state.
The multi-core processor according to claim 3, wherein the scheduler is further configured to:

In the case that the task to be processed belongs to the second type of task, the task to be processed is allocated to the processor cores whose power consumption management mechanism is in an enabled state.
The multi-core processor according to claim 1, wherein a manager runs on the plurality of processor cores;

The manager is configured to dynamically adjust the state of the power consumption management mechanism on the multiple processor cores according to application requirements.
The multi-core processor according to claim 5, wherein the manager is specifically configured to:

When the overall processing capacity of the processor core with the power management mechanism in the disabled state cannot meet the application requirements, select the processor core to be disabled from the processor cores with the power management mechanism in the enabled state, and set the processor core to be disabled. The power management mechanism on the processor core is disabled.
The multi-core processor according to claim 6, wherein when the manager selects the processor to be disabled, it is specifically configured to:

Randomly select one or more processor cores as the processor cores to be disabled from the processor cores whose power management mechanism is in the enabled state; or

Use all the processor cores in the processor cores with the power management mechanism in the enabled state as the processor cores to be disabled; or

According to the task volume corresponding to the application requirements, select one or more processor cores as the to-be-disabled processor cores from the processor cores whose power management mechanism is in the enabled state; or

According to the processing capabilities of the processor cores, one or more processor cores are selected as the processor cores to be disabled from the processor cores in which the power management mechanism is in the enabled state.
The multi-core processor according to claim 7, wherein the plurality of processor cores comprise a first type of processor core and a second type of processor core; the processing capability of the first type of processor core is stronger than The processing capability of the second type of processor core.
The multi-core processor according to claim 7, wherein the manager is specifically configured to: when selecting the processor core to be disabled according to the processing capability of the processor core:

If there is a second type of processor core with a power management mechanism in an enabled state, select the to-be-disabled processor core from the second type of processor core with a power management mechanism in the enabled state;

If there is no second-type processor core with the power management mechanism in the enabled state, select the to-be-disabled processor core from the first-type processor cores with the power management mechanism in the enabled state.
The multi-core processor according to claim 7, wherein the manager is specifically configured to: when selecting the processor to be disabled according to the processing capability of the processor core:

In the case that the task amount corresponding to the application requirement is greater than or equal to the set task amount threshold, select the processor core to be disabled from the first type of processor cores whose power management mechanism is in an enabled state;

In the case that the task amount corresponding to the application requirement is less than the set task amount threshold, the processor core to be disabled is selected from the second type of processor cores in which the power consumption management mechanism is in the enabled state.
The multi-core processor according to claim 5, wherein the manager is further configured to:

Monitor the utilization and/or load of each processor core whose power management mechanism is disabled;

According to the utilization rate and/or load of each processor core with the power management mechanism in the disabled state, it is determined whether the overall processing capability of the processor core with the power management mechanism in the disabled state meets the application requirements.
The multi-core processor according to claim 5, wherein the manager is further configured to:

When the overall processing capacity of the processor core with the power management mechanism in the disabled state meets the application requirements and is surplus, select the processor core to be enabled from the processor cores with the power management mechanism in the disabled state, and re-enable the The power management mechanism on the processor core is to be enabled.
The multi-core processor according to claim 10, wherein the multi-core processor is an ARM processor or an X86 processor.
A scheduling method for a multi-core processor, which is characterized in that it comprises:

Receive pending tasks;

In the case that the task to be processed belongs to the first type of task, allocating the task to be processed to the processor core of the multi-core processor whose power consumption management mechanism is in a disabled state;

Wherein, the multi-core processor includes a plurality of processor cores, wherein a power consumption management mechanism on at least one processor core is in a disabled state.
The method according to claim 14, further comprising:

In the case that the task to be processed belongs to the second type of task, the task to be processed is allocated to the processor core of the multi-core processor whose power consumption management mechanism is in the enabled state.
The method according to claim 14, further comprising:

When the overall processing capacity of the processor core with the power management mechanism in the disabled state cannot meet the application requirements, select the processor core to be disabled from the processor cores with the power management mechanism in the enabled state, and set the processor core to be disabled. The power management mechanism on the processor core is disabled.
The method according to claim 16, further comprising:

Monitor the utilization and/or load of each processor core whose power management mechanism is disabled;

According to the utilization rate and/or load of each processor core with the power management mechanism in the disabled state, it is determined whether the overall processing capability of the processor core with the power management mechanism in the disabled state meets application requirements.
The method according to claim 16, further comprising:

When the overall processing capacity of the processor core with the power management mechanism in the disabled state meets the application requirements and is surplus, select the processor core to be enabled from the processor cores with the power management mechanism in the disabled state, and re-enable the The power management mechanism on the processor core is to be enabled.
A computer device is characterized by comprising: a multi-core processor: the multi-core processor includes a plurality of processor cores, wherein the power consumption management mechanism on at least one of the processor cores is disabled.
The computer device according to claim 19, further comprising:

Memory, used to store computer programs;

The multi-core processor is coupled with the memory, and is configured to execute the computer program for:

Receiving the task to be processed; in the case that the task to be processed belongs to the first type of task, the task to be processed is allocated to the processor core whose power consumption management mechanism is in a disabled state.
The computer device according to claim 20, wherein the multi-core processor is further configured to:

In the case that the task to be processed belongs to the second type of task, the task to be processed is allocated to the processor cores whose power consumption management mechanism is in an enabled state.
22. The computer device of claim 20, wherein the multi-core processor is further configured to dynamically adjust the state of the power consumption management mechanism on the multiple processor cores according to application requirements.
The computer device according to claim 22, wherein the multi-core processor is specifically configured to:

When the overall processing capacity of the processor core with the power management mechanism in the disabled state cannot meet the application requirements, select the processor core to be disabled from the processor cores with the power management mechanism in the enabled state, and set the processor core to be disabled. The power management mechanism on the processor core is disabled.
The computer device according to claim 22, wherein the multi-core processor is specifically configured to:

When the overall processing capacity of the processor core with the power management mechanism in the disabled state meets the application requirements and is surplus, select the processor core to be enabled from the processor cores with the power management mechanism in the disabled state, and re-enable the The power management mechanism on the processor core is to be enabled.
The computer device according to claim 23 or 24, wherein the multi-core processor is further configured to:

Monitor the utilization and/or load of each processor core whose power management mechanism is disabled;

According to the utilization rate and/or load of each processor core with the power management mechanism in the disabled state, it is determined whether the overall processing capability of the processor core with the power management mechanism in the disabled state meets application requirements.
A computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the processor is caused to implement the steps in the method of any one of claims 14-18.
The storage medium according to claim 26, wherein the computer program is a system-level program; or, the computer program is an application-level program; or, the computer program includes a system-level program and an application-level program.