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WO2020224196A1 - 像素驱动电路以及显示面板 - Google Patents

像素驱动电路以及显示面板 Download PDF

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Publication number
WO2020224196A1
WO2020224196A1 PCT/CN2019/112960 CN2019112960W WO2020224196A1 WO 2020224196 A1 WO2020224196 A1 WO 2020224196A1 CN 2019112960 W CN2019112960 W CN 2019112960W WO 2020224196 A1 WO2020224196 A1 WO 2020224196A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
module
control signal
reset
potential
Prior art date
Application number
PCT/CN2019/112960
Other languages
English (en)
French (fr)
Inventor
蔡振飞
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2020224196A1 publication Critical patent/WO2020224196A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

Definitions

  • This application relates to the field of display technology, specifically a pixel drive circuit and a display panel.
  • transistors in the pixel driving circuit are low-temperature polysilicon thin film transistors or oxide thin film transistors.
  • the pixel driving circuit is compensated.
  • the existing pixel compensation circuit has a shortcoming.
  • the driving current is related to the power signal, and the voltage drop of the power signal will affect the driving current, resulting in unstable light emission of the light-emitting device, and thus affecting the image quality.
  • the main technical problem to be solved by this application is how to compensate the threshold voltage change of the driving transistor, improve the light emission uniformity of the light emitting device, and thereby improve the image quality.
  • the present application provides a pixel driving circuit, including: a reset module, a compensation module, a data writing module, and a light emitting module; the reset module, the data writing module, and the light emitting module are all compatible with the Compensation module connection;
  • the reset module accesses a first control signal, and the reset module is configured to transmit a reset signal to the light-emitting module under the control of the first control signal to reset the light-emitting module for the first time;
  • the data writing module is connected to the first control signal, and the data writing module is used to perform a second time on the light emitting module through the reference potential of the data signal under the control of the first control signal Reset
  • the compensation module is connected to a second control signal, and the compensation module is configured to obtain a threshold voltage under the control of the second control signal;
  • the data writing module is also used to transmit the display potential of the data signal to the compensation module under the control of the first control signal;
  • the first control signal and the second control signal are both provided by an external timing device, and the current flowing through the light emitting device is independent of the threshold voltage of the fourth transistor.
  • the reset module includes: a first transistor
  • the gate of the first transistor is electrically connected to the first control signal
  • the drain of the first transistor is electrically connected to the reset signal
  • the source of the first transistor is electrically connected to the first control signal. node.
  • the compensation module includes: a second transistor and a storage capacitor;
  • the gate of the second transistor is electrically connected to the second control signal
  • the drain of the second transistor is electrically connected to the first node
  • the source of the third transistor is electrically connected to the first node.
  • the first end of the storage capacitor is electrically connected to the data writing module, and the second end of the storage capacitor is electrically connected to the second node.
  • the data writing module includes: a third transistor
  • the gate of the third transistor is electrically connected to the first control signal, the drain of the third transistor is electrically connected to the data signal, and the source of the third transistor is electrically connected to the The first end of the storage capacitor.
  • the light-emitting module includes: a light-emitting device and a fourth transistor;
  • the anode of the light emitting device is electrically connected to a first power signal, and the cathode of the light emitting device is electrically connected to the first node;
  • the gate of the fourth transistor is electrically connected to the second node, the drain of the fourth transistor is electrically connected to the first node, and the source of the fourth transistor is electrically connected to the second node. Power signal.
  • the first transistor, the second transistor, the third transistor, and the fourth transistor are all NMOS transistors.
  • the driving timing of the pixel driving circuit includes:
  • the threshold voltage of the fourth transistor is captured and stored on the storage capacitor
  • the data signal is written to the first end of the storage capacitor, and according to the coupling effect of the storage capacitor, the potential of the second end of the storage capacitor jumps to a corresponding potential;
  • the pixel driving circuit In the light-emitting stage, the pixel driving circuit generates a driving current and supplies it to the light-emitting device for driving the light-emitting display of the light-emitting device.
  • the first control signal in the reset phase, is at a high potential, the second control signal is at a low potential, and the reset signal is transmitted to all through the second transistor.
  • the data signal is transmitted to the first end of the storage capacitor through the first transistor, and the potential of the second node jumps to the one corresponding to the data signal according to the coupling effect of the storage capacitor Potential
  • the first control signal is at a low potential
  • the second control signal is at a high potential
  • the first power signal charges the storage capacitor through the third transistor until the first When the voltage difference between the gate and the source of the four transistors is equal to the threshold voltage of the fourth transistor, it is turned off;
  • the first control signal is at a high potential
  • the second control signal is at a low potential
  • the data signal is transmitted to the first end of the storage capacitor through the first transistor, and the first The potential of a node jumps to a corresponding potential according to the coupling effect of the storage capacitor;
  • the first control signal is at a low potential
  • the second control signal is at a low potential
  • the power signal is transmitted to the cathode of the light emitting device through the anode of the light emitting device, and the light emitting device emits light.
  • the present application provides a pixel driving circuit, including: a reset module, a compensation module, a data writing module, and a light emitting module; the reset module, the data writing module, and the light emitting module are all compatible with the Compensation module connection;
  • the reset module accesses a first control signal, and the reset module is configured to transmit a reset signal to the light-emitting module under the control of the first control signal to reset the light-emitting module for the first time;
  • the data writing module is connected to the first control signal, and the data writing module is used to perform a second time on the light emitting module through the reference potential of the data signal under the control of the first control signal Reset
  • the compensation module is connected to a second control signal, and the compensation module is configured to obtain a threshold voltage under the control of the second control signal;
  • the data writing module is also used to transmit the display potential of the data signal to the compensation module under the control of the first control signal.
  • the reset module includes: a first transistor
  • the gate of the first transistor is electrically connected to the first control signal
  • the drain of the first transistor is electrically connected to the reset signal
  • the source of the first transistor is electrically connected to the first control signal. node.
  • the compensation module includes: a second transistor and a storage capacitor;
  • the gate of the second transistor is electrically connected to the second control signal
  • the drain of the second transistor is electrically connected to the first node
  • the source of the third transistor is electrically connected to the first node.
  • the first end of the storage capacitor is electrically connected to the data writing module, and the second end of the storage capacitor is electrically connected to the second node.
  • the data writing module includes: a third transistor
  • the gate of the third transistor is electrically connected to the first control signal, the drain of the third transistor is electrically connected to the data signal, and the source of the third transistor is electrically connected to the The first end of the storage capacitor.
  • the light-emitting module includes: a light-emitting device and a fourth transistor;
  • the anode of the light emitting device is electrically connected to a first power signal, and the cathode of the light emitting device is electrically connected to the first node;
  • the gate of the fourth transistor is electrically connected to the second node, the drain of the fourth transistor is electrically connected to the first node, and the source of the fourth transistor is electrically connected to the second node. Power signal.
  • the first transistor, the second transistor, the third transistor, and the fourth transistor are all NMOS transistors.
  • the driving timing of the pixel driving circuit includes:
  • the threshold voltage of the fourth transistor is captured and stored on the storage capacitor
  • the data signal is written to the first end of the storage capacitor, and according to the coupling effect of the storage capacitor, the potential of the second end of the storage capacitor jumps to a corresponding potential;
  • the pixel driving circuit In the light-emitting stage, the pixel driving circuit generates a driving current and supplies it to the light-emitting device for driving the light-emitting display of the light-emitting device.
  • the first control signal in the reset phase, is at a high potential, the second control signal is at a low potential, and the reset signal is transmitted to all through the second transistor.
  • the data signal is transmitted to the first end of the storage capacitor through the first transistor, and the potential of the second node jumps to the one corresponding to the data signal according to the coupling effect of the storage capacitor Potential
  • the first control signal is at a low potential
  • the second control signal is at a high potential
  • the first power signal charges the storage capacitor through the third transistor until the first When the voltage difference between the gate and the source of the four transistors is equal to the threshold voltage of the fourth transistor, it is turned off;
  • the first control signal is at a high potential
  • the second control signal is at a low potential
  • the data signal is transmitted to the first end of the storage capacitor through the first transistor, and the first The potential of a node jumps to a corresponding potential according to the coupling effect of the storage capacitor;
  • the first control signal is at a low potential
  • the second control signal is at a low potential
  • the power signal is transmitted to the cathode of the light emitting device through the anode of the light emitting device, and the light emitting device emits light.
  • the first control signal and the second control signal are both provided by an external timing device.
  • the current flowing through the light-emitting device is independent of the threshold voltage of the fourth transistor.
  • the present application provides a display panel including a pixel driving circuit
  • the pixel driving circuit includes: a reset module, a compensation module, a data writing module, and a light emitting module; the reset module, the data writing module, and the light emitting module are all connected to the compensation module;
  • the reset module accesses a first control signal, and the reset module is configured to transmit a reset signal to the light-emitting module under the control of the first control signal to reset the light-emitting module for the first time;
  • the data writing module is connected to the first control signal, and the data writing module is used to perform a second time on the light emitting module through the reference potential of the data signal under the control of the first control signal Reset
  • the compensation module is connected to a second control signal, and the compensation module is configured to obtain a threshold voltage under the control of the second control signal;
  • the data writing module is also used to transmit the display potential of the data signal to the compensation module under the control of the first control signal.
  • the pixel driving circuit adopts the 4T1C structure to effectively compensate the threshold voltage of the driving transistor in each pixel, and the driving current of the light-emitting device is not affected by the first power signal, therefore, the light emission is improved.
  • the stability of the device's light emission improves the picture quality.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application
  • FIG. 2 is a schematic circuit diagram of a pixel drive circuit provided by an embodiment of the application.
  • FIG. 3 is a timing diagram of driving signals of the pixel driving circuit provided by this application.
  • the transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one of the poles is called the source and the other is called the drain. According to the form in the figure, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the source, and the output end is the drain.
  • the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors. The P-type transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level. The gate is turned on when the gate is high, and it is turned off when the gate is low.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by the present invention.
  • the pixel driving circuit includes a reset module 101, a compensation module 102, a data writing module 103, and a light emitting module 104.
  • the reset module 101, the data writing module 103, and the light emitting module 104 are all connected to the compensation module 102.
  • the reset module 101 accesses the first control signal Y, and the reset module 101 is used to transmit the reset signal R to the light-emitting module 103 under the control of the first control signal Y to reset the light-emitting module 103 for the first time.
  • the data writing module 103 is connected to the first control signal Y, and the data writing module 103 is used to reset the light emitting module 104 for the second time under the control of the first control signal Y and using the reference potential of the data signal D.
  • the compensation module 102 is connected to the second control signal E, and the compensation module 102 is used to write the data signal D under the control of the second control signal E to obtain the threshold voltage.
  • the data writing module 103 is also used to transmit the display potential of the data signal D to the compensation module 102 under the control of the first control signal Y.
  • FIG. 2 is a schematic circuit diagram of the pixel driving circuit provided by the present invention.
  • the reset module 101 includes: a first transistor T1.
  • the gate of the first transistor T1 is electrically connected to the first control signal Y
  • the drain of the first transistor T1 is electrically connected to the reset signal R
  • the source of the first transistor T1 is electrically connected to the first node a.
  • the compensation module 102 includes: a second transistor T2 and a storage capacitor C.
  • the gate of the second transistor T2 is electrically connected to the second control signal E, the drain of the second transistor T2 is electrically connected to the first node a, and the source of the second transistor T2 is electrically connected to the second node b.
  • the first end of the storage capacitor C is electrically connected to the data writing module 103, and the second end of the storage capacitor C is electrically connected to the second node b.
  • the data writing module 103 includes: a third transistor.
  • the gate of the third transistor T3 is electrically connected to the first control signal Y, the drain of the third transistor T3 is electrically connected to the data signal D, and the source of the third transistor T3 is electrically connected to the first end of the storage capacitor C .
  • the light emitting module 104 includes a light emitting device L and a fourth transistor T4.
  • the anode of the light emitting device L is electrically connected to the first power signal Y, and the cathode of the light emitting device L is electrically connected to the first node a.
  • the fourth transistor T4 is a driving transistor.
  • the gate of the fourth transistor T4 is electrically connected to the second node b, the drain of the fourth transistor T4 is electrically connected to the first node a, and the source of the fourth transistor T4 is electrically connected In the second power signal W.
  • the first transistor T1 is used to reset the cathode of the light-emitting device L
  • the second transistor T3 is used to capture the threshold voltage of the fourth transistor T4
  • the third transistor T2 is used to reset the first terminal of the storage capacitor C
  • reset the second node b through the coupling effect of the storage capacitor C that is, reset the gate of the fourth transistor T4 through the coupling effect of the storage capacitor C
  • the fourth transistor T4 is used to generate a driving current and provide it to the light emitting
  • the device L makes the light-emitting device L emit light.
  • the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all N-type transistors.
  • the transistors in the pixel driving circuit provided by the embodiments of the present application are the same type of transistors, so as to avoid the influence of the difference between different types of transistors on the pixel driving circuit.
  • FIG. 3 is a timing diagram of driving signals of the pixel driving circuit provided by the present invention.
  • the driving timing of the pixel driving circuit includes:
  • the potential of the first node a and the potential of the second node b are reset.
  • the threshold voltage Vth of the fourth transistor T4 is captured and stored on the storage capacitor
  • the data signal D is written into the first end of the storage capacitor C, and according to the coupling effect of the storage capacitor C, the potential of the second end of the storage capacitor C jumps to a corresponding potential.
  • the pixel driving circuit In the light emitting stage t4, the pixel driving circuit generates a driving current and supplies it to the light emitting device L for driving the light emitting device L to emit light.
  • both the first control signal Y and the second control signal E are provided by an external timing device.
  • the first control signal Y is at a high potential
  • the second control signal E is at a low potential
  • the first transistor T1 is turned on
  • the second transistor T2 is turned on
  • the reset signal R is transmitted to the first transistor through the first transistor T1.
  • a node a eliminates the signal remaining in the light-emitting device L in the previous stage to reset the light-emitting device L.
  • the data signal D is transmitted to the first end of the storage capacitor C through the second transistor T2. Due to the coupling effect of the storage capacitor C, the storage capacitor The potential of the second terminal of C is raised to a corresponding potential, that is, the potential of the second node b is raised to a corresponding potential, so that the fourth transistor T4 is turned on.
  • the reset module 101 resetting the light-emitting module 104 for the first time means that the first transistor T1 in the reset module 101 resets the first node a to reset the light-emitting device L in the light-emitting module 104.
  • the data writing module 103 resets the light emitting module 104 for the second time through the reference potential of the data signal D. This means that the third transistor T3 in the data writing module 103 resets the second node b through the reference potential of the data signal D. .
  • the potential of the first control signal is 22V
  • the potential of the second control signal is -8V.
  • the first transistor T1 is turned on
  • the second transistor T2 is turned on
  • the reset signal R is transmitted to the first node a through the first transistor T1 to eliminate the signal remaining in the light emitting device L in the previous stage to reset the light emitting device L
  • the data signal D The reference potential of is transmitted to the first end of the storage capacitor C through the second transistor T2, and the reference potential of the data signal D may be 0V.
  • the potential of the second end of the storage capacitor C rises to a corresponding potential, that is, the potential of the second node b rises to a potential that can turn on the fourth transistor T4.
  • the fourth transistor T4 It can be the same type of transistor as the third transistor T3, that is, when the potential of the gate of the fourth transistor T4 is greater than -8V, the fourth transistor is turned on. That is, in some embodiments, the potential of the second node b can be raised to the reference potential of the data signal D 0V, thereby turning on the fourth transistor T4.
  • the first control signal Y is at a low potential
  • the second control signal E is at a high potential
  • the third transistor T3 is turned on
  • the fourth transistor T4 is turned on.
  • the first power signal H passes through the third transistor T3.
  • the storage capacitor is charged until the voltage difference between the gate and source of the fourth transistor T4 is equal to the threshold voltage Vth of the fourth transistor.
  • the source of the fourth transistor T4 is at the potential Vw of the second power signal W, That is, when the fourth transistor T4 is turned off, the potential of the gate of the fourth transistor T4 is equal to Vw+
  • the potential of the first control signal Y is 0V
  • the potential of the second control signal E is 22V
  • the third transistor T3 is turned on
  • the fourth transistor T4 is turned on
  • the first power signal H is connected to the storage capacitor through the third transistor T3. It is charged until the voltage difference between the gate and source of the fourth transistor T4 is equal to the threshold voltage Vth of the fourth transistor.
  • the source of the fourth transistor T4 is at the potential Vw of the second power signal W, that is, the first When the four transistor T4 is turned off, the potential of the gate of the fourth transistor T4 is equal to Vw+
  • the first control signal Y is at a high potential
  • the second control signal E is at a low potential
  • the first transistor T1 is turned on
  • the second transistor T2 is turned on
  • the data signal D is transmitted to the storage through the second transistor T2
  • the potential of the second node b jumps to the corresponding potential according to the coupling effect of the storage capacitor C
  • the potential of the second node b is Vd+Vw+
  • the potential of the first control signal Y is 22V
  • the potential of the second control signal E is -8V
  • the first transistor T1 is turned on
  • the second transistor T2 is turned on
  • the display potential of the data signal D is transmitted to the second transistor T2.
  • the display potential of the data signal D may be 8V
  • the potential of the second node b jumps to the display potential of the data signal D to 8V according to the coupling effect of the storage capacitor C.
  • the first control signal Y is at a low potential
  • the second control signal E is at a low potential
  • the fourth transistor T4 is turned on. Due to the coupling effect of the storage capacitor C, the potential of the second node b is Vd+Vw+
  • the driving current Id corresponding to the gate-source voltage of the fourth transistor T4 is supplied to the light emitting device D, causing the light emitting device D to emit light, and the driving current Id generated by the fourth transistor T4 is expressed by the following equation:
  • ]2 k(Vd)2.
  • Id represents the current flowing through the light emitting device D
  • Vgs represents the gate-source voltage of the fourth transistor T4
  • Vth represents the threshold voltage of the fourth transistor T4
  • Vd represents the potential of the data signal Z
  • k represents a constant.
  • the pixel driving circuit of the 4T1C structure effectively compensates the threshold voltage of the driving transistor in each pixel, and the driving current of the light-emitting device is not affected by the first power signal, so , Improve the stability of the light-emitting device, and then improve the image quality.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

一种像素驱动电路和显示面板，像素驱动电路包括复位模块（101）、补偿模块（102）、数据写入模块（103）和发光模块（104）；复位模块（101）、数据写入模块（103）以及发光模块（104）均与补偿模块（102）连接。能够对像素中驱动晶体管（T4）的阈值电压进行有效补偿，提高了发光的稳定性，进而提高画质。

Description

像素驱动电路以及显示面板 技术领域
本申请涉及显示技术领域，具体一种像素驱动电路以及显示面板。
 背景技术
现有技术中，像素驱动电路中的晶体管大多采用低温多晶硅薄膜晶体管或氧化物薄膜晶体管。
由于晶化工艺的局限性，在大面积玻璃基板上制作的低温多晶硅薄膜晶体管，常常在诸如阈值电压、迁移率等电学参数上具有非均匀性。因此，会对像素驱动电路进行补偿。然而现有的像素补偿电路存在一个不足，驱动电流与电源信号相关，电源信号的压降会影响驱动电流，导致发光器件的发光不稳定，进而影响画质。
 技术问题
本申请主要解决的技术问题，如何能够补偿驱动晶体管的阈值电压变化，提高发光器件的发光均匀性，进而提升画质。
 技术解决方案
第一方面，本申请提供了一种像素驱动电路，包括：复位模块、补偿模块、数据写入模块和发光模块；所述复位模块、所述数据写入模块以及所述发光模块均与所述补偿模块连接；
所述复位模块接入第一控制信号，所述复位模块用于在所述第一控制信号的控制下将复位信号传输至所述发光模块以对所述发光模块进行第一次复位；
所述数据写入模块接入所述第一控制信号，所述数据写入模块用于在所述第一控制信号的控制下，并通过数据信号的参考电位对所述发光模块进行第二次复位；
所述补偿模块接入第二控制信号，所述补偿模块用于在所述第二控制信号的控制下获取阈值电压；
所述数据写入模块还用于在所述第一控制信号的控制下将数据信号的显示电位传输至所述补偿模块；
其中，所述第一控制信号以及所述第二控制信号均由外部时序器提供，流经所述发光器件的电流与所述第四晶体管的阈值电压无关。
在本申请所提供的像素驱动电路中，所述复位模块包括：第一晶体管；
所述第一晶体管的栅极电性连接于所述第一控制信号，所述第一晶体管的漏极电性连接于所述复位信号，所述第一晶体管的源极电性连接于第一节点。
在本申请所提供的像素驱动电路中，所述补偿模块包括：第二晶体管以及存储电容；
所述第二晶体管的栅极电性连接于所述第二控制信号，所述第二晶体管的漏极电性连接于所述第一节点，所述第三晶体管的源极电性连接于第二节点；
所述存储电容的第一端电性连接于数据写入模块，所述存储电容的第二端电性连接于所述第二节点。
在本申请所提供的像素驱动电路中，所述数据写入模块包括：第三晶体管；
所述第三晶体管的栅极电性连接于所述第一控制信号，所述第三晶体管的漏极电性连接于所述数据信号，所述第三晶体管的源极电性连接于所述存储电容的第一端。
在本申请所提供的像素驱动电路中，所述发光模块包括：发光器件以及第四晶体管；
所述发光器件的阳极电性连接于第一电源信号，所述发光器件的阴极电性连接于所述第一节点；
所述第四晶体管的栅极电性连接于所述第二节点，所述第四晶体管的漏极电性连接于所述第一节点，所述第四晶体管的源极电性连接于第二电源信号。
在本申请所提供的像素驱动电路中，所述第一晶体管、所述第二晶体管、所述第三晶体管以及所述第四晶体管均为NMOS管。
在本申请所提供的像素驱动电路中，所述像素驱动电路的驱动时序包括：
复位阶段，对所述第一节点的电位以及所述第二节点的电位进行复位；
阈值电压获取阶段，抓取所述第四晶体管的阈值电压并存储至所述存储电容上
数据写入阶段，将所述数据信号写入所述存储电容的第一端，并根据所述存储电容的耦合作用，所述存储电容的第二端的电位跳变至相应电位；
发光阶段，像素驱动电路产生驱动电流并提供至所述发光器件，用于驱动所述发光器件的发光显示。
在本申请所提供的像素驱动电路中，在所述复位阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述复位信号通过所述第二晶体管传输至所述第一节点，所述数据信号通过所述第一晶体管传输至所述存储电容的第一端，所述第二节点的电位根据所述存储电容的耦合作用跳变至所述数据信号对应的电位；
在阈值电压获取阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第一电源信号通过所述第三晶体管对所述存储电容进行充电，直至所述第四晶体管的栅极与源极之间的压差等于所述第四晶体管的阈值电压时截止；
在数据写入阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述数据信号通过所述第一晶体管传输至所述存储电容的第一端，所述第一节点的电位根据所述存储电容的耦合作用跳变相应电位；
在所述发光阶段，所述第一控制信号为低电位，所述第二控制信号为低电位，所述电源信号通过发光器件的阳极传输至所述发光器件的阴极，所述发光器件发光。
第二方面，本申请提供了一种像素驱动电路，包括：复位模块、补偿模块、数据写入模块和发光模块；所述复位模块、所述数据写入模块以及所述发光模块均与所述补偿模块连接；
所述复位模块接入第一控制信号，所述复位模块用于在所述第一控制信号的控制下将复位信号传输至所述发光模块以对所述发光模块进行第一次复位；
所述数据写入模块接入所述第一控制信号，所述数据写入模块用于在所述第一控制信号的控制下，并通过数据信号的参考电位对所述发光模块进行第二次复位；
所述补偿模块接入第二控制信号，所述补偿模块用于在所述第二控制信号的控制下获取阈值电压；
所述数据写入模块还用于在所述第一控制信号的控制下将数据信号的显示电位传输至所述补偿模块。
在本申请所提供的像素驱动电路中，所述复位模块包括：第一晶体管；
所述第一晶体管的栅极电性连接于所述第一控制信号，所述第一晶体管的漏极电性连接于所述复位信号，所述第一晶体管的源极电性连接于第一节点。
在本申请所提供的像素驱动电路中，所述补偿模块包括：第二晶体管以及存储电容；
所述第二晶体管的栅极电性连接于所述第二控制信号，所述第二晶体管的漏极电性连接于所述第一节点，所述第三晶体管的源极电性连接于第二节点；
所述存储电容的第一端电性连接于数据写入模块，所述存储电容的第二端电性连接于所述第二节点。
在本申请所提供的像素驱动电路中，所述数据写入模块包括：第三晶体管；
所述第三晶体管的栅极电性连接于所述第一控制信号，所述第三晶体管的漏极电性连接于所述数据信号，所述第三晶体管的源极电性连接于所述存储电容的第一端。
在本申请所提供的像素驱动电路中，所述发光模块包括：发光器件以及第四晶体管；
所述发光器件的阳极电性连接于第一电源信号，所述发光器件的阴极电性连接于所述第一节点；
所述第四晶体管的栅极电性连接于所述第二节点，所述第四晶体管的漏极电性连接于所述第一节点，所述第四晶体管的源极电性连接于第二电源信号。
在本申请所提供的像素驱动电路中，所述第一晶体管、所述第二晶体管、所述第三晶体管以及所述第四晶体管均为NMOS管。
在本申请所提供的像素驱动电路中，所述像素驱动电路的驱动时序包括：
复位阶段，对所述第一节点的电位以及所述第二节点的电位进行复位；
阈值电压获取阶段，抓取所述第四晶体管的阈值电压并存储至所述存储电容上
数据写入阶段，将所述数据信号写入所述存储电容的第一端，并根据所述存储电容的耦合作用，所述存储电容的第二端的电位跳变至相应电位；
发光阶段，像素驱动电路产生驱动电流并提供至所述发光器件，用于驱动所述发光器件的发光显示。
在本申请所提供的像素驱动电路中，在所述复位阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述复位信号通过所述第二晶体管传输至所述第一节点，所述数据信号通过所述第一晶体管传输至所述存储电容的第一端，所述第二节点的电位根据所述存储电容的耦合作用跳变至所述数据信号对应的电位；
在阈值电压获取阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第一电源信号通过所述第三晶体管对所述存储电容进行充电，直至所述第四晶体管的栅极与源极之间的压差等于所述第四晶体管的阈值电压时截止；
在数据写入阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述数据信号通过所述第一晶体管传输至所述存储电容的第一端，所述第一节点的电位根据所述存储电容的耦合作用跳变相应电位；
在所述发光阶段，所述第一控制信号为低电位，所述第二控制信号为低电位，所述电源信号通过发光器件的阳极传输至所述发光器件的阴极，所述发光器件发光。
在本申请所提供的像素驱动电路中，所述第一控制信号以及所述第二控制信号均由外部时序器提供。
在本申请所提供的像素驱动电路中，流经所述发光器件的电流与所述第四晶体管的阈值电压无关。
第三方面，本申请提供一种显示面板，包括像素驱动电路；
所述像素驱动电路包括：复位模块、补偿模块、数据写入模块和发光模块；所述复位模块、所述数据写入模块以及所述发光模块均与所述补偿模块连接；
所述复位模块接入第一控制信号，所述复位模块用于在所述第一控制信号的控制下将复位信号传输至所述发光模块以对所述发光模块进行第一次复位；
所述数据写入模块接入所述第一控制信号，所述数据写入模块用于在所述第一控制信号的控制下，并通过数据信号的参考电位对所述发光模块进行第二次复位；
所述补偿模块接入第二控制信号，所述补偿模块用于在所述第二控制信号的控制下获取阈值电压；
所述数据写入模块还用于在所述第一控制信号的控制下将数据信号的显示电位传输至所述补偿模块。
 有益效果
本申请的有益效果是：采用4T1C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，并且，发光器件的驱动电流不受第一电源信号的影响，因此，提高了发光器件发光的稳定性，进而提高画质。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的像素驱动电路的结构示意图；
图2为本申请实施例提供的像素驱动电路的电路示意图；
图3为本申请提供的像素驱动电路的驱动信号的时序图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管可以包括P 型晶体管和/或N 型晶体管两种，其中，P 型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N 型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
参阅图1，图1为本发明提供的像素驱动电路的结构示意图。如图1所示，该像素驱动电路，包括:复位模块101、补偿模块102、数据写入模块103和发光模块104。复位模块101、数据写入模块103以及发光模块104均与补偿模块102连接。
其中，复位模块101接入第一控制信号Y，复位模块101用于在第一控制信号Y的控制下将复位信号R传输至发光模块103以对发光模块103进行第一次复位。数据写入模块103接入第一控制信号Y，数据写入模块103用于在第一控制信号Y的控制下，并通过数据信号D的参考电位对发光模块104进行第二次复位。补偿模块102接入第二控制信号E，补偿模块102用于在第二控制信号E的控制下写入数据信号D获取阈值电压。数据写入模块103还用于在第一控制信号Y的控制下将数据信号D的显示电位传输至补偿模块102。
具体的，请参阅图2，图2为本发明提供的像素驱动电路的电路原理图。
复位模块101包括：第一晶体管T1。第一晶体管T1的栅极电性连接于第一控制信号Y，第一晶体管T1的漏极电性连接于复位信号R，第一晶体管T1的源极电性连接于第一节点a。
补偿模块102包括：第二晶体管T2以及存储电容C。第二晶体管T2的栅极电性连接于第二控制信号E，第二晶体管T2的漏极电性连接于第一节点a，第二晶体管T2的源极电性连接于第二节点b。存储电容C的第一端电性连接于数据写入模块103，存储电容C的第二端电性连接于第二节点b。
数据写入模块103包括：第三晶体管。第三晶体管T3的栅极电性连接于第一控制信号Y，第三晶体管T3的漏极电性连接于数据信号D，第三晶体管T3的源极电性连接于存储电容C的第一端。
发光模块104包括：发光器件L以及第四晶体管T4。发光器件L的阳极电性连接于第一电源信号Y，发光器件L的阴极电性连接于所述第一节点a。第四晶体管T4为驱动晶体管，第四晶体管T4的栅极电性连接于第二节点b，第四晶体管T4的漏极电性连接于第一节点a，第四晶体管T4的源极电性连接于第二电源信号W。
进一步的，第一晶体管T1用于对发光器件L的阴极进行复位，第二晶体管T3用于抓取第四晶体管T4的阈值电压，第三晶体管T2用于对存储电容C的第一端进行复位，并通过存储电容C的耦合作用对第二节点b进行复位，即，通过存储电容C的耦合作用对第四晶体管T4的栅极进行复位，第四晶体管T4用于产生驱动电流并提供至发光器件L，使发光器件L发光。
在一些实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3以及第四晶体管T4均为N型晶体管。本申请实施例提供的像素驱动电路中的晶体管为同一种类型的晶体管，从而避免不同类型的晶体管之间的差异性对像素驱动电路造成的影响。
请参阅图3，图3为本发明提供的像素驱动电路的驱动信号的时序图。该像素驱动电路的驱动时序包括：
复位阶段t1，对第一节点a的电位以及第二节点b的电位进行复位。
阈值电压获取阶段t2，抓取第四晶体管T4的阈值电压Vth并存储至所述存储电容上
数据写入阶段t3，将数据信号D写入存储电容C的第一端，并根据存储电容C的耦合作用，存储电容C的第二端的电位跳变至相应电位。
发光阶段t4，像素驱动电路产生驱动电流并提供至发光器件L，用于驱动发光器件L的发光显示。
需要说明的是，在一些实施例中，第一控制信号Y以及第二控制信号E均由外部时序器提供。
其中，在复位阶段t1，第一控制信号Y为高电位，第二控制信号E为低电位，第一晶体管T1导通，第二晶体管T2导通，复位信号R通过第一晶体管T1传输至第一节点a，消除上一阶段残留在发光器件L的信号，以复位发光器件L，数据信号D通过第二晶体管T2传输至存储电容C的第一端，由于存储电容C的耦合作用，存储电容C的第二端的电位抬升至相应的电位，即第二节点b的电位抬升至相应的电位，以使第四晶体管T4导通。
也就是说，复位模块101对发光模块104进行第一次复位指的是：复位模块101中的第一晶体管T1对第一节点a进行复位，以复位发光模块104中的发光器件L。数据写入模块103通过数据信号D的参考电位对发光模块104进行第二次复位指的是：数据写入模块103中的第三晶体管T3通过数据信号D的参考电位对第二节点b进行复位。
比如，在复位阶段t1，第一控制信号的电位为22V，第二控制信号的电位为-8V。第一晶体管T1导通，第二晶体管T2导通，复位信号R通过第一晶体管T1传输至第一节点a，消除上一阶段残留在发光器件L的信号，以复位发光器件L，数据信号D的参考电位通过第二晶体管T2传输至存储电容C的第一端，数据信号D的参考电位可以为0V。由于存储电容C的耦合作用，存储电容C的第二端的电位抬升至相应的电位，即第二节点b的电位抬升至可以使第四晶体管T4导通电位，需要说明的是，第四晶体管T4可以和第三晶体管T3为同种晶体管，即，当第四晶体管T4栅极的电位大于-8V时，第四晶体管导通。即，在一些实施例中，第二节点b的电位可以抬升至数据信号D的参考电位0V，从而导通第四晶体管T4。
在阈值电压获取阶段t2，第一控制信号Y为低电位，第二控制信号E为高电位，第三晶体管T3导通，第四晶体管T4导通，第一电源信号H通过第三晶体管T3对存储电容进行充电，直至第四晶体管T4的栅极与源极之间的压差等于第四晶体管的阈值电压Vth时截止，第四晶体管T4源极的电位为第二电源信号W的电位Vw，即，第四晶体管T4截止时，第四晶体管T4的栅极的电位等于Vw+|Vth|。
比如，第一控制信号Y的电位为0V，第二控制信号E的电位为22V，第三晶体管T3导通，第四晶体管T4导通，第一电源信号H通过第三晶体管T3对存储电容进行充电，直至第四晶体管T4的栅极与源极之间的压差等于第四晶体管的阈值电压Vth时截止，第四晶体管T4源极的电位为第二电源信号W的电位Vw，即，第四晶体管T4截止时，第四晶体管T4的栅极的电位等于Vw+|Vth|。
在数据写入阶段t3，第一控制信号Y为高电位，第二控制信号E为低电位，第一晶体管T1导通，第二晶体管T2导通，数据信号D通过第二晶体管T2传输至存储电容C的第一端，第二节点b的电位根据存储电容C的耦合作用跳变相应电位，第二节点b的电位Vd+Vw+|Vth|，即，第四晶体管T4的栅极的电位为Vd+Vw+|Vth|。
比如，第一控制信号Y的电位为22V，第二控制信号E的电位为-8V，第一晶体管T1导通，第二晶体管T2导通，数据信号D的显示电位通过第二晶体管T2传输至存储电容C的第一端，数据信号D的显示电位可以为8V，第二节点b的电位根据存储电容C的耦合作用跳变至数据信号D的显示电位8V。
在所述发光阶段t4，第一控制信号Y为低电位，第二控制信号E为低电位，第四晶体管T4导通，由于存储电容C的耦合作用，第二节点b的电位Vd+Vw+|Vth|，即，第四晶体管T4的栅极的电位为Vd+Vw+|Vth|，第一电源信号H通过发光器件L的阳极传输至发光器件的阴极，即，第一电源信号H通过发光器件L传输至第一节点a，即，第四晶体管T4的漏极电位为第一电源信号H的电位Vh。此时，将对应于第四晶体管T4的栅源电压的驱动电流Id供应到发光器件D，导致发光器件D发光，第四晶体管T4产生的驱动电流Id由以下方程表示：
Id= k(Vgs-Vth)2=k[Vd+Vw+|Vth|-Vw）-|Vth|]2＝k（Vd）2。
在这个方程中，Id 表示流经发光器件D的电流，Vgs 表示第四晶体管T4的栅源电压，Vth 表示第四晶体管T4的阈值电压，Vd表示数据信号Z的电位，k 表示常数。由上式分析可知：该像素补偿电路的驱动电流Id将与Vth和Vw无关。因此，提高发光器件发光的稳定性，进而提高画质。
本申请提供的像素驱动电路以及显示面板，采用4T1C结构的像素驱动电路对每一像素中的驱动晶体管的阈值电压进行有效补偿，并且，发光器件的驱动电流不受第一电源信号的影响，因此，提高了发光器件发光的稳定性，进而提高画质。
以上仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (18)

  1. 一种像素驱动电路，其包括：复位模块、补偿模块、数据写入模块和发光模块；所述复位模块、所述数据写入模块以及所述发光模块均与所述补偿模块连接；
    所述复位模块接入第一控制信号，所述复位模块用于在所述第一控制信号的控制下将复位信号传输至所述发光模块以对所述发光模块进行第一次复位；
    所述数据写入模块接入所述第一控制信号，所述数据写入模块用于在所述第一控制信号的控制下，并通过数据信号的参考电位对所述发光模块进行第二次复位；
    所述补偿模块接入第二控制信号，所述补偿模块用于在所述第二控制信号的控制下获取阈值电压；
    所述数据写入模块还用于在所述第一控制信号的控制下将数据信号的显示电位传输至所述补偿模块；
    其中，所述第一控制信号以及所述第二控制信号均由外部时序器提供，流经所述发光器件的电流与所述第四晶体管的阈值电压无关。
  2. 根据权利要求1所述的像素驱动电路，其中，所述复位模块包括：第一晶体管；
    所述第一晶体管的栅极电性连接于所述第一控制信号，所述第一晶体管的漏极电性连接于所述复位信号，所述第一晶体管的源极电性连接于第一节点。
  3. 根据权利要求2所述的像素驱动电路，其中，所述补偿模块包括：第二晶体管以及存储电容；
    所述第二晶体管的栅极电性连接于所述第二控制信号，所述第二晶体管的漏极电性连接于所述第一节点，所述第三晶体管的源极电性连接于第二节点；
    所述存储电容的第一端电性连接于数据写入模块，所述存储电容的第二端电性连接于所述第二节点。
  4. 根据权利要求3所述的像素驱动电路，其中，所述数据写入模块包括：第三晶体管；
    所述第三晶体管的栅极电性连接于所述第一控制信号，所述第三晶体管的漏极电性连接于所述数据信号，所述第三晶体管的源极电性连接于所述存储电容的第一端。
  5. 根据权利要求4所述的像素驱动电路，其中，所述发光模块包括：发光器件以及第四晶体管；
    所述发光器件的阳极电性连接于第一电源信号，所述发光器件的阴极电性连接于所述第一节点；
    所述第四晶体管的栅极电性连接于所述第二节点，所述第四晶体管的漏极电性连接于所述第一节点，所述第四晶体管的源极电性连接于第二电源信号。
  6. 根据权利要求5所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管以及所述第四晶体管均为N型晶体管。
  7. 根据权利要求6所述的像素驱动电路，其中，所述像素驱动电路的驱动时序包括：
    复位阶段，对所述第一节点的电位以及所述第二节点的电位进行复位；
    阈值电压获取阶段，抓取所述第四晶体管的阈值电压并存储至所述存储电容上；
    数据写入阶段，将所述数据信号写入所述存储电容的第一端，并根据所述存储电容的耦合作用，所述存储电容的第二端的电位跳变至相应电位；
    发光阶段，像素驱动电路产生驱动电流并提供至所述发光器件，用于驱动所述发光器件的发光显示。
  8. 根据权利要求7所述的像素驱动电路，其中，在所述复位阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述复位信号通过所述第二晶体管传输至所述第一节点，所述数据信号通过所述第一晶体管传输至所述存储电容的第一端，所述第二节点的电位根据所述存储电容的耦合作用跳变至所述数据信号对应的电位；
    在阈值电压获取阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第一电源信号通过所述第三晶体管对所述存储电容进行充电，直至所述第四晶体管的栅极与源极之间的压差等于所述第四晶体管的阈值电压时截止；
    在数据写入阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述数据信号通过所述第一晶体管传输至所述存储电容的第一端，所述第一节点的电位根据所述存储电容的耦合作用跳变相应电位；
    在所述发光阶段，所述第一控制信号为低电位，所述第二控制信号为低电位，所述电源信号通过发光器件的阳极传输至所述发光器件的阴极，所述发光器件发光。
  9. 一种像素驱动电路，其包括：复位模块、补偿模块、数据写入模块和发光模块；所述复位模块、所述数据写入模块以及所述发光模块均与所述补偿模块连接；
    所述复位模块接入第一控制信号，所述复位模块用于在所述第一控制信号的控制下将复位信号传输至所述发光模块以对所述发光模块进行第一次复位；
    所述数据写入模块接入所述第一控制信号，所述数据写入模块用于在所述第一控制信号的控制下，并通过数据信号的参考电位对所述发光模块进行第二次复位；
    所述补偿模块接入第二控制信号，所述补偿模块用于在所述第二控制信号的控制下获取阈值电压；
    所述数据写入模块还用于在所述第一控制信号的控制下将数据信号的显示电位传输至所述补偿模块。
  10. 根据权利要求9所述的像素驱动电路，其中，所述复位模块包括：第一晶体管；
    所述第一晶体管的栅极电性连接于所述第一控制信号，所述第一晶体管的漏极电性连接于所述复位信号，所述第一晶体管的源极电性连接于第一节点。
  11. 根据权利要求10所述的像素驱动电路，其中，所述补偿模块包括：第二晶体管以及存储电容；
    所述第二晶体管的栅极电性连接于所述第二控制信号，所述第二晶体管的漏极电性连接于所述第一节点，所述第三晶体管的源极电性连接于第二节点；
    所述存储电容的第一端电性连接于数据写入模块，所述存储电容的第二端电性连接于所述第二节点。
  12. 根据权利要求11所述的像素驱动电路，其中，所述数据写入模块包括：第三晶体管；
    所述第三晶体管的栅极电性连接于所述第一控制信号，所述第三晶体管的漏极电性连接于所述数据信号，所述第三晶体管的源极电性连接于所述存储电容的第一端。
  13. 根据权利要求12所述的像素驱动电路，其中，所述发光模块包括：发光器件以及第四晶体管；
    所述发光器件的阳极电性连接于第一电源信号，所述发光器件的阴极电性连接于所述第一节点；
    所述第四晶体管的栅极电性连接于所述第二节点，所述第四晶体管的漏极电性连接于所述第一节点，所述第四晶体管的源极电性连接于第二电源信号。
  14. 根据权利要求13所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管以及所述第四晶体管均为N型晶体管。
  15. 根据权利要求14所述的像素驱动电路，其中，所述像素驱动电路的驱动时序包括：
    复位阶段，对所述第一节点的电位以及所述第二节点的电位进行复位；
    阈值电压获取阶段，抓取所述第四晶体管的阈值电压并存储至所述存储电容上；
    数据写入阶段，将所述数据信号写入所述存储电容的第一端，并根据所述存储电容的耦合作用，所述存储电容的第二端的电位跳变至相应电位；
    发光阶段，像素驱动电路产生驱动电流并提供至所述发光器件，用于驱动所述发光器件的发光显示。
  16. 根据权利要求15所述的像素驱动电路，其中，在所述复位阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述复位信号通过所述第二晶体管传输至所述第一节点，所述数据信号通过所述第一晶体管传输至所述存储电容的第一端，所述第二节点的电位根据所述存储电容的耦合作用跳变至所述数据信号对应的电位；
    在阈值电压获取阶段，所述第一控制信号为低电位，所述第二控制信号为高电位，所述第一电源信号通过所述第三晶体管对所述存储电容进行充电，直至所述第四晶体管的栅极与源极之间的压差等于所述第四晶体管的阈值电压时截止；
    在数据写入阶段，所述第一控制信号为高电位，所述第二控制信号为低电位，所述数据信号通过所述第一晶体管传输至所述存储电容的第一端，所述第一节点的电位根据所述存储电容的耦合作用跳变相应电位；
    在所述发光阶段，所述第一控制信号为低电位，所述第二控制信号为低电位，所述电源信号通过发光器件的阳极传输至所述发光器件的阴极，所述发光器件发光。
  17. 根据权利要求9所述的像素驱动电路，其中，所述第一控制信号以及所述第二控制信号均由外部时序器提供。
  18. 一种显示面板，其特征在于，包括像素驱动电路；
    所述像素驱动电路包括：复位模块、补偿模块、数据写入模块和发光模块；所述复位模块、所述数据写入模块以及所述发光模块均与所述补偿模块连接；
    所述复位模块接入第一控制信号，所述复位模块用于在所述第一控制信号的控制下将复位信号传输至所述发光模块以对所述发光模块进行第一次复位；
    所述数据写入模块接入所述第一控制信号，所述数据写入模块用于在所述第一控制信号的控制下，并通过数据信号的参考电位对所述发光模块进行第二次复位；
    所述补偿模块接入第二控制信号，所述补偿模块用于在所述第二控制信号的控制下获取阈值电压；
    所述数据写入模块还用于在所述第一控制信号的控制下将数据信号的显示电位传输至所述补偿模块。
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