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WO2020218526A1 - Semiconductor device having dolmen structure and manufacturing method therefor, and support piece formation laminate film and manufacturing method therefor - Google Patents

Semiconductor device having dolmen structure and manufacturing method therefor, and support piece formation laminate film and manufacturing method therefor Download PDF

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Publication number
WO2020218526A1
WO2020218526A1 PCT/JP2020/017731 JP2020017731W WO2020218526A1 WO 2020218526 A1 WO2020218526 A1 WO 2020218526A1 JP 2020017731 W JP2020017731 W JP 2020017731W WO 2020218526 A1 WO2020218526 A1 WO 2020218526A1
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WO
WIPO (PCT)
Prior art keywords
chip
support piece
film
layer
resin layer
Prior art date
Application number
PCT/JP2020/017731
Other languages
French (fr)
Japanese (ja)
Inventor
達也 矢羽田
紘平 谷口
慎太郎 橋本
義信 尾崎
Original Assignee
日立化成株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立化成株式会社 filed Critical 日立化成株式会社
Priority to KR1020217028895A priority Critical patent/KR20220002255A/en
Priority to CN202080020997.0A priority patent/CN113574665A/en
Priority to JP2021516271A priority patent/JP7494843B2/en
Priority to SG11202110148YA priority patent/SG11202110148YA/en
Priority to US17/439,400 priority patent/US20220149031A1/en
Publication of WO2020218526A1 publication Critical patent/WO2020218526A1/en

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Definitions

  • the present disclosure is supported and first by a substrate, a first chip arranged on the substrate, a plurality of support pieces arranged on the substrate and around the first chip, and a plurality of support pieces.
  • the present invention relates to a semiconductor device having a dolmen structure including a second chip arranged so as to cover the chip.
  • the present disclosure also relates to a method for manufacturing a semiconductor device having a dolmen structure, a laminated film for forming a support piece, and a method for manufacturing the same.
  • a dolmen (dolmen) is a kind of stone tomb, and has a plurality of pillar stones and a plate-shaped rock placed on the pillar stone.
  • a support piece corresponds to a "dolmen"
  • a second chip corresponds to a "plate-shaped rock”.
  • Patent Document 1 discloses a semiconductor die assembly including a controller die and a memory die supported by a support member on the controller die. It can be said that the semiconductor assembly 100 illustrated in FIG. 1A of Patent Document 1 has a dolmen structure.
  • the semiconductor assembly 100 includes the package substrate 102, the controller dies 103 arranged on the surface of the package substrate 102, the memory dies 106a and 106b arranged above the controller dies 103, and the support members 130a and 130b for supporting the memory dies 106a. To be equipped.
  • Patent Document 1 discloses that a semiconductor material such as silicon can be used as a support member (support piece), and more specifically, a fragment of the semiconductor material obtained by dicing a semiconductor wafer can be used (Patent Document 1). 1 [0012], [0014] and FIG. 2).
  • a support piece for a dolmen structure using a semiconductor wafer for example, the following steps are required as in the case of manufacturing a normal semiconductor chip. (1) A process of attaching a back grind tape to a semiconductor wafer (2) A process of back grinding a semiconductor wafer (3) An adhesive layer and an adhesive layer are applied to a dicing ring and a semiconductor wafer after back grinding arranged therein.
  • the present disclosure provides a method for manufacturing a semiconductor device that can simplify the process of manufacturing a support piece in the process for manufacturing a semiconductor device having a dolmen structure.
  • the present disclosure also provides a semiconductor device having a dolmen structure, a laminated film for forming a support piece, and a method for producing the same.
  • One aspect of the present disclosure relates to a method for manufacturing a semiconductor device having a dolmen structure.
  • This manufacturing method includes the following steps.
  • D Step of arranging the first chip on the substrate
  • E Around the first chip on the substrate or Step of arranging a plurality of support pieces around the area where the first chip should be arranged
  • Adhesion including a second chip and an adhesive piece provided on one surface of the second chip.
  • Step of preparing chips with agent pieces Step of constructing a dolmen structure by arranging chips with adhesive pieces on the surfaces of a plurality of support pieces
  • the support piece forming film is one of the following films. .. -A film composed of a thermosetting resin layer-A film composed of a layer obtained by curing at least a part of the thermosetting resin layer-A thermosetting resin layer and a resin layer having higher rigidity than the thermosetting resin layer
  • the multilayer film (D) and (E) steps having the multilayer film / thermosetting resin layer having the above and the metal layer having higher rigidity than the thermosetting resin layer may be carried out first. Good.
  • a plurality of support pieces may be arranged on the substrate and around the first chip.
  • a plurality of support pieces are placed around the region on the substrate on which the first chip should be placed, and then (D).
  • the first chip may be placed in the region.
  • the rigidity of the thermosetting resin layer after heat curing may be lower or higher than the rigidity of the resin layer or the metal layer. Rigidity means the ability of an object to withstand fracture against bending or twisting.
  • a support piece obtained by individualizing a support piece forming film is used.
  • the process of manufacturing the support piece can be simplified as compared with the conventional manufacturing method in which a fragment of the semiconductor material obtained by dicing a semiconductor wafer is used as the support piece. That is, while the above-mentioned steps (1) to (7) have been conventionally required, since the support piece forming film does not include the semiconductor wafer, the back grind of the semiconductor wafer (1), (2) and The step (4) can be omitted.
  • the thermosetting resin layer has adhesiveness to other members (for example, a substrate), it is not necessary to separately provide an adhesive layer or the like on the support piece.
  • the adhesive layer of the laminated film prepared in the step (A) may be a pressure-sensitive type or an ultraviolet curable type. That is, the adhesive layer may or may not be cured by ultraviolet irradiation, in other words, it may or may not contain a resin having a carbon-carbon double bond having photoreactivity. It does not have to be.
  • the pressure-sensitive adhesive layer may contain a resin having a carbon-carbon double bond having photoreactivity.
  • the adhesive layer may be one in which the adhesiveness of the predetermined region is lowered by irradiating the predetermined region with ultraviolet rays, and for example, a resin having a carbon-carbon double bond having photoreactivity may be used. It may remain.
  • the adhesive layer is an ultraviolet curable type, the adhesiveness of the adhesive layer can be reduced by carrying out a step of irradiating the adhesive layer with ultraviolet rays between the steps (B) and (C).
  • the support piece forming film contains a thermosetting resin layer.
  • the step of heating the support piece forming film or the support piece to cure the thermosetting resin layer or the adhesive piece may be carried out at an appropriate timing, and may be carried out, for example, before the step (G).
  • the thermosetting resin layer is already cured to prevent the support pieces from being deformed with the arrangement of the chips with adhesive pieces. it can.
  • One aspect of this disclosure relates to a semiconductor device having a dolmen structure. That is, this semiconductor device is supported by a substrate, a first chip arranged on the substrate, a plurality of support pieces arranged on the substrate and around the first chip, and a plurality of support pieces. It has a dolmen structure including a second chip arranged so as to cover the first chip, and the support piece is made of a cured product of the thermosetting resin composition, or is a thermosetting resin composition. It includes a layer made of a cured product and a resin layer or a metal layer. The first chip may be separated from the second chip.
  • the semiconductor device may further include an adhesive piece provided on one surface of the second chip and sandwiched between the second chip and a plurality of support pieces.
  • the first chip may be separated from the adhesive piece or may be in contact with the adhesive piece.
  • the adhesive piece is provided, for example, so as to cover at least the area of the second chip facing the first chip.
  • the adhesive piece extends continuously from the above-mentioned region of the second chip to the peripheral side of the second chip, and may be sandwiched between the second chip and a plurality of support pieces. That is, one piece of adhesive may cover the region of the second chip and bond the second chip to the plurality of support pieces.
  • This laminated film includes a base film, an adhesive layer, and a support piece forming film in this order, and the support piece forming film is a film made of a thermosetting resin layer or a thermosetting resin layer. It is a film composed of at least a partially cured layer, or a multilayer film having a thermosetting resin layer and a resin layer or a metal layer having higher rigidity than the thermosetting resin layer.
  • the thickness of the support piece forming film is, for example, 5 to 180 ⁇ m. When the thickness of the support piece forming film is in this range, a dolmen structure having an appropriate height with respect to the first chip (for example, a controller chip) can be constructed.
  • the thermosetting resin layer in the support piece forming film contains, for example, an epoxy resin.
  • the thermosetting resin layer preferably contains an elastomer. Since the thermosetting resin layer constituting the support piece contains an elastomer, the stress in the semiconductor device can be relaxed.
  • the resin layer of the support piece forming film is, for example, a polyimide layer.
  • the metal layer of the support piece forming film is, for example, a copper layer or an aluminum layer.
  • One aspect of the present disclosure relates to a method for manufacturing a laminated film for forming a support piece.
  • This manufacturing method includes a step of preparing an adhesive film having a base film and an adhesive layer formed on one surface thereof, and a step of laminating a support piece forming film on the surface of the adhesive layer.
  • the support piece forming film is a film composed of a thermosetting resin layer, a film composed of a layer obtained by curing at least a part of the thermosetting resin layer, or a thermosetting resin layer and the thermosetting resin layer. It is a multilayer film having a resin layer or a metal layer having higher rigidity.
  • a laminated film for forming a support piece having a resin layer or a metal layer can be manufactured, for example, as follows. That is, the method for producing the laminated film for forming the support piece is a step of preparing a laminated film including a base film, an adhesive layer, and a thermosetting resin layer in this order, and a step of preparing a laminated film on the surface of the thermosetting resin layer. It includes a step of laminating a resin layer or a metal layer having higher rigidity than the thermosetting resin layer.
  • a method for manufacturing a semiconductor device that can simplify the process of manufacturing a support piece in the process for manufacturing a semiconductor device having a dolmen structure. Further, the present disclosure provides a semiconductor device having a dolmen structure, a laminated film for forming a support piece, and a method for producing the same.
  • FIG. 1 is a cross-sectional view schematically showing a first embodiment of the semiconductor device according to the present disclosure.
  • 2 (a) and 2 (b) are plan views schematically showing an example of the positional relationship between the first chip and the plurality of support pieces.
  • FIG. 3A is a plan view schematically showing an embodiment of a laminated film for forming a support piece
  • FIG. 3B is a cross-sectional view taken along the line bb of FIG. 3A.
  • FIG. 4 is a cross-sectional view schematically showing a step of bonding the adhesive layer and the support piece forming film.
  • 5 (a) to 5 (d) are cross-sectional views schematically showing a manufacturing process of the support piece.
  • FIG. 1 is a cross-sectional view schematically showing a first embodiment of the semiconductor device according to the present disclosure.
  • 2 (a) and 2 (b) are plan views schematically showing an example of the positional relationship between the first chip and the plurality of support pieces.
  • FIG. 3A
  • FIG. 6 is a cross-sectional view schematically showing a state in which a plurality of support pieces are arranged on the substrate and around the first chip.
  • FIG. 7 is a cross-sectional view schematically showing an example of a chip with an adhesive piece.
  • FIG. 8 is a cross-sectional view schematically showing a dolmen structure formed on the substrate.
  • FIG. 9 is a cross-sectional view schematically showing a second embodiment of the semiconductor device according to the present disclosure.
  • 10 (a) and 10 (b) are cross-sectional views schematically showing other embodiments of a laminated film for forming a support piece.
  • (meth) acrylic acid means acrylic acid or methacrylic acid
  • (meth) acrylate means acrylate or the corresponding methacrylate
  • a or B may include either A or B, or both.
  • the term “layer” includes not only a structure having a shape formed on the entire surface but also a structure having a shape partially formed when observed as a plan view.
  • the term “process” is used not only as an independent process but also as a term as long as the desired action of the process is achieved even when it cannot be clearly distinguished from other processes. included.
  • the numerical range indicated by using "-” indicates a range including the numerical values before and after "-" as the minimum value and the maximum value, respectively.
  • the content of each component in the composition is the total amount of the plurality of substances present in the composition unless otherwise specified, when a plurality of substances corresponding to each component are present in the composition. means.
  • the exemplary materials may be used alone or in combination of two or more.
  • the upper limit value or the lower limit value of the numerical range of one step may be replaced with the upper limit value or the lower limit value of the numerical range of another step.
  • the upper limit value or the lower limit value of the numerical range may be replaced with the value shown in the examples.
  • FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to the present embodiment.
  • the semiconductor device 100 shown in this figure includes a substrate 10, a chip T1 (first chip) arranged on the surface of the substrate 10, and a plurality of chips T1 arranged on the surface of the substrate 10 and around the chip T1.
  • the support piece Dc, the chip T2 (second chip) arranged above the chip T1, the adhesive piece Tc sandwiched between the chip T2 and the plurality of support pieces Dc, and the chip T2 are laminated.
  • a stopper 50 is provided.
  • a dolmen structure is formed on the substrate 10 by a plurality of support pieces Dc, a chip T2, and an adhesive piece Tc located between the support piece Dc and the chip T2.
  • the chip T1 is separated from the adhesive piece Tc.
  • the adhesive piece Tc between the chip T1 and the chip T2 covers the region R of the chip T2 facing the chip T1 and continuously extends from the region R to the peripheral side of the chip T2. doing. That is, one adhesive piece Tc covers the region R of the chip T2, intervenes between the chip T2 and the plurality of support pieces, and adheres them.
  • FIG. 1 illustrates an embodiment in which the adhesive piece Tc is provided so as to cover the entire one surface (lower surface) of the chip T2.
  • the adhesive piece Tc may shrink in the manufacturing process of the semiconductor device 100, it suffices to substantially cover the entire one surface (lower surface) of the chip T2, for example, the peripheral edge of the chip T2.
  • the lower surface of the chip T2 in FIG. 1 corresponds to the back surface of the chip. In recent years, the back surface of chips is often uneven. Since substantially the entire back surface of the chip T2 is covered with the adhesive piece Tc, it is possible to prevent the chip T2 from cracking or cracking.
  • the substrate 10 may be an organic substrate or a metal substrate such as a lead frame. From the viewpoint of suppressing the warp of the semiconductor device 100, the thickness of the substrate 10 is, for example, 90 to 300 ⁇ m, and may be 90 to 210 ⁇ m.
  • the chip T1 is, for example, a controller chip, which is adhered to the substrate 10 by the adhesive piece T1c and electrically connected to the substrate 10 by the wire w.
  • the shape of the chip T1 in a plan view is, for example, a rectangle (square or rectangle).
  • the length of one side of the chip T1 is, for example, 5 mm or less, and may be 2 to 5 mm or 1 to 5 mm.
  • the thickness of the chip T1 is, for example, 10 to 150 ⁇ m, and may be 20 to 100 ⁇ m.
  • the chip T2 is, for example, a memory chip, and is adhered onto the support piece Dc via the adhesive piece Tc. In plan view, the chip T2 has a larger size than the chip T1.
  • the shape of the chip T2 in a plan view is, for example, a rectangle (square or rectangle).
  • the length of one side of the chip T2 is, for example, 20 mm or less, and may be 4 to 20 mm or 4 to 12 mm.
  • the thickness of the chip T2 is, for example, 10 to 170 ⁇ m, and may be 20 to 120 ⁇ m.
  • the chips T3 and T4 are also memory chips, for example, and are adhered onto the chip T2 via an adhesive piece Tc.
  • the length of one side of the chips T3 and T4 may be the same as that of the chip T2, and the thickness of the chips T3 and T4 may be the same as that of the chip T2.
  • the support piece Dc acts as a spacer that forms a space around the chip T1.
  • the support piece Dc is made of a cured product of a thermosetting resin composition.
  • two support pieces Dc shape: rectangle
  • One support piece Dc shape: square, total of four
  • the length of one side of the support piece Dc in a plan view is, for example, 20 mm or less, and may be 1 to 20 mm or 1 to 12 mm.
  • the thickness (height) of the support piece Dc is, for example, 10 to 180 ⁇ m, and may be 20 to 120 ⁇ m.
  • the support piece Dc shown in FIG. 1 is after the thermosetting tree composition has been cured.
  • the support piece Da is in a state before the thermosetting tree composition is completely cured (see, for example, FIG. 5B).
  • the laminated film 20 for forming a support piece (hereinafter, sometimes referred to as "laminated film 20") shown in FIGS. 3 (a) and 3 (b) is prepared.
  • the laminated film 20 includes a base film 1, an adhesive layer 2, and a support piece forming film D.
  • the base film 1 is, for example, a polyethylene terephthalate film (PET film).
  • PET film polyethylene terephthalate film
  • the adhesive layer 2 is formed in a circular shape by punching or the like (see FIG. 3A).
  • the adhesive layer 2 is made of an ultraviolet curable adhesive. That is, the adhesive layer 2 has a property that the adhesiveness is lowered by being irradiated with ultraviolet rays.
  • the support piece forming film D is formed in a circular shape by punching or the like, and has a diameter smaller than that of the adhesive layer 2 (see FIG. 3A).
  • the support piece forming film D is made of a thermosetting resin composition.
  • thermosetting resin composition constituting the support piece forming film D can be in a semi-cured (B stage) state and then in a completely cured product (C stage) state by a subsequent curing treatment.
  • the thermosetting resin composition contains an epoxy resin, a curing agent, and an elastomer (for example, an acrylic resin), and further contains an inorganic filler, a curing accelerator, and the like, if necessary. Details of the thermosetting resin composition constituting the support piece forming film D will be described later.
  • the laminated film 20 is, for example, a second laminated film having a base film 1 and an adhesive layer 2 on the surface thereof, and a cover film 3 and a support piece forming film D on the surface thereof. It can be produced by laminating with a film (see FIG. 4).
  • the first laminated film is obtained through a step of forming an adhesive layer on the surface of the base film 1 by coating and a step of processing the adhesive layer into a predetermined shape (for example, a circle) by punching or the like.
  • the second laminated film has a step of forming a support piece forming film on the surface of the cover film 3 (for example, PET film or polyethylene film) by coating, and a predetermined shape (for example, by punching the support piece forming film). For example, it is obtained through a process of processing into a circular shape.
  • the cover film 3 is peeled off at an appropriate timing.
  • the dicing ring DR is attached to the laminated film 20. That is, the dicing ring DR is attached to the adhesive layer 2 of the laminated film 20, and the support piece forming film D is arranged inside the dicing ring DR.
  • the support piece forming film D is individualized by dicing (see FIG. 5B). As a result, a large number of support pieces Da can be obtained from the support piece forming film D.
  • the adhesive layer 2 is irradiated with ultraviolet rays to reduce the adhesive force between the adhesive layer 2 and the support piece Da.
  • the base film 1 is expanded to separate the support pieces Da from each other. As shown in FIG.
  • the support piece Da is peeled off from the adhesive layer 2 by pushing up the support piece Da with the push-up jig 42, and the support piece Da is picked up by suction with the suction collet 44.
  • the curing reaction of the thermosetting resin may be allowed to proceed by heating the support piece forming film D before dicing or the support piece Da before picking up. Excellent pickup performance can be achieved by appropriately curing the support piece Da when picking up.
  • the notch for individualization is formed up to the outer edge of the support piece forming film D.
  • the diameter of the support piece forming film D may be, for example, 300 to 310 mm or 300 to 305 mm.
  • the shape of the support piece forming film D in a plan view is not limited to the circle shown in FIG. 3A, and may be a rectangle (square or rectangle).
  • the manufacturing method according to this embodiment includes the following steps (A) to (H).
  • E Step of arranging a plurality of support pieces Da on the substrate 10 around the first chip T1 (see FIG. 6).
  • (F) A step of preparing a chip T2a with an adhesive piece, which includes a second chip T2 and an adhesive piece Ta provided on one surface of the second chip T2 (see FIG. 7).
  • (G) A step of constructing a dolmen structure by arranging a chip T2a with an adhesive piece on the surface of a plurality of support pieces Dc (see FIG. 8).
  • (H) A step of sealing the gap between the chip T1 and the chip T2 with the sealing material 50 (see FIG. 1).
  • the steps (A) to (C) are processes for producing a plurality of support pieces Da, and have already been described.
  • the steps (D) to (H) are processes in which a dolmen structure is constructed on the substrate 10 by using a plurality of support pieces Da.
  • the steps (D) to (H) will be described with reference to FIGS. 6 to 8.
  • the step (D) is a step of arranging the first chip T1 on the substrate 10. For example, first, the chip T1 is arranged at a predetermined position on the substrate 10 via the adhesive layer T1c. After that, the chip T1 is electrically connected to the substrate 10 by the wire w.
  • the step (D) may be a step performed before the step (E), and before the step (A), between the steps (A) and (B), the steps (B) and (C). It may be between steps, or between steps (C) and (E).
  • the step (E) is a step of arranging a plurality of support pieces Da on the substrate 10 around the first chip T1.
  • the structure 30 shown in FIG. 6 is produced.
  • the structure 30 includes a substrate 10, a chip T1 arranged on the surface thereof, and a plurality of support pieces Da.
  • the support piece Da may be arranged by crimping.
  • the crimping treatment is preferably carried out, for example, under the conditions of 80 to 180 ° C. and 0.01 to 0.50 MPa for 0.5 to 3.0 seconds.
  • the support piece Da may be completely cured at the time of the step (E) to become the support piece Dc, and may not be completely cured at this time. It is preferable that the support piece Da is completely cured to become the support piece Dc before the start of the step (G).
  • the step (F) is a step of preparing the adhesive chip T2a shown in FIG. 7.
  • the adhesive piece T2a includes a chip T2 and an adhesive piece Ta provided on the surface of one of the chips T2.
  • the chip T2a with an adhesive piece can be obtained through a dicing step and a pick-up step using, for example, a semiconductor wafer and a dicing / die bonding integrated film.
  • the step (G) is a step of arranging the chip T2a with the adhesive piece above the chip T1 so that the adhesive piece Ta is in contact with the upper surface of the plurality of support pieces Dc.
  • the chip T2 is crimped to the upper surface of the support piece Dc via the adhesive piece Ta.
  • This crimping treatment is preferably carried out for 0.5 to 3.0 seconds under the conditions of, for example, 80 to 180 ° C. and 0.01 to 0.50 MPa.
  • the adhesive piece Ta is cured by heating. This curing treatment is preferably carried out for 5 minutes or more under the conditions of, for example, 60 to 175 ° C. and 0.01 to 1.0 MPa.
  • the adhesive piece Ta is cured to become the adhesive piece Tc.
  • a dolmen structure is constructed on the substrate 10 (see FIG. 8). Since the tip T1 is separated from the tip T2a with the adhesive piece, it is possible to prevent the wire w from being short-circuited due to the upper portion of the wire w coming into contact with the tip T2. Further, since it is not necessary to embed the wire in the adhesive piece Ta in contact with the chip T2, there is an advantage that the adhesive piece Ta can be thinned.
  • the chip T3 is placed on the chip T2 via the adhesive piece, and further, the chip T4 is placed on the chip T3 via the adhesive piece.
  • the adhesive piece may be any thermosetting resin composition similar to the above-mentioned adhesive piece Ta, and becomes an adhesive piece Tc by heat curing (see FIG. 1).
  • the chips T2, T3 and T4 and the substrate 10 are electrically connected by wires w.
  • the number of chips stacked above the chip T1 is not limited to the three in this embodiment, and may be appropriately set.
  • Step (H) The step (H) is a step of sealing the gap between the chip T1 and the chip T2 with the sealing material 50. Through this step, the semiconductor device 100 shown in FIG. 1 is completed.
  • thermosetting resin composition constituting the support piece forming film D contains an epoxy resin, a curing agent, and an elastomer, and further contains an inorganic filler, a curing accelerator, and the like, if necessary.
  • the support piece Da and the support piece Dc after curing have the following characteristics.
  • -Characteristic 1 When the support piece Da is thermocompression bonded to a predetermined position on the substrate 10, the position shift is unlikely to occur (the melt viscosity of the support piece Da at 120 ° C. is, for example, 4300 to 50,000 Pa ⁇ s or 5000 to 40,000 Pa ⁇ s.
  • -Characteristic 2 The support piece Dc exhibits stress relaxation property in the semiconductor device 100 (the thermosetting resin composition contains an elastomer (rubber component)).
  • -Characteristic 3 The adhesive strength of the chip with the adhesive piece to the adhesive piece Tc is sufficiently high (the die share strength of the support piece Dc with respect to the adhesive piece Tc is, for example, 2.0 to 7.0 Mpa or 3.0 to 3.0 to. (Being 6.0 Mpa)
  • -Characteristic 4 The shrinkage rate due to curing is sufficiently small.
  • -Characteristic 5 The visibility of the support piece Da by the camera in the pickup process is good (the thermosetting resin composition contains, for example, a colorant).
  • -Characteristic 6 The support piece Dc has sufficient mechanical strength.
  • Epoxy resin The epoxy resin is not particularly limited as long as it is cured and has an adhesive action.
  • Bifunctional epoxy resins such as bisphenol A type epoxy resin, bisphenol F type epoxy resin, and bisphenol S type epoxy resin, novolak type epoxy resins such as phenol novolac type epoxy resin and cresol novolac type epoxy resin can be used.
  • novolak type epoxy resins such as phenol novolac type epoxy resin and cresol novolac type epoxy resin
  • generally known ones such as a polyfunctional epoxy resin, a glycidylamine type epoxy resin, a heterocyclic epoxy resin, and an alicyclic epoxy resin can be applied. These may be used alone or in combination of two or more.
  • Examples of the curing agent include phenolic resins, ester compounds, aromatic amines, aliphatic amines and acid anhydrides. Of these, phenolic resins are preferred from the perspective of achieving high die shear strength.
  • Commercially available phenolic resins include, for example, LF-4871 (trade name, BPA novolac type phenolic resin) manufactured by DIC Co., Ltd. and HE-100C-30 (trade name, phenylarakil type) manufactured by Air Water Inc. Phenolic resin), Phenolite KA and TD series manufactured by DIC Co., Ltd., Millex XLC-series and XL series manufactured by Mitsui Chemicals Co., Ltd.
  • Millex XLC-LL HE series manufactured by Air Water Inc.
  • HE100C-30 HE100C-30
  • MEHC-7800 series manufactured by Meiwa Kasei Co., Ltd. for example, MEHC-7800-4S
  • JDPP series manufactured by JEF Chemical Co., Ltd. can be mentioned. These may be used alone or in combination of two or more.
  • the blending amount of the epoxy resin and the phenol resin is preferably such that the equivalent ratio of the epoxy equivalent and the hydroxyl group equivalent is 0.6 to 1.5, and is 0.7 to 1.4, respectively, from the viewpoint of achieving high die shear strength. More preferably, it is more preferably 0.8 to 1.3. When the compounding ratio is within the above range, it is easy to achieve both curability and fluidity at a sufficiently high level.
  • Examples of the elastoma include acrylic resin, polyester resin, polyamide resin, polyimide resin, silicone resin, polybutadiene, acrylonitrile, epoxy-modified polybutadiene, maleic anhydride-modified polybutadiene, phenol-modified polybutadiene and carboxy-modified acrylonitrile.
  • an acrylic resin is preferable as the elastoma, and further, an epoxy group-containing epoxy group obtained by polymerizing an epoxy group such as glycidyl acrylate or glycidyl methacrylate or a functional monomer having a glycidyl group as a crosslinkable functional group.
  • Acrylic resins such as (meth) acrylic copolymers are more preferable.
  • epoxy group-containing (meth) acrylic acid ester copolymers and epoxy group-containing acrylic rubbers are preferable, and epoxy group-containing acrylic rubbers are more preferable.
  • the epoxy group-containing acrylic rubber is a rubber having an epoxy group, which is mainly composed of an acrylic acid ester as a main component, a copolymer such as butyl acrylate and acrylonitrile, and a copolymer such as ethyl acrylate and acrylonitrile.
  • the acrylic resin may have not only an epoxy group but also a crosslinkable functional group such as an alcoholic or phenolic hydroxyl group or a carboxyl group.
  • acrylic resin products include SG-70L, SG-708-6, WS-023 EK30, SG-280 EK23, SG-P3 solvent modified products (trade name, acrylic rubber, weight) manufactured by Nagase Chemtech Co., Ltd. Average molecular weight: 800,000, Tg: 12 ° C., solvent is cyclohexanone) and the like.
  • the glass transition temperature (Tg) of the acrylic resin is preferably ⁇ 50 to 50 ° C., more preferably ⁇ 30 to 30 ° C. from the viewpoint of achieving high die shear strength.
  • the weight average molecular weight (Mw) of the acrylic resin is preferably 100,000 to 3 million, more preferably 500,000 to 2 million, from the viewpoint of achieving high die share strength.
  • Mw means a value measured by gel permeation chromatography (GPC) and converted using a calibration curve using standard polystyrene.
  • the amount of the acrylic resin contained in the thermosetting resin composition is preferably 10 to 200 parts by mass with respect to 100 parts by mass of the total of the epoxy resin and the epoxy resin curing agent from the viewpoint of achieving high die shear strength. More preferably, it is 20 to 100 parts by mass.
  • Inorganic fillers include, for example, aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, aluminum oxide, aluminum nitride, aluminum borate whisker, boron nitride and crystalline. Examples include silica and amorphous silica. These may be used alone or in combination of two or more.
  • the average particle size of the inorganic filler is preferably 0.005 ⁇ m to 1.0 ⁇ m, more preferably 0.05 to 0.5 ⁇ m, from the viewpoint of achieving high die shear strength.
  • the surface of the inorganic filler is preferably chemically modified from the viewpoint of achieving high die shear strength.
  • Silane coupling agents are suitable as materials for chemically modifying the surface. Examples of the types of functional groups of the silane coupling agent include vinyl group, acryloyl group, epoxy group, mercapto group, amino group, diamino group, alkoxy group and ethoxy group.
  • the content of the inorganic filler is preferably 20 to 200 parts by mass and 30 to 100 parts by mass with respect to 100 parts by mass of the resin component of the thermosetting resin composition. Is more preferable.
  • curing accelerator examples include imidazoles and derivatives thereof, organophosphorus compounds, secondary amines, tertiary amines, and quaternary ammonium salts. From the viewpoint of achieving high die shear strength, imidazole-based compounds are preferable. Examples of the imidazoles include 2-methylimidazole, 1-benzyl-2-methylimidazole, 1-cyanoethyl-2-phenylimidazole, 1-cyanoethyl-2-methylimidazole and the like. These may be used alone or in combination of two or more.
  • the content of the curing accelerator in the thermosetting resin composition is preferably 0.04 to 3 parts by mass with respect to 100 parts by mass in total of the epoxy resin and the epoxy resin curing agent from the viewpoint of achieving high die shear strength, and is 0. .04 to 0.2 parts by mass is more preferable.
  • FIG. 9 is a cross-sectional view schematically showing the semiconductor device according to the second embodiment.
  • the chip T1 is separated from the adhesive piece Tc, whereas in the semiconductor device 200 according to the present embodiment, the chip T1 is in contact with the adhesive piece Tc. .. That is, the adhesive piece Tc is in contact with the upper surface of the chip T1 and the upper surface of the support piece Dc.
  • the position of the upper surface of the chip T1 and the position of the upper surface of the support piece Dc can be matched.
  • the chip T1 is connected to the substrate 10 by a flip chip instead of wire bonding. If the wire w is embedded in the adhesive piece Ta, the chip T1 can be in contact with the adhesive piece Tc even when the chip T1 is wire-bonded to the substrate 10.
  • the adhesive piece Ta constitutes the chip T2a with the adhesive piece together with the chip T2 (see FIG. 8).
  • the adhesive piece Tc between the chip T1 and the chip T2 covers the region R of the chip T2 facing the chip T1 and continuously extends from the region R to the peripheral side of the chip T2. doing.
  • This one adhesive piece Tc covers the region R of the chip T2 and is interposed between the chip T2 and the plurality of support pieces to bond them.
  • the lower surface of the chip T2 in FIG. 9 corresponds to the back surface. As described above, the back surface of recent chips is often formed with irregularities. Since substantially the entire back surface of the chip T2 is covered with the adhesive piece Tc, it is possible to prevent the chip T2 from cracking or cracking even if the upper surface of the chip T1 comes into contact with the adhesive piece Tc.
  • the present invention is not limited to the above embodiments.
  • the laminated film 20 having the ultraviolet curable adhesive layer 2 is illustrated, but the adhesive layer 2 may be a pressure sensitive type.
  • a support piece forming laminated film 20 including a support piece forming film D made of a thermosetting resin layer is illustrated, but the support piece forming laminated film 20 is illustrated.
  • It may be provided with a multilayer film having a thermosetting resin layer and a resin layer or a metal layer having higher rigidity than the thermosetting resin layer.
  • the laminated film 20A for forming a support piece shown in FIG. 10A is a two-layer film D2 (support piece formation) having a thermosetting resin layer 5 and a resin layer 6 having a higher rigidity than the thermosetting resin layer 5. Film).
  • thermosetting resin layer 5 is arranged between the adhesive layer 2 and the outermost resin layer 6.
  • the thermosetting resin layer 5 is made of a thermosetting resin composition constituting the support piece forming film D according to the first embodiment.
  • the thickness of the resin layer 6 is, for example, 5 to 100 ⁇ m, and may be 10 to 90 ⁇ m or 20 to 80 ⁇ m.
  • the resin layer 6 is, for example, a polyimide layer.
  • the thermosetting resin layer 5 is made of a material different from that of the resin layer 6.
  • the ratio of the thickness of the thermosetting resin layer 5 to the thickness of the bilayer film D2 is preferably 0.1 to 0.8, more preferably 0.2 to 0.7, and even more preferably 0. It is 2 to 0.6.
  • this ratio is 0.1 or more, the adhesive pieces 5p and 5c can play their roles (for example, supporting the chip T2 and preventing the resin piece 6p from being displaced) to a higher degree.
  • the ratio is 0.8 or less, since the resin piece 6p has a sufficient thickness, the resin piece 6p acts like a spring plate, and more excellent pick-up property can be achieved (FIG. 5 (d)). )reference).
  • the thickness of the resin layer 6 is, for example, 20 to 80 ⁇ m, and may be 20 to 60 ⁇ m.
  • the thickness of the thermosetting resin layer 5 is, for example, 5 to 120 ⁇ m, and may be 10 to 60 ⁇ m.
  • the laminated film 20B for forming a support piece shown in FIG. 10B has a resin layer 6 having a higher rigidity than a thermosetting resin layer and a two-layer thermosetting resin layer 5 sandwiching the resin layer 6. It has a layer film D3 (a film for forming a support piece). In the support piece forming laminated film 20B, the three-layer film D3 is arranged on the surface of the adhesive layer 2.
  • the thermosetting resin layer 5 is made of a material different from that of the resin layer 6.
  • the laminated films 20A and 20B for forming support pieces include a resin layer 6 having a higher rigidity than the thermosetting resin layer 5, so that the thermosetting resin layer 5 is heat-cured after being individualized by dicing. Excellent pick-up performance can be achieved without performing processing.
  • a metal layer for example, a copper layer or an aluminum layer
  • the thickness of the metal layer is, for example, 5 to 100 ⁇ m and may be 10 to 90 ⁇ m or 20 to 80 ⁇ m.
  • the ratio of the total thickness of the two thermosetting resin layers 5 and 5 to the thickness of the three-layer film D3 is preferably 0.1 to 0.9, and more preferably 0.2 to 0.8. , More preferably 0.2 to 0.7.
  • pick-up property can be realized in the manufacturing process of the support piece (see FIG. 5D). That is, when the ratio is 0.1 or more, even when a metal layer is used instead of the resin layer 6, the edge of the metal piece (the metal layer is individualized) becomes the adhesive layer 2. It is possible to more highly suppress the deterioration of the pick-up property of the support piece due to the entry.
  • the resin piece (the resin layer 6 is separated into individual pieces) or the metal piece has a sufficient thickness, so that they act like a spring plate, and more. Excellent pickup performance can be achieved.
  • the thickness of the resin layer 6 or the metal layer is, for example, 10 to 80 ⁇ m, and may be 20 to 60 ⁇ m.
  • the thickness of the thermosetting resin layer 5 (one layer) is, for example, 5 to 120 ⁇ m, and may be 10 to 60 ⁇ m.
  • the functions can be shared among the layers, and the functionality of the film can be improved.
  • a support piece Da more suitable for the dolmen structure can be produced.
  • the laminated film 20A for forming a support piece can be manufactured, for example, through the following steps. -A step of preparing a laminated film including a base film 1, an adhesive layer 2, and a thermosetting resin layer 5 in this order.-A resin having a higher rigidity than the thermosetting resin layer 5 on the surface of the laminated film. Step of laminating layer 6 or metal layer
  • Varnish A for the support piece forming film was prepared using the following materials.
  • -Epoxy resin 1 YDCN-700-10: (trade name, manufactured by Nippon Steel & Sumitomo Metal Corporation, cresol novolac type epoxy resin, solid at 25 ° C) 5.4 parts by mass-Epoxy resin 2: YDF-8170C: (product Name, manufactured by Nippon Steel & Sumitomo Metal Chemical Co., Ltd., liquid bisphenol F type epoxy resin, liquid at 25 ° C) 16.2 parts by mass ⁇
  • Varnish B for the support piece forming film was prepared using the following materials.
  • -Epoxy resin YDCN-700-10: (trade name, manufactured by Nippon Steel & Sumitomo Metal Chemical Co., Ltd., cresol novolac type epoxy resin, solid at 25 ° C) 13.2 parts by mass-Pphenol resin (hardener): HE-100C- 30: (Product name, manufactured by Air Water Co., Ltd., phenyl araquil type phenol resin) 11.0 parts by mass ⁇
  • Elastoma SG-P3 solvent modified product (trade name, manufactured by Nagase ChemteX Corporation, acrylic rubber, weight average molecular weight: 800,000, Tg: 12 ° C, solvent is cyclohe
  • coupling agent 1 A-189: (trade name, manufactured by GE Toshiba Corporation, ⁇ -mercaptopropyltrimethoxysilane) 0.4 parts by mass
  • coupling agent 2 A-1160: (trade name) , GE Toshiba Co., Ltd., ⁇ -ureidopropyltriethoxysilane) 1.15 parts by mass
  • Curing accelerator Curesol 2PZ-CN: (trade name, manufactured by Shikoku Kasei Kogyo Co., Ltd., 1-cyanoethyl-2-phenyl) Imidazole) 0.03 parts by mass
  • Solvent Cyclohexane
  • Example 1 As described above, cyclohexanone was used as a solvent, and the solid content ratio of varnish A was adjusted to 40% by mass. Varnish A was filtered with a 100 mesh filter and vacuum defoamed. As a film to which the varnish A was applied, a polyethylene terephthalate (PET) film (thickness 38 ⁇ m) subjected to a mold release treatment was prepared. The varnish A after vacuum defoaming was applied onto the release-treated surface of the PET film. The applied varnish A was heated and dried in two steps at 90 ° C. for 5 minutes and then at 140 ° C. for 5 minutes. In this way, the thermosetting resin layer A in the B stage state (semi-cured state) was formed on the surface of the PET film.
  • PET polyethylene terephthalate
  • a laminated film (dicing tape) having an ultraviolet curable adhesive layer was prepared by the following procedure.
  • a copolymer was obtained by solution radical polymerization using 83 parts by mass of 2-ethylhexyl acrylate, 15 parts by mass of 2-hydroxyethyl acrylate, and 2 parts by mass of methacrylic acid as raw materials and ethyl acetate as a solvent. 12 parts by mass of 2-methacryloyloxyethyl isocyanate was reacted with this acrylic copolymer to synthesize an ultraviolet irradiation type acrylic copolymer having a carbon-carbon double bond. In the above reaction, 0.05 part of hydroquinone / monomethyl ether was used as a polymerization inhibitor.
  • the weight average molecular weight of the synthesized acrylic copolymer was measured by GPC and found to be 300,000 to 700,000.
  • the acrylic copolymer thus obtained and a polyisocyanate compound manufactured by Nippon Polyurethane Industry Co., Ltd., trade name: Coronate L
  • a polyisocyanate compound manufactured by Nippon Polyurethane Industry Co., Ltd., trade name: Coronate L
  • Coronate L a polyisocyanate compound
  • -Hydroxycyclohexylphenylketone 0.5 part was mixed to prepare an ultraviolet irradiation type pressure-sensitive adhesive solution.
  • This ultraviolet irradiation type pressure-sensitive adhesive solution was applied and dried on a polyethylene terephthalate release film (thickness: 38 ⁇ m) so that the thickness after drying was 10 ⁇ m. Then, a polyolefin film (thickness: 90 ⁇ m) having been subjected to corona discharge treatment on one side was attached to the pressure-sensitive adhesive layer. The obtained laminated film was aged in a constant temperature bath at 40 ° C. for 72 hours to prepare a dicing tape.
  • thermosetting resin layer A having a thickness of 50 ⁇ m was heated at 110 ° C. for 1 hour and then heated at 130 ° C. for 3 hours to cure the cured resin layer A.
  • the cured resin layer A was attached to the adhesive layer of the dicing tape on a hot plate at 70 ° C. using a rubber roll. Through this step, a laminate of a support piece forming film and a dicing tape was obtained.
  • thermosetting resin layer A was heated at 110 ° C. for 1 hour and then cured by heating at 110 ° C. for 2 hours instead of heating at 130 ° C. for 3 hours.
  • a laminate of a support piece forming film and a dicing tape was obtained.
  • thermosetting resin layer B is formed on the surface of the PET film by using the varnish B instead of the varnish A, and the thermosetting resin layer B is rubber-rolled on the adhesive layer of the dicing tape on a hot plate at 70 ° C.
  • a polyimide film (thickness 25 ⁇ m) was bonded to the thermosetting resin layer B with a rubber roll. Through this step, a laminate of a support piece forming film and a dicing tape was obtained.
  • peeling Strength A test piece was prepared by cutting the laminate containing the support piece forming film according to Examples 1 to 3 into a width of 25 mm and a length of 100 mm, respectively. Then, ultraviolet rays were irradiated from the dicing tape side under the conditions of 80 mW / cm 2 and 200 mJ / cm 2 with a halogen lamp. The peel strength (peeling angle: 180 °, peeling speed: 300 mm / min) at the interface between the adhesive layer irradiated with ultraviolet rays and the film for forming a support piece was measured. For each example, the measurement was performed three times, and the average value is shown below. Example 1 ... 0.03N / 25mm
  • Example 3 0.05 N / 25 mm
  • Ultraviolet rays were irradiated from the dicing tape side toward the adhesive layer of the support piece with a halogen lamp under the conditions of 80 mW / cm 2 and 200 mJ / cm 2 . Then, the support piece was picked up in a state of being expanded (expanded amount: 3 mm) with a die bonder. A three-stage push-up stage was used as the push-up jig, and the conditions were a push-up speed of 10 mm / sec and a push-up height of 1200 ⁇ m. When an attempt was made to pick up the six support pieces for each example, all of the six support pieces could be picked up in any of the first to third embodiments.
  • a method for manufacturing a semiconductor device that can simplify the process of manufacturing a support piece in the process for manufacturing a semiconductor device having a dolmen structure. Further, the present disclosure provides a semiconductor device having a dolmen structure, a laminated film for forming a support piece, and a method for producing the same.

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Abstract

A semiconductor device according to the present disclosure has a dolmen structure including: a substrate; a first chip disposed on the substrate; a plurality of support pieces arranged on the substrate and around the first chip; and a second chip supported by the plurality of support pieces and disposed to cover the first chip, wherein the support piece is made of a cured product of a thermosetting resin composition or includes a layer made of a cured product of the thermosetting resin composition and a resin layer or a metal layer.

Description

ドルメン構造を有する半導体装置及びその製造方法、並びに、支持片形成用積層フィルム及びその製造方法A semiconductor device having a dolmen structure and a manufacturing method thereof, and a laminated film for forming a support piece and a manufacturing method thereof.
　本開示は、基板と、基板上に配置された第一のチップと、基板上であって第一のチップの周囲に配置された複数の支持片と、複数の支持片によって支持され且つ第一のチップを覆うように配置された第二のチップとを含むドルメン構造を有する半導体装置に関する。また、本開示は、ドルメン構造を有する半導体装置の製造方法、並びに、支持片形成用積層フィルム及びその製造方法に関する。なお、ドルメン（ｄｏｌｍｅｎ、支石墓）は、石墳墓の一種であり、複数の支柱石と、その上に載せられた板状の岩とを備える。ドルメン構造を有する半導体装置において、支持片が「支柱石」に相当し、第二のチップが「板状の岩」に相当する。 The present disclosure is supported and first by a substrate, a first chip arranged on the substrate, a plurality of support pieces arranged on the substrate and around the first chip, and a plurality of support pieces. The present invention relates to a semiconductor device having a dolmen structure including a second chip arranged so as to cover the chip. The present disclosure also relates to a method for manufacturing a semiconductor device having a dolmen structure, a laminated film for forming a support piece, and a method for manufacturing the same. A dolmen (dolmen) is a kind of stone tomb, and has a plurality of pillar stones and a plate-shaped rock placed on the pillar stone. In a semiconductor device having a dolmen structure, a support piece corresponds to a "dolmen" and a second chip corresponds to a "plate-shaped rock".
　近年、半導体装置の分野において、高集積、小型化及び高速化が求められている。半導体装置の一態様として、基板上に配置されたコントローラーチップの上に半導体チップを積層させる構造が注目を集めている。例えば、特許文献１は、コントローラダイと、コントローラダイの上に支持部材によって支持されたメモリダイとを含む半導体ダイアセンブリを開示している。特許文献１の図１Ａに図示された半導体アセンブリ１００はドルメン構造を有するということができる。すなわち、半導体アセンブリ１００は、パッケージ基板１０２と、その表面上に配置されたコントローラダイ１０３と、コントローラダイ１０３の上方に配置されたメモリダイ１０６ａ，１０６ｂと、メモリダイ１０６ａを支持する支持部材１３０ａ，１３０ｂとを備える。 In recent years, in the field of semiconductor devices, high integration, miniaturization, and high speed have been required. As one aspect of a semiconductor device, a structure in which a semiconductor chip is laminated on a controller chip arranged on a substrate is attracting attention. For example, Patent Document 1 discloses a semiconductor die assembly including a controller die and a memory die supported by a support member on the controller die. It can be said that the semiconductor assembly 100 illustrated in FIG. 1A of Patent Document 1 has a dolmen structure. That is, the semiconductor assembly 100 includes the package substrate 102, the controller dies 103 arranged on the surface of the package substrate 102, the memory dies 106a and 106b arranged above the controller dies 103, and the support members 130a and 130b for supporting the memory dies 106a. To be equipped.
特表２０１７－５１５３０６号公報Special Table 2017-515306
　特許文献１は、支持部材（支持片）として、シリコンなどの半導体材料を使用できること、より具体的には半導体ウェハをダイシングして得られる半導体材料の断片を使用できることを開示している（特許文献１の［００１２］、［００１４］及び図２参照）。半導体ウェハを使用してドルメン構造用の支持片を製造するには、通常の半導体チップの製造と同様、例えば、以下の各工程が必要である。
（１）半導体ウェハにバックグラインドテープを貼り付ける工程
（２）半導体ウェハをバックグラインドする工程
（３）ダイシングリングとその中に配置されたバックグラインド後の半導体ウェハに対し、粘着層と接着剤層とを有するフィルム（ダイシング・ダイボンディング一体型フィルム）を貼り付ける工程
（４）半導体ウェハからバックグラインドテープを剥がす工程
（５）半導体ウェハを個片化する工程
（６）半導体チップと接着剤片の積層体からなる支持片を粘着層からピックアップする工程
（７）複数の支持片を基板の所定の位置に圧着する工程 Patent Document 1 discloses that a semiconductor material such as silicon can be used as a support member (support piece), and more specifically, a fragment of the semiconductor material obtained by dicing a semiconductor wafer can be used (Patent Document 1). 1 [0012], [0014] and FIG. 2). In order to manufacture a support piece for a dolmen structure using a semiconductor wafer, for example, the following steps are required as in the case of manufacturing a normal semiconductor chip.
(1) A process of attaching a back grind tape to a semiconductor wafer (2) A process of back grinding a semiconductor wafer (3) An adhesive layer and an adhesive layer are applied to a dicing ring and a semiconductor wafer after back grinding arranged therein. Step of pasting a film (die-bonding integrated film) with and (4) Step of peeling backgrinding tape from semiconductor wafer (5) Step of fragmenting semiconductor wafer (6) Semiconductor chip and adhesive piece Step of picking up a support piece made of a laminated body from an adhesive layer (7) A step of crimping a plurality of support pieces to a predetermined position on a substrate
　本開示は、ドルメン構造を有する半導体装置の製造プロセスにおいて支持片を作製する工程を簡略化できる半導体装置の製造方法を提供する。また、本開示は、ドルメン構造を有する半導体装置、並びに支持片形成用積層フィルム及びその製造方法を提供する。 The present disclosure provides a method for manufacturing a semiconductor device that can simplify the process of manufacturing a support piece in the process for manufacturing a semiconductor device having a dolmen structure. The present disclosure also provides a semiconductor device having a dolmen structure, a laminated film for forming a support piece, and a method for producing the same.
　本開示の一側面はドルメン構造を有する半導体装置の製造方法に関する。この製造方法は以下の工程を含む。
（Ａ）基材フィルムと、粘着層と、支持片形成用フィルムとをこの順序で備える積層フィルムを準備する工程
（Ｂ）支持片形成用フィルムを個片化することによって、粘着層の表面上に複数の支持片を形成する工程
（Ｃ）粘着層から支持片をピックアップする工程
（Ｄ）基板上に第一のチップを配置する工程
（Ｅ）基板上であって第一のチップの周囲又は第一のチップが配置されるべき領域の周囲に複数の支持片を配置する工程
（Ｆ）第二のチップと、第二のチップの一方の面上に設けられた接着剤片とを備える接着剤片付きチップを準備する工程
（Ｇ）複数の支持片の表面上に接着剤片付きチップを配置することによってドルメン構造を構築する工程
　上記支持片形成用フィルムは以下のフィルムのいずれか一つである。
・熱硬化性樹脂層からなるフィルム
・熱硬化性樹脂層のうち少なくとも一部を硬化させた層からなるフィルム
・熱硬化性樹脂層と、当該熱硬化性樹脂層よりも高い剛性を有する樹脂層とを有する多層フィルム
・熱硬化性樹脂層と、当該熱硬化性樹脂層よりも高い剛性を有する金属層とを有する多層フィルム
　（Ｄ）工程及び（Ｅ）工程はどちらを先に実施してもよい。（Ｄ）工程を先に実施する場合、（Ｅ）工程において、基板上であって第一のチップの周囲に複数の支持片を配置すればよい。他方、（Ｅ）工程を先に実施する場合、（Ｅ）工程において、基板上であって第一のチップが配置されるべき領域の周囲に複数の支持片を配置し、その後、（Ｄ）工程において、当該領域に第一のチップを配置すればよい。なお、上記熱硬化性樹脂層の熱硬化後の剛性は樹脂層又は金属層の剛性よりも低くても高くてもよい。剛性は、物体が曲げ又はねじれに対して破壊に耐える能力を意味する。 One aspect of the present disclosure relates to a method for manufacturing a semiconductor device having a dolmen structure. This manufacturing method includes the following steps.
(A) Step of preparing a laminated film including a base film, an adhesive layer, and a support piece forming film in this order (B) By individualizing the support piece forming film on the surface of the adhesive layer Step of forming a plurality of support pieces in (C) Step of picking up support pieces from the adhesive layer (D) Step of arranging the first chip on the substrate (E) Around the first chip on the substrate or Step of arranging a plurality of support pieces around the area where the first chip should be arranged (F) Adhesion including a second chip and an adhesive piece provided on one surface of the second chip. Step of preparing chips with agent pieces (G) Step of constructing a dolmen structure by arranging chips with adhesive pieces on the surfaces of a plurality of support pieces The support piece forming film is one of the following films. ..
-A film composed of a thermosetting resin layer-A film composed of a layer obtained by curing at least a part of the thermosetting resin layer-A thermosetting resin layer and a resin layer having higher rigidity than the thermosetting resin layer The multilayer film (D) and (E) steps having the multilayer film / thermosetting resin layer having the above and the metal layer having higher rigidity than the thermosetting resin layer may be carried out first. Good. When the step (D) is carried out first, in the step (E), a plurality of support pieces may be arranged on the substrate and around the first chip. On the other hand, when the step (E) is carried out first, in the step (E), a plurality of support pieces are placed around the region on the substrate on which the first chip should be placed, and then (D). In the process, the first chip may be placed in the region. The rigidity of the thermosetting resin layer after heat curing may be lower or higher than the rigidity of the resin layer or the metal layer. Rigidity means the ability of an object to withstand fracture against bending or twisting.
　本開示に係る上記製造方法においては、支持片形成用フィルムを個片化して得られる支持片を使用する。これにより、支持片として、半導体ウェハをダイシングして得られる半導体材料の断片を使用する従来の製造方法と比較すると、支持片を作製する工程を簡略化できる。すなわち、従来、上述の（１）～（７）の工程を必要としていたのに対し、支持片形成用フィルムは半導体ウェハを含まないため、半導体ウェハのバックグラインドに関する（１）、（２）及び（４）の工程を省略できる。また、樹脂材料と比較して高価な半導体ウェハを使用しないため、コストも削減できる。なお、熱硬化性樹脂層は他の部材（例えば、基板）に対して接着性を有するため、支持片に接着剤層等を別途設けなくてもよい。 In the above-mentioned manufacturing method according to the present disclosure, a support piece obtained by individualizing a support piece forming film is used. As a result, the process of manufacturing the support piece can be simplified as compared with the conventional manufacturing method in which a fragment of the semiconductor material obtained by dicing a semiconductor wafer is used as the support piece. That is, while the above-mentioned steps (1) to (7) have been conventionally required, since the support piece forming film does not include the semiconductor wafer, the back grind of the semiconductor wafer (1), (2) and The step (4) can be omitted. In addition, since a semiconductor wafer, which is more expensive than a resin material, is not used, the cost can be reduced. Since the thermosetting resin layer has adhesiveness to other members (for example, a substrate), it is not necessary to separately provide an adhesive layer or the like on the support piece.
　（Ａ）工程で準備する積層フィルムの粘着層は、感圧型であっても、紫外線硬化型であってもよい。すなわち、粘着層は、紫外線照射によって硬化するものであっても、そうでなくてもよく、換言すれば、光反応性を有する炭素－炭素二重結合を有する樹脂を含有しても、含有しなくてもよい。なお、感圧型の粘着層が光反応性を有する炭素－炭素二重結合を有する樹脂を含有してもよい。例えば、粘着層は、その所定の領域に紫外線を照射することによって当該領域の粘着性を低下させたものであってもよく、例えば、光反応性を有する炭素－炭素二重結合を有する樹脂が残存していてもよい。粘着層が紫外線硬化型である場合、（Ｂ）工程と（Ｃ）工程の間に、粘着層に紫外線を照射する工程を実施することで粘着層の粘着性を低下させることができる。 The adhesive layer of the laminated film prepared in the step (A) may be a pressure-sensitive type or an ultraviolet curable type. That is, the adhesive layer may or may not be cured by ultraviolet irradiation, in other words, it may or may not contain a resin having a carbon-carbon double bond having photoreactivity. It does not have to be. The pressure-sensitive adhesive layer may contain a resin having a carbon-carbon double bond having photoreactivity. For example, the adhesive layer may be one in which the adhesiveness of the predetermined region is lowered by irradiating the predetermined region with ultraviolet rays, and for example, a resin having a carbon-carbon double bond having photoreactivity may be used. It may remain. When the adhesive layer is an ultraviolet curable type, the adhesiveness of the adhesive layer can be reduced by carrying out a step of irradiating the adhesive layer with ultraviolet rays between the steps (B) and (C).
　支持片形成用フィルムは熱硬化性樹脂層を含む。支持片形成用フィルム又は支持片を加熱して熱硬化性樹脂層又は接着剤片を硬化させる工程は適切なタイミングで実施すればよく、例えば、（Ｇ）工程よりも前に実施すればよい。複数の支持片の表面に接するように接着剤片付きチップを配置する段階において、熱硬化性樹脂層が既に硬化していることで接着剤片付きチップの配置に伴って支持片が変形することを抑制できる。 The support piece forming film contains a thermosetting resin layer. The step of heating the support piece forming film or the support piece to cure the thermosetting resin layer or the adhesive piece may be carried out at an appropriate timing, and may be carried out, for example, before the step (G). At the stage of arranging the chips with adhesive pieces so as to be in contact with the surfaces of a plurality of support pieces, the thermosetting resin layer is already cured to prevent the support pieces from being deformed with the arrangement of the chips with adhesive pieces. it can.
　本開示の一側面はドルメン構造を有する半導体装置に関する。すなわち、この半導体装置は、基板と、基板上に配置された第一のチップと、基板上であって第一のチップの周囲に配置された複数の支持片と、複数の支持片によって支持され且つ第一のチップを覆うように配置された第二のチップとを含むドルメン構造を有し、支持片が、熱硬化性樹脂組成物の硬化物からなる、あるいは、熱硬化性樹脂組成物の硬化物からなる層と樹脂層又は金属層とを含む。第一のチップは、第二のチップと離間していてもよい。 One aspect of this disclosure relates to a semiconductor device having a dolmen structure. That is, this semiconductor device is supported by a substrate, a first chip arranged on the substrate, a plurality of support pieces arranged on the substrate and around the first chip, and a plurality of support pieces. It has a dolmen structure including a second chip arranged so as to cover the first chip, and the support piece is made of a cured product of the thermosetting resin composition, or is a thermosetting resin composition. It includes a layer made of a cured product and a resin layer or a metal layer. The first chip may be separated from the second chip.
　本開示に係る上記半導体装置は、第二のチップの一方の面上に設けられており且つ第二のチップと複数の支持片とによって挟まれている接着剤片を更に備えてもよい。この場合、上記第一のチップは、接着剤片と離間していてもよいし、接着剤片と接していてもよい。接着剤片は、例えば、第二のチップにおける第一のチップと対面する領域を少なくとも覆うように設けられている。接着剤片は、第二のチップの上記領域から第二のチップの周縁側にまで連続的に延在しており第二のチップと複数の支持片とによって挟まれていてもよい。つまり、一つの接着剤片が第二のチップの上記領域を覆い且つ第二のチップと複数の支持片とを接着していてもよい。 The semiconductor device according to the present disclosure may further include an adhesive piece provided on one surface of the second chip and sandwiched between the second chip and a plurality of support pieces. In this case, the first chip may be separated from the adhesive piece or may be in contact with the adhesive piece. The adhesive piece is provided, for example, so as to cover at least the area of the second chip facing the first chip. The adhesive piece extends continuously from the above-mentioned region of the second chip to the peripheral side of the second chip, and may be sandwiched between the second chip and a plurality of support pieces. That is, one piece of adhesive may cover the region of the second chip and bond the second chip to the plurality of support pieces.
　本開示の一側面は支持片形成用積層フィルムに関する。この積層フィルムは、基材フィルムと、粘着層と、支持片形成用フィルムとをこの順序で備え、支持片形成用フィルムは、熱硬化性樹脂層からなるフィルム、又は熱硬化性樹脂層のうち少なくとも一部を硬化させた層からなるフィルム、あるいは、熱硬化性樹脂層と当該熱硬化性樹脂層よりも高い剛性を有する樹脂層又は金属層とを有する多層フィルムである。 One aspect of the present disclosure relates to a laminated film for forming a support piece. This laminated film includes a base film, an adhesive layer, and a support piece forming film in this order, and the support piece forming film is a film made of a thermosetting resin layer or a thermosetting resin layer. It is a film composed of at least a partially cured layer, or a multilayer film having a thermosetting resin layer and a resin layer or a metal layer having higher rigidity than the thermosetting resin layer.
　上記支持片形成用フィルムの厚さは、例えば、５～１８０μｍである。支持片形成用フィルムの厚さがこの範囲であることで、第一のチップ（例えば、コントローラチップ）に対して適度な高さのドルメン構造を構築できる。支持片形成用フィルムにおける熱硬化性樹脂層は、例えば、エポキシ樹脂を含む。熱硬化性樹脂層はエラストマを含むことが好ましい。支持片を構成する熱硬化性樹脂層がエラストマを含むことで半導体装置内における応力を緩和できる。 The thickness of the support piece forming film is, for example, 5 to 180 μm. When the thickness of the support piece forming film is in this range, a dolmen structure having an appropriate height with respect to the first chip (for example, a controller chip) can be constructed. The thermosetting resin layer in the support piece forming film contains, for example, an epoxy resin. The thermosetting resin layer preferably contains an elastomer. Since the thermosetting resin layer constituting the support piece contains an elastomer, the stress in the semiconductor device can be relaxed.
　支持片形成用フィルムが有する樹脂層は、例えば、ポリイミド層である。支持片形成用フィルムが有する金属層は、例えば、銅層又はアルミニウム層である。 The resin layer of the support piece forming film is, for example, a polyimide layer. The metal layer of the support piece forming film is, for example, a copper layer or an aluminum layer.
　本開示の一側面は支持片形成用積層フィルムの製造方法に関する。この製造方法は、基材フィルムと、その一方の面上に形成された粘着層とを有する粘着フィルムを準備する工程と、粘着層の表面上に支持片形成用フィルムを積層する工程とを含み、支持片形成用フィルムは、熱硬化性樹脂層からなるフィルム又は熱硬化性樹脂層のうち少なくとも一部を硬化させた層からなるフィルム、あるいは、熱硬化性樹脂層と当該熱硬化性樹脂層よりも高い剛性を有する樹脂層又は金属層とを有する多層フィルムである。 One aspect of the present disclosure relates to a method for manufacturing a laminated film for forming a support piece. This manufacturing method includes a step of preparing an adhesive film having a base film and an adhesive layer formed on one surface thereof, and a step of laminating a support piece forming film on the surface of the adhesive layer. The support piece forming film is a film composed of a thermosetting resin layer, a film composed of a layer obtained by curing at least a part of the thermosetting resin layer, or a thermosetting resin layer and the thermosetting resin layer. It is a multilayer film having a resin layer or a metal layer having higher rigidity.
　樹脂層又は金属層を有する支持片形成用積層フィルムは、例えば、以下のように製造することができる。すなわち、この支持片形成用積層フィルムの製造方法は、基材フィルムと、粘着層と、熱硬化性樹脂層とをこの順序で備える積層フィルムを準備する工程と、熱硬化性樹脂層の表面に当該熱硬化性樹脂層よりも高い剛性を有する樹脂層又は金属層を貼り合わせる工程とを含む。 A laminated film for forming a support piece having a resin layer or a metal layer can be manufactured, for example, as follows. That is, the method for producing the laminated film for forming the support piece is a step of preparing a laminated film including a base film, an adhesive layer, and a thermosetting resin layer in this order, and a step of preparing a laminated film on the surface of the thermosetting resin layer. It includes a step of laminating a resin layer or a metal layer having higher rigidity than the thermosetting resin layer.
　本開示によれば、ドルメン構造を有する半導体装置の製造プロセスにおいて支持片を作製する工程を簡略化できる半導体装置の製造方法が提供される。また、本開示によれば、ドルメン構造を有する半導体装置、並びに支持片形成用積層フィルム及びその製造方法が提供される。 According to the present disclosure, there is provided a method for manufacturing a semiconductor device that can simplify the process of manufacturing a support piece in the process for manufacturing a semiconductor device having a dolmen structure. Further, the present disclosure provides a semiconductor device having a dolmen structure, a laminated film for forming a support piece, and a method for producing the same.
図１は本開示に係る半導体装置の第一実施形態を模式的に示す断面図である。FIG. 1 is a cross-sectional view schematically showing a first embodiment of the semiconductor device according to the present disclosure. 図２（ａ）及び図２（ｂ）は第一のチップと複数の支持片との位置関係の例を模式的に示す平面図である。2 (a) and 2 (b) are plan views schematically showing an example of the positional relationship between the first chip and the plurality of support pieces. 図３（ａ）は支持片形成用積層フィルムの一実施形態を模式的に示す平面図であり、図３（ｂ）は図３（ａ）のｂ－ｂ線における断面図である。FIG. 3A is a plan view schematically showing an embodiment of a laminated film for forming a support piece, and FIG. 3B is a cross-sectional view taken along the line bb of FIG. 3A. 図４は粘着層と支持片形成用フィルムとを貼り合わせる工程を模式的に示す断面図である。FIG. 4 is a cross-sectional view schematically showing a step of bonding the adhesive layer and the support piece forming film. 図５（ａ）～図５（ｄ）は支持片の作製過程を模式的に示す断面図である。5 (a) to 5 (d) are cross-sectional views schematically showing a manufacturing process of the support piece. 図６は基板上であって第一のチップの周囲に複数の支持片を配置した状態を模式的に示す断面図である。FIG. 6 is a cross-sectional view schematically showing a state in which a plurality of support pieces are arranged on the substrate and around the first chip. 図７は接着剤片付きチップの一例を模式的に示す断面図である。FIG. 7 is a cross-sectional view schematically showing an example of a chip with an adhesive piece. 図８は基板上に形成されたドルメン構造を模式的に示す断面図である。FIG. 8 is a cross-sectional view schematically showing a dolmen structure formed on the substrate. 図９は本開示に係る半導体装置の第二実施形態を模式的に示す断面図である。FIG. 9 is a cross-sectional view schematically showing a second embodiment of the semiconductor device according to the present disclosure. 図１０（ａ）及び図１０（ｂ）は支持片形成用積層フィルムの他の実施形態をそれぞれ模式的に示す断面図である。10 (a) and 10 (b) are cross-sectional views schematically showing other embodiments of a laminated film for forming a support piece.
　以下、図面を参照しつつ、本開示の実施形態について詳細に説明する。ただし、本発明は以下の実施形態に限定されるものではない。なお、本明細書において、「（メタ）アクリル酸」とは、アクリル酸又はメタクリル酸を意味し、「（メタ）アクリレート」とは、アクリレート又はそれに対応するメタクリレートを意味する。「Ａ又はＢ」とは、ＡとＢのどちらか一方を含んでいればよく、両方とも含んでいてもよい。 Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. However, the present invention is not limited to the following embodiments. In addition, in this specification, "(meth) acrylic acid" means acrylic acid or methacrylic acid, and "(meth) acrylate" means acrylate or the corresponding methacrylate. “A or B” may include either A or B, or both.
　本明細書において「層」との語は、平面図として観察したときに、全面に形成されている形状の構造に加え、一部に形成されている形状の構造も包含される。また、本明細書において「工程」との語は、独立した工程だけではなく、他の工程と明確に区別できない場合であってもその工程の所期の作用が達成されれば、本用語に含まれる。また、「～」を用いて示された数値範囲は、「～」の前後に記載される数値をそれぞれ最小値及び最大値として含む範囲を示す。 In the present specification, the term "layer" includes not only a structure having a shape formed on the entire surface but also a structure having a shape partially formed when observed as a plan view. Further, in the present specification, the term "process" is used not only as an independent process but also as a term as long as the desired action of the process is achieved even when it cannot be clearly distinguished from other processes. included. In addition, the numerical range indicated by using "-" indicates a range including the numerical values before and after "-" as the minimum value and the maximum value, respectively.
　本明細書において組成物中の各成分の含有量は、組成物中に各成分に該当する物質が複数存在する場合、特に断らない限り、組成物中に存在する当該複数の物質の合計量を意味する。また、例示材料は特に断らない限り単独で用いてもよいし、二種以上を組み合わせて用いてもよい。また、本明細書中に段階的に記載されている数値範囲において、ある段階の数値範囲の上限値又は下限値は、他の段階の数値範囲の上限値又は下限値に置き換えてもよい。また、本明細書中に記載されている数値範囲において、その数値範囲の上限値又は下限値は、実施例に示されている値に置き換えてもよい。 In the present specification, the content of each component in the composition is the total amount of the plurality of substances present in the composition unless otherwise specified, when a plurality of substances corresponding to each component are present in the composition. means. Further, unless otherwise specified, the exemplary materials may be used alone or in combination of two or more. Further, in the numerical range described stepwise in the present specification, the upper limit value or the lower limit value of the numerical range of one step may be replaced with the upper limit value or the lower limit value of the numerical range of another step. Further, in the numerical range described in the present specification, the upper limit value or the lower limit value of the numerical range may be replaced with the value shown in the examples.
＜第一実施形態＞
（半導体装置）
　図１は本実施形態に係る半導体装置を模式的に示す断面図である。この図に示す半導体装置１００は、基板１０と、基板１０の表面上に配置されたチップＴ１（第一のチップ）と、基板１０の表面上であってチップＴ１の周囲に配置された複数の支持片Ｄｃと、チップＴ１の上方に配置されたチップＴ２（第二のチップ）と、チップＴ２と複数の支持片Ｄｃとによって挟まれている接着剤片Ｔｃと、チップＴ２上に積層されたチップＴ３，Ｔ４と、基板１０の表面上の電極（不図示）とチップＴ１～Ｔ４とをそれぞれ電気的に接続する複数のワイヤｗと、チップＴ１とチップＴ２との隙間等に充填された封止材５０とを備える。 <First Embodiment>
(Semiconductor device)
FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to the present embodiment. The semiconductor device 100 shown in this figure includes a substrate 10, a chip T1 (first chip) arranged on the surface of the substrate 10, and a plurality of chips T1 arranged on the surface of the substrate 10 and around the chip T1. The support piece Dc, the chip T2 (second chip) arranged above the chip T1, the adhesive piece Tc sandwiched between the chip T2 and the plurality of support pieces Dc, and the chip T2 are laminated. A plurality of wires w that electrically connect the chips T3 and T4, electrodes (not shown) on the surface of the substrate 10 and the chips T1 to T4, respectively, and a seal filled in a gap between the chips T1 and the chips T2 and the like. A stopper 50 is provided.
　本実施形態においては、複数の支持片Ｄｃと、チップＴ２と、支持片ＤｃとチップＴ２との間に位置する接着剤片Ｔｃとによって基板１０上にドルメン構造が構成されている。チップＴ１は、接着剤片Ｔｃと離間している。支持片Ｄｃの厚さを適宜設定することで、チップＴ１の上面と基板１０とを接続するワイヤｗのためのスペースを確保することができる。チップＴ１が接着剤片Ｔｃと離間していることで、チップＴ１と接続されるワイヤｗの上部がチップＴ２に接することによるワイヤｗのショートを防ぐことができる。また、チップＴ２と接する接着剤片Ｔｃにワイヤを埋め込む必要性がないため、接着剤片Ｔｃを薄くできるという利点がある。 In the present embodiment, a dolmen structure is formed on the substrate 10 by a plurality of support pieces Dc, a chip T2, and an adhesive piece Tc located between the support piece Dc and the chip T2. The chip T1 is separated from the adhesive piece Tc. By appropriately setting the thickness of the support piece Dc, it is possible to secure a space for the wire w connecting the upper surface of the chip T1 and the substrate 10. Since the tip T1 is separated from the adhesive piece Tc, it is possible to prevent a short circuit of the wire w due to the upper portion of the wire w connected to the tip T1 coming into contact with the tip T2. Further, since it is not necessary to embed the wire in the adhesive piece Tc in contact with the chip T2, there is an advantage that the adhesive piece Tc can be thinned.
　図１に示すように、チップＴ１とチップＴ２の間の接着剤片Ｔｃは、チップＴ２におけるチップＴ１と対面する領域Ｒを覆うとともに、領域ＲからチップＴ２の周縁側にまで連続的に延在している。つまり、一つの接着剤片Ｔｃが、チップＴ２の領域Ｒを覆うとともに、チップＴ２と複数の支持片の間に介在し、これらを接着している。なお、図１には、接着剤片ＴｃがチップＴ２の一方の面（下面）の全体を覆うように設けられている態様を図示した。しかし、接着剤片Ｔｃは、半導体装置１００の製造過程において収縮することがあり得るため、チップＴ２の一方の面（下面）の全体を実質的に覆っていればよく、例えば、チップＴ２の周縁の一部に接着剤片Ｔｃで覆われていない箇所があってもよい。図１におけるチップＴ２の下面はチップの裏面に相当する。近年のチップの裏面は凹凸が形成されていることが多い。チップＴ２の裏面の実質的全体が接着剤片Ｔｃで覆われていることで、チップＴ２にクラック又は割れが生じることを抑制できる。 As shown in FIG. 1, the adhesive piece Tc between the chip T1 and the chip T2 covers the region R of the chip T2 facing the chip T1 and continuously extends from the region R to the peripheral side of the chip T2. doing. That is, one adhesive piece Tc covers the region R of the chip T2, intervenes between the chip T2 and the plurality of support pieces, and adheres them. Note that FIG. 1 illustrates an embodiment in which the adhesive piece Tc is provided so as to cover the entire one surface (lower surface) of the chip T2. However, since the adhesive piece Tc may shrink in the manufacturing process of the semiconductor device 100, it suffices to substantially cover the entire one surface (lower surface) of the chip T2, for example, the peripheral edge of the chip T2. There may be a part not covered with the adhesive piece Tc. The lower surface of the chip T2 in FIG. 1 corresponds to the back surface of the chip. In recent years, the back surface of chips is often uneven. Since substantially the entire back surface of the chip T2 is covered with the adhesive piece Tc, it is possible to prevent the chip T2 from cracking or cracking.
　基板１０は、有機基板であってもよく、リードフレーム等の金属基板であってもよい。基板１０は、半導体装置１００の反りを抑制する観点から、基板１０の厚さは、例えば、９０～３００μｍであり、９０～２１０μｍであってもよい。 The substrate 10 may be an organic substrate or a metal substrate such as a lead frame. From the viewpoint of suppressing the warp of the semiconductor device 100, the thickness of the substrate 10 is, for example, 90 to 300 μm, and may be 90 to 210 μm.
　チップＴ１は、例えば、コントローラーチップであり、接着剤片Ｔ１ｃによって基板１０に接着され且つワイヤｗによって基板１０と電気的に接続されている。平面視におけるチップＴ１の形状は、例えば矩形（正方形又は長方形）である。チップＴ１の一辺の長さは、例えば、５ｍｍ以下であり、２～５ｍｍ又は１～５ｍｍであってもよい。チップＴ１の厚さは、例えば、１０～１５０μｍであり、２０～１００μｍであってもよい。 The chip T1 is, for example, a controller chip, which is adhered to the substrate 10 by the adhesive piece T1c and electrically connected to the substrate 10 by the wire w. The shape of the chip T1 in a plan view is, for example, a rectangle (square or rectangle). The length of one side of the chip T1 is, for example, 5 mm or less, and may be 2 to 5 mm or 1 to 5 mm. The thickness of the chip T1 is, for example, 10 to 150 μm, and may be 20 to 100 μm.
　チップＴ２は、例えば、メモリチップであり、接着剤片Ｔｃを介して支持片Ｄｃの上に接着されている。平面視でチップＴ２は、チップＴ１よりも大きいサイズを有する。平面視におけるチップＴ２の形状は、例えば矩形（正方形又は長方形）である。チップＴ２の一辺の長さは、例えば、２０ｍｍ以下であり、４～２０ｍｍ又は４～１２ｍｍであってもよい。チップＴ２の厚さは、例えば、１０～１７０μｍであり、２０～１２０μｍであってもよい。なお、チップＴ３，Ｔ４も、例えば、メモリチップであり、接着剤片Ｔｃを介してチップＴ２の上に接着されている。チップＴ３，Ｔ４の一辺の長さは、チップＴ２と同様であればよく、チップＴ３，Ｔ４の厚さもチップＴ２と同様であればよい。 The chip T2 is, for example, a memory chip, and is adhered onto the support piece Dc via the adhesive piece Tc. In plan view, the chip T2 has a larger size than the chip T1. The shape of the chip T2 in a plan view is, for example, a rectangle (square or rectangle). The length of one side of the chip T2 is, for example, 20 mm or less, and may be 4 to 20 mm or 4 to 12 mm. The thickness of the chip T2 is, for example, 10 to 170 μm, and may be 20 to 120 μm. The chips T3 and T4 are also memory chips, for example, and are adhered onto the chip T2 via an adhesive piece Tc. The length of one side of the chips T3 and T4 may be the same as that of the chip T2, and the thickness of the chips T3 and T4 may be the same as that of the chip T2.
　支持片Ｄｃは、チップＴ１の周囲に空間を形成するスペーサーの役割を果たす。支持片Ｄｃは、熱硬化性樹脂組成物の硬化物からなる。なお、図２（ａ）に示すように、チップＴ１の両側の離れた位置に、二つの支持片Ｄｃ（形状：長方形）を配置してもよいし、図２（ｂ）に示すように、チップＴ１の角に対応する位置にそれぞれ一つの支持片Ｄｃ（形状：正方形、計４個）を配置してもよい。平面視における支持片Ｄｃの一辺の長さは、例えば、２０ｍｍ以下であり、１～２０ｍｍ又は１～１２ｍｍであってもよい。支持片Ｄｃの厚さ（高さ）は、例えば、１０～１８０μｍであり、２０～１２０μｍであってもよい。 The support piece Dc acts as a spacer that forms a space around the chip T1. The support piece Dc is made of a cured product of a thermosetting resin composition. As shown in FIG. 2A, two support pieces Dc (shape: rectangle) may be arranged at positions separated from each other on both sides of the chip T1, or as shown in FIG. 2B. One support piece Dc (shape: square, total of four) may be arranged at a position corresponding to the corner of the chip T1. The length of one side of the support piece Dc in a plan view is, for example, 20 mm or less, and may be 1 to 20 mm or 1 to 12 mm. The thickness (height) of the support piece Dc is, for example, 10 to 180 μm, and may be 20 to 120 μm.
（支持片の作製方法）
　支持片の作製方法の一例について説明する。なお、図１に示す支持片Ｄｃは熱硬化性樹組成物が硬化した後のものである。一方、支持片Ｄａは熱硬化性樹組成物が完全に硬化する前の状態のものである（例えば、図５（ｂ）参照）。 (Method of manufacturing support piece)
An example of a method for producing the support piece will be described. The support piece Dc shown in FIG. 1 is after the thermosetting tree composition has been cured. On the other hand, the support piece Da is in a state before the thermosetting tree composition is completely cured (see, for example, FIG. 5B).
　まず、図３（ａ）及び図３（ｂ）に示す支持片形成用積層フィルム２０（以下、場合により「積層フィルム２０」という。）を準備する。積層フィルム２０は、基材フィルム１と、粘着層２と、支持片形成用フィルムＤとを備える。基材フィルム１は、例えば、ポリエチレンテレフタレートフィルム（ＰＥＴフィルム）である。粘着層２は、パンチング等によって円形に形成されている（図３（ａ）参照）。粘着層２は、紫外線硬化型の粘着剤からなる。すなわち、粘着層２は紫外線が照射されることによって粘着性が低下する性質を有する。支持片形成用フィルムＤは、パンチング等によって円形に形成されており、粘着層２よりも小さい直径を有する（図３（ａ）参照）。支持片形成用フィルムＤは、熱硬化性樹脂組成物からなる。 First, the laminated film 20 for forming a support piece (hereinafter, sometimes referred to as "laminated film 20") shown in FIGS. 3 (a) and 3 (b) is prepared. The laminated film 20 includes a base film 1, an adhesive layer 2, and a support piece forming film D. The base film 1 is, for example, a polyethylene terephthalate film (PET film). The adhesive layer 2 is formed in a circular shape by punching or the like (see FIG. 3A). The adhesive layer 2 is made of an ultraviolet curable adhesive. That is, the adhesive layer 2 has a property that the adhesiveness is lowered by being irradiated with ultraviolet rays. The support piece forming film D is formed in a circular shape by punching or the like, and has a diameter smaller than that of the adhesive layer 2 (see FIG. 3A). The support piece forming film D is made of a thermosetting resin composition.
　支持片形成用フィルムＤを構成する熱硬化性樹脂組成物は、半硬化（Ｂステージ）状態を経て、その後の硬化処理によって完全硬化物（Ｃステージ）状態となり得るものである。熱硬化性樹脂組成物は、エポキシ樹脂と、硬化剤と、エラストマ（例えば、アクリル樹脂）とを含み、必要に応じて、無機フィラー及び硬化促進剤等を更に含む。支持片形成用フィルムＤを構成する熱硬化性樹脂組成物の詳細については後述する。 The thermosetting resin composition constituting the support piece forming film D can be in a semi-cured (B stage) state and then in a completely cured product (C stage) state by a subsequent curing treatment. The thermosetting resin composition contains an epoxy resin, a curing agent, and an elastomer (for example, an acrylic resin), and further contains an inorganic filler, a curing accelerator, and the like, if necessary. Details of the thermosetting resin composition constituting the support piece forming film D will be described later.
　積層フィルム２０は、例えば、基材フィルム１とその表面上に粘着層２とを有する第１の積層フィルムと、カバーフィルム３とその表面上に支持片形成用フィルムＤとを有する第２の積層フィルムとを貼り合わせることによって作製することができる（図４参照）。第１の積層フィルムは、基材フィルム１の表面上に粘着層を塗工によって形成する工程と、粘着層をパンチング等によって所定の形状（例えば、円形）に加工する工程を経て得られる。第２の積層フィルムは、カバーフィルム３（例えば、ＰＥＴフィルム又はポリエチレンフィルム）の表面上に支持片形成用フィルムを塗工によって形成する工程と、支持片形成用フィルムをパンチング等によって所定の形状（例えば、円形）に加工する工程を経て得られる。積層フィルム２０を使用するに際し、カバーフィルム３は適当なタイミングで剥がされる。 The laminated film 20 is, for example, a second laminated film having a base film 1 and an adhesive layer 2 on the surface thereof, and a cover film 3 and a support piece forming film D on the surface thereof. It can be produced by laminating with a film (see FIG. 4). The first laminated film is obtained through a step of forming an adhesive layer on the surface of the base film 1 by coating and a step of processing the adhesive layer into a predetermined shape (for example, a circle) by punching or the like. The second laminated film has a step of forming a support piece forming film on the surface of the cover film 3 (for example, PET film or polyethylene film) by coating, and a predetermined shape (for example, by punching the support piece forming film). For example, it is obtained through a process of processing into a circular shape. When using the laminated film 20, the cover film 3 is peeled off at an appropriate timing.
　図５（ａ）に示されたように、積層フィルム２０にダイシングリングＤＲを貼り付ける。すなわち、積層フィルム２０の粘着層２にダイシングリングＤＲを貼り付け、ダイシングリングＤＲの内側に支持片形成用フィルムＤが配置された状態にする。支持片形成用フィルムＤをダイシングによって個片化する（図５（ｂ）参照）。これにより、支持片形成用フィルムＤから多数の支持片Ｄａが得られる。その後、粘着層２に対して紫外線を照射することにより、粘着層２と支持片Ｄａとの間の粘着力を低下させる。紫外線照射後、図５（ｃ）に示されるように、基材フィルム１をエキスパンドすることで、支持片Ｄａを互いに離間させる。図５（ｄ）に示されるように、支持片Ｄａを突き上げ治具４２で突き上げることによって粘着層２から支持片Ｄａを剥離させるとともに、吸引コレット４４で吸引して支持片Ｄａをピックアップする。なお、ダイシング前の支持片形成用フィルムＤ又はピックアップ前の支持片Ｄａを加熱することによって、熱硬化性樹脂の硬化反応を進行させておいてもよい。ピックアップする際に支持片Ｄａが適度に硬化していることで優れたピックアップ性を達成し得る。個片化のための切り込みは支持片形成用フィルムＤの外縁まで形成されていることが好ましい。支持片形成用フィルムＤの直径は、例えば、３００～３１０ｍｍ又は３００～３０５ｍｍであってもよい。支持片形成用フィルムＤの平面視における形状は、図３（ａ）に示す円形に限られず、矩形（正方形又は長方形）であってもよい。 As shown in FIG. 5A, the dicing ring DR is attached to the laminated film 20. That is, the dicing ring DR is attached to the adhesive layer 2 of the laminated film 20, and the support piece forming film D is arranged inside the dicing ring DR. The support piece forming film D is individualized by dicing (see FIG. 5B). As a result, a large number of support pieces Da can be obtained from the support piece forming film D. After that, the adhesive layer 2 is irradiated with ultraviolet rays to reduce the adhesive force between the adhesive layer 2 and the support piece Da. After the irradiation with ultraviolet rays, as shown in FIG. 5C, the base film 1 is expanded to separate the support pieces Da from each other. As shown in FIG. 5D, the support piece Da is peeled off from the adhesive layer 2 by pushing up the support piece Da with the push-up jig 42, and the support piece Da is picked up by suction with the suction collet 44. The curing reaction of the thermosetting resin may be allowed to proceed by heating the support piece forming film D before dicing or the support piece Da before picking up. Excellent pickup performance can be achieved by appropriately curing the support piece Da when picking up. It is preferable that the notch for individualization is formed up to the outer edge of the support piece forming film D. The diameter of the support piece forming film D may be, for example, 300 to 310 mm or 300 to 305 mm. The shape of the support piece forming film D in a plan view is not limited to the circle shown in FIG. 3A, and may be a rectangle (square or rectangle).
（半導体装置の製造方法）
　半導体装置１００の製造方法について説明する。本実施形態に係る製造方法は、以下の（Ａ）～（Ｈ）の工程を含む。
（Ａ）積層フィルム２０を準備する工程（図４参照）
（Ｂ）支持片形成用フィルムＤを個片化することによって、粘着層２の表面上に複数の支持片Ｄａを形成する工程（図５（ｂ）参照）
（Ｃ）粘着層２から支持片Ｄａをピックアップする工程（図５（ｄ）参照）
（Ｄ）基板１０上に第一のチップＴ１を配置する工程
（Ｅ）基板１０上であって第一のチップＴ１の周囲に複数の支持片Ｄａを配置する工程（図６参照）
（Ｆ）第二のチップＴ２と、第二のチップＴ２の一方の面上に設けられた接着剤片Ｔａとを備える接着剤片付きチップＴ２ａを準備する工程（図７参照）
（Ｇ）複数の支持片Ｄｃの表面上に接着剤片付きチップＴ２ａを配置することによってドルメン構造を構築する工程（図８参照）
（Ｈ）チップＴ１とチップＴ２との隙間等を封止材５０で封止する工程（図１参照） (Manufacturing method of semiconductor device)
A method of manufacturing the semiconductor device 100 will be described. The manufacturing method according to this embodiment includes the following steps (A) to (H).
(A) Step of preparing laminated film 20 (see FIG. 4)
(B) A step of forming a plurality of support pieces Da on the surface of the adhesive layer 2 by individualizing the support piece forming film D (see FIG. 5B).
(C) A step of picking up the support piece Da from the adhesive layer 2 (see FIG. 5D).
(D) Step of arranging the first chip T1 on the substrate 10 (E) Step of arranging a plurality of support pieces Da on the substrate 10 around the first chip T1 (see FIG. 6).
(F) A step of preparing a chip T2a with an adhesive piece, which includes a second chip T2 and an adhesive piece Ta provided on one surface of the second chip T2 (see FIG. 7).
(G) A step of constructing a dolmen structure by arranging a chip T2a with an adhesive piece on the surface of a plurality of support pieces Dc (see FIG. 8).
(H) A step of sealing the gap between the chip T1 and the chip T2 with the sealing material 50 (see FIG. 1).
　（Ａ）～（Ｃ）工程は、複数の支持片Ｄａを作製するプロセスであり、説明済みである。（Ｄ）～（Ｈ）工程は、複数の支持片Ｄａを使用してドルメン構造を基板１０上に構築していくプロセスである。以下、図６～８を参照しながら、（Ｄ）～（Ｈ）工程について説明する。 The steps (A) to (C) are processes for producing a plurality of support pieces Da, and have already been described. The steps (D) to (H) are processes in which a dolmen structure is constructed on the substrate 10 by using a plurality of support pieces Da. Hereinafter, the steps (D) to (H) will be described with reference to FIGS. 6 to 8.
［（Ｄ）工程］
　（Ｄ）工程は、基板１０上に第一のチップＴ１を配置する工程である。例えば、まず、基板１０上の所定の位置に接着剤層Ｔ１ｃを介してチップＴ１を配置する。その後、チップＴ１はワイヤｗで基板１０と電気的に接続される。（Ｄ）工程は、（Ｅ）工程よりも前に行われる工程であってよく、（Ａ）工程よりも前、（Ａ）工程と（Ｂ）工程の間、（Ｂ）工程と（Ｃ）工程の間、又は（Ｃ）工程と（Ｅ）工程の間であってもよい。 [Step (D)]
The step (D) is a step of arranging the first chip T1 on the substrate 10. For example, first, the chip T1 is arranged at a predetermined position on the substrate 10 via the adhesive layer T1c. After that, the chip T1 is electrically connected to the substrate 10 by the wire w. The step (D) may be a step performed before the step (E), and before the step (A), between the steps (A) and (B), the steps (B) and (C). It may be between steps, or between steps (C) and (E).
［（Ｅ）工程］
　（Ｅ）工程は、基板１０上であって第一のチップＴ１の周囲に複数の支持片Ｄａを配置する工程である。この工程を経て、図６に示す構造体３０が作製される。構造体３０は、基板１０と、その表面上に配置されたチップＴ１と、複数の支持片Ｄａとを備える。支持片Ｄａの配置は圧着処理によって行えばよい。圧着処理は、例えば、８０～１８０℃、０．０１～０．５０ＭＰａの条件で、０．５～３．０秒間にわたって実施することが好ましい。なお、支持片Ｄａは（Ｅ）工程の時点で完全に硬化して支持片Ｄｃとなっていてもよく、この時点では完全硬化していなくてもよい。支持片Ｄａは（Ｇ）工程の開始前の時点で完全硬化して支持片Ｄｃとなっていることが好ましい。 [Step (E)]
The step (E) is a step of arranging a plurality of support pieces Da on the substrate 10 around the first chip T1. Through this step, the structure 30 shown in FIG. 6 is produced. The structure 30 includes a substrate 10, a chip T1 arranged on the surface thereof, and a plurality of support pieces Da. The support piece Da may be arranged by crimping. The crimping treatment is preferably carried out, for example, under the conditions of 80 to 180 ° C. and 0.01 to 0.50 MPa for 0.5 to 3.0 seconds. The support piece Da may be completely cured at the time of the step (E) to become the support piece Dc, and may not be completely cured at this time. It is preferable that the support piece Da is completely cured to become the support piece Dc before the start of the step (G).
［（Ｆ）工程］
　（Ｆ）工程は、図７に示す接着剤片付きチップＴ２ａを準備する工程である。接着剤片付きチップＴ２ａは、チップＴ２と、その一方の表面に設けられた接着剤片Ｔａとを備える。接着剤片付きチップＴ２ａは、例えば、半導体ウェハ及びダイシング・ダイボンディング一体型フィルムを使用し、ダイシング工程及びピックアップ工程を経て得ることができる。 [Step (F)]
The step (F) is a step of preparing the adhesive chip T2a shown in FIG. 7. The adhesive piece T2a includes a chip T2 and an adhesive piece Ta provided on the surface of one of the chips T2. The chip T2a with an adhesive piece can be obtained through a dicing step and a pick-up step using, for example, a semiconductor wafer and a dicing / die bonding integrated film.
［（Ｇ）工程］
　（Ｇ）工程は、複数の支持片Ｄｃの上面に接着剤片Ｔａが接するように、チップＴ１の上方に接着剤片付きチップＴ２ａを配置する工程である。具体的には、支持片Ｄｃの上面に接着剤片Ｔａを介してチップＴ２を圧着する。この圧着処理は、例えば、８０～１８０℃、０．０１～０．５０ＭＰａの条件で、０．５～３．０秒間にわたって実施することが好ましい。次に、加熱によって接着剤片Ｔａを硬化させる。この硬化処理は、例えば、６０～１７５℃、０．０１～１．０ＭＰａの条件で、５分間以上にわたって実施することが好ましい。これにより、接着剤片Ｔａが硬化して接着剤片Ｔｃとなる。この工程を経て、基板１０上にドルメン構造が構築される（図８参照）。チップＴ１が接着剤片付きチップＴ２ａと離間していることで、ワイヤｗの上部がチップＴ２に接することによるワイヤｗのショートを防ぐことができる。また、チップＴ２と接する接着剤片Ｔａにワイヤを埋め込む必要性がないため、接着剤片Ｔａを薄くできるという利点がある。 [(G) step]
The step (G) is a step of arranging the chip T2a with the adhesive piece above the chip T1 so that the adhesive piece Ta is in contact with the upper surface of the plurality of support pieces Dc. Specifically, the chip T2 is crimped to the upper surface of the support piece Dc via the adhesive piece Ta. This crimping treatment is preferably carried out for 0.5 to 3.0 seconds under the conditions of, for example, 80 to 180 ° C. and 0.01 to 0.50 MPa. Next, the adhesive piece Ta is cured by heating. This curing treatment is preferably carried out for 5 minutes or more under the conditions of, for example, 60 to 175 ° C. and 0.01 to 1.0 MPa. As a result, the adhesive piece Ta is cured to become the adhesive piece Tc. Through this step, a dolmen structure is constructed on the substrate 10 (see FIG. 8). Since the tip T1 is separated from the tip T2a with the adhesive piece, it is possible to prevent the wire w from being short-circuited due to the upper portion of the wire w coming into contact with the tip T2. Further, since it is not necessary to embed the wire in the adhesive piece Ta in contact with the chip T2, there is an advantage that the adhesive piece Ta can be thinned.
　（Ｇ）工程後であって（Ｈ）工程前に、チップＴ２の上に接着剤片を介してチップＴ３を配置し、更に、チップＴ３の上に接着剤片を介してチップＴ４を配置する。接着剤片は上述の接着剤片Ｔａと同様の熱硬化性樹脂組成物であればよく、加熱硬化によって接着剤片Ｔｃとなる（図１参照）。他方、チップＴ２，Ｔ３，Ｔ４と基板１０とをワイヤｗで電気的にそれぞれ接続する。なお、チップＴ１の上方に積層するチップの数は本実施形態の三つに限定されず、適宜設定すればよい。 After the step (G) and before the step (H), the chip T3 is placed on the chip T2 via the adhesive piece, and further, the chip T4 is placed on the chip T3 via the adhesive piece. .. The adhesive piece may be any thermosetting resin composition similar to the above-mentioned adhesive piece Ta, and becomes an adhesive piece Tc by heat curing (see FIG. 1). On the other hand, the chips T2, T3 and T4 and the substrate 10 are electrically connected by wires w. The number of chips stacked above the chip T1 is not limited to the three in this embodiment, and may be appropriately set.
［（Ｈ）工程］
　（Ｈ）工程は、チップＴ１とチップＴ２との隙間等を封止材５０で封止する工程である。この工程を経て図１に示す半導体装置１００が完成する。 [Step (H)]
The step (H) is a step of sealing the gap between the chip T1 and the chip T2 with the sealing material 50. Through this step, the semiconductor device 100 shown in FIG. 1 is completed.
（支持片形成用フィルムを構成する熱硬化性樹脂組成物）
　支持片形成用フィルムＤを構成する熱硬化性樹脂組成物は、上述のとおり、エポキシ樹脂と、硬化剤と、エラストマとを含み、必要に応じて、無機フィラー及び硬化促進剤等を更に含む。本発明者らの検討によると、支持片Ｄａ及び硬化後の支持片Ｄｃは以下の特性を有することが好ましい。
・特性１：基板１０の所定の位置に支持片Ｄａを熱圧着したとき位置ずれが生じにくいこと（１２０℃における支持片Ｄａの溶融粘度が、例えば、４３００～５００００Ｐａ・ｓ又は５０００～４００００Ｐａ・ｓであること）
・特性２：半導体装置１００内において支持片Ｄｃが応力緩和性を発揮すること（熱硬化性樹脂組成物がエラストマ（ゴム成分）を含むこと）
・特性３：接着剤片付きチップの接着剤片Ｔｃとの接着強度が十分に高いこと（接着剤片Ｔｃに対する支持片Ｄｃのダイシェア強度が、例えば、２．０～７．０Ｍｐａ又は３．０～６．０Ｍｐａであること）
・特性４：硬化に伴う収縮率が十分に小さいこと
・特性５：ピックアップ工程においてカメラによる支持片Ｄａの視認性が良いこと（熱硬化性樹脂組成物が、例えば、着色料を含んでいること）
・特性６：支持片Ｄｃが十分な機械的強度を有すること (Thermosetting resin composition constituting the support piece forming film)
As described above, the thermosetting resin composition constituting the support piece forming film D contains an epoxy resin, a curing agent, and an elastomer, and further contains an inorganic filler, a curing accelerator, and the like, if necessary. According to the studies by the present inventors, it is preferable that the support piece Da and the support piece Dc after curing have the following characteristics.
-Characteristic 1: When the support piece Da is thermocompression bonded to a predetermined position on the substrate 10, the position shift is unlikely to occur (the melt viscosity of the support piece Da at 120 ° C. is, for example, 4300 to 50,000 Pa · s or 5000 to 40,000 Pa · s. To be)
-Characteristic 2: The support piece Dc exhibits stress relaxation property in the semiconductor device 100 (the thermosetting resin composition contains an elastomer (rubber component)).
-Characteristic 3: The adhesive strength of the chip with the adhesive piece to the adhesive piece Tc is sufficiently high (the die share strength of the support piece Dc with respect to the adhesive piece Tc is, for example, 2.0 to 7.0 Mpa or 3.0 to 3.0 to. (Being 6.0 Mpa)
-Characteristic 4: The shrinkage rate due to curing is sufficiently small.-Characteristic 5: The visibility of the support piece Da by the camera in the pickup process is good (the thermosetting resin composition contains, for example, a colorant). )
-Characteristic 6: The support piece Dc has sufficient mechanical strength.
［エポキシ樹脂］
　エポキシ樹脂は、硬化して接着作用を有するものであれば特に限定されない。ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、ビスフェノールＳ型エポキシ樹脂等の二官能エポキシ樹脂、フェノールノボラック型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂等のノボラック型エポキシ樹脂などを使用することができる。また、多官能エポキシ樹脂、グリシジルアミン型エポキシ樹脂、複素環含有エポキシ樹脂または脂環式エポキシ樹脂など、一般に知られているものを適用することができる。これらは一種を単独で使用してもよいし、二種以上を併用してもよい。 [Epoxy resin]
The epoxy resin is not particularly limited as long as it is cured and has an adhesive action. Bifunctional epoxy resins such as bisphenol A type epoxy resin, bisphenol F type epoxy resin, and bisphenol S type epoxy resin, novolak type epoxy resins such as phenol novolac type epoxy resin and cresol novolac type epoxy resin can be used. Further, generally known ones such as a polyfunctional epoxy resin, a glycidylamine type epoxy resin, a heterocyclic epoxy resin, and an alicyclic epoxy resin can be applied. These may be used alone or in combination of two or more.
［硬化剤］
　硬化剤として、例えば、フェノール樹脂、エステル化合物、芳香族アミン、脂肪族アミン及び酸無水物が挙げられる。これらのうち、高いダイシェア強度を達成する観点から、フェノール樹脂が好ましい。フェノール樹脂の市販品として、例えば、ＤＩＣ（株）製のＬＦ－４８７１（商品名、ＢＰＡノボラック型フェノール樹脂）、エア・ウォーター（株）製のＨＥ－１００Ｃ－３０（商品名、フェニルアラキル型フェノール樹脂）、ＤＩＣ（株）製のフェノライトＫＡ及びＴＤシリーズ、三井化学（株）製のミレックスＸＬＣ－シリーズとＸＬシリーズ（例えば、ミレックスＸＬＣ－ＬＬ）、エア・ウォーター（株）製のＨＥシリーズ（例えば、ＨＥ１００Ｃ－３０）、明和化成（株）製のＭＥＨＣ－７８００シリーズ（例えばＭＥＨＣ－７８００－４Ｓ）、ＪＥＦケミカル（株）のＪＤＰＰシリーズが挙げられる。これらは一種を単独で使用してもよいし、二種以上を併用してもよい。 [Hardener]
Examples of the curing agent include phenolic resins, ester compounds, aromatic amines, aliphatic amines and acid anhydrides. Of these, phenolic resins are preferred from the perspective of achieving high die shear strength. Commercially available phenolic resins include, for example, LF-4871 (trade name, BPA novolac type phenolic resin) manufactured by DIC Co., Ltd. and HE-100C-30 (trade name, phenylarakil type) manufactured by Air Water Inc. Phenolic resin), Phenolite KA and TD series manufactured by DIC Co., Ltd., Millex XLC-series and XL series manufactured by Mitsui Chemicals Co., Ltd. (for example, Millex XLC-LL), HE series manufactured by Air Water Inc. (For example, HE100C-30), MEHC-7800 series manufactured by Meiwa Kasei Co., Ltd. (for example, MEHC-7800-4S), and JDPP series manufactured by JEF Chemical Co., Ltd. can be mentioned. These may be used alone or in combination of two or more.
　エポキシ樹脂とフェノール樹脂の配合量は、高いダイシェア強度を達成する観点から、それぞれエポキシ当量と水酸基当量の当量比が０．６～１．５であることが好ましく、０．７～１．４であることがより好ましく、０．８～１．３であることが更に好ましい。配合比が上記範囲内であることで、硬化性及び流動性の両方を十分に高水準に達成しやすい。 The blending amount of the epoxy resin and the phenol resin is preferably such that the equivalent ratio of the epoxy equivalent and the hydroxyl group equivalent is 0.6 to 1.5, and is 0.7 to 1.4, respectively, from the viewpoint of achieving high die shear strength. More preferably, it is more preferably 0.8 to 1.3. When the compounding ratio is within the above range, it is easy to achieve both curability and fluidity at a sufficiently high level.
［エラストマ］
　エラストマとして、例えば、アクリル樹脂、ポリエステル樹脂、ポリアミド樹脂、ポリイミド樹脂、シリコーン樹脂、ポリブタジエン、アクリロニトリル、エポキシ変性ポリブタジエン、無水マレイン酸変性ポリブタジエン、フェノール変性ポリブタジエン及びカルボキシ変性アクリロニトリルが挙げられる。 [Elastomer]
Examples of the elastoma include acrylic resin, polyester resin, polyamide resin, polyimide resin, silicone resin, polybutadiene, acrylonitrile, epoxy-modified polybutadiene, maleic anhydride-modified polybutadiene, phenol-modified polybutadiene and carboxy-modified acrylonitrile.
　高いダイシェア強度を達成する観点から、エラストマとしてアクリル系樹脂が好ましく、更に、グリシジルアクリレート又はグリシジルメタクリレート等のエポキシ基又はグリシジル基を架橋性官能基として有する官能性モノマーを重合して得たエポキシ基含有（メタ）アクリル共重合体等のアクリル系樹脂がより好ましい。アクリル系樹脂のなかでもエポキシ基含有（メタ）アクリル酸エステル共重合体及びエポキシ基含有アクリルゴムが好ましく、エポキシ基含有アクリルゴムがより好ましい。エポキシ基含有アクリルゴムは、アクリル酸エステルを主成分とし、主として、ブチルアクリレートとアクリロニトリル等の共重合体、エチルアクリレートとアクリロニトリル等の共重合体などからなる、エポキシ基を有するゴムである。なお、アクリル系樹脂は、エポキシ基だけでなく、アルコール性又はフェノール性水酸基、カルボキシル基等の架橋性官能基を有していてもよい。 From the viewpoint of achieving high die shear strength, an acrylic resin is preferable as the elastoma, and further, an epoxy group-containing epoxy group obtained by polymerizing an epoxy group such as glycidyl acrylate or glycidyl methacrylate or a functional monomer having a glycidyl group as a crosslinkable functional group. Acrylic resins such as (meth) acrylic copolymers are more preferable. Among the acrylic resins, epoxy group-containing (meth) acrylic acid ester copolymers and epoxy group-containing acrylic rubbers are preferable, and epoxy group-containing acrylic rubbers are more preferable. The epoxy group-containing acrylic rubber is a rubber having an epoxy group, which is mainly composed of an acrylic acid ester as a main component, a copolymer such as butyl acrylate and acrylonitrile, and a copolymer such as ethyl acrylate and acrylonitrile. The acrylic resin may have not only an epoxy group but also a crosslinkable functional group such as an alcoholic or phenolic hydroxyl group or a carboxyl group.
　アクリル樹脂の市販品としては、ナガセケムテック（株）製のＳＧ－７０Ｌ、ＳＧ－７０８－６、ＷＳ－０２３　ＥＫ３０、ＳＧ－２８０　ＥＫ２３、ＳＧ－Ｐ３溶剤変更品（商品名、アクリルゴム、重量平均分子量：８０万、Ｔｇ：１２℃、溶剤はシクロヘキサノン）等が挙げられる。 Commercially available acrylic resin products include SG-70L, SG-708-6, WS-023 EK30, SG-280 EK23, SG-P3 solvent modified products (trade name, acrylic rubber, weight) manufactured by Nagase Chemtech Co., Ltd. Average molecular weight: 800,000, Tg: 12 ° C., solvent is cyclohexanone) and the like.
　アクリル樹脂のガラス転移温度（Ｔｇ）は、高いダイシェア強度を達成する観点から、－５０～５０℃であることが好ましく、－３０～３０℃であることがより好ましい。アクリル樹脂の重量平均分子量（Ｍｗ）は、高いダイシェア強度を達成する観点から、１０万～３００万であることが好ましく、５０万～２００万であることがより好ましい。ここで、Ｍｗは、ゲルパーミエーションクロマトグラフィー（ＧＰＣ）で測定し、標準ポリスチレンによる検量線を用いて換算した値を意味する。なお、分子量分布の狭いアクリル樹脂を用いることにより、高弾性の接着剤片を形成できる傾向にある。 The glass transition temperature (Tg) of the acrylic resin is preferably −50 to 50 ° C., more preferably −30 to 30 ° C. from the viewpoint of achieving high die shear strength. The weight average molecular weight (Mw) of the acrylic resin is preferably 100,000 to 3 million, more preferably 500,000 to 2 million, from the viewpoint of achieving high die share strength. Here, Mw means a value measured by gel permeation chromatography (GPC) and converted using a calibration curve using standard polystyrene. By using an acrylic resin having a narrow molecular weight distribution, a highly elastic adhesive piece tends to be formed.
　熱硬化性樹脂組成物に含まれるアクリル樹脂の量は、高いダイシェア強度を達成する観点から、エポキシ樹脂及びエポキシ樹脂硬化剤の合計１００質量部に対して１０～２００質量部であることが好ましく、２０～１００質量部であることがより好ましい。 The amount of the acrylic resin contained in the thermosetting resin composition is preferably 10 to 200 parts by mass with respect to 100 parts by mass of the total of the epoxy resin and the epoxy resin curing agent from the viewpoint of achieving high die shear strength. More preferably, it is 20 to 100 parts by mass.
［無機フィラー］
　無機フィラーとして、例えば、水酸化アルミニウム、水酸化マグネシウム、炭酸カルシウム、炭酸マグネシウム、ケイ酸カルシウム、ケイ酸マグネシウム、酸化カルシウム、酸化マグネシウム、酸化アルミニウム、窒化アルミニウム、ホウ酸アルミウィスカ、窒化ホウ素及び結晶性シリカ、非晶性シリカが挙げられる。これらは一種を単独で使用してもよいし、二種以上を併用してもよい。 [Inorganic filler]
Inorganic fillers include, for example, aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, aluminum oxide, aluminum nitride, aluminum borate whisker, boron nitride and crystalline. Examples include silica and amorphous silica. These may be used alone or in combination of two or more.
　無機フィラーの平均粒径は、高いダイシェア強度を達成する観点から、０．００５μｍ～１．０μｍが好ましく、０．０５～０．５μｍがより好ましい。無機フィラーの表面は、高いダイシェア強度を達成する観点から、化学修飾されていることが好ましい。表面を化学修飾する材料として適したものにシランカップリング剤が挙げられる。シランカップリング剤の官能基の種類として、例えば、ビニル基、アクリロイル基、エポキシ基、メルカプト基、アミノ基、ジアミノ基、アルコキシ基、エトキシ基が挙げられる。 The average particle size of the inorganic filler is preferably 0.005 μm to 1.0 μm, more preferably 0.05 to 0.5 μm, from the viewpoint of achieving high die shear strength. The surface of the inorganic filler is preferably chemically modified from the viewpoint of achieving high die shear strength. Silane coupling agents are suitable as materials for chemically modifying the surface. Examples of the types of functional groups of the silane coupling agent include vinyl group, acryloyl group, epoxy group, mercapto group, amino group, diamino group, alkoxy group and ethoxy group.
　高いダイシェア強度を達成する観点から、熱硬化性樹脂組成物の樹脂成分１００質量部に対して、無機フィラーの含有量は２０～２００質量部であることが好ましく、３０～１００質量部であることがより好ましい。 From the viewpoint of achieving high die shear strength, the content of the inorganic filler is preferably 20 to 200 parts by mass and 30 to 100 parts by mass with respect to 100 parts by mass of the resin component of the thermosetting resin composition. Is more preferable.
［硬化促進剤］
　硬化促進剤として、例えば、イミダゾール類及びその誘導体、有機リン系化合物、第二級アミン類、第三級アミン類、及び第四級アンモニウム塩が挙げられる。高いダイシェア強度を達成する観点から、イミダゾール系の化合物が好ましい。イミダゾール類としては、２－メチルイミダゾール、１－ベンジル－２－メチルイミダゾール、１－シアノエチル－２－フェニルイミダゾール、１－シアノエチルー２－メチルイミダゾール等が挙げられる。これらは一種を単独で使用してもよいし、二種以上を併用してもよい。 [Curing accelerator]
Examples of the curing accelerator include imidazoles and derivatives thereof, organophosphorus compounds, secondary amines, tertiary amines, and quaternary ammonium salts. From the viewpoint of achieving high die shear strength, imidazole-based compounds are preferable. Examples of the imidazoles include 2-methylimidazole, 1-benzyl-2-methylimidazole, 1-cyanoethyl-2-phenylimidazole, 1-cyanoethyl-2-methylimidazole and the like. These may be used alone or in combination of two or more.
　熱硬化性樹脂組成物における硬化促進剤の含有量は、高いダイシェア強度を達成する観点から、エポキシ樹脂及びエポキシ樹脂硬化剤の合計１００質量部に対して０．０４～３質量部が好ましく、０．０４～０．２質量部がより好ましい。 The content of the curing accelerator in the thermosetting resin composition is preferably 0.04 to 3 parts by mass with respect to 100 parts by mass in total of the epoxy resin and the epoxy resin curing agent from the viewpoint of achieving high die shear strength, and is 0. .04 to 0.2 parts by mass is more preferable.
＜第二実施形態＞
　図９は第二実施形態に係る半導体装置を模式的に示す断面図である。第一実施形態に係る半導体装置１００はチップＴ１が接着剤片Ｔｃと離間している態様であったのに対し、本実施形態に係る半導体装置２００はチップＴ１が接着剤片Ｔｃと接している。つまり、接着剤片Ｔｃは、チップＴ１の上面及び支持片Ｄｃの上面に接している。例えば、支持片形成用フィルムＤの厚さを適宜設定することで、チップＴ１の上面の位置と支持片Ｄｃの上面の位置を一致させることができる。 <Second embodiment>
FIG. 9 is a cross-sectional view schematically showing the semiconductor device according to the second embodiment. In the semiconductor device 100 according to the first embodiment, the chip T1 is separated from the adhesive piece Tc, whereas in the semiconductor device 200 according to the present embodiment, the chip T1 is in contact with the adhesive piece Tc. .. That is, the adhesive piece Tc is in contact with the upper surface of the chip T1 and the upper surface of the support piece Dc. For example, by appropriately setting the thickness of the support piece forming film D, the position of the upper surface of the chip T1 and the position of the upper surface of the support piece Dc can be matched.
　半導体装置２００においては、チップＴ１が基板１０に対し、ワイヤボンディングではなく、フリップチップ接続されている。なお、ワイヤｗが接着剤片Ｔａに埋め込まれる構成とすれば、基板１０にチップＴ１がワイヤボンディングされた態様であっても、チップＴ１が接着剤片Ｔｃと接した状態とすることができる。接着剤片ＴａはチップＴ２とともに接着剤片付きチップＴ２ａを構成するものである（図８参照）。 In the semiconductor device 200, the chip T1 is connected to the substrate 10 by a flip chip instead of wire bonding. If the wire w is embedded in the adhesive piece Ta, the chip T1 can be in contact with the adhesive piece Tc even when the chip T1 is wire-bonded to the substrate 10. The adhesive piece Ta constitutes the chip T2a with the adhesive piece together with the chip T2 (see FIG. 8).
　図９に示すように、チップＴ１とチップＴ２の間の接着剤片Ｔｃは、チップＴ２におけるチップＴ１と対面する領域Ｒを覆うとともに、領域ＲからチップＴ２の周縁側にまで連続的に延在している。この一つの接着剤片Ｔｃが、チップＴ２の領域Ｒを覆うとともに、チップＴ２と複数の支持片の間に介在し、これらを接着している。図９におけるチップＴ２の下面は裏面に相当する。上述のとおり、近年のチップの裏面は凹凸が形成されていることが多い。チップＴ２の裏面の実質的全体が接着剤片Ｔｃで覆われていることで、接着剤片ＴｃにチップＴ１の上面が接してもチップＴ２にクラック又は割れが生じることを抑制できる。 As shown in FIG. 9, the adhesive piece Tc between the chip T1 and the chip T2 covers the region R of the chip T2 facing the chip T1 and continuously extends from the region R to the peripheral side of the chip T2. doing. This one adhesive piece Tc covers the region R of the chip T2 and is interposed between the chip T2 and the plurality of support pieces to bond them. The lower surface of the chip T2 in FIG. 9 corresponds to the back surface. As described above, the back surface of recent chips is often formed with irregularities. Since substantially the entire back surface of the chip T2 is covered with the adhesive piece Tc, it is possible to prevent the chip T2 from cracking or cracking even if the upper surface of the chip T1 comes into contact with the adhesive piece Tc.
　以上、本開示の実施形態について詳細に説明したが、本発明は上記実施形態に限定されるものではない。例えば、上記実施形態においては、紫外線硬化型の粘着層２を有する積層フィルム２０を例示したが、粘着層２は感圧型であってもよい。 Although the embodiments of the present disclosure have been described in detail above, the present invention is not limited to the above embodiments. For example, in the above embodiment, the laminated film 20 having the ultraviolet curable adhesive layer 2 is illustrated, but the adhesive layer 2 may be a pressure sensitive type.
　上記実施形態においては、図３（ｂ）に示すように、熱硬化性樹脂層からなる支持片形成用フィルムＤを備える支持片形成用積層フィルム２０を例示したが、支持片形成用積層フィルムは、熱硬化性樹脂層と当該熱硬化性樹脂層よりも高い剛性を有する樹脂層又は金属層とを有する多層フィルムを備えたものであってもよい。図１０（ａ）に示す支持片形成用積層フィルム２０Ａは、熱硬化性樹脂層５と、熱硬化性樹脂層５よりも高い剛性を有する樹脂層６とを有する二層フィルムＤ２（支持片形成用フィルム）を有する。すなわち、支持片形成用積層フィルム２０Ａにおいては、粘着層２と最外面の樹脂層６との間に熱硬化性樹脂層５が配置されている。なお、熱硬化性樹脂層５は、第一実施形態に係る支持片形成用フィルムＤを構成する熱硬化性樹脂組成物からなる。樹脂層６の厚さは、例えば、５～１００μｍであり、１０～９０μｍ又は２０～８０μｍであってもよい。樹脂層６は、例えば、ポリイミド層である。熱硬化性樹脂層５は、樹脂層６と異なる材質からなるものである。 In the above embodiment, as shown in FIG. 3B, a support piece forming laminated film 20 including a support piece forming film D made of a thermosetting resin layer is illustrated, but the support piece forming laminated film 20 is illustrated. , It may be provided with a multilayer film having a thermosetting resin layer and a resin layer or a metal layer having higher rigidity than the thermosetting resin layer. The laminated film 20A for forming a support piece shown in FIG. 10A is a two-layer film D2 (support piece formation) having a thermosetting resin layer 5 and a resin layer 6 having a higher rigidity than the thermosetting resin layer 5. Film). That is, in the support piece forming laminated film 20A, the thermosetting resin layer 5 is arranged between the adhesive layer 2 and the outermost resin layer 6. The thermosetting resin layer 5 is made of a thermosetting resin composition constituting the support piece forming film D according to the first embodiment. The thickness of the resin layer 6 is, for example, 5 to 100 μm, and may be 10 to 90 μm or 20 to 80 μm. The resin layer 6 is, for example, a polyimide layer. The thermosetting resin layer 5 is made of a material different from that of the resin layer 6.
　二層フィルムＤ２の厚さに対する熱硬化性樹脂層５の厚さの比率は好ましくは０．１～０．８であり、より好ましくは０．２～０．７であり、更に好ましくは０．２～０．６である。この比率が０．１以上であることで、接着剤片５ｐ，５ｃがその役割（例えば、チップＴ２の支持及び樹脂片６ｐの位置ずれ防止）をより一層高度に果たすことができる。他方、比率が０．８以下であれば、樹脂片６ｐが十分な厚さを有するため、樹脂片６ｐがバネ板のような役割を果たし、より優れたピックアップ性を達成できる（図５（ｄ）参照）。これらの観点から、樹脂層６の厚さは、例えば、２０～８０μｍであり、２０～６０μｍであってもよい。熱硬化性樹脂層５の厚さは、例えば、５～１２０μｍであり、１０～６０μｍであってもよい。 The ratio of the thickness of the thermosetting resin layer 5 to the thickness of the bilayer film D2 is preferably 0.1 to 0.8, more preferably 0.2 to 0.7, and even more preferably 0. It is 2 to 0.6. When this ratio is 0.1 or more, the adhesive pieces 5p and 5c can play their roles (for example, supporting the chip T2 and preventing the resin piece 6p from being displaced) to a higher degree. On the other hand, when the ratio is 0.8 or less, since the resin piece 6p has a sufficient thickness, the resin piece 6p acts like a spring plate, and more excellent pick-up property can be achieved (FIG. 5 (d)). )reference). From these viewpoints, the thickness of the resin layer 6 is, for example, 20 to 80 μm, and may be 20 to 60 μm. The thickness of the thermosetting resin layer 5 is, for example, 5 to 120 μm, and may be 10 to 60 μm.
　図１０（ｂ）に示す支持片形成用積層フィルム２０Ｂは、熱硬化性樹脂層よりも高い剛性を有する樹脂層６と、樹脂層６を挟む二層の熱硬化性樹脂層５とを有する三層フィルムＤ３（支持片形成用フィルム）を有する。支持片形成用積層フィルム２０Ｂにおいては、粘着層２の表面上に三層フィルムＤ３が配置されている。熱硬化性樹脂層５は、樹脂層６と異なる材質からなるものである。 The laminated film 20B for forming a support piece shown in FIG. 10B has a resin layer 6 having a higher rigidity than a thermosetting resin layer and a two-layer thermosetting resin layer 5 sandwiching the resin layer 6. It has a layer film D3 (a film for forming a support piece). In the support piece forming laminated film 20B, the three-layer film D3 is arranged on the surface of the adhesive layer 2. The thermosetting resin layer 5 is made of a material different from that of the resin layer 6.
　支持片形成用積層フィルム２０Ａ，２０Ｂは、熱硬化性樹脂層５よりも高い剛性を有する樹脂層６を含むことで、ダイシングによって個片化された後において、熱硬化性樹脂層５の熱硬化処理を実施しなくても、優れたピックアップ性を達成し得る。支持片形成用積層フィルム２０Ａ，２０Ｂにおいて、樹脂層６の代わりに、熱硬化性樹脂層よりも高い金属層（例えば、銅層又はアルミニウム層）を採用してもよい。金属層の厚さは、例えば、５～１００μｍであり、１０～９０μｍ又は２０～８０μｍであってもよい。支持片形成用積層フィルム２０Ａ，２０Ｂが金属層を含むことで、優れたピックアップ性に加え、樹脂材料と金属材料の光学的なコントラストにより、ピックアップ工程において支持片の優れた視認性を達成し得る。 The laminated films 20A and 20B for forming support pieces include a resin layer 6 having a higher rigidity than the thermosetting resin layer 5, so that the thermosetting resin layer 5 is heat-cured after being individualized by dicing. Excellent pick-up performance can be achieved without performing processing. In the support piece forming laminated films 20A and 20B, a metal layer (for example, a copper layer or an aluminum layer) higher than the thermosetting resin layer may be adopted instead of the resin layer 6. The thickness of the metal layer is, for example, 5 to 100 μm and may be 10 to 90 μm or 20 to 80 μm. By including the metal layer in the laminated films 20A and 20B for forming the support piece, in addition to the excellent pick-up property, the optical contrast between the resin material and the metal material can achieve excellent visibility of the support piece in the pick-up process. ..
　三層フィルムＤ３の厚さに対する二つの熱硬化性樹脂層５，５の厚さの合計の比率は好ましくは０．１～０．９であり、より好ましくは０．２～０．８であり、更に好ましくは０．２～０．７である。この比率が上記範囲であることで、支持片の製造過程においてピックアップ性を実現し得る（図５（ｄ）参照）。すなわち、比率が０．１以上であることで、樹脂層６の代わりに金属層を採用した場合であっても、金属片（金属層が個片化されたもの）のエッジが粘着層２に入り込むことに起因して支持片のピックアップ性が低下することをより高度に抑制できる。他方、比率が０．９以下であれば、樹脂片（樹脂層６が個片化されたもの）又は金属片が十分な厚さを有するため、これらがバネ板のような役割を果たし、より優れたピックアップ性を達成できる。これらの観点から、樹脂層６又は金属層の厚さは、例えば、１０～８０μｍであり、２０～６０μｍであってもよい。熱硬化性樹脂層５（一層）の厚さは、例えば、５～１２０μｍであり、１０～６０μｍであってもよい。 The ratio of the total thickness of the two thermosetting resin layers 5 and 5 to the thickness of the three-layer film D3 is preferably 0.1 to 0.9, and more preferably 0.2 to 0.8. , More preferably 0.2 to 0.7. When this ratio is within the above range, pick-up property can be realized in the manufacturing process of the support piece (see FIG. 5D). That is, when the ratio is 0.1 or more, even when a metal layer is used instead of the resin layer 6, the edge of the metal piece (the metal layer is individualized) becomes the adhesive layer 2. It is possible to more highly suppress the deterioration of the pick-up property of the support piece due to the entry. On the other hand, when the ratio is 0.9 or less, the resin piece (the resin layer 6 is separated into individual pieces) or the metal piece has a sufficient thickness, so that they act like a spring plate, and more. Excellent pickup performance can be achieved. From these viewpoints, the thickness of the resin layer 6 or the metal layer is, for example, 10 to 80 μm, and may be 20 to 60 μm. The thickness of the thermosetting resin layer 5 (one layer) is, for example, 5 to 120 μm, and may be 10 to 60 μm.
　上記のフィルムＤ２，Ｄ３のように。支持片形成用フィルムが互いに異なる材質からなる複数の層を有することで、各層に機能を分担させることができ、フィルムの高機能化を図ることができる。かかる多層構造のフィルムを個片化することで、ドルメン構造により一層適した支持片Ｄａを作製し得る。 Like the above films D2 and D3. By having a plurality of layers made of different materials for the support piece forming film, the functions can be shared among the layers, and the functionality of the film can be improved. By individualizing the film having such a multilayer structure, a support piece Da more suitable for the dolmen structure can be produced.
　支持片形成用積層フィルム２０Ａは、例えば、以下の工程を経て製造することができる。
・基材フィルム１と、粘着層２と、熱硬化性樹脂層５とをこの順序で備える積層フィルムを準備する工程
・上記積層フィルムの表面に熱硬化性樹脂層５よりも高い剛性を有する樹脂層６又は金属層を貼り合わせる工程 The laminated film 20A for forming a support piece can be manufactured, for example, through the following steps.
-A step of preparing a laminated film including a base film 1, an adhesive layer 2, and a thermosetting resin layer 5 in this order.-A resin having a higher rigidity than the thermosetting resin layer 5 on the surface of the laminated film. Step of laminating layer 6 or metal layer
　以下、実施例により本開示について説明するが、本発明はこれらの実施例に限定されるものではない。 Hereinafter, the present disclosure will be described with reference to Examples, but the present invention is not limited to these Examples.
（ワニスＡの調製）
　以下の材料を使用して支持片形成用フィルムのためのワニスＡを調製した。
・エポキシ樹脂１：ＹＤＣＮ－７００－１０：（商品名、新日鉄住金化学（株）製、クレゾールノボラック型エポキシ樹脂、２５℃において固体）５．４質量部
・エポキシ樹脂２：ＹＤＦ－８１７０Ｃ：（商品名、新日鉄住金化学（株）製、液状ビスフェノールＦ型エポキシ樹脂、２５℃において液状）１６．２質量部
・フェノール樹脂（硬化剤）：ＬＦ－４８７１：（商品名、ＤＩＣ（株）製、ＢＰＡノボラック型フェノール樹脂）１３．３質量部
・無機フィラー：ＳＣ２０５０－ＨＬＧ：（商品名、（株）アドマテックス製、シリカフィラー分散液、平均粒径０．５０μｍ）４９．８質量部
・エラストマ：ＳＧ－Ｐ３溶剤変更品（商品名、ナガセケムテックス（株）製、アクリルゴム、重量平均分子量：８０万、Ｔｇ：１２℃、溶剤はシクロヘキサノン）１４．９質量部
・カップリング剤１：Ａ－１８９：（商品名、ＧＥ東芝（株）製、γ－メルカプトプロピルトリメトキシシラン）０．１質量部
・カップリング剤２：Ａ－１１６０：（商品名、ＧＥ東芝（株）製、γ－ウレイドプロピルトリエトキシシラン）０．３質量部
・硬化促進剤：キュアゾール２ＰＺ－ＣＮ：（商品名、四国化成工業（株）製、１－シアノエチル－２－フェニルイミダゾール）０．０５質量部
・溶媒：シクロヘキサン (Preparation of varnish A)
Varnish A for the support piece forming film was prepared using the following materials.
-Epoxy resin 1: YDCN-700-10: (trade name, manufactured by Nippon Steel & Sumitomo Metal Corporation, cresol novolac type epoxy resin, solid at 25 ° C) 5.4 parts by mass-Epoxy resin 2: YDF-8170C: (product Name, manufactured by Nippon Steel & Sumitomo Metal Chemical Co., Ltd., liquid bisphenol F type epoxy resin, liquid at 25 ° C) 16.2 parts by mass ・ Phenolic resin (hardener): LF-4871: (trade name, manufactured by DIC Co., Ltd., BPA) Novolac type phenol resin) 13.3 parts by mass ・ Inorganic filler: SC2050-HLG: (trade name, manufactured by Admatex Co., Ltd., silica filler dispersion, average particle size 0.50 μm) 49.8 parts by mass ・ Elastoma: SG -P3 solvent modified product (trade name, manufactured by Nagase ChemteX Corporation, acrylic rubber, weight average molecular weight: 800,000, Tg: 12 ° C., solvent is cyclohexanone) 14.9 parts by mass, coupling agent 1: A-189 : (Product name, GE Toshiba Co., Ltd., γ-mercaptopropyltrimethoxysilane) 0.1 part by mass ・ Coupling agent 2: A-1160: (Product name, GE Toshiba Co., Ltd., γ-ureidopropyl) Triethoxysilane) 0.3 parts by mass ・ Curing accelerator: Curesol 2PZ-CN: (trade name, manufactured by Shikoku Kasei Kogyo Co., Ltd., 1-cyanoethyl-2-phenylimidazole) 0.05 parts by mass ・ Solvent: Cyclohexane
（ワニスＢの調製）
　以下の材料を使用して支持片形成用フィルムのためのワニスＢを調製した。
・エポキシ樹脂：ＹＤＣＮ－７００－１０：（商品名、新日鉄住金化学（株）製、クレゾールノボラック型エポキシ樹脂、２５℃において固体）１３．２質量部
・フェノール樹脂（硬化剤）：ＨＥ－１００Ｃ－３０：（商品名、エア・ウォーター（株）製、フェニルアラキル型フェノール樹脂）１１．０質量部
・無機フィラー：アエロジルＲ９７２：（商品名、日本アエロジル（株）製、シリカ、平均粒径０．０１６μｍ）７．８質量部
・エラストマ：ＳＧ－Ｐ３溶剤変更品（商品名、ナガセケムテックス（株）製、アクリルゴム、重量平均分子量：８０万、Ｔｇ：１２℃、溶剤はシクロヘキサノン）６６．４質量部
・カップリング剤１：Ａ－１８９：（商品名、ＧＥ東芝（株）製、γ－メルカプトプロピルトリメトキシシラン）０．４質量部
・カップリング剤２：Ａ－１１６０：（商品名、ＧＥ東芝（株）製、γ－ウレイドプロピルトリエトキシシラン）１．１５質量部
・硬化促進剤：キュアゾール２ＰＺ－ＣＮ：（商品名、四国化成工業（株）製、１－シアノエチル－２－フェニルイミダゾール）０．０３質量部
・溶媒：シクロヘキサン (Preparation of varnish B)
Varnish B for the support piece forming film was prepared using the following materials.
-Epoxy resin: YDCN-700-10: (trade name, manufactured by Nippon Steel & Sumitomo Metal Chemical Co., Ltd., cresol novolac type epoxy resin, solid at 25 ° C) 13.2 parts by mass-Pphenol resin (hardener): HE-100C- 30: (Product name, manufactured by Air Water Co., Ltd., phenyl araquil type phenol resin) 11.0 parts by mass ・ Inorganic filler: Aerosil R972: (Product name, manufactured by Nippon Aerosil Co., Ltd., silica, average particle size 0 .016 μm) 7.8 parts by mass ・ Elastoma: SG-P3 solvent modified product (trade name, manufactured by Nagase ChemteX Corporation, acrylic rubber, weight average molecular weight: 800,000, Tg: 12 ° C, solvent is cyclohexanone) 66. 4 parts by mass, coupling agent 1: A-189: (trade name, manufactured by GE Toshiba Corporation, γ-mercaptopropyltrimethoxysilane) 0.4 parts by mass, coupling agent 2: A-1160: (trade name) , GE Toshiba Co., Ltd., γ-ureidopropyltriethoxysilane) 1.15 parts by mass ・ Curing accelerator: Curesol 2PZ-CN: (trade name, manufactured by Shikoku Kasei Kogyo Co., Ltd., 1-cyanoethyl-2-phenyl) Imidazole) 0.03 parts by mass ・ Solvent: Cyclohexane
＜実施例１＞
　上記のとおり、溶媒としてシクロヘキサノンを使用し、ワニスＡの固形分割合が４０質量％となるように調整した。１００メッシュのフィルターでワニスＡをろ過するとともに真空脱泡した。ワニスＡを塗布するフィルムとして、離型処理が施されたポリエチレンテレフタレート（ＰＥＴ）フィルム（厚さ３８μｍ）を準備した。真空脱泡後のワニスＡを、ＰＥＴフィルムの離型処理が施された面上に塗布した。塗布したワニスＡを、９０℃で５分間、続いて１４０℃で５分間の二段階で加熱乾燥した。こうして、Ｂステージ状態（半硬化状態）の熱硬化性樹脂層ＡをＰＥＴフィルムの表面上に作製した。 <Example 1>
As described above, cyclohexanone was used as a solvent, and the solid content ratio of varnish A was adjusted to 40% by mass. Varnish A was filtered with a 100 mesh filter and vacuum defoamed. As a film to which the varnish A was applied, a polyethylene terephthalate (PET) film (thickness 38 μm) subjected to a mold release treatment was prepared. The varnish A after vacuum defoaming was applied onto the release-treated surface of the PET film. The applied varnish A was heated and dried in two steps at 90 ° C. for 5 minutes and then at 140 ° C. for 5 minutes. In this way, the thermosetting resin layer A in the B stage state (semi-cured state) was formed on the surface of the PET film.
　紫外線硬化型の粘着層を有する積層フィルム（ダイシングテープ）を以下の手順で作製した。まず、アクリル酸２－エチルヘキシル８３質量部、アクリル酸２－ヒドロキシエチル１５質量部、メタクリル酸２質量部を原料として、溶媒には酢酸エチルを用いて、溶液ラジカル重合により共重合体を得た。このアクリル共重合体に対し、２－メタクリロイルオキシエチルイソシアネートを、１２質量部反応させて、炭素－炭素二重結合を有する紫外線照射型アクリル共重合体を合成した。上記の反応にあたっては、重合禁止剤としてヒドロキノン・モノメチルエーテルを０．０５部用いた。合成したアクリル共重合体の重量平均分子量をＧＰＣにより測定したところ、３０万～７０万であった。このようにして得られたアクリル共重合体と、硬化剤としてポリイソシアネート化合物（日本ポリウレタン（株）製、商品名：コロネートＬ）を固形分換算で２．０部と、光重合開始剤として１－ヒドロキシシクロヘキシルフェニルケトン０．５部とを混合し、紫外線照射型粘着剤溶液を調製した。この紫外線照射型粘着剤溶液を、ポリエチレンテレフタレート製剥離フィルム（厚み：３８μｍ）上に、乾燥後の厚さが１０μｍとなるように塗布及び乾燥した。その後、粘着剤層に、片面にコロナ放電処理が施されたポリオレフィン製フィルム（厚さ：９０μｍ）を貼り合わせた。得られた積層フィルムを４０℃の恒温槽で７２時間エージングを行い、ダイシングテープを作製した。 A laminated film (dicing tape) having an ultraviolet curable adhesive layer was prepared by the following procedure. First, a copolymer was obtained by solution radical polymerization using 83 parts by mass of 2-ethylhexyl acrylate, 15 parts by mass of 2-hydroxyethyl acrylate, and 2 parts by mass of methacrylic acid as raw materials and ethyl acetate as a solvent. 12 parts by mass of 2-methacryloyloxyethyl isocyanate was reacted with this acrylic copolymer to synthesize an ultraviolet irradiation type acrylic copolymer having a carbon-carbon double bond. In the above reaction, 0.05 part of hydroquinone / monomethyl ether was used as a polymerization inhibitor. The weight average molecular weight of the synthesized acrylic copolymer was measured by GPC and found to be 300,000 to 700,000. The acrylic copolymer thus obtained and a polyisocyanate compound (manufactured by Nippon Polyurethane Industry Co., Ltd., trade name: Coronate L) as a curing agent were added to 2.0 parts in terms of solid content, and 1 as a photopolymerization initiator. -Hydroxycyclohexylphenylketone 0.5 part was mixed to prepare an ultraviolet irradiation type pressure-sensitive adhesive solution. This ultraviolet irradiation type pressure-sensitive adhesive solution was applied and dried on a polyethylene terephthalate release film (thickness: 38 μm) so that the thickness after drying was 10 μm. Then, a polyolefin film (thickness: 90 μm) having been subjected to corona discharge treatment on one side was attached to the pressure-sensitive adhesive layer. The obtained laminated film was aged in a constant temperature bath at 40 ° C. for 72 hours to prepare a dicing tape.
　厚さは５０μｍの熱硬化性樹脂層Ａを１１０℃で１時間にわたって加熱した後、１３０℃で３時間にわたって加熱することによって硬化させ、硬化樹脂層Ａを得た。ダイシングテープの粘着層に、硬化樹脂層Ａを７０℃のホットプレート上でゴムロールを使用して貼り合わせた。この工程を経て支持片形成用フィルムと、ダイシングテープとの積層体を得た。 A thermosetting resin layer A having a thickness of 50 μm was heated at 110 ° C. for 1 hour and then heated at 130 ° C. for 3 hours to cure the cured resin layer A. The cured resin layer A was attached to the adhesive layer of the dicing tape on a hot plate at 70 ° C. using a rubber roll. Through this step, a laminate of a support piece forming film and a dicing tape was obtained.
＜実施例２＞
　熱硬化性樹脂層Ａを１１０℃で１時間にわたって加熱した後、１３０℃で３時間にわたって加熱する代わりに、１１０℃で２時間にわたって加熱することによ　って硬化させたことの他は実施例１と同様にして、支持片形成用フィルムと、ダイシングテープとの積層体を得た。 <Example 2>
Examples except that the thermosetting resin layer A was heated at 110 ° C. for 1 hour and then cured by heating at 110 ° C. for 2 hours instead of heating at 130 ° C. for 3 hours. In the same manner as in No. 1, a laminate of a support piece forming film and a dicing tape was obtained.
＜実施例３＞
　ワニスＡの代わりにワニスＢを使用してＰＥＴフィルムの表面上に熱硬化性樹脂層Ｂを形成するとともに、７０℃のホットプレート上において、ダイシングテープの粘着層に熱硬化性樹脂層Ｂをゴムロールで貼り合わせた後、熱硬化性樹脂層Ｂにポリイミドフィルム（厚さ２５μｍ）をゴムロールで貼り合わせた。この工程を経て支持片形成用フィルムと、ダイシングテープとの積層体を得た。 <Example 3>
A thermosetting resin layer B is formed on the surface of the PET film by using the varnish B instead of the varnish A, and the thermosetting resin layer B is rubber-rolled on the adhesive layer of the dicing tape on a hot plate at 70 ° C. A polyimide film (thickness 25 μm) was bonded to the thermosetting resin layer B with a rubber roll. Through this step, a laminate of a support piece forming film and a dicing tape was obtained.
　実施例１～３の支持片形成用フィルムに対して以下の評価を行った。
（１）剥離強度
　実施例１～３に係る支持片形成用フィルムを含む積層体を幅２５ｍｍ、長さ１００ｍｍの長さにそれぞれカットして試験片を作製した。その後、ハロゲンランンプにて８０ｍＷ／ｃｍ２、２００ｍＪ／ｃｍ２の条件でダイシングテープ側から紫外線を照射した。紫外線照射の粘着層と支持片形成用フィルムとの界面の剥離強度（剥離角度：１８０°、剥離速度：３００ｍｍ／分）を測定した。各実施例につき、測定を３回ずつ行い、その平均値を以下に示す。
・実施例１…０．０３Ｎ／２５ｍｍ
・実施例２…０．０４Ｎ／２５ｍｍ
・実施例３…０．０５Ｎ／２５ｍｍ The following evaluations were performed on the support piece forming films of Examples 1 to 3.
(1) Peeling Strength A test piece was prepared by cutting the laminate containing the support piece forming film according to Examples 1 to 3 into a width of 25 mm and a length of 100 mm, respectively. Then, ultraviolet rays were irradiated from the dicing tape side under the conditions of 80 mW / cm 2 and 200 mJ / cm 2 with a halogen lamp. The peel strength (peeling angle: 180 °, peeling speed: 300 mm / min) at the interface between the adhesive layer irradiated with ultraviolet rays and the film for forming a support piece was measured. For each example, the measurement was performed three times, and the average value is shown below.
Example 1 ... 0.03N / 25mm
Example 2: 0.04 N / 25 mm
Example 3: 0.05 N / 25 mm
（２）ピックアップ性
　実施例１～３に係る支持片形成用フィルム（形状：直径３２０ｍｍの円形）と、上記と同様にして作製したダイシングテープ（形状：直径３３５ｍｍの円形）の積層体を準備した。この積層体のダイシングテープにダイシングリングを７０℃の条件でラミネートした。ダイサーを用いて支持片形成用フィルムをハイト５５μｍの条件で個片化した。これにより、サイズが１０ｍｍ×１０ｍｍの支持片を得た。支持片の粘着層に向けてハロゲンランンプにて８０ｍＷ／ｃｍ２、２００ｍＪ／ｃｍ２の条件でダイシングテープ側から紫外線照射した。その後、ダイボンダにてエキスパンド（エキスパンド量：３ｍｍ）した状態で、支持片をピックアップした。突き上げ治具として、三段突き上げステージを使用し、条件は突き上げ速度１０ｍｍ／秒及び突き上げ高さ１２００μｍとした。各実施例について、６個の支持片に対してピックアップを試みたところ、実施例１～３のいずれにおいても、６個の支持片のすべてをピックアップすることができた。 (2) Pickup property A laminate of the support piece forming film (shape: circle with a diameter of 320 mm) according to Examples 1 to 3 and the dicing tape (shape: circle with a diameter of 335 mm) produced in the same manner as above was prepared. .. A dicing ring was laminated on the dicing tape of this laminated body under the condition of 70 ° C. The support piece forming film was individualized using a dicer under the condition of a height of 55 μm. As a result, a support piece having a size of 10 mm × 10 mm was obtained. Ultraviolet rays were irradiated from the dicing tape side toward the adhesive layer of the support piece with a halogen lamp under the conditions of 80 mW / cm 2 and 200 mJ / cm 2 . Then, the support piece was picked up in a state of being expanded (expanded amount: 3 mm) with a die bonder. A three-stage push-up stage was used as the push-up jig, and the conditions were a push-up speed of 10 mm / sec and a push-up height of 1200 μm. When an attempt was made to pick up the six support pieces for each example, all of the six support pieces could be picked up in any of the first to third embodiments.
　本開示によれば、ドルメン構造を有する半導体装置の製造プロセスにおいて支持片を作製する工程を簡略化できる半導体装置の製造方法が提供される。また、本開示によれば、ドルメン構造を有する半導体装置、並びに支持片形成用積層フィルム及びその製造方法が提供される。 According to the present disclosure, there is provided a method for manufacturing a semiconductor device that can simplify the process of manufacturing a support piece in the process for manufacturing a semiconductor device having a dolmen structure. Further, the present disclosure provides a semiconductor device having a dolmen structure, a laminated film for forming a support piece, and a method for producing the same.
１…基材フィルム、２…粘着層、５…熱硬化性樹脂層、６…樹脂層、１０…基板、２０，２０Ａ，２０Ｂ…支持片形成用積層フィルム、５０…封止材、１００，２００…半導体装置、Ｄ…支持片形成用フィルム、Ｄ２…二層フィルム（支持片形成用フィルム）、Ｄ３…三層フィルム（支持片形成用フィルム）、Ｄａ…支持片、Ｄｃ…支持片（硬化物）、Ｒ…領域、Ｔ１…第一のチップ、Ｔ２…第二のチップ、Ｔ２ａ…接着剤片付きチップ、Ｔａ…接着剤片、Ｔｃ…接着剤片（硬化物）

  1 ... Base film, 2 ... Adhesive layer, 5 ... Thermocurable resin layer, 6 ... Resin layer, 10 ... Substrate, 20, 20A, 20B ... Laminated film for forming support pieces, 50 ... Encapsulant, 100, 200 ... Semiconductor device, D ... Support piece forming film, D2 ... Double layer film (support piece forming film), D3 ... Three layer film (support piece forming film), Da ... Support piece, Dc ... Support piece (cured product) ), R ... region, T1 ... first chip, T2 ... second chip, T2a ... chip with adhesive piece, Ta ... adhesive piece, Tc ... adhesive piece (cured product)

Claims (20)

  1. 　基板と、前記基板上に配置された第一のチップと、前記基板上であって前記第一のチップの周囲に配置された複数の支持片と、前記複数の支持片によって支持され且つ前記第一のチップを覆うように配置された第二のチップとを含むドルメン構造を有する半導体装置の製造方法であって、
    （Ａ）基材フィルムと、粘着層と、支持片形成用フィルムとをこの順序で備える積層フィルムを準備する工程と、
    （Ｂ）前記支持片形成用フィルムを個片化することによって、前記粘着層の表面上に複数の支持片を形成する工程と、
    （Ｃ）前記粘着層から前記支持片をピックアップする工程と、
    （Ｄ）基板上に第一のチップを配置する工程と、
    （Ｅ）前記基板上であって前記第一のチップの周囲又は前記第一のチップが配置されるべき領域の周囲に複数の前記支持片を配置する工程と、
    （Ｆ）第二のチップと、前記第二のチップの一方の面上に設けられた接着剤片とを備える接着剤片付きチップを準備する工程と、
    （Ｇ）複数の前記支持片の表面上に前記接着剤片付きチップを配置することによってドルメン構造を構築する工程と、
    を含み、
    　前記支持片形成用フィルムが、熱硬化性樹脂層からなるフィルム又は熱硬化性樹脂層のうち少なくとも一部を硬化させた層からなるフィルム、あるいは、熱硬化性樹脂層と当該熱硬化性樹脂層よりも高い剛性を有する樹脂層又は金属層とを有する多層フィルムである、半導体装置の製造方法。     A substrate, a first chip arranged on the substrate, a plurality of support pieces arranged on the substrate and around the first chip, and the first support piece supported by the plurality of support pieces. A method for manufacturing a semiconductor device having a dolmen structure including a second chip arranged so as to cover one chip.
    (A) A step of preparing a laminated film including a base film, an adhesive layer, and a support piece forming film in this order.
    (B) A step of forming a plurality of support pieces on the surface of the adhesive layer by individualizing the support piece forming film.
    (C) A step of picking up the support piece from the adhesive layer and
    (D) The process of arranging the first chip on the substrate and
    (E) A step of arranging a plurality of the support pieces on the substrate or around the region where the first chip should be arranged.
    (F) A step of preparing a chip with an adhesive piece, which comprises a second chip and an adhesive piece provided on one surface of the second chip.
    (G) A step of constructing a dolmen structure by arranging the chips with adhesive pieces on the surfaces of a plurality of the support pieces, and
    Including
    The support piece forming film is a film made of a thermosetting resin layer, a film made of a layer obtained by curing at least a part of the thermosetting resin layer, or a thermosetting resin layer and the thermosetting resin layer. A method for manufacturing a semiconductor device, which is a multilayer film having a resin layer or a metal layer having higher rigidity.
  2. 　前記粘着層が紫外線硬化型であり、
    　（Ｂ）工程と（Ｃ）工程の間に、前記粘着層に紫外線を照射する工程を含む、請求項１に記載の半導体装置の製造方法。     The adhesive layer is UV curable and
    The method for manufacturing a semiconductor device according to claim 1, further comprising a step of irradiating the adhesive layer with ultraviolet rays between the steps (B) and (C).
  3. 　（Ｇ）工程よりも前に、前記支持片形成用フィルム又は前記支持片を加熱する工程を含む、請求項１又は２に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1 or 2, further comprising a step of heating the support piece forming film or the support piece prior to the step (G).
  4. 　基板と、
    　前記基板上に配置された第一のチップと、
    　前記基板上であって前記第一のチップの周囲に配置された複数の支持片と、
    　前記複数の支持片によって支持され且つ前記第一のチップを覆うように配置された第二のチップと、
    を含むドルメン構造を有し、
    　前記支持片が、熱硬化性樹脂組成物の硬化物からなる、あるいは、熱硬化性樹脂組成物の硬化物からなる層と樹脂層又は金属層とを含む、半導体装置。     With the board
    With the first chip arranged on the substrate,
    A plurality of support pieces arranged on the substrate and around the first chip,
    A second chip supported by the plurality of support pieces and arranged so as to cover the first chip.
    Has a dolmen structure, including
    A semiconductor device in which the support piece is made of a cured product of a thermosetting resin composition, or includes a layer made of a cured product of a thermosetting resin composition and a resin layer or a metal layer.
  5. 　前記第一のチップが前記第二のチップと離間している、請求項４に記載の半導体装置。 The semiconductor device according to claim 4, wherein the first chip is separated from the second chip.
  6. 　前記第二のチップの一方の面上に設けられており且つ前記第二のチップと前記複数の支持片とによって挟まれている接着剤片を更に備える、請求項４又は５に記載の半導体装置。 The semiconductor device according to claim 4 or 5, further comprising an adhesive piece provided on one surface of the second chip and sandwiched between the second chip and the plurality of support pieces. ..
  7. 　前記第一のチップが前記接着剤片と離間している、請求項６に記載の半導体装置。 The semiconductor device according to claim 6, wherein the first chip is separated from the adhesive piece.
  8. 　前記第二のチップにおける前記第一のチップと対面する領域を少なくとも覆うように設けられた接着剤片を更に備え、
    　前記第一のチップが前記接着剤片と離間している、請求項４又は５に記載の半導体装置。     Further comprising an adhesive piece provided so as to cover at least the area of the second chip facing the first chip.
    The semiconductor device according to claim 4 or 5, wherein the first chip is separated from the adhesive piece.
  9. 　前記接着剤片が、前記第二のチップの前記領域から前記第二のチップの周縁側にまで連続的に延在しており前記第二のチップと前記複数の支持片とによって挟まれている、請求項８に記載の半導体装置。 The adhesive piece continuously extends from the region of the second chip to the peripheral side of the second chip, and is sandwiched between the second chip and the plurality of support pieces. The semiconductor device according to claim 8.
  10. 　前記第一のチップが前記接着剤片と接している、請求項６に記載の半導体装置。 The semiconductor device according to claim 6, wherein the first chip is in contact with the adhesive piece.
  11. 　前記接着剤片が、前記第二のチップにおける前記第一のチップと対面する領域を覆うとともに、前記第二のチップの前記領域から前記第二のチップの周縁側にまで連続的に延在しており前記第二のチップと前記複数の支持片とによって挟まれている、請求項１０に記載の半導体装置。 The adhesive piece covers the region of the second chip facing the first chip and continuously extends from the region of the second chip to the peripheral side of the second chip. The semiconductor device according to claim 10, wherein the semiconductor device is sandwiched between the second chip and the plurality of support pieces.
  12. 　基板と、前記基板上に配置された第一のチップと、前記基板上であって前記第一のチップの周囲に配置された複数の支持片と、前記複数の支持片によって支持され且つ前記第一のチップを覆うように配置された第二のチップとを含むドルメン構造を有する半導体装置の製造プロセスにおいて使用される支持片形成用積層フィルムであって、
    　基材フィルムと、
    　粘着層と、
    　支持片形成用フィルムと、
    をこの順序で備え、
    　前記支持片形成用フィルムが、熱硬化性樹脂層からなるフィルム又は熱硬化性樹脂層のうち少なくとも一部を硬化させた層からなるフィルム、あるいは、熱硬化性樹脂層と当該熱硬化性樹脂層よりも高い剛性を有する樹脂層又は金属層とを有する多層フィルムである、支持片形成用積層フィルム。     A substrate, a first chip arranged on the substrate, a plurality of support pieces arranged on the substrate and around the first chip, and the first support piece supported by the plurality of support pieces. A laminated film for forming a support piece used in a manufacturing process of a semiconductor device having a dolmen structure including a second chip arranged so as to cover one chip.
    Base film and
    Adhesive layer and
    A film for forming support pieces and
    In this order,
    The support piece forming film is a film made of a thermosetting resin layer, a film made of a layer obtained by curing at least a part of the thermosetting resin layer, or a thermosetting resin layer and the thermosetting resin layer. A laminated film for forming a support piece, which is a multilayer film having a resin layer or a metal layer having higher rigidity.
  13. 　前記支持片形成用フィルムの厚さが５～１８０μｍである、請求項１２に記載の支持片形成用積層フィルム。 The laminated film for forming a support piece according to claim 12, wherein the film for forming a support piece has a thickness of 5 to 180 μm.
  14. 　前記粘着層が感圧型又は紫外線硬化型である、請求項１２又は１３に記載の支持片形成用積層フィルム。 The laminated film for forming a support piece according to claim 12 or 13, wherein the adhesive layer is a pressure-sensitive type or an ultraviolet curable type.
  15. 　前記熱硬化性樹脂層がエポキシ樹脂を含む、請求項１２～１４のいずれか一項に記載の支持片形成用積層フィルム。 The laminated film for forming a support piece according to any one of claims 12 to 14, wherein the thermosetting resin layer contains an epoxy resin.
  16. 　前記熱硬化性樹脂層がエラストマを含む、請求項１２～１５のいずれか一項に記載の支持片形成用積層フィルム。 The laminated film for forming a support piece according to any one of claims 12 to 15, wherein the thermosetting resin layer contains an elastomer.
  17. 　前記樹脂層がポリイミド層である、請求項１２～１６のいずれか一項に記載の支持片形成用積層フィルム。 The laminated film for forming a support piece according to any one of claims 12 to 16, wherein the resin layer is a polyimide layer.
  18. 　前記金属層が銅層又はアルミニウム層である、請求項１２～１７のいずれか一項に記載の支持片形成用積層フィルム。 The laminated film for forming a support piece according to any one of claims 12 to 17, wherein the metal layer is a copper layer or an aluminum layer.
  19. 　基板と、前記基板上に配置された第一のチップと、前記基板上であって前記第一のチップの周囲に配置された複数の支持片と、前記複数の支持片によって支持され且つ前記第一のチップを覆うように配置された第二のチップとを含むドルメン構造を有する半導体装置の製造プロセスにおいて使用される支持片形成用積層フィルムの製造方法であって、
    　基材フィルムと、その一方の面上に形成された粘着層とを有する粘着フィルムを準備する工程と、
    　前記粘着層の表面上に支持片形成用フィルムを積層する工程と、
    を含み、
    　前記支持片形成用フィルムが、熱硬化性樹脂層からなるフィルム又は熱硬化性樹脂層のうち少なくとも一部を硬化させた層からなるフィルム、あるいは、熱硬化性樹脂層と当該熱硬化性樹脂層よりも高い剛性を有する樹脂層又は金属層とを有する多層フィルムである、支持片形成用積層フィルムの製造方法。     A substrate, a first chip arranged on the substrate, a plurality of support pieces arranged on the substrate and around the first chip, and the first support piece supported by the plurality of support pieces. A method for manufacturing a laminated film for forming a support piece used in a manufacturing process of a semiconductor device having a dolmen structure including a second chip arranged so as to cover one chip.
    A step of preparing an adhesive film having a base film and an adhesive layer formed on one surface thereof, and
    A step of laminating a support piece forming film on the surface of the adhesive layer, and
    Including
    The support piece forming film is a film made of a thermosetting resin layer, a film made of a layer obtained by curing at least a part of the thermosetting resin layer, or a thermosetting resin layer and the thermosetting resin layer. A method for producing a laminated film for forming a support piece, which is a multilayer film having a resin layer or a metal layer having a higher rigidity.
  20. 　基板と、前記基板上に配置された第一のチップと、前記基板上であって前記第一のチップの周囲に配置された複数の支持片と、前記複数の支持片によって支持され且つ前記第一のチップを覆うように配置された第二のチップとを含むドルメン構造を有する半導体装置の製造プロセスにおいて使用される支持片形成用積層フィルムの製造方法であって、
    　基材フィルムと、粘着層と、熱硬化性樹脂層とをこの順序で備える積層フィルムを準備する工程と、
    　前記熱硬化性樹脂層の表面に当該熱硬化性樹脂層よりも高い剛性を有する樹脂層又は金属層を貼り合わせる工程と、
    を含む、支持片形成用積層フィルムの製造方法。

          A substrate, a first chip arranged on the substrate, a plurality of support pieces arranged on the substrate and around the first chip, and the first support piece supported by the plurality of support pieces. A method for manufacturing a laminated film for forming a support piece used in a manufacturing process of a semiconductor device having a dolmen structure including a second chip arranged so as to cover one chip.
    A step of preparing a laminated film including a base film, an adhesive layer, and a thermosetting resin layer in this order, and
    A step of laminating a resin layer or a metal layer having a higher rigidity than the thermosetting resin layer on the surface of the thermosetting resin layer,
    A method for producing a laminated film for forming a support piece, including.
PCT/JP2020/017731 2019-04-25 2020-04-24 Semiconductor device having dolmen structure and manufacturing method therefor, and support piece formation laminate film and manufacturing method therefor WO2020218526A1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023136059A1 (en) * 2022-01-12 2023-07-20 株式会社レゾナック Multilayer film for individualized piece formation, method for producing same, and method for producing semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003124433A (en) * 2001-08-27 2003-04-25 Samsung Electronics Co Ltd Multichip package
JP2006005333A (en) * 2004-05-20 2006-01-05 Toshiba Corp Stacked electronic component and manufacturing method of same
JP2010206136A (en) * 2009-03-06 2010-09-16 Disco Abrasive Syst Ltd Work dividing device
US7859119B1 (en) * 2003-11-10 2010-12-28 Amkor Technology, Inc. Stacked flip chip die assembly
JP2017515306A (en) * 2014-04-29 2017-06-08 マイクロン テクノロジー， インク． Stacked semiconductor die assembly having support members and associated systems and methods

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3210126B2 (en) * 1993-03-15 2001-09-17 株式会社東芝 Manufacturing method of liquid crystal display device
US5721452A (en) * 1995-08-16 1998-02-24 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
JP2002222889A (en) * 2001-01-24 2002-08-09 Nec Kyushu Ltd Semiconductor device and method of manufacturing the same
DE10360708B4 (en) * 2003-12-19 2008-04-10 Infineon Technologies Ag Semiconductor module with a semiconductor stack, rewiring plate, and method of making the same
TWI292617B (en) * 2006-02-03 2008-01-11 Siliconware Precision Industries Co Ltd Stacked semiconductor structure and fabrication method thereof
US20080029885A1 (en) * 2006-08-07 2008-02-07 Sandisk Il Ltd. Inverted Pyramid Multi-Die Package Reducing Wire Sweep And Weakening Torques
TWI317993B (en) * 2006-08-18 2009-12-01 Advanced Semiconductor Eng Stackable semiconductor package
US8169058B2 (en) * 2009-08-21 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars
JP5840479B2 (en) * 2011-12-20 2016-01-06 株式会社東芝 Semiconductor device and manufacturing method thereof
KR101906269B1 (en) * 2012-04-17 2018-10-10 삼성전자 주식회사 Semiconductor package and method of fabricating the same
JP2015176906A (en) * 2014-03-13 2015-10-05 株式会社東芝 Semiconductor device and method of manufacturing the same
KR102161776B1 (en) * 2014-03-28 2020-10-06 에스케이하이닉스 주식회사 Stack package
US9412722B1 (en) * 2015-02-12 2016-08-09 Dawning Leading Technology Inc. Multichip stacking package structure and method for manufacturing the same
US11359431B2 (en) * 2017-02-28 2022-06-14 Panasonic Intellectual Property Management Co., Ltd. Method for manufacturing pillar supply sheet, method for manufacturing glass panel unit, and method for manufacturing glass window
CN113574663A (en) * 2019-04-25 2021-10-29 昭和电工材料株式会社 Semiconductor device with stone tomb structure and manufacturing method thereof
WO2020217401A1 (en) * 2019-04-25 2020-10-29 日立化成株式会社 Semiconductor device having dolmen structure, method for manufacturing same, laminated film for forming support piece, and method for manufacturing same
IT201900006736A1 (en) * 2019-05-10 2020-11-10 Applied Materials Inc PACKAGE MANUFACTURING PROCEDURES

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003124433A (en) * 2001-08-27 2003-04-25 Samsung Electronics Co Ltd Multichip package
US7859119B1 (en) * 2003-11-10 2010-12-28 Amkor Technology, Inc. Stacked flip chip die assembly
JP2006005333A (en) * 2004-05-20 2006-01-05 Toshiba Corp Stacked electronic component and manufacturing method of same
JP2010206136A (en) * 2009-03-06 2010-09-16 Disco Abrasive Syst Ltd Work dividing device
JP2017515306A (en) * 2014-04-29 2017-06-08 マイクロン テクノロジー， インク． Stacked semiconductor die assembly having support members and associated systems and methods

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023136059A1 (en) * 2022-01-12 2023-07-20 株式会社レゾナック Multilayer film for individualized piece formation, method for producing same, and method for producing semiconductor device

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