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WO2020218472A1 - Hysteresis comparator and communication circuit - Google Patents

Hysteresis comparator and communication circuit Download PDF

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Publication number
WO2020218472A1
WO2020218472A1 PCT/JP2020/017609 JP2020017609W WO2020218472A1 WO 2020218472 A1 WO2020218472 A1 WO 2020218472A1 JP 2020017609 W JP2020017609 W JP 2020017609W WO 2020218472 A1 WO2020218472 A1 WO 2020218472A1
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WO
WIPO (PCT)
Prior art keywords
chip
comparator
hysteresis
substrate
input
Prior art date
Application number
PCT/JP2020/017609
Other languages
French (fr)
Japanese (ja)
Inventor
忠広 黒田
Original Assignee
学校法人慶應義塾
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 学校法人慶應義塾 filed Critical 学校法人慶應義塾
Priority to JP2021516235A priority Critical patent/JP7324529B2/en
Publication of WO2020218472A1 publication Critical patent/WO2020218472A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B5/00—Near-field transmission systems, e.g. inductive or capacitive transmission systems
    • H04B5/40—Near-field transmission systems, e.g. inductive or capacitive transmission systems characterised by components specially adapted for near-field transmission
    • H04B5/48—Transceivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

Definitions

  • the present invention relates to a hysteresis comparator and a communication circuit.
  • the inventor of the present application has proposed an electronic circuit that performs data communication between substrates by using capacitive coupling and inductive coupling (collectively referred to as electromagnetic coupling) (see, for example, Patent Documents 1 and 2).
  • a coupler is attached to a flexible printed circuit board (FPC), a printed circuit board (Printed Circuit Board; PCB), a module, and a terminal (hereinafter, abbreviated as a board). It is formed.
  • the signal line is used as a coupler.
  • Two signal lines (signal line and feedback signal line) arranged in parallel are formed on each substrate (FIG. 33).
  • the signal line and the feedback signal line are terminated and matched using resistors.
  • the signal line and the feedback signal line of one substrate are arranged so as to be parallel to and in the same direction as the signal line and the feedback signal line of the other substrate.
  • the signal lines are arranged close to each other. Since the signal lines overlap and the feedback signal lines overlap, wireless communication can be performed by electromagnetic field coupling.
  • Patent Document 2 discloses a communication device using a signal line as a coupler.
  • a leader transmission line is connected to both ends of one signal line.
  • a positive signal is input to the transmission line from one of the lead transmission lines, and a negative signal is input to the transmission line from the other lead transmission line.
  • the digital signal is a Non Return to Zero signal (NRZ signal), and when it passes through an AC coupler such as an electromagnetic field coupler, the DC component is lost and it becomes a pulse signal with a small amplitude.
  • the receiver restores this small-amplitude pulse signal into a digital signal using a hysteresis comparator (paragraph 0191 and FIG. 30 of Patent Document 1).
  • the hysteresis comparator can change the input threshold value, and can increase the noise immunity when there is no change in the signal (that is, when the same digital data is continuous). Hysteresis of 50 mV or more and 1/3 or less of the signal amplitude is often required.
  • hysteresis comparator IC Integrated Circuit
  • the parts when applying the comparator IC chip to an in-vehicle device, the parts must be in-vehicle certified, however, there are relatively few hysteresis comparator IC chips that have been in-vehicle certified.
  • the comparators having no hysteresis are highly versatile, more in-vehicle certified comparators are commercially available. Therefore, a comparator having no hysteresis and a comparator having a small hysteresis width are easily available and can be configured inexpensively.
  • the present embodiment is in view of the above problems, and even when an IC chip having a comparator having no hysteresis or a hysteresis comparator having a small hysteresis width is used, a hysteresis comparator having desired characteristics and communication.
  • the purpose is to provide a circuit.
  • the communication circuit includes a substrate, an electromagnetic field coupler provided on the substrate, and a first comparator for comparing the level of a received signal received by the electromagnetic field coupler.
  • the first IC chip may have a serial-parallel converter arranged after the first comparator.
  • a capacitor may be provided in the feedback loop.
  • a resistor may be provided in the feedback loop.
  • the communication circuit has a substrate, an electromagnetic field coupler provided on the substrate, and a comparator for comparing the level of the received signal received by the electromagnetic field coupler, and the substrate has the same.
  • a feedback loop having a mounted IC chip and a first capacitor provided on the substrate and positively feeding back the output of the IC chip to an input is arranged between the electromagnetic field coupler and the IC chip. It also has a second capacitor.
  • the communication circuit has a substrate, an electromagnetic field coupler provided on the substrate, and a comparator for comparing the level of the received signal received by the electromagnetic field coupler, and the substrate has the same. It is provided with a mounted IC chip and a feedback loop having a resistor provided on the board and positively feeding back the output of the IC chip to an input.
  • the hysteresis comparator includes a substrate and a first comparator for comparing the levels of the two input signals, the first IC chip mounted on the substrate, and the two input signals. It has a second comparator for comparing the levels of the above, and includes a second IC chip mounted on the substrate and a feedback loop in which the output of the second IC chip is positively fed back to the input.
  • the first IC chip may have a serial-parallel converter arranged after the first comparator.
  • a capacitor may be provided in the feedback loop.
  • a resistor may be provided in the feedback loop.
  • a hysteresis comparator and a communication circuit capable of obtaining desired characteristics even when an IC chip having a comparator having no hysteresis or a comparator having a small hysteresis width is used. it can.
  • FIG. It is a block diagram which shows the structure of the communication circuit which concerns on Embodiment 1.
  • FIG. It is a block diagram which shows the structural example of the IC chip in Embodiment 1.
  • FIG. It is a figure which shows the hysteresis width HYS calculated by the simulation. It is a figure which shows the hysteresis width HYS calculated by the simulation. It is a figure which shows the circuit structure used for the simulation. It is a waveform diagram which shows the simulation result in Embodiment 1.
  • FIG. It is a block diagram which shows the structural example of an IC chip. It is a block diagram which shows the structure of the communication circuit which concerns on Embodiment 2.
  • FIG. It is a waveform diagram which shows the simulation result in Embodiment 2.
  • Embodiment It is a block diagram which shows the structure of the communication circuit which concerns on Embodiment 3.
  • FIG. It is a block diagram which shows the structural example of the IC chip in Embodiment 3.
  • FIG. 1 is a block diagram showing a configuration of a hysteresis comparator according to the first embodiment.
  • the communication circuit 1 includes a substrate 2, an IC chip 13, a buffer 14, feedback loops 20p, 20n, resistors 21p, 21n, couplers 31p, 31n, and output terminals 41p, 41n. And resistors 51 to 54. Couplers 31p and 31n, resistors 51 to 54, an IC chip 13, a buffer 14, and resistors 21p and 21n are provided on the substrate 2.
  • the board 2 is a wiring board on which wiring for connecting each configuration is formed.
  • the signal received by the communication circuit 1 is described as a differential signal, but a single-ended configuration in which a part or all of the communication circuit 1 transmits a single-ended (single differential) signal. It may be.
  • identifying two components (differential pairs) that transmit a differential signal they will be described with a subscript of p or n.
  • p and n will be described without subscripts. For example, when the two couplers 31p and 31n are not identified, the coupler 31 is used. Further, the resistors 21p and 21n and the output terminals 41p and 41n are also simply described as the resistors 21 and the output terminals 41 when the differential pair is not identified.
  • the coupler 31 is, for example, the electromagnetic field coupler shown in Patent Documents 1 and 2.
  • the coupler 31 is a transmission line coupler composed of transmission lines on the substrate 2, as shown in FIG. 33 of Patent Document 1 or FIG. 2 of Patent Document 2.
  • the coupler 31 is provided with a coupler similar to the coupler 31 in a communication circuit (not shown) which is a communication partner.
  • the coupler 31 can be, for example, a transmission line arranged parallel to each other so as to be coupled as a distributed constant system by an electric field and a magnetic field.
  • the coupler 31 may be an overlapping coil (inductive coupler) so as to be magnetically coupled (inductively coupled) as a lumped constant system.
  • the coupler 31 can be an electrode arranged in parallel with each other so as to be electrically coupled (capacitively coupled) as a lumped constant system.
  • the electromagnetic field coupling may be a coupling using at least one of an electric field and a magnetic field.
  • the communication circuit 1 performs, for example, half-duplex communication with a communication circuit (not shown) which is a communication partner.
  • the communication circuit 1 is a communication device that transmits and receives data by wireless communication.
  • the coupler 31 of the communication circuit 1 is non-contact coupled with the coupler of the communication circuit to be the communication partner.
  • the digital signal is a Non Return to Zero signal (NRZ signal), and when it passes through the coupler 31, the DC component is lost and it becomes a pulse signal with a small amplitude. Therefore, the received signals received by the couplers 31p and 31n are small amplitude pulse signals.
  • NRZ signal Non Return to Zero signal
  • the communication circuit 1 since the communication circuit 1 according to the present embodiment has the configuration of the receiver as one of the technical features, only the configuration on the receiving side will be described, and the configuration on the transmitting side will be omitted. Further, the communication circuit 1 may be a receiving device having no transmission function.
  • Coupler 31p One end of the coupler 31p is connected to the resistor 51, and the other end is connected to the non-inverting input terminal of the IC chip 13.
  • One end of the coupler 31n is connected to the resistor 52, and the other end is connected to the inverting input terminal of the IC chip 13.
  • Resistors 51 and 52 are connected between the coupler 31p and the coupler 31n. The resistors 51 and 52 are terminating resistors that terminate the coupler 31p and the coupler 31n.
  • the IC chip 13 is a semiconductor chip mounted on the substrate 2.
  • the IC chip 13 is a receiver chip that functions as a receiver. Specifically, the IC chip 13 has a semiconductor circuit for restoring a digital signal. The configuration of the IC chip 13 will be described later.
  • the received signal received by the couplers 31p and 31n is input to the IC chip 13.
  • the IC chip 13 has a comparator that restores the received data. That is, the comparator restores the digital signal by comparing the levels of the two received signals. When the level of the received signal from the coupler 31p is higher than the level of the received signal from the coupler 31n, the digital signal becomes 1, and when it is lower, it becomes 0.
  • the comparator provided on the IC chip 13 is a comparator that does not have a hysteresis characteristic. Alternatively, the comparator provided on the IC chip 13 may be a comparator having a small hysteresis width.
  • Resistors 53 and 54 are connected between the two input terminals of the IC chip 13.
  • the node between the resistors 53 and 54 is biased at the termination potential Vb.
  • the output of the IC chip 13 is connected to the buffer 14. Therefore, the digital signal restored by the IC chip 13 is input to the buffer 14.
  • the buffer 14 amplifies the output amplitude of the IC chip 13 to the power supply voltage.
  • the buffer 14 outputs the received signal to the output terminals OUTP and OUTN.
  • the output of the buffer 14 is used as received data.
  • the IC chip 13 and the buffer 14 are assumed to be general-purpose semiconductor chips, respectively. That is, the IC chip 13 and the buffer 14 may be commercially available chips, respectively.
  • the buffer 14 can be omitted.
  • Feedback loops 20p and 20n are provided between the input and the output of the IC chip 13.
  • the feedback loops 20p and 20n connect the output of the IC chip 13 to the input. It is desirable that this connection be made within a range that is sufficiently short compared to the wavelength that is a component of the digital signal.
  • the feedback loops 20p and 20n are provided with resistors 21p and 21n, respectively.
  • the feedback loops 20p and 20n have the wiring of the substrate 2 and the resistor 21.
  • the resistors 21p and 21n are feedback resistors. That is, the input and the output of the IC chip 13 are connected via the resistor 21.
  • the resistance values of the resistor 21p and the resistor 21n are the same value, and are, for example, 300 ⁇ to 3k ⁇ .
  • the output from the IC chip 13 returns to the input of the IC chip 13 via the resistor 21.
  • the feedback loops 20p and 20n positively feed back the output of the IC chip 13 to the input.
  • the input potentials of the IC chip 13 are VIP and VIN, and the output potentials are VOP and VON.
  • FIG. 2 shows the circuit configurations of the IC chip 13 and the buffer 14.
  • the IC chip 13 includes a comparator COM and an inverter INV.
  • the comparator COM compares the levels of the differential input terminals INP and INN of the IC chip 13 with the input potentials VIP and VIN.
  • a two-stage inverter INV is provided in the output stage of the comparator COM.
  • a resistor 56 is provided after the inverter INV.
  • the inverter INV is a CMOS (Complementary Metal-Oxide-Semiconductor) inverter.
  • the buffer 14 has a two-stage CMOS inverter.
  • the comparator COM When the differential signal of the positive electrode is input to the comparator COM of the IC chip 13, the comparator COM outputs the signal of the positive electrode having an amplitude close to VDD. This signal adds positive feedback to the input potential via the resistor 21.
  • the current output from the comparator COM is the output impedance Z0 (the sum of the impedance of the inverter INV of the output stage in FIG. 2 and the impedance of the resistor 56) and the resistance value R of the resistor 21. It flows to the terminating potential Vb (that is, VDD / 2) via two terminating resistors Z0 (equivalent resistance value is Z0 / 2) connected in parallel. Therefore, the differential voltage v_hys represented by the following equation (1) is added to the input terminal of the comparator COM by positive feedback.
  • VDD 1.8V
  • R is about 1.7 k ⁇ in order to obtain a hysteresis width of 70 mV.
  • the output of the comparator COM is not inverted unless a negative electrode differential signal having a larger amplitude is input to the input terminals INP and INN. That is, the input threshold value of the comparator COM has hysteresis. By changing the value of R, the hysteresis width of the input threshold value can be adjusted.
  • FIGS. 3 and 4 show the hysteresis width HYS when the simulation result is performed with the circuit configuration shown in FIG. As shown in FIGS. 3 and 4, a hysteresis width HYS corresponding to the resistance values R of the resistors 21p and 21n can be obtained.
  • the input potential and the output potential when the received signal received by the coupler 31 is input to the comparator are shown.
  • VI shows the waveforms of the input potentials VIP and VIN
  • VO shows the waveforms of the output potentials VOP and VON.
  • the positive feedback signal component is added to the input signal of the comparator COM. Therefore, the comparator COM can appropriately compare the levels of the received signals.
  • the input threshold value changes to the opposite polarity of the input signal
  • the signal component of the input signal is added to the same polarity as the input signal as described above. ..
  • the IC chip 13 can obtain the same effect (noise immunity) as the hysteresis comparator.
  • the IC chip 13 serving as a receiver can appropriately restore data by comparing the received signals from the coupler 31.
  • the IC chip 13 can appropriately restore data from a small amplitude pulse signal. Therefore, it has high noise immunity and enables high-speed data communication.
  • resistors 21p, 21n having a resistance value corresponding to the required hysteresis width may be arranged in the feedback loops 20p, 20n.
  • R of the resistance element chip resistance, lead resistance, etc.
  • the comparator COM is not limited to a comparator having no hysteresis, and may be a hysteresis comparator having a small hysteresis width. Even in such a case, the hysteresis width can be widened by providing the resistor 21 in the feedback loop 20. Therefore, a desired hysteresis characteristic can be obtained.
  • a general-purpose chip can be used as the IC chip 13.
  • Various IC chips using a comparator without hysteresis as a receiving circuit are commercially available. Further, such an IC chip is commercially available as an in-vehicle certified chip and is easily available. Therefore, even when the easily available IC chip 13 is used as the receiver, the digital signal can be appropriately restored. Therefore, the hysteresis comparator and the receiving circuit can be manufactured with inexpensive commercially available parts. It is not necessary to develop and manufacture a dedicated IC chip, and a low-cost hysteresis comparator and communication circuit can be realized. In addition, an in-vehicle communication circuit can be manufactured at low cost.
  • the comparator compares the input signal from the coupler 31 with the reference voltage. That is, one of the two input signals to the IC chip 13 becomes the received signal from the coupler 31, and the other becomes the reference voltage.
  • the IC chip 13 compares the level of the input signal with the reference voltage and restores the digital signal.
  • FIG. 7 is a block diagram showing a configuration example of the IC chip 13 as a receiving chip.
  • the IC chip 13 includes an equivalent device 131, a receiving circuit 132, a CDR (clock data recovery) circuit, and an output circuit 134.
  • the equivalent device 131 is a circuit that adjusts the frequency characteristics of the received signal.
  • the equivalent device 131 has a frequency filter or the like that amplifies a high frequency component.
  • the receiving circuit 132 has, for example, the comparator COM without hysteresis shown in FIG. Further, the receiving circuit 132 may have an inverter INV of the output stage. The receiving circuit 132 restores the data by comparing the levels of the two received signals.
  • the CDR (clock data recovery) circuit is a circuit that separates the data from the clock of the received signal on which the clock is superimposed on the data.
  • the output circuit 134 has, for example, the two-stage inverter INV shown in FIG.
  • the receiving circuit 132 can appropriately restore data from a small amplitude pulse signal. Therefore, data can be restored using a hysteresis comparator having a desired hysteresis characteristic, and high-speed data communication becomes possible.
  • FIG. 8 is a block diagram showing the configuration of the communication circuit 1.
  • capacitors 22p, 22n are provided in the feedback loops 20p, 20n. That is, the resistors 21p and 21n in FIG. 2 are replaced with the capacitors 22p and 22n, respectively.
  • capacitors 63p and 63n are provided on the transmission line between the coupler 31 and the IC chip 13.
  • the basic configurations other than the capacitors 22p and 22n and the capacitors 63p and 63n are the same as those in the first embodiment, and thus the description thereof will be omitted.
  • Capacitors 22p and 22n are arranged in feedback loops 20p and 20n, respectively. That is, the input and output of the IC chip 13 are connected via the capacitor 22.
  • Capacitors 63p and 63n are arranged on the input side of the IC chip 13. That is, the capacitor 63p is arranged between the coupler 31p and the non-inverting input terminal of the IC chip 13. The capacitor 63n is arranged between the coupler 31n and the inverting input terminal of the IC chip 13. Capacitors 63p and 63n are provided outside the feedback loops 20p and 20n. The capacitors 63p and 63n transmit the received signal received by the couplers 31p and 31n to the IC chip 13. That is, the received signal received by the coupler 31p is input to the non-inverting input terminal of the IC chip 13 via the capacitor 63p. The received signal received by the coupler 31n is input to the inverting input terminal of the IC chip 13 via the capacitor 63n.
  • C be the capacitance value of the capacitors 22p and 22n
  • C1 be the capacitance value of the capacitors 63p and 63n.
  • Vc be the amplitude of the output pulse signal of the coupler 31
  • Vfb be the amplitude of the signal positively fed back from the output of the IC chip 13 by the capacitors 22p and 22n. Since the electric charge is stored at the input node of the IC chip 13, the input potential Vin of the IC chip 13 is expressed by Vc and Vfb by the following equation (2).
  • C1 (Vin-Vc) + C (Vin-Vfb) 0 ... (2)
  • the hysteresis width of the input threshold of the comparator can be adjusted with C1 / C.
  • the capacity value C1 is made larger than the capacity value C.
  • the capacitor 22p and the capacitor 22n have the same capacitance value C.
  • the capacitor 63p and the capacitor 63n have the same capacitance value C1.
  • the capacitance value C1 is preferably larger than the capacitance value C.
  • the ratio (C1 / C) of the capacitance value C1 to the capacitance value C is preferably 10 to 1000. That is, the capacity value C1 is preferably about 10 to 1000 times the capacity value C.
  • the input of the IC chip 13 is biased to Vb with resistors 53 and 54.
  • FIG. 9 shows a waveform diagram when a signal is transmitted at 5 Gps. Here, the waveforms of the input potentials VIP and VON and the output potentials VOP and VON when the received signal received by the coupler 31 is input to the comparator are shown. According to the configuration of the present embodiment, the positive feedback signal component is added to the input signal of the comparator COM. Therefore, the same effect as that of the first embodiment can be obtained.
  • FIG. 10 is a block diagram showing the configuration of the communication circuit 1 according to the third embodiment.
  • the IC chip 70 is added to the configuration of the first embodiment. That is, two IC chips 13 and an IC chip 70 are mounted on the substrate 2. Further, in the third embodiment, the feedback loops 20p and 20n are provided not on the IC chip 13 but on the IC chip 70. In the present embodiment, the IC chip 70 is used to give hysteresis to the comparator COM of the IC chip 13.
  • the coupler 31 is the same as in the first embodiment.
  • the resistor 57 corresponds to the resistors 51 and 52
  • the resistor 58 corresponds to the resistors 53 and 54. Therefore, description of these configurations will be omitted.
  • the couplers 31p and 31n are connected to the IC chip 13.
  • the coupler 31p is connected to the non-inverting input terminal of the IC chip 13, and the coupler 31n is connected to the inverting input terminal of the IC chip 13.
  • the IC chip 13 has a comparator COM without hysteresis, as in the first embodiment. Therefore, the voltage levels of the differential received signals from the couplers 31p and 31n of the IC chip 13 are compared.
  • a branch node BP is provided between the coupler 31p and the non-inverting input terminal of the IC chip 13.
  • the branch node BP is connected to the non-inverting input terminal of the IC chip 70.
  • a branch node BN is provided between the coupler 31n and the inverting input terminal of the IC chip 13.
  • the branch node BN is connected to the inverting input terminal of the IC chip 70. Therefore, the received signals from the couplers 31p and 31n are input to the IC chip 70. That is, the received signal from the coupler 31p is input to the IC chip 70 via the branch node BP.
  • the received signal from the coupler 31n is input to the IC chip 70 via the branch node BN.
  • the IC chip 70 has the same configuration as the IC chip 13 of FIG.
  • the IC chip 70 has a comparator COM without hysteresis.
  • the comparator COM of the IC chip 70 compares the levels of two received signals from the coupler 31.
  • the feedback loops 20p and 20n feed back the output of the IC chip 70 to the input.
  • the feedback loop 20p is provided with a resistor 21p
  • the feedback loop 20n is provided with a resistor 21n. Therefore, the feedback loops 20p and 20n provide positive feedback to the output and input of the IC chip 70 with resistors 21p and 21n.
  • the output of the IC chip 70 is connected to the input of the IC chip 13 via the feedback loops 20p and 20n, and the branch nodes BP and BN. Therefore, the positively fed signal component is added to the input signal of the IC chip 13.
  • the IC chip 70 can be used to give the comparator of the IC chip 13 a hysteresis width. As a result, the IC chip 13 can appropriately restore the digital signal as in the first and second embodiments.
  • the output of the comparator COM is serial-parallel converted and then output from the IC chip 13.
  • S / P converter serial-parallel converter
  • the comparator of the IC chip 13 can have hysteresis.
  • the comparator COM of the IC chip 70 may have a slower data transfer rate than the comparator of the IC chip 13. Even in such a case, hysteresis can be given to the comparator of the IC chip 13.
  • the hysteresis can be appropriately provided by using the IC chip 70 having a fast signal propagation delay tpd.
  • the feedback loop 20 is configured by using the resistor 21 in FIG. 10, the feedback loop may be configured by using the capacitance as in the second embodiment.
  • the capacitor 22 and the capacitor 63 as shown in FIG. 8 may be provided on the IC chip 70.
  • FIG. 11 is a block diagram showing the configurations of the IC chip 13 and the IC chip 70.
  • the IC chip 70 has the same configuration as the IC chip 13 of FIG. That is, the equivalent device 171, the receiving circuit 172, the CDR circuit 173, and the output circuit 174 of the IC chip 70 are the same as the equivalent device 131, the receiving circuit 132, the CDR circuit 133, and the output circuit 134 of FIG. Therefore, the description thereof will be omitted.
  • the receiving circuit 172 is a comparator without hysteresis as shown in FIG.
  • the IC chip 70 is a receiving chip that does not have an S / P converter.
  • the IC chip 13 has an S / P converter 135 added to the IC chip 13 shown in FIG.
  • the receiving circuit 132 is a comparator COM having no hysteresis as shown in FIG.
  • the S / P converter 135 is arranged after the receiving circuit 132, and serial-parallel converts the data restored by the receiving circuit 132.
  • the S / P converter 135 includes a shift register and the like.
  • the S / P converter 135 sequentially holds data according to the clock signals separated by the CDR circuit 133 and converts the data into parallel data.
  • the parallel data converted by the S / P converter 135 is output from the IC chip 13.
  • FIG. 11 since the parallel data is set to 2 bits for simplification of the description, only the four output terminals OUT1P, OUT1N, OUT2P, and OUT2N are shown, but the bit length of the parallel data is 3 bits or more. It may be.
  • the IC chip 13 and the IC chip 70 can be general-purpose semiconductor chips. That is, two IC chips having a comparator having no hysteresis are prepared and mounted on the substrate 2. Since a commercially available receiving chip that is easily available can be used as the IC chip 13 and the IC chip 70, a hysteresis comparator and a communication circuit can be realized at low cost.
  • the comparators of the IC chip 13 and the IC chip 70 are not limited to the comparators having no hysteresis, and may be a comparator having a small hysteresis width.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dc Digital Transmission (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)

Abstract

Provided are a hysteresis comparator with which it is possible to obtain desired characteristics even when an IC chip comprising a comparator with no hysteresis or a comparator with a small hysteresis width is used, and a communication circuit. A communication circuit (1) according to an embodiment is provided with: a substrate (2); a coupler (31) provided on the substrate (2); an IC chip (13) which is mounted on the substrate (2) and includes a comparator for comparing the levels of two input signals; an IC chip (70) which includes a second comparator for comparing the levels of reception signals and which is mounted on the substrate (2); and feedback loops (20p), (20n) for positively feeding back outputs of the IC chip (70) to the inputs thereof.

Description

ヒステリシス比較器、及び通信回路Hysteresis comparator and communication circuit
　本発明はヒステリシス比較器、及び通信回路に関する。 The present invention relates to a hysteresis comparator and a communication circuit.
　本件出願の発明者は、容量結合及び誘導結合（合わせて電磁界結合と称する）を用いて、基板間でデータ通信を行なう電子回路を提案している（例えば、特許文献１、２参照）。このような電子回路では、フレキシブルプリント回路基板（Ｆｌｅｘｉｂｌｅ　Ｐｒｉｎｔｅｄ　Ｃｉｒｃｕｉｔ；ＦＰＣ）、プリント回路基板（Ｐｒｉｎｔｅｄ　Ｃｉｒｃｕｉｔ　Ｂｏａｒｄ；ＰＣＢ）、モジュール、及び端末（以下、総称して基板と略称する）に、結合器が形成されている。 The inventor of the present application has proposed an electronic circuit that performs data communication between substrates by using capacitive coupling and inductive coupling (collectively referred to as electromagnetic coupling) (see, for example, Patent Documents 1 and 2). In such an electronic circuit, a coupler is attached to a flexible printed circuit board (FPC), a printed circuit board (Printed Circuit Board; PCB), a module, and a terminal (hereinafter, abbreviated as a board). It is formed.
　特許文献１では、信号線路が結合器として用いられている。それぞれの基板には、平行に配置された２本の信号線路（信号線路と帰還信号線路）が形成されている（図３３）。信号線路と帰還信号線路とは、抵抗を用いて終端整合されている。一方の基板の信号線路、帰還信号線路が、他方の基板の信号線路、帰還信号線路と平行かつ同一方向になるように配置される。基板を積層することで、信号線路が近接配置される。信号線路同士が重複し、帰還信号線路同士が重複するため，電磁界結合により無線通信を行なうことができる。 In Patent Document 1, the signal line is used as a coupler. Two signal lines (signal line and feedback signal line) arranged in parallel are formed on each substrate (FIG. 33). The signal line and the feedback signal line are terminated and matched using resistors. The signal line and the feedback signal line of one substrate are arranged so as to be parallel to and in the same direction as the signal line and the feedback signal line of the other substrate. By stacking the substrates, the signal lines are arranged close to each other. Since the signal lines overlap and the feedback signal lines overlap, wireless communication can be performed by electromagnetic field coupling.
　特許文献２には、信号線路を結合器として用いた通信装置が開示されている。特許文献２では、差動信号を用いるため、一本の信号線路の両端に引出伝送線路が接続されている。一方の引出伝送線路から正極性の信号が伝送線路に入力され、他方の引出し伝送線路から負極性の信号が伝送線路に入力される。 Patent Document 2 discloses a communication device using a signal line as a coupler. In Patent Document 2, since a differential signal is used, a leader transmission line is connected to both ends of one signal line. A positive signal is input to the transmission line from one of the lead transmission lines, and a negative signal is input to the transmission line from the other lead transmission line.
特許第５２１３０８７号公報Japanese Patent No. 5213087 特開２０１４－０３３４３２号公報Japanese Unexamined Patent Publication No. 2014-033432
　デジタル信号はNon Return to Zero信号（NRZ信号）であり、これが電磁界結合器などの交流結合器を通過すると、直流成分が失われて小振幅のパルス信号になる。受信器は、この小振幅パルス信号を、ヒステリシス比較器を用いてデジタル信号に復元する（特許文献１の段落０１９１および図３０）。ヒステリシス比較器は入力しきい値を変化させることができ、信号の変化がない場合（つまり同じデジタルデータが連続した場合）のノイズ耐性を高めることができる。５０ｍＶ以上かつ信号振幅の１／３以下のヒステリシスが求められることが多い。 The digital signal is a Non Return to Zero signal (NRZ signal), and when it passes through an AC coupler such as an electromagnetic field coupler, the DC component is lost and it becomes a pulse signal with a small amplitude. The receiver restores this small-amplitude pulse signal into a digital signal using a hysteresis comparator (paragraph 0191 and FIG. 30 of Patent Document 1). The hysteresis comparator can change the input threshold value, and can increase the noise immunity when there is no change in the signal (that is, when the same digital data is continuous). Hysteresis of 50 mV or more and 1/3 or less of the signal amplitude is often required.
　市販のヒステリシス比較器ＩＣ（Integrated Circuit）チップを用いた場合、データ通信の高速化が困難である。一方でヒステリシスを持たない比較器は、汎用性が高いので、高速なＩＣチップが市販されている。また、市販のヒステリシス比較器ＩＣチップにおいて、ヒステリシス幅が不足する場合がある。 When a commercially available hysteresis comparator IC (Integrated Circuit) chip is used, it is difficult to speed up data communication. On the other hand, a comparator having no hysteresis is highly versatile, so a high-speed IC chip is commercially available. Further, in a commercially available hysteresis comparator IC chip, the hysteresis width may be insufficient.
　また、比較器ＩＣチップを車載に応用する場合は、部品が車載認定を受けたものでなければならない、しかしながら、ヒステリシス比較器ＩＣチップで車載認定を受けたものは比較的少ない。一方、ヒステリシスを持たない比較器は、汎用性が高いので、車載認定を受けたものがより多く市販されている。よって、ヒステリシスを持たない比較器やヒステリシス幅が小さい比較器は入手が容易で有り、安価な構成とすることができる。 In addition, when applying the comparator IC chip to an in-vehicle device, the parts must be in-vehicle certified, however, there are relatively few hysteresis comparator IC chips that have been in-vehicle certified. On the other hand, since the comparators having no hysteresis are highly versatile, more in-vehicle certified comparators are commercially available. Therefore, a comparator having no hysteresis and a comparator having a small hysteresis width are easily available and can be configured inexpensively.
　本実施形態は、上記の課題に鑑みたものであり、ヒステリシスを持たない比較器やヒステリシス幅が小さいヒステリシス比較器を有するＩＣチップを用いた場合でも、所望の特性を有するヒステリシス比較器、及び通信回路を提供することを目的とする。 The present embodiment is in view of the above problems, and even when an IC chip having a comparator having no hysteresis or a hysteresis comparator having a small hysteresis width is used, a hysteresis comparator having desired characteristics and communication. The purpose is to provide a circuit.
　本実施の形態に係る通信回路は、基板と、前記基板に設けられた電磁界結合器と、前記電磁界結合器で受信された受信信号のレベルを比較する第１の比較器を有し、前記基板に実装された第１のＩＣチップと、前記受信信号のレベルを比較する第２の比較器を有し、前記基板に実装された第２のＩＣチップと、前記第２のＩＣチップの出力を入力に正帰還する帰還ループと、を備えている。 The communication circuit according to the present embodiment includes a substrate, an electromagnetic field coupler provided on the substrate, and a first comparator for comparing the level of a received signal received by the electromagnetic field coupler. A first IC chip mounted on the board and a second comparator for comparing the level of the received signal, and the second IC chip mounted on the board and the second IC chip It has a feedback loop that feeds the output back to the input.
　上記の通信回路において、前記第１のＩＣチップが、前記第１の比較器の後段に配置されたシリアルパラレル変換器を有していてもよい。 In the above communication circuit, the first IC chip may have a serial-parallel converter arranged after the first comparator.
　上記の通信回路において、前記帰還ループにキャパシタが設けられていてもよい。 In the above communication circuit, a capacitor may be provided in the feedback loop.
　上記の通信回路において、前記帰還ループに抵抗が設けられていてもよい。 In the above communication circuit, a resistor may be provided in the feedback loop.
　本実施の形態に係る通信回路は、基板と、前記基板に設けられた電磁界結合器と、前記電磁界結合器で受信された受信信号のレベルを比較する比較器を有し、前記基板に実装されたＩＣチップと、前記基板に設けられた第１キャパシタを有し、前記ＩＣチップの出力を入力に正帰還する帰還ループと、前記電磁界結合器と前記ＩＣチップとの間に配置された第２のキャパシタと、を備えている。 The communication circuit according to the present embodiment has a substrate, an electromagnetic field coupler provided on the substrate, and a comparator for comparing the level of the received signal received by the electromagnetic field coupler, and the substrate has the same. A feedback loop having a mounted IC chip and a first capacitor provided on the substrate and positively feeding back the output of the IC chip to an input is arranged between the electromagnetic field coupler and the IC chip. It also has a second capacitor.
　本実施の形態に係る通信回路は、基板と、前記基板に設けられた電磁界結合器と、前記電磁界結合器で受信された受信信号のレベルを比較する比較器を有し、前記基板に実装されたＩＣチップと、前記基板に設けられた抵抗を有し、前記ＩＣチップの出力を入力に正帰還する帰還ループと、を備えている The communication circuit according to the present embodiment has a substrate, an electromagnetic field coupler provided on the substrate, and a comparator for comparing the level of the received signal received by the electromagnetic field coupler, and the substrate has the same. It is provided with a mounted IC chip and a feedback loop having a resistor provided on the board and positively feeding back the output of the IC chip to an input.
　本実施の形態に係るヒステリシス比較器は、基板と、２つの入力信号のレベルを比較する第１の比較器を有し、前記基板に実装された第１のＩＣチップと、前記２つの入力信号のレベルを比較する第２の比較器を有し、前記基板に実装された第２のＩＣチップと、前記第２のＩＣチップの出力を入力に正帰還する帰還ループと、を備えている。 The hysteresis comparator according to the present embodiment includes a substrate and a first comparator for comparing the levels of the two input signals, the first IC chip mounted on the substrate, and the two input signals. It has a second comparator for comparing the levels of the above, and includes a second IC chip mounted on the substrate and a feedback loop in which the output of the second IC chip is positively fed back to the input.
　上記のヒステリシス比較器において、前記第１のＩＣチップが、前記第１の比較器の後段に配置されたシリアルパラレル変換器を有していてもよい。 In the above-mentioned hysteresis comparator, the first IC chip may have a serial-parallel converter arranged after the first comparator.
　上記のヒステリシス比較器において、前記帰還ループにキャパシタが設けられていてもよい。 In the above-mentioned hysteresis comparator, a capacitor may be provided in the feedback loop.
　上記のヒステリシス比較器において、前記帰還ループに抵抗が設けられていてもよい。 In the above-mentioned hysteresis comparator, a resistor may be provided in the feedback loop.
　本実施の形態によれば、ヒステリシスのない比較器又はヒステリシス幅の小さい比較器を有するＩＣチップを用いた場合でも、所望の特性を得ることができるヒステリシス比較器、及び通信回路を提供することができる。 According to the present embodiment, it is possible to provide a hysteresis comparator and a communication circuit capable of obtaining desired characteristics even when an IC chip having a comparator having no hysteresis or a comparator having a small hysteresis width is used. it can.
実施の形態１にかかる通信回路の構成を示すブロック図である。It is a block diagram which shows the structure of the communication circuit which concerns on Embodiment 1. FIG. 実施の形態１でのＩＣチップの構成例を示すブロック図である。It is a block diagram which shows the structural example of the IC chip in Embodiment 1. FIG. シミュレーションで算出されたヒステリシス幅ＨＹＳを示す図である。It is a figure which shows the hysteresis width HYS calculated by the simulation. シミュレーションで算出されたヒステリシス幅ＨＹＳを示す図である。It is a figure which shows the hysteresis width HYS calculated by the simulation. シミュレーションに用いた回路構成を示す図である。It is a figure which shows the circuit structure used for the simulation. 実施の形態１でのシミュレーション結果を示す波形図である。It is a waveform diagram which shows the simulation result in Embodiment 1. FIG. ＩＣチップの構成例を示すブロック図である。It is a block diagram which shows the structural example of an IC chip. 実施の形態２にかかる通信回路の構成を示すブロック図である。It is a block diagram which shows the structure of the communication circuit which concerns on Embodiment 2. FIG. 実施の形態２でのシミュレーション結果を示す波形図である。It is a waveform diagram which shows the simulation result in Embodiment 2. 実施の形態３にかかる通信回路の構成を示すブロック図である。It is a block diagram which shows the structure of the communication circuit which concerns on Embodiment 3. FIG. 実施の形態３でのＩＣチップの構成例を示すブロック図である。It is a block diagram which shows the structural example of the IC chip in Embodiment 3.
　実施の形態１．
　以下、図面を参照して本実施の形態について説明する。図１は、本実施の形態１にかかるヒステリシス比較器の構成を示すブロック図である。図１に示すように、通信回路１は、基板２と、ＩＣチップ１３と、バッファ１４と、帰還ループ２０ｐ、２０ｎと、抵抗２１ｐ、２１ｎと、結合器３１ｐ、３１ｎと、出力端子４１ｐ、４１ｎと、抵抗５１～５４とを有している。基板２上には、結合器３１ｐ、３１ｎ、抵抗５１～５４、ＩＣチップ１３、バッファ１４，及び抵抗２１ｐ、２１ｎが設けられている。基板２は、各構成を接続するための配線が形成された配線基板である。 Embodiment 1.
Hereinafter, the present embodiment will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a hysteresis comparator according to the first embodiment. As shown in FIG. 1, the communication circuit 1 includes a substrate 2, an IC chip 13, a buffer 14, feedback loops 20p, 20n, resistors 21p, 21n, couplers 31p, 31n, and output terminals 41p, 41n. And resistors 51 to 54. Couplers 31p and 31n, resistors 51 to 54, an IC chip 13, a buffer 14, and resistors 21p and 21n are provided on the substrate 2. The board 2 is a wiring board on which wiring for connecting each configuration is formed.
　なお、本実施の形態では、通信回路１が受信する信号が差動信号であるとして説明するが、通信回路１の一部又は全部がシングルエンド（片差動）信号を伝送するシングルエンド構成となっていてもよい。以下の説明において、差動信号を伝送する２つの構成要素（差動対）を識別する場合、ｐ、又はｎの添え字を付して説明する。差動信号を伝送する２つの構成要素を特に区別しない場合は、ｐ、及びｎを添え字を付さずに説明する。例えば２つの結合器３１ｐ、３１ｎを識別しない場合、結合器３１とする。また、抵抗２１ｐ、２１ｎ、及び出力端子４１ｐ、４１ｎについても、差動対を識別しない場合、抵抗２１、及び出力端子４１と簡略化して記載する。 In the present embodiment, the signal received by the communication circuit 1 is described as a differential signal, but a single-ended configuration in which a part or all of the communication circuit 1 transmits a single-ended (single differential) signal. It may be. In the following description, when identifying two components (differential pairs) that transmit a differential signal, they will be described with a subscript of p or n. When the two components that transmit the differential signal are not particularly distinguished, p and n will be described without subscripts. For example, when the two couplers 31p and 31n are not identified, the coupler 31 is used. Further, the resistors 21p and 21n and the output terminals 41p and 41n are also simply described as the resistors 21 and the output terminals 41 when the differential pair is not identified.
　結合器３１は、例えば、特許文献１、２に示した電磁界結合器である。結合器３１は、特許文献１の図３３，又は特許文献２の図２等に示すように、基板２上の伝送線路で構成された伝送線路結合器である。結合器３１は、通信相手となる通信回路（不図示）にも結合器３１と同様の結合器が設けられている。結合器３１は、例えば、電界および磁界で分布定数系として結合するように互い平行に配置された伝送線路とすることができる。あるいは、結合器３１は、集中定数系として磁界結合（誘導結合）するように、重複配置されたコイル（誘導結合器）とすることができる。あるいは、結合器３１は、集中定数系として電界結合（容量結合）するように、互い平行に配置された電極とすることができる。電磁界結合とは、電界及び磁界の少なくとも一方を用いた結合であればよい。 The coupler 31 is, for example, the electromagnetic field coupler shown in Patent Documents 1 and 2. The coupler 31 is a transmission line coupler composed of transmission lines on the substrate 2, as shown in FIG. 33 of Patent Document 1 or FIG. 2 of Patent Document 2. The coupler 31 is provided with a coupler similar to the coupler 31 in a communication circuit (not shown) which is a communication partner. The coupler 31 can be, for example, a transmission line arranged parallel to each other so as to be coupled as a distributed constant system by an electric field and a magnetic field. Alternatively, the coupler 31 may be an overlapping coil (inductive coupler) so as to be magnetically coupled (inductively coupled) as a lumped constant system. Alternatively, the coupler 31 can be an electrode arranged in parallel with each other so as to be electrically coupled (capacitively coupled) as a lumped constant system. The electromagnetic field coupling may be a coupling using at least one of an electric field and a magnetic field.
　通信回路１は、通信相手となる通信回路（不図示）との間で、例えば、半二重通信を行なう。通信回路１は、無線通信によりデータを送受信する通信装置となる。具体的には、通信回路１の結合器３１は、通信相手となる通信回路の結合器と非接触で結合している。デジタル信号はNon Return to Zero信号（NRZ信号）であり、結合器３１を通過すると、直流成分が失われて小振幅のパルス信号になる。よって、結合器３１ｐ、３１ｎが受信した受信信号は、小振幅パルス信号となっている。本実施の形態にかかる通信回路１は、受信器の構成を技術的特徴の一つとしているため、受信側の構成についてのみ説明を行い、送信側の構成については省略する。また、通信回路１は、送信機能のない受信装置であってもよい。 The communication circuit 1 performs, for example, half-duplex communication with a communication circuit (not shown) which is a communication partner. The communication circuit 1 is a communication device that transmits and receives data by wireless communication. Specifically, the coupler 31 of the communication circuit 1 is non-contact coupled with the coupler of the communication circuit to be the communication partner. The digital signal is a Non Return to Zero signal (NRZ signal), and when it passes through the coupler 31, the DC component is lost and it becomes a pulse signal with a small amplitude. Therefore, the received signals received by the couplers 31p and 31n are small amplitude pulse signals. Since the communication circuit 1 according to the present embodiment has the configuration of the receiver as one of the technical features, only the configuration on the receiving side will be described, and the configuration on the transmitting side will be omitted. Further, the communication circuit 1 may be a receiving device having no transmission function.
　結合器３１ｐの一端は、抵抗５１と接続され、他端はＩＣチップ１３の非反転入力端子に接続される。結合器３１ｎの一端は、抵抗５２と接続され、他端はＩＣチップ１３の反転入力端子に接続される。結合器３１ｐと結合器３１ｎとの間には、抵抗５１，５２が接続されている。抵抗５１，５２は、結合器３１ｐと結合器３１ｎとを終端する終端抵抗である。 One end of the coupler 31p is connected to the resistor 51, and the other end is connected to the non-inverting input terminal of the IC chip 13. One end of the coupler 31n is connected to the resistor 52, and the other end is connected to the inverting input terminal of the IC chip 13. Resistors 51 and 52 are connected between the coupler 31p and the coupler 31n. The resistors 51 and 52 are terminating resistors that terminate the coupler 31p and the coupler 31n.
　ＩＣチップ１３は、基板２に実装された半導体チップである。ＩＣチップ１３は、受信器として機能する受信器チップである。具体的には、ＩＣチップ１３は、デジタル信号を復元するための半導体回路を有している。ＩＣチップ１３の構成に付いては、後述する。 The IC chip 13 is a semiconductor chip mounted on the substrate 2. The IC chip 13 is a receiver chip that functions as a receiver. Specifically, the IC chip 13 has a semiconductor circuit for restoring a digital signal. The configuration of the IC chip 13 will be described later.
　ＩＣチップ１３には、結合器３１ｐ、３１ｎが受信した受信信号が入力される。ＩＣチップ１３は、受信したデータを復元する比較器を有している。つまり、比較器が２つの受信信号のレベルを比較することで、デジタル信号を復元する。結合器３１ｐからの受信信号のレベルが結合器３１ｎからの受信信号のレベルよりも高い場合、デジタル信号が１となり、低い場合０となる。ＩＣチップ１３に設けられた比較器はヒステリシス特性を備えていない比較器である。あるいは、ＩＣチップ１３に設けられた比較器は、ヒステリシス幅の小さい比較器であってもよい。 The received signal received by the couplers 31p and 31n is input to the IC chip 13. The IC chip 13 has a comparator that restores the received data. That is, the comparator restores the digital signal by comparing the levels of the two received signals. When the level of the received signal from the coupler 31p is higher than the level of the received signal from the coupler 31n, the digital signal becomes 1, and when it is lower, it becomes 0. The comparator provided on the IC chip 13 is a comparator that does not have a hysteresis characteristic. Alternatively, the comparator provided on the IC chip 13 may be a comparator having a small hysteresis width.
　ＩＣチップ１３の２つの入力端子の間には抵抗５３、５４が接続されている。抵抗５３と抵抗５４の間のノードは、終端電位Ｖｂでバイアスされている。電源電圧をＶＤＤとすると、例えば、Ｖｂ＝ＶＤＤ／２となっている。抵抗５１～５４の抵抗値は、結合器３１又は伝送線路の特性インピーダンスＺ０に対応し、典型的にはＺ０＝５０Ωとなっている。 Resistors 53 and 54 are connected between the two input terminals of the IC chip 13. The node between the resistors 53 and 54 is biased at the termination potential Vb. Assuming that the power supply voltage is VDD, for example, Vb = VDD / 2. The resistance values of the resistors 51 to 54 correspond to the characteristic impedance Z0 of the coupler 31 or the transmission line, and typically Z0 = 50Ω.
　ＩＣチップ１３の出力は、バッファ１４に接続されている。よって、ＩＣチップ１３が復元したデジタル信号は、バッファ１４に入力される。なお、バッファ１４は、ＩＣチップ１３の出力振幅を電源電圧に増幅する。バッファ１４は、受信信号を出力端子ＯＵＴＰ、ＯＵＴＮに出力する。バッファ１４の出力が受信データとして用いられる。ＩＣチップ１３とバッファ１４は、それぞれ汎用の半導体チップを想定している。つまり、ＩＣチップ１３、及びバッファ１４は、それぞれ市販チップであってもよい。なお、バッファ１４は省略することも可能である。 The output of the IC chip 13 is connected to the buffer 14. Therefore, the digital signal restored by the IC chip 13 is input to the buffer 14. The buffer 14 amplifies the output amplitude of the IC chip 13 to the power supply voltage. The buffer 14 outputs the received signal to the output terminals OUTP and OUTN. The output of the buffer 14 is used as received data. The IC chip 13 and the buffer 14 are assumed to be general-purpose semiconductor chips, respectively. That is, the IC chip 13 and the buffer 14 may be commercially available chips, respectively. The buffer 14 can be omitted.
　ＩＣチップ１３の入力と出力との間には帰還ループ２０ｐ、２０ｎが設けられている。帰還ループ２０ｐ、２０ｎは、ＩＣチップ１３の出力を入力に接続する。この接続は、デジタル信号の成分である波長に比べて十分に短い距離の範囲内で接続することが望ましい。 Feedback loops 20p and 20n are provided between the input and the output of the IC chip 13. The feedback loops 20p and 20n connect the output of the IC chip 13 to the input. It is desirable that this connection be made within a range that is sufficiently short compared to the wavelength that is a component of the digital signal.
　帰還ループ２０ｐ、２０ｎには、抵抗２１ｐ、２１ｎがそれぞれ設けられている。帰還ループ２０ｐ、２０ｎは基板２の配線と抵抗２１とを有している。抵抗２１ｐ、２１ｎは帰還抵抗である。つまり、ＩＣチップ１３の入力と出力とが抵抗２１を介して接続されている。抵抗２１ｐと抵抗２１ｎの抵抗値は、同じ値であり、例えば、３００Ωから３ｋΩである。ＩＣチップ１３からの出力は、抵抗２１を介して、ＩＣチップ１３の入力に帰還する。帰還ループ２０ｐ、２０ｎは、ＩＣチップ１３の出力を入力に正帰還する。なお、ＩＣチップ１３の入力電位をＶＩＰ、ＶＩＮとし、出力電位をＶＯＰ、ＶＯＮとする。 The feedback loops 20p and 20n are provided with resistors 21p and 21n, respectively. The feedback loops 20p and 20n have the wiring of the substrate 2 and the resistor 21. The resistors 21p and 21n are feedback resistors. That is, the input and the output of the IC chip 13 are connected via the resistor 21. The resistance values of the resistor 21p and the resistor 21n are the same value, and are, for example, 300Ω to 3kΩ. The output from the IC chip 13 returns to the input of the IC chip 13 via the resistor 21. The feedback loops 20p and 20n positively feed back the output of the IC chip 13 to the input. The input potentials of the IC chip 13 are VIP and VIN, and the output potentials are VOP and VON.
　ＩＣチップ１３、及びバッファ１４の回路構成を図２に示す。ＩＣチップ１３は比較器ＣＯＭと、インバータＩＮＶを備えている。比較器ＣＯＭは、ＩＣチップ１３の差動の入力端子ＩＮＰ、ＩＮＮの入力電位ＶＩＰ、ＶＩＮのレベルを比較する。比較器ＣＯＭの出力段には２段のインバータＩＮＶが設けられている。インバータＩＮＶの後段には抵抗５６が設けられている。インバータＩＮＶはＣＭＯＳ（Complementary Metal-Oxide-Semiconductor）インバータである。また、バッファ１４は２段のＣＭＯＳインバータを有している。 FIG. 2 shows the circuit configurations of the IC chip 13 and the buffer 14. The IC chip 13 includes a comparator COM and an inverter INV. The comparator COM compares the levels of the differential input terminals INP and INN of the IC chip 13 with the input potentials VIP and VIN. A two-stage inverter INV is provided in the output stage of the comparator COM. A resistor 56 is provided after the inverter INV. The inverter INV is a CMOS (Complementary Metal-Oxide-Semiconductor) inverter. Further, the buffer 14 has a two-stage CMOS inverter.
　ＩＣチップ１３の比較器ＣＯＭに正極の差動信号が入力されると、比較器ＣＯＭはＶＤＤに近い振幅の正極の信号を出力する。この信号は、抵抗２１を介して入力電位に正帰還を加える。たとえば、電圧ＶｂがＶＤＤ／２のとき、比較器ＣＯＭから出力された電流は、出力インピーダンスＺ０（図２の出力段のインバータＩＮＶと抵抗５６のインピーダンスの合計）と、抵抗２１の抵抗値Ｒと、２つの並列接続された終端抵抗Ｚ０（等価抵抗値はＺ０／２）と、を介して、終端電位Ｖｂ（つまりＶＤＤ／２）に流れる。従って、比較器ＣＯＭの入力端子には、以下の式（１）で示される差動電圧ｖ＿ｈｙｓが正帰還で追加される。 When the differential signal of the positive electrode is input to the comparator COM of the IC chip 13, the comparator COM outputs the signal of the positive electrode having an amplitude close to VDD. This signal adds positive feedback to the input potential via the resistor 21. For example, when the voltage Vb is VDD / 2, the current output from the comparator COM is the output impedance Z0 (the sum of the impedance of the inverter INV of the output stage in FIG. 2 and the impedance of the resistor 56) and the resistance value R of the resistor 21. It flows to the terminating potential Vb (that is, VDD / 2) via two terminating resistors Z0 (equivalent resistance value is Z0 / 2) connected in parallel. Therefore, the differential voltage v_hys represented by the following equation (1) is added to the input terminal of the comparator COM by positive feedback.
ｖ＿ｈｙｓ＝（ＶＤＤ／２）＊｛（Ｚ０／２）／（（Ｚ０／２）＋Ｒ＋Ｚ０）｝
　　　　　＝ＶＤＤ＊｛１／（６＋（４Ｒ／Ｚ０））｝　　・・・（１） v_hys = (VDD / 2) * {(Z0 / 2) / ((Z0 / 2) + R + Z0)}
= VDD * {1 / (6+ (4R / Z0))} ... (1)
　例えば、ＶＤＤ＝１．８Ｖとすると、Ｒ＝１ｋΩでｖ＿ｈｙｓ＝２１ｍＶとなり、Ｒ＝０．５ｋΩでＶ＿ｈｙｓ＝３９ｍＶとなる。ＶＤＤ＝±５ＶでＶｂ＝０Ｖの場合、７０ｍＶのヒステリシス幅を得るには、Ｒは約１．７ｋΩとなる。 For example, if VDD = 1.8V, v_hys = 21mV at R = 1kΩ and V_hys = 39mV at R = 0.5kΩ. When VDD = ± 5V and Vb = 0V, R is about 1.7 kΩ in order to obtain a hysteresis width of 70 mV.
　その結果、入力端子ＩＮＰ、ＩＮＮにそれ以上の振幅の負極の差動信号が入力しない限り、比較器ＣＯＭの出力は反転しない。つまり、比較器ＣＯＭの入力しきい値がヒステリシスを備えたことになる。Ｒの値を変えることで、入力しきい値のヒステリシス幅を調整できる。 As a result, the output of the comparator COM is not inverted unless a negative electrode differential signal having a larger amplitude is input to the input terminals INP and INN. That is, the input threshold value of the comparator COM has hysteresis. By changing the value of R, the hysteresis width of the input threshold value can be adjusted.
　ＶＤＤ＝１．８Ｖ，Ｖｂ＝０．９Ｖとして、抵抗２１ｐ、２１ｎの抵抗値Ｒを変えたときのシミュレーション結果を図３、図４に示す。図３、図４は、図５に示す回路構成でシミュレーション結果を行ったときのヒステリシス幅ＨＹＳを示している。図３，図４に示すように、抵抗２１ｐ、２１ｎの抵抗値Ｒに応じたヒステリシス幅ＨＹＳを得ることができる。 The simulation results when the resistance values R of the resistors 21p and 21n are changed with VDD = 1.8V and Vb = 0.9V are shown in FIGS. 3 and 4. 3 and 4 show the hysteresis width HYS when the simulation result is performed with the circuit configuration shown in FIG. As shown in FIGS. 3 and 4, a hysteresis width HYS corresponding to the resistance values R of the resistors 21p and 21n can be obtained.
　図６はＲ＝０．５ｋΩとしたときの過渡応答を示すシミュレーション結果である。ここでは、結合器３１を用いて受信した受信信号を比較器に入力したときの入力電位と出力電位を示している。ＶＩは入力電位ＶＩＰ、ＶＩＮの波形を示し、ＶＯは出力電位ＶＯＰ、ＶＯＮの波形を示している。本実施の形態の構成によれば、比較器ＣＯＭの入力信号に正帰還された信号成分が加わることになる。よって、適切に、比較器ＣＯＭが受信信号のレベルを比較することができる。 FIG. 6 is a simulation result showing a transient response when R = 0.5 kΩ. Here, the input potential and the output potential when the received signal received by the coupler 31 is input to the comparator are shown. VI shows the waveforms of the input potentials VIP and VIN, and VO shows the waveforms of the output potentials VOP and VON. According to the configuration of the present embodiment, the positive feedback signal component is added to the input signal of the comparator COM. Therefore, the comparator COM can appropriately compare the levels of the received signals.
　一般的なヒステリシス比較器では入力しきい値が入力信号の反対極性に変化するのに対して、本実施形態では、上記のように、入力信号の信号成分が入力信号と同一極性に追加される。この結果、ＩＣチップ１３は、ヒステリシス比較器と同等の効果（ノイズ耐性）を得ることができる。受信器となるＩＣチップ１３が、結合器３１からの受信信号を比較することで、適切にデータを復元することができる。ＩＣチップ１３は、小振幅パルス信号から適切にデータを復元することができる。よって、ノイズ耐性が高く、高速なデータ通信が可能となる。 In the general hysteresis comparator, the input threshold value changes to the opposite polarity of the input signal, whereas in the present embodiment, the signal component of the input signal is added to the same polarity as the input signal as described above. .. As a result, the IC chip 13 can obtain the same effect (noise immunity) as the hysteresis comparator. The IC chip 13 serving as a receiver can appropriately restore data by comparing the received signals from the coupler 31. The IC chip 13 can appropriately restore data from a small amplitude pulse signal. Therefore, it has high noise immunity and enables high-speed data communication.
　本実施の形態の構成によれば、ヒステリシスのない比較器ＣＯＭを有するＩＣチップ１３を用いた場合でも、適切なヒステリシス幅を設けることが可能となる。換言すると、必要とされるヒステリシス幅に応じた抵抗値を有する抵抗２１ｐ、２１ｎを帰還ループ２０ｐ、２０ｎに配置すればよい。例えば、基板２上に実装する抵抗素子（チップ抵抗やリード抵抗等）の抵抗値Ｒを変えることで、所望のヒステリシス幅を有するヒステリシス比較器を実現することができる。また、比較器ＣＯＭはヒステリシスのない比較器に限らず、ヒステリシス幅が小さいヒステリシス比較器であってもよい。このような場合でも、帰還ループ２０に抵抗２１を設けることで、ヒステリシス幅を広くすることができる。よって、所望のヒステリシス特性を得ることができる。 According to the configuration of the present embodiment, it is possible to provide an appropriate hysteresis width even when an IC chip 13 having a comparator COM having no hysteresis is used. In other words, resistors 21p, 21n having a resistance value corresponding to the required hysteresis width may be arranged in the feedback loops 20p, 20n. For example, by changing the resistance value R of the resistance element (chip resistance, lead resistance, etc.) mounted on the substrate 2, it is possible to realize a hysteresis comparator having a desired hysteresis width. Further, the comparator COM is not limited to a comparator having no hysteresis, and may be a hysteresis comparator having a small hysteresis width. Even in such a case, the hysteresis width can be widened by providing the resistor 21 in the feedback loop 20. Therefore, a desired hysteresis characteristic can be obtained.
　ＩＣチップ１３としては、汎用チップを用いることができる。ヒステリシスのない比較器を受信回路として用いたＩＣチップは、種々のものが市販されている。さらに、このようなＩＣチップは、車載認定を受けたチップとしても市販されており、入手が容易である。したがって、入手が容易なＩＣチップ１３を受信器として用いた場合であっても、デジタル信号を適切に復元することができる。よって、安価な市販部品でヒステリシス比較器、及び受信回路を製造することができる。専用のＩＣチップの開発、製造が不要となり、低コストなヒステリシス比較器、及び通信回路を実現できる。また、車載用通信回路を安価に製造することができる。ヒステリシスのない比較器又はヒステリシス幅の小さい比較器を有するＩＣチップ１３を用いた場合でも、所望の特性を得ることができるヒステリシス比較器、及び通信回路１を実現することができる。 A general-purpose chip can be used as the IC chip 13. Various IC chips using a comparator without hysteresis as a receiving circuit are commercially available. Further, such an IC chip is commercially available as an in-vehicle certified chip and is easily available. Therefore, even when the easily available IC chip 13 is used as the receiver, the digital signal can be appropriately restored. Therefore, the hysteresis comparator and the receiving circuit can be manufactured with inexpensive commercially available parts. It is not necessary to develop and manufacture a dedicated IC chip, and a low-cost hysteresis comparator and communication circuit can be realized. In addition, an in-vehicle communication circuit can be manufactured at low cost. Even when an IC chip 13 having a comparator without hysteresis or a comparator having a small hysteresis width is used, it is possible to realize a hysteresis comparator and a communication circuit 1 capable of obtaining desired characteristics.
　なお、シングルエンド構成の場合、結合器３１が一つとなる。比較器は、結合器３１からの入力信号を、基準電圧と比較する。つまり、ＩＣチップ１３への２つの入力信号の一方が結合器３１からの受信信号となり、他方が基準電圧となる。ＩＣチップ１３は、入力信号のレベルを基準電圧と比較して、デジタル信号を復元する。 In the case of a single-ended configuration, there is only one coupler 31. The comparator compares the input signal from the coupler 31 with the reference voltage. That is, one of the two input signals to the IC chip 13 becomes the received signal from the coupler 31, and the other becomes the reference voltage. The IC chip 13 compares the level of the input signal with the reference voltage and restores the digital signal.
　図７は、受信チップとしてのＩＣチップ１３の構成例を示すブロック図である。ＩＣチップ１３は、等価器１３１、受信回路１３２、ＣＤＲ（クロックデータリカバリ）回路、及び出力回路１３４を備えている。 FIG. 7 is a block diagram showing a configuration example of the IC chip 13 as a receiving chip. The IC chip 13 includes an equivalent device 131, a receiving circuit 132, a CDR (clock data recovery) circuit, and an output circuit 134.
　等価器１３１は、受信信号の周波数特性を調整する回路である。例えば、等価器１３１は、高周波成分を増幅する周波数フィルタなどを有している。受信回路１３２は、例えば図２に示したヒステリシスのない比較器ＣＯＭを有している。また、受信回路１３２は、出力段のインバータＩＮＶを有していてもよい。受信回路１３２は、２つの受信信号のレベルを比較することで、データを復元する。ＣＤＲ（クロックデータリカバリ）回路は、データにクロックが重畳されている受信信号のクロックとデータを分離する回路である。出力回路１３４は、例えば、図２に示した２段のインバータＩＮＶを有している。 The equivalent device 131 is a circuit that adjusts the frequency characteristics of the received signal. For example, the equivalent device 131 has a frequency filter or the like that amplifies a high frequency component. The receiving circuit 132 has, for example, the comparator COM without hysteresis shown in FIG. Further, the receiving circuit 132 may have an inverter INV of the output stage. The receiving circuit 132 restores the data by comparing the levels of the two received signals. The CDR (clock data recovery) circuit is a circuit that separates the data from the clock of the received signal on which the clock is superimposed on the data. The output circuit 134 has, for example, the two-stage inverter INV shown in FIG.
　このようなＩＣチップ１３を受信チップとして用いた場合であっても、受信回路１３２が小振幅パルス信号から適切にデータを復元することができる。よって、所望のヒステリシス特性を有するヒステリシス比較器を用いてデータを復元することができため、高速なデータ通信が可能となる。 Even when such an IC chip 13 is used as a receiving chip, the receiving circuit 132 can appropriately restore data from a small amplitude pulse signal. Therefore, data can be restored using a hysteresis comparator having a desired hysteresis characteristic, and high-speed data communication becomes possible.
実施の形態２．
　本実施の形態について、図８を用いて説明する。図８は、通信回路１の構成を示すブロック図である。本実地の形態では、帰還ループ２０ｐ、２０ｎにキャパシタ２２ｐ、２２ｎが設けられている。つまり、図２の抵抗２１ｐ、２１ｎがそれぞれキャパシタ２２ｐ、２２ｎに置き換わっている。さらに、結合器３１とＩＣチップ１３との間の伝送線路に、キャパシタ６３ｐ、６３ｎが設けられている。なお、キャパシタ２２ｐ、２２ｎ、及びキャパシタ６３ｐ、６３ｎ以外の基本的な構成については、実施の形態１と同様であるため説明を省略する。 Embodiment 2.
The present embodiment will be described with reference to FIG. FIG. 8 is a block diagram showing the configuration of the communication circuit 1. In this hands-on form, capacitors 22p, 22n are provided in the feedback loops 20p, 20n. That is, the resistors 21p and 21n in FIG. 2 are replaced with the capacitors 22p and 22n, respectively. Further, capacitors 63p and 63n are provided on the transmission line between the coupler 31 and the IC chip 13. The basic configurations other than the capacitors 22p and 22n and the capacitors 63p and 63n are the same as those in the first embodiment, and thus the description thereof will be omitted.
　キャパシタ２２ｐ、２２ｎはそれぞれ帰還ループ２０ｐ、２０ｎに配置されている。つまり、ＩＣチップ１３の入力と出力とがキャパシタ２２を介して接続されている。 Capacitors 22p and 22n are arranged in feedback loops 20p and 20n, respectively. That is, the input and output of the IC chip 13 are connected via the capacitor 22.
　キャパシタ６３ｐ、６３ｎは、ＩＣチップ１３の入力側に配置されている。つまり、キャパシタ６３ｐは、結合器３１ｐとＩＣチップ１３の非反転入力端子との間に配置されている。キャパシタ６３ｎは、結合器３１ｎとＩＣチップ１３の反転入力端子との間に配置されている。キャパシタ６３ｐ、６３ｎは帰還ループ２０ｐ、２０ｎの外側に設けられている。キャパシタ６３ｐ、６３ｎは、結合器３１ｐ、３１ｎが受信した受信信号は、ＩＣチップ１３に伝送する。つまり、結合器３１ｐが受信した受信信号が、キャパシタ６３ｐを介して、ＩＣチップ１３の非反転入力端子に入力される。結合器３１ｎが受信した受信信号が、キャパシタ６３ｎを介して、ＩＣチップ１３の反転入力端子に入力される。 Capacitors 63p and 63n are arranged on the input side of the IC chip 13. That is, the capacitor 63p is arranged between the coupler 31p and the non-inverting input terminal of the IC chip 13. The capacitor 63n is arranged between the coupler 31n and the inverting input terminal of the IC chip 13. Capacitors 63p and 63n are provided outside the feedback loops 20p and 20n. The capacitors 63p and 63n transmit the received signal received by the couplers 31p and 31n to the IC chip 13. That is, the received signal received by the coupler 31p is input to the non-inverting input terminal of the IC chip 13 via the capacitor 63p. The received signal received by the coupler 31n is input to the inverting input terminal of the IC chip 13 via the capacitor 63n.
　本実施形態ではキャパシタ２２ｐ、２２ｎによる正帰還を用いている。つまり、帰還ループ２０ｐ、２０ｎは、実施の形態１と同様にＩＣチップ１３の入力を出力に正帰還する。よって、通信回路１は、実施形態１と同様に動作をするため、同様の効果を得ることができる。 In this embodiment, positive feedback by capacitors 22p and 22n is used. That is, the feedback loops 20p and 20n positively feed back the input of the IC chip 13 to the output as in the first embodiment. Therefore, since the communication circuit 1 operates in the same manner as in the first embodiment, the same effect can be obtained.
　キャパシタ２２ｐ、２２ｎの容量値をＣとし、キャパシタ６３ｐ、６３ｎの容量値をＣ１とする。結合器３１の出力パルス信号の振幅をＶｃ、ＩＣチップ１３の出力からキャパシタ２２ｐ、２２ｎで正帰還される信号の振幅をＶｆｂとする。ＩＣチップ１３の入力のノードで電荷が保存されるため、ＩＣチップ１３の入力電位ＶｉｎをＶｃ、Ｖｆｂで表すと、以下の式（２）となる。
Ｃ１（Ｖｉｎ－Ｖｃ）＋Ｃ（Ｖｉｎ－Ｖｆｂ）＝０　　・・・（２） Let C be the capacitance value of the capacitors 22p and 22n, and C1 be the capacitance value of the capacitors 63p and 63n. Let Vc be the amplitude of the output pulse signal of the coupler 31, and Vfb be the amplitude of the signal positively fed back from the output of the IC chip 13 by the capacitors 22p and 22n. Since the electric charge is stored at the input node of the IC chip 13, the input potential Vin of the IC chip 13 is expressed by Vc and Vfb by the following equation (2).
C1 (Vin-Vc) + C (Vin-Vfb) = 0 ... (2)
　式（２）をＶｉｎで解くと、式（３）のようになる。
Ｖｉｎ＝Ｖｃ／｛（１＋（Ｃ／Ｃ１））＋Ｖｆｂ／｛（１＋（Ｃ１／Ｃ））　・・・（３） Solving equation (2) with Vin yields equation (3).
Vin = Vc / {(1+ (C / C1)) + Vfb / {(1+ (C1 / C)) ... (3)
　従って、比較器の入力しきい値のヒステリシス幅をＣ１／Ｃで調整することができる。例えば、ＶＤＤ－＝１．８Ｖのとき、Ｃ１＝１ｎＦ、Ｃ＝２３ｐＦとすると、ｖ＿ｈｙｓ＝４０ｍＶとなる。ＶＤＤが±５Ｖで、Ｖｂ＝０Ｖの場合に、７０ｍＶのヒステリシス幅を得るためには、Ｃ１＝１ｎＦ、Ｃ＝７ｐＦとなる。ここでは、容量値Ｃ１を容量値Ｃよりも大きくしている。 Therefore, the hysteresis width of the input threshold of the comparator can be adjusted with C1 / C. For example, when VDD− = 1.8V and C1 = 1nF and C = 23pF, v_hys = 40mV. When VDD is ± 5V and Vb = 0V, in order to obtain a hysteresis width of 70 mV, C1 = 1nF and C = 7pF. Here, the capacity value C1 is made larger than the capacity value C.
　キャパシタ２２ｐとキャパシタ２２ｎは同じ容量値Ｃを有している。キャパシタ６３ｐとキャパシタ６３ｎは同じ容量値Ｃ１を有している。容量値Ｃ１は容量値Ｃよりも大きくなっていることが好ましい。容量値Ｃ１と容量値Ｃの比（Ｃ１／Ｃ）は、１０～１０００とすることが好ましい。つまり、容量値Ｃ１は容量値Ｃの１０倍から１０００倍程度とすることが好ましい The capacitor 22p and the capacitor 22n have the same capacitance value C. The capacitor 63p and the capacitor 63n have the same capacitance value C1. The capacitance value C1 is preferably larger than the capacitance value C. The ratio (C1 / C) of the capacitance value C1 to the capacitance value C is preferably 10 to 1000. That is, the capacity value C1 is preferably about 10 to 1000 times the capacity value C.
　なお、比較器の入力同相電位を定めるために、ＩＣチップ１３の入力に抵抗５３，５４でＶｂにバイアスしている。抵抗５３、５４の抵抗値ｒは、上記電荷の保存の時定数で決めることができる。例えば、時定数を１μｓｅｃにしたければ、Ｃ１＝１ｎＦのとき、rは約１ｋΩとなる In order to determine the input common mode potential of the comparator, the input of the IC chip 13 is biased to Vb with resistors 53 and 54. The resistance value r of the resistors 53 and 54 can be determined by the time constant of charge conservation. For example, if the time constant is set to 1 μsec, r is about 1 kΩ when C1 = 1 nF.
　図９は、Ｃ１＝４００ｐＦ、Ｃ＝１２ｐＦ、ｒ＝２ｋΩとしたときの過渡応答を示すシミュレーション結果である。図９は、５Ｇｐｓで信号を伝送したときの波形図を示している。ここでは、結合器３１を用いて受信した受信信号を比較器に入力したときの、入力電位ＶＩＰ、ＶＯＮと出力電位ＶＯＰ、ＶＯＮの波形を示している。本実施の形態の構成によれば、比較器ＣＯＭの入力信号に正帰還された信号成分が加わることになる。よって、実施の形態１と同様の効果を得ることができる。 FIG. 9 is a simulation result showing a transient response when C1 = 400pF, C = 12pF, and r = 2kΩ. FIG. 9 shows a waveform diagram when a signal is transmitted at 5 Gps. Here, the waveforms of the input potentials VIP and VON and the output potentials VOP and VON when the received signal received by the coupler 31 is input to the comparator are shown. According to the configuration of the present embodiment, the positive feedback signal component is added to the input signal of the comparator COM. Therefore, the same effect as that of the first embodiment can be obtained.
　実施の形態３．
　実施の形態３について、図１０を用いて説明する。図１０は、実施の形態３にかかる通信回路１の構成を示すブロック図である。なお、実施の形態３では、実施の形態１の構成にＩＣチップ７０が追加されている。つまり、基板２には、２つのＩＣチップ１３，及びＩＣチップ７０が実装されている。さらに、実施の形態３では、帰還ループ２０ｐ、２０ｎがＩＣチップ１３ではなく、ＩＣチップ７０に設けられている。本実施の形態では、ＩＣチップ７０を用いることでＩＣチップ１３の比較器ＣＯＭにヒステリシスを持たせている。 Embodiment 3.
The third embodiment will be described with reference to FIG. FIG. 10 is a block diagram showing the configuration of the communication circuit 1 according to the third embodiment. In the third embodiment, the IC chip 70 is added to the configuration of the first embodiment. That is, two IC chips 13 and an IC chip 70 are mounted on the substrate 2. Further, in the third embodiment, the feedback loops 20p and 20n are provided not on the IC chip 13 but on the IC chip 70. In the present embodiment, the IC chip 70 is used to give hysteresis to the comparator COM of the IC chip 13.
　実施の形態１と同様の構成については適宜説明を省略する。例えば、結合器３１は実施の形態１と同様である。また、抵抗５７は、抵抗５１，５２に対応し、抵抗５８は抵抗５３，５４に対応する。よって、これらの構成については、説明を省略する。 The description of the same configuration as that of the first embodiment will be omitted as appropriate. For example, the coupler 31 is the same as in the first embodiment. Further, the resistor 57 corresponds to the resistors 51 and 52, and the resistor 58 corresponds to the resistors 53 and 54. Therefore, description of these configurations will be omitted.
　結合器３１ｐ、３１ｎはＩＣチップ１３に接続されている。結合器３１ｐはＩＣチップ１３の非反転入力端子と接続され、結合器３１ｎはＩＣチップ１３の反転入力端子と接続されている。ＩＣチップ１３は、実施の形態１と同様に、ヒステリシスのない比較器ＣＯＭを有している。よって、ＩＣチップ１３の結合器３１ｐ、３１ｎからの差動の受信信号の電圧レベルを比較する。 The couplers 31p and 31n are connected to the IC chip 13. The coupler 31p is connected to the non-inverting input terminal of the IC chip 13, and the coupler 31n is connected to the inverting input terminal of the IC chip 13. The IC chip 13 has a comparator COM without hysteresis, as in the first embodiment. Therefore, the voltage levels of the differential received signals from the couplers 31p and 31n of the IC chip 13 are compared.
　結合器３１ｐとＩＣチップ１３の非反転入力端子との間には、分岐ノードＢＰが設けられている。分岐ノードＢＰは、ＩＣチップ７０の非反転入力端子に接続されている。結合器３１ｎとＩＣチップ１３の反転入力端子との間には、分岐ノードＢＮが設けられている。分岐ノードＢＮは、ＩＣチップ７０の反転入力端子に接続されている。よって、ＩＣチップ７０には、結合器３１ｐ、３１ｎからの受信信号が入力される。つまり、結合器３１ｐからの受信信号は分岐ノードＢＰを介して、ＩＣチップ７０に入力される。結合器３１ｎからの受信信号は分岐ノードＢＮを介して、ＩＣチップ７０に入力される。 A branch node BP is provided between the coupler 31p and the non-inverting input terminal of the IC chip 13. The branch node BP is connected to the non-inverting input terminal of the IC chip 70. A branch node BN is provided between the coupler 31n and the inverting input terminal of the IC chip 13. The branch node BN is connected to the inverting input terminal of the IC chip 70. Therefore, the received signals from the couplers 31p and 31n are input to the IC chip 70. That is, the received signal from the coupler 31p is input to the IC chip 70 via the branch node BP. The received signal from the coupler 31n is input to the IC chip 70 via the branch node BN.
　ＩＣチップ７０は図２のＩＣチップ１３と同様の構成を有している。ＩＣチップ７０は、ヒステリシスのない比較器ＣＯＭを有している。ＩＣチップ７０の比較器ＣＯＭは、結合器３１からの２つの受信信号のレベルを比較する。帰還ループ２０ｐ、２０ｎは、ＩＣチップ７０の出力を入力に帰還している。帰還ループ２０ｐには、抵抗２１ｐが設けられ、帰還ループ２０ｎには抵抗２１ｎが設けられている。したがって、帰還ループ２０ｐ、２０ｎは、ＩＣチップ７０の出力と入力とに抵抗２１ｐ、２１ｎで正帰還を与えている。 The IC chip 70 has the same configuration as the IC chip 13 of FIG. The IC chip 70 has a comparator COM without hysteresis. The comparator COM of the IC chip 70 compares the levels of two received signals from the coupler 31. The feedback loops 20p and 20n feed back the output of the IC chip 70 to the input. The feedback loop 20p is provided with a resistor 21p, and the feedback loop 20n is provided with a resistor 21n. Therefore, the feedback loops 20p and 20n provide positive feedback to the output and input of the IC chip 70 with resistors 21p and 21n.
　さらに、ＩＣチップ７０の出力は、帰還ループ２０ｐ、２０ｎ、及び分岐ノードＢＰ、ＢＮを介して、ＩＣチップ１３の入力に接続される。したがって、ＩＣチップ１３の入力信号に正帰還された信号成分が加わることになる。本実施の形態では、ＩＣチップ７０を用いて、ＩＣチップ１３の比較器にヒステリシス幅を持たせることができる。これにより、実施の形態１、２と同様に、ＩＣチップ１３が適切にデジタル信号を復元することができる。 Further, the output of the IC chip 70 is connected to the input of the IC chip 13 via the feedback loops 20p and 20n, and the branch nodes BP and BN. Therefore, the positively fed signal component is added to the input signal of the IC chip 13. In the present embodiment, the IC chip 70 can be used to give the comparator of the IC chip 13 a hysteresis width. As a result, the IC chip 13 can appropriately restore the digital signal as in the first and second embodiments.
　例えば、ＩＣチップ１３がシリアルパラレル変換器（以下、Ｓ／Ｐ変換器とする）を備える場合、比較器ＣＯＭの出力がシリアルパラレル変換された後に、ＩＣチップ１３から出力される。この場合、ＩＣチップ１３の出力から入力に抵抗２１ｐ、２１ｎで正帰還を与えることができなくなる。これに対して、本実施の形態では、ＩＣチップ１３として、Ｓ／Ｐ変換器を有する受信器チップを用いることができる。ＩＣチップ１３がシリアルパラレル変換器を有する場合であっても、ＩＣチップ１３の比較器にヒステリシスを持たせることができる。 For example, when the IC chip 13 includes a serial-parallel converter (hereinafter referred to as an S / P converter), the output of the comparator COM is serial-parallel converted and then output from the IC chip 13. In this case, it becomes impossible to give positive feedback from the output of the IC chip 13 to the input with the resistors 21p and 21n. On the other hand, in the present embodiment, a receiver chip having an S / P converter can be used as the IC chip 13. Even when the IC chip 13 has a serial-parallel converter, the comparator of the IC chip 13 can have hysteresis.
　あるいは、ＩＣチップ７０の比較器ＣＯＭは、ＩＣチップ１３の比較器よりもデータの転送速度が遅くなっていてもよい。このような場合であっても、ＩＣチップ１３の比較器にヒステリシスを与えることができる。あるいは、ＩＣチップ１３の信号伝搬遅延ｔｐｄが結合器３１のデータ転送のサイクル時間に比べて遅い場合に、信号伝搬遅延ｔｐｄの速いＩＣチップ７０を用いることで、ヒステリシスを適切に与えることができる。 Alternatively, the comparator COM of the IC chip 70 may have a slower data transfer rate than the comparator of the IC chip 13. Even in such a case, hysteresis can be given to the comparator of the IC chip 13. Alternatively, when the signal propagation delay tpd of the IC chip 13 is slower than the data transfer cycle time of the coupler 31, the hysteresis can be appropriately provided by using the IC chip 70 having a fast signal propagation delay tpd.
　なお、図１０では、抵抗２１を用いて帰還ループ２０を構成したが、実施の形態２にように容量を用いて帰還ループを構成してもよい。この場合、図８に示すようなキャパシタ２２、及びキャパシタ６３をＩＣチップ７０に設ければよい。 Although the feedback loop 20 is configured by using the resistor 21 in FIG. 10, the feedback loop may be configured by using the capacitance as in the second embodiment. In this case, the capacitor 22 and the capacitor 63 as shown in FIG. 8 may be provided on the IC chip 70.
　図１１は、ＩＣチップ１３とＩＣチップ７０の構成を示すブロック図である。ＩＣチップ７０は、図２のＩＣチップ１３と同様の構成を有している。すなわち、ＩＣチップ７０の等価器１７１、受信回路１７２、ＣＤＲ回路１７３、出力回路１７４は図２の等価器１３１、受信回路１３２、ＣＤＲ回路１３３、及び出力回路１３４と同様である。このため、ため説明を省略する。受信回路１７２は図２のようにヒステリシスのない比較器である。ＩＣチップ７０はＳ／Ｐ変換器を有していない受信チップである。 FIG. 11 is a block diagram showing the configurations of the IC chip 13 and the IC chip 70. The IC chip 70 has the same configuration as the IC chip 13 of FIG. That is, the equivalent device 171, the receiving circuit 172, the CDR circuit 173, and the output circuit 174 of the IC chip 70 are the same as the equivalent device 131, the receiving circuit 132, the CDR circuit 133, and the output circuit 134 of FIG. Therefore, the description thereof will be omitted. The receiving circuit 172 is a comparator without hysteresis as shown in FIG. The IC chip 70 is a receiving chip that does not have an S / P converter.
　ＩＣチップ１３は、図２のＩＣチップ１３に対して、Ｓ／Ｐ変換器１３５が追加されている。受信回路１３２は図２のようにヒステリシスのない比較器ＣＯＭである。Ｓ／Ｐ変換器１３５は、受信回路１３２の後段に配置されており、受信回路１３２で復元されたデータをシリアルパラレル変換する。 The IC chip 13 has an S / P converter 135 added to the IC chip 13 shown in FIG. The receiving circuit 132 is a comparator COM having no hysteresis as shown in FIG. The S / P converter 135 is arranged after the receiving circuit 132, and serial-parallel converts the data restored by the receiving circuit 132.
　例えば、Ｓ／Ｐ変換器１３５は、シフトレジスタなどを備えている。Ｓ／Ｐ変換器１３５は、ＣＤＲ回路１３３で分離されたクロック信号に応じて、データを順次保持していき、パラレルデータに変換する。Ｓ／Ｐ変換器１３５で変換されたパラレルデータがＩＣチップ１３から出力される。なお、図１１では、説明の簡略化のため、パラレルデータを２ビットとしているため、４つの出力端子ＯＵＴ１Ｐ、ＯＵＴ１Ｎ、ＯＵＴ２Ｐ、ＯＵＴ２Ｎのみが示されているが、パラレルデータのビット長は３ビット以上であってもよい。 For example, the S / P converter 135 includes a shift register and the like. The S / P converter 135 sequentially holds data according to the clock signals separated by the CDR circuit 133 and converts the data into parallel data. The parallel data converted by the S / P converter 135 is output from the IC chip 13. In FIG. 11, since the parallel data is set to 2 bits for simplification of the description, only the four output terminals OUT1P, OUT1N, OUT2P, and OUT2N are shown, but the bit length of the parallel data is 3 bits or more. It may be.
　本実施の形態では、ＩＣチップ１３，及びＩＣチップ７０が汎用の半導体チップとすることができる。つまり、ヒステリシスを有していない比較器を有するＩＣチップを２つ用意して、基板２上に実装する。ＩＣチップ１３，及びＩＣチップ７０として、入手が容易な市販の受信チップを用いることができるため、ヒステリシス比較器、及び通信回路を安価に実現することができる。ＩＣチップ１３，及びＩＣチップ７０の比較器は、ヒステリシスを有していない比較器に限らず、ヒステリシス幅の小さい比較器であってもよい。 In the present embodiment, the IC chip 13 and the IC chip 70 can be general-purpose semiconductor chips. That is, two IC chips having a comparator having no hysteresis are prepared and mounted on the substrate 2. Since a commercially available receiving chip that is easily available can be used as the IC chip 13 and the IC chip 70, a hysteresis comparator and a communication circuit can be realized at low cost. The comparators of the IC chip 13 and the IC chip 70 are not limited to the comparators having no hysteresis, and may be a comparator having a small hysteresis width.
　なお、本発明は上記実施の形態に限られたものではなく、趣旨を逸脱しない範囲で適宜変更することが可能である。 The present invention is not limited to the above embodiment, and can be appropriately modified without departing from the spirit.
　この出願は、２０１９年４月２４日に出願された日本出願特願２０１９－８２６１６を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims priority based on Japanese application Japanese Patent Application No. 2019-82616 filed on April 24, 2019, and incorporates all of its disclosures herein.
　１　通信回路
　２　基板
　１３　ＩＣチップ
　１４　バッファ
　２０ｐ　帰還ループ
　２０ｎ　帰還ループ
　２１ｐ　抵抗
　２１ｎ　抵抗
　３１ｐ　結合器
　３１ｎ　結合器
　４１ｐ　出力端子
　４１ｎ　出力端子
　５１　抵抗
　５２　抵抗
　５３　抵抗
　５４　抵抗
　７０　ＩＣチップ
　１３１　等価器
　１３２　受信回路
　１３３　ＣＤＲ回路
　１３４　出力回路
　１３５　Ｓ／Ｐ変換器 1 Communication circuit 2 Board 13 IC chip 14 Buffer 20p Feedback loop 20n Feedback loop 21p Resistance 21n Resistance 31p Coupler 31n Coupler 41p Output terminal 41n Output terminal 51 Resistance 52 Resistance 53 Resistance 54 Resistance 70 IC chip 131 Equivalent device 132 Receiver circuit 133 CDR circuit 134 Output circuit 135 S / P converter

Claims (10)

  1. 　基板と、
    　前記基板に設けられた電磁界結合器と、
    　前記電磁界結合器で受信された受信信号のレベルを比較する第１の比較器を有し、前記基板に実装された第１のＩＣチップと、
    　前記受信信号のレベルを比較する第２の比較器を有し、前記基板に実装された第２のＩＣチップと、
    　前記第２のＩＣチップの出力を入力に正帰還する帰還ループと、を備えた通信回路。     With the board
    With the electromagnetic field coupler provided on the substrate,
    A first IC chip having a first comparator for comparing the levels of received signals received by the electromagnetic field coupler and mounted on the substrate, and a first IC chip.
    A second IC chip having a second comparator for comparing the levels of the received signals and mounted on the substrate,
    A communication circuit including a feedback loop that positively feeds back the output of the second IC chip to an input.
  2. 　前記第１のＩＣチップが、前記第１の比較器の後段に配置されたシリアルパラレル変換器を有している請求項１に記載の通信回路。 The communication circuit according to claim 1, wherein the first IC chip has a serial-parallel converter arranged after the first comparator.
  3. 　前記帰還ループにキャパシタが設けられている請求項１、又は２に記載の通信回路。 The communication circuit according to claim 1 or 2, wherein a capacitor is provided in the feedback loop.
  4. 　前記帰還ループに抵抗が設けられている請求項１、又は２に記載の通信回路。 The communication circuit according to claim 1 or 2, wherein a resistor is provided in the feedback loop.
  5. 　基板と、
    　前記基板に設けられた電磁界結合器と、
    　前記電磁界結合器で受信された受信信号のレベルを比較する比較器を有し、前記基板に実装されたＩＣチップと、
    　前記基板に設けられた第１キャパシタを有し、前記ＩＣチップの出力を入力に正帰還する帰還ループと、
    　前記電磁界結合器と前記ＩＣチップとの間に配置された第２のキャパシタと、を備えた通信回路。     With the board
    With the electromagnetic field coupler provided on the substrate,
    An IC chip mounted on the substrate, which has a comparator for comparing the levels of received signals received by the electromagnetic field coupler, and
    A feedback loop that has a first capacitor provided on the substrate and positively feeds back the output of the IC chip to the input.
    A communication circuit including a second capacitor arranged between the electromagnetic field coupler and the IC chip.
  6. 　基板と、
    　前記基板に設けられた電磁界結合器と、
    　前記電磁界結合器で受信された受信信号のレベルを比較する比較器を有し、前記基板に実装されたＩＣチップと、
    　前記基板に設けられた抵抗を有し、前記ＩＣチップの出力を入力に正帰還する帰還ループと、を備えた通信回路。     With the board
    With the electromagnetic field coupler provided on the substrate,
    An IC chip mounted on the substrate, which has a comparator for comparing the levels of received signals received by the electromagnetic field coupler, and
    A communication circuit having a resistor provided on the substrate and including a feedback loop that positively feeds back the output of the IC chip to an input.
  7. 　基板と、
    　２つの入力信号のレベルを比較する第１の比較器を有し、前記基板に実装された第１のＩＣチップと、
    　前記２つの入力信号のレベルを比較する第２の比較器を有し、前記基板に実装された第２のＩＣチップと、
    　前記第２のＩＣチップの出力を入力に正帰還する帰還ループと、を備えたヒステリシス比較器。     With the board
    A first comparator that has a first comparator that compares the levels of two input signals, and a first IC chip mounted on the substrate.
    A second IC chip having a second comparator that compares the levels of the two input signals and mounted on the substrate, and a second IC chip.
    A hysteresis comparator comprising a feedback loop that positively feeds back the output of the second IC chip to an input.
  8. 　前記第１のＩＣチップが、前記第１の比較器の後段に配置されたシリアルパラレル変換器を有している請求項７に記載のヒステリシス比較器。 The hysteresis comparator according to claim 7, wherein the first IC chip has a serial-parallel converter arranged after the first comparator.
  9. 　前記帰還ループにキャパシタが設けられている請求項７、又は８に記載のヒステリシス比較器。 The hysteresis comparator according to claim 7 or 8, wherein a capacitor is provided in the feedback loop.
  10. 　前記帰還ループに抵抗が設けられている請求項７、又は８に記載のヒステリシス比較器。 The hysteresis comparator according to claim 7 or 8, wherein a resistor is provided in the feedback loop.
PCT/JP2020/017609 2019-04-24 2020-04-24 Hysteresis comparator and communication circuit WO2020218472A1 (en)

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Citations (3)

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JP2004274360A (en) * 2003-03-07 2004-09-30 Fujitsu Ltd Amplifier circuit, receiving circuit and optical receiving circuit
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