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WO2020255347A1 - Micro led device and method for manufacturing same - Google Patents

Micro led device and method for manufacturing same Download PDF

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Publication number
WO2020255347A1
WO2020255347A1 PCT/JP2019/024564 JP2019024564W WO2020255347A1 WO 2020255347 A1 WO2020255347 A1 WO 2020255347A1 JP 2019024564 W JP2019024564 W JP 2019024564W WO 2020255347 A1 WO2020255347 A1 WO 2020255347A1
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WO
WIPO (PCT)
Prior art keywords
layer
semiconductor layer
mask
μled
contact
Prior art date
Application number
PCT/JP2019/024564
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French (fr)
Japanese (ja)
Inventor
克彦 岸本
Original Assignee
堺ディスプレイプロダクト株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 堺ディスプレイプロダクト株式会社 filed Critical 堺ディスプレイプロダクト株式会社
Priority to PCT/JP2019/024564 priority Critical patent/WO2020255347A1/en
Publication of WO2020255347A1 publication Critical patent/WO2020255347A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes

Definitions

  • This disclosure relates to a micro LED device and a method for manufacturing the same.
  • Patent Document 1 discloses a display device including a large number of micro LEDs transferred onto a TFT substrate and a method for manufacturing the same.
  • Patent Document 2 discloses a display device including a GaN wafer on which a plurality of LEDs are formed and a backplane control unit (TFT substrate) to which the GaN wafers are bonded, and a method for manufacturing the display device.
  • TFT substrate backplane control unit
  • the method of transferring a large number of micro LEDs onto the TFT substrate has a problem that the size of the micro LEDs becomes small and the number of the micro LEDs increases, it becomes difficult to align the micro LEDs with respect to the TFT substrate. Further, the method of joining the GaN wafer to the backplane control unit also requires a complicated process of transferring the GaN wafer to the wafer temporarily holding the GaN wafer and further mounting the GaN wafer on the backplane control unit.
  • the present disclosure provides a new structure and manufacturing method of a micro LED device that can solve the above problems.
  • the micro LED device of the present disclosure is an insulating crystal growth substrate whose upper surface is covered with a mask layer having a plurality of openings, and a front plane supported by the crystal growth substrate.
  • Each includes a plurality of microLEDs each having a first conductive type first semiconductor layer and a second conductive type second semiconductor layer, and an element separation region located between the plurality of microLEDs.
  • a front plane having at least one metal plug electrically connected to the second semiconductor layer and an intermediate layer supported by the front plane, each of the plurality of microLEDs.
  • An intermediate layer including a plurality of first contact electrodes electrically connected to the first semiconductor layer and at least one second contact electrode connected to the metal plug, and a back plane supported by the intermediate layer.
  • the electric circuit includes an electric circuit electrically connected to the plurality of micro LEDs via the plurality of first contact electrodes and the at least one second contact electrode, and the electric circuit includes a plurality of thin film transistors.
  • the mask layer is formed of a conductive material, and the mask layer has a plurality of mask openings defining the positions of the plurality of micro LEDs and a connection portion connected to the metal plug.
  • the first semiconductor layer and the second semiconductor layer of the micro LED are epitaxial layers selectively grown from the plurality of mask openings of the mask layer, and the second semiconductor layer is ohmic to the mask layer. Are in contact.
  • Each of the plurality of thin film transistors has a semiconductor layer grown on the front plane and / or the intermediate layer.
  • the mask layer is in electrical resistant or insulating contact with the first semiconductor layer.
  • the second semiconductor layer partially overlaps the mask layer.
  • the conductive type of the second semiconductor layer is p-type
  • the mask layer is at least one refractory metal selected from the group consisting of Ti, Cr, Mo, Mn, W, and Ta. Is formed from.
  • an insulating layer that insulates the mask layer from the first semiconductor layer is provided on the mask layer.
  • the second semiconductor layer has a portion that grows laterally on the mask layer, and the portion that grows laterally partially overlaps the insulating layer. ing.
  • the mask opening has a different size or shape depending on its position on the substrate, and the size or shape of the mask opening is the size or shape of the light emitted from each micro LED. Define the wavelength.
  • the element separation region of the front plane has an embedded insulator that fills between the plurality of micro LEDs, the embedded insulator being at least one through hole for the metal plug. have.
  • the front plane has a flat surface, which is in contact with the intermediate layer.
  • the intermediate layer comprises an interlayer insulating layer having a flat surface, and the interlayer insulating layer connects the plurality of first contact electrodes and the at least one second contact electrode to the electric circuit, respectively. It has a plurality of contact holes for forming the contact holes and via electrodes for filling the contact holes.
  • each of the plurality of thin film transistors has a source electrode, a drain electrode, and a gate electrode formed on the flat surface of the interlayer insulating layer, and the semiconductor layer is the gate electrode. It is located above and is in contact with the upper surfaces of the source electrode and the drain electrode.
  • each of the plurality of thin film transistors has a source electrode, a drain electrode, and a gate electrode located above the semiconductor layer, and the semiconductor layer is a flat surface of the interlayer insulating layer. A part of the semiconductor layer is formed above, and is sandwiched from above and below by at least one of the source electrode and the drain electrode and the via electrode.
  • the method for manufacturing the micro LED device of the present disclosure is, in an exemplary embodiment, a front plane supported by an insulating crystal growth substrate, the first semiconductor layer of the first conductive type and the second conductive type, respectively.
  • the element separation region includes a plurality of micro LEDs having the second semiconductor layer, and an element separation region located between the plurality of micro LEDs, and the element separation region is electrically connected to the second semiconductor layer.
  • the steps of preparing the laminated structure are a step of forming the mask layer which is a mask layer covering the crystal growth substrate and has a plurality of mask openings defining the positions of the plurality of micro LEDs, and a step of forming the mask. This includes a step of sequentially growing the second semiconductor layer and the first semiconductor layer from the opening.
  • the mask layer is formed of a conductive material
  • the second semiconductor layer is in ohmic contact with the mask layer
  • the steps of forming the back plane include a step of depositing the semiconductor layer on the laminated structure and the step of depositing the semiconductor layer on the laminated structure. It includes a step of patterning the semiconductor layer on the laminated structure.
  • the shape and position of the element separation region is defined by the second semiconductor layer and the first semiconductor layer selectively grown from the plurality of mask openings of the mask layer.
  • the step of preparing the laminated structure is a step of sequentially epitaxially growing the second semiconductor layer and the first semiconductor layer from the plurality of mask openings, and then the mask layer and the second. Includes a heat treatment step to complete ohmic contact with the semiconductor layer.
  • the heat treatment step is performed before the front plane is completed.
  • ohmic contact between the mask layer and the second semiconductor layer is performed by heating during a step of sequentially epitaxially growing the second semiconductor layer and the first semiconductor layer from the plurality of mask openings.
  • a micro LED device that solves the above-mentioned problems and a method for manufacturing the same are provided.
  • micro LED in the present disclosure means a light emitting diode (LED) having a size included in an area of 100 ⁇ m ⁇ 100 ⁇ m in which the size of the occupied area is 100 ⁇ m ⁇ 100 ⁇ m.
  • the "light” emitted by the micro LED is not limited to visible light, but includes a wide range of visible, ultraviolet, or infrared electromagnetic waves.
  • micro LED may be referred to as " ⁇ LED”.
  • the ⁇ LED has a first conductive type first semiconductor layer and a second conductive type second semiconductor layer.
  • the first conductive type is one of the p-type and the n-type
  • the second conductive type is the other of the p-type and the n-type.
  • the first conductive type is p type
  • the second conductive type is n type
  • the first conductive type is n type
  • the second conductive type is p type.
  • Each of the first semiconductor layer and the second semiconductor layer may have a single-layer structure or a multi-layer structure.
  • a light emitting layer having at least one quantum well (or double heterostructure) is formed between the first semiconductor layer and the second semiconductor layer.
  • micro LED device in the present disclosure is a device including a plurality of ⁇ LEDs.
  • a plurality of ⁇ LEDs in a ⁇ LED device may be referred to as a “ ⁇ LED array”.
  • a typical example of a ⁇ LED device is a display device, but the ⁇ LED device is not limited to a display device.
  • FIG. 1A is a cross-sectional view showing a part of the ⁇ LED device 1000.
  • FIG. 1B is a plan view showing an arrangement example of the ⁇ LED array in the ⁇ LED device 1000.
  • the cross section of the ⁇ LED device 1000 shown in FIG. 1A corresponds to the cross section taken along line AA of FIG. 1B.
  • the ⁇ LED device 1000 may include a large number of ⁇ LEDs, for example, exceeding 1 million.
  • 1A and 1B show only a portion of the ⁇ LED device 1000 containing a few ⁇ LEDs.
  • the entire ⁇ LED device 1000 has a configuration in which the illustrated portions are periodically arranged.
  • the ⁇ LED device 1000 includes an insulating crystal growth substrate 100, a front plane 200 supported by the crystal growth substrate 100, an intermediate layer 300 supported by the front plane 200, and a backplane 400 supported by the intermediate layer. I have.
  • FIGS. 1A and 1B show right-handed coordinate axes of the X-axis, Y-axis, and Z-axis that are orthogonal to each other.
  • the crystal growth substrate 100 is a substrate on which semiconductor crystals constituting the ⁇ LED grow epitaxially.
  • a crystal growth substrate is simply referred to as a "substrate”.
  • the surface 100T on which crystal growth of the substrate 100 occurs is referred to as an "upper surface” or “crystal growth surface”, and the surface 100B on the opposite side of the substrate 100 is referred to as a “lower surface”.
  • the terms “top” and “bottom” are used independently of the actual orientation of the substrate 100.
  • a typical example of a semiconductor crystal that can be used in the embodiment of the present disclosure is a gallium nitride based compound semiconductor.
  • the gallium nitride based compound semiconductor may be referred to as “GaN”.
  • a part of the gallium (Ga) atom in GaN may be replaced by an aluminum (Al) atom or an indium (In) atom.
  • AlGaN aluminum
  • InGaN in which a part of Ga atom is replaced with In atom
  • GaN in which a part of Ga atom is replaced with In atom may be referred to as "InGaN”.
  • GaN in which a part of Ga atom is replaced with Al atom and In atom may be referred to as "AlInGaN” or “InAlGaN".
  • the bandgap of GaN is smaller than the bandgap of AlGaN and larger than the bandgap of InGaN.
  • gallium nitride based compound semiconductors in which some of the constituent atoms are replaced with other atoms may be collectively referred to as “GaN”.
  • the "GaN” can be doped with n-type impurities and / or p-type impurities as impurity ions.
  • the semiconductor crystal constituting the ⁇ LED is not limited to the GaN-based semiconductor, and may be formed of a nitride semiconductor such as AlN, InN, or AlInN, or another semiconductor.
  • the substrate 100 in the present disclosure has an insulating property, and the upper surface 100T of the substrate 100 is covered with a mask layer 150 having a plurality of openings.
  • the mask layer 150 can be formed of, for example, a refractory metal (conductive material) such as titanium (Ti), chromium (Cr), molybdenum (Mo), manganese (Mn), tungsten (W), and tantalum (Ta).
  • the mask layer 150 has a plurality of mask openings 150G that define the positions and arrangements of a plurality of ⁇ LED 220s, which will be described later, and a connection portion 150C that is connected to the metal plug 24.
  • the connection portion 150C is a portion of the mask layer 150 that is in contact with the metal plug 24.
  • Another conductive layer may be interposed between the connection portion 150C and the metal plug 24.
  • the substrate 100 is a sapphire substrate.
  • the sapphire substrate has high translucency for visible light and ultraviolet rays having a wavelength of 300 nm or more, and is particularly preferable as the insulating crystal growth substrate 100.
  • the substrate 100 is a component of the final ⁇ LED device 1000.
  • the thickness of the substrate 100 can be, for example, 30 ⁇ m or more and 1000 ⁇ m or less, preferably 500 ⁇ m or less.
  • the rigidity of the ⁇ LED device 1000 may be supplemented by a rigid member other than the substrate 100.
  • a rigid member can be fixed to, for example, the backplane 400.
  • a support substrate (not shown) that supplements the rigidity of the substrate 100 may be fixed to the lower surface 100B of the substrate 100.
  • Such a support substrate may be removed from the final ⁇ LED device 1000, or may be used while being fixed to the substrate 100.
  • the upper surface (crystal growth surface) 100T of the substrate 100 may be provided with a structure such as a groove or a ridge that alleviates the crystal lattice strain.
  • the lower surface 100B of the substrate 100 may be formed with fine irregularities for improving the extraction efficiency of the light radiated from the ⁇ LED array and transmitted through the substrate 100 or for diffusing the light. Examples of fine irregularities include a moth-eye structure. Since the moth-eye structure continuously changes the effective refractive index on the lower surface 100B of the substrate 100, the ratio (reflectance) reflected inside the substrate 100 on the lower surface 100B of the substrate 100 is significantly reduced (substantially). Can be zero).
  • the positive direction of the Z axis (direction of the arrow) shown in FIG. 1A may be referred to as “crystal growth direction” or “semiconductor lamination direction”.
  • the lower surface 100B and the upper surface 100T of the substrate 100 may be referred to as “front” and “back” of the substrate 100, respectively.
  • the front plane 200 includes a plurality of ⁇ LEDs 220 and an element separation region 240 located between the plurality of ⁇ LEDs 220.
  • the plurality of ⁇ LED 220s can be arranged in rows and columns in a two-dimensional plane (XY plane) parallel to the upper surface 100T of the substrate 100.
  • XY plane two-dimensional plane
  • each of the plurality of ⁇ LED 220s has a first conductive type first semiconductor layer 21 and a second conductive type second semiconductor layer 22, as shown in FIG. 1A.
  • the second semiconductor layer 22 of each ⁇ LED 220 is located in the region defined by the mask opening 150G of the mask layer 150.
  • the second semiconductor layer 22 is a semiconductor crystal that is selectively grown from a region exposed through the mask opening 150G on the upper surface 100T of the substrate 100. Is formed from.
  • ohmic contact is realized at the portion where the mask layer 150 and the second semiconductor layer 22 are in contact with each other. The heat treatment for achieving ohmic contact will be described later.
  • each ⁇ LED 220 has a light emitting layer 23 that can emit light independently of the other ⁇ LED 220.
  • the light emitting layer 23 is located between the first semiconductor layer 21 and the second semiconductor layer 22.
  • the element separation region 240 has at least one metal plug 24 electrically connected to the second semiconductor layer 22.
  • the metal plug 24 functions as a substrate-side electrode of the ⁇ LED 220. More specifically, the metal plug 24 connects the second semiconductor layers 22 of the plurality of ⁇ LED 220s to each other via the connecting portion 150C of the mask layer 150.
  • a typical example of the first conductive type first semiconductor layer 21 is a p-GaN layer.
  • a typical example of the second conductive type second semiconductor layer 22 is an n-GaN layer.
  • the p-GaN layer and the n-GaN layer do not have to have the same composition along the direction perpendicular to the upper surface 100T of the substrate 100 (semiconductor stacking direction: positive direction of the Z axis), and have a multilayer structure.
  • Ga in GaN can be at least partially replaced by Al and / or In. Such substitutions may be made to adjust the bandgap and / or index of refraction of the GaN.
  • the concentrations of p-type impurities and n-type impurities, that is, the doping level need not be uniform along the semiconductor stacking direction (positive direction of the Z axis).
  • a typical example of the light emitting layer 23 includes at least one InGaN well layer.
  • a GaN barrier layer or an AlGaN barrier layer having a bandgap larger than that of the InGaN well layer may be arranged between the InGaN well layers.
  • the InGaN well layer and the AlGaN barrier layer may be the InAlGaN well layer and the InAlGaN barrier layer, respectively.
  • the bandgap of the InGaN well layer defines the emission wavelength.
  • the bandgap Eg of the InGaN well layer may be adjusted to about 2.76 eV.
  • the bandgap of the InGaN well layer can be adjusted according to the In composition ratio in the InGaN well layer.
  • the bandgap can be similarly adjusted according to the In and Al composition ratio.
  • the In composition ratio in the InGaN well layer growing on the substrate 100 has substantially the same value on the entire surface of the substrate 100. Therefore, the plurality of ⁇ LED 220s formed on the same substrate 100 emit light having substantially the same wavelength.
  • the plurality of semiconductor layers constituting each ⁇ LED 220 are single crystal layers (epitaxial layers) epitaxially grown on the substrate 100, respectively.
  • the element separation region 240 is defined by a trench-shaped recess (hereinafter referred to as a “trench”) formed by a space between a plurality of semiconductor layers epitaxially grown on the substrate 100.
  • the occupied region of each ⁇ LED 220 separated by the trench has a size (for example, a region of 10 ⁇ m ⁇ 10 ⁇ m) included in the region of 100 ⁇ m ⁇ 100 ⁇ m.
  • the occupied area of the ⁇ LED 220 is defined by the contour of the first semiconductor layer 21 divided by the element separation area 240.
  • the element separation region 240 surrounds each ⁇ LED 220 and separates each ⁇ LED 220 from the other ⁇ LED 220. More specifically, the element separation region 240 electrically and spatially separates the first semiconductor layer 21 and the light emitting layer 23 of each ⁇ LED 220 from the first semiconductor layer 21 and the light emitting layer 23 of the other ⁇ LED 220. ing.
  • the element separation region 240 is a region located between a plurality of ⁇ LEDs 220 formed by selective growth of the semiconductor layer, and is not a recess formed by deeply etching the semiconductor layer. According to the embodiment of the present disclosure, steps such as lithography required for etching are not required, and damage to the semiconductor layer due to etching can be prevented.
  • the element separation region 240 has an embedded insulator 25 that fills the space between the plurality of ⁇ LEDs 220.
  • the embedded insulator 25 has one or more through holes for the metal plug 24. The through holes are filled with the metal material constituting the metal plug 24.
  • the metal plug 24 may have a structure in which different metal layers are stacked.
  • a plurality of metal plugs 24 are arranged discretely, but the embodiment of the present disclosure is not limited to such an example.
  • Each of the plurality of metal plugs 24 may have a ring shape surrounding the corresponding ⁇ LED 220. Further, the metal plug 24 may have a striped shape extending in parallel in one direction as shown in FIG. 1C, or may be a single conductor having a lattice shape as shown in FIG. 1D. Good.
  • the metal plug 24 does not transmit light. Therefore, when the metal plug 24 has a shape surrounding each ⁇ LED 220 (for example, when it has the shape of FIG. 1D), the metal plug 24 emits light emitted from each ⁇ LED 220 from another ⁇ LED 220. Produces the effect of preventing mixing with light.
  • a light-shielding member surrounding each ⁇ LED 220 may be separately provided in the element separation region 240. As described above, the element separation region 240 may have an additional function of optically separating the light emitting layer 23 of each ⁇ LED 220 from the light emitting layer 23 of another ⁇ LED 220.
  • the upper surface of the front plane 200 is flattened as shown in FIG. 1A.
  • Such flattening is realized by the level of the upper surface of the metal plug 24 and the embedded insulator 25 in the element separation region 240 substantially matching the level of the upper surface of the first semiconductor layer 21 in the ⁇ LED 220.
  • the intermediate layer 300 includes a plurality of first contact electrodes 31 and a second contact electrode 32 (see FIG. 1A). Each of the plurality of first contact electrodes 31 is electrically connected to the first semiconductor layer 21 of the plurality of ⁇ LED 220s. At least one second contact electrode 32 is connected to the metal plug 24.
  • FIG. 2 is a perspective view showing an arrangement example of the first contact electrode 31 and the second contact electrode 32.
  • the description of the backplane 400 is omitted.
  • the structure shown in FIG. 2 is only a part of the ⁇ LED device 1000, and as described above, the embodiment of the ⁇ LED device 1000 includes a large number of ⁇ LED 220s.
  • the second contact electrode 32 shown in FIG. 2 is electrically connected to the second semiconductor layer 22 via a metal plug 24.
  • the shape and size of the second contact electrode 32 are not limited to the examples shown. As described above, since the metal plug 24 can take various shapes, the degree of freedom in arranging the second contact electrode 32 is high as long as it is electrically connected to the second semiconductor layer 22 via the metal plug 24.
  • the first contact electrode 31 is independently electrically connected to the first semiconductor layer 21 of the plurality of ⁇ LED 220s. When viewed from a direction perpendicular to the upper surface 100T of the substrate 100, the shape and size of the first contact electrode 31 need not match the shape and size of the first semiconductor layer 21.
  • the distance from the substrate 100 to the first contact electrode 31 and the second contact electrode 32 in other words, the “height” of these contact electrodes 31 and 32.
  • “Or” level are equal to each other. This facilitates the formation of the backplane 400, which will be described later, using semiconductor manufacturing technology.
  • the "semiconductor manufacturing technique" in the present disclosure includes a step of depositing a thin film of a semiconductor, an insulator, or a conductor, and a step of patterning the thin film by a lithography and etching steps.
  • the "flattened surface” means a surface having a step difference of 300 nm or less due to a convex portion or a concave portion existing on the surface. In a preferred embodiment, this step is 100 nm or less.
  • the intermediate layer 300 includes an interlayer insulating layer 38 having a flat surface.
  • the interlayer insulating layer 38 has a plurality of contact holes for connecting the first and second contact electrodes 31 and 32 to the electric circuit of the backplane 400, respectively.
  • the contact hole is filled with the via electrode 36.
  • the upper surface of the interlayer insulating layer 38 it is preferable to flatten the upper surface of the interlayer insulating layer 38 before forming the backplane 400. By doing so, it becomes easy to form the backplane 400 on the upper surface of the interlayer insulating layer 38 by using the semiconductor manufacturing technique.
  • the upper surface of the intermediate layer 300 is flattened, the upper surface of the front plane 200 does not necessarily have to be flattened. However, if both the upper surface of the intermediate layer 300 and the upper surface of the front plane 200 are flattened, the formation of the electric circuit included in the backplane 400 becomes easier.
  • CMP chemical mechanical polishing
  • the backplane 400 has an electrical circuit (not shown) in FIG. 1A.
  • the electric circuit is electrically connected to the plurality of ⁇ LED 220s via the plurality of first contact electrodes 31 and at least one second contact electrode 32.
  • the electrical circuit includes a plurality of thin film transistors (TFTs) and other circuit elements. As will be described later, each of the TFTs has a semiconductor layer grown on the front plane 200 and / or the intermediate layer 300 supported by the substrate 100.
  • TFTs thin film transistors
  • FIG. 3 is a basic equivalent circuit diagram of sub-pixels when the ⁇ LED device 1000 functions as a display device.
  • One pixel of the display device may be composed of sub-pixels of different colors such as R, G, B and the like.
  • the electric circuit of the backplane 400 has a selection TFT element Tr1, a driving TFT element Tr2, and a holding capacitance CH.
  • the ⁇ LED shown in FIG. 3 resides in the front plane 200 rather than in the backplane 400.
  • the selection TFT element Tr1 is connected to the data line DL and the selection line SL.
  • the data line DL is a wiring that carries a data signal that defines an image to be displayed.
  • the data line DL is electrically connected to the gate of the driving TFT element Tr2 via the selection TFT element Tr1.
  • the selection line SL is a wiring that carries a signal for controlling on / off of the selection TFT element Tr1.
  • the driving TFT element Tr2 controls the conduction state between the power line PL and the ⁇ LED. When the driving TFT element Tr2 is turned on, a current flows from the power line PL to the ground line GL via the ⁇ LED. This current causes the ⁇ LED to emit light. Even if the selection TFT element Tr1 is turned off, the driving TFT element Tr2 is maintained in the ON state due to the holding capacitance CH.
  • the electric circuit of the backplane 400 may include a selection TFT element Tr1, a drive TFT element Tr2, a data line DL, a selection line SL, and the like, but the configuration of the electric circuit is not limited to such an example.
  • the ⁇ LED device 1000 in the present embodiment can function as a display device by itself, a plurality of ⁇ LED devices 1000 may be tiling to realize a display device having a larger display area.
  • a substrate 100 having an upper surface (crystal growth surface) 100T is prepared.
  • the substrate 100 in this embodiment is a sapphire substrate.
  • FIG. 4A shows only a part of the substrate 100 extending along a plane parallel to the upper surface 100T.
  • the upper surface 100T of the substrate 100 is covered with the mask layer 150.
  • the mask layer 150 is obtained by depositing a refractory metal film and then etching a predetermined region of the refractory metal film to form a plurality of mask openings 150G.
  • the lift-off method may be used to form the mask layer 150 having the mask opening 150G in a predetermined region.
  • the mask opening 150G partially exposes the upper surface 100T of the substrate 100.
  • the thickness of the mask layer 150 is, for example, in the range of 100 nm or more and 1000 nm or less (for example, about 300 nm).
  • the shape and position of the mask opening 150G defines the shape and position of the second semiconductor layer 22 of each ⁇ LED 220.
  • the shape of the mask opening 150G is rectangular, but the shape of the mask opening 150G is not limited to this example. Further, the arrangement of the mask opening 150G is not limited to the example shown in FIG. 4B.
  • the emission wavelength can be changed in a wide range. This makes it possible to simultaneously form a plurality of ⁇ LEDs 220 that emit light at different wavelengths on one substrate 100.
  • the second conductive type second semiconductor layer 22 is epitaxially grown from the exposed portion of the upper surface 100T of the substrate 100. At this time, the second semiconductor layer 22 does not epitaxially grow on the mask layer 150. However, a part of the second semiconductor layer 22 epitaxially grown from the mask opening 150G may grow laterally along the surface of the mask layer 150. At this time, it is preferable that ohmic contact is realized between the mask layer 150 and the second semiconductor layer 22. Heat treatment at an appropriate temperature is required to achieve particularly good ohmic contact. During the epitaxial growth step for forming the ⁇ LED 220, the mask layer 150 and the second semiconductor layer 22 are sufficiently heated, and as a result, ohmic contact may be completed.
  • the heating during crystal growth is insufficient to achieve ohmic contact, it is preferable to additionally perform a heat treatment to complete the ohmic contact after the epitaxial growth step for forming the ⁇ LED 22 is completed.
  • the lateral growth of the second semiconductor layer 22 expands the contact area between the second semiconductor layer 22 and the surface of the mask layer 150.
  • good ohmic contact between the second semiconductor layer 22 and the surface of the mask layer 150 is realized by heating during epitaxial growth or by performing appropriate heat treatment after a series of epitaxial growth. Therefore, the electrical resistance (contact resistance) between the second semiconductor layer 22 and the mask layer 150 decreases.
  • the length of the portion of the second semiconductor layer 22 that grows in the horizontal direction does not exceed the thickness of the portion that grows in the vertical direction.
  • the mask layer 150 has a high melting point of at least one selected from the group consisting of materials that realize good ohmic contact with the second semiconductor layer 22, for example, Ti, Cr, Mo, Mn, W, and Ta. It can be formed from metal. Since the work function of these refractory metals is 4.5 eV or less, good ohmic contact with the second semiconductor layer 22 can be formed when the second semiconductor layer 22 is n-type. Further, such a refractory metal exhibits high resistance even when it comes into contact with the light emitting layer 23 and the n-type first semiconductor layer 21.
  • the mask layer 150 exhibits electrical resistance to the light emitting layer 23 and the first semiconductor layer 21 that grow on the second semiconductor layer 22. As described above, the mask layer 150 withstands high temperatures during epitaxial growth of the semiconductor crystal and realizes good ohmic contact with the second semiconductor layer 22, while with respect to the light emitting layer 23 and the first semiconductor layer 21. Is desirable to exhibit electrical resistance.
  • each semiconductor layer is a single crystal epitaxial growth layer of a gallium nitride based compound semiconductor.
  • the gallium nitride based compound semiconductor can be grown by, for example, the MOCVD (Metal Organic Chemical Vapor Deposition) method. Impurities defining each conductive type can be doped from the gas phase during crystal growth.
  • the arrangement pitch (intercenter distance) of the ⁇ LED 220 is determined by the selective growth. It can be set to twice or more the height of the semiconductor layer (epitaxial growth layer) to be formed. Further, in the region where the metal plug 24 is formed, the arrangement pitch of the ⁇ LED 220 is determined so that the width of the trench is larger than the width of the metal plug 24. Even if the mask layer 150 having the same pattern is used, the size of the ⁇ LED 220 and the width of the trench can be changed by changing the height of the semiconductor layer formed by selective growth.
  • good ohmic contact is obtained between the refractory metal material constituting the mask layer 150 and the second semiconductor layer 22 by heating in a series of epitaxial growth. If heating during epitaxial growth is insufficient to obtain good ohmic contact, then after the epitaxial growth step, additional to obtain good ohmic contact between the surface of the second semiconductor layer 22 and the mask layer 150. It is preferable to perform heat treatment.
  • the temperature of the heat treatment may be any temperature at which the interaction (alloying near the interface) between the metal material constituting the mask layer 150 and the material of the second semiconductor layer 22 proceeds. For example, in order to realize ohmic contact between the Ti layer and the GaN semiconductor layer, heat treatment with a lower limit of 500 to 600 ° C. may be performed.
  • the heat treatment time depends on the heat treatment temperature, but is, for example, about 1 to 10 minutes or more.
  • an element separation region 240 is formed in the space (trench) between the ⁇ LED 220s.
  • the space (trench) formed between the adjacent ⁇ LED 220s is filled with an organic or inorganic insulating material to form an embedded insulator 25.
  • an organic or inorganic insulating material For example, after depositing the insulating material by a thin film deposition technique such as the CVD method, flattening such as polishing may be performed until the upper surface of the ⁇ LED 220 is exposed. Further, a liquid thermosetting resin or an ultraviolet curable resin may be supplied into the trench and cured by heat or ultraviolet rays. By using the liquid resin material, it becomes easy to form the embedded insulator 25 having a flat upper surface.
  • a through hole for the metal plug 24 (not shown in FIG. 4E) is then formed at the desired location of the embedded insulator 25 by using photolithography and etching techniques.
  • the element separation region 240 in this example has an embedded insulator 25 and a plurality of metal plugs 24 each provided in a plurality of through holes of the embedded insulator 25.
  • a plurality of contact holes for connecting the electric circuit of the backplane 400 to the ⁇ LED 220 of the frontplane 200. (Not shown in FIG. 4G) is formed on the interlayer insulating layer 38.
  • the contact hole is formed so as to reach the contact electrodes 31 and 32 located in the lower layer.
  • the contact hole is filled with via electrodes.
  • the upper surface of the interlayer insulating layer 38 can be smoothed by CMP treatment.
  • the backplane 400 is formed on the intermediate layer 300.
  • a characteristic point in the present disclosure is that the backplane 400 is not attached on the intermediate layer 300, but various electronic elements and wirings constituting the backplane 400 are mounted on the front plane 200 and the intermediate layer 300 by semiconductor manufacturing technology. It is to be formed directly on the laminated structure containing.
  • each of the plurality of TFTs included in the backplane 400 has a semiconductor layer grown on a laminated structure composed of a front plane 200 and an intermediate layer 300 supported by the substrate 100.
  • the backplane 400 including the TFT when the upper surface of the front plane 200 and the upper surface of the intermediate layer 300 are flattened, it becomes easy to manufacture the backplane 400 including the TFT by the semiconductor manufacturing technology.
  • a TFT is formed by a semiconductor manufacturing technique, it is necessary to pattern the deposited semiconductor layer, insulating layer, and metal layer. Such patterning is realized by a lithography process involving exposure. If there is a large step on the base of the deposited semiconductor layer, insulating layer, and metal layer, the focus will not be achieved during exposure, and highly accurate fine patterning will not be realized.
  • the intermediate layer 300 is also flattened, and the backplane 400 can be easily formed by the semiconductor manufacturing technique.
  • the shape of the ⁇ LED 220 is generally a rectangular parallelepiped, but the shape of the ⁇ LED 220 may be a cylinder, a polygonal column such as a hexagonal column, or a polygonal column as shown in FIGS. 5A and 5B. It may be an elliptical column.
  • FIG. 5A is a perspective view showing a part of the ⁇ LED device including the cylindrical ⁇ LED 220
  • FIG. 5B is a plan view thereof.
  • the element separation region 240 includes an embedded insulator 25 that covers the sides of each ⁇ LED 220 and a metal plug 24 that fills the space between the ⁇ LED 220s. By the action of the metal plug 24, the element separation region 240 can prevent the light emitted from each ⁇ LED 220 from being mixed with the light emitted from another ⁇ LED 220.
  • each ⁇ LED 220 is defined by the shape and position of the mask opening 150G of the mask layer 150, by adjusting the pattern of the mask layer 150, the shape and position of each ⁇ LED 220 and further the ⁇ LED 220
  • the array pattern can be controlled arbitrarily.
  • the ⁇ LED device 1000A in this embodiment is a display device having the same configuration as the above-mentioned basic configuration example.
  • the ⁇ LED device 1000A includes a crystal growth substrate (hereinafter, “substrate”) 100 that transmits visible light and / or ultraviolet rays, a front plane 200 formed on the substrate 100, and an intermediate layer formed on the front plane 200. It includes a 300 and a backplane 400 formed on the intermediate layer 300.
  • FIG. 7A shows a configuration example of the substrate 100 used in this embodiment.
  • the mask layer 150 can be formed, for example, from a layer of refractory metal having a thickness of 100 to 1000 nm, typically 300 nm.
  • the metal mask layer 150 can function as a part of the common electrode on the n side by making good ohmic contact with the n-GaN layer 22n.
  • the mask layer 150 is formed by a thin film deposition technique such as a sputtering method, and then patterned by a photolithography and etching technique. By this patterning, a plurality of mask openings 150G having a predetermined shape are formed.
  • Each of the plurality of mask openings 150G in the present embodiment determines the shape and position of the n-GaN layer 22n of each ⁇ LED 220.
  • the substrate 100 is placed in the reaction chamber of the MOCVD apparatus, and various gases are supplied to perform epitaxial growth of the gallium nitride (GaN) -based compound semiconductor.
  • the main body of the substrate 100 in this embodiment is, for example, a sapphire substrate having a thickness of about 50 to 600 ⁇ m.
  • the upper surface 100T of the substrate 100 is typically a C surface (0001), but may have a non-polar surface or a semi-polar surface such as an m surface, an a surface, or an r surface on the upper surface. Further, the upper surface 100T may be inclined by about several degrees from these crystal planes.
  • the substrate 100 is typically disc-shaped, and its diameter can be, for example, 1 to 8 inches.
  • the shape and size of the substrate 100 are not limited to this example, and may be rectangular. Further, the manufacturing process may be advanced using the disk-shaped substrate 100, and finally the periphery of the substrate 100 may be cut and processed into a rectangular shape. Further, the manufacturing process may be advanced using the relatively large substrate 100, and finally one substrate 100 may be divided to form a plurality of ⁇ LED devices (singulation).
  • TMG trimethylgallium
  • TAG triethylgallium
  • H 2 hydrogen
  • N 2 nitrogen
  • NH 3 ammonia
  • SiH 4 silane
  • the substrate 100 is heated to about 1100 ° C.
  • the n-GaN layer (thickness: for example, 2 ⁇ m) 22n is selectively selected from the region not covered by the mask layer 150 of the substrate 100, that is, the region defined by the mask opening 150G.
  • Silane is a raw material gas that supplies Si, which is an n-type dopant.
  • the doping concentration of n-type impurities can be, for example, 5 ⁇ 10 17 cm -3 .
  • the supply of SiH 4 is stopped, the temperature of the substrate 100 is lowered to less than 800 ° C., and the light emitting layer 23 is formed on the surface of the n—GaN layer 22n as shown in FIG. 7C.
  • the GaN barrier layer is grown.
  • the supply of trimethylindium (TMI) is started to grow the In y Ga 1-y N (0 ⁇ y ⁇ 1) well layer.
  • TMI trimethylindium
  • One light emitting layer 23 may have a single In y Ga 1-y N (0 ⁇ y ⁇ 1) well layer sandwiched between two GaN barrier layers.
  • An In y Ga 1-y N (0 ⁇ y ⁇ 1) well layer is directly formed on the n-GaN layer 22n, and a GaN barrier is formed on the In y Ga 1-y N (0 ⁇ y ⁇ 1) well layer. Layers may be formed.
  • the In y Ga 1-y N (0 ⁇ y ⁇ 1) well layer may contain Al.
  • Al x In y Ga z N (0 ⁇ x ⁇ 1,0 ⁇ y ⁇ 1,0 ⁇ z ⁇ 1) formed from You may.
  • TMI trimethylaluminum
  • Cp 2 Mg biscyclopentadienyl magnesium
  • the refractory metal used for the mask layer 150 of the present embodiment preferably has a melting point of at least 1100 ° C., Ti (melting point: 1666 ° C.), Cr (same: 1857 ° C.), Mo ( The same: 2623 ° C.), Mn (same as above: 1246 ° C.), W (same as above: 3407 ° C.), Ta (same as above: 2985 ° C.) and the like can be preferably used.
  • the ⁇ LED 220 can be formed in any shape and arrangement depending on the shape and arrangement of the mask opening 150G of the mask layer 150.
  • the temperature of the epitaxial growth step is high, and good ohmic contact can be obtained between the n-GaN layer 22n and the surface of the mask layer 150. Therefore, it is not particularly necessary to perform an additional heat treatment step for completing the ohmic contact before the completion of the front plane 200.
  • the space defining the element separation region 240 is filled with the embedded insulator 25.
  • the material and method of forming the embedded insulator 25 are arbitrary.
  • the upper surface of the embedded insulator 25 is flattened and located at the same level as the upper surface of the p-GaN layer 21p.
  • the surface is flattened by selectively dropping a thermosetting resin onto the device separation region 240 using an inkjet method and allowing it to stand for a while. Then it is heated to cure the resin.
  • a through hole 26 reaching the mask layer 150 is formed in a part of the embedded insulator 25.
  • the through hole 26 defines the position and shape of the metal plug 24.
  • the through hole 26 has, for example, a rectangular shape having a side of 5 ⁇ m or more and a circular shape having a diameter of 5 ⁇ m or more. Further, the through hole 26 may have a shape for accommodating a metal plug 24 having a shape as shown in FIGS. 1C and 1D, for example.
  • a metal plug 24 that fills the through hole 26 is formed, and the upper surface of the front plane 200 is flattened.
  • the lower end of the metal plug 24 comes into electrical contact with the mask layer 150.
  • the portion of the mask layer 150 that comes into contact with the lower end of the metal plug 24 functions as the connecting portion 150C.
  • the first contact electrode 31 and the second contact electrode 32 are formed. Flattening can be performed by various processes such as etchback, selective growth, CMP or lift-off.
  • the metal plug 24 comes into contact with the metal mask layer 150, the degree of freedom of combination increases unlike the case of contacting with the semiconductor layer, so that the metal plug 24 can be formed from any metal or other conductive material.
  • the first and second contact electrodes 31 and 32 can be formed by depositing and patterning a metal layer.
  • a metal-semiconductor interface is formed between the first contact electrode 31 and the p-GaN layer 21p of the ⁇ LED 220.
  • the material of the first contact electrode 31 can be selected from metals with a high work function, such as platinum (Pt) and / or palladium (Pd). After forming the Pt or Pd layer (thickness: about 50 nm), heat treatment can be performed, for example, at a temperature of 350 ° C. or higher and 400 ° C. or lower for about 30 seconds.
  • a Pt or Pd layer is present in the portion that is in direct contact with the p-GaN layer 21p, another metal such as a Ti layer (thickness: about 50 nm) and / or an Au layer (thickness: about 50 nm) and / or Au layer (thickness: about 50 nm) and / or Au layer Thickness: about 200 nm) may be laminated.
  • a region in which p-type impurities are doped at a relatively high concentration may be formed in the upper part of the p-GaN layer 21p and in the lower layer of the first contact electrode 31.
  • the second contact electrode 32 is electrically connected to the metal plug 24 instead of the semiconductor. Therefore, the material of the second contact electrode 32 can be selected from a wide range.
  • the first contact electrode 31 and the second contact electrode 32 may be formed by patterning one continuous metal layer. This patterning also includes lift-off. When the thicknesses of the first contact electrode 31 and the second contact electrode 32 are equal to each other, it becomes easy to connect to an electric circuit in the backplane 400 such as the TFT 40 described later.
  • the first and second contact electrodes 31 and 32 are covered with an interlayer insulating layer (thickness: for example, 500 nm to 1500 nm) 38.
  • the upper surface of the interlayer insulating layer 38 can be flattened by CMP treatment or the like.
  • the thickness of the interlayer insulating layer 38 whose upper surface is flattened means "average thickness".
  • a contact hole 39 is formed in the interlayer insulating layer 38.
  • the contact hole 39 is used to electrically connect the electrical circuit of the backplane 400 to the ⁇ LED 220 of the frontplane 200 by a via electrode 36 (not shown) formed thereafter.
  • the TFT 40 is a semiconductor that contacts at least a part of the upper surfaces of the drain electrode 41 and the source electrode 42 formed on the interlayer insulating layer 38 and the drain electrode 41 and the source electrode 42, respectively. It has a thin film 43, a gate insulating film 44 formed on the semiconductor thin film 43, and a gate electrode 45 formed on the gate insulating film 44.
  • the drain electrode 41 and the source electrode 42 are connected to the first contact electrode 31 and the second contact electrode 32 by a via electrode 36 formed in the contact hole, respectively.
  • Each of these components of the TFT 40 can be formed by known semiconductor manufacturing techniques.
  • the TFT 40 shown has a known TFT configuration in that it is electrically connected to the ⁇ LED 220 of the front plane 200 to be driven by a via electrode 36 formed directly below the drain electrode 41 and the source electrode 42. Is different.
  • the semiconductor thin film 43 can be formed from polycrystalline silicon, amorphous silicon, oxide semiconductors, and / or gallium nitride based semiconductors.
  • the polycrystalline silicon can be formed, for example, by depositing amorphous silicon on the interlayer insulating layer 38 of the intermediate layer 300 by a thin film deposition technique, and then crystallizing the amorphous silicon with a laser beam.
  • the polycrystalline silicon formed in this way is called LTPS (Low-Temperature Poly Silicon).
  • the polycrystalline silicon is patterned into the desired shape in the lithography and etching steps.
  • the TFT 40 in FIG. 6 is covered with an insulating layer (thickness: for example, 500 nm to 3000 nm) 46.
  • the insulating layer 46 is provided with an opening hole (not shown), which makes it possible to connect the TFT 40, for example, the gate electrode 45 to an external driver integrated circuit element or the like. It is preferable that the upper surface of the insulating layer 46 is also flattened.
  • the electrical circuit of the backplane 400 may include circuit elements such as TFTs, capacitors, and diodes (not shown). Therefore, the insulating layer 46 may have a structure in which a plurality of insulating layers are laminated, and in that case, each insulating layer may be provided with a via electrode for connecting circuit elements, if necessary. Further, wiring may be formed on each insulating layer as needed.
  • the backplane 400 in the present embodiment is formed by semiconductor manufacturing technology on the ⁇ LED 220 located in the lower layer, and the contact hole 39 and the via electrode 36 are electrically formed in the ⁇ LED 220 arranged in the lower layer than the backplane 400. It is characterized in that it is formed so as to be joined. Therefore, for example, the drain electrode 41 and the source electrode 42 of the TFT 40 can be formed by patterning a metal layer deposited so as to cover the front plane 200. Such patterning enables highly accurate alignment by lithographic techniques. In particular, in the present embodiment, since the front plane 200 and / or the intermediate layer 300 are both flattened, it is possible to increase the resolution of lithography.
  • the configuration of the TFT 40 shown in FIG. 6 is an example.
  • the drain electrode 41 of the TFT 40 may be another circuit element in the backplane 400 or It may be connected to the wiring.
  • the source electrode 42 of the TFT 40 does not need to be electrically connected to the second contact electrode 32.
  • the second contact electrode 32 may be connected to a wiring (for example, a ground wiring) that commonly gives a predetermined potential to the n-GaN layer 22n of the ⁇ LED 220.
  • a wiring for example, a ground wiring
  • the metal plug 24 provided in the element separation region 240 is connected to the electric circuit in the backplane 400 located directly above the metal plug 24. In order to pass a current through a large number of ⁇ LED 220s through one continuous metal plug 24 or a plurality of metal plugs 24, it is necessary to reduce the electric resistance on the current path.
  • the electric circuit of the backplane 400 has a plurality of metal layers (drain electrode 41 and source electrode) connected to the first contact electrode 31 and the second contact electrode 32 provided below the backplane 400, respectively. It has a metal layer) that functions as 42).
  • a flat base is required in order to form the electric circuit in these electrodes 31, 32 and the backplane 400 by the lithography technique. This is because the presence of large irregularities on the base reduces the accuracy of pattern formation in the lithography process.
  • the backplane 400 can be formed with high accuracy and high yield by using a lithography technique.
  • the plurality of first contact electrodes 31 each cover the p-GaN layer 21p of the plurality of ⁇ LED 220s and function as a light-shielding layer or a reflective layer.
  • the individual first contact electrodes 31 do not have to completely cover the upper surface of the ⁇ LED 220, that is, the entire upper surface of the p-GaN layer 21p.
  • the shape, size, and position of the first contact electrode 31 are determined to achieve a sufficiently low contact resistance and to sufficiently suppress the light emitted from the light emitting layer 23 from entering the channel region of the TFT 40. Will be done. It should be noted that preventing the light emitted from the light emitting layer 23 from entering the channel region of the TFT 40 can also be realized by arranging another metal layer at an appropriate position.
  • an intermediate layer 300 having a flat upper surface is formed on a front plane 200 having a flat upper surface realized by embedding the element separation region 240 with a metal plug 24 and an embedded insulator 25.
  • These structures (substructures) function as a base for forming circuit elements such as TFTs on the structures.
  • the above-mentioned substructure is treated at a temperature of, for example, 350 ° C. or higher.
  • the embedded insulator 25 in the device separation region 240 and the interlayer insulating layer 38 contained in the intermediate layer 300 are formed of a material that does not deteriorate even by heat treatment at 350 ° C. or higher.
  • polyimide and SOG Spin-on Glass
  • the configuration of the TFT included in the electric circuit in the backplane 400 is not limited to the above example.
  • FIG. 8 is a cross-sectional view schematically showing another example of the TFT.
  • FIG. 9 is a cross-sectional view schematically showing still another example of the TFT.
  • the TFT 40 has a drain electrode 41, a source electrode 42, and a gate electrode 45 formed on a flat interlayer insulating layer 38, a gate insulating film 44 formed on the gate electrode 45, and gate insulation. It has a semiconductor thin film 43 formed on the film 44 and in contact with at least a part of the upper surface of each of the drain electrode 41 and the source electrode 42.
  • the drain electrode 41 and the source electrode 42 are connected to the first contact electrode 31 and the second contact electrode 32 by a via electrode 36 located directly below, respectively.
  • the drain electrode 41, the source electrode 42, and the gate electrode 45 can be formed from the same conductive film.
  • the substrate is flat.
  • the voids between the ⁇ LEDs 220 formed by selective growth are filled with the embedded insulator 25 and / or the metal plug 24, and the entire front plane 200 is flattened.
  • the drain electrode 41, the source electrode 42, and the gate electrode 45 may be formed of different conductive materials. Unlike the gate electrode 45, the drain electrode 41 and the source electrode 42 are in electrical contact with the semiconductor thin film 43, so that the drain electrode 41 and the source electrode 42 have a material or layer structure suitable for achieving low contact resistance. You may be doing it.
  • the drain electrode 41, the source electrode 42, and the gate electrode 45 are all located below the semiconductor thin film 43. Therefore, it is easy to electrically connect to the front plane 200 located below the TFT 40. Further, it is easy to shorten the distance from the ⁇ LED 220 or the metal plug 24 to the drain electrode 41 or the source electrode 42. As shown in FIG. 8, an interlayer insulating layer 38 having a simple structure is present between the upper surface of the front plane 200 and the drain electrode 41 or the source electrode 42.
  • the thickness of the interlayer insulating layer 38 is, for example, 300 nm or more and 1000 nm or less, and when the height of the via electrode 36 is T and the pore diameter (in the case of a rectangle, the length of the short side) is R, the aspect ratio (T). / R) can be, for example, 1/3 or less.
  • the higher the aspect ratio the lower the yield of forming via electrodes, and the more likely it is that poor electrical connection between the front plane 200 and the back plane 400 will occur.
  • the drain electrode 41, the source electrode 42, and the gate electrode 45 are formed on the same flattened base layer, and a semiconductor is formed on the upper layers of the electrodes 41, 42, and 45.
  • the aspect ratio can be lowered, so that even when the ⁇ LED 220s are arranged in various patterns in the front plane 200, the electrical connection between the front plane 200 and the back plane 400 can be easily performed. Become.
  • the TFT 40 has a semiconductor thin film 43 formed on the interlayer insulating layer 38, and a drain electrode 41 and a source electrode 42 formed on the interlayer insulating layer 38 and in contact with a part of the semiconductor thin film 43, respectively. And a gate insulating film 44 formed on the semiconductor thin film 43, and a gate electrode 45 formed on the gate insulating film 44.
  • the drain electrode 41 and the source electrode 42 are connected to the first contact electrode 31 and the second contact electrode 32 by the via electrode 36, respectively.
  • the semiconductor thin film 43 is located below the drain electrode 41, the source electrode 42, and the gate electrode 45, the semiconductor thin film 43 is formed before the electrodes 41, 42, and 45 are formed.
  • the semiconductor thin film 43 serving as the channel of the TFT 40 is formed on the flattened interlayer insulating layer 38, the film quality or the film quality due to the underlying step is formed in the step of growing the semiconductor layer during manufacturing.
  • the film thickness is unlikely to be non-uniform.
  • the gate electrode 45 is located above the semiconductor thin film 43, the LDD (Lightly Drain Dope) structure can be self-consistently formed by using the gate electrode 45 as a mask for ion implantation.
  • the semiconductor thin film 43 partially overlaps the contact hole 39 and the via electrode 36 provided in the intermediate layer 300. Both the upper surface and the lower surface of the semiconductor thin film 43 are in contact with the electrodes. More specifically, the drain region of the semiconductor thin film 43 is sandwiched between the drain electrode 41 in the upper layer and the via electrode 36 in the lower layer. The sort region of the semiconductor thin film 43 is sandwiched from above and below by the source electrode 42 in the upper layer and the via electrode 36 in the lower layer. As a result, the contact resistance of the electrode is reduced and the TFT characteristics are improved. It is not necessary that both the drain region and the source region of the semiconductor thin film 43 are in contact with the via electrode 36 of the lower layer, and one of the drain region and the source region may be in contact with the via electrode 36 of the lower layer.
  • the configuration of the TFT 40 is not limited to the above example, but the configuration shown in the above example of the present embodiment is preferable so that the ⁇ LED 220 formed in the lower layer of the backplane 400 can be appropriately contacted.
  • it in the initial stage of the process of forming the TFT 40, it is connected to the first and second contact electrodes 31 and 32 of the front plane 200 via the contact hole 39 of the interlayer insulating layer 38 in the intermediate layer 300.
  • Multiple metal layers are formed. These metal layers can be, but are not limited to, the drain electrode 41 or the source electrode 42 of the TFT 40.
  • the drain electrode 41 and the source electrode 42 in this embodiment are patterned by a photolithography and etching process after depositing a metal layer on the interlayer insulating layer 38 in the flattened intermediate layer 300. Therefore, there is no misalignment between the front plane 200 (intermediate layer 300) and the back plane 400 that causes a decrease in yield.
  • a large number of ⁇ LED 220s are arranged over a wide range, and at least one metal plug 24 connects the n-GaN layer 22n of the ⁇ LED 220 to the electric circuit of the backplane 400. Therefore, if the electric resistance component (sheet resistance) with respect to the current flowing from the n-GaN layer 22n to the metal plug 24 is too high, the power consumption will increase.
  • the metal plug 24 and the n-GaN of each ⁇ LED 220 are n-GaN. Electrical continuity with the layer 22n is ensured.
  • the mask layer 150 functions as an n-side common electrode of the plurality of ⁇ LED 220s.
  • the electrodes on the second conductive side of the plurality of ⁇ LED 220s are shared by the mask layer 150 having conductivity, there is a problem that some ⁇ LED 220s have poor continuity due to disconnection. Avoided.
  • the trench is filled with the embedded insulator 25.
  • the embedded insulator 25 can be formed by applying a resin material such as thermosetting polyimide and then curing the resin material by heat treatment at 400 ° C. for 60 minutes, for example.
  • the embedded insulator 25 does not have to be formed of a resin, and may be formed of an inorganic insulating material such as silicon nitride or silicon oxide.
  • the TFTs and other components contained in the backplane 400 are formed on the upper layers of the front plane 200 and the intermediate layer 300 by semiconductor manufacturing technology, so that the process temperature for forming these components is set. It is necessary to form the front plane 200 and the intermediate layer 300 using a material that can withstand.
  • the embedded insulator 25, the interlayer insulating layer 38, and the insulating layer 46 can be formed from an organic material, which must withstand the maximum temperature of the process of forming the backplane 400. Specifically, when a heat treatment exceeding 300 ° C.
  • the insulating layer 38 and / or the insulating layer 46 can be formed.
  • the embedded insulator 25, the interlayer insulating layer 38, and the insulating layer 46 do not necessarily have a single-layer structure, and may have a multi-layer structure.
  • the multilayer structure may include, for example, a stack of organic and inorganic materials.
  • the upper surface of the metal plug 24 in the above example is at almost the same level as the upper surface of each ⁇ LED 220, it is possible to form circuit elements such as TFT 40 and fine wiring on it with high accuracy by semiconductor manufacturing technology. ..
  • the metal plug 24 that fills the through hole 26 is used, but as described above, the form of the metal plug 24 can be various.
  • FIG. 10 is a cross-sectional view showing a part of the ⁇ LED device 1100 in the modified example.
  • the difference between the ⁇ LED device 1100 of FIG. 10 and the ⁇ LED device 1000 of FIG. 1A is that the insulating layer 160 is provided on the mask layer 150.
  • the insulating layer 160 has an opening 160G that enables contact between the metal plug 24 and the connecting portion 150C of the mask layer 150. Further, the insulating layer 160 does not cover the peripheral region of the mask opening 150G on the upper surface of the mask layer 150. Therefore, the portion where the second semiconductor layer 22 grows in the lateral direction and the upper surface of the mask layer 150 are brought into contact with each other. Therefore, good ohmic contact is also realized between the second semiconductor layer 22 and the surface of the mask layer 150 by heating during epitaxial growth or by performing appropriate heat treatment after epitaxial growth.
  • the insulating layer 160 may be deposited before the growth of the second semiconductor layer 22, or may be deposited after the growth of the second semiconductor layer 22 and before the growth of the light emitting layer 23.
  • the step of forming the opening 160G in the insulating layer 160 can be performed, for example, after the step of forming the through holes 26 in the embedded insulator 25.
  • the insulating layer 160 prevents the mask layer 150 from coming into contact with the light emitting layer 23 and the first semiconductor layer 21. Therefore, in this modification, the mask layer 150 may be formed of a metal material capable of realizing some kind of electrical conduction such as ohmic contact with the first semiconductor layer 21.
  • the laterally grown portion of the second semiconductor layer 22 reaches the edge of the insulating layer 160 on the mask layer 150.
  • the second semiconductor layer 22 may overlap a part of the insulating layer 160.
  • the mask layer 150 is formed of a material exhibiting high electrical resistance to the light emitting layer 23, the second semiconductor layer 22 does not need to reach the edge of the insulating layer 160. In that case, the portion of the mask layer 150 that is not covered by the insulating layer 160 may come into contact with the light emitting layer 23 and / or the first semiconductor layer 21.
  • an insulating layer 160 exists between the mask layer 150 and the light emitting layer 23 and the first semiconductor layer 21.
  • the laterally grown portion of the second semiconductor layer 22 overcomes the edge of the insulating layer 160 on the mask layer 150 and partially over the insulating layer 160. It is desirable to wrap it.
  • the insulating layer 160 may be formed of a material that does not deteriorate at the growth temperature of the light emitting layer 23 and the first semiconductor layer 21, such as silicon oxide or silicon nitride.
  • ⁇ Color display I> a configuration example of the ⁇ LED device 1000B capable of full-color display according to the embodiment of the present disclosure will be described with reference to FIG. In FIG. 11, the direction of the Z axis is reversed from the direction of the Z axis in FIG. 1A. The same reference numerals are given to the components corresponding to the components in the ⁇ LED device 1000A described above, and the description of these components will not be repeated here.
  • the ⁇ LED device 1000B in the present embodiment includes a substrate 100, a front plane 200, an intermediate layer 300, and a back plane 400. These elements may have the various configurations described above.
  • the ⁇ LED device 1000B shown in FIG. 11 further includes a phosphor layer 600 that converts light emitted from each of the plurality of ⁇ LED 220s into white light, and a color filter array 620 that selectively transmits each color component of white light.
  • the color filter array 620 is supported by the substrate 100 with the phosphor layer 600 interposed therebetween, and has a red filter 62R, a green filter 62G, and a blue filter 62B.
  • the composition and bandgap of the light emitting layer 23 are adjusted so that the light emitted from the light emitting layer 23 of the ⁇ LED 220 has a blue wavelength (435 to 485 nm).
  • An example of the phosphor layer 600 may be a sheet containing a large number of nanoparticles (quantum dot phosphors) called "quantum dots".
  • the quantum dot phosphor can be formed from a semiconductor such as CdTe, InP, or GaN.
  • the wavelength of light emitted from a quantum dot phosphor changes according to its size.
  • a quantum dot dispersion sheet adjusted to receive excitation light and emit red and green light can be used as the phosphor layer 600.
  • blue light is used as the light for exciting the phosphor layer 600, the blue light transmitted through the phosphor layer 600 and the light converted into red or green by the quantum dots of the phosphor layer 600 are mixed. The white light thus formed can be emitted from the phosphor layer 600.
  • the particle size of the quantum dot phosphor is, for example, 2 nm or more and 30 nm or less.
  • the particle size of the quantum dot phosphor is significantly smaller than that of general phosphor powder particles having a particle size of more than 10 ⁇ m.
  • ⁇ LED220s are arranged at a narrow pitch of, for example, about 5 to 10 ⁇ m, it is difficult to perform efficient wavelength conversion for phosphor powder particles having a particle size of more than 10 ⁇ m because the phosphors are too large for the arrangement pitch of ⁇ LED220.
  • the phosphor layer 600 may include a scatterer having a size that mainly causes Rayleigh scattering of blue light (excitation light). Rayleigh scattering is caused by particles smaller than the wavelength of light, and the degree of scattering is inversely proportional to the fourth power of the wavelength. Therefore, the shorter the wavelength of light, the more it is scattered.
  • a scatterer that selectively scatters blue light titanium oxide (TiO 2 ) ultrafine particles having a diameter of 10 nm or more and 50 nm or less (typically 30 nm or less) can be preferably used.
  • TiO 2 ultrafine particles of rutile-type crystals are preferable because they are physically and chemically stable. Such TiO 2 ultrafine particles have a low effect of scattering light of colors (green and red) having a wavelength longer than that of blue.
  • the TiO 2 ultrafine particles in the phosphor layer 600 it is preferable to perform a surface treatment using an organic substance such as an alkanolamine, a polyol, a siloxane, or a carboxylic acid (for example, stearic acid or lauric acid). Further, the surface treatment may be performed using an inorganic substance such as Al (OH) 3 or SiO 2 .
  • an organic substance such as an alkanolamine, a polyol, a siloxane, or a carboxylic acid (for example, stearic acid or lauric acid).
  • the surface treatment may be performed using an inorganic substance such as Al (OH) 3 or SiO 2 .
  • zinc oxide fine particles particles (particle diameter: for example, 20 nm or more and 100 nm or less) may be used instead of the titanium oxide fine particles or together with the titanium oxide fine particles. Since such blue scatterers are uniformly dispersed, color unevenness depending on the direction is less likely to occur, and a display having excellent viewing angle characteristics is realized.
  • the ⁇ LED device 1000B of the present embodiment needs to transmit the light emitted from the light emitting layer 23 of the ⁇ LED 220. If the substrate 100 is a sapphire substrate, high translucency is exhibited in a wide range of visible light and ultraviolet rays.
  • the red filter 62R, the green filter 62G, and the blue filter 62B in the color filter array 620 are arranged at positions facing the ⁇ LED 220, respectively.
  • the red filter 62R, the green filter 62G, and the blue filter 62B receive white light from the phosphor layer 600 excited by the light emitted from the corresponding ⁇ LED 220, and the red component and the green component contained in the white light, respectively. And the blue component is transmitted.
  • the metal plug 24 should be shaped to surround each individual ⁇ LED device 1000B. It is desirable to have.
  • a portion that functions as a black matrix formed of a light-shielding or absorbent material is located between the red filter 62R, the green filter 62G, and the blue filter 62B.
  • the phosphor layer 600 may be a stacked phosphor sheet on the color filter array 620.
  • the phosphor layer 600 does not have to be a sheet in which quantum dot phosphors are dispersed.
  • the phosphor layer 600 may be formed by dispersing the quantum dot phosphor (fluorescent powder) in a resin, applying and curing the lower surface 100B of the substrate 100. In this case, the phosphor powder is located on the lower surface 100B of the substrate 100.
  • An optical sheet, a protective sheet, a touch sensor, or the like other than the phosphor layer 600 and the color filter array 620 may be attached to the substrate 100. This also applies to other embodiments described later.
  • FIGS. 12A and 12B are perspective views of the ⁇ LED device 1000C.
  • the ⁇ LED device 1000C in the present embodiment includes a substrate 100, a front plane 200, an intermediate layer 300, and a back plane 400. These elements may have the various configurations described above.
  • the illustrated ⁇ LED device 1000C is a bank layer (thickness: 0.5 to 3.0 ⁇ m) that is supported by the substrate 100 and defines a plurality of pixel openings 645 in which light emitted from the plurality of ⁇ LEDs is incident. It has 640. Further, the ⁇ LED device 1000C includes a red phosphor 64R, a green phosphor 64G, and a blue scatterer 64B respectively arranged in a plurality of pixel openings 645 of the bank layer 640. The red phosphor 64R converts the blue light emitted from the ⁇ LED 220 into red light, and the green phosphor 64G converts the blue light emitted from the ⁇ LED 220 into green light.
  • the blue scatterer 64B scatters the blue light emitted from the ⁇ LED 220.
  • the blue scatterer 64B can be designed to have a radiation angle dependence similar to the radiation angle dependence (eg, Lambersian distribution) exhibited by the intensity of light emitted from the red phosphor 64R or the green phosphor 64G.
  • the composition and bandgap of the light emitting layer 23 are adjusted so that the light emitted from the light emitting layer 23 of the ⁇ LED 220 has a blue wavelength (435 to 485 nm).
  • the ⁇ LED device 1000C includes a transparent protective layer 650 that covers the pixel openings 645 in the bank layer 640.
  • the description of the transparent protective layer 650 is omitted in FIG. 12B.
  • the transparent protective layer 650 exerts a sealing function so that moisture in the atmosphere does not adversely affect these phosphors.
  • the transparent protective layer 650 may be a laminate of an organic layer and an inorganic layer.
  • the bank layer 640 has, for example, a lattice shape, and can be formed from a light-shielding material in which a black dye is dissolved or a light-shielding material in which a black pigment such as carbon black is dispersed.
  • the bank layer 640 can be formed of a photosensitive material, a resin material such as acrylic or polyimide, a paste material containing low melting point glass, a sol-gel material (for example, SOG), or the like.
  • the bank layer 640 is formed from a photosensitive material
  • the pixel opening 645 is formed at a predetermined position by applying the photosensitive material to the lower surface 100B of the substrate 100 and then performing patterning by exposure and development in a lithography process. Just do it.
  • the position and size of the pixel openings 645 are determined to match the placement of the ⁇ LED 220.
  • the size of the pixel opening 645 can be, for example, 10 ⁇ m ⁇ 10 ⁇ m or less.
  • the particle sizes of the red phosphor 64R, the green phosphor 64G, and the blue scatterer 64B arranged in the pixel opening 645 are preferably 1 ⁇ m or less, and are uniformly and densely arranged in the pixel opening 645. Considering the arrangement, it is more desirable to be 100 nm or less. Therefore, the red phosphor 64R and the green phosphor 64G can each be suitably formed from the quantum dot phosphor.
  • the blue scatterer 64B can be formed from transparent powder particles having a particle size of 10 nm or more and 60 nm or less.
  • the blue scatterer 64B is a matrix material having a refractive index sufficiently lower than the refractive index (n) of particles having a particle size of about 10% of the wavelength of blue light (for example, about 450 nm) emitted from the ⁇ LED 220. Can be formed by dispersing in. The blue scatterer 64B formed in this way can cause Rayleigh scattering in blue light.
  • the refractive index of the matrix material is preferably 0.25 or more, for example 0.5 or more, lower than the refractive index of the powder particles.
  • the lower surface 100B of the substrate 100 may have an uneven surface that acts on the light emitted from the ⁇ LED 220.
  • the presence of such an uneven surface adjusts the radiation intensity dependence of the light emitted from the red phosphor 64R, the green phosphor 64G, and the blue scatterer 64B, or the reflectance on the lower surface 100B of the substrate 100.
  • FIG. 13A the direction of the Z axis is reversed from the direction of the Z axis in FIG. 1A.
  • FIG. 13B is a perspective view of the ⁇ LED device 1000D.
  • the ⁇ LED device 1000D in the present embodiment includes a substrate 100, a front plane 200, an intermediate layer 300, and a back plane 400. These elements may have the various configurations described above.
  • the illustrated ⁇ LED device 1000D has a plurality of recesses 660 formed on the substrate 100. These recesses 660 are arranged so that the light emitted from the plurality of ⁇ LEDs 220 is incident on each of them. In other words, each recess 660 defines a pixel area.
  • the ⁇ LED device 1000D further includes a red phosphor 66R, a green phosphor 66G, and a blue scatterer 66B, which are respectively arranged in a plurality of recesses 660 of the substrate 100.
  • the red phosphor 66R converts the blue light emitted from the ⁇ LED 220 into red light
  • the green phosphor 66G converts the blue light emitted from the ⁇ LED 220 into green light.
  • the blue scatterer 66B scatters the blue light emitted from the ⁇ LED 220.
  • the blue scatterer 66B can be designed to have a radiation angle dependence similar to the radiation angle dependence (eg, Lambersian distribution) exhibited by the intensity of light emitted from the red phosphor 66R or the green phosphor 66G.
  • the roles and materials of the red phosphor 66R, the green phosphor 66G, and the blue scatterer 66B are similar to the roles and materials of the red phosphor 66R, the green phosphor 64G, and the blue scatterer 64B in the ⁇ LED device 1000C described above. ..
  • composition and bandgap of the light emitting layer 23 are adjusted so that the light emitted from the light emitting layer 23 of the ⁇ LED 220 has a blue wavelength (435 to 485 nm).
  • the ⁇ LED device 1000D includes a transparent protective layer 650 that covers the recess 660.
  • the description of the transparent protective layer 650 is omitted in FIG. 13B.
  • the transparent protective layer 650 exerts a sealing function so that moisture in the atmosphere does not adversely affect these phosphors.
  • the transparent protective layer 650 may be a laminate of an organic layer and an inorganic layer.
  • the main difference between the ⁇ LED device 1000C and the ⁇ LED device 1000D is that in the ⁇ LED device 1000D, the substrate 100 itself has a recess (recess 660) that accommodates the red phosphor 66R, the green phosphor 66G, and the blue scatterer 66B. ) Is provided.
  • the shape of the recess 660 is not limited to a rectangle when viewed from the normal direction of the lower surface 100B of the substrate 100, and may be a circle, an ellipse, a triangle, or another polygon. Further, the inner wall of the recess 660 does not have to be orthogonal to the lower surface 100B of the substrate 100, and may be inclined. Specifically, the recess 660 may be composed of mortar-shaped or pyramidal-shaped recesses.
  • the depth of the recess 660 can be, for example, 500 nm or more and 250 ⁇ m or less.
  • the depth of the recess 660 is, for example, 0.001 T or more and 0.5 T or less, and more preferably 0.1 T or more and 0.3 T or less.
  • the location of the red phosphor 66R, the green phosphor 66G, and the blue scatterer 66B at the bottom of the recess 660 reduces the distance from each to the light emitting layer 23 of the ⁇ LED 220.
  • the luminous flux emitted from the light emitting layer 23 of the ⁇ LED 220 and incident on each of the red phosphor 66R, the green phosphor 66G, and the blue scatterer 66B increases.
  • the viewing angle characteristics are also improved.
  • the recess 660 can be formed by processing the lower surface 100B of the substrate 100 with an ultrashort pulse laser such as a femtosecond laser or a picosecond laser (ablation method).
  • the recess 660 can also be formed by forming a resist mask having a plurality of openings that define the shape and position of the recess 660 on the lower surface 100B of the substrate 100 by lithography technology, and then etching the exposed portion of the lower surface 100B of the substrate 100. Can be formed. Such etching can be achieved, for example, by a combination of ICP and RIE.
  • Fine irregularities may be formed on the bottom surface and / or the side surface of the recess 660. Such irregularities can improve image quality because they diffuse light and increase extraction efficiency.
  • the wavelength of the light (excitation light) emitted from the ⁇ LED 220 is in the range of 435 to 485 nm, that is, the composition of the light emitting layer 23 and the light emitting layer 23 so as to emit blue light.
  • the bandgap has been adjusted.
  • the ⁇ LED device in the embodiments of the present disclosure is not limited to these examples.
  • the composition and band of the light emitting layer 23 such that the light emitted from the light emitting layer 23 of the ⁇ LED 220 has an ultraviolet wavelength (eg, 365 to 400 nm) or a bluish-purple wavelength (400 nm to 420 nm, typically 405 nm).
  • the gap may be adjusted.
  • the semiconductor layer constituting the light emitting layer 23 By forming the semiconductor layer constituting the light emitting layer 23 from AlGaN or InAlGaN, light having a wavelength shorter than 365 nm can be emitted.
  • the light emitted from the ⁇ LED 220 is used to excite the red, green, and blue phosphors, respectively. Therefore, even if the emission wavelength of the ⁇ LED 220 fluctuates or shifts, color unevenness is less likely to occur.
  • the emission wavelength of the ⁇ LED 220 may vary depending on the composition ratio of the light emitting layer 23, the magnitude of the drive current, the temperature, and the like.
  • An example of a phosphor can be a large number of nanoparticles (quantum dot phosphors) called "quantum dots".
  • the quantum dot phosphor can be formed from a semiconductor such as CdTe, InP, or GaN.
  • the wavelength of light emitted from a quantum dot phosphor changes according to its size.
  • a quantum dot dispersion sheet adjusted to emit red, green, and blue light in response to excitation light can be used as the phosphor layer 600 in FIG. 11 or as the phosphor in FIGS. 12 and 13. Good.
  • Quantum dot phosphors are dispersed and used in a matrix formed of an inorganic material such as an organic resin or low melting point glass, or a hybrid material of an organic material and an inorganic material.
  • the amount (weight ratio) of the dispersed phosphors decreases in the order of blue, green, and red.
  • the quantum dot phosphor in one example has a core-shell structure.
  • the core can be formed from, for example, CdS, InP, InGaP, InN, CdSe, InGaN, or ZnCdSe.
  • a phosphor having a core formed from CdS can be preferably used.
  • the particle size of the core is adjusted in the range of 4.0 nm to 7.3 nm, blue light emission having a wavelength of 440 nm to 460 nm can be obtained.
  • blue light (center wavelength 475 nm) has a particle size of 1.4 nm to 3.3 nm, and green light (center wavelength 530 nm).
  • a particle size of 1.7 nm to 4.2 nm and red light (center wavelength of 630 nm) can be obtained with a particle size of 2.0 nm to 6.1 nm.
  • the material from which the quantum dots are formed can be appropriately determined based on the quantum efficiency, particle size, and the like.
  • the quantum dot phosphor having a core formed from In 0.5 Ga 0.5 P has an advantage that it is easy to manufacture because it has a relatively large particle size. When it is desired to realize higher quantum efficiency, it is desirable to use, for example, a quantum dot whose core is formed from InP containing no Ga.
  • An embodiment of the present invention provides a new micro LED device.
  • the micro LED device When used as a display, the micro LED device can be widely applied to smartphones, tablet terminals, in-vehicle displays, and small to medium to large television devices. Applications of micro LED devices are not limited to displays.

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Abstract

A micro LED device according to the present disclosure is provided with: an insulated crystal- growing substrate, (100) the upper surface of which is covered by a conductive mask layer (150) having a plurality of open sections (150G); and a front plane (200) that includes a plurality of micro LEDs (220), each having a first conductive-type first semiconductor layer (21) and a second conductive-type second semiconductor layer (22), and element separating regions (240) positioned between micro LEDs. The element separating regions each have at least one metal plug (24) electrically connected to the second semiconductor layer. This device is provided with: an intermediate layer (300) that includes a first contact electrode (31) electrically connected to the first semiconductor layer and a second contact electrode (32) electrically connected to the metal plug; and a back plane (400) formed on the intermediate layer. The first and second semiconductor layers are epitaxial layers selectively grown from the plurality of mask open sections of the mask layer, and the second semiconductor layer is in ohmic contact with the mask layer.

Description

マイクロＬＥＤデバイスおよびその製造方法Micro LED device and its manufacturing method
　本開示は、マイクロＬＥＤデバイスおよびその製造方法に関する。 This disclosure relates to a micro LED device and a method for manufacturing the same.
　多数のマイクロＬＥＤが狭ピッチで配列されたディスプレイ装置を実用化するためには、微細なマイクロＬＥＤをＴＦＴ基板などの実装回路基板上の所定位置に実装する量産技術の開発が必要である。個々のマイクロＬＥＤをピックアンドプレイス（pick-and-place）方式で回路上に実装する技術によれば、多数のマイクロＬＥＤを例えば数１０μｍのピッチで回路上に実装することは非常に長い作業時間と多大なコストを必要とする。 In order to put into practical use a display device in which a large number of micro LEDs are arranged at a narrow pitch, it is necessary to develop a mass production technology for mounting fine micro LEDs at predetermined positions on a mounting circuit board such as a TFT board. According to the technology of mounting individual micro LEDs on a circuit by a pick-and-place method, mounting a large number of micro LEDs on a circuit at a pitch of, for example, several tens of μm is a very long working time. And requires a great deal of cost.
　特許文献１は、ＴＦＴ基板上に転写された多数のマイクロＬＥＤを備えるディスプレイ装置およびその製造方法を開示している。 Patent Document 1 discloses a display device including a large number of micro LEDs transferred onto a TFT substrate and a method for manufacturing the same.
　特許文献２は、複数のＬＥＤが形成されたＧａＮウェハと、このＧａＮウェハが接合されたバックプレーン制御部（ＴＦＴ基板）とを備えるディスプレイ装置およびその製造方法を開示している。 Patent Document 2 discloses a display device including a GaN wafer on which a plurality of LEDs are formed and a backplane control unit (TFT substrate) to which the GaN wafers are bonded, and a method for manufacturing the display device.
特表２０１６－５２２５８５号公報Special Table 2016-522585 Gazette 特表２０１７－５３８２９０号公報Special Table 2017-538290
　多数のマイクロＬＥＤをＴＦＴ基板上に転写する方法は、マイクロＬＥＤのサイズが小さくなり、その個数が増えると、ＴＦＴ基板に対するマイクロＬＥＤの位置合わせが難しくなるという問題がある。また、ＧａＮウェハをバックプレーン制御部に接合する方法も、ＧａＮウェハを一時的に保持するウェハに移しかえ、かつ、更にバックプレーン制御部に実装するという複雑な工程が必要になる。 The method of transferring a large number of micro LEDs onto the TFT substrate has a problem that the size of the micro LEDs becomes small and the number of the micro LEDs increases, it becomes difficult to align the micro LEDs with respect to the TFT substrate. Further, the method of joining the GaN wafer to the backplane control unit also requires a complicated process of transferring the GaN wafer to the wafer temporarily holding the GaN wafer and further mounting the GaN wafer on the backplane control unit.
　本開示は、上記の課題を解決することができる、マイクロＬＥＤデバイスの新しい構造および製造方法を提供する。 The present disclosure provides a new structure and manufacturing method of a micro LED device that can solve the above problems.
　本開示のマイクロＬＥＤデバイスは、例示的な実施形態において、複数の開口部を有するマスク層によって上面が覆われた絶縁性の結晶成長基板と、前記結晶成長基板に支持されたフロントプレーンであって、それぞれが第１導電型の第１半導体層および第２導電型の第２半導体層を有する複数のマイクロＬＥＤ、ならびに前記複数のマイクロＬＥＤの間に位置する素子分離領域を含み、前記素子分離領域が、前記第２半導体層に電気的に接続された少なくともひとつの金属プラグを有している、フロントプレーンと、前記フロントプレーンに支持された中間層であって、それぞれが前記複数のマイクロＬＥＤの前記第１半導体層に電気的に接続された複数の第１コンタクト電極、および前記金属プラグに接続された少なくともひとつの第２コンタクト電極を含む、中間層と、前記中間層に支持されたバックプレーンであって、前記複数の第１コンタクト電極および前記少なくともひとつの第２コンタクト電極を介して前記複数のマイクロＬＥＤに電気的に接続された電気回路を有し、前記電気回路は複数の薄膜トランジスタを含む、バックプレーンとを備える。前記マスク層は、導電材料から形成されており、前記マスク層は、前記複数のマイクロＬＥＤの位置を規定する複数のマスク開口部と、前記金属プラグに接続する接続部とを有し、前記複数のマイクロＬＥＤの前記第１半導体層および前記第２半導体層は、前記マスク層が有する前記複数のマスク開口部から選択的に成長したエピタキシャル層であり、前記第２半導体層は前記マスク層にオーミック接触している。前記複数の薄膜トランジスタのそれぞれは、前記フロントプレーンおよび／または前記中間層上に成長した半導体層を有している。 In an exemplary embodiment, the micro LED device of the present disclosure is an insulating crystal growth substrate whose upper surface is covered with a mask layer having a plurality of openings, and a front plane supported by the crystal growth substrate. Each includes a plurality of microLEDs each having a first conductive type first semiconductor layer and a second conductive type second semiconductor layer, and an element separation region located between the plurality of microLEDs. A front plane having at least one metal plug electrically connected to the second semiconductor layer and an intermediate layer supported by the front plane, each of the plurality of microLEDs. An intermediate layer including a plurality of first contact electrodes electrically connected to the first semiconductor layer and at least one second contact electrode connected to the metal plug, and a back plane supported by the intermediate layer. The electric circuit includes an electric circuit electrically connected to the plurality of micro LEDs via the plurality of first contact electrodes and the at least one second contact electrode, and the electric circuit includes a plurality of thin film transistors. , With a back plane. The mask layer is formed of a conductive material, and the mask layer has a plurality of mask openings defining the positions of the plurality of micro LEDs and a connection portion connected to the metal plug. The first semiconductor layer and the second semiconductor layer of the micro LED are epitaxial layers selectively grown from the plurality of mask openings of the mask layer, and the second semiconductor layer is ohmic to the mask layer. Are in contact. Each of the plurality of thin film transistors has a semiconductor layer grown on the front plane and / or the intermediate layer.
　ある実施形態において、前記マスク層は、前記第１半導体層に対して、電気的抵抗性または絶縁性の接触をしている。 In certain embodiments, the mask layer is in electrical resistant or insulating contact with the first semiconductor layer.
　ある実施形態において、前記第２半導体層は、前記マスク層に部分的にオーバーラップしている。 In certain embodiments, the second semiconductor layer partially overlaps the mask layer.
　ある実施形態において、前記第２半導体層の導電型はｐ型であり、前記マスク層は、Ｔｉ、Ｃｒ、Ｍｏ、Ｍｎ、Ｗ、およびＴａからなる群から選択された少なくとも１種の高融点金属から形成されている。 In certain embodiments, the conductive type of the second semiconductor layer is p-type, and the mask layer is at least one refractory metal selected from the group consisting of Ti, Cr, Mo, Mn, W, and Ta. Is formed from.
　ある実施形態において、前記マスク層を前記第１半導体層から絶縁する絶縁層を前記マスク層上に備えている。 In a certain embodiment, an insulating layer that insulates the mask layer from the first semiconductor layer is provided on the mask layer.
　ある実施形態において、前記第２半導体層は、前記マスク層上を横方向に成長した部分を有しており、前記横方向に成長した部分は、前記絶縁層に対して部分的にオーバーラップしている。 In certain embodiments, the second semiconductor layer has a portion that grows laterally on the mask layer, and the portion that grows laterally partially overlaps the insulating layer. ing.
　ある実施形態において、前記マスク開口部は、前記基板上の位置に応じて異なる大きさまたは形状を有しており、前記マスク開口部の大きさまたは形状は、各マイクロＬＥＤから放射される光の波長を規定する。 In certain embodiments, the mask opening has a different size or shape depending on its position on the substrate, and the size or shape of the mask opening is the size or shape of the light emitted from each micro LED. Define the wavelength.
　ある実施形態において、前記フロントプレーンの前記素子分離領域は、前記複数のマイクロＬＥＤの間を埋める埋め込み絶縁物を有しており、前記埋め込み絶縁物は、前記金属プラグのための少なくともひとつのスルーホールを有している。 In certain embodiments, the element separation region of the front plane has an embedded insulator that fills between the plurality of micro LEDs, the embedded insulator being at least one through hole for the metal plug. have.
　ある実施形態において、前記フロントプレーンは、平坦な表面を有しており、前記平坦な表面は前記中間層に接している。 In certain embodiments, the front plane has a flat surface, which is in contact with the intermediate layer.
　ある実施形態において、前記中間層は、平坦な表面を有する層間絶縁層を含み、前記層間絶縁層は、前記複数の第１コンタクト電極および前記少なくともひとつの第２コンタクト電極をそれぞれ前記電気回路に接続するための複数のコンタクトホールと、前記コンタクトホールを埋めるビア電極とを有している。 In certain embodiments, the intermediate layer comprises an interlayer insulating layer having a flat surface, and the interlayer insulating layer connects the plurality of first contact electrodes and the at least one second contact electrode to the electric circuit, respectively. It has a plurality of contact holes for forming the contact holes and via electrodes for filling the contact holes.
　ある実施形態において、前記複数の薄膜トランジスタのそれぞれは、前記層間絶縁層の前記平坦な表面上に形成されたソース電極、ドレイン電極、およびゲート電極を有しており、前記半導体層は、前記ゲート電極の上方に位置し、前記ソース電極および前記ドレイン電極の上面に接触している。 In certain embodiments, each of the plurality of thin film transistors has a source electrode, a drain electrode, and a gate electrode formed on the flat surface of the interlayer insulating layer, and the semiconductor layer is the gate electrode. It is located above and is in contact with the upper surfaces of the source electrode and the drain electrode.
　ある実施形態において、前記複数の薄膜トランジスタのそれぞれは、前記半導体層の上層に位置するソース電極、ドレイン電極、およびゲート電極を有しており、前記半導体層は、前記層間絶縁層の前記平坦な表面上に形成されており、前記半導体層の一部は、前記ソース電極および前記ドレイン電極の少なくとも一方と前記ビア電極とによって上下から挟まれている。 In certain embodiments, each of the plurality of thin film transistors has a source electrode, a drain electrode, and a gate electrode located above the semiconductor layer, and the semiconductor layer is a flat surface of the interlayer insulating layer. A part of the semiconductor layer is formed above, and is sandwiched from above and below by at least one of the source electrode and the drain electrode and the via electrode.
　本開示のマイクロＬＥＤデバイスの製造方法は、例示的な実施形態において、絶縁性の結晶成長基板に支持されたフロントプレーンであって、それぞれが第１導電型の第１半導体層および第２導電型の第２半導体層を有する複数のマイクロＬＥＤ、ならびに前記複数のマイクロＬＥＤの間に位置する素子分離領域を含み、前記素子分離領域が、前記第２半導体層に電気的に接続された少なくともひとつの金属プラグを有している、フロントプレーン、および前記フロントプレーンに支持された中間層であって、それぞれが前記複数のマイクロＬＥＤの前記第１半導体層に電気的に接続された複数の第１コンタクト電極、および前記金属プラグに接続された少なくともひとつの第２コンタクト電極を含む、中間層を備える積層構造体を用意する工程と、前記積層構造体上にバックプレーンを形成する工程であって、前記複数の第１コンタクト電極および前記少なくともひとつの第２コンタクト電極を介して前記複数のマイクロＬＥＤに電気的に接続された電気回路を有し、前記電気回路は複数の薄膜トランジスタを含む、バックプレーンを形成する工程と、を含む。前記積層構造体を用意する工程は、前記結晶成長基板を覆うマスク層であって、前記複数のマイクロＬＥＤの位置を規定する複数のマスク開口部を有する前記マスク層を形成する工程と、前記マスク開口部から前記第２半導体層および前記第１半導体層を、順次、成長させる工程とを含む。前記マスク層は導電材料から形成され、前記第２半導体層は前記マスク層にオーミック接触しており、前記バックプレーンを形成する工程は、前記積層構造体上に半導体層を堆積する工程と、前記積層構造体上の前記半導体層をパターニングする工程とを含む。 The method for manufacturing the micro LED device of the present disclosure is, in an exemplary embodiment, a front plane supported by an insulating crystal growth substrate, the first semiconductor layer of the first conductive type and the second conductive type, respectively. The element separation region includes a plurality of micro LEDs having the second semiconductor layer, and an element separation region located between the plurality of micro LEDs, and the element separation region is electrically connected to the second semiconductor layer. A front plane having a metal plug, and a plurality of first contacts electrically connected to the first semiconductor layer of the plurality of micro LEDs, each of which is an intermediate layer supported by the front plane. A step of preparing a laminated structure including an intermediate layer including an electrode and at least one second contact electrode connected to the metal plug, and a step of forming a back plane on the laminated structure. It has an electric circuit electrically connected to the plurality of micro LEDs via a plurality of first contact electrodes and the at least one second contact electrode, and the electric circuit forms a back plane including a plurality of thin films. Including the process of The steps of preparing the laminated structure are a step of forming the mask layer which is a mask layer covering the crystal growth substrate and has a plurality of mask openings defining the positions of the plurality of micro LEDs, and a step of forming the mask. This includes a step of sequentially growing the second semiconductor layer and the first semiconductor layer from the opening. The mask layer is formed of a conductive material, the second semiconductor layer is in ohmic contact with the mask layer, and the steps of forming the back plane include a step of depositing the semiconductor layer on the laminated structure and the step of depositing the semiconductor layer on the laminated structure. It includes a step of patterning the semiconductor layer on the laminated structure.
　ある実施形態において、前記素子分離領域の形状および位置は、前記マスク層が有する前記複数のマスク開口部から選択的に成長した前記第２半導体層および前記第１半導体層によって規定される。 In certain embodiments, the shape and position of the element separation region is defined by the second semiconductor layer and the first semiconductor layer selectively grown from the plurality of mask openings of the mask layer.
　ある実施形態において、前記積層構造体を用意する工程は、前記複数のマスク開口部から前記第２半導体層および前記第１半導体層を、順次、エピタキシャル成長させる工程の後、前記マスク層と前記第２半導体層との間でオーミック接触を完成する熱処理工程を含む。 In a certain embodiment, the step of preparing the laminated structure is a step of sequentially epitaxially growing the second semiconductor layer and the first semiconductor layer from the plurality of mask openings, and then the mask layer and the second. Includes a heat treatment step to complete ohmic contact with the semiconductor layer.
　ある実施形態において、前記積層構造体を用意する工程において、前記熱処理工程は、前記フロントプレーンを完成する前に行う。 In a certain embodiment, in the step of preparing the laminated structure, the heat treatment step is performed before the front plane is completed.
　ある実施形態において、前記複数のマスク開口部から前記第２半導体層および前記第１半導体層を、順次、エピタキシャル成長させる工程中の加熱により、前記マスク層と前記第２半導体層との間でオーミック接触を完成させる。 In a certain embodiment, ohmic contact between the mask layer and the second semiconductor layer is performed by heating during a step of sequentially epitaxially growing the second semiconductor layer and the first semiconductor layer from the plurality of mask openings. To complete.
　本発明の実施形態によれば、前記の課題を解決するマイクロＬＥＤデバイスおよびその製造方法が提供される。 According to the embodiment of the present invention, a micro LED device that solves the above-mentioned problems and a method for manufacturing the same are provided.
本開示によるμＬＥＤデバイス１０００の一部を示す断面図である。It is sectional drawing which shows a part of the μLED device 1000 by this disclosure. μＬＥＤデバイス１０００におけるμＬＥＤ２２０の配置例を示す平面図である。It is a top view which shows the arrangement example of the μLED 220 in the μLED device 1000. μＬＥＤデバイス１０００における金属プラグ２４の配置例を示す平面図である。It is a top view which shows the arrangement example of the metal plug 24 in the μLED device 1000. μＬＥＤデバイス１０００における金属プラグ２４の他の配置例を示す平面図である。It is a top view which shows the other arrangement example of the metal plug 24 in the μLED device 1000. μＬＥＤデバイス１０００における第１コンタクト電極３１および第２コンタクト電極３２の配置例を示す斜視図である。It is a perspective view which shows the arrangement example of the 1st contact electrode 31 and the 2nd contact electrode 32 in the μLED device 1000. μＬＥＤデバイス１０００における電気回路の一部の例を示す回路図である。It is a circuit diagram which shows a part example of the electric circuit in the μLED device 1000. μＬＥＤデバイス１０００の製造工程を模式的に示す斜視図である。It is a perspective view which shows typically the manufacturing process of the μLED device 1000. μＬＥＤデバイス１０００の製造工程を模式的に示す斜視図である。It is a perspective view which shows typically the manufacturing process of the μLED device 1000. μＬＥＤデバイス１０００の製造工程を模式的に示す斜視図である。It is a perspective view which shows typically the manufacturing process of the μLED device 1000. μＬＥＤデバイス１０００の製造工程を模式的に示す斜視図である。It is a perspective view which shows typically the manufacturing process of the μLED device 1000. μＬＥＤデバイス１０００の製造工程を模式的に示す斜視図である。It is a perspective view which shows typically the manufacturing process of the μLED device 1000. μＬＥＤデバイス１０００の製造工程を模式的に示す斜視図である。It is a perspective view which shows typically the manufacturing process of the μLED device 1000. μＬＥＤデバイス１０００の製造工程を模式的に示す斜視図である。It is a perspective view which shows typically the manufacturing process of the μLED device 1000. μＬＥＤデバイス１０００の製造工程を模式的に示す斜視図である。It is a perspective view which shows typically the manufacturing process of the μLED device 1000. 円柱形のμＬＥＤ２２０を備えるμＬＥＤデバイス１０００の一部を示す斜視図である。It is a perspective view which shows a part of the μLED device 1000 provided with the cylindrical μLED 220. 円柱形のμＬＥＤ２２０を備えるμＬＥＤデバイス１０００の平面図である。It is a top view of the μLED device 1000 including the cylindrical μLED 220. 本開示の実施形態におけるμＬＥＤデバイス１０００Ａの断面図である。It is sectional drawing of the μLED device 1000A in embodiment of this disclosure. μＬＥＤデバイス１０００Ａの製造工程を模式的に示す断面図である。It is sectional drawing which shows typically the manufacturing process of the μLED device 1000A. μＬＥＤデバイス１０００Ａの製造工程を模式的に示す断面図である。It is sectional drawing which shows typically the manufacturing process of the μLED device 1000A. μＬＥＤデバイス１０００Ａの製造工程を模式的に示す断面図である。It is sectional drawing which shows typically the manufacturing process of the μLED device 1000A. μＬＥＤデバイス１０００Ａの製造工程を模式的に示す断面図である。It is sectional drawing which shows typically the manufacturing process of the μLED device 1000A. μＬＥＤデバイス１０００Ａの製造工程を模式的に示す断面図である。It is sectional drawing which shows typically the manufacturing process of the μLED device 1000A. μＬＥＤデバイス１０００Ａの製造工程を模式的に示す断面図である。It is sectional drawing which shows typically the manufacturing process of the μLED device 1000A. μＬＥＤデバイス１０００Ａの製造工程を模式的に示す断面図である。It is sectional drawing which shows typically the manufacturing process of the μLED device 1000A. 本開示の実施形態におけるμＬＥＤデバイス１０００Ａの他の構成例を示す断面図である。It is sectional drawing which shows the other structural example of the μLED device 1000A in embodiment of this disclosure. 本開示の実施形態におけるμＬＥＤデバイス１０００Ａの更に他の構成例を示す断面図である。It is sectional drawing which shows still another structural example of the μLED device 1000A in embodiment of this disclosure. 本開示の実施形態の改変例におけるμＬＥＤデバイス１１００の構成例を示す断面図である。It is sectional drawing which shows the structural example of the μLED device 1100 in the modified example of the embodiment of this disclosure. 本開示による更に他の実施形態におけるμＬＥＤデバイス１０００Ｂの構成を模式的に示す断面図である。It is sectional drawing which shows typically the structure of the μLED device 1000B in still another Embodiment by this disclosure. 本開示による更に他の実施形態におけるμＬＥＤデバイス１０００Ｃの構成を模式的に示す断面図である。It is sectional drawing which shows typically the structure of the μLED device 1000C in still another Embodiment by this disclosure. 図１２ＡのμＬＥＤデバイス１０００Ｃの構成を模式的に示す斜視図である。It is a perspective view which shows typically the structure of the μLED device 1000C of FIG. 12A. 本開示による更に他の実施形態におけるμＬＥＤデバイス１０００Ｄの構成を模式的に示す断面図である。It is sectional drawing which shows typically the structure of the μLED device 1000D in still another Embodiment by this disclosure. 図１３ＡのμＬＥＤデバイス１０００Ｄの構成を模式的に示す斜視図である。It is a perspective view which shows typically the structure of the μLED device 1000D of FIG. 13A.
　＜定義＞
　本開示における「マイクロＬＥＤ」とは、占有領域のサイズが１００μｍ×１００μｍの領域内に含まれる大きさを有する発光ダイオード（ＬＥＤ）を意味する。マイクロＬＥＤが放射する「光」は、可視光に限定されず、可視、紫外、または赤外の電磁波を広く含む。以下、「マイクロＬＥＤ」を「μＬＥＤ」と表記することがある。 <Definition>
The “micro LED” in the present disclosure means a light emitting diode (LED) having a size included in an area of 100 μm × 100 μm in which the size of the occupied area is 100 μm × 100 μm. The "light" emitted by the micro LED is not limited to visible light, but includes a wide range of visible, ultraviolet, or infrared electromagnetic waves. Hereinafter, "micro LED" may be referred to as "μLED".
　μＬＥＤは、第１導電型の第１半導体層および第２導電型の第２半導体層を有する。第１導電型はｐ型およびｎ型の一方であり、第２導電型はｐ型およびｎ型の他方である。例えば第１導電型がｐ型であるとき、第２導電型はｎ型である。逆に第１導電型がｎ型であるとき、第２導電型はｐ型である。第１半導体層および第２半導体層のそれぞれは、単層構造または多層構造を有し得る。典型的には、少なくとも１個の量子井戸（またはダブルヘテロ構造）を有する発光層が第１半導体層と第２半導体層との間に形成される。 The μLED has a first conductive type first semiconductor layer and a second conductive type second semiconductor layer. The first conductive type is one of the p-type and the n-type, and the second conductive type is the other of the p-type and the n-type. For example, when the first conductive type is p type, the second conductive type is n type. On the contrary, when the first conductive type is n type, the second conductive type is p type. Each of the first semiconductor layer and the second semiconductor layer may have a single-layer structure or a multi-layer structure. Typically, a light emitting layer having at least one quantum well (or double heterostructure) is formed between the first semiconductor layer and the second semiconductor layer.
　本開示における「マイクロＬＥＤデバイス（μＬＥＤデバイス）」とは、複数のμＬＥＤを備えるデバイスである。μＬＥＤデバイスにおける複数のμＬＥＤを「μＬＥＤアレイ」と呼ぶことがある。μＬＥＤデバイスの典型例はディスプレイデバイスであるが、μＬＥＤデバイスはディスプレイデバイスに限定されない。 The "micro LED device (μLED device)" in the present disclosure is a device including a plurality of μLEDs. A plurality of μLEDs in a μLED device may be referred to as a “μLED array”. A typical example of a μLED device is a display device, but the μLED device is not limited to a display device.
　＜基本構成＞
　図１Ａおよび図１Ｂを参照して、本開示のμＬＥＤデバイスの基本構成例を説明する。図１Ａは、μＬＥＤデバイス１０００の一部を示す断面図である。図１Ｂは、μＬＥＤデバイス１０００におけるμＬＥＤアレイの配置例を示す平面図である。図１Ａに示されているμＬＥＤデバイス１０００の断面は、図１ＢのＡ－Ａ線断面に相当する。 <Basic configuration>
A basic configuration example of the μLED device of the present disclosure will be described with reference to FIGS. 1A and 1B. FIG. 1A is a cross-sectional view showing a part of the μLED device 1000. FIG. 1B is a plan view showing an arrangement example of the μLED array in the μLED device 1000. The cross section of the μLED device 1000 shown in FIG. 1A corresponds to the cross section taken along line AA of FIG. 1B.
　μＬＥＤデバイス１０００は、例えば１００万個を超えるような多数のμＬＥＤを備え得る。図１Ａおよび図１Ｂは、μＬＥＤデバイス１０００のうちの、数個のμＬＥＤを含む一部分のみを示している。μＬＥＤデバイス１０００の全体は、図示されている部分が周期的に配列された構成を備えている。 The μLED device 1000 may include a large number of μLEDs, for example, exceeding 1 million. 1A and 1B show only a portion of the μLED device 1000 containing a few μLEDs. The entire μLED device 1000 has a configuration in which the illustrated portions are periodically arranged.
　μＬＥＤデバイス１０００は、絶縁性の結晶成長基板１００と、結晶成長基板１００に支持されたフロントプレーン２００と、フロントプレーン２００に支持された中間層３００と、中間層に支持されたバックプレーン４００とを備えている。 The μLED device 1000 includes an insulating crystal growth substrate 100, a front plane 200 supported by the crystal growth substrate 100, an intermediate layer 300 supported by the front plane 200, and a backplane 400 supported by the intermediate layer. I have.
　添付図面において、μＬＥＤなどの各構成要素の縦方向サイズに対する横方向サイズの比率は、実施形態における実際の比率を必ずしも反映していない。図面では、わかりやすさを優先した比率で各構成要素が記載されている。また図面における各構成要素の向きは、実際にμＬＥＤデバイスを製造するときの向き、および、使用時における向きを何ら制限しない。図１Ａおよび図１Ｂには、参考のため、相互に直交するＸ軸、Ｙ軸、およびＺ軸の右手系座標軸が記載されている。 In the attached drawings, the ratio of the horizontal size to the vertical size of each component such as μLED does not necessarily reflect the actual ratio in the embodiment. In the drawings, each component is described in a ratio that prioritizes clarity. Further, the orientation of each component in the drawing does not limit the orientation when the μLED device is actually manufactured and the orientation when used. For reference, FIGS. 1A and 1B show right-handed coordinate axes of the X-axis, Y-axis, and Z-axis that are orthogonal to each other.
　＜結晶成長基板＞
　結晶成長基板１００は、μＬＥＤを構成する半導体結晶がエピタキシャル成長する基板である。以下、このような結晶成長基板を単に「基板（substrate）」と称する。基板１００の結晶成長が生じる面１００Ｔを「上面」または「結晶成長面」と呼び、基板１００の反対側の面１００Ｂを「下面」と称する。本明細書において、「上面」および「下面」の語句は、基板１００の実際の向きに依存することなく用いられる。 <Crystal growth substrate>
The crystal growth substrate 100 is a substrate on which semiconductor crystals constituting the μLED grow epitaxially. Hereinafter, such a crystal growth substrate is simply referred to as a "substrate". The surface 100T on which crystal growth of the substrate 100 occurs is referred to as an "upper surface" or "crystal growth surface", and the surface 100B on the opposite side of the substrate 100 is referred to as a "lower surface". As used herein, the terms "top" and "bottom" are used independently of the actual orientation of the substrate 100.
　本開示の実施形態で利用され得る半導体結晶の典型例は、窒化ガリウム系化合物半導体である。以下、窒化ガリウム系化合物半導体を「ＧａＮ」と表記することがある。ＧａＮにおけるガリウム（Ｇａ）原子の一部は、アルミニウム（Ａｌ）原子またはインジウム（Ｉｎ）原子によって置換されていてもよい。Ｇａ原子の一部がＡｌ原子で置換されたＧａＮを「ＡｌＧａＮ」と表記する場合がある。また、Ｇａ原子の一部がＩｎ原子で置換されたＧａＮを「ＩｎＧａＮ」と表記する場合がある。更には、Ｇａ原子の一部がＡｌ原子およびＩｎ原子で置換されたＧａＮを「ＡｌＩｎＧａＮ」または「ＩｎＡｌＧａＮ」と表記することがある。ＧａＮのバンドギャップは、ＡｌＧａＮのバンドギャップよりも小さく、ＩｎＧａＮのバンドギャップよりも大きい。なお、本開示では、構成原子の一部が他の原子で置換された窒化ガリウム系化合物半導体を総称して「ＧａＮ」と表記する場合がある。「ＧａＮ」には、不純物イオンとしてｎ型不純物および／またはｐ型不純物がドープされ得る。導電型がｎ型であるＧａＮは「ｎ－ＧａＮ」、導電型がｐ型であるＧａＮは「ｐ－ＧａＮ」と表記する。半導体結晶の成長方法の詳細については、後述する。なお、本開示の実施形態において、μＬＥＤを構成する半導体結晶は、ＧａＮ系半導体に限定されず、ＡｌＮ、ＩｎＮ、またはＡｌＩｎＮなどの窒化物半導体、あるいは他の半導体から形成されていてもよい。 A typical example of a semiconductor crystal that can be used in the embodiment of the present disclosure is a gallium nitride based compound semiconductor. Hereinafter, the gallium nitride based compound semiconductor may be referred to as “GaN”. A part of the gallium (Ga) atom in GaN may be replaced by an aluminum (Al) atom or an indium (In) atom. A GaN in which a part of a Ga atom is replaced with an Al atom may be referred to as "AlGaN". Further, GaN in which a part of Ga atom is replaced with In atom may be referred to as "InGaN". Further, GaN in which a part of Ga atom is replaced with Al atom and In atom may be referred to as "AlInGaN" or "InAlGaN". The bandgap of GaN is smaller than the bandgap of AlGaN and larger than the bandgap of InGaN. In the present disclosure, gallium nitride based compound semiconductors in which some of the constituent atoms are replaced with other atoms may be collectively referred to as “GaN”. The "GaN" can be doped with n-type impurities and / or p-type impurities as impurity ions. GaN whose conductive type is n-type is referred to as "n-GaN", and GaN whose conductive type is p-type is referred to as "p-GaN". The details of the semiconductor crystal growth method will be described later. In the embodiment of the present disclosure, the semiconductor crystal constituting the μLED is not limited to the GaN-based semiconductor, and may be formed of a nitride semiconductor such as AlN, InN, or AlInN, or another semiconductor.
　本開示における基板１００は、絶縁性を有しており、基板１００の上面１００Ｔは、複数の開口部を有するマスク層１５０によって覆われている。マスク層１５０は、例えば、チタニウム（Ｔｉ）、クロム（Ｃｒ）、モリブデン（Ｍｏ）、マンガン（Ｍｎ）、タングステン（Ｗ）、タンタル（Ｔａ）などの高融点金属（導電材料）から形成され得る。マスク層１５０は、後述する複数のμＬＥＤ２２０の位置および配列を規定する複数のマスク開口部１５０Ｇと、金属プラグ２４に接続される接続部１５０Ｃとを有している。接続部１５０Ｃは、マスク層１５０のうち、金属プラグ２４に接触している部分である。接続部１５０Ｃと金属プラグ２４との間に他の導電層が介在していてもよい。 The substrate 100 in the present disclosure has an insulating property, and the upper surface 100T of the substrate 100 is covered with a mask layer 150 having a plurality of openings. The mask layer 150 can be formed of, for example, a refractory metal (conductive material) such as titanium (Ti), chromium (Cr), molybdenum (Mo), manganese (Mn), tungsten (W), and tantalum (Ta). The mask layer 150 has a plurality of mask openings 150G that define the positions and arrangements of a plurality of μLED 220s, which will be described later, and a connection portion 150C that is connected to the metal plug 24. The connection portion 150C is a portion of the mask layer 150 that is in contact with the metal plug 24. Another conductive layer may be interposed between the connection portion 150C and the metal plug 24.
　基板１００の例は、サファイア基板である。サファイア基板は、可視光および波長３００ｎｍ以上の紫外線にとって透光性が高く、絶縁性の結晶成長基板１００として特に好ましい。 An example of the substrate 100 is a sapphire substrate. The sapphire substrate has high translucency for visible light and ultraviolet rays having a wavelength of 300 nm or more, and is particularly preferable as the insulating crystal growth substrate 100.
　本開示の実施形態において、基板１００は、最終的なμＬＥＤデバイス１０００の構成要素である。基板１００の厚さは、例えば３０μｍ以上１０００μｍ以下、好ましくは５００μｍ以下であり得る。基板１００の役割は、結晶成長のベースとなることであるため、μＬＥＤデバイス１０００の剛性は、基板１００以外の他の剛性部材によって補われてもよい。そのような剛性部材は、例えばバックプレーン４００に固着され得る。なお、製造工程中においては、基板１００の下面１００Ｂに基板１００の剛性を補う支持基板（不図示）を固定してもよい。このような支持基板は、最終的なμＬＥＤデバイス１０００からは除去されてもよいし、基板１００に固着されたまま使用されてもよい。 In the embodiments of the present disclosure, the substrate 100 is a component of the final μLED device 1000. The thickness of the substrate 100 can be, for example, 30 μm or more and 1000 μm or less, preferably 500 μm or less. Since the role of the substrate 100 is to serve as a base for crystal growth, the rigidity of the μLED device 1000 may be supplemented by a rigid member other than the substrate 100. Such a rigid member can be fixed to, for example, the backplane 400. During the manufacturing process, a support substrate (not shown) that supplements the rigidity of the substrate 100 may be fixed to the lower surface 100B of the substrate 100. Such a support substrate may be removed from the final μLED device 1000, or may be used while being fixed to the substrate 100.
　基板１００の上面（結晶成長面）１００Ｔには、結晶格子歪を緩和するような溝またはリッジなどの構造が付与されていてもよい。基板１００の下面１００Ｂには、μＬＥＤアレイから放射され、基板１００を透過してきた光の取り出し効率を向上させたり、光を拡散させたりするための微細な凹凸が形成されていてもよい。微細な凹凸の例はモスアイ構造を含む。モスアイ構造は、基板１００の下面１００Ｂにおける実効的な屈折率を連続的に変化させるため、基板１００の下面１００Ｂで基板１００の内側に反射される割合（反射率）を大きく低下させる（実質的にゼロにする）ことができる。 The upper surface (crystal growth surface) 100T of the substrate 100 may be provided with a structure such as a groove or a ridge that alleviates the crystal lattice strain. The lower surface 100B of the substrate 100 may be formed with fine irregularities for improving the extraction efficiency of the light radiated from the μLED array and transmitted through the substrate 100 or for diffusing the light. Examples of fine irregularities include a moth-eye structure. Since the moth-eye structure continuously changes the effective refractive index on the lower surface 100B of the substrate 100, the ratio (reflectance) reflected inside the substrate 100 on the lower surface 100B of the substrate 100 is significantly reduced (substantially). Can be zero).
　本開示において、図１Ａに示されるＺ軸の正方向（矢印の向き）を「結晶成長方向」または「半導体積層方向」と呼ぶ場合がある。また、基板１００の下面１００Ｂおよび上面１００Ｔを、それぞれ、基板１００の「正面」および「背面」と呼んでもよい。 In the present disclosure, the positive direction of the Z axis (direction of the arrow) shown in FIG. 1A may be referred to as "crystal growth direction" or "semiconductor lamination direction". Further, the lower surface 100B and the upper surface 100T of the substrate 100 may be referred to as "front" and "back" of the substrate 100, respectively.
　＜フロントプレーン＞
　フロントプレーン２００は、複数のμＬＥＤ２２０と、複数のμＬＥＤ２２０の間に位置する素子分離領域２４０とを含む。複数のμＬＥＤ２２０は、基板１００の上面１００Ｔに平行な２次元平面（ＸＹ面）内において、行および列状に配列され得る。図示される例において複数のμＬＥＤ２２０のそれぞれは、図１Ａに示されるように、第１導電型の第１半導体層２１および第２導電型の第２半導体層２２を有する。 <Front plane>
The front plane 200 includes a plurality of μLEDs 220 and an element separation region 240 located between the plurality of μLEDs 220. The plurality of μLED 220s can be arranged in rows and columns in a two-dimensional plane (XY plane) parallel to the upper surface 100T of the substrate 100. In the illustrated example, each of the plurality of μLED 220s has a first conductive type first semiconductor layer 21 and a second conductive type second semiconductor layer 22, as shown in FIG. 1A.
　本開示の実施形態において、各μＬＥＤ２２０の第２半導体層２２は、マスク層１５０のマスク開口部１５０Ｇに規定される領域に位置している。後述するように、この第２半導体層２２は、半導体結晶のエピタキシャル成長工程を開始するとき、基板１００の上面１００Ｔにおいてマスク開口部１５０Ｇを介して露出していた領域から、選択的に成長した半導体結晶から形成されている。このとき、マスク層１５０と第２半導体層２２と接する部分においてオーミック接触が実現している。オーミック接触を実現するための熱処理については後述する。 In the embodiment of the present disclosure, the second semiconductor layer 22 of each μLED 220 is located in the region defined by the mask opening 150G of the mask layer 150. As will be described later, when the epitaxial growth step of the semiconductor crystal is started, the second semiconductor layer 22 is a semiconductor crystal that is selectively grown from a region exposed through the mask opening 150G on the upper surface 100T of the substrate 100. Is formed from. At this time, ohmic contact is realized at the portion where the mask layer 150 and the second semiconductor layer 22 are in contact with each other. The heat treatment for achieving ohmic contact will be described later.
　本開示の実施形態において、各μＬＥＤ２２０は、他のμＬＥＤ２２０から独立して発光し得る発光層２３を有している。発光層２３は、第１半導体層２１と第２半導体層２２との間に位置している。素子分離領域２４０は、第２半導体層２２に電気的に接続された少なくともひとつの金属プラグ２４を有している。金属プラグ２４は、μＬＥＤ２２０の基板側電極として機能する。より具体的には、金属プラグ２４は、マスク層１５０の接続部１５０Ｃを介して複数のμＬＥＤ２２０の第２半導体層２２を相互に接続している。 In the embodiment of the present disclosure, each μLED 220 has a light emitting layer 23 that can emit light independently of the other μLED 220. The light emitting layer 23 is located between the first semiconductor layer 21 and the second semiconductor layer 22. The element separation region 240 has at least one metal plug 24 electrically connected to the second semiconductor layer 22. The metal plug 24 functions as a substrate-side electrode of the μLED 220. More specifically, the metal plug 24 connects the second semiconductor layers 22 of the plurality of μLED 220s to each other via the connecting portion 150C of the mask layer 150.
　第１導電型の第１半導体層２１の典型例は、ｐ－ＧａＮ層である。第２導電型の第２半導体層２２の典型例は、ｎ－ＧａＮ層である。ｐ－ＧａＮ層およびｎ－ＧａＮ層は、それぞれ、基板１００の上面１００Ｔに垂直な方向（半導体積層方向：Ｚ軸の正方向）に沿って同一の組成を有している必要はなく、多層構造を有し得る。前述したように、ＧａＮのＧａはＡｌおよび／またはＩｎによって少なくとも部分的に置換され得る。このような置換は、ＧａＮのバンドギャップおよび／または屈折率を調整するために行われ得る。また、ｐ型不純物およびｎ型不純物の濃度、すなわちドーピングレベルも、半導体積層方向（Ｚ軸の正方向）に沿って一様である必要はない。 A typical example of the first conductive type first semiconductor layer 21 is a p-GaN layer. A typical example of the second conductive type second semiconductor layer 22 is an n-GaN layer. The p-GaN layer and the n-GaN layer do not have to have the same composition along the direction perpendicular to the upper surface 100T of the substrate 100 (semiconductor stacking direction: positive direction of the Z axis), and have a multilayer structure. Can have. As mentioned above, Ga in GaN can be at least partially replaced by Al and / or In. Such substitutions may be made to adjust the bandgap and / or index of refraction of the GaN. Further, the concentrations of p-type impurities and n-type impurities, that is, the doping level, need not be uniform along the semiconductor stacking direction (positive direction of the Z axis).
　発光層２３の典型例は、少なくともひとつのＩｎＧａＮ井戸層を含む。発光層２３が複数のＩｎＧａＮ井戸層を含む場合、それぞれのＩｎＧａＮ井戸層の間には、ＩｎＧａＮ井戸層よりもバンドギャップが大きなＧａＮ障壁層またはＡｌＧａＮ障壁層が配置され得る。ＩｎＧａＮ井戸層およびＡｌＧａＮ障壁層は、それぞれＩｎＡｌＧａＮ井戸層およびＩｎＡｌＧａＮ障壁層であってもよい。ＩｎＧａＮ井戸層のバンドギャップは、発光波長を規定する。具体的には、真空中における発光波長をλ［ｎｍ］、バンドギャップをＥｇ［エレクトロンボルト：ｅＶ］とすると、λ×Ｅｇ＝１２４０の関係が成立する。従って、例えばλ＝４５０ｎｍの青色光を放射させるには、ＩｎＧａＮ井戸層のバンドギャップＥｇを約２．７６ｅＶに調整すればよい。ＩｎＧａＮ井戸層のバンドギャップは、ＩｎＧａＮ井戸層におけるＩｎ組成比率に応じて調整され得る。ＩｎＡｌＧａＮ井戸層を用いる場合は、同様にＩｎおよびＡｌ組成比率に応じてバンドギャップが調整され得る。基板１００上に成長するＩｎＧａＮ井戸層におけるＩｎ組成比率は、基板１００の全面において、ほぼ同一の値を持つ。このため、同一の基板１００上に形成された複数のμＬＥＤ２２０は、ほぼ等しい波長を有する光を放射することになる。 A typical example of the light emitting layer 23 includes at least one InGaN well layer. When the light emitting layer 23 includes a plurality of InGaN well layers, a GaN barrier layer or an AlGaN barrier layer having a bandgap larger than that of the InGaN well layer may be arranged between the InGaN well layers. The InGaN well layer and the AlGaN barrier layer may be the InAlGaN well layer and the InAlGaN barrier layer, respectively. The bandgap of the InGaN well layer defines the emission wavelength. Specifically, assuming that the emission wavelength in vacuum is λ [nm] and the band gap is Eg [electron volt: eV], the relationship of λ × Eg = 1240 is established. Therefore, for example, in order to emit blue light of λ = 450 nm, the bandgap Eg of the InGaN well layer may be adjusted to about 2.76 eV. The bandgap of the InGaN well layer can be adjusted according to the In composition ratio in the InGaN well layer. When the InAlGaN well layer is used, the bandgap can be similarly adjusted according to the In and Al composition ratio. The In composition ratio in the InGaN well layer growing on the substrate 100 has substantially the same value on the entire surface of the substrate 100. Therefore, the plurality of μLED 220s formed on the same substrate 100 emit light having substantially the same wavelength.
　各μＬＥＤ２２０を構成する上記複数の半導体層は、それぞれ、基板１００上にエピタキシャル成長した単結晶の層（エピタキシャル層）である。素子分離領域２４０は、基板１００上にエピタキシャル成長した複数の半導体層の間の空間によって形成されたトレンチ状の凹部（以下、「トレンチ」と称する）によって規定される。トレンチによって分離された個々のμＬＥＤ２２０の占有領域は、１００μｍ×１００μｍの領域内に含まれる大きさ（例えば１０μｍ×１０μｍの領域）を有している。なお、μＬＥＤ２２０の占有領域は、素子分離領域２４０によって区分された第１半導体層２１の輪郭によって規定される。 The plurality of semiconductor layers constituting each μLED 220 are single crystal layers (epitaxial layers) epitaxially grown on the substrate 100, respectively. The element separation region 240 is defined by a trench-shaped recess (hereinafter referred to as a “trench”) formed by a space between a plurality of semiconductor layers epitaxially grown on the substrate 100. The occupied region of each μLED 220 separated by the trench has a size (for example, a region of 10 μm × 10 μm) included in the region of 100 μm × 100 μm. The occupied area of the μLED 220 is defined by the contour of the first semiconductor layer 21 divided by the element separation area 240.
　図１Ｂに示されるように、素子分離領域２４０は各μＬＥＤ２２０を取り囲み、個々のμＬＥＤ２２０を他のμＬＥＤ２２０から分離している。より具体的には、素子分離領域２４０は、個々のμＬＥＤ２２０の第１半導体層２１および発光層２３を、他のμＬＥＤ２２０の第１半導体層２１および発光層２３から、電気的・空間的に分離している。 As shown in FIG. 1B, the element separation region 240 surrounds each μLED 220 and separates each μLED 220 from the other μLED 220. More specifically, the element separation region 240 electrically and spatially separates the first semiconductor layer 21 and the light emitting layer 23 of each μLED 220 from the first semiconductor layer 21 and the light emitting layer 23 of the other μLED 220. ing.
　本開示において、素子分離領域２４０は、半導体層の選択成長によって形成された複数のμＬＥＤ２２０の間に位置する領域であり、半導体層を深くエッチングして形成された凹部ではない。本開示の実施形態によれば、エッチングのために必要なリソグラフィなどの工程が不要になり、また、エッチングによる半導体層の損傷を防止できる。 In the present disclosure, the element separation region 240 is a region located between a plurality of μLEDs 220 formed by selective growth of the semiconductor layer, and is not a recess formed by deeply etching the semiconductor layer. According to the embodiment of the present disclosure, steps such as lithography required for etching are not required, and damage to the semiconductor layer due to etching can be prevented.
　この例において、素子分離領域２４０は、複数のμＬＥＤ２２０の間を埋める（fill）埋め込み絶縁物（embedded insulator）２５を有している。埋め込み絶縁物２５は、金属プラグ２４のための１個または複数個のスルーホールを有している。スルーホールは金属プラグ２４を構成する金属材料によって埋められている。金属プラグ２４は、異なる金属の層がスタックされた構造を有していてもよい。 In this example, the element separation region 240 has an embedded insulator 25 that fills the space between the plurality of μLEDs 220. The embedded insulator 25 has one or more through holes for the metal plug 24. The through holes are filled with the metal material constituting the metal plug 24. The metal plug 24 may have a structure in which different metal layers are stacked.
　図１Ｂに示される例では、複数の金属プラグ２４が離散的に配置されているが、本開示の実施形態は、このような例に限定されない。複数の金属プラグ２４のそれぞれが、対応するμＬＥＤ２２０を囲むリング形状を有していてもよい。また、金属プラグ２４は、図１Ｃに示すように、一方向に平行に延びるストライプ形状を有してもよいし、図１Ｄに示すように、格子形状を有する１個の導電物であってもよい。 In the example shown in FIG. 1B, a plurality of metal plugs 24 are arranged discretely, but the embodiment of the present disclosure is not limited to such an example. Each of the plurality of metal plugs 24 may have a ring shape surrounding the corresponding μLED 220. Further, the metal plug 24 may have a striped shape extending in parallel in one direction as shown in FIG. 1C, or may be a single conductor having a lattice shape as shown in FIG. 1D. Good.
　金属プラグ２４は、光を透過しない。このため、金属プラグ２４が、個々のμＬＥＤ２２０を囲む形状を有する場合（例えば図１Ｄの形状を有する場合）、金属プラグ２４は、個々のμＬＥＤ２２０から放射された光が、他のμＬＥＤ２２０から放射された光と混合されないようにする効果を生じさせる。金属プラグ２４がこのような遮光部材として機能する代わりに、個々のμＬＥＤ２２０を囲む遮光部材を、別途、素子分離領域２４０内に設けてもよい。このように素子分離領域２４０は、個々のμＬＥＤ２２０の発光層２３を他のμＬＥＤ２２０の発光層２３から光学的に分離する付加的な機能を有していてもよい。 The metal plug 24 does not transmit light. Therefore, when the metal plug 24 has a shape surrounding each μLED 220 (for example, when it has the shape of FIG. 1D), the metal plug 24 emits light emitted from each μLED 220 from another μLED 220. Produces the effect of preventing mixing with light. Instead of the metal plug 24 functioning as such a light-shielding member, a light-shielding member surrounding each μLED 220 may be separately provided in the element separation region 240. As described above, the element separation region 240 may have an additional function of optically separating the light emitting layer 23 of each μLED 220 from the light emitting layer 23 of another μLED 220.
　本開示の実施形態において、フロントプレーン２００の上面は、図１Ａに示されるように平坦化されていることが好ましい。このような平坦化は、素子分離領域２４０における金属プラグ２４および埋め込み絶縁物２５の上面のレベルが、μＬＥＤ２２０における第１半導体層２１の上面のレベルに略一致することにより実現されている。 In the embodiments of the present disclosure, it is preferable that the upper surface of the front plane 200 is flattened as shown in FIG. 1A. Such flattening is realized by the level of the upper surface of the metal plug 24 and the embedded insulator 25 in the element separation region 240 substantially matching the level of the upper surface of the first semiconductor layer 21 in the μLED 220.
　＜中間層＞
　中間層３００は、複数の第１コンタクト電極３１と、第２コンタクト電極３２とを含む（図１Ａ参照）。複数の第１コンタクト電極３１は、それぞれ、複数のμＬＥＤ２２０の第１半導体層２１に電気的に接続されている。少なくともひとつの第２コンタクト電極３２は、金属プラグ２４に接続されている。 <Middle layer>
The intermediate layer 300 includes a plurality of first contact electrodes 31 and a second contact electrode 32 (see FIG. 1A). Each of the plurality of first contact electrodes 31 is electrically connected to the first semiconductor layer 21 of the plurality of μLED 220s. At least one second contact electrode 32 is connected to the metal plug 24.
　図２は、第１コンタクト電極３１および第２コンタクト電極３２の配置例を示す斜視図である。図２では、コンタクト電極３１、３２の配置例を示すため、バックプレーン４００の記載が省略されている。図２に示されている構造は、μＬＥＤデバイス１０００の一部分にすぎず、前述したように、μＬＥＤデバイス１０００の実施形態は多数のμＬＥＤ２２０を備えている。 FIG. 2 is a perspective view showing an arrangement example of the first contact electrode 31 and the second contact electrode 32. In FIG. 2, since the arrangement example of the contact electrodes 31 and 32 is shown, the description of the backplane 400 is omitted. The structure shown in FIG. 2 is only a part of the μLED device 1000, and as described above, the embodiment of the μLED device 1000 includes a large number of μLED 220s.
　図２に示されている第２コンタクト電極３２は、金属プラグ２４を介して、第２半導体層２２に電気的に接続されている。第２コンタクト電極３２の形状およびサイズは、図示されている例に限定されない。前述したように、金属プラグ２４が多様な形状を取り得るため、金属プラグ２４を介して第２半導体層２２に電気的に接続される限り、第２コンタクト電極３２の配置の自由度は高い。これに対して、第１コンタクト電極３１は、複数のμＬＥＤ２２０の第１半導体層２１に、それぞれ、独立して電気的に接続されている。基板１００の上面１００Ｔに垂直な方向から視たとき、第１コンタクト電極３１の形状および大きさは、第１半導体層２１の形状および大きさに一致している必要はない。 The second contact electrode 32 shown in FIG. 2 is electrically connected to the second semiconductor layer 22 via a metal plug 24. The shape and size of the second contact electrode 32 are not limited to the examples shown. As described above, since the metal plug 24 can take various shapes, the degree of freedom in arranging the second contact electrode 32 is high as long as it is electrically connected to the second semiconductor layer 22 via the metal plug 24. On the other hand, the first contact electrode 31 is independently electrically connected to the first semiconductor layer 21 of the plurality of μLED 220s. When viewed from a direction perpendicular to the upper surface 100T of the substrate 100, the shape and size of the first contact electrode 31 need not match the shape and size of the first semiconductor layer 21.
　前述したように、フロントプレーン２００の上面が平坦化されているため、基板１００から第１コンタクト電極３１および第２コンタクト電極３２までの距離、言い換えると、これらのコンタクト電極３１、３２の「高さ」または「レベル」は、相互に等しい。このことは、半導体製造技術を用いて後述するバックプレーン４００を形成することを容易にする。本開示における「半導体製造技術」とは、半導体、絶縁体、または導電体の薄膜を堆積する工程と、リソグラフィおよびエッチング工程によって薄膜をパターニングする工程とを含む。なお、本明細書において、「平坦化された表面」とは、その表面に存在する凸部または凹部による段差が３００ｎｍ以下である表面を意味するものとする。好ましい実施形態において、この段差は１００ｎｍ以下である。 As described above, since the upper surface of the front plane 200 is flattened, the distance from the substrate 100 to the first contact electrode 31 and the second contact electrode 32, in other words, the “height” of these contact electrodes 31 and 32. "Or" level "are equal to each other. This facilitates the formation of the backplane 400, which will be described later, using semiconductor manufacturing technology. The "semiconductor manufacturing technique" in the present disclosure includes a step of depositing a thin film of a semiconductor, an insulator, or a conductor, and a step of patterning the thin film by a lithography and etching steps. In the present specification, the "flattened surface" means a surface having a step difference of 300 nm or less due to a convex portion or a concave portion existing on the surface. In a preferred embodiment, this step is 100 nm or less.
　再び図１Ａを参照する。図１Ａに示される例において、中間層３００は、平坦な表面を有する層間絶縁層３８を含む。層間絶縁層３８は、第１および第２コンタクト電極３１、３２をそれぞれバックプレーン４００の電気回路に接続するための複数のコンタクトホールを有している。コンタクトホールは、ビア電極３６によって埋められている。 Refer to FIG. 1A again. In the example shown in FIG. 1A, the intermediate layer 300 includes an interlayer insulating layer 38 having a flat surface. The interlayer insulating layer 38 has a plurality of contact holes for connecting the first and second contact electrodes 31 and 32 to the electric circuit of the backplane 400, respectively. The contact hole is filled with the via electrode 36.
　本開示の実施形態では、バックプレーン４００を形成する前の段階において、層間絶縁層３８の上面を平坦化することが好ましい。こうすることによって、層間絶縁層３８の上面に対して、半導体製造技術を用いたバックプレーン４００の形成が容易になる。なお、中間層３００の上面を平坦化した場合、フロントプレーン２００の上面については必ずしも平坦化を行わなくてもよい。しかし、中間層３００の上面とフロントプレーン２００の上面の両方が平坦化されていると、バックプレーン４００に含まれる電気回路の形成がより容易になる。 In the embodiment of the present disclosure, it is preferable to flatten the upper surface of the interlayer insulating layer 38 before forming the backplane 400. By doing so, it becomes easy to form the backplane 400 on the upper surface of the interlayer insulating layer 38 by using the semiconductor manufacturing technique. When the upper surface of the intermediate layer 300 is flattened, the upper surface of the front plane 200 does not necessarily have to be flattened. However, if both the upper surface of the intermediate layer 300 and the upper surface of the front plane 200 are flattened, the formation of the electric circuit included in the backplane 400 becomes easier.
　バックプレーン４００を形成する前、あるいは形成途中の工程における絶縁層の平坦化には、エッチバック以外に化学的機械的研磨（ＣＭＰ）処理が好適に用いられ得る。 In addition to etch back, chemical mechanical polishing (CMP) treatment can be preferably used for flattening the insulating layer before or during the process of forming the backplane 400.
　＜バックプレーン＞
　バックプレーン４００は、図１Ａにおいて不図示の電気回路を有している。電気回路は、複数の第１コンタクト電極３１および少なくともひとつの第２コンタクト電極３２を介して、複数のμＬＥＤ２２０に電気的に接続されている。電気回路は、複数の薄膜トランジスタ（ＴＦＴ）およびその他の回路要素を含む。後述するように、ＴＦＴのそれぞれは、基板１００に支持されたフロントプレーン２００および／または中間層３００上に成長した半導体層を有している。 <Backplane>
The backplane 400 has an electrical circuit (not shown) in FIG. 1A. The electric circuit is electrically connected to the plurality of μLED 220s via the plurality of first contact electrodes 31 and at least one second contact electrode 32. The electrical circuit includes a plurality of thin film transistors (TFTs) and other circuit elements. As will be described later, each of the TFTs has a semiconductor layer grown on the front plane 200 and / or the intermediate layer 300 supported by the substrate 100.
　図３は、μＬＥＤデバイス１０００がディスプレイデバイスとして機能する場合におけるサブ画素の基本的な等価回路図である。ディスプレイデバイスの１個の画素は、例えばＲ、Ｇ、Ｂなどの異なる色のサブ画素によって構成され得る。図３に示される例において、バックプレーン４００の電気回路は、選択用ＴＦＴ素子Ｔｒ１、駆動用ＴＦＴ素子Ｔｒ２、保持容量ＣＨを有している。図３に示されているμＬＥＤは、バックプレーン４００ではなく、フロントプレーン２００内に存在している。 FIG. 3 is a basic equivalent circuit diagram of sub-pixels when the μLED device 1000 functions as a display device. One pixel of the display device may be composed of sub-pixels of different colors such as R, G, B and the like. In the example shown in FIG. 3, the electric circuit of the backplane 400 has a selection TFT element Tr1, a driving TFT element Tr2, and a holding capacitance CH. The μLED shown in FIG. 3 resides in the front plane 200 rather than in the backplane 400.
　図３の例において、選択用ＴＦＴ素子Ｔｒ１は、データラインＤＬと選択ラインＳＬとに接続されている。データラインＤＬは、表示されるべき映像を規定するデータ信号を運ぶ配線である。データラインＤＬは選択用ＴＦＴ素子Ｔｒ１を介して駆動用ＴＦＴ素子Ｔｒ２のゲートに電気的に接続される。選択ラインＳＬは、選択用ＴＦＴ素子Ｔｒ１のオン／オフを制御する信号を運ぶ配線である。駆動用ＴＦＴ素子Ｔｒ２は、パワーラインＰＬとμＬＥＤとの間の導通状態を制御する。駆動用ＴＦＴ素子Ｔｒ２がオンすれば、μＬＥＤを介してパワーラインＰＬから接地ラインＧＬに電流が流れる。この電流がμＬＥＤを発光させる。選択用ＴＦＴ素子Ｔｒ１がオフしても、保持容量ＣＨにより、駆動用ＴＦＴ素子Ｔｒ２のオン状態は維持される。 In the example of FIG. 3, the selection TFT element Tr1 is connected to the data line DL and the selection line SL. The data line DL is a wiring that carries a data signal that defines an image to be displayed. The data line DL is electrically connected to the gate of the driving TFT element Tr2 via the selection TFT element Tr1. The selection line SL is a wiring that carries a signal for controlling on / off of the selection TFT element Tr1. The driving TFT element Tr2 controls the conduction state between the power line PL and the μLED. When the driving TFT element Tr2 is turned on, a current flows from the power line PL to the ground line GL via the μLED. This current causes the μLED to emit light. Even if the selection TFT element Tr1 is turned off, the driving TFT element Tr2 is maintained in the ON state due to the holding capacitance CH.
　バックプレーン４００の電気回路は、選択用ＴＦＴ素子Ｔｒ１、駆動用ＴＦＴ素子Ｔｒ２、データラインＤＬ、および選択ラインＳＬなどを含み得るが、電気回路の構成は、このような例に限定されない。 The electric circuit of the backplane 400 may include a selection TFT element Tr1, a drive TFT element Tr2, a data line DL, a selection line SL, and the like, but the configuration of the electric circuit is not limited to such an example.
　本実施形態におけるμＬＥＤデバイス１０００は、単独でディスプレイデバイスとして機能し得るが、複数のμＬＥＤデバイス１０００をタイリングして、より大きな表示面積を有するディスプレイデバイスを実現してもよい。 Although the μLED device 1000 in the present embodiment can function as a display device by itself, a plurality of μLED devices 1000 may be tiling to realize a display device having a larger display area.
　＜製造方法＞
　次に、μＬＥＤデバイス１０００を製造する方法の基本的な例を説明する。 <Manufacturing method>
Next, a basic example of a method for manufacturing the μLED device 1000 will be described.
　まず、図４Ａに示すように、上面（結晶成長面）１００Ｔを有する基板１００を用意する。本実施形態における基板１００は、サファイア基板である。図４Ａは、上面１００Ｔに平行な平面に沿って広がる基板１００の一部を示しているにすぎない。 First, as shown in FIG. 4A, a substrate 100 having an upper surface (crystal growth surface) 100T is prepared. The substrate 100 in this embodiment is a sapphire substrate. FIG. 4A shows only a part of the substrate 100 extending along a plane parallel to the upper surface 100T.
　図４Ｂに示すように、基板１００の上面１００Ｔをマスク層１５０によって覆う。マスク層１５０は、高融点金属膜を堆積した後、その高融点金属膜の所定領域をエッチングして複数のマスク開口部１５０Ｇを形成することによって得られる。あるいは、リフトオフ法を用いて、所定領域にマスク開口部１５０Ｇを有するマスク層１５０を形成してもよい。マスク開口部１５０Ｇは、基板１００の上面１００Ｔを部分的に露出させる。マスク層１５０の厚さは、例えば、１００ｎｍ以上１０００ｎｍ以下の範囲内（例えば約３００ｎｍ）にある。 As shown in FIG. 4B, the upper surface 100T of the substrate 100 is covered with the mask layer 150. The mask layer 150 is obtained by depositing a refractory metal film and then etching a predetermined region of the refractory metal film to form a plurality of mask openings 150G. Alternatively, the lift-off method may be used to form the mask layer 150 having the mask opening 150G in a predetermined region. The mask opening 150G partially exposes the upper surface 100T of the substrate 100. The thickness of the mask layer 150 is, for example, in the range of 100 nm or more and 1000 nm or less (for example, about 300 nm).
　マスク開口部１５０Ｇの形状および位置は、各μＬＥＤ２２０の第２半導体層２２の形状および位置を規定する。図４Ｂに示す例において、マスク開口部１５０Ｇの形状は矩形であるが、マスク開口部１５０Ｇの形状は、この例に限定されない。また、マスク開口部１５０Ｇの配置も図４Ｂに示す例に限定されない。マスク開口部１５０Ｇのサイズまたは形状を調整することにより、発光波長を広い範囲で変化させることができる。このことは、１個の基板１００上に異なる波長で発光する複数のμＬＥＤ２２０を同時に形成することを可能にする。 The shape and position of the mask opening 150G defines the shape and position of the second semiconductor layer 22 of each μLED 220. In the example shown in FIG. 4B, the shape of the mask opening 150G is rectangular, but the shape of the mask opening 150G is not limited to this example. Further, the arrangement of the mask opening 150G is not limited to the example shown in FIG. 4B. By adjusting the size or shape of the mask opening 150G, the emission wavelength can be changed in a wide range. This makes it possible to simultaneously form a plurality of μLEDs 220 that emit light at different wavelengths on one substrate 100.
　図４Ｃに示すように、基板１００の上面１００Ｔの露出部分から第２導電型の第２半導体層２２をエピタキシャル成長させる。このとき、第２半導体層２２は、マスク層１５０上にはエピタキシャル成長しない。しかし、マスク開口部１５０Ｇからエピタキシャル成長した第２半導体層２２の一部は、マスク層１５０の表面に沿って横方向に成長してもよい。このとき、マスク層１５０と第２半導体層２２との間でオーミック接触が実現していることが好ましい。特に良好なオーミック接触を実現するためには、適切な温度での熱処理が必要である。μＬＥＤ２２０を形成するためのエピタキシャル成長工程中にマスク層１５０と第２半導体層２２とが充分に加熱され、その結果、オーミック接触が完成することもある。しかし、結晶成長中の加熱がオーミック接触の実現に不充分な場合、μＬＥＤ２２の形成するためのエピタキシャル成長工程が終わった後、オーミック接触を完成するための熱処理を付加的に実行することが好ましい。第２半導体層２２の横方向成長は、第２半導体層２２とマスク層１５０の表面との接触面積を拡大する。前述したように、エピタキシャル成長中の加熱、または一連のエピタキシャル成長後の適切な熱処理を行うことにより、第２半導体層２２とマスク層１５０の表面との間に良好なオーミック接触が実現される。このため、第２半導体層２２とマスク層１５０との間の電気抵抗（コンタクト抵抗）が低下する。第２半導体層２２の横方向に成長する部分の長さは、縦方向に成長する部分の厚さを超えることはない。また、マスク層１５０は、第２半導体層２２に対して良好なオーミック接触を実現する材料、例えばＴｉ、Ｃｒ、Ｍｏ、Ｍｎ、Ｗ、およびＴａからなる群から選択された少なくとも１種の高融点金属から形成され得る。これらの高融点金属の仕事関数は４．５ｅＶ以下であるため、第２半導体層２２がｎ型であるとき、第２半導体層２２に対して良好なオーミック接触を形成できる。また、このような高融点金属は、発光層２３およびｎ型の第１半導体層２１と接触しても、高い抵抗性を示す。 As shown in FIG. 4C, the second conductive type second semiconductor layer 22 is epitaxially grown from the exposed portion of the upper surface 100T of the substrate 100. At this time, the second semiconductor layer 22 does not epitaxially grow on the mask layer 150. However, a part of the second semiconductor layer 22 epitaxially grown from the mask opening 150G may grow laterally along the surface of the mask layer 150. At this time, it is preferable that ohmic contact is realized between the mask layer 150 and the second semiconductor layer 22. Heat treatment at an appropriate temperature is required to achieve particularly good ohmic contact. During the epitaxial growth step for forming the μLED 220, the mask layer 150 and the second semiconductor layer 22 are sufficiently heated, and as a result, ohmic contact may be completed. However, if the heating during crystal growth is insufficient to achieve ohmic contact, it is preferable to additionally perform a heat treatment to complete the ohmic contact after the epitaxial growth step for forming the μLED 22 is completed. The lateral growth of the second semiconductor layer 22 expands the contact area between the second semiconductor layer 22 and the surface of the mask layer 150. As described above, good ohmic contact between the second semiconductor layer 22 and the surface of the mask layer 150 is realized by heating during epitaxial growth or by performing appropriate heat treatment after a series of epitaxial growth. Therefore, the electrical resistance (contact resistance) between the second semiconductor layer 22 and the mask layer 150 decreases. The length of the portion of the second semiconductor layer 22 that grows in the horizontal direction does not exceed the thickness of the portion that grows in the vertical direction. Further, the mask layer 150 has a high melting point of at least one selected from the group consisting of materials that realize good ohmic contact with the second semiconductor layer 22, for example, Ti, Cr, Mo, Mn, W, and Ta. It can be formed from metal. Since the work function of these refractory metals is 4.5 eV or less, good ohmic contact with the second semiconductor layer 22 can be formed when the second semiconductor layer 22 is n-type. Further, such a refractory metal exhibits high resistance even when it comes into contact with the light emitting layer 23 and the n-type first semiconductor layer 21.
　したがって、マスク層１５０は、第２半導体層２２上に成長する発光層２３および第１半導体層２１に対しては電気抵抗性を示す。このように、マスク層１５０は、半導体結晶のエピタキシャル成長時に高温に耐え、かつ、第２半導体層２２に対しては良好なオーミック接触を実現する一方、発光層２３および第１半導体層２１に対しては電気的抵抗性を示すことが望ましい。 Therefore, the mask layer 150 exhibits electrical resistance to the light emitting layer 23 and the first semiconductor layer 21 that grow on the second semiconductor layer 22. As described above, the mask layer 150 withstands high temperatures during epitaxial growth of the semiconductor crystal and realizes good ohmic contact with the second semiconductor layer 22, while with respect to the light emitting layer 23 and the first semiconductor layer 21. Is desirable to exhibit electrical resistance.
　次に、図４Ｄに示すように、第２半導体層２２の上面および側面から発光層２３、および第１導電型の第１半導体層２１を含む複数の半導体層をエピタキシャル成長させる。各半導体層は、窒化ガリウム系化合物半導体の単結晶エピタキシャル成長層である。窒化ガリウム系化合物半導体の成長は、例えばＭＯＣＶＤ（Metal Organic Chemical Vapor Deposition）法で行うことができる。各導電型を規定する不純物は、結晶成長中に気相中からドープされ得る。 Next, as shown in FIG. 4D, a plurality of semiconductor layers including the light emitting layer 23 and the first conductive type first semiconductor layer 21 are epitaxially grown from the upper surface and the side surface of the second semiconductor layer 22. Each semiconductor layer is a single crystal epitaxial growth layer of a gallium nitride based compound semiconductor. The gallium nitride based compound semiconductor can be grown by, for example, the MOCVD (Metal Organic Chemical Vapor Deposition) method. Impurities defining each conductive type can be doped from the gas phase during crystal growth.
　上記の選択成長の結果、図４Ｄに示されるように、それぞれの間に空間（トレンチ）を有する複数のμＬＥＤ２２０を形成することができる。こうして、半導体層のエッチングを行うことなく、素子分離のためのトレンチが形成される。マスク開口部１５０Ｇを介して露出していた基板１００の上面１００Ｔから選択的に成長した半導体が横方向にも成長し得ることを考慮すると、μＬＥＤ２２０の配列ピッチ（中心間距離）は、選択成長によって形成する半導体層（エピタキシャル成長層）の高さの２倍以上に設定され得る。また、金属プラグ２４が形成される領域では、トレンチの幅が金属プラグ２４の幅よりも大きくなるように、μＬＥＤ２２０の配列ピッチが決定される。同一パターンを有するマスク層１５０を使用しても、選択成長によって形成する半導体層の高さを変更すると、μＬＥＤ２２０の大きさおよびトレンチの幅を変更することができる。 As a result of the above selective growth, as shown in FIG. 4D, a plurality of μLED 220s having a space (trench) between them can be formed. In this way, a trench for element separation is formed without etching the semiconductor layer. Considering that the semiconductor selectively grown from the upper surface 100T of the substrate 100 exposed through the mask opening 150G can also grow in the lateral direction, the arrangement pitch (intercenter distance) of the μLED 220 is determined by the selective growth. It can be set to twice or more the height of the semiconductor layer (epitaxial growth layer) to be formed. Further, in the region where the metal plug 24 is formed, the arrangement pitch of the μLED 220 is determined so that the width of the trench is larger than the width of the metal plug 24. Even if the mask layer 150 having the same pattern is used, the size of the μLED 220 and the width of the trench can be changed by changing the height of the semiconductor layer formed by selective growth.
　本実施形態では、一連のエピタキシャル成長における加熱により、マスク層１５０を構成する高融点金属材料と第２半導体層２２との間で良好なオーミック接触が得られる。良好なオーミック接触を得るために、エピタキシャル成長中の加熱では不足な場合は、エピタキシャル成長工程の後、第２半導体層２２とマスク層１５０の表面との間の良好なオーミック接触を得るために付加的な熱処理を行うことが好ましい。熱処理の温度は、マスク層１５０を構成する金属材料と第２半導体層２２の材料との相互反応（界面近傍での合金化）が進行する温度であればよい。例えば、Ｔｉ層とＧａＮ半導体層との間でオーミック接触を実現するには、５００～６００℃を下限とする熱処理を行えばよい。熱処理の時間は、熱処理の温度に依存するが、例えば１～１０分程度、または、それ以上である。 In the present embodiment, good ohmic contact is obtained between the refractory metal material constituting the mask layer 150 and the second semiconductor layer 22 by heating in a series of epitaxial growth. If heating during epitaxial growth is insufficient to obtain good ohmic contact, then after the epitaxial growth step, additional to obtain good ohmic contact between the surface of the second semiconductor layer 22 and the mask layer 150. It is preferable to perform heat treatment. The temperature of the heat treatment may be any temperature at which the interaction (alloying near the interface) between the metal material constituting the mask layer 150 and the material of the second semiconductor layer 22 proceeds. For example, in order to realize ohmic contact between the Ti layer and the GaN semiconductor layer, heat treatment with a lower limit of 500 to 600 ° C. may be performed. The heat treatment time depends on the heat treatment temperature, but is, for example, about 1 to 10 minutes or more.
　次に、図４Ｅに示すように、μＬＥＤ２２０の間の空間（トレンチ）に素子分離領域２４０を形成する。具体的には、隣接するμＬＥＤ２２０の間に形成されている空間（トレンチ）を有機または無機の絶縁材料で埋めて埋め込み絶縁物２５を形成する。例えば、ＣＶＤ法などの薄膜堆積技術によって絶縁材料を堆積した後、μＬＥＤ２２０の上面が露出するまで研磨などの平坦化を行ってもよい。また、トレンチ内に液状の熱硬化性樹脂または紫外線硬化樹脂を供給し、熱または紫外線によって硬化させてもよい。液状の樹脂材料を用いることにより、上面が平坦な埋め込み絶縁物２５を形成することが容易になる。その後、フォトリソグラフィおよびエッチング技術を用いることにより、金属プラグ２４のためのスルーホール（図４Ｅでは不図示）を埋め込み絶縁物２５の所望の位置に形成する。 Next, as shown in FIG. 4E, an element separation region 240 is formed in the space (trench) between the μLED 220s. Specifically, the space (trench) formed between the adjacent μLED 220s is filled with an organic or inorganic insulating material to form an embedded insulator 25. For example, after depositing the insulating material by a thin film deposition technique such as the CVD method, flattening such as polishing may be performed until the upper surface of the μLED 220 is exposed. Further, a liquid thermosetting resin or an ultraviolet curable resin may be supplied into the trench and cured by heat or ultraviolet rays. By using the liquid resin material, it becomes easy to form the embedded insulator 25 having a flat upper surface. A through hole for the metal plug 24 (not shown in FIG. 4E) is then formed at the desired location of the embedded insulator 25 by using photolithography and etching techniques.
　次に、図４Ｆに示すように、素子分離領域２４０内のスルーホールに金属プラグ２４を形成した後、第１コンタクト電極３１および第２コンタクト電極３２を形成する。この例における素子分離領域２４０は、埋め込み絶縁物２５と、埋め込み絶縁物２５の複数のスルーホール内にそれぞれ設けられた複数の金属プラグ２４とを有している。 Next, as shown in FIG. 4F, after forming the metal plug 24 in the through hole in the element separation region 240, the first contact electrode 31 and the second contact electrode 32 are formed. The element separation region 240 in this example has an embedded insulator 25 and a plurality of metal plugs 24 each provided in a plurality of through holes of the embedded insulator 25.
　図４Ｇに示すように中間層３００の層間絶縁層（厚さ：例えば５００ｎｍ～１５００ｎｍ）３８を形成した後、バックプレーン４００の電気回路をフロントプレーン２００のμＬＥＤ２２０に接続するための複数のコンタクトホール（図４Ｇにおいて不図示）を層間絶縁層３８に形成する。コンタクトホールは、下層に位置するコンタクト電極３１、３２に達するように形成される。コンタクトホールはビア電極で埋められる。なお、層間絶縁層３８の上面はＣＭＰ処理によって平滑化され得る。 After forming the interlayer insulating layer (thickness: 500 nm to 1500 nm) 38 of the intermediate layer 300 as shown in FIG. 4G, a plurality of contact holes (thickness: for example, 500 nm to 1500 nm) for connecting the electric circuit of the backplane 400 to the μLED 220 of the frontplane 200. (Not shown in FIG. 4G) is formed on the interlayer insulating layer 38. The contact hole is formed so as to reach the contact electrodes 31 and 32 located in the lower layer. The contact hole is filled with via electrodes. The upper surface of the interlayer insulating layer 38 can be smoothed by CMP treatment.
　図４Ｈに示すように、中間層３００上にバックプレーン４００を形成する。本開示において特徴的な点は、バックプレーン４００を中間層３００上に張り付けるのではなく、バックプレーン４００を構成する各種の電子素子および配線を、半導体製造技術により、フロントプレーン２００および中間層３００を含む積層構造体の上に直接に形成することにある。この結果、バックプレーン４００に含まれる複数のＴＦＴのそれぞれは、基板１００に支持されたフロントプレーン２００および中間層３００からなる積層構造体の上に成長した半導体層を有している。 As shown in FIG. 4H, the backplane 400 is formed on the intermediate layer 300. A characteristic point in the present disclosure is that the backplane 400 is not attached on the intermediate layer 300, but various electronic elements and wirings constituting the backplane 400 are mounted on the front plane 200 and the intermediate layer 300 by semiconductor manufacturing technology. It is to be formed directly on the laminated structure containing. As a result, each of the plurality of TFTs included in the backplane 400 has a semiconductor layer grown on a laminated structure composed of a front plane 200 and an intermediate layer 300 supported by the substrate 100.
　前述したように、フロントプレーン２００の上面および中間層３００の上面が平坦化されていると、ＴＦＴを含むバックプレーン４００を半導体製造技術によって製造することが容易になる。一般に、半導体製造技術によってＴＦＴを形成する場合、堆積した半導体層、絶縁層、および金属層のパターニングを行う必要がある。このようなパターニングは、露光を伴うリソグラフィ工程によって実現される。堆積した半導体層、絶縁層、および金属層の下地に大きな段差が存在する場合、露光時の焦点が合わず、精度の高い微細パターニングが実現しない。本開示の実施形態では、素子分離領域２４０を含むフロントプレーン２００の全体が平坦化されることにより、中間層３００も平坦化され、半導体製造技術によるバックプレーン４００の形成が容易になる。 As described above, when the upper surface of the front plane 200 and the upper surface of the intermediate layer 300 are flattened, it becomes easy to manufacture the backplane 400 including the TFT by the semiconductor manufacturing technology. Generally, when a TFT is formed by a semiconductor manufacturing technique, it is necessary to pattern the deposited semiconductor layer, insulating layer, and metal layer. Such patterning is realized by a lithography process involving exposure. If there is a large step on the base of the deposited semiconductor layer, insulating layer, and metal layer, the focus will not be achieved during exposure, and highly accurate fine patterning will not be realized. In the embodiment of the present disclosure, by flattening the entire front plane 200 including the element separation region 240, the intermediate layer 300 is also flattened, and the backplane 400 can be easily formed by the semiconductor manufacturing technique.
　上述の例において、μＬＥＤ２２０の形状は、概略的に直方体であるが、μＬＥＤ２２０の形状は、図５Ａおよび図５Ｂに示されるように、円柱であってもよいし、六角柱などの多角柱、あるいは楕円柱であってもよい。図５Ａは、円柱形のμＬＥＤ２２０を備えるμＬＥＤデバイスの一部を示す斜視図であり、図５Ｂは、その平面図である。図５Ｂに示される例において、素子分離領域２４０は、個々のμＬＥＤ２２０の側面を覆う埋め込み絶縁物２５と、μＬＥＤ２２０の間の空間を埋める金属プラグ２４とを備えている。この金属プラグ２４の働きにより、素子分離領域２４０は、個々のμＬＥＤ２２０から放射された光を他のμＬＥＤ２２０から放射された光と混合しないようにすることができる。 In the above example, the shape of the μLED 220 is generally a rectangular parallelepiped, but the shape of the μLED 220 may be a cylinder, a polygonal column such as a hexagonal column, or a polygonal column as shown in FIGS. 5A and 5B. It may be an elliptical column. FIG. 5A is a perspective view showing a part of the μLED device including the cylindrical μLED 220, and FIG. 5B is a plan view thereof. In the example shown in FIG. 5B, the element separation region 240 includes an embedded insulator 25 that covers the sides of each μLED 220 and a metal plug 24 that fills the space between the μLED 220s. By the action of the metal plug 24, the element separation region 240 can prevent the light emitted from each μLED 220 from being mixed with the light emitted from another μLED 220.
　各μＬＥＤ２２０の形状および位置は、マスク層１５０のマスク開口部１５０Ｇの形状および位置によって規定されるため、マスク層１５０のパターンを調整することにより、個々のμＬＥＤ２２０の形状および位置、さらには、μＬＥＤ２２０の配列パターンを任意に制御することができる。 Since the shape and position of each μLED 220 is defined by the shape and position of the mask opening 150G of the mask layer 150, by adjusting the pattern of the mask layer 150, the shape and position of each μLED 220 and further the μLED 220 The array pattern can be controlled arbitrarily.
　＜実施形態＞
　以下、本開示によるμＬＥＤデバイスの基本的な実施形態を更に詳細に説明する。 <Embodiment>
Hereinafter, a basic embodiment of the μLED device according to the present disclosure will be described in more detail.
　図６を参照する。本実施形態におけるμＬＥＤデバイス１０００Ａは、前述した基本構成例と同様の構成を備えているディスプレイデバイスである。このμＬＥＤデバイス１０００Ａは、可視光および／または紫外を透過する結晶成長基板（以下、「基板」）１００と、基板１００上に形成されたフロントプレーン２００と、フロントプレーン２００上に形成された中間層３００と、中間層３００上に形成されたバックプレーン４００とを備えている。 Refer to FIG. The μLED device 1000A in this embodiment is a display device having the same configuration as the above-mentioned basic configuration example. The μLED device 1000A includes a crystal growth substrate (hereinafter, “substrate”) 100 that transmits visible light and / or ultraviolet rays, a front plane 200 formed on the substrate 100, and an intermediate layer formed on the front plane 200. It includes a 300 and a backplane 400 formed on the intermediate layer 300.
　次に、図７Ａから図１１を参照しながら、本実施形態におけるμＬＥＤデバイス１０００Ａの構成および製造方法の一例を説明する。 Next, an example of the configuration and manufacturing method of the μLED device 1000A in the present embodiment will be described with reference to FIGS. 7A to 11.
　まず、図７Ａを参照する。図７Ａは、本実施形態で使用する基板１００の構成例を示している。マスク層１５０は、例えば、厚さが１００～１０００ｎｍ、典型的には３００ｎｍの高融点金属の層から形成され得る。金属製のマスク層１５０は、ｎ－ＧａＮ層２２ｎと良好なオーミック接触をしていることにより、ｎ側の共通電極の一部として機能し得る。マスク層１５０は、スパッタ法などの薄膜堆積技術により形成された後、フォトリソグラフィおよびエッチング技術によってパターニングされる。このパターニングによって所定の形状を有する複数のマスク開口部１５０Ｇが形成される。本実施形態における複数のマスク開口部１５０Ｇのそれぞれは、個々のμＬＥＤ２２０のｎ－ＧａＮ層２２ｎの形状および位置を決定する。 First, refer to FIG. 7A. FIG. 7A shows a configuration example of the substrate 100 used in this embodiment. The mask layer 150 can be formed, for example, from a layer of refractory metal having a thickness of 100 to 1000 nm, typically 300 nm. The metal mask layer 150 can function as a part of the common electrode on the n side by making good ohmic contact with the n-GaN layer 22n. The mask layer 150 is formed by a thin film deposition technique such as a sputtering method, and then patterned by a photolithography and etching technique. By this patterning, a plurality of mask openings 150G having a predetermined shape are formed. Each of the plurality of mask openings 150G in the present embodiment determines the shape and position of the n-GaN layer 22n of each μLED 220.
　本実施形態では、ＭＯＣＶＤ装置の反応室内に基板１００を置き、種々のガスを供給して窒化ガリウム（ＧａＮ）系化合物半導体のエピタキシャル成長を行う。本実施形態における基板１００の本体は、例えば厚さが約５０～６００μｍのサファイア基板である。基板１００の上面１００Ｔは、典型的にはＣ面（０００１）であるが、ｍ面、ａ面、ｒ面などの非極性面または半極性面を上面に有していてもよい。また、上面１００Ｔは、これらの結晶面から数度程度は傾斜していてもよい。基板１００は典型的には円板状であり、その直径は、例えば１インチから８インチであり得る。基板１００の形状およびサイズは、この例に限定されず、矩形であってもよい。また、円板状の基板１００を用いて製造工程を進め、最終的に基板１００の周辺をカットして矩形形状に加工してもよい。また、比較的な大きな基板１００を用いて製造工程を進め、最終的に１枚の基板１００を分割して複数のμＬＥＤデバイスを形成してもよい（シンギュレーション）。 In the present embodiment, the substrate 100 is placed in the reaction chamber of the MOCVD apparatus, and various gases are supplied to perform epitaxial growth of the gallium nitride (GaN) -based compound semiconductor. The main body of the substrate 100 in this embodiment is, for example, a sapphire substrate having a thickness of about 50 to 600 μm. The upper surface 100T of the substrate 100 is typically a C surface (0001), but may have a non-polar surface or a semi-polar surface such as an m surface, an a surface, or an r surface on the upper surface. Further, the upper surface 100T may be inclined by about several degrees from these crystal planes. The substrate 100 is typically disc-shaped, and its diameter can be, for example, 1 to 8 inches. The shape and size of the substrate 100 are not limited to this example, and may be rectangular. Further, the manufacturing process may be advanced using the disk-shaped substrate 100, and finally the periphery of the substrate 100 may be cut and processed into a rectangular shape. Further, the manufacturing process may be advanced using the relatively large substrate 100, and finally one substrate 100 may be divided to form a plurality of μLED devices (singulation).
　ＭＯＣＶＤ装置の反応室内には、まず、トリメチルガリウム（ＴＭＧ）またはトリエチルガリウム（ＴＥＧ）、キャリアガスである水素（Ｈ2）、窒素（Ｎ2）と、アンモニア（ＮＨ3）およびシラン（ＳｉＨ4）を供給する。基板１００を１１００℃程度に加熱する。こうして、図７Ｂに示すように、基板１００のマスク層１５０によって覆われていない領域、すなわちマスク開口部１５０Ｇによって規定される領域から、ｎ－ＧａＮ層（厚さ：例えば２μｍ）２２ｎを選択的に成長させる。シランはｎ型ドーパントであるＳｉを供給する原料ガスである。ｎ型不純物のドーピング濃度は、例えば５×１０17ｃｍ-3であり得る。 In the reaction chamber of the MOCVD equipment, first, trimethylgallium (TMG) or triethylgallium (TEG), hydrogen (H 2 ) and nitrogen (N 2 ) as carrier gases, ammonia (NH 3 ) and silane (SiH 4 ) To supply. The substrate 100 is heated to about 1100 ° C. Thus, as shown in FIG. 7B, the n-GaN layer (thickness: for example, 2 μm) 22n is selectively selected from the region not covered by the mask layer 150 of the substrate 100, that is, the region defined by the mask opening 150G. Grow. Silane is a raw material gas that supplies Si, which is an n-type dopant. The doping concentration of n-type impurities can be, for example, 5 × 10 17 cm -3 .
　次にＳｉＨ4の供給を止め、基板１００の温度を８００℃未満まで降温して、図７Ｃに示すように、ｎ－ＧａＮ層２２ｎの表面に発光層２３を形成する。具体的には、まず、ＧａＮ障壁層を成長させる。更にトリメチルインジウム（ＴＭＩ）の供給を開始してＩｎyＧａ1-yＮ（０＜ｙ＜１）井戸層を成長させる。ＧａＮ障壁層とＩｎyＧａ1-yＮ（０＜ｙ＜１）井戸層は２周期以上で交互に成長させることにより、発光部として機能するＧａＮ／ＩｎＧａＮ多重量子井戸を有する発光層（厚さ：例えば１００ｎｍ）２３を形成することができる。ＩｎyＧａ1-yＮ（０＜ｙ＜１）井戸層の数が多い方が、大電流駆動時において井戸層内部のキャリア密度が過剰に大きくなることを抑制できる。１つの発光層２３が２つのＧａＮ障壁層によって挟まれた単一のＩｎyＧａ1-yＮ（０＜ｙ＜１）井戸層を有していてもよい。ｎ－ＧａＮ層２２ｎの上にＩｎyＧａ1-yＮ（０＜ｙ＜１）井戸層を直接形成し、ＩｎyＧａ1-yＮ（０＜ｙ＜１）井戸層の上にＧａＮ障壁層を形成してもよい。ＩｎyＧａ1-yＮ（０＜ｙ＜１）井戸層は、Ａｌを含んでいてもよい。例えば、ＩｎyＧａ1-yＮ（０＜ｙ＜１）井戸層は、ＡｌxＩｎyＧａzＮ（０≦ｘ＜１、０＜ｙ＜１、０＜ｚ＜１）から形成されていてもよい。 Next, the supply of SiH 4 is stopped, the temperature of the substrate 100 is lowered to less than 800 ° C., and the light emitting layer 23 is formed on the surface of the n—GaN layer 22n as shown in FIG. 7C. Specifically, first, the GaN barrier layer is grown. Further, the supply of trimethylindium (TMI) is started to grow the In y Ga 1-y N (0 <y <1) well layer. A light emitting layer (thickness) having a GaN / InGaN multiple quantum well that functions as a light emitting part by alternately growing a GaN barrier layer and an In y Ga 1-y N (0 <y <1) well layer in two or more cycles. : For example, 100 nm) 23 can be formed. When the number of In y Ga 1-y N (0 <y <1) well layers is large, it is possible to prevent the carrier density inside the well layers from becoming excessively large when driven by a large current. One light emitting layer 23 may have a single In y Ga 1-y N (0 <y <1) well layer sandwiched between two GaN barrier layers. An In y Ga 1-y N (0 <y <1) well layer is directly formed on the n-GaN layer 22n, and a GaN barrier is formed on the In y Ga 1-y N (0 <y <1) well layer. Layers may be formed. The In y Ga 1-y N (0 <y <1) well layer may contain Al. For example, In y Ga 1-y N (0 <y <1) well layer, Al x In y Ga z N (0 ≦ x <1,0 <y <1,0 <z <1) formed from You may.
　次に、発光層２３の形成後、一旦、ＴＭＩの供給を停止させる。その後、キャリアガス（水素）に窒素に加えて、アンモニアの供給を再開する。成長温度を８５０℃～１０００℃に上昇させ、トリメチルアルミニウム（ＴＭＡ）と、ｐ型ドーパントであるＭｇの原料としてビスシクロペンタジエニルマグネシウム（Ｃｐ2Ｍｇ）を供給し、ｐ－ＡｌＧａＮオーバーフロー抑制層を成長させてもよい。次にＴＭＡの供給を停止し、ｐ－ＧａＮ層（厚さ：例えば０．５μｍ）２１ｐを成長させる。ｐ型不純物のドーピング濃度は、例えば５×１０17ｃｍ-3であり得る。したがって、本実施形態のマスク層１５０に使用される高融点金属は、少なくとも融点が１１００℃を超えるものであることが好ましく、Ｔｉ（融点：１６６６℃）、Ｃｒ（同：１８５７℃）、Ｍｏ（同：２６２３℃）、Ｍｎ（同：１２４６℃）、Ｗ（同：３４０７℃）、Ｔａ（同：２９８５℃）などを好適に使用することができる。 Next, after the light emitting layer 23 is formed, the supply of TMI is temporarily stopped. After that, the carrier gas (hydrogen) is added to nitrogen, and the supply of ammonia is restarted. The growth temperature was raised to 850 ° C to 1000 ° C, and trimethylaluminum (TMA) and biscyclopentadienyl magnesium (Cp 2 Mg) were supplied as raw materials for Mg, which is a p-type dopant, to form a p-AlGaN overflow suppression layer. You may grow it. Next, the supply of TMA is stopped, and the p-GaN layer (thickness: for example, 0.5 μm) 21p is grown. The doping concentration of p-type impurities can be, for example, 5 × 10 17 cm -3 . Therefore, the refractory metal used for the mask layer 150 of the present embodiment preferably has a melting point of at least 1100 ° C., Ti (melting point: 1666 ° C.), Cr (same: 1857 ° C.), Mo ( The same: 2623 ° C.), Mn (same as above: 1246 ° C.), W (same as above: 3407 ° C.), Ta (same as above: 2985 ° C.) and the like can be preferably used.
　本実施形態によれば、マスク層１５０のマスク開口部１５０Ｇの形状および配置により、任意の形状および配置でμＬＥＤ２２０を形成できる。 According to this embodiment, the μLED 220 can be formed in any shape and arrangement depending on the shape and arrangement of the mask opening 150G of the mask layer 150.
　本実施形態では、上述のように、エピタキシャル成長工程の温度が高く、ｎ－ＧａＮ層２２ｎとマスク層１５０の表面との間で良好なオーミック接触が得られる。このため、オーミック接触を完成するための付加的な熱処理工程を、フロントプレーン２００の完成前に実行しておく必要は特にない。 In the present embodiment, as described above, the temperature of the epitaxial growth step is high, and good ohmic contact can be obtained between the n-GaN layer 22n and the surface of the mask layer 150. Therefore, it is not particularly necessary to perform an additional heat treatment step for completing the ohmic contact before the completion of the front plane 200.
　図７Ｄに示すように、素子分離領域２４０を規定する空間を埋め込み絶縁物２５で満たす。埋め込み絶縁物２５の材料および形成方法は、任意である。図示されている例において、埋め込み絶縁物２５の上面は平坦化され、ｐ－ＧａＮ層２１ｐの上面と同一のレベルに位置している。本実施形態では、インクジェット法を用いて選択的に素子分離領域２４０に対して熱硬化性樹脂を滴下し、しばらく静置することで表面を平坦化する。その後加熱して樹脂を硬化させる。 As shown in FIG. 7D, the space defining the element separation region 240 is filled with the embedded insulator 25. The material and method of forming the embedded insulator 25 are arbitrary. In the illustrated example, the upper surface of the embedded insulator 25 is flattened and located at the same level as the upper surface of the p-GaN layer 21p. In the present embodiment, the surface is flattened by selectively dropping a thermosetting resin onto the device separation region 240 using an inkjet method and allowing it to stand for a while. Then it is heated to cure the resin.
　図７Ｅに示すように、埋め込み絶縁物２５の一部にマスク層１５０に達する貫通孔（スルーホール）２６を形成する。このスルーホール２６は、金属プラグ２４の位置および形状を規定する。スルーホール２６は、例えば一辺が５μｍ以上の矩形形状、また直径５μｍ以上の円形を有している。また、スルーホール２６は、例えば図１Ｃおよび図１Ｄに示されるような形状を有する金属プラグ２４を収容する形状を有していてもよい。 As shown in FIG. 7E, a through hole 26 reaching the mask layer 150 is formed in a part of the embedded insulator 25. The through hole 26 defines the position and shape of the metal plug 24. The through hole 26 has, for example, a rectangular shape having a side of 5 μm or more and a circular shape having a diameter of 5 μm or more. Further, the through hole 26 may have a shape for accommodating a metal plug 24 having a shape as shown in FIGS. 1C and 1D, for example.
　図７Ｆに示すように、スルーホール２６を埋める金属プラグ２４を形成し、フロントプレーン２００の上面を平坦化する。金属プラグ２４の下端は、マスク層１５０に電気的に接触する。マスク層１５０のうち、金属プラグ２４の下端が接触する部分は、接続部１５０Ｃとして機能する。その後、第１コンタクト電極３１および第２コンタクト電極３２を形成する。平坦化は、例えば、エッチバック、選択成長、ＣＭＰまたはリフトオフなどの各種のプロセスによって行うことができる。 As shown in FIG. 7F, a metal plug 24 that fills the through hole 26 is formed, and the upper surface of the front plane 200 is flattened. The lower end of the metal plug 24 comes into electrical contact with the mask layer 150. The portion of the mask layer 150 that comes into contact with the lower end of the metal plug 24 functions as the connecting portion 150C. After that, the first contact electrode 31 and the second contact electrode 32 are formed. Flattening can be performed by various processes such as etchback, selective growth, CMP or lift-off.
　金属プラグ２４は、金属製のマスク層１５０と接触するため、半導体層と接触させる場合と異なり組合せの自由度が増すため、任意の金属、または他の導電性材料から形成され得る。 Since the metal plug 24 comes into contact with the metal mask layer 150, the degree of freedom of combination increases unlike the case of contacting with the semiconductor layer, so that the metal plug 24 can be formed from any metal or other conductive material.
　第１および第２コンタクト電極３１、３２は、金属層の堆積およびパターニングによって形成され得る。第１コンタクト電極３１とμＬＥＤ２２０のｐ－ＧａＮ層２１ｐとの間では、金属－半導体界面が形成される。ｐ型のオーミック接触を実現するため、第１コンタクト電極３１の材料は、例えば白金（Ｐｔ）および／またはパラジウム（Ｐｄ）などの仕事関数が大きい金属から選択され得る。ＰｔまたはＰｄの層（厚さ：約５０ｎｍ）を形成した後、例えば、３５０℃以上４００℃以下の温度で３０秒程度の熱処理が行われ得る。ｐ－ＧａＮ層２１ｐに直接に接触する部分にＰｔまたはＰｄの層が存在していれば、その層の上には他の金属、例えばＴｉ層（厚さ：約５０ｎｍ）および／またはＡｕ層（厚さ：約２００ｎｍ）が積層されていてもよい。 The first and second contact electrodes 31 and 32 can be formed by depositing and patterning a metal layer. A metal-semiconductor interface is formed between the first contact electrode 31 and the p-GaN layer 21p of the μLED 220. To achieve p-type ohmic contact, the material of the first contact electrode 31 can be selected from metals with a high work function, such as platinum (Pt) and / or palladium (Pd). After forming the Pt or Pd layer (thickness: about 50 nm), heat treatment can be performed, for example, at a temperature of 350 ° C. or higher and 400 ° C. or lower for about 30 seconds. If a Pt or Pd layer is present in the portion that is in direct contact with the p-GaN layer 21p, another metal such as a Ti layer (thickness: about 50 nm) and / or an Au layer (thickness: about 50 nm) and / or Au layer (thickness: about 50 nm) and / or Au layer Thickness: about 200 nm) may be laminated.
　ｐ－ＧａＮ層２１ｐの上部で、かつ第１コンタクト電極３１の下層には、ｐ型不純物が相対的に高濃度にドープされた領域が形成されていてもよい。第２コンタクト電極３２は、半導体ではなく、金属プラグ２４と電気的に接続される。このため、第２コンタクト電極３２の材料は、広い範囲から選択可能である。第１コンタクト電極３１および第２コンタクト電極３２は、一枚の連続した金属層をパターニングすることによって形成されてもよい。このパターニングは、リフトオフも含む。第１コンタクト電極３１および第２コンタクト電極３２の厚さが相互に等しいと、後述するＴＦＴ４０などの、バックプレーン４００における電気回路との接続が容易になる。 A region in which p-type impurities are doped at a relatively high concentration may be formed in the upper part of the p-GaN layer 21p and in the lower layer of the first contact electrode 31. The second contact electrode 32 is electrically connected to the metal plug 24 instead of the semiconductor. Therefore, the material of the second contact electrode 32 can be selected from a wide range. The first contact electrode 31 and the second contact electrode 32 may be formed by patterning one continuous metal layer. This patterning also includes lift-off. When the thicknesses of the first contact electrode 31 and the second contact electrode 32 are equal to each other, it becomes easy to connect to an electric circuit in the backplane 400 such as the TFT 40 described later.
　第１および第２コンタクト電極３１、３２を形成した後、これらは層間絶縁層（厚さ：例えば５００ｎｍから１５００ｎｍ）３８によって覆われる。ある好ましい例において、層間絶縁層３８の上面はＣＭＰ処理などによって平坦化され得る。上面が平坦化された層間絶縁層３８の厚さは、「平均厚さ」を意味する。 After forming the first and second contact electrodes 31 and 32, these are covered with an interlayer insulating layer (thickness: for example, 500 nm to 1500 nm) 38. In a preferred example, the upper surface of the interlayer insulating layer 38 can be flattened by CMP treatment or the like. The thickness of the interlayer insulating layer 38 whose upper surface is flattened means "average thickness".
　図７Ｇに示すように、層間絶縁層３８にコンタクトホール３９を形成する。コンタクトホール３９は、その後に形成されるビア電極３６（不図示）によって、バックプレーン４００の電気回路をフロントプレーン２００のμＬＥＤ２２０に電気的に接続するために使用される。 As shown in FIG. 7G, a contact hole 39 is formed in the interlayer insulating layer 38. The contact hole 39 is used to electrically connect the electrical circuit of the backplane 400 to the μLED 220 of the frontplane 200 by a via electrode 36 (not shown) formed thereafter.
　再び図６を参照して、バックプレーン４００の電気回路に含まれるＴＦＴの構造例および形成方法を以下に説明する。 With reference to FIG. 6 again, a structural example of the TFT included in the electric circuit of the backplane 400 and a method of forming the TFT will be described below.
　図６に示されている例において、ＴＦＴ４０は、層間絶縁層３８上に形成されたドレイン電極４１およびソース電極４２と、ドレイン電極４１およびソース電極４２のそれぞれの上面の少なくとも一部に接触する半導体薄膜４３と、半導体薄膜４３上に形成されたゲート絶縁膜４４と、ゲート絶縁膜４４上に形成されたゲート電極４５とを有している。図示されている例において、ドレイン電極４１およびソース電極４２は、それぞれ、コンタクトホール内に形成されたビア電極３６によって第１コンタクト電極３１および第２コンタクト電極３２に接続されている。これらＴＦＴ４０の構成要素のそれぞれは、公知の半導体製造技術によって形成され得る。図示されているＴＦＴ４０は、ドレイン電極４１およびソース電極４２の直下に形成されたビア電極３６によって、駆動対象となるフロントプレーン２００のμＬＥＤ２２０に電気的に接続されている点で、公知のＴＦＴ構成とは異なる。 In the example shown in FIG. 6, the TFT 40 is a semiconductor that contacts at least a part of the upper surfaces of the drain electrode 41 and the source electrode 42 formed on the interlayer insulating layer 38 and the drain electrode 41 and the source electrode 42, respectively. It has a thin film 43, a gate insulating film 44 formed on the semiconductor thin film 43, and a gate electrode 45 formed on the gate insulating film 44. In the illustrated example, the drain electrode 41 and the source electrode 42 are connected to the first contact electrode 31 and the second contact electrode 32 by a via electrode 36 formed in the contact hole, respectively. Each of these components of the TFT 40 can be formed by known semiconductor manufacturing techniques. The TFT 40 shown has a known TFT configuration in that it is electrically connected to the μLED 220 of the front plane 200 to be driven by a via electrode 36 formed directly below the drain electrode 41 and the source electrode 42. Is different.
　半導体薄膜４３は、多結晶シリコン、非晶質シリコン、酸化物半導体、および／または窒化ガリウム系半導体から形成され得る。多結晶シリコンは、例えば薄膜堆積技術によって非晶質シリコンを中間層３００の層間絶縁層３８上に堆積した後、非晶質シリコンをレーザビームで結晶化することにより、形成され得る。このようにして形成される多結晶シリコンは、ＬＴＰＳ（Low-Temperature Polｙ Silicon）と称される。多結晶シリコンはリソグラフィおよびエッチング工程で所望の形状にパターニングされる。 The semiconductor thin film 43 can be formed from polycrystalline silicon, amorphous silicon, oxide semiconductors, and / or gallium nitride based semiconductors. The polycrystalline silicon can be formed, for example, by depositing amorphous silicon on the interlayer insulating layer 38 of the intermediate layer 300 by a thin film deposition technique, and then crystallizing the amorphous silicon with a laser beam. The polycrystalline silicon formed in this way is called LTPS (Low-Temperature Poly Silicon). The polycrystalline silicon is patterned into the desired shape in the lithography and etching steps.
　図６におけるＴＦＴ４０は、絶縁層（厚さ：例えば５００ｎｍ～３０００ｎｍ）４６に覆われている。絶縁層４６には、不図示の開口孔が設けられ、ＴＦＴ４０の例えばゲート電極４５を外部のドライバ集積回路素子などに接続することを可能にしている。絶縁層４６の上面も平坦化されていることが好ましい。バックプレーン４００の電気回路は、図示されていないＴＦＴ、キャパシタ、およびダイオードなどの回路要素を含み得る。このため、絶縁層４６は、複数の絶縁層が積層された構成を有していてもよく、その場合の各絶縁層には、必要に応じて回路要素を接続するビア電極が設けられ得る。また、各絶縁層上には、必要に応じて配線が形成され得る。 The TFT 40 in FIG. 6 is covered with an insulating layer (thickness: for example, 500 nm to 3000 nm) 46. The insulating layer 46 is provided with an opening hole (not shown), which makes it possible to connect the TFT 40, for example, the gate electrode 45 to an external driver integrated circuit element or the like. It is preferable that the upper surface of the insulating layer 46 is also flattened. The electrical circuit of the backplane 400 may include circuit elements such as TFTs, capacitors, and diodes (not shown). Therefore, the insulating layer 46 may have a structure in which a plurality of insulating layers are laminated, and in that case, each insulating layer may be provided with a via electrode for connecting circuit elements, if necessary. Further, wiring may be formed on each insulating layer as needed.
　本実施形態におけるバックプレーン４００は、下層に位置するμＬＥＤ２２０の上に半導体製造技術によって形成されており、コンタクトホール３９とビア電極３６が、バックプレーン４００よりも下層に配置されたμＬＥＤ２２０に電気的に接合するように形成されている点に特徴を有している。このため、例えばＴＦＴ４０のドレイン電極４１およびソース電極４２は、フロントプレーン２００を覆うように堆積した金属層をパターニングすることによって形成され得る。このようなパターニングは、リソグラフィ技術による高精度の位置合わせを可能にする。特に本実施形態では、フロントプレーン２００および／または中間層３００がいずれも平坦化されているため、リソグラフィの解像度を高めることが可能になる。その結果、例えば２０μｍ以下、極端な例では５μｍ以下の微細ピッチで配列された多数のμＬＥＤ２２０を備えるデバイスを歩留まり良く、かつ、低価格で製造することが可能になる。 The backplane 400 in the present embodiment is formed by semiconductor manufacturing technology on the μLED 220 located in the lower layer, and the contact hole 39 and the via electrode 36 are electrically formed in the μLED 220 arranged in the lower layer than the backplane 400. It is characterized in that it is formed so as to be joined. Therefore, for example, the drain electrode 41 and the source electrode 42 of the TFT 40 can be formed by patterning a metal layer deposited so as to cover the front plane 200. Such patterning enables highly accurate alignment by lithographic techniques. In particular, in the present embodiment, since the front plane 200 and / or the intermediate layer 300 are both flattened, it is possible to increase the resolution of lithography. As a result, it becomes possible to manufacture a device having a large number of μLED 220s arranged at a fine pitch of, for example, 20 μm or less, and in an extreme case, 5 μm or less, with good yield and at a low price.
　図６に示されるＴＦＴ４０の構成は、一例である。説明をわかりやすくするため、ＴＦＴ４０のドレイン電極４１が第１コンタクト電極３１に電気的に接続されている例を説明しているが、ＴＦＴ４０のドレイン電極４１はバックプレーン４００内の他の回路要素または配線に接続されていてもよい。また、ＴＦＴ４０のソース電極４２は、第２コンタクト電極３２に電気的に接続されている必要はない。第２コンタクト電極３２は、μＬＥＤ２２０のｎ－ＧａＮ層２２ｎに共通して所定の電位を与える配線（例えばグランド配線）に接続され得る。重要な点は、素子分離領域２４０に設けられた金属プラグ２４が、その直上に位置するバックプレーン４００内の電気回路に接続されていることにある。１個の連続した金属プラグ２４または複数の金属プラグ２４を介して、多数のμＬＥＤ２２０に電流を流すためには、電流経路上の電気抵抗を低下させることが必要になる。 The configuration of the TFT 40 shown in FIG. 6 is an example. For the sake of clarity, an example in which the drain electrode 41 of the TFT 40 is electrically connected to the first contact electrode 31 is described, but the drain electrode 41 of the TFT 40 may be another circuit element in the backplane 400 or It may be connected to the wiring. Further, the source electrode 42 of the TFT 40 does not need to be electrically connected to the second contact electrode 32. The second contact electrode 32 may be connected to a wiring (for example, a ground wiring) that commonly gives a predetermined potential to the n-GaN layer 22n of the μLED 220. An important point is that the metal plug 24 provided in the element separation region 240 is connected to the electric circuit in the backplane 400 located directly above the metal plug 24. In order to pass a current through a large number of μLED 220s through one continuous metal plug 24 or a plurality of metal plugs 24, it is necessary to reduce the electric resistance on the current path.
　本実施形態において、バックプレーン４００の電気回路は、バックプレーン４００よりも下層に設けられた第１コンタクト電極３１および第２コンタクト電極３２にそれぞれ接続された複数の金属層（ドレイン電極４１およびソース電極４２として機能する金属層）を有している。このような構成を採用することにより、上述の電気抵抗を低下させ、消費電力を低減することが可能になる。リソグラフィ技術により、これらの電極３１、３２およびバックプレーン４００内の電気回路を形成するには、下地が平坦であることが求められる。下地に大きな凹凸が存在すると、リソグラフィ工程におけるパターン形成の精度が低下するからである。本実施形態では、フロントプレーン２００および中間層３００が平坦化されているため、バックプレーン４００をリソグラフィ技術を用いて高い精度で歩留まり良く形成することが可能になる。また、本実施形態において、複数の第１コンタクト電極３１は、それぞれ、複数のμＬＥＤ２２０のｐ－ＧａＮ層２１ｐを覆い、遮光層または反射層として機能する。個々の第１コンタクト電極３１は、μＬＥＤ２２０の上面、すなわち、ｐ－ＧａＮ層２１ｐの上面の全体を全て覆っている必要はない。第１コンタクト電極３１の形状、サイズ、および位置は、十分に低いコンタクト抵抗を実現し、かつ、発光層２３から放射された光がＴＦＴ４０のチャネル領域に入射することを充分に抑制するように決定される。なお、発光層２３から放射された光がＴＦＴ４０のチャネル領域に入射しないようにすることは、他の金属層を適切な位置に配置することによっても実現し得る。 In the present embodiment, the electric circuit of the backplane 400 has a plurality of metal layers (drain electrode 41 and source electrode) connected to the first contact electrode 31 and the second contact electrode 32 provided below the backplane 400, respectively. It has a metal layer) that functions as 42). By adopting such a configuration, it is possible to reduce the above-mentioned electric resistance and reduce power consumption. In order to form the electric circuit in these electrodes 31, 32 and the backplane 400 by the lithography technique, a flat base is required. This is because the presence of large irregularities on the base reduces the accuracy of pattern formation in the lithography process. In the present embodiment, since the front plane 200 and the intermediate layer 300 are flattened, the backplane 400 can be formed with high accuracy and high yield by using a lithography technique. Further, in the present embodiment, the plurality of first contact electrodes 31 each cover the p-GaN layer 21p of the plurality of μLED 220s and function as a light-shielding layer or a reflective layer. The individual first contact electrodes 31 do not have to completely cover the upper surface of the μLED 220, that is, the entire upper surface of the p-GaN layer 21p. The shape, size, and position of the first contact electrode 31 are determined to achieve a sufficiently low contact resistance and to sufficiently suppress the light emitted from the light emitting layer 23 from entering the channel region of the TFT 40. Will be done. It should be noted that preventing the light emitted from the light emitting layer 23 from entering the channel region of the TFT 40 can also be realized by arranging another metal layer at an appropriate position.
　本開示の実施形態によれば、素子分離領域２４０を金属プラグ２４および埋め込み絶縁物２５によって埋め込んで実現した平坦な上面を有するフロントプレーン２００上に、平坦化された上面を有する中間層３００を形成する。これらの構造（下部構造）は、その上にＴＦＴなどの回路要素を形成するベースとして機能する。ＴＦＴのための半導体を堆積するとき、あるいは、堆積後に熱処理をするとき、上記の下部構造は、例えば３５０℃以上の温度で処理される。このため、素子分離領域２４０内の埋め込み絶縁物２５および中間層３００に含まれる層間絶縁層３８は、３５０℃以上の熱処理によっても劣化しない材料から形成されることが好ましい。例えばポリイミドおよびＳＯＧ（Spin-on Glass）は、好適に用いられ得る。 According to the embodiment of the present disclosure, an intermediate layer 300 having a flat upper surface is formed on a front plane 200 having a flat upper surface realized by embedding the element separation region 240 with a metal plug 24 and an embedded insulator 25. To do. These structures (substructures) function as a base for forming circuit elements such as TFTs on the structures. When depositing a semiconductor for a TFT, or when heat-treating after deposition, the above-mentioned substructure is treated at a temperature of, for example, 350 ° C. or higher. Therefore, it is preferable that the embedded insulator 25 in the device separation region 240 and the interlayer insulating layer 38 contained in the intermediate layer 300 are formed of a material that does not deteriorate even by heat treatment at 350 ° C. or higher. For example, polyimide and SOG (Spin-on Glass) can be preferably used.
　バックプレーン４００における電気回路が含むＴＦＴの構成は、上記の例に限定されない。 The configuration of the TFT included in the electric circuit in the backplane 400 is not limited to the above example.
　図８は、ＴＦＴの他の例を模式的に示す断面図である。図９は、ＴＦＴの更に他の例を模式的に示す断面図である。 FIG. 8 is a cross-sectional view schematically showing another example of the TFT. FIG. 9 is a cross-sectional view schematically showing still another example of the TFT.
　図８の例において、ＴＦＴ４０は、平坦な層間絶縁層３８上に形成されたドレイン電極４１、ソース電極４２、およびゲート電極４５と、ゲート電極４５上に形成されたゲート絶縁膜４４と、ゲート絶縁膜４４上に形成され、ドレイン電極４１およびソース電極４２のそれぞれの上面の少なくとも一部に接触する半導体薄膜４３とを有している。図示されている例において、ドレイン電極４１およびソース電極４２は、それぞれ、真下に位置するビア電極３６によって第１コンタクト電極３１および第２コンタクト電極３２に接続されている。図８の構成によれば、ドレイン電極４１、ソース電極４２、およびゲート電極４５を同一の導電膜から形成することが可能になる。リソグラフィ技術によって金属膜を高い精度でパターニングするためには、下地が平坦であることが重要である。本実施形態では、選択成長によって形成されたμＬＥＤ２２０の間の空隙が、埋め込み絶縁物２５および／または金属プラグ２４によって満たされ、かつ、フロントプレーン２００の全体が平坦化されている。その結果、図８に示すように電極４１、４２、４５が狭い間隔を置いて並んだＴＦＴ４０を実現することが可能になる。ドレイン電極４１、ソース電極４２、およびゲート電極４５は、異なる導電材料から形成されていてもよい。ゲート電極４５と異なり、ドレイン電極４１およびソース電極４２は半導体薄膜４３に電気的に接触するため、ドレイン電極４１およびソース電極４２は、低コンタクト抵抗を実現するために適した材料または層構造を有していてもよい。 In the example of FIG. 8, the TFT 40 has a drain electrode 41, a source electrode 42, and a gate electrode 45 formed on a flat interlayer insulating layer 38, a gate insulating film 44 formed on the gate electrode 45, and gate insulation. It has a semiconductor thin film 43 formed on the film 44 and in contact with at least a part of the upper surface of each of the drain electrode 41 and the source electrode 42. In the illustrated example, the drain electrode 41 and the source electrode 42 are connected to the first contact electrode 31 and the second contact electrode 32 by a via electrode 36 located directly below, respectively. According to the configuration of FIG. 8, the drain electrode 41, the source electrode 42, and the gate electrode 45 can be formed from the same conductive film. In order to pattern a metal film with high accuracy by lithography technology, it is important that the substrate is flat. In this embodiment, the voids between the μLEDs 220 formed by selective growth are filled with the embedded insulator 25 and / or the metal plug 24, and the entire front plane 200 is flattened. As a result, as shown in FIG. 8, it becomes possible to realize a TFT 40 in which electrodes 41, 42, and 45 are arranged at a narrow interval. The drain electrode 41, the source electrode 42, and the gate electrode 45 may be formed of different conductive materials. Unlike the gate electrode 45, the drain electrode 41 and the source electrode 42 are in electrical contact with the semiconductor thin film 43, so that the drain electrode 41 and the source electrode 42 have a material or layer structure suitable for achieving low contact resistance. You may be doing it.
　図８のＴＦＴ４０では、ドレイン電極４１、ソース電極４２、およびゲート電極４５の全てが半導体薄膜４３の下方に位置している。このため、ＴＦＴ４０の下方に位置するフロントプレーン２００に電気的に接続しやすい。また、μＬＥＤ２２０または金属プラグ２４からドレイン電極４１またはソース電極４２までの距離を短縮しやすい。図８に示されるように、フロントプレーン２００の上面とドレイン電極４１またはソース電極４２との間には、単純な構成を有する層間絶縁層３８が存在している。層間絶縁層３８の厚さは、例えば３００ｎｍ以上１０００ｎｍ以下であり、ビア電極３６の高さをＴ、孔径（矩形の場合は、短辺の長さ）をＲとしたときに、アスペクト比（Ｔ／Ｒ）を例えば１／３以下にすることができる。一般に、アスペクト比が高いほど、ビア電極の形成歩留まりが低下してフロントプレーン２００とバックプレーン４００の電気的接続不良が発生しやすくなる。しかし、図８に示されるように、ドレイン電極４１、ソース電極４２、およびゲート電極４５を、平坦化された同一の下地層の上に形成し、それらの電極４１、４２、４５の上層に半導体薄膜４３を配置する構成によれば、アスペクト比を低くできるため、フロントプレーン２００内でμＬＥＤ２２０が多様なパターンで配列されている場合でも、フロントプレーン２００とバックプレーン４００との電気的接続が容易になる。 In the TFT 40 of FIG. 8, the drain electrode 41, the source electrode 42, and the gate electrode 45 are all located below the semiconductor thin film 43. Therefore, it is easy to electrically connect to the front plane 200 located below the TFT 40. Further, it is easy to shorten the distance from the μLED 220 or the metal plug 24 to the drain electrode 41 or the source electrode 42. As shown in FIG. 8, an interlayer insulating layer 38 having a simple structure is present between the upper surface of the front plane 200 and the drain electrode 41 or the source electrode 42. The thickness of the interlayer insulating layer 38 is, for example, 300 nm or more and 1000 nm or less, and when the height of the via electrode 36 is T and the pore diameter (in the case of a rectangle, the length of the short side) is R, the aspect ratio (T). / R) can be, for example, 1/3 or less. In general, the higher the aspect ratio, the lower the yield of forming via electrodes, and the more likely it is that poor electrical connection between the front plane 200 and the back plane 400 will occur. However, as shown in FIG. 8, the drain electrode 41, the source electrode 42, and the gate electrode 45 are formed on the same flattened base layer, and a semiconductor is formed on the upper layers of the electrodes 41, 42, and 45. According to the configuration in which the thin film 43 is arranged, the aspect ratio can be lowered, so that even when the μLED 220s are arranged in various patterns in the front plane 200, the electrical connection between the front plane 200 and the back plane 400 can be easily performed. Become.
　図９の例において、ＴＦＴ４０は、層間絶縁層３８上に形成された半導体薄膜４３と、層間絶縁層３８上に形成され、それぞれが半導体薄膜４３の一部に接触するドレイン電極４１およびソース電極４２と、半導体薄膜４３上に形成されたゲート絶縁膜４４と、ゲート絶縁膜４４上に形成されたゲート電極４５とを有している。図示されている例において、ドレイン電極４１およびソース電極４２は、それぞれ、ビア電極３６によって第１コンタクト電極３１および第２コンタクト電極３２に接続されている。図９の構成によれば、半導体薄膜４３がドレイン電極４１、ソース電極４２、およびゲート電極４５の下方に位置しているため、これらの電極４１、４２、４５を形成する前において、半導体薄膜４３をレーザでアニールして結晶品質を高めることが可能である。このため、レーザアニールによる温度上昇を考慮することなく、融点の低い電極材料を選択することが可能になる。具体的には、一部にアルミニウム層を含む多層構造の電極を採用することが可能になる。 In the example of FIG. 9, the TFT 40 has a semiconductor thin film 43 formed on the interlayer insulating layer 38, and a drain electrode 41 and a source electrode 42 formed on the interlayer insulating layer 38 and in contact with a part of the semiconductor thin film 43, respectively. And a gate insulating film 44 formed on the semiconductor thin film 43, and a gate electrode 45 formed on the gate insulating film 44. In the illustrated example, the drain electrode 41 and the source electrode 42 are connected to the first contact electrode 31 and the second contact electrode 32 by the via electrode 36, respectively. According to the configuration of FIG. 9, since the semiconductor thin film 43 is located below the drain electrode 41, the source electrode 42, and the gate electrode 45, the semiconductor thin film 43 is formed before the electrodes 41, 42, and 45 are formed. Can be annealed with a laser to improve crystal quality. Therefore, it is possible to select an electrode material having a low melting point without considering the temperature rise due to laser annealing. Specifically, it becomes possible to adopt an electrode having a multi-layer structure including an aluminum layer in part.
　また、図９の例では、平坦化された層間絶縁層３８上にＴＦＴ４０のチャネルとなる半導体薄膜４３が形成されるため、製造時に半導体層を成長させる工程において、下地段差に起因して膜質または膜厚が不均一しにくい。その結果、レーザアニールによって多結晶化した場合、キャリア移動度の高い、結晶性に優れた半導体薄膜４３を形成しやすい。さらに、ゲート電極４５が半導体薄膜４３の上方に位置するため、ゲート電極４５をイオン注入のマスクとして利用することにより、ＬＤＤ（Lightly Drain Dope）構造を自己整合的に形成することができる。 Further, in the example of FIG. 9, since the semiconductor thin film 43 serving as the channel of the TFT 40 is formed on the flattened interlayer insulating layer 38, the film quality or the film quality due to the underlying step is formed in the step of growing the semiconductor layer during manufacturing. The film thickness is unlikely to be non-uniform. As a result, when polycrystallized by laser annealing, it is easy to form a semiconductor thin film 43 having high carrier mobility and excellent crystallinity. Further, since the gate electrode 45 is located above the semiconductor thin film 43, the LDD (Lightly Drain Dope) structure can be self-consistently formed by using the gate electrode 45 as a mask for ion implantation.
　半導体薄膜４３は、中間層３００に設けられたコンタクトホール３９およびビア電極３６に対して部分的にオーバーラップしている。半導体薄膜４３の上面および下面の両方が電極とコンタクトしている。より具体的には、半導体薄膜４３のドレイン領域は、上層のドレイン電極４１と下層のビア電極３６とによって挟まれている。半導体薄膜４３のソート領域は、上層のソース電極４２と下層のビア電極３６とによって上下から挟まれている。この結果、電極のコンタクト抵抗が低下し、ＴＦＴ特性が向上する。なお、半導体薄膜４３のドレイン領域およびソース領域の両方が、下層のビア電極３６に接触している必要はなく、ドレイン領域およびソース領域の一方が下層のビア電極３６に接触していてもよい。 The semiconductor thin film 43 partially overlaps the contact hole 39 and the via electrode 36 provided in the intermediate layer 300. Both the upper surface and the lower surface of the semiconductor thin film 43 are in contact with the electrodes. More specifically, the drain region of the semiconductor thin film 43 is sandwiched between the drain electrode 41 in the upper layer and the via electrode 36 in the lower layer. The sort region of the semiconductor thin film 43 is sandwiched from above and below by the source electrode 42 in the upper layer and the via electrode 36 in the lower layer. As a result, the contact resistance of the electrode is reduced and the TFT characteristics are improved. It is not necessary that both the drain region and the source region of the semiconductor thin film 43 are in contact with the via electrode 36 of the lower layer, and one of the drain region and the source region may be in contact with the via electrode 36 of the lower layer.
　ＴＦＴ４０の構成は、上記の例に限定されないが、バックプレーン４００の下層に形成されたμＬＥＤ２２０と適切にコンタクトできるように、上記本実施形態の例で示した構成が好ましい。本開示の実施形態では、ＴＦＴ４０を形成する工程の初期段階において、中間層３００における層間絶縁層３８のコンタクトホール３９を介してフロントプレーン２００の第１および第２コンタクト電極３１、３２に接続される複数の金属層が形成される。これらの金属層は、ＴＦＴ４０のドレイン電極４１またはソース電極４２であり得るが、それらに限定されない。 The configuration of the TFT 40 is not limited to the above example, but the configuration shown in the above example of the present embodiment is preferable so that the μLED 220 formed in the lower layer of the backplane 400 can be appropriately contacted. In the embodiment of the present disclosure, in the initial stage of the process of forming the TFT 40, it is connected to the first and second contact electrodes 31 and 32 of the front plane 200 via the contact hole 39 of the interlayer insulating layer 38 in the intermediate layer 300. Multiple metal layers are formed. These metal layers can be, but are not limited to, the drain electrode 41 or the source electrode 42 of the TFT 40.
　本実施形態におけるドレイン電極４１およびソース電極４２は、平坦化された中間層３００における層間絶縁層３８上に金属層を堆積した後、フォトリソグラフィおよびエッチング工程でパターニングされる。このため、フロントプレーン２００（中間層３００）とバックプレーン４００との間で、歩留まり低下を招くような位置合わせずれは生じない。 The drain electrode 41 and the source electrode 42 in this embodiment are patterned by a photolithography and etching process after depositing a metal layer on the interlayer insulating layer 38 in the flattened intermediate layer 300. Therefore, there is no misalignment between the front plane 200 (intermediate layer 300) and the back plane 400 that causes a decrease in yield.
　本開示の実施形態では、広い範囲にわたって多数のμＬＥＤ２２０が配列され、少なくとも１個の金属プラグ２４によってμＬＥＤ２２０のｎ－ＧａＮ層２２ｎがバックプレーン４００の電気回路に接続される。このため、ｎ－ＧａＮ層２２ｎから金属プラグ２４に流れる電流に対する電気抵抗成分（シート抵抗）が高すぎると、消費電力の増加を招いてしまう。 In the embodiments of the present disclosure, a large number of μLED 220s are arranged over a wide range, and at least one metal plug 24 connects the n-GaN layer 22n of the μLED 220 to the electric circuit of the backplane 400. Therefore, if the electric resistance component (sheet resistance) with respect to the current flowing from the n-GaN layer 22n to the metal plug 24 is too high, the power consumption will increase.
　本実施形態では、適切な熱処理工程により、１枚の連続したマスク層１５０が全てのμＬＥＤ２２０におけるｎ－ＧａＮ層２２ｎに電気的に接続しているため、金属プラグ２４と個々のμＬＥＤ２２０のｎ－ＧａＮ層２２ｎとの電気的導通が確保される。この例において、マスク層１５０は、複数のμＬＥＤ２２０のｎ側共通電極として機能する。本開示の実施形態では、複数のμＬＥＤ２２０における第２導電側の電極が導電性を有するマスク層１５０によって共通化されているため、断線に起因して一部のμＬＥＤ２２０に導通不良が生じるという問題が回避される。 In the present embodiment, since one continuous mask layer 150 is electrically connected to the n-GaN layer 22n in all μLED 220s by an appropriate heat treatment step, the metal plug 24 and the n-GaN of each μLED 220 are n-GaN. Electrical continuity with the layer 22n is ensured. In this example, the mask layer 150 functions as an n-side common electrode of the plurality of μLED 220s. In the embodiment of the present disclosure, since the electrodes on the second conductive side of the plurality of μLED 220s are shared by the mask layer 150 having conductivity, there is a problem that some μLED 220s have poor continuity due to disconnection. Avoided.
　トレンチは、埋め込み絶縁物２５によって埋められる。具体的には、例えば熱硬化性のポリイミドなどの樹脂材料を塗布した後、例えば４００℃で６０分間の熱処理によって樹脂材料を硬化させることにより、埋め込み絶縁物２５を形成できる。埋め込み絶縁物２５は、樹脂から形成されている必要はなく、例えばシリコン窒化物、シリコン酸化物などの無機絶縁材料から形成されていてもよい。 The trench is filled with the embedded insulator 25. Specifically, the embedded insulator 25 can be formed by applying a resin material such as thermosetting polyimide and then curing the resin material by heat treatment at 400 ° C. for 60 minutes, for example. The embedded insulator 25 does not have to be formed of a resin, and may be formed of an inorganic insulating material such as silicon nitride or silicon oxide.
　本開示の実施形態では、バックプレーン４００に含まれるＴＦＴおよびその他の構成要素を半導体製造技術によってフロントプレーン２００および中間層３００の上層に形成するため、これらの構成要素を形成するためのプロセス温度に耐える材料を用いてフロントプレーン２００および中間層３００を形成する必要がある。例えば、埋め込み絶縁物２５、層間絶縁層３８、絶縁層４６は、有機材料から形成され得るが、この有機材料はバックプレーン４００を形成するプロセスの最高温度に耐える必要がある。具体的には、ＴＦＴを形成する工程で例えば３００℃を超えるような熱処理が行われる場合、３００℃の熱処理でも劣化しにくい耐熱性のある樹脂材料（たとえばポリイミド）から、埋め込み絶縁物２５、層間絶縁層３８、および／または絶縁層４６を形成することができる。 In the embodiments of the present disclosure, the TFTs and other components contained in the backplane 400 are formed on the upper layers of the front plane 200 and the intermediate layer 300 by semiconductor manufacturing technology, so that the process temperature for forming these components is set. It is necessary to form the front plane 200 and the intermediate layer 300 using a material that can withstand. For example, the embedded insulator 25, the interlayer insulating layer 38, and the insulating layer 46 can be formed from an organic material, which must withstand the maximum temperature of the process of forming the backplane 400. Specifically, when a heat treatment exceeding 300 ° C. is performed in the process of forming the TFT, from a heat-resistant resin material (for example, polyimide) that is not easily deteriorated even by the heat treatment at 300 ° C., the embedded insulator 25 and the layers The insulating layer 38 and / or the insulating layer 46 can be formed.
　埋め込み絶縁物２５、層間絶縁層３８および絶縁層４６は、それぞれ、単層構造を有している必要はなく、多層構造を有していてもよい。多層構造は、例えば有機材料と無機材料の積層物（stack）を含み得る。 The embedded insulator 25, the interlayer insulating layer 38, and the insulating layer 46 do not necessarily have a single-layer structure, and may have a multi-layer structure. The multilayer structure may include, for example, a stack of organic and inorganic materials.
　上記の例における金属プラグ２４の上面は、各μＬＥＤ２２０の上面とほぼ同じレベルにあるため、その上に半導体製造技術によってＴＦＴ４０などの回路要素および微細な配線を高い精度で形成することが可能になる。 Since the upper surface of the metal plug 24 in the above example is at almost the same level as the upper surface of each μLED 220, it is possible to form circuit elements such as TFT 40 and fine wiring on it with high accuracy by semiconductor manufacturing technology. ..
　上記の例では、スルーホール２６を埋める金属プラグ２４が用いられているが、前述したように、金属プラグ２４の形態はさまざまであり得る。 In the above example, the metal plug 24 that fills the through hole 26 is used, but as described above, the form of the metal plug 24 can be various.
　＜改変例＞
　図１０は、改変例におけるμＬＥＤデバイス１１００の一部を示す断面図である。図１０のμＬＥＤデバイス１１００が、図１ＡのμＬＥＤデバイス１０００から異なっている点は、マスク層１５０上に絶縁層１６０が設けられていることにある。絶縁層１６０は、金属プラグ２４とマスク層１５０の接続部１５０Ｃとの接触を可能にする開口部１６０Ｇを有している。また、絶縁層１６０は、マスク層１５０の上面のうち、マスク開口部１５０Ｇの周辺領域は覆っていない。このため、第２半導体層２２が横方向に成長した部分とマスク層１５０の上面との接触が実現している。したがって、エピタキシャル成長中の加熱、またはエピタキシャル成長後に適切な熱処理を行うことにより、第２半導体層２２とマスク層１５０の表面との間にも良好なオーミック接触が実現される。 <Modification example>
FIG. 10 is a cross-sectional view showing a part of the μLED device 1100 in the modified example. The difference between the μLED device 1100 of FIG. 10 and the μLED device 1000 of FIG. 1A is that the insulating layer 160 is provided on the mask layer 150. The insulating layer 160 has an opening 160G that enables contact between the metal plug 24 and the connecting portion 150C of the mask layer 150. Further, the insulating layer 160 does not cover the peripheral region of the mask opening 150G on the upper surface of the mask layer 150. Therefore, the portion where the second semiconductor layer 22 grows in the lateral direction and the upper surface of the mask layer 150 are brought into contact with each other. Therefore, good ohmic contact is also realized between the second semiconductor layer 22 and the surface of the mask layer 150 by heating during epitaxial growth or by performing appropriate heat treatment after epitaxial growth.
　絶縁層１６０は、第２半導体層２２の成長前に堆積されてもよいし、第２半導体層２２の成長後において発光層２３の成長前に堆積されてもよい。絶縁層１６０に開口部１６０Ｇを形成する工程は、例えば、埋め込み絶縁物２５にスルーホール２６を形成する工程の後に実行され得る。 The insulating layer 160 may be deposited before the growth of the second semiconductor layer 22, or may be deposited after the growth of the second semiconductor layer 22 and before the growth of the light emitting layer 23. The step of forming the opening 160G in the insulating layer 160 can be performed, for example, after the step of forming the through holes 26 in the embedded insulator 25.
　絶縁層１６０は、マスク層１５０が発光層２３および第１半導体層２１に接触することを防止する。このため、この改変例では、マスク層１５０は、第１半導体層２１との間でオーミック接触などの何らかの電気的導通を実現し得る金属材料から形成されていてもよい。 The insulating layer 160 prevents the mask layer 150 from coming into contact with the light emitting layer 23 and the first semiconductor layer 21. Therefore, in this modification, the mask layer 150 may be formed of a metal material capable of realizing some kind of electrical conduction such as ohmic contact with the first semiconductor layer 21.
　図１０の例において、第２半導体層２２の横方向に成長した部分は、マスク層１５０上の絶縁層１６０のエッジまで達している。第２半導体層２２は、絶縁層１６０の一部にオーバーラップしていてもよい。また、マスク層１５０が発光層２３に対して高い電気抵抗性を示す材料から形成されている場合、第２半導体層２２は、絶縁層１６０のエッジに達している必要はない。その場合、マスク層１５０のうち絶縁層１６０によって覆われていない部分が発光層２３および／または第１半導体層２１と接触し得る。マスク層１５０と発光層２３および第１半導体層２１との間の電気的絶縁を確保するためには、絶縁層１６０がマスク層１５０と発光層２３および第１半導体層２１との間の存在することが好ましい。製造工程中に発生し得るマスクアライメントのずれを考慮すると、第２半導体層２２の横方向に成長した部分は、マスク層１５０上の絶縁層１６０のエッジを乗り越え、絶縁層１６０に部分的にオーバーラップしていることが望ましい。絶縁層１６０は、発光層２３および第１半導体層２１の成長温度で劣化しない材料、例えば、シリコン酸化物、またはシリコン窒化物などから形成され得る。 In the example of FIG. 10, the laterally grown portion of the second semiconductor layer 22 reaches the edge of the insulating layer 160 on the mask layer 150. The second semiconductor layer 22 may overlap a part of the insulating layer 160. Further, when the mask layer 150 is formed of a material exhibiting high electrical resistance to the light emitting layer 23, the second semiconductor layer 22 does not need to reach the edge of the insulating layer 160. In that case, the portion of the mask layer 150 that is not covered by the insulating layer 160 may come into contact with the light emitting layer 23 and / or the first semiconductor layer 21. In order to ensure electrical insulation between the mask layer 150 and the light emitting layer 23 and the first semiconductor layer 21, an insulating layer 160 exists between the mask layer 150 and the light emitting layer 23 and the first semiconductor layer 21. Is preferable. Considering the mask alignment deviation that may occur during the manufacturing process, the laterally grown portion of the second semiconductor layer 22 overcomes the edge of the insulating layer 160 on the mask layer 150 and partially over the insulating layer 160. It is desirable to wrap it. The insulating layer 160 may be formed of a material that does not deteriorate at the growth temperature of the light emitting layer 23 and the first semiconductor layer 21, such as silicon oxide or silicon nitride.
　以下、本開示のμＬＥＤデバイスによるカラーディスプレイの実施形態を説明する。 Hereinafter, embodiments of a color display using the μLED device of the present disclosure will be described.
　＜カラーディスプレイI＞
　以下、図１１を参照しながら、本開示の実施形態におけるフルカラー表示が可能なμＬＥＤデバイス１０００Ｂの構成例を説明する。図１１では、Ｚ軸の方向が図１ＡにおけるＺ軸の方向から反転している。前述したμＬＥＤデバイス１０００Ａにおける構成要素に対応する構成要素に同一の参照符号を与え、それらの構成要素の説明はここでは繰り返さない。 <Color display I>
Hereinafter, a configuration example of the μLED device 1000B capable of full-color display according to the embodiment of the present disclosure will be described with reference to FIG. In FIG. 11, the direction of the Z axis is reversed from the direction of the Z axis in FIG. 1A. The same reference numerals are given to the components corresponding to the components in the μLED device 1000A described above, and the description of these components will not be repeated here.
　本実施形態におけるμＬＥＤデバイス１０００Ｂは、基板１００、フロントプレーン２００、中間層３００およびバックプレーン４００を備えている。これらの要素は、前述した様々な構成を備え得る。 The μLED device 1000B in the present embodiment includes a substrate 100, a front plane 200, an intermediate layer 300, and a back plane 400. These elements may have the various configurations described above.
　図１１に示されるμＬＥＤデバイス１０００Ｂは、複数のμＬＥＤ２２０のそれぞれから放射された光を白色光に変換する蛍光体層６００と、白色光の各色成分を選択的に透過するカラーフィルタアレイ６２０とを更に備えている。カラーフィルタアレイ６２０は、蛍光体層６００を間に挟んで基板１００に支持されており、レッドフィルタ６２Ｒ、グリーンフィルタ６２Ｇ、およびブルーフィルタ６２Ｂを有している。 The μLED device 1000B shown in FIG. 11 further includes a phosphor layer 600 that converts light emitted from each of the plurality of μLED 220s into white light, and a color filter array 620 that selectively transmits each color component of white light. I have. The color filter array 620 is supported by the substrate 100 with the phosphor layer 600 interposed therebetween, and has a red filter 62R, a green filter 62G, and a blue filter 62B.
　本実施形態では、μＬＥＤ２２０の発光層２３から放射された光が青の波長（４３５～４８５ｎｍ）を有するように、発光層２３の組成およびバンドギャップが調整されている。 In the present embodiment, the composition and bandgap of the light emitting layer 23 are adjusted so that the light emitted from the light emitting layer 23 of the μLED 220 has a blue wavelength (435 to 485 nm).
　蛍光体層６００の例は、「量子ドット」と呼ばれる多数のナノ粒子（量子ドット蛍光体）を含有するシートであり得る。量子ドット蛍光体は、例えばＣｄＴｅ、ＩｎＰ、ＧａＮなどの半導体から形成され得る。量子ドット蛍光体は、そのサイズに応じて発する光の波長が変化する。励起光を受けて赤および緑の光を発するように調整された量子ドット分散シートを蛍光体層６００として利用することができる。このような蛍光体層６００を励起する光として青の光を用いると、蛍光体層６００を透過する青の光と、蛍光体層６００の量子ドットで赤または緑に変換された光とが混合して形成された白色光が蛍光体層６００から出射され得る。 An example of the phosphor layer 600 may be a sheet containing a large number of nanoparticles (quantum dot phosphors) called "quantum dots". The quantum dot phosphor can be formed from a semiconductor such as CdTe, InP, or GaN. The wavelength of light emitted from a quantum dot phosphor changes according to its size. A quantum dot dispersion sheet adjusted to receive excitation light and emit red and green light can be used as the phosphor layer 600. When blue light is used as the light for exciting the phosphor layer 600, the blue light transmitted through the phosphor layer 600 and the light converted into red or green by the quantum dots of the phosphor layer 600 are mixed. The white light thus formed can be emitted from the phosphor layer 600.
　量子ドット蛍光体の粒径は、例えば２ｎｍ以上３０ｎｍ以下である。粒径が１０μｍを超えている一般的な蛍光体粉末粒子に比べると、量子ドット蛍光体の粒径は著しく小さい。μＬＥＤ２２０が例えば５～１０μｍ程度の狭ピッチで配列されているとき、粒径が１０μｍを超える蛍光体粉末粒子では、μＬＥＤ２２０の配列ピッチに対して蛍光体が大き過ぎるため、効率的な波長変換が難しくなる。また、通常の蛍光体粉末粒子を粉砕して粒径を１μｍよりも小さくすると、蛍光体としての性能が著しく低下することが知られている。 The particle size of the quantum dot phosphor is, for example, 2 nm or more and 30 nm or less. The particle size of the quantum dot phosphor is significantly smaller than that of general phosphor powder particles having a particle size of more than 10 μm. When μLED220s are arranged at a narrow pitch of, for example, about 5 to 10 μm, it is difficult to perform efficient wavelength conversion for phosphor powder particles having a particle size of more than 10 μm because the phosphors are too large for the arrangement pitch of μLED220. Become. Further, it is known that when ordinary phosphor powder particles are pulverized to make the particle size smaller than 1 μm, the performance as a phosphor is remarkably deteriorated.
　蛍光体層６００は、主として青の光（励起光）をレイリー散乱させるようなサイズを有する散乱体を含んでいてもよい。レイリー散乱は、光の波長よりも小さな粒子によって引き起こされ、その散乱の程度は波長の４乗に反比例する。そのため、短い波長の光ほど多く散乱される。青の光を選択的に散乱させる散乱体としては、１０ｎｍ以上５０ｎｍ以下の直径（典型的には３０ｎｍ以下）を有する酸化チタン（ＴｉＯ2）超微粒子が好適に用いられ得る。特に、ルチル型結晶のＴｉＯ2超微粒子は、物理的化学的に安定であるため好ましい。このようなＴｉＯ2超微粒子は、青の波長よりも長い波長の色（緑および赤）の光を散乱させる効果は低い。 The phosphor layer 600 may include a scatterer having a size that mainly causes Rayleigh scattering of blue light (excitation light). Rayleigh scattering is caused by particles smaller than the wavelength of light, and the degree of scattering is inversely proportional to the fourth power of the wavelength. Therefore, the shorter the wavelength of light, the more it is scattered. As a scatterer that selectively scatters blue light, titanium oxide (TiO 2 ) ultrafine particles having a diameter of 10 nm or more and 50 nm or less (typically 30 nm or less) can be preferably used. In particular, TiO 2 ultrafine particles of rutile-type crystals are preferable because they are physically and chemically stable. Such TiO 2 ultrafine particles have a low effect of scattering light of colors (green and red) having a wavelength longer than that of blue.
　ＴｉＯ2超微粒子を蛍光体層６００内で均一に分散させるには、アルカノールアミン、ポリオール、シロキサン、カルボン酸（例えばステアリン酸またはラウリン酸）などの有機物を用いた表面処理を行うことが好ましい。また、Ａｌ（ＯＨ）3またはＳｉＯ2などの無機物を用いて表面処理を行ってもよい。 In order to uniformly disperse the TiO 2 ultrafine particles in the phosphor layer 600, it is preferable to perform a surface treatment using an organic substance such as an alkanolamine, a polyol, a siloxane, or a carboxylic acid (for example, stearic acid or lauric acid). Further, the surface treatment may be performed using an inorganic substance such as Al (OH) 3 or SiO 2 .
　青散乱体としては、酸化チタン微粒子に代えて、あるいは酸化チタン微粒子とともに酸化亜鉛微粒子（粒子径：例えば２０ｎｍ以上１００ｎｍ以下）を用いても良い。このような青散乱体が均一に分散されていることにより、方向に依存した色むらが生じにくくなり、視野角特性に優れた表示が実現する。 As the blue scatterer, zinc oxide fine particles (particle diameter: for example, 20 nm or more and 100 nm or less) may be used instead of the titanium oxide fine particles or together with the titanium oxide fine particles. Since such blue scatterers are uniformly dispersed, color unevenness depending on the direction is less likely to occur, and a display having excellent viewing angle characteristics is realized.
　上述の説明から明らかなように、本実施形態のμＬＥＤデバイス１０００Ｂは、μＬＥＤ２２０の発光層２３から放射された光を透過させる必要がある。基板１００がサファイア基板であれば、可視光および紫外線の広い範囲で高い透光性が発揮される。 As is clear from the above description, the μLED device 1000B of the present embodiment needs to transmit the light emitted from the light emitting layer 23 of the μLED 220. If the substrate 100 is a sapphire substrate, high translucency is exhibited in a wide range of visible light and ultraviolet rays.
　カラーフィルタアレイ６２０におけるレッドフィルタ６２Ｒ、グリーンフィルタ６２Ｇ、およびブルーフィルタ６２Ｂは、それぞれ、μＬＥＤ２２０に対向する位置に配置される。レッドフィルタ６２Ｒ、グリーンフィルタ６２Ｇ、およびブルーフィルタ６２Ｂは、それぞれ、対応するμＬＥＤ２２０から放射された光によって励起された蛍光体層６００から白色光を受け、その白色光に含まれる赤成分、緑成分、および青成分を透過する。 The red filter 62R, the green filter 62G, and the blue filter 62B in the color filter array 620 are arranged at positions facing the μLED 220, respectively. The red filter 62R, the green filter 62G, and the blue filter 62B receive white light from the phosphor layer 600 excited by the light emitted from the corresponding μLED 220, and the red component and the green component contained in the white light, respectively. And the blue component is transmitted.
　各μＬＥＤ２２０から放射された光を、対応するレッドフィルタ６２Ｒ、グリーンフィルタ６２Ｇ、およびブルーフィルタ６２Ｂのいずれかに効率的に入射させるためには、金属プラグ２４が個々の各μＬＥＤデバイス１０００Ｂを取り囲む形状を有していることが望ましい。 In order for the light emitted from each μLED 220 to be efficiently incident on any of the corresponding red filter 62R, green filter 62G, and blue filter 62B, the metal plug 24 should be shaped to surround each individual μLED device 1000B. It is desirable to have.
　カラーフィルタアレイ６２０において、レッドフィルタ６２Ｒ、グリーンフィルタ６２Ｇ、およびブルーフィルタ６２Ｂの間は、遮光性または吸光性を有する材料から形成されたブラックマトリックスとして機能する部分が位置していることが好ましい。 In the color filter array 620, it is preferable that a portion that functions as a black matrix formed of a light-shielding or absorbent material is located between the red filter 62R, the green filter 62G, and the blue filter 62B.
　蛍光体層６００は、カラーフィルタアレイ６２０に積層された（stacked）蛍光体シートであってもよい。 The phosphor layer 600 may be a stacked phosphor sheet on the color filter array 620.
　蛍光体層６００は、量子ドット蛍光体が分散されたシートである必要はない。量子ドット蛍光体（蛍光体粉末）を樹脂に分散して基板１００の下面１００Ｂに塗布・硬化することにより、蛍光体層６００を形成してもよい。この場合、蛍光体粉末は基板１００の下面１００Ｂ上に位置している。 The phosphor layer 600 does not have to be a sheet in which quantum dot phosphors are dispersed. The phosphor layer 600 may be formed by dispersing the quantum dot phosphor (fluorescent powder) in a resin, applying and curing the lower surface 100B of the substrate 100. In this case, the phosphor powder is located on the lower surface 100B of the substrate 100.
　蛍光体層６００およびカラーフィルタアレイ６２０以外の光学シート、保護シート、またはタッチセンサなどが基板１００に取り付けられていてもよい。このことは、後述する他の実施形態でも同様である。 An optical sheet, a protective sheet, a touch sensor, or the like other than the phosphor layer 600 and the color filter array 620 may be attached to the substrate 100. This also applies to other embodiments described later.
　＜カラーディスプレイII＞
　以下、図１２Ａおよび図１２Ｂを参照しながら、本開示の実施形態におけるフルカラー表示が可能なμＬＥＤデバイス１０００Ｃの構成例を説明する。図１２Ａでは、Ｚ軸の方向が図１ＡにおけるＺ軸の方向から反転している。図１２Ｂは、μＬＥＤデバイス１０００Ｃの斜視図である。 <Color Display II>
Hereinafter, a configuration example of the μLED device 1000C capable of full-color display according to the embodiment of the present disclosure will be described with reference to FIGS. 12A and 12B. In FIG. 12A, the direction of the Z axis is reversed from the direction of the Z axis in FIG. 1A. FIG. 12B is a perspective view of the μLED device 1000C.
　本実施形態におけるμＬＥＤデバイス１０００Ｃは、基板１００、フロントプレーン２００、中間層３００およびバックプレーン４００を備えている。これらの要素は、前述した様々な構成を備え得る。 The μLED device 1000C in the present embodiment includes a substrate 100, a front plane 200, an intermediate layer 300, and a back plane 400. These elements may have the various configurations described above.
　図示されているμＬＥＤデバイス１０００Ｃは、基板１００に支持され、複数のμＬＥＤから放射された光がそれぞれ入射する複数の画素開口部６４５を規定するバンク層（厚さ：０．５～３．０μｍ）６４０を備えている。また、μＬＥＤデバイス１０００Ｃは、バンク層６４０の複数の画素開口部６４５にそれぞれ配置された赤蛍光体６４Ｒ、緑蛍光体６４Ｇ、および青散乱体６４Ｂを備えている。赤蛍光体６４Ｒは、μＬＥＤ２２０から放射された青の光を赤の光に変換し、緑蛍光体６４Ｇは、μＬＥＤ２２０から放射された青の光を緑の光に変換する。青散乱体６４Ｂは、μＬＥＤ２２０から放射された青の光を散乱する。青散乱体６４Ｂは、赤蛍光体６４Ｒまたは緑蛍光体６４Ｇから発せられた光の強度が示す放射角依存性（例えばランバーシアン分布）に似た放射角依存性を持つように設計され得る。 The illustrated μLED device 1000C is a bank layer (thickness: 0.5 to 3.0 μm) that is supported by the substrate 100 and defines a plurality of pixel openings 645 in which light emitted from the plurality of μLEDs is incident. It has 640. Further, the μLED device 1000C includes a red phosphor 64R, a green phosphor 64G, and a blue scatterer 64B respectively arranged in a plurality of pixel openings 645 of the bank layer 640. The red phosphor 64R converts the blue light emitted from the μLED 220 into red light, and the green phosphor 64G converts the blue light emitted from the μLED 220 into green light. The blue scatterer 64B scatters the blue light emitted from the μLED 220. The blue scatterer 64B can be designed to have a radiation angle dependence similar to the radiation angle dependence (eg, Lambersian distribution) exhibited by the intensity of light emitted from the red phosphor 64R or the green phosphor 64G.
　本実施形態では、μＬＥＤ２２０の発光層２３から放射された光が青の波長（４３５～４８５ｎｍ）を有するように、発光層２３の組成およびバンドギャップが調整されている。 In the present embodiment, the composition and bandgap of the light emitting layer 23 are adjusted so that the light emitted from the light emitting layer 23 of the μLED 220 has a blue wavelength (435 to 485 nm).
　図１２Ａに示されている例において、μＬＥＤデバイス１０００Ｃは、バンク層６４０における画素開口部６４５を覆う透明保護層６５０を備えている。簡単のため、図１２Ｂでは、透明保護層６５０の記載は省略されている。透明保護層６５０は、赤蛍光体６４Ｒおよび緑蛍光体６４Ｇが吸湿によって劣化しやすい場合、大気中の水分がこれらの蛍光体に悪影響を与えないように封止機能を発揮することが望ましい。透明保護層６５０は、有機層および無機層の積層体であってもよい。 In the example shown in FIG. 12A, the μLED device 1000C includes a transparent protective layer 650 that covers the pixel openings 645 in the bank layer 640. For simplicity, the description of the transparent protective layer 650 is omitted in FIG. 12B. When the red phosphor 64R and the green phosphor 64G are easily deteriorated by moisture absorption, it is desirable that the transparent protective layer 650 exerts a sealing function so that moisture in the atmosphere does not adversely affect these phosphors. The transparent protective layer 650 may be a laminate of an organic layer and an inorganic layer.
　バンク層６４０は、例えば格子形状を有しており、黒色染料が溶解した遮光材料、または、カーボンブラックのような黒色顔料が分散された遮光材料から形成され得る。バンク層６４０は、感光性材料、アクリル、ポリイミドなどの樹脂材料、低融点ガラスを含むペースト材料、ゾルゲル材料（例えばＳＯＧ）などから形成され得る。バンク層６４０を感光性材料から形成するときは、基板１００の下面１００Ｂに感光性材料を塗布した後、リソグラフィ工程で露光・現像によるパターニングを行うことにより、所定位置に画素開口部６４５を形成すればよい。画素開口部６４５の位置および大きさは、μＬＥＤ２２０の配置に整合するように決定される。画素開口部６４５のサイズは、例えば１０μｍ×１０μｍ以下であり得る。このとき、画素開口部６４５内に配置される赤蛍光体６４Ｒ、緑蛍光体６４Ｇ、および青散乱体６４Ｂの粒径は、１μｍ以下であることが望ましく、画素開口部６４５内に均一かつ緻密に配置することを考慮すると、１００ｎｍ以下であることがさらに望ましい。そのため、赤蛍光体６４Ｒおよび緑蛍光体６４Ｇは、それぞれ、量子ドット蛍光体から好適に形成され得る。青散乱体６４Ｂは、粒径が１０ｎｍ以上６０ｎｍ以下の透明な粉末粒子から形成され得る。 The bank layer 640 has, for example, a lattice shape, and can be formed from a light-shielding material in which a black dye is dissolved or a light-shielding material in which a black pigment such as carbon black is dispersed. The bank layer 640 can be formed of a photosensitive material, a resin material such as acrylic or polyimide, a paste material containing low melting point glass, a sol-gel material (for example, SOG), or the like. When the bank layer 640 is formed from a photosensitive material, the pixel opening 645 is formed at a predetermined position by applying the photosensitive material to the lower surface 100B of the substrate 100 and then performing patterning by exposure and development in a lithography process. Just do it. The position and size of the pixel openings 645 are determined to match the placement of the μLED 220. The size of the pixel opening 645 can be, for example, 10 μm × 10 μm or less. At this time, the particle sizes of the red phosphor 64R, the green phosphor 64G, and the blue scatterer 64B arranged in the pixel opening 645 are preferably 1 μm or less, and are uniformly and densely arranged in the pixel opening 645. Considering the arrangement, it is more desirable to be 100 nm or less. Therefore, the red phosphor 64R and the green phosphor 64G can each be suitably formed from the quantum dot phosphor. The blue scatterer 64B can be formed from transparent powder particles having a particle size of 10 nm or more and 60 nm or less.
　青散乱体６４Ｂは、μＬＥＤ２２０から放射される青の光の波長（例えば約４５０ｎｍ）の１０％程度の粒径を持つ粒子を、その屈折率（ｎ）よりも充分に低い屈折率を有するマトリックス材料に分散させることによって形成され得る。このようにして形成された青散乱体６４Ｂは、青の光にレイリー散乱を生じさせることができる。青散乱体６４Ｂを構成する粉末粒子は、例えば酸化チタン（ｎ＝２．５～２．７）、酸化クロム（ｎ＝２．５）、酸化ジルコニウム（ｎ＝２．２）、酸化亜鉛（ｎ＝１．９５）、アルミナ（ｎ＝１．７６）などの無機酸化物から形成され得る。マトリックス材料の屈折率は、粉末粒子の屈折率よりも０．２５以上、例えば０．５以上低いことが望ましい。 The blue scatterer 64B is a matrix material having a refractive index sufficiently lower than the refractive index (n) of particles having a particle size of about 10% of the wavelength of blue light (for example, about 450 nm) emitted from the μLED 220. Can be formed by dispersing in. The blue scatterer 64B formed in this way can cause Rayleigh scattering in blue light. The powder particles constituting the blue scatterer 64B are, for example, titanium oxide (n = 2.5 to 2.7), chromium oxide (n = 2.5), zirconium oxide (n = 2.2), zinc oxide (n). = 1.95), can be formed from inorganic oxides such as alumina (n = 1.76). The refractive index of the matrix material is preferably 0.25 or more, for example 0.5 or more, lower than the refractive index of the powder particles.
　基板１００の下面１００Ｂは、μＬＥＤ２２０から放射された光に作用する凹凸表面を有していてもよい。そのような凹凸表面の存在は、赤蛍光体６４Ｒ、緑蛍光体６４Ｇ、および青散乱体６４Ｂから出射される光の放射強度依存性、または基板１００の下面１００Ｂにおける反射率を調整する。 The lower surface 100B of the substrate 100 may have an uneven surface that acts on the light emitted from the μLED 220. The presence of such an uneven surface adjusts the radiation intensity dependence of the light emitted from the red phosphor 64R, the green phosphor 64G, and the blue scatterer 64B, or the reflectance on the lower surface 100B of the substrate 100.
　＜カラーディスプレイIII＞
　以下、図１３Ａおよび図１３Ｂを参照しながら、本開示の実施形態におけるフルカラー表示が可能なμＬＥＤデバイス１０００Ｄの構成例を説明する。図１３Ａでは、Ｚ軸の方向が図１ＡにおけるＺ軸の方向から反転している。図１３Ｂは、μＬＥＤデバイス１０００Ｄの斜視図である。 <Color Display III>
Hereinafter, a configuration example of the μLED device 1000D capable of full-color display according to the embodiment of the present disclosure will be described with reference to FIGS. 13A and 13B. In FIG. 13A, the direction of the Z axis is reversed from the direction of the Z axis in FIG. 1A. FIG. 13B is a perspective view of the μLED device 1000D.
　本実施形態におけるμＬＥＤデバイス１０００Ｄは、基板１００、フロントプレーン２００、中間層３００およびバックプレーン４００を備えている。これらの要素は、前述した様々な構成を備え得る。 The μLED device 1000D in the present embodiment includes a substrate 100, a front plane 200, an intermediate layer 300, and a back plane 400. These elements may have the various configurations described above.
　図示されているμＬＥＤデバイス１０００Ｄは、基板１００に形成された複数のリセス６６０を有している。これらのリセス６６０は、複数のμＬＥＤ２２０から放射された光がそれぞれ入射するように配置されている。言い換えると、個々のリセス６６０は画素領域を規定する。 The illustrated μLED device 1000D has a plurality of recesses 660 formed on the substrate 100. These recesses 660 are arranged so that the light emitted from the plurality of μLEDs 220 is incident on each of them. In other words, each recess 660 defines a pixel area.
　μＬＥＤデバイス１０００Ｄは、更に基板１００の複数のリセス６６０にそれぞれ配置された、赤蛍光体６６Ｒ、緑蛍光体６６Ｇ、および青散乱体６６Ｂを備えている。赤蛍光体６６Ｒは、μＬＥＤ２２０から放射された青の光を赤の光に変換し、緑蛍光体６６Ｇは、μＬＥＤ２２０から放射された青の光を緑の光に変換する。青散乱体６６Ｂは、μＬＥＤ２２０から放射された青の光を散乱する。青散乱体６６Ｂは、赤蛍光体６６Ｒまたは緑蛍光体６６Ｇから発せられた光の強度が示す放射角依存性（例えばランバーシアン分布）に似た放射角依存性を持つように設計され得る。 The μLED device 1000D further includes a red phosphor 66R, a green phosphor 66G, and a blue scatterer 66B, which are respectively arranged in a plurality of recesses 660 of the substrate 100. The red phosphor 66R converts the blue light emitted from the μLED 220 into red light, and the green phosphor 66G converts the blue light emitted from the μLED 220 into green light. The blue scatterer 66B scatters the blue light emitted from the μLED 220. The blue scatterer 66B can be designed to have a radiation angle dependence similar to the radiation angle dependence (eg, Lambersian distribution) exhibited by the intensity of light emitted from the red phosphor 66R or the green phosphor 66G.
　赤蛍光体６６Ｒ、緑蛍光体６６Ｇ、および青散乱体６６Ｂの役割および材料は、前述したμＬＥＤデバイス１０００Ｃにおける赤蛍光体６６Ｒ、緑蛍光体６４Ｇ、および青散乱体６４Ｂの役割および材料と同様である。 The roles and materials of the red phosphor 66R, the green phosphor 66G, and the blue scatterer 66B are similar to the roles and materials of the red phosphor 66R, the green phosphor 64G, and the blue scatterer 64B in the μLED device 1000C described above. ..
　本実施形態でも、μＬＥＤ２２０の発光層２３から放射された光が青の波長（４３５～４８５ｎｍ）を有するように、発光層２３の組成およびバンドギャップが調整されている。 Also in this embodiment, the composition and bandgap of the light emitting layer 23 are adjusted so that the light emitted from the light emitting layer 23 of the μLED 220 has a blue wavelength (435 to 485 nm).
　図１３Ａに示されている例においても、μＬＥＤデバイス１０００Ｄは、リセス６６０を覆う透明保護層６５０を備えている。簡単のため、図１３Ｂでは、透明保護層６５０の記載は省略されている。透明保護層６５０は、赤蛍光体６６Ｒおよび緑蛍光体６６Ｇが吸湿によって劣化しやすい場合、大気中の水分がこれらの蛍光体に悪影響を与えないように封止機能を発揮することが望ましい。透明保護層６５０は、有機層および無機層の積層体であってもよい。 Also in the example shown in FIG. 13A, the μLED device 1000D includes a transparent protective layer 650 that covers the recess 660. For the sake of simplicity, the description of the transparent protective layer 650 is omitted in FIG. 13B. When the red phosphor 66R and the green phosphor 66G are easily deteriorated by moisture absorption, it is desirable that the transparent protective layer 650 exerts a sealing function so that moisture in the atmosphere does not adversely affect these phosphors. The transparent protective layer 650 may be a laminate of an organic layer and an inorganic layer.
　μＬＥＤデバイス１０００ＣとμＬＥＤデバイス１０００Ｄとの間にある主な相違点は、μＬＥＤデバイス１０００Ｄは、基板１００そのものが、赤蛍光体６６Ｒ、緑蛍光体６６Ｇ、および青散乱体６６Ｂを収容する凹部（リセス６６０）を備えていることにある。 The main difference between the μLED device 1000C and the μLED device 1000D is that in the μLED device 1000D, the substrate 100 itself has a recess (recess 660) that accommodates the red phosphor 66R, the green phosphor 66G, and the blue scatterer 66B. ) Is provided.
　リセス６６０の形状は、基板１００の下面１００Ｂの法線方向から視たとき、矩形に限定されず、円、楕円、三角形その他の多角形などであり得る。また、リセス６６０の内壁は基板１００の下面１００Ｂに直交している必要はなく、傾斜していてもよい。具体的には、すり鉢状、角錐状の凹部からリセス６６０が構成されていてもよい。 The shape of the recess 660 is not limited to a rectangle when viewed from the normal direction of the lower surface 100B of the substrate 100, and may be a circle, an ellipse, a triangle, or another polygon. Further, the inner wall of the recess 660 does not have to be orthogonal to the lower surface 100B of the substrate 100, and may be inclined. Specifically, the recess 660 may be composed of mortar-shaped or pyramidal-shaped recesses.
　リセス６６０の深さは、例えば５００ｎｍ以上２５０μｍ以下であり得る。基板１００の厚さをＴとするとき、リセス６６０の深さは、例えば０．００１Ｔ以上０．５Ｔ以下であり、より好ましくは、０．１Ｔ以上０．３Ｔ以下である。赤蛍光体６６Ｒ、緑蛍光体６６Ｇ、および青散乱体６６Ｂがリセス６６０の底部に位置することにより、それぞれからμＬＥＤ２２０の発光層２３までの距離が短縮される。このことにより、μＬＥＤ２２０の発光層２３から放射され、赤蛍光体６６Ｒ、緑蛍光体６６Ｇ、および青散乱体６６Ｂのそれぞれに入射する光束が増加する。また視野角特性も改善される。 The depth of the recess 660 can be, for example, 500 nm or more and 250 μm or less. When the thickness of the substrate 100 is T, the depth of the recess 660 is, for example, 0.001 T or more and 0.5 T or less, and more preferably 0.1 T or more and 0.3 T or less. The location of the red phosphor 66R, the green phosphor 66G, and the blue scatterer 66B at the bottom of the recess 660 reduces the distance from each to the light emitting layer 23 of the μLED 220. As a result, the luminous flux emitted from the light emitting layer 23 of the μLED 220 and incident on each of the red phosphor 66R, the green phosphor 66G, and the blue scatterer 66B increases. The viewing angle characteristics are also improved.
　本実施形態によれば、基板１００の厚さおよび強度を大きく維持しつつ、赤蛍光体６６Ｒ、緑蛍光体６６Ｇ、および青散乱体６６ＢからμＬＥＤ２２０の発光層２３までの距離を短縮することが可能になる。 According to this embodiment, it is possible to shorten the distance from the red phosphor 66R, the green phosphor 66G, and the blue scatterer 66B to the light emitting layer 23 of the μLED 220 while maintaining a large thickness and intensity of the substrate 100. become.
　リセス６６０は、例えば、フェムト秒レーザまたはピコ秒レーザなどの超短パルスレーザで基板１００の下面１００Ｂを加工することによって形成され得る（アブレーション法）。また、リセス６６０の形状および位置を規定する複数の開口部を有するレジストマスクをリソグラフィ技術によって基板１００の下面１００Ｂ上に形成した後、基板１００の下面１００Ｂの露出部分をエッチングすることによってもリセス６６０を形成できる。このようなエッチングは、例えばＩＣＰおよびＲＩＥの組合せによって実現され得る。 The recess 660 can be formed by processing the lower surface 100B of the substrate 100 with an ultrashort pulse laser such as a femtosecond laser or a picosecond laser (ablation method). The recess 660 can also be formed by forming a resist mask having a plurality of openings that define the shape and position of the recess 660 on the lower surface 100B of the substrate 100 by lithography technology, and then etching the exposed portion of the lower surface 100B of the substrate 100. Can be formed. Such etching can be achieved, for example, by a combination of ICP and RIE.
　リセス６６０の底面および／または側面には、微細な凹凸が形成されていてもよい。そのような凹凸は、光を拡散したり、取り出し効率を高めたりするため、画像品質を向上させ得る。 Fine irregularities may be formed on the bottom surface and / or the side surface of the recess 660. Such irregularities can improve image quality because they diffuse light and increase extraction efficiency.
　上記のフルカラー表示が可能なμＬＥＤデバイス１０００Ｂ、１０００Ｃ、１０００Ｄでは、μＬＥＤ２２０から放射された光（励起光）の波長が４３５～４８５ｎｍの範囲、すなわち、青の光を発するように発光層２３の組成およびバンドギャップが調整されている。しかし、本開示の実施形態におけるμＬＥＤデバイスは、これらの例に限定されない。例えば、μＬＥＤ２２０の発光層２３から放射された光が紫外の波長（例えば３６５～４００ｎｍ）または青紫の波長（４００ｎｍ～４２０ｎｍ。典型的には、４０５ｎｍ）を有するように、発光層２３の組成およびバンドギャップが調整されていてもよい。具体的には、発光層２３を構成するＩｎyＧａ1-yＮにおけるＩｎの組成比率ｙを、例えば０≦ｙ≦０．１５の範囲内に設定してもよい。ｙ＝０のとき、波長３６５ｎｍの発光が得られる。ｙ＝０．１のとき、波長４１０ｎｍ近傍の青紫の波長を有する発光が得られる。なお、発光層２３を構成する半導体層をＡｌＧａＮまたはＩｎＡｌＧａＮから形成することにより、３６５ｎｍよりも短い波長を有する光を放射されることもできる。このような例では、μＬＥＤ２２０から放射された光を赤、緑、および青のそれぞれの蛍光体を励起するために用いる。このため、μＬＥＤ２２０の発光波長が変動またはシフトしても、色むらが発生しにくくなる。μＬＥＤ２２０の発光波長は、発光層２３の組成比率、駆動電流の大きさ、温度などによって変動し得る。しかし、３原色のそれぞれに量子ドットの蛍光体を用いていると、上記の原因から励起光の波長が変動しても、蛍光体から出る光の波長にはほとんど影響しない。このため、本実施形態によれば、色むらが生じにくく、より優れた表示特性が実現する。 In the above-mentioned μLED devices 1000B, 1000C, 1000D capable of full-color display, the wavelength of the light (excitation light) emitted from the μLED 220 is in the range of 435 to 485 nm, that is, the composition of the light emitting layer 23 and the light emitting layer 23 so as to emit blue light. The bandgap has been adjusted. However, the μLED device in the embodiments of the present disclosure is not limited to these examples. For example, the composition and band of the light emitting layer 23 such that the light emitted from the light emitting layer 23 of the μLED 220 has an ultraviolet wavelength (eg, 365 to 400 nm) or a bluish-purple wavelength (400 nm to 420 nm, typically 405 nm). The gap may be adjusted. Specifically, the composition ratio y of In in In y Ga 1-y N constituting the light emitting layer 23 may be set within the range of, for example, 0 ≦ y ≦ 0.15. When y = 0, light emission with a wavelength of 365 nm can be obtained. When y = 0.1, light emission having a bluish-purple wavelength near 410 nm can be obtained. By forming the semiconductor layer constituting the light emitting layer 23 from AlGaN or InAlGaN, light having a wavelength shorter than 365 nm can be emitted. In such an example, the light emitted from the μLED 220 is used to excite the red, green, and blue phosphors, respectively. Therefore, even if the emission wavelength of the μLED 220 fluctuates or shifts, color unevenness is less likely to occur. The emission wavelength of the μLED 220 may vary depending on the composition ratio of the light emitting layer 23, the magnitude of the drive current, the temperature, and the like. However, when a quantum dot phosphor is used for each of the three primary colors, even if the wavelength of the excitation light fluctuates due to the above-mentioned cause, the wavelength of the light emitted from the phosphor is hardly affected. Therefore, according to the present embodiment, color unevenness is less likely to occur, and better display characteristics are realized.
　蛍光体の例は、「量子ドット」と呼ばれる多数のナノ粒子（量子ドット蛍光体）であり得る。量子ドット蛍光体は、例えばＣｄＴｅ、ＩｎＰ、ＧａＮなどの半導体から形成され得る。量子ドット蛍光体は、そのサイズに応じて発する光の波長が変化する。励起光を受けて赤、緑、および青の光を発するように調整された量子ドット分散シートを図１１の蛍光体層６００として利用したり、図１２および図１３の蛍光体として利用してもよい。 An example of a phosphor can be a large number of nanoparticles (quantum dot phosphors) called "quantum dots". The quantum dot phosphor can be formed from a semiconductor such as CdTe, InP, or GaN. The wavelength of light emitted from a quantum dot phosphor changes according to its size. A quantum dot dispersion sheet adjusted to emit red, green, and blue light in response to excitation light can be used as the phosphor layer 600 in FIG. 11 or as the phosphor in FIGS. 12 and 13. Good.
　量子ドットの蛍光体は、有機樹脂、低融点ガラスなどの無機材料、または、有機材料と無機材料のハイブリット材料から形成されたマトリクス内に分散されて使用される。分散される蛍光体の量（重量比率）は、青、緑、赤の順序で少なくなる。 Quantum dot phosphors are dispersed and used in a matrix formed of an inorganic material such as an organic resin or low melting point glass, or a hybrid material of an organic material and an inorganic material. The amount (weight ratio) of the dispersed phosphors decreases in the order of blue, green, and red.
　ある例における量子ドット蛍光体は、コア・シェル構造を有している。コアは、例えばＣｄＳ、ＩｎＰ、ＩｎＧａＰ、ＩｎＮ、ＣｄＳｅ、ＩｎＧａＮ、またはＺｎＣｄＳｅから形成され得る。特に波長３６０ｎｍ～４６０ｎｍの発光を得る場合、ＣｄＳからコアが形成された蛍光体を好適に用いることができる。ＣｄＳからコアを形成する場合、コアの粒子径を４．０ｎｍ～７．３ｎｍの範囲で調整すると、波長４４０ｎｍ～４６０ｎｍの青の発光を得ることができる。他の材料（ＩｎＰ、ＩｎＧａＰ、ＩｎＮ、ＣｄＳｅ）からコアを形成する場合、例えば、青の光（中心波長４７５ｎｍ）は１．４ｎｍ～３．３ｎｍの粒子径、緑の光（中心波長５３０ｎｍ）は１．７ｎｍ～４．２ｎｍの粒子径、赤の光（中心波長６３０ｎｍ）は２．０ｎｍ～６．１ｎｍの粒子径で得ることが可能である。どのような材料から量子ドットを形成するかは、量子効率、粒子径などに基づいて適宜決定され得る。なお、Ｉｎ0.5Ｇａ0.5Ｐからコアを形成した量子ドット蛍光体は、相対的に粒子径が大きいため、製造しやすいという利点がある。より高い量子効率を実現したい場合には、例えばＧａを含有しないＩｎＰからコアが形成された量子ドットを用いることが望ましい。 The quantum dot phosphor in one example has a core-shell structure. The core can be formed from, for example, CdS, InP, InGaP, InN, CdSe, InGaN, or ZnCdSe. In particular, in the case of obtaining light emission having a wavelength of 360 nm to 460 nm, a phosphor having a core formed from CdS can be preferably used. When forming a core from CdS, if the particle size of the core is adjusted in the range of 4.0 nm to 7.3 nm, blue light emission having a wavelength of 440 nm to 460 nm can be obtained. When forming a core from other materials (InP, InGaP, InN, CdSe), for example, blue light (center wavelength 475 nm) has a particle size of 1.4 nm to 3.3 nm, and green light (center wavelength 530 nm). A particle size of 1.7 nm to 4.2 nm and red light (center wavelength of 630 nm) can be obtained with a particle size of 2.0 nm to 6.1 nm. The material from which the quantum dots are formed can be appropriately determined based on the quantum efficiency, particle size, and the like. The quantum dot phosphor having a core formed from In 0.5 Ga 0.5 P has an advantage that it is easy to manufacture because it has a relatively large particle size. When it is desired to realize higher quantum efficiency, it is desirable to use, for example, a quantum dot whose core is formed from InP containing no Ga.
　本発明の実施形態は、新しいマイクロＬＥＤデバイスを提供する。マイクロＬＥＤデバイスは、ディスプレイとして用いられる場合、スマートフォン、タブレット端末、車載用ディスプレイ、および中小型から大型のテレビジョン装置に広く適用され得る。マイクロＬＥＤデバイスの用途は、ディスプレイに限定されない。 An embodiment of the present invention provides a new micro LED device. When used as a display, the micro LED device can be widely applied to smartphones, tablet terminals, in-vehicle displays, and small to medium to large television devices. Applications of micro LED devices are not limited to displays.
　２１・・・第１半導体層、２２・・・第２半導体層、２３・・・発光層、２４・・・金属プラグ、２５・・・埋め込み絶縁物、３１・・・第１コンタクト電極、３２・・・第２コンタクト電極、３６・・・ビア電極、３８・・・層間絶縁層、１００・・・結晶成長基板、２００・・・フロントプレーン、２２０・・・μＬＥＤ、２４０・・・素子分離領域、３００・・・中間層、４００・・・バックプレーン、１０００・・・μＬＥＤデバイス 21 ... 1st semiconductor layer, 22 ... 2nd semiconductor layer, 23 ... light emitting layer, 24 ... metal plug, 25 ... embedded insulator, 31 ... 1st contact electrode, 32 ... 2nd contact electrode, 36 ... via electrode, 38 ... interlayer insulating layer, 100 ... crystal growth substrate, 200 ... front plane, 220 ... μLED, 240 ... element separation Region, 300 ... Intermediate layer, 400 ... Back plane, 1000 ... μLED device

Claims (17)

  1. 　複数の開口部を有するマスク層によって上面が覆われた絶縁性の結晶成長基板と、
    　前記結晶成長基板に支持されたフロントプレーンであって、それぞれが第１導電型の第１半導体層および第２導電型の第２半導体層を有する複数のマイクロＬＥＤ、ならびに前記複数のマイクロＬＥＤの間に位置する素子分離領域を含み、前記素子分離領域が、前記第２半導体層に電気的に接続された少なくともひとつの金属プラグを有している、フロントプレーンと、
    　前記フロントプレーンに支持された中間層であって、それぞれが前記複数のマイクロＬＥＤの前記第１半導体層に電気的に接続された複数の第１コンタクト電極、および前記金属プラグに接続された少なくともひとつの第２コンタクト電極を含む、中間層と、
    　前記中間層に支持されたバックプレーンであって、前記複数の第１コンタクト電極および前記少なくともひとつの第２コンタクト電極を介して前記複数のマイクロＬＥＤに電気的に接続された電気回路を有し、前記電気回路は複数の薄膜トランジスタを含む、バックプレーンと
    を備え、
    　前記マスク層は、導電材料から形成されており、
    　前記マスク層は、前記複数のマイクロＬＥＤの位置を規定する複数のマスク開口部と、前記金属プラグに接続する接続部とを有し、
    　前記複数のマイクロＬＥＤの前記第１半導体層および前記第２半導体層は、前記マスク層が有する前記複数のマスク開口部から選択的に成長したエピタキシャル層であり、前記第２半導体層は前記マスク層にオーミック接触しており、
    　前記複数の薄膜トランジスタのそれぞれは、前記フロントプレーンおよび／または前記中間層上に成長した半導体層を有している、マイクロＬＥＤデバイス。     An insulating crystal growth substrate whose upper surface is covered with a mask layer having a plurality of openings,
    Between the plurality of micro LEDs supported by the crystal growth substrate, each having a first conductive type first semiconductor layer and a second conductive type second semiconductor layer, and the plurality of micro LEDs. A front plane comprising an element separation region located in, wherein the element separation region has at least one metal plug electrically connected to the second semiconductor layer.
    A plurality of first contact electrodes, each of which is an intermediate layer supported by the front plane and electrically connected to the first semiconductor layer of the plurality of micro LEDs, and at least one connected to the metal plug. In the intermediate layer, including the second contact electrode of
    It is a backplane supported by the intermediate layer and has an electric circuit electrically connected to the plurality of micro LEDs via the plurality of first contact electrodes and the at least one second contact electrode. The electrical circuit comprises a backplane containing a plurality of thin film transistors.
    The mask layer is formed of a conductive material and
    The mask layer has a plurality of mask openings that define the positions of the plurality of micro LEDs, and a connection portion that connects to the metal plug.
    The first semiconductor layer and the second semiconductor layer of the plurality of micro LEDs are epitaxial layers selectively grown from the plurality of mask openings of the mask layer, and the second semiconductor layer is the mask layer. Have an ohmic contact with
    A micro LED device in which each of the plurality of thin film transistors has a semiconductor layer grown on the front plane and / or the intermediate layer.
  2. 　前記マスク層は、前記第１半導体層に対して、電気的抵抗性または絶縁性の接触をしている、請求項１に記載のマイクロＬＥＤデバイス。 The micro LED device according to claim 1, wherein the mask layer is in electrical resistant or insulating contact with the first semiconductor layer.
  3. 　前記第２半導体層は、前記マスク層に部分的にオーバーラップしている、請求項１に記載のマイクロＬＥＤデバイス。 The micro LED device according to claim 1, wherein the second semiconductor layer partially overlaps the mask layer.
  4. 　前記第２半導体層の導電型はｐ型であり、
    　前記マスク層は、Ｔｉ、Ｃｒ、Ｍｏ、Ｍｎ、Ｗ、およびＴａからなる群から選択された少なくとも１種の高融点金属から形成されている、請求項１から３のいずれかに記載のマイクロＬＥＤデバイス。     The conductive type of the second semiconductor layer is p type, and is
    The micro LED according to any one of claims 1 to 3, wherein the mask layer is formed of at least one refractory metal selected from the group consisting of Ti, Cr, Mo, Mn, W, and Ta. device.
  5. 　前記マスク層を前記第１半導体層から絶縁する絶縁層を前記マスク層上に備えている、請求項１から４のいずれかに記載のマイクロＬＥＤデバイス。 The micro LED device according to any one of claims 1 to 4, wherein an insulating layer that insulates the mask layer from the first semiconductor layer is provided on the mask layer.
  6. 　前記第２半導体層は、前記マスク層上を横方向に成長した部分を有しており、
    　前記横方向に成長した部分は、前記絶縁層に対して部分的にオーバーラップしている、請求項１から５のいずれかに記載のマイクロＬＥＤデバイス。     The second semiconductor layer has a portion that grows laterally on the mask layer.
    The micro LED device according to any one of claims 1 to 5, wherein the laterally grown portion partially overlaps the insulating layer.
  7. 　前記マスク開口部は、前記基板上の位置に応じて異なる大きさまたは形状を有しており、
    　前記マスク開口部の大きさまたは形状は、各マイクロＬＥＤから放射される光の波長を規定する、請求項１から６のいずれかに記載のマイクロＬＥＤデバイス。     The mask opening has a different size or shape depending on the position on the substrate.
    The micro LED device according to any one of claims 1 to 6, wherein the size or shape of the mask opening defines a wavelength of light emitted from each micro LED.
  8. 　前記フロントプレーンの前記素子分離領域は、前記複数のマイクロＬＥＤの間を埋める埋め込み絶縁物を有しており、前記埋め込み絶縁物は、前記金属プラグのための少なくともひとつのスルーホールを有している、請求項１から７のいずれかに記載のマイクロＬＥＤデバイス。 The element separation region of the front plane has an embedded insulator that fills between the plurality of micro LEDs, and the embedded insulator has at least one through hole for the metal plug. , The micro LED device according to any one of claims 1 to 7.
  9. 　前記フロントプレーンは、平坦な表面を有しており、
    　前記平坦な表面は前記中間層に接している、請求項１から８のいずれかに記載のマイクロＬＥＤデバイス。     The front plane has a flat surface and
    The micro LED device according to any one of claims 1 to 8, wherein the flat surface is in contact with the intermediate layer.
  10. 　前記中間層は、平坦な表面を有する層間絶縁層を含み、
    　前記層間絶縁層は、前記複数の第１コンタクト電極および前記少なくともひとつの第２コンタクト電極をそれぞれ前記電気回路に接続するための複数のコンタクトホールと、
    　前記コンタクトホールを埋めるビア電極と、
    を有している、請求項１から９のいずれかに記載のマイクロＬＥＤデバイス。     The intermediate layer includes an interlayer insulating layer having a flat surface.
    The interlayer insulating layer includes a plurality of contact holes for connecting the plurality of first contact electrodes and the at least one second contact electrode to the electric circuit, respectively.
    A via electrode that fills the contact hole and
    The micro LED device according to any one of claims 1 to 9.
  11. 　前記複数の薄膜トランジスタのそれぞれは、前記層間絶縁層の前記平坦な表面上に形成されたソース電極、ドレイン電極、およびゲート電極を有しており、
    　前記半導体層は、前記ゲート電極の上方に位置し、前記ソース電極および前記ドレイン電極の上面に接触している、請求項１０に記載のマイクロＬＥＤデバイス。     Each of the plurality of thin film transistors has a source electrode, a drain electrode, and a gate electrode formed on the flat surface of the interlayer insulating layer.
    The micro LED device according to claim 10, wherein the semiconductor layer is located above the gate electrode and is in contact with the upper surfaces of the source electrode and the drain electrode.
  12. 　前記複数の薄膜トランジスタのそれぞれは、前記半導体層の上層に位置するソース電極、ドレイン電極、およびゲート電極を有しており、
    　前記半導体層は、前記層間絶縁層の前記平坦な表面上に形成されており、
    　前記半導体層の一部は、前記ソース電極および前記ドレイン電極の少なくとも一方と前記ビア電極とによって上下から挟まれている、請求項１０に記載のマイクロＬＥＤデバイス。     Each of the plurality of thin film transistors has a source electrode, a drain electrode, and a gate electrode located above the semiconductor layer.
    The semiconductor layer is formed on the flat surface of the interlayer insulating layer.
    The micro LED device according to claim 10, wherein a part of the semiconductor layer is sandwiched from above and below by at least one of the source electrode and the drain electrode and the via electrode.
  13. 　絶縁性の結晶成長基板に支持されたフロントプレーンであって、それぞれが第１導電型の第１半導体層および第２導電型の第２半導体層を有する複数のマイクロＬＥＤ、ならびに前記複数のマイクロＬＥＤの間に位置する素子分離領域を含み、前記素子分離領域が、前記第２半導体層に電気的に接続された少なくともひとつの金属プラグを有している、フロントプレーン、および
    　前記フロントプレーンに支持された中間層であって、それぞれが前記複数のマイクロＬＥＤの前記第１半導体層に電気的に接続された複数の第１コンタクト電極、および前記金属プラグに接続された少なくともひとつの第２コンタクト電極を含む、中間層、
    を備える積層構造体を用意する工程と、
    　前記積層構造体上にバックプレーンを形成する工程であって、前記複数の第１コンタクト電極および前記少なくともひとつの第２コンタクト電極を介して前記複数のマイクロＬＥＤに電気的に接続された電気回路を有し、前記電気回路は複数の薄膜トランジスタを含む、バックプレーンを形成する工程と、
    を含み、
    　前記積層構造体を用意する工程は、前記結晶成長基板を覆うマスク層であって、前記複数のマイクロＬＥＤの位置を規定する複数のマスク開口部を有する前記マスク層を形成する工程と、
    　前記マスク開口部から前記第２半導体層および前記第１半導体層を、順次、成長させる工程と、
    を含み、
    　前記マスク層は導電材料から形成され、前記第２半導体層は前記マスク層にオーミック接触しており、
    　前記バックプレーンを形成する工程は、
    　前記積層構造体上に半導体層を堆積する工程と、
    　前記積層構造体上の前記半導体層をパターニングする工程と、
    を含む、マイクロＬＥＤデバイスの製造方法。     A plurality of microLEDs supported by an insulating crystal growth substrate, each having a first conductive type first semiconductor layer and a second conductive type second semiconductor layer, and the plurality of microLEDs. The element separation region includes an element separation region located between the two, and the front plane having at least one metal plug electrically connected to the second semiconductor layer, and supported by the front plane. A plurality of first contact electrodes, each of which is electrically connected to the first semiconductor layer of the plurality of microLEDs, and at least one second contact electrode connected to the metal plug. Including, middle layer,
    And the process of preparing a laminated structure
    In the step of forming a back plane on the laminated structure, an electric circuit electrically connected to the plurality of micro LEDs via the plurality of first contact electrodes and the at least one second contact electrode is provided. The electric circuit has a step of forming a back plane including a plurality of thin film transistors, and
    Including
    The steps of preparing the laminated structure include a step of forming the mask layer that covers the crystal growth substrate and has a plurality of mask openings that define the positions of the plurality of micro LEDs.
    A step of sequentially growing the second semiconductor layer and the first semiconductor layer from the mask opening, and
    Including
    The mask layer is formed of a conductive material, and the second semiconductor layer is in ohmic contact with the mask layer.
    The step of forming the backplane is
    A step of depositing a semiconductor layer on the laminated structure and
    The step of patterning the semiconductor layer on the laminated structure and
    A method for manufacturing a micro LED device, including.
  14. 　前記素子分離領域の形状および位置は、前記マスク層が有する前記複数のマスク開口部から選択的に成長した前記第２半導体層および前記第１半導体層によって規定される、請求項１３に記載の製造方法。 The production according to claim 13, wherein the shape and position of the element separation region are defined by the second semiconductor layer and the first semiconductor layer selectively grown from the plurality of mask openings of the mask layer. Method.
  15. 　前記積層構造体を用意する工程は、
    　前記複数のマスク開口部から前記第２半導体層および前記第１半導体層を、順次、エピタキシャル成長させる工程の後、前記マスク層と前記第２半導体層との間でオーミック接触を完成する熱処理工程を含む、請求項１３または１４に記載の製造方法。     The step of preparing the laminated structure is
    After the step of sequentially epitaxially growing the second semiconductor layer and the first semiconductor layer from the plurality of mask openings, a heat treatment step of completing ohmic contact between the mask layer and the second semiconductor layer is included. , The manufacturing method according to claim 13 or 14.
  16. 　前記積層構造体を用意する工程において、前記熱処理工程は、前記フロントプレーンを完成する前に行う、請求項１５に記載の製造方法。 The manufacturing method according to claim 15, wherein in the step of preparing the laminated structure, the heat treatment step is performed before the front plane is completed.
  17. 　前記複数のマスク開口部から前記第２半導体層および前記第１半導体層を、順次、エピタキシャル成長させる工程中の加熱により、前記マスク層と前記第２半導体層との間でオーミック接触を完成させる、請求項１３または１４に記載の製造方法。 Claims to complete ohmic contact between the mask layer and the second semiconductor layer by heating during the step of sequentially epitaxially growing the second semiconductor layer and the first semiconductor layer from the plurality of mask openings. Item 13. The manufacturing method according to Item 13.
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