[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

WO2020115813A1 - 半導体装置、内視鏡、および、半導体装置の製造方法 - Google Patents

半導体装置、内視鏡、および、半導体装置の製造方法 Download PDF

Info

Publication number
WO2020115813A1
WO2020115813A1 PCT/JP2018/044530 JP2018044530W WO2020115813A1 WO 2020115813 A1 WO2020115813 A1 WO 2020115813A1 JP 2018044530 W JP2018044530 W JP 2018044530W WO 2020115813 A1 WO2020115813 A1 WO 2020115813A1
Authority
WO
WIPO (PCT)
Prior art keywords
core wire
terminal
semiconductor
wiring
electrode
Prior art date
Application number
PCT/JP2018/044530
Other languages
English (en)
French (fr)
Inventor
慧一 小林
Original Assignee
オリンパス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by オリンパス株式会社 filed Critical オリンパス株式会社
Priority to PCT/JP2018/044530 priority Critical patent/WO2020115813A1/ja
Publication of WO2020115813A1 publication Critical patent/WO2020115813A1/ja
Priority to US17/336,499 priority patent/US12033975B2/en

Links

Images

Classifications

    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B1/00—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor
    • A61B1/00064—Constructional details of the endoscope body
    • A61B1/0011—Manufacturing of endoscope parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B1/00—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor
    • A61B1/00064—Constructional details of the endoscope body
    • A61B1/00071—Insertion part of the endoscope body
    • A61B1/0008—Insertion part of the endoscope body characterised by distal tip features
    • A61B1/00096—Optical elements
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B1/00—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor
    • A61B1/04—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor combined with photographic or television appliances
    • A61B1/05—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor combined with photographic or television appliances characterised by the image sensor, e.g. camera, being in the distal end portion
    • A61B1/051—Details of CCD assembly
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H04N23/54—Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H04N23/555—Constructional details for picking-up images in sites, inaccessible due to their dimensions or hazardous conditions, e.g. endoscopes or borescopes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/57—Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/24011—Deposited, e.g. MCM-D type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24101—Connecting bonding areas at the same height
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2512—Layout
    • H01L2224/25175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32155—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. being an insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/82005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82106—Forming a build-up interconnect by subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H04N23/55—Optical parts specially adapted for electronic image sensors; Mounting thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/56—Cameras or camera modules comprising electronic image sensors; Control thereof provided with illuminating means

Definitions

  • the present invention relates to a semiconductor device in which a semiconductor unit and an electric cable are connected, an endoscope including a semiconductor device in which a semiconductor unit and an electric cable are connected, and a semiconductor unit and an electric cable are connected.
  • the present invention relates to a method for manufacturing a semiconductor device.
  • the image pickup element is provided with an external electrode for supplying a drive signal and outputting an image pickup signal.
  • the image sensor may be damaged by heat or stress at the time of joining.
  • WO 2017/037828 discloses an imaging device in which an imaging element is joined to a wiring board and an electric cable is joined to the wiring board.
  • the image pickup device will be damaged or the reliability of the image sensor will be reduced due to heat or stress when the image sensor is bonded to the wiring board. Further, if the image pickup device is joined to the wiring board, the thickness of the image pickup device becomes thicker, which may impair the reduction in diameter of the distal end portion of the endoscope. Furthermore, when manufacturing a plurality of image pickup devices, the process of joining the image pickup element to the wiring board is complicated for each device.
  • Japanese Patent Laid-Open No. 2007-287801 discloses a hybrid circuit device in which a semiconductor module including a light emitting element device and an LSI are mounted on a multilayer wiring board. An optical fiber is provided in the light emitting device.
  • Embodiments of the present invention provide a highly reliable and small semiconductor device, a highly reliable and small-diameter endoscope, and a semiconductor device manufacturing method capable of easily manufacturing a highly reliable and small semiconductor device.
  • the purpose is to
  • a semiconductor device has a semiconductor portion that has a first surface and a second surface facing the first surface, and an external electrode is disposed on the second surface, a first upper surface and the first surface.
  • the semiconductor layer and the terminal portion are disposed on the third surface of the wiring layer and have the same outer dimensions as the wiring layer, and the semiconductor portion and the terminal portion are fixed in a state of not covering the first surface and the first upper surface.
  • the endoscope of the embodiment includes a semiconductor device, and the semiconductor device has a first surface and a second surface facing the first surface, and an external electrode is provided on the second surface.
  • the wiring layer that is in contact with the lower surface of the wiring layer and the third surface of the wiring layer, the outer dimensions of which are the same as those of the wiring layer.
  • a resin layer that is fixed without covering the first upper surface; and an electric cable that has a core wire and the core wire is joined to the core wire terminal. It is in contact with the core wire electrode.
  • a method of manufacturing a semiconductor device includes a plurality of semiconductor parts each having a first surface and a second surface facing the first surface, and a plurality of semiconductor parts having one or more external electrodes arranged on the second surface.
  • a plurality of terminal portions each having an upper surface of 1 and a lower surface facing the first upper surface, the core wire terminals being disposed on the first upper surface, and the core wire electrodes being disposed on the lower surface;
  • a first temporary fixing step of temporarily fixing to the first support substrate, and a resin is disposed around the plurality of semiconductor portions and the plurality of terminal portions of the first support substrate, and the semiconductor portion and the terminals are provided.
  • a resin disposing step in which a portion is fixed by the resin, and a first separating step in which a main portion including the plurality of semiconductor portions, the plurality of terminal portions, and the resin is separated from the first support substrate.
  • a second temporary fixing step of temporarily fixing at least one of the first surface of the plurality of semiconductor portions and the first upper surface of the plurality of terminal portions of the main portion to a second support substrate.
  • a wiring layer arranging step in which a plurality of wiring layers including wiring that connects the external electrodes of the plurality of semiconductor portions and the core wire electrodes of the plurality of terminal portions are arranged, and from the second support substrate
  • a highly reliable and small semiconductor device a highly reliable and small-diameter endoscope, and a method for manufacturing a highly reliable and small semiconductor device can be provided easily. Can be provided.
  • FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment.
  • FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment.
  • FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment.
  • FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment.
  • FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment.
  • FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment.
  • FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment.
  • FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment.
  • FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment.
  • FIG. 7 is a plan view for explaining the method for manufacturing the semiconductor device of the first embodiment.
  • FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment.
  • FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment.
  • It is an exploded view of the semiconductor device of 2nd Embodiment. It is a disassembled sectional view of a part of semiconductor device of a 2nd embodiment. It is sectional drawing of the semiconductor device of 3rd Embodiment. It is sectional drawing of the semiconductor device of 4th Embodiment. It is a perspective view of the endoscope of a 5th embodiment.
  • the semiconductor device of the present embodiment shown in FIGS. 1, 2 and 3 is the image pickup device 1 arranged at the tip 90A of the endoscope 9 (see FIG. 19).
  • the horizontal type image pickup device 1 includes an image pickup section 10 which is a semiconductor section, a prism 15, a wiring layer 20, a terminal section 30, an electric cable 40, and a resin layer 45.
  • the image pickup unit 10 includes an image pickup element 11 which is a semiconductor element and a cover glass 12.
  • the imaging unit 10 is a rectangular parallelepiped having a first surface 10SA and a second surface 10SB facing the first surface 10SA.
  • a plurality of external electrodes 14 are arranged on the second surface 10SB.
  • the light receiving portion 13 of the image sensor 11 and the external electrode 14 are connected to each other, for example, via the first penetrating wiring 11X (see FIG. 5).
  • the image sensor 11 may be either a front side illumination type image sensor or a back side illumination type image sensor.
  • the prism 15 is adhered to the first surface 10SA with a transparent adhesive 16.
  • the terminal portion 30 has a first upper surface 30SA1 and a lower surface 30SB that faces the first upper surface 30SA1.
  • the terminal portion 30 is a cable connecting portion in which a plurality of core wire terminals (connection lands) 31 are arranged on the first upper surface 30SA1 and a plurality of core wire electrodes 32 are arranged on the lower surface 30SB.
  • the core wire terminal 31 and the core wire electrode 32 are connected to each other, for example, via the second through wiring 30X (see FIG. 5).
  • the wiring layer 20 is a wiring member having a third surface 20SA and a fourth surface 20SB facing the third surface 20SA, and including an insulating layer 22 (22A, 22B) and a wiring 21.
  • the third surface 20SA is in contact with the second surface 10SB of the imaging unit 10 and the lower surface 30SB of the terminal unit 30.
  • the electric cable 40 has a core wire 41 and a first coating layer 42 that covers the core wire 41.
  • the core wire 41 is joined to the core wire terminal 31 of the terminal portion 30 by using, for example, solder.
  • the core wire 41 is electrically connected to the light receiving unit 13 via the core wire terminal 31, the second through wiring 30X, the core wire electrode 32, the wiring 21, and the external electrode 14.
  • the resin layer 45 is arranged on the third surface 20SA of the wiring layer 20, and fixes the imaging unit 10 and the terminal unit 30.
  • the resin layer 45 is a fixing portion that fixes the image pickup unit 10 and the terminal unit 30 to the wiring layer 20 in a state of being integrally held.
  • the thickness H45 of the resin layer 45 is smaller than the thickness of the terminal portion 30 (the length H31 from the first upper surface 30SA1 to the lower surface 30SB). Therefore, the core terminal 31 of the terminal portion 30 is not covered with the resin layer 45. That is, the upper surface 45SA of the resin layer 45 is located at a position lower than the first surface 10SA and the first upper surface 30SA1 (position closer to the third surface 20SA).
  • the upper surface 45SA of the resin layer 45 is parallel to the third surface 20SA of the wiring layer 20, and the outer dimensions of both are the same. In other words, the side surface of the resin layer 45 and the side surface of the wiring layer are on the same plane.
  • the wiring 21 of the wiring layer 20 is in contact with the external electrode 14 and the core wire electrode 32.
  • the wiring layer 20 is a rewiring layer provided on the resin layer 45 to which the imaging unit 10 and the terminal unit 30 are fixed.
  • At least a region of the wiring 21 that is in contact with the external electrode 14 and the core wire electrode 32 is made of a conductive material deposited on the surfaces of the external electrode 14 and the core wire electrode 32.
  • the wiring 21 is made of a copper sputtered film or a base conductive film and an electrolytic copper plating film formed on the external electrode 14 and the core wire electrode 32.
  • the wiring 21 is formed into a film, and the wiring 21 and the external electrode 14 and the core wire electrode 32 are electrically connected to each other by being joined in a state of being in contact with each other. For this reason, the imaging device 1 is easy to manufacture and has high reliability in joining the wiring 21 to the external electrode 14 and the core wire electrode 32.
  • the image pickup element When the electric cable 40 is joined to the external electrode 14 of the image pickup element 11, the image pickup element may be damaged by heat or stress at the time of joining. Further, when the image pickup device 11 is joined to the wiring board, the thickness of the image pickup device is increased.
  • the external terminal 14 of the image pickup element 11 is in contact with the wiring 21 and is not joined using solder. Therefore, the image pickup element 11 is damaged by heat or stress when the solder is melted, and There is no risk of reducing reliability. Further, since the image pickup device 11 is fixed to the resin layer 45, not to the wiring board, the image pickup device 1 is thin and compact.
  • a known semiconductor manufacturing technique is used to fabricate an imaging element wafer by disposing a plurality of light receiving sections 13 and the like on a silicon wafer. It Peripheral circuits that perform primary processing on the output signal of the light receiving unit 13 or process drive control signals may be formed on the imaging element wafer.
  • a glass wafer that protects the light receiving section 13 is bonded to the light receiving surface of the image pickup element wafer. Then, the external electrode 14 connected to the light receiving portion 13 by passing through the first penetrating wiring 11X is arranged on the back surface.
  • the image pickup element wafer to which the glass wafer is attached a plurality of image pickup sections 10 (image pickup element 11 to which the cover glass 12 is attached) are manufactured.
  • the terminal portion 30 is a three-dimensional wiring board whose base is resin, ceramic, silicon or the like.
  • the terminal portion 30 may be a molded circuit component (MID: Molded Interconnect Device) that is a three-dimensional component in which a conductive pattern is formed on an injection-molded product.
  • MID Molded Interconnect Device
  • the core wire terminal 31 and the core wire electrode 32 may be connected via a surface wiring.
  • Step S20 First Temporary Fixing Step As shown in FIG. 5, the imaging unit 10 and the terminal unit 30 are temporarily fixed to the first support substrate 60 in a predetermined arrangement state.
  • an adhesive layer (temporary fixing layer) 60A is provided on a base body 60B. Since the adhesive layer 60A is soft, when the external electrode 14 and the core wire electrode 32 are convex electrodes, both are in a state of being embedded in the adhesive layer 60A. As will be described later, the adhesive layer 60A loses its adhesive force by ultraviolet irradiation treatment or heat treatment.
  • the plurality of image capturing units 10 and the plurality of terminal units 30 are temporarily fixed to one first support substrate 60.
  • the uncured resin layer 45 is disposed on the main surface 60SA around the image capturing section 10 and the terminal section 30 of the first support substrate 60.
  • the resin layer 45 By curing the resin layer 45, the main part wafer 2W in which the imaging section 10 and the terminal section 30 are fixed by the resin layer 45 is manufactured.
  • the uncured epoxy resin is disposed on the first support substrate 60, and then the thermosetting process is performed.
  • the resin layer 45 is arranged so as not to cover the first surface 10SA of the imaging unit 10 and the first upper surface 30SA1 of the terminal unit 30.
  • the resin layer 45 may completely cover the side surface of the imaging unit 10.
  • the main wafer 2W in which the plurality of imaging units 10 and the plurality of terminal units 30 are fixed by the resin layer 45 is separated from the first support substrate 60.
  • the adhesive layer 60A loses its adhesive force by the ultraviolet irradiation process, so that the main part wafer 2W is easily separated from the first support substrate 60.
  • the lower surface 45SB of the resin layer 45, the second surface 10SB of the imaging unit 10, and the lower surface 30SB of the terminal portion 30 are located on the same plane.
  • the external electrode 14 and the core wire electrode 32 are convex electrodes, both of them protrude from the plane including the lower surface 45SB of the resin layer 45.
  • the external electrode 14 or the core wire electrode 32 is a convex electrode, only the convex electrode projects from the plane including the lower surface 45SB of the resin layer 45.
  • the main wafer 2W is temporarily fixed to the second support substrate 61.
  • the adhesive layer 61A is provided on the base 61B.
  • the second support substrate 61 may have the same configuration as the first support substrate 60 or may have a different configuration.
  • the first upper surface 30SA1 of the terminal portion 30 is temporarily fixed to the second support substrate 61. Further, when the terminal portion 30 has substantially the same height as the image pickup portion 10, the first upper surface 30SA1 of the terminal portion 30 and the first surface 10SA of the image pickup portion 10 are temporarily fixed to the second support substrate 61. . That is, at least one of the first surface 10SA and the first upper surface 30SA1 is temporarily fixed to the second support substrate 61.
  • the wiring layer 20 including the wiring 21 that connects the external electrode 14 of the imaging unit 10 and the core wire electrode 32 of the terminal portion 30 and the insulating layer 22 (22A, 22B) is arranged.
  • the wiring layer disposing step S60 includes a film forming step of forming the conductor layer 21M to be the wiring 21 on the respective surfaces of the external electrode 14 and the core wire electrode 32.
  • the wiring 21 is formed into a film, the wiring 21 and the external electrode 14 and the core wire electrode 32 are brought into contact with each other without sandwiching other members, and are electrically connected. Therefore, the imaging device 1 is easy to manufacture, and the connection between the wiring 21 and the external electrode 14 and the core electrode 32 has a small electric resistance at the bonding interface and high reliability.
  • an insulating layer 22A having an opening H22 exposing the external electrode 14 and an opening H23 exposing the core wire electrode 32 is provided. Side surfaces of the convex external electrode 14 and the core wire electrode 32 are covered with the insulating layer 22A.
  • the external electrode 14 or the core wire electrode 32 is a convex electrode, only the side surface of the convex electrode is covered with the insulating layer 22A. That is, at least one of the side surface of the external electrode 14 and the side surface of the core wire electrode 32 is covered with the insulating layer 22A.
  • the wiring 21 is formed by forming the wiring 21.
  • the electrode 14 and the core wire electrode 32 can be regarded as an image pickup device in a contact state.
  • the conductor layer 21M is formed in the openings H22, H23 and the insulating layer 22A.
  • the conductor layer 21M is formed on the surface of the insulating layer 22A, the surface of the external electrode 14 exposed in the opening H22, and the surface of the core wire electrode 32 exposed in the opening H23 by sputtering or vapor deposition. To be done.
  • the conductor layer 21M is made of copper or aluminum.
  • the wiring 21 that connects the external electrode 14 and the core wire electrode 32 is produced by the patterning process of the conductor layer 21M.
  • an electroplating method may be used after forming the underlying conductive film and using a plating mask in which the pattern of the wiring 21 is an opening.
  • the electroplating method the underlying conductive film around the wiring 21 is removed after removing the plating mask.
  • the wiring layer 20 is manufactured by disposing the insulating layer 22B that covers the wiring 21.
  • the wiring layer 20 may be a multilayer wiring layer having two or more wirings 21.
  • the main part wafer 2W including the wiring layer 20 is separated into the main parts 2. Since the main part 2 is produced by dividing (cutting) the main part wafer 2W, the side surface of the resin layer 45 and the side surface of the wiring layer 20 are cut surfaces cut at the same time, and the upper surface 45SA of the resin layer 45. And the third surface 20SA (fourth surface 20SB) of the wiring layer 20 have the same outer dimensions.
  • the core wire 41 of the electric cable 40 is joined to the core wire terminal 31 of the terminal portion 30 of the main part 2.
  • the prism 15 is adhered to the first main surface 10SA with an adhesive 16.
  • the main wafer 2W to which the second support substrate 61 is bonded may be singulated, or before the singulated second support substrate 61 is separated.
  • the electric cable 40 may be joined to the terminal portion 30. Furthermore, the electric cable 40 may be joined to the terminal portion 30 before the individual wafer 2W is singulated.
  • the cutting step of dividing the main part wafer 2W into the main parts 2 is performed from after the wiring layer disposing step S60 to after the cable joining step S80.
  • the imaging device 1 of the present embodiment is easy to manufacture because a large number of main parts 2 are manufactured in a wafer state.
  • the main part 2 may be manufactured one by one.
  • the image pickup unit 10A which is a semiconductor unit of the image pickup apparatus 1A, is an image pickup device having a thickness H10 in which the first surface 10SA is a light receiving surface.
  • a cover glass or a prism may be adhered to the light receiving surface of the imaging unit 10A.
  • the terminal portion 30A has a second upper surface 30SA2 that faces the lower surface 30SB and is parallel to the first upper surface 30SA1.
  • the height H33 of the second upper surface 30SA2 from the lower surface 30SB is smaller than the height H31 of the first upper surface 30SA1.
  • a shield terminal 33 is provided on the second upper surface 30SA2, and a shield electrode 34 is provided on the lower surface 30SB.
  • the shield terminal 33 and the shield electrode 34 are connected by a through wiring or the like.
  • the electric cable 40A is a shielded cable having a core wire 41, a first coating layer 42 that covers the core wire 41, a shield wire 43 that covers the first coating layer 42, and a second coating layer 44 that covers the shield wire 43.
  • the core wire 41 is joined to the core wire terminal 31, and the shield wire 43 is joined to the shield terminal 33.
  • the shield wires 43 of the plurality of electric cables 40A are joined to one shield terminal 33 which is a common terminal.
  • the shield wires 43 of the plurality of electric cables 40A may be joined to the respective shield terminals 33.
  • the length ⁇ 30 from the first upper surface 30SA1 to the second upper surface 30SA2 is the sum ⁇ 40 of the thickness T42 of the first coating layer 42 and the thickness T43 of the shield wire 43. Is substantially the same (for example, more than 75% and less than 125%). That is, the terminal portion 30A is set according to the electric cable 40A. Furthermore, in other words, the length ⁇ 30 from the first upper surface 30SA1 to the second upper surface 30SA2 is set to a distance at which the shield wire 43 also contacts the shield terminal 33 when the core wire 41 contacts the core terminal 31. ing.
  • the core wire 41 and the shield wire 43 of the electric cable 40A which is a shielded cable, can be easily joined to the terminal portion 30A.
  • the imaging device 1B and the method of manufacturing the imaging device 1B according to the present embodiment are similar to the imaging device 1 and the manufacturing method of the imaging device 1 and have the same effect, the same reference numeral is given to the component having the same function and described. Is omitted.
  • the image pickup section 10B in which the cover glass 12B is bonded to the light receiving surface 11SA of the image pickup element 11B orthogonal to the second surface 10SB is a semiconductor section. That is, the imaging unit 10B is arranged such that the direction of the optical axis O of the imaging element 11B is parallel to the third surface 20SA of the wiring layer 20.
  • the first surface 10SA and the second surface 10SB are side surfaces of the image pickup device 11B having a smaller area than the light receiving surface 11SA.
  • facing surface 11SB facing the light receiving surface 11SA of the imaging unit 10B may be in contact with the side surface of the terminal unit 30 in order to facilitate the positioning between the terminal unit 30 and the imaging unit 10B.
  • the image pickup apparatus 1B is a vertical type image pickup apparatus that does not include a prism, but has the same effect as the horizontal type image pickup apparatus 1 and the like. Further, the vertically-placed image pickup device 1B is shorter and smaller than the horizontally-placed image pickup device 1.
  • the semiconductor device 1C and the method of manufacturing the semiconductor device 1C according to the present embodiment are similar to the imaging device 1 and the method of manufacturing the imaging device 1 and have the same effect, and therefore, components having the same function are denoted by the same reference numerals and described. Is omitted.
  • a semiconductor device 1C shown in FIG. 18 has a semiconductor section 10C.
  • the semiconductor unit 10 processes signals input/output by passing through the terminal 42.
  • an AD conversion circuit for example, an AD conversion circuit, a memory, a transmission output circuit, a filter circuit, a thin film capacitor, a thin film resistor, a thin film, which performs primary processing on an image pickup signal output from an image pickup device (not shown) and processes a control signal for controlling the image pickup device. It is an inductor.
  • the semiconductor device 1C has high reliability because the wiring 21 is formed on the surface of the external electrode 14 of the semiconductor unit 10 and heat and stress are not applied to the semiconductor unit 10. Moreover, since the main part 2 to which the electric cable 40 is joined is manufactured by the wafer process, the manufacturing is easy.
  • the semiconductor device having the semiconductor section is not limited to the image pickup apparatus having the image pickup section.
  • various semiconductor devices including an AD conversion circuit for an operation signal in the operation unit 91, a memory, a transmission output circuit, a filter circuit, a thin film capacitor, a thin film resistor, and a terminal unit to which an electric cable of a thin film inductor is joined.
  • An endoscope system 8 including the endoscope 9 of the present embodiment shown in FIG. 19 includes the endoscope 9, a processor 80, a light source device 81, and a monitor 82.
  • the endoscope 9 has an insertion section 90, an operation section 91, and a universal cord 92, and the imaging signal output from the imaging device 1 or the like arranged at the distal end portion 90A of the insertion section 90 is inserted into the insertion section 90. It is transmitted by the electric cable 40.
  • the universal cord 92 extending from the operation unit 91 is connected to the processor 80 and the light source device 81 via the connector 93.
  • the endoscope 9 has the insertion portion 90 inserted into the body cavity of the subject, captures an in-vivo image of the subject, and outputs an image signal.
  • the insertion portion 90 is provided continuously with the distal end portion 90A in which the imaging device 1 is arranged, the bendable bending portion 90B continuously provided at the proximal end portion of the distal end portion 90A, and the proximal end portion of the bending portion 90B. And a flexible portion 90C.
  • the bending section 90B is bent by the operation of the operation section 91.
  • the endoscope 9 may be a rigid endoscope, and its application may be medical or industrial.
  • an operation portion 91 provided with various buttons for operating the endoscope 9 is arranged.
  • the light source device 81 has, for example, a white LED.
  • the illumination light emitted from the light source device 81 passes through the universal cord 92 and a light guide (not shown) that passes through the insertion portion 90 and is guided to the tip 90A to illuminate the subject.
  • the imaging device 1 is highly reliable and small, and therefore the endoscope 9 is highly reliable and has a small diameter.
  • the endoscopes 9A to 9C equipped with the imaging devices 1A, 1B or the semiconductor device 1C have the effects of the imaging devices 1A, 1B or the semiconductor device 1C in addition to the effects of the endoscope 9. There is also no.
  • Imaging part (semiconductor part) 10SA... First surface 10SB... Second surface 11... Imaging element 11B... Imaging element 11SA... Light receiving surface 11SB... Opposing surface 12... Cover glass 13... Light receiving part 14... External electrode 15... Prism 20... Wiring layer 20SA... Third surface 20SB... Fourth surface 21... Wiring 21M... Conductor layer 22A... Insulating layer 22A 22B... Insulating layer 30... Terminal part 30SA1... 1st upper surface 30SA2... 2nd upper surface 30SB... Lower surface 31... Core wire terminal 32... Core wire electrode 33... Shield Terminal 34... Shield electrode 40... Electric cable 41...
  • Core wire 42 First coating layer 43... Shield wire 44... Second coating layer 45... Resin layer 45SA... Upper surface 45SB... Lower surface 60... First support substrate 60A... Adhesive layer 60B... Substrate 61... Second support substrate 61A... Adhesive layer 61B... Substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Surgery (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Medical Informatics (AREA)
  • Nuclear Medicine, Radiotherapy & Molecular Imaging (AREA)
  • Biomedical Technology (AREA)
  • Molecular Biology (AREA)
  • Animal Behavior & Ethology (AREA)
  • General Health & Medical Sciences (AREA)
  • Public Health (AREA)
  • Veterinary Medicine (AREA)
  • Biophysics (AREA)
  • Heart & Thoracic Surgery (AREA)
  • Radiology & Medical Imaging (AREA)
  • Pathology (AREA)
  • Optics & Photonics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Endoscopes (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

撮像装置１は、第１面１０ＳＡと第２面１０ＳＢとを有し前記第２面１０ＳＢに外部電極１４が配設されている撮像部１０と、第１の上面３０ＳＡ１に芯線端子３１が配設されており下面３０ＳＢに芯線電極３２が配設されている端子部３０と、絶縁層２２と配線２１とを含み第３面２０ＳＡが前記第２面１０ＳＢおよび前記下面３０ＳＢと当接している配線層２０と、前記第３面２０ＳＡに配設され、外寸が前記配線層２０と同じであり、前記撮像部１０および前記端子部３０を、第１面１０ＳＡおよび第１の上面３０ＳＡ１を覆わない状態において固定している樹脂層４５と、芯線４１が前記芯線端子３１に接合されている電気ケーブル４０と、を具備し、前記配線２１が、前記外部電極１４および前記芯線電極３２と当接している。

Description

半導体装置、内視鏡、および、半導体装置の製造方法
　本発明は、半導体部と電気ケーブルとが接続されている半導体装置、半導体部と電気ケーブルとが接続されている半導体装置を含む内視鏡、および、半導体部と電気ケーブルとが接続されている半導体装置の製造方法に関する。
　内視鏡の先端部の細径化のために、超小型の撮像素子を具備する撮像装置の開発が進められている。撮像素子には、駆動信号を供給したり撮像信号を出力したりする外部電極が配設されている。外部電極に電気ケーブルを接合すると、接合時の熱または応力によって撮像素子を損傷するおそれがある。
　国際公開第２０１７／０３７８２８号には、撮像素子が配線板に接合され、配線板に電気ケーブルが接合されている撮像装置が開示されている。
　しかし、撮像素子を配線板に接合するときの熱または応力によって撮像素子が損傷したり、撮像装置の信頼性が低下したりするおそれがある。また、撮像素子を配線板に接合すると、撮像装置の厚さが厚くなり、内視鏡の先端部の細径化を損なうおそれがある。さらに、複数の撮像装置を作製する場合に、撮像素子を配線板に接合する工程は装置毎に行われるため、繁雑であった。
　なお、日本国特開２００７－２８７８０１号公報には、多層配線基板に、発光素子デバイスを含む半導体モジュールと、ＬＳＩとを実装したハイブリット回路装置が開示されている。発光素子デバイスには光ファイバが配設されている。
国際公開第２０１７／０３７８２８号 特開２００７－２８７８０１号公報
　本発明の実施形態は、信頼性が高く小型の半導体装置、信頼性が高く細径の内視鏡、および、信頼性が高く小型の半導体装置を容易に製造できる半導体装置の製造方法を提供することを目的とする。
　実施形態の半導体装置は、第１面と前記第１面に対向する第２面とを有し、前記第２面に外部電極が配設されている半導体部と、第１の上面と前記第１の上面に対向する下面とを有し、前記第１の上面に芯線端子が配設されており、前記下面に芯線電極が配設されている端子部と、第３面と、前記第３面に対向する第４面とを有し、絶縁層と配線とを含み、前記第３面が前記半導体部の前記第２面および前記端子部の前記下面と当接している配線層と、前記配線層の前記第３面に配設され、外寸が前記配線層と同じであり、前記半導体部および前記端子部を、前記第１面および前記第１の上面を覆わない状態において固定している樹脂層と、芯線を有し、前記芯線が前記芯線端子に接合されている電気ケーブルと、を具備し、前記配線が、前記外部電極および前記芯線電極と当接している。
　実施形態の内視鏡は、半導体装置を含み、前記半導体装置は、第１面と、前記第１面に対向する第２面とを有し、前記第２面に外部電極が配設されている半導体部と、第１の上面と、前記第１の上面に対向する下面とを有し、前記第１の上面に芯線端子が配設されており、前記下面に芯線電極が配設されている端子部、と第３面と、前記第３面に対向する第４面とを有し、絶縁層と配線とを含み、前記第３面が前記半導体部の前記第２面および前記端子部の前記下面と当接している配線層と、前記配線層の前記第３面に配設され、外寸が前記配線層と同じであり、前記半導体部および前記端子部を、前記第１面および前記第１の上面を覆わない状態において固定している樹脂層と、芯線を有し、前記芯線が前記芯線端子に接合されている電気ケーブルと、を具備し、前記配線が、前記外部電極および前記芯線電極と当接している。
　実施形態の半導体装置の製造方法は、第１面と前記第１面に対向する第２面を有し前記第２面に１以上の外部電極が配設されている複数の半導体部と、第１の上面と前記第１の上面に対向する下面とを有し前記第１の上面に芯線端子が配設されており前記下面に芯線電極が配設されている複数の端子部とが、第１のサポート基板に仮固定される第１仮固定工程と、前記第１のサポート基板の前記複数の半導体部および前記複数の端子部の周囲に、樹脂が配設され、前記半導体部と前記端子部とが前記樹脂によって固定される樹脂配設工程と、前記第１のサポート基板から、前記複数の半導体部と前記複数の端子部と前記樹脂とを含む要部が分離される第１分離工程と、前記要部の、前記複数の半導体部の前記第１面および前記複数の端子部の前記第１の上面の少なくともいずれかが、第２のサポート基板に仮固定される第２仮固定工程と、前記複数の半導体部の前記外部電極と前記複数の端子部の芯線電極とを接続する配線を含む複数の配線層が配設される配線層配設工程と、前記第２のサポート基板から、前記配線層を含む前記複数の要部が分離される第２分離工程と、芯線を有する電気ケーブルの前記芯線が前記芯線端子に接合されるケーブル接合工程と、を具備する。
　　本発明の実施形態によれば、信頼性が高く小型の半導体装置、信頼性が高く細径の内視鏡、および、信頼性が高く小型の半導体装置を容易に製造できる半導体装置の製造方法を提供できる。
第１実施形態の半導体装置の斜視図である。 第１実施形態の半導体装置の断面図である。 第１実施形態の半導体装置の分解図である。 第１実施形態の半導体装置の製造方法のフローチャートである。 第１実施形態の半導体装置の製造方法を説明するための断面図である。 第１実施形態の半導体装置の製造方法を説明するための断面図である。 第１実施形態の半導体装置の製造方法を説明するための断面図である。 第１実施形態の半導体装置の製造方法を説明するための断面図である。 第１実施形態の半導体装置の製造方法を説明するための断面図である。 第１実施形態の半導体装置の製造方法を説明するための断面図である。 第１実施形態の半導体装置の製造方法を説明するための断面図である。 第１実施形態の半導体装置の製造方法を説明するための平面図である。 第１実施形態の半導体装置の製造方法を説明するための断面図である。 第１実施形態の半導体装置の製造方法を説明するための断面図である。 第２実施形態の半導体装置の分解図である。 第２実施形態の半導体装置の一部分の分解断面図である。 第３実施形態の半導体装置の断面図である。 第４実施形態の半導体装置の断面図である。 第５実施形態の内視鏡の斜視図である。
＜第１実施形態＞
　図１、図２および図３に示す本実施形態の半導体装置は、内視鏡９の先端部９０Ａに配設される撮像装置１である（図１９参照）。
　横置き型の撮像装置１は、半導体部である撮像部１０と、プリズム１５と、配線層２０と、端子部３０と、電気ケーブル４０と、樹脂層４５と、を具備する。
　なお、以下の説明において、各実施の形態に基づく図面は、模式的なものであり、各部分の厚さと幅との関係、夫々の部分の厚さの比率および相対角度などは現実のものとは異なることに留意すべきであり、図面の相互間においても互いの寸法の関係や比率が異なる部分が含まれている場合がある。また、一部の構成要素の図示および符号の付与を省略する場合がある。
　撮像部１０は、半導体素子である撮像素子１１とカバーガラス１２とを含む。撮像部１０は、第１面１０ＳＡと、第１面１０ＳＡに対向する第２面１０ＳＢと、を有する直方体である。第２面１０ＳＢには、複数の外部電極１４が配設されている。撮像素子１１の受光部１３と外部電極１４とは、例えば、第１の貫通配線１１Ｘ（図５参照）を経由することによって接続されている。撮像素子１１は、表面照射型イメージセンサまたは裏面照射型イメージセンサのいずれでもよい。
　プリズム１５は、第１面１０ＳＡに透明な接着剤１６を用いて接着されている。
　端子部３０は、第１の上面３０ＳＡ１と、第１の上面３０ＳＡ１に対向する下面３０ＳＢとを有する。端子部３０は、第１の上面３０ＳＡ１に複数の芯線端子（接続用ランド）３１が配設されており、下面３０ＳＢに複数の芯線電極３２が配設されているケーブル接続部である。芯線端子３１と芯線電極３２とは、例えば第２の貫通配線３０Ｘ（図５参照）を経由することによって接続されている。
　配線層２０は、第３面２０ＳＡと、第３面２０ＳＡに対向する第４面２０ＳＢとを有し、絶縁層２２（２２Ａ、２２Ｂ）と配線２１とを含む配線部材である。第３面２０ＳＡは、撮像部１０の第２面１０ＳＢおよび端子部３０の下面３０ＳＢと当接している。
　電気ケーブル４０は、芯線４１と、芯線４１を覆う第１被覆層４２と、を有する。芯線４１は、端子部３０の芯線端子３１に例えば半田を用いて接合されている。芯線４１は、芯線端子３１、第２の貫通配線３０Ｘ、芯線電極３２、配線２１および外部電極１４を経由することによって受光部１３と電気的に接続されている。
　樹脂層４５は、配線層２０の第３面２０ＳＡに配設され、撮像部１０および端子部３０を固定している。樹脂層４５は、撮像部１０と端子部３０とを一体に保持した状態において配線層２０に固定する固定部である。樹脂層４５の厚さＨ４５は、端子部３０の厚さ（第１の上面３０ＳＡ１から下面３０ＳＢまでの長さＨ３１）よりも薄い。このため、端子部３０の芯線端子３１は、樹脂層４５に覆われていない。すなわち、樹脂層４５の上面４５ＳＡは第１面１０ＳＡおよび第１の上面３０ＳＡ１よりも低い位置（第３面２０ＳＡに近い位置）にある。
　樹脂層４５の上面４５ＳＡは配線層２０の第３面２０ＳＡと平行であり、両者の外寸は同じである。言い替えれば、樹脂層４５の側面と配線層の側面は、同一平面上にある。
　撮像装置１では、配線層２０の配線２１が、外部電極１４および芯線電極３２と当接している。配線層２０は、撮像部１０および端子部３０が固定された樹脂層４５に配設された再配線層である。配線２１のうち少なくとも外部電極１４および芯線電極３２と当接している領域は、外部電極１４および芯線電極３２の表面に成膜された導電材料からなる。例えば、配線２１は、外部電極１４および芯線電極３２に成膜された、銅スパッタ膜、または、下地導電膜および電気銅めっき膜からなる。
　撮像装置１では、配線２１が成膜されることによって、配線２１と外部電極１４および芯線電極３２とは、当接した状態で接合されることによって、電気的に接続される。このため、撮像装置１は作製が容易で、かつ、配線２１と外部電極１４および芯線電極３２との接合信頼性が高い。
　撮像素子１１の外部電極１４に電気ケーブル４０を接合すると、接合時の熱または応力によって撮像素子を損傷するおそれがある。また、撮像素子１１を配線板に接合すると、撮像装置の厚さが厚くなる。
　撮像装置１では、撮像素子１１の外部端子１４は配線２１と当接しており、半田を用いて接合されていないため、半田溶融時の熱または応力によって撮像素子１１が損傷し、撮像装置１の信頼性が低下するおそれがない。また、撮像素子１１は、配線板ではなく、樹脂層４５に固定されているため、撮像装置１は厚さが薄く小型である。
＜撮像装置の製造方法＞
　図４のフローチャートに沿って撮像装置１の製造方法を説明する。
＜ステップＳ１０＞半導体部（撮像部）および端子部作製工程
　図示しないが、公知の半導体製造技術を用いて、シリコンウエハに複数の受光部１３等が配設されることによって撮像素子ウエハが作製される。撮像素子ウエハには、受光部１３の出力信号を１次処理したり、駆動制御信号を処理したりする周辺回路が形成されていてもよい。
　撮像素子ウエハの受光面に受光部１３を保護するガラスウエハが接着される。そして、第１の貫通配線１１Ｘを経由することによって受光部１３と接続された外部電極１４が裏面に配設される。ガラスウエハが接着された撮像素子ウエハを切断することによって、複数の撮像部１０（カバーガラス１２が接着された撮像素子１１）が作製される。
　端子部３０は、樹脂、セラミックまたはシリコン等を基体とする立体配線板である。端子部３０は、射出成形品に導電性パターンが形成された立体部品である成形回路部品（ＭＩＤ：Molded Interconnect Device）でもよい。芯線端子３１と芯線電極３２とは、表面配線を経由することによって接続されていてもよい。
＜ステップＳ２０＞第１仮固定工程
　図５に示すように、撮像部１０と端子部３０とが所定の配置状態において第１のサポート基板６０に仮固定される。
　第１のサポート基板６０は、基体６０Ｂに粘着層（仮固定層）６０Ａが配設されている。粘着層６０Ａは軟らかいため、外部電極１４および芯線電極３２が凸状電極の場合には、両者は粘着層６０Ａに埋め込まれた状態となる。後述するように、粘着層６０Ａは紫外線照射処理または加熱処理によって粘着力を消失する。
　なお、１つの第１のサポート基板６０に、複数の撮像部１０および複数の端子部３０が仮固定される。
＜ステップＳ３０＞樹脂配設工程
　図６に示すように、第１のサポート基板６０の撮像部１０および端子部３０の周囲の主面６０ＳＡに未硬化の樹脂層４５が配設される。樹脂層４５を硬化処理することによって、撮像部１０と端子部３０とが樹脂層４５によって固定された要部ウエハ２Ｗが作製される。
　例えば、未硬化のエポキシ樹脂が第１のサポート基板６０に配設されてから熱硬化処理が行われる。樹脂層４５は、撮像部１０の第１面１０ＳＡおよび端子部３０の第１の上面３０ＳＡ１を覆わない状態に配設される。なお、樹脂層４５が、撮像部１０の側面を完全に覆っていてもよい。
＜ステップＳ４０＞第１分離工程
　図７に示すように、第１のサポート基板６０から、複数の撮像部１０と複数の端子部３０とが樹脂層４５によって固定されている要部ウエハ２Ｗが分離される。例えば、紫外線照射処理によって粘着層６０Ａが粘着力を消失することによって、要部ウエハ２Ｗは簡単に第１のサポート基板６０から剥離される。
　なお、樹脂層４５の下面４５ＳＢと撮像部１０の第２面１０ＳＢと端子部３０の下面３０ＳＢとは同一平面上に位置している。外部電極１４および芯線電極３２が凸状電極の場合には、両者は樹脂層４５の下面４５ＳＢが含まれる平面から突出している。なお、外部電極１４または芯線電極３２が凸状電極の場合には、凸状電極だけが、樹脂層４５の下面４５ＳＢが含まれる平面から突出する。
＜ステップＳ５０＞第２仮固定工程
　図８に示すように、要部ウエハ２Ｗが、第２のサポート基板６１に仮固定される。第２のサポート基板６１は、基体６１Ｂに粘着層６１Ａが配設されている。第２のサポート基板６１は第１のサポート基板６０と同じ構成でもよいし、異なる構成でもよい。
　なお、端子部３０が撮像部１０よりも高さが高い場合には、端子部３０の第１の上面３０ＳＡ１が、第２のサポート基板６１に仮固定される。また、端子部３０が撮像部１０と略同じ高さの場合には、端子部３０の第１の上面３０ＳＡ１および撮像部１０の第１面１０ＳＡが、第２のサポート基板６１に仮固定される。すなわち、第１面１０ＳＡおよび第１の上面３０ＳＡ１の少なくともいずれかが、第２のサポート基板６１に仮固定される。
＜ステップＳ６０＞配線層配設工程
　撮像部１０の外部電極１４と端子部３０の芯線電極３２とを接続する配線２１および絶縁層２２（２２Ａ、２２Ｂ）を含む配線層２０が配設される。配線層配設工程Ｓ６０は、配線２１となる導体層２１Ｍを外部電極１４および芯線電極３２のそれぞれの表面に成膜する成膜工程を含む。
[0]　配線２１が成膜されることによって、配線２１と外部電極１４および芯線電極３２とは他部材を間にはさむことのない当接状態となり、電気的に接続される。このため、撮像装置１は作製が容易で、かつ、配線２１と外部電極１４および芯線電極３２との接合は、接合界面の電気抵抗が小さく、かつ、信頼性が高い。
　図９に示すように、外部電極１４が露出した開口Ｈ２２およびと芯線電極３２が露出した開口Ｈ２３のある絶縁層２２Ａが配設される。凸状の外部電極１４および芯線電極３２のそれぞれの側面は、絶縁層２２Ａに覆われる。なお、外部電極１４または芯線電極３２が凸状電極の場合には、凸状電極の側面だけが、絶縁層２２Ａに覆われる。すなわち、外部電極１４の側面および芯線電極３２の側面の少なくともいずれかは、絶縁層２２Ａに覆われる。
　逆に言えば、外部電極１４の側面および芯線電極３２の側面の少なくともいずれかは、絶縁層２２Ａに覆われている撮像装置であれば、配線２１が成膜されることによって、配線２１と外部電極１４および芯線電極３２とは当接状態になった撮像装置であると見なすことができる。
　図１０に示すように、成膜工程では、開口Ｈ２２、Ｈ２３および絶縁層２２Ａに導体層２１Ｍが成膜される。導体層２１Ｍが、絶縁層２２Ａの表面、開口Ｈ２２に露出している外部電極１４の表面、および、開口Ｈ２３に露出している芯線電極３２の表面に、スパッタ法または蒸着法を用いて成膜される。導体層２１Ｍは銅またはアルミニウム等からなる。
　図１１および図１２に示すように、導体層２１Ｍのパターニング処理によって、外部電極１４と芯線電極３２とを接続する配線２１が作製される。
　導体層２１Ｍの成膜には、下地導電膜を成膜後に、配線２１のパターンが開口となっているめっきマスクを用いて電気めっき法を用いてもよい。電気めっき法の場合には、めっきマスクを剥離後に配線２１の周囲の下地導電膜が除去される。
　さらに、配線２１を覆う絶縁層２２Ｂが配設されることによって、配線層２０が作製される。なお、配線層２０は２層以上の配線２１を有する多層配線層でもよい。
＜ステップＳ７０＞第２分離工程
　図１３に示すように、第２のサポート基板６１から、配線層２０を含む要部ウエハ２Ｗが分離される。
＜ステップＳ８０＞ケーブル接合工程
　図１４に示すように、配線層２０を含む要部ウエハ２Ｗが要部２に個片化される。要部２は要部ウエハ２Ｗの個片化（切断）によって作製されるため、樹脂層４５の側面と配線層２０の側面とは、同時に切断された切断面であり、樹脂層４５の上面４５ＳＡと配線層２０の第３面２０ＳＡ（第４面２０ＳＢ）とは外寸が同じである。
　電気ケーブル４０の芯線４１が、要部２の端子部３０の芯線端子３１に接合される。また、図示しないが、プリズム１５が接着剤１６を用いて第１の主面１０ＳＡに接着される。
　なお、第２分離工程Ｓ７０の前に、第２のサポート基板６１が接着された要部ウエハ２Ｗを、個片化してもよいし、個片化された第２のサポート基板６１を分離する前に電気ケーブル４０が端子部３０に接合されてもよい。さらに、要部ウエハ２Ｗの個片化前に、電気ケーブル４０が端子部３０に接合されてもよい。
　すなわち、要部ウエハ２Ｗを要部２に個片化する切断工程は、配線層配設工程Ｓ６０の後からケーブル接合工程Ｓ８０の後までの間に行われる。
　従来技術においては、複数の撮像装置を作製する場合に、撮像素子を配線板に接合する工程は装置毎に行われるため、繁雑であった。
　本実施形態の撮像装置１は、ウエハ状態において多数の要部２が作製されるため、製造が容易である。もちろん、１つずつ要部２を作製してもよい。
＜第２実施形態＞
　本実施形態の撮像装置１Ａ、および撮像装置１Ａの製造方法は、撮像装置１、および撮像装置１の製造方法と類似し同じ効果を有するため、同じ機能の構成要素には同じ符号を付し説明を省略する。
　図１５に示すように、撮像装置１Ａの半導体部である撮像部１０Ａは、第１面１０ＳＡが受光面である、厚さがＨ１０の撮像素子である。撮像部１０Ａの受光面にカバーガラスまたはプリズムが接着されていてもよい。
　また、端子部３０Ａは、下面３０ＳＢと対向しており第１の上面３０ＳＡ１と平行な状態の第２の上面３０ＳＡ２を有する。第２の上面３０ＳＡ２の下面３０ＳＢからの高さＨ３３は、第１の上面３０ＳＡ１の高さＨ３１よりも小さい。第２の上面３０ＳＡ２にはシールド端子３３が配設されており、下面３０ＳＢにはシールド電極３４が配設されている。図示しないが、シールド端子３３とシールド電極３４とは貫通配線等によって接続されている。
　電気ケーブル４０Ａは、芯線４１と、芯線４１を覆う第１被覆層４２と、第１被覆層４２を覆うシールド線４３と、シールド線４３を覆う第２被覆層４４とを有するシールドケーブルである。
　芯線４１は芯線端子３１と接合されており、シールド線４３はシールド端子３３と接合されている。複数の電気ケーブル４０Ａのシールド線４３が、共通端子である１つのシールド端子３３と接合されている。複数の電気ケーブル４０Ａのシールド線４３が、それぞれのシールド端子３３と接合されていてもよい。
　図１６に示すように、端子部３０Ａは第１の上面３０ＳＡ１から第２の上面３０ＳＡ２までの長さΔ３０が、第１被覆層４２の厚さＴ４２とシールド線４３の厚さＴ４３との和Δ４０と略同じ（例えば、７５％超１２５％未満）である。すなわち、端子部３０Ａは、電気ケーブル４０Ａにあわせて設定されている。さらに言い換えると、第１の上面３０ＳＡ１から第２の上面３０ＳＡ２までの長さΔ３０が、芯線４１が芯線端子３１に当接しているときに、シールド線４３もシールド端子３３に当接する距離に設定されている。
　撮像装置１Ａでは、シールドケーブルである電気ケーブル４０Ａの芯線４１およびシールド線４３を、端子部３０Ａに容易に接合できる。
＜第３実施形態＞
　本実施形態の撮像装置１Ｂ、および撮像装置１Ｂの製造方法は、撮像装置１、および撮像装置１の製造方法と類似し同じ効果を有するため、同じ機能の構成要素には同じ符号を付し説明を省略する。
　図１７に示すように、縦置き型の撮像装置１Ｂでは、第２面１０ＳＢと直交する撮像素子１１Ｂの受光面１１ＳＡにカバーガラス１２Ｂが接着されている撮像部１０Ｂが、半導体部である。つまり、撮像部１０Ｂは、撮像素子１１Ｂの光軸Ｏの方向が配線層２０の第３面２０ＳＡに対して平行となるように配置されている。また、第１面１０ＳＡおよび第２面１０ＳＢは、受光面１１ＳＡよりも面積の小さい撮像素子１１Ｂの側面である。
　なお、端子部３０と撮像部１０Ｂとの位置決めを容易にするために、端子部３０の側面に撮像部１０Ｂの受光面１１ＳＡに対向する対向面１１ＳＢが当接した状態であってもよい。
　撮像装置１Ｂは、プリズムを具備しない縦置き型の撮像装置であるが、横置き型の撮像装置１等と同じ効果を有する。また、縦置き型の撮像装置１Ｂは横置き型の撮像装置１よりも短小である。
＜第４実施形態＞
　本実施形態の半導体装置１Ｃ、および半導体装置１Ｃの製造方法は、撮像装置１、および撮像装置１の製造方法と類似し同じ効果を有するため、同じ機能の構成要素には同じ符号を付し説明を省略する。
　図１８に示す半導体装置１Ｃは、半導体部１０Ｃを有する。
　半導体部１０は、端子４２を経由することによって入出力する信号を処理する。例えば、図示しない撮像素子が出力する撮像信号を１次処理したり、撮像素子を制御する制御信号を処理したりするＡＤ変換回路、メモリ、伝送出力回路、フィルタ回路、薄膜コンデンサ、薄膜抵抗、薄膜インダクタである。
　半導体装置１Ｃは、半導体部１０の外部電極１４の表面に配線２１が成膜されているため、半導体部１０に熱および応力が印加されることがないため、信頼性が高い。また、ウエハプロセスによって電気ケーブル４０が接合される要部２が作製されるため、製造が容易である。
　すなわち、半導体部を有する半導体装置は、撮像部を有する撮像装置に限られるものではない。例えば、操作部９１での操作信号のＡＤ変換回路、メモリ、伝送出力回路、フィルタ回路、薄膜コンデンサ、薄膜抵抗、薄膜インダクタの電気ケーブルが接合された端子部を含む各種の半導体装置である。
＜第５実施形態＞
　図１９に示す本実施形態の内視鏡９を含む内視鏡システム８は、内視鏡９と、プロセッサ８０と、光源装置８１と、モニタ８２と、を具備する。内視鏡９は、挿入部９０と操作部９１とユニバーサルコード９２とを有し、挿入部９０の先端部９０Ａに配設された撮像装置１等が出力する撮像信号を、挿入部９０を挿通する電気ケーブル４０にて伝送する。操作部９１から延設されているユニバーサルコード９２は、コネクタ９３を経由することによってプロセッサ８０および光源装置８１に接続されている。
内視鏡９は、挿入部９０が被検体の体腔内に挿入されて、被検体の体内画像を撮影し画像信号を出力する。
　挿入部９０は、撮像装置１が配設されている先端部９０Ａと、先端部９０Ａの基端部に連設された湾曲自在な湾曲部９０Ｂと、湾曲部９０Ｂの基端部に連設された軟性部９０Ｃとによって構成される。湾曲部９０Ｂは、操作部９１の操作によって湾曲する。なお、内視鏡９は硬性鏡であってもよいし、その用途は医療用でも工業用でもよい。
　内視鏡９の挿入部９０の基端部には、内視鏡９を操作する各種ボタン類が設けられた操作部９１が配設されている。
　光源装置８１は、例えば、白色ＬＥＤを有する。光源装置８１が出射する照明光は、ユニバーサルコード９２および挿入部９０を挿通するライトガイド（不図示）を経由することによって先端部９０Ａに導光され、被写体を照明する。
　すでに説明したように、撮像装置１は信頼性が高く小型であるため、内視鏡９は信頼性が高く細径である。
　なお、撮像装置１Ａ、１Ｂ、または半導体装置１Ｃを具備する内視鏡９Ａ～９Ｃが、内視鏡９の効果に加えて撮像装置１Ａ、１Ｂ、または半導体装置１Ｃの効果を有することは言うまでも無い。
　本発明は上述した実施形態等に限定されるものではなく、本発明の要旨を変えない範囲において、種々の変更、改変、組み合わせ等ができる。
１、１Ａ、１Ｂ・・・撮像装置
１Ｃ・・・半導体装置
２・・・要部
８・・・内視鏡システム
９・・・内視鏡
１０・・・撮像部（半導体部）
１０ＳＡ・・・第１面
１０ＳＢ・・・第２面
１１・・・撮像素子
１１Ｂ・・・撮像素子
１１ＳＡ・・・受光面
１１ＳＢ・・・対向面
１２・・・カバーガラス
１３・・・受光部
１４・・・外部電極
１５・・・プリズム
２０・・・配線層
２０ＳＡ・・・第３面
２０ＳＢ・・・第４面
２１・・・配線
２１Ｍ・・・導体層
２２Ａ・・・絶縁層
２２Ａ、２２Ｂ・・・絶縁層
３０・・・端子部
３０ＳＡ１・・・第１の上面
３０ＳＡ２・・・第２の上面
３０ＳＢ・・・下面
３１・・・芯線端子
３２・・・芯線電極
３３・・・シールド端子
３４・・・シールド電極
４０・・・電気ケーブル
４１・・・芯線
４２・・・第１被覆層
４３・・・シールド線
４４・・・第２被覆層
４５・・・樹脂層
４５ＳＡ・・・上面
４５ＳＢ・・・下面
６０・・・第１のサポート基板
６０Ａ・・・粘着層
６０Ｂ・・・基体
６１・・・第２のサポート基板
６１Ａ・・・粘着層
６１Ｂ・・・基体

Claims (9)

  1. 　第１面と、前記第１面に対向する第２面とを有し、前記第２面に外部電極が配設されている半導体部と、
    　第１の上面と、前記第１の上面に対向する下面とを有し、前記第１の上面に芯線端子が配設されており、前記下面に芯線電極が配設されている端子部と、
    　第３面と、前記第３面に対向する第４面とを有し、絶縁層と配線とを含み、前記第３面が前記半導体部の前記第２面および前記端子部の前記下面と当接している配線層と、
    　前記配線層の前記第３面に配設され、外寸が前記配線層と同じであり、前記半導体部および前記端子部を、前記第１面および前記第１の上面を覆わない状態において固定している樹脂層と、
    　芯線を有し、前記芯線が前記芯線端子に接合されている電気ケーブルと、を具備し、
    　前記配線が、前記外部電極および前記芯線電極と当接していることを特徴とする半導体装置。
  2. 　前記端子部が、前記下面と対向している第２の上面を有し、前記樹脂層によって覆われていない前記第２の上面にシールド端子が配設されており、前記下面にシールド電極が配設されており、
    　前記電気ケーブルが、前記芯線を覆う第１被覆層と、前記第１被覆層を覆うシールド線と、前記シールド線を覆う第２被覆層とを有し、前記シールド線が前記シールド端子と接合されており、
    　前記第１の上面から前記第２の上面までの長さが、前記第１被覆層の厚さと前記シールド線の厚さとの和と略同じであることを特徴とする請求項１に記載の半導体装置。
  3. 　前記半導体部が、カバーガラスが接着されている撮像素子であることを特徴とする請求項１または請求項２に記載の半導体装置。
  4. 　前記撮像素子は光軸方向が前記第３面に対して平行となるように配置されていることを特徴とする請求項３に記載の半導体装置。
  5. 　前記外部電極の側面または前記芯線電極の側面の少なくともいずれかが、前記絶縁層に覆われていることを特徴とする請求項１から請求項４のいずれか１項に記載の半導体装置。
  6. 　前記配線のうち少なくとも前記外部電極または前記芯線電極と当接している領域は、前記外部電極または前記芯線電極の表面に成膜された導電材料からなることを特徴とする請求項１から請求項５のいずれか１項に記載の半導体装置。
  7. 　請求項１から請求項６のいずれか１項に記載の半導体装置を含むことを特徴とする内視鏡。
  8. 　第１面と前記第１面に対向する第２面とを有し前記第２面に１以上の外部電極が配設されている複数の半導体部と、第１の上面と前記第１の上面に対向する下面とを有し前記第１の上面に芯線端子が配設され前記下面に芯線電極が配設されている複数の端子部とが、第１のサポート基板に仮固定される第１仮固定工程と、
    　前記第１のサポート基板の前記複数の半導体部および前記複数の端子部の周囲に、樹脂が配設され、前記半導体部と前記端子部とが前記樹脂によって固定される樹脂配設工程と、
    　前記第１のサポート基板から、前記複数の半導体部と前記複数の端子部と前記樹脂とを含む要部ウエハが分離される第１分離工程と、
    　前記要部ウエハの、前記複数の半導体部の前記第１面および前記複数の端子部の前記第１の上面の少なくともいずれかが、第２のサポート基板に仮固定される第２仮固定工程と、
    　前記複数の半導体部の前記外部電極と前記複数の端子部の前記芯線電極とを接続する配線を含む複数の配線層が配設される配線層配設工程と、
    　前記第２のサポート基板から、前記配線層を含む前記要部ウエハが分離される第２分離工程と、
    　芯線を有する電気ケーブルの前記芯線が前記芯線端子に接合されるケーブル接合工程と、を具備することを特徴とする半導体装置の製造方法。
  9. 　前記配線層配設工程が、前記配線を前記外部電極および前記芯線電極の表面に成膜する成膜工程を含むことを特徴とする請求項８に記載の半導体装置の製造方法。
PCT/JP2018/044530 2018-12-04 2018-12-04 半導体装置、内視鏡、および、半導体装置の製造方法 WO2020115813A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP2018/044530 WO2020115813A1 (ja) 2018-12-04 2018-12-04 半導体装置、内視鏡、および、半導体装置の製造方法
US17/336,499 US12033975B2 (en) 2018-12-04 2021-06-02 Semiconductor device, endoscope, and method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2018/044530 WO2020115813A1 (ja) 2018-12-04 2018-12-04 半導体装置、内視鏡、および、半導体装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/336,499 Continuation US12033975B2 (en) 2018-12-04 2021-06-02 Semiconductor device, endoscope, and method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
WO2020115813A1 true WO2020115813A1 (ja) 2020-06-11

Family

ID=70973852

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2018/044530 WO2020115813A1 (ja) 2018-12-04 2018-12-04 半導体装置、内視鏡、および、半導体装置の製造方法

Country Status (2)

Country Link
US (1) US12033975B2 (ja)
WO (1) WO2020115813A1 (ja)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001016486A (ja) * 1999-06-25 2001-01-19 Toshiba Corp 固体撮像素子モジュール
JP2005317887A (ja) * 2004-04-28 2005-11-10 Advanced Chip Engineering Technology Inc イメージセンサモジュールの構造及びウェハレベルパッケージを製造する方法
JP2013215309A (ja) * 2012-04-05 2013-10-24 Olympus Corp 内視鏡
JP2014164110A (ja) * 2013-02-25 2014-09-08 Rohm Co Ltd 光通信モジュールおよびその製造方法
WO2017037828A1 (ja) * 2015-08-31 2017-03-09 オリンパス株式会社 内視鏡、電子ユニットおよび電子ユニットの製造方法
WO2018186163A1 (ja) * 2017-04-06 2018-10-11 オリンパス株式会社 撮像ユニット、および内視鏡

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4865267B2 (ja) * 2005-07-14 2012-02-01 富士フイルム株式会社 固体撮像装置及び内視鏡
JP2007287801A (ja) 2006-04-13 2007-11-01 Sony Corp 電気・光混載三次元半導体モジュール及びハイブリット回路装置並びに携帯型電話機
JP5302138B2 (ja) 2009-08-31 2013-10-02 オリンパスメディカルシステムズ株式会社 撮像装置及び電子内視鏡
CN107210306B (zh) * 2015-01-23 2020-07-14 奥林巴斯株式会社 摄像装置和内窥镜
KR101982040B1 (ko) 2016-06-21 2019-05-24 삼성전기주식회사 팬-아웃 반도체 패키지
JP6393018B1 (ja) 2017-04-06 2018-09-19 オリンパス株式会社 撮像ユニット、および内視鏡

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001016486A (ja) * 1999-06-25 2001-01-19 Toshiba Corp 固体撮像素子モジュール
JP2005317887A (ja) * 2004-04-28 2005-11-10 Advanced Chip Engineering Technology Inc イメージセンサモジュールの構造及びウェハレベルパッケージを製造する方法
JP2013215309A (ja) * 2012-04-05 2013-10-24 Olympus Corp 内視鏡
JP2014164110A (ja) * 2013-02-25 2014-09-08 Rohm Co Ltd 光通信モジュールおよびその製造方法
WO2017037828A1 (ja) * 2015-08-31 2017-03-09 オリンパス株式会社 内視鏡、電子ユニットおよび電子ユニットの製造方法
WO2018186163A1 (ja) * 2017-04-06 2018-10-11 オリンパス株式会社 撮像ユニット、および内視鏡

Also Published As

Publication number Publication date
US20210288023A1 (en) 2021-09-16
US12033975B2 (en) 2024-07-09

Similar Documents

Publication Publication Date Title
US20180070799A1 (en) Imaging device, endoscope system, and method of manufacturing imaging device
JP5926890B2 (ja) 配線板、配線板の製造方法、および撮像装置
US9509890B2 (en) Solid image pickup apparatus
WO2015045616A1 (ja) 撮像ユニットおよび内視鏡装置
US10924640B2 (en) Image pickup module and endoscope including image pickup module in which bonding junction between image pickup portion and signal cable is resin-sealed by curable resin
WO2018092318A1 (ja) 内視鏡用撮像モジュール、および内視鏡
US11000184B2 (en) Image pickup module, fabrication method for image pickup module, and endoscope
WO2019138737A1 (ja) 内視鏡用撮像装置、内視鏡、および、内視鏡用撮像装置の製造方法
JP2011045173A (ja) 集合ケーブル、電子回路モジュールおよび撮像装置
US10930696B2 (en) Image pickup unit, endoscope, and method for manufacturing image pickup unit
JP6431698B2 (ja) 撮像ユニット、ケーブル付き配線板、およびケーブル付き配線板の製造方法
WO2018092234A1 (ja) 光モジュール、撮像モジュールおよび内視鏡
JP2014108282A (ja) 撮像装置、内視鏡及び撮像装置の製造方法
WO2020115813A1 (ja) 半導体装置、内視鏡、および、半導体装置の製造方法
US20230291988A1 (en) Image pickup unit, method of manufacturing image pickup unit, and endoscope
US20230353853A1 (en) Image pickup unit and endoscope
US20210250473A1 (en) Image pickup apparatus, endoscope and method for manufacturing image pickup apparatus
WO2021260863A1 (ja) 電子モジュール、電子モジュールの製造方法および内視鏡
US10888217B2 (en) Imaging module applicable to head-swing endoscope
US11876107B2 (en) Image pickup apparatus for endoscope and endoscope
WO2022264337A1 (ja) 撮像ユニット、および、内視鏡
JP7149489B2 (ja) 固体撮像装置
US20210109337A1 (en) Image pickup apparatus, endoscope, and method for manufacturing image pickup apparatus
JP2019047300A (ja) 撮像モジュール及びハーネスユニット
WO2021149177A1 (ja) 撮像装置、内視鏡、および撮像装置の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18942006

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18942006

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP