WO2020199064A1

WO2020199064A1 - Chip package, terminal device, and preparation method

Info

Publication number: WO2020199064A1
Application number: PCT/CN2019/080703
Authority: WO
Inventors: 罗立德; 郭健炜; 胡骁; 张弛
Original assignee: 华为技术有限公司
Priority date: 2019-03-30
Filing date: 2019-03-30
Publication date: 2020-10-08
Also published as: CN113348551B; CN113348551A

Abstract

The present application provides a chip package, a terminal device, and a preparation method. The chip package comprises a substrate, a chip, and a first metal ring. In a specific configuration, the chip is disposed on a surface of the substrate and electrically connected to the substrate. The first metal ring is disposed on a surface of the substrate facing the chip, and surrounds the chip. The first metal ring, in a specific configuration, can be a closed ring, and can also be a ring having at least one opening. The technical solution uses the first metal ring to suppress thermal deformation of the substrate caused by high temperature, so as to reduce substrate deformation during a package reflow process, thereby effectively reducing warpage and deformation of a package structure, and improving PCB-level mounting yields.

Description

Chip packaging, terminal equipment and preparation method

Technical field

This application relates to the field of semiconductors, and in particular to a chip package, terminal equipment and manufacturing method.

Background technique

As the degree of chip integration continues to increase, the size of chips that integrate more functional requirements continues to increase, resulting in an increase in the size of the package substrate. However, due to the large difference in thermal expansion coefficient between the chip and the package substrate and the printed circuit board, this difference will cause large warpage of the chip package during the reflow process after the size of the package substrate increases, which seriously affects the board-level mounting Yield rate, on the other hand, leads to solder ball fatigue failure in the reliability test of high and low temperature cycling, which seriously reduces board-level reliability. This is an important problem currently faced by chip packaging.

At present, in order to reduce the warpage of the chip package, the core idea is to improve the structure of the package substrate. The package substrate chooses a material with a lower thermal expansion coefficient and uses a thicker core material of the package substrate, but this improvement will introduce other effects On the one hand, the thicker core layer material of the package substrate has a negative impact on signal integrity, and on the other hand, the material with a lower thermal expansion coefficient will cause a greater degree of thermal mismatch between the package substrate and the printed circuit board, resulting in solder balls Fatigue life is reduced.

Summary of the invention

The present application provides a chip package, a terminal device, and a manufacturing method to solve the problems of chip package warpage and low board-level reliability in the prior art.

In a first aspect, the present application provides a chip package that includes a substrate, a chip, and a first metal ring. When specifically installed, the chip is disposed on the surface of the substrate and is electrically connected to the substrate, The first metal ring is arranged on the surface of the substrate facing the chip and surrounds the chip. When specifically arranged, the first metal ring may be a closed ring, and the first metal ring may also have at least A gaped ring.

In the above technical solution, the first metal ring is used to suppress the thermal deformation of the substrate at high temperature, so as to reduce the deformation of the substrate during the package reflow process, thereby effectively reducing the warpage of the package structure and improving the board-level mounting Yield rate.

In a specific embodiment, the first metal ring may be arranged symmetrically with respect to the center of the chip. The first metal ring includes, but is not limited to, symmetry about the center of the chip.

In a specific embodiment, the chip package further includes a first insulating layer disposed on the surface of the substrate facing the chip, and the chip and the first metal ring are disposed on the Inside the first insulating layer. The first insulating layer just covers the chip and exposes the upper surface for subsequent operations with the chip.

In a specific embodiment, the chip package further includes a second metal ring. The second metal ring is arranged on the surface of the first insulating layer away from the substrate and surrounds the chip. The second metal ring may be a closed ring, and the second metal ring may also be a ring with at least one gap. By providing the first insulating layer and the second metal ring, the thermal deformation of the substrate during the packaging process can be further reduced.

In a specific embodiment, the second metal ring may be arranged symmetrically with respect to the center of the chip. The second metal ring includes, but is not limited to, symmetry about the center of the chip.

In a specific embodiment, the chip package further includes a passive device, the passive device is disposed on the surface of the substrate facing the chip, and is connected to the pins of the chip, and the passive device is connected to the chip. The substrate is electrically connected, and the passive device is arranged in the first insulating layer and located between the first metal ring and the chip.

In a specific embodiment, the number of the chips is multiple, the chip package further includes a third metal ring, the third metal ring is disposed on the surface of the substrate facing the chip, and is located on the multiple Between at least two of the chips. In order to further reduce the thermal deformation of the substrate during the packaging process.

In a specific embodiment, in order to solve the problem of low board-level reliability of the chip package in the prior art, the chip package further includes solder balls and a second insulating layer, and the second insulating layer is disposed on the back of the substrate. On the surface of the chip, the solder balls are arranged on the part of the substrate facing the surface of the substrate away from the chip and are arranged in the second insulating layer, and the height of the second insulating layer is perpendicular to The direction of the substrate is smaller than the height of the solder ball, and the thermal expansion coefficient of the second insulating layer is greater than the thermal expansion coefficient of the substrate. By using a second insulating layer with a thermal expansion coefficient greater than that of the substrate to encapsulate the solder balls, not only can the thermal mismatch between the substrate and the printed circuit board be reduced during the temperature cycle, but on the other hand, the solder ball stress can be buffered and the soldering can be enhanced. The anti-fatigue properties of the ball during the temperature cycling process, thereby the board-level reliability of the chip.

In a specific embodiment, the solder ball includes a first solder ball connected to the substrate and a second solder ball embedded on a side of the first solder ball facing away from the substrate. The solder balls are arranged in the second insulating layer, and the height of the second insulating layer is equal to the height of the first solder balls in a direction perpendicular to the substrate. Through the arrangement of two layers of solder balls, the special-shaped solder balls can be packaged on the substrate more conveniently and quickly.

In a specific embodiment, the chip package further includes a solder ball, a metal block, and a second insulating layer. The second insulating layer is disposed on the surface of the substrate facing away from the chip, and the metal block is disposed on the surface of the substrate. The substrate faces away from the surface of the chip and is located in the second insulating layer, the solder balls are fixed on the side of the metal block away from the substrate, and the height of the second insulating layer is perpendicular to the The direction of the substrate is equal to the height of the metal block. The height of the solder ball relative to the substrate can be adjusted conveniently and quickly by arranging a metal block between the solder ball and the substrate.

In a specific embodiment, the material of the second insulating layer is resin or molding compound, and can also be other insulating materials with a larger thermal expansion coefficient than the substrate.

In the second aspect, the application also provides a terminal device, including a chip package and a printed circuit board P(C)(B), the chip package is electrically connected to the P(C)(B), and the chip The package is a chip package as described in any technical solution. Since the warpage deformation of the chip packaging structure is small, and the board-level mounting yield is high, the product yield of the terminal device with the chip packaging is relatively high.

In a third aspect, the present application also provides a method for preparing a chip package, including: mounting a chip and a first metal ring on one side of a substrate, the first metal ring being disposed on the surface of the substrate facing the chip , And surrounding the chip, the first metal ring is a closed ring or a ring with at least one gap.

In the above technical solution, the first metal ring is mounted on the substrate, and the first metal ring is used to suppress the thermal deformation of the substrate at high temperature; the above-mentioned forming process has fewer steps, more convenient and quick preparation, and the formed chip package is warped The bending deformation is small.

In a specific embodiment, the first metal ring is symmetrical about the center of the chip.

In a specific embodiment, the manufacturing method of the chip package further includes: forming a first insulating layer on the surface of the substrate facing the chip, and the chip and the first metal ring are arranged in the first insulating layer;

A second metal ring is attached to the side of the first insulating layer facing away from the substrate. The second metal ring is a closed ring or a ring with at least one gap and surrounds the chip. Two mounting times further reduce the thermal deformation of the substrate during the packaging process.

In a specific embodiment, the second metal ring is symmetrical about the center of the chip.

In a specific embodiment, the manufacturing method of the chip package further includes: mounting a passive device on the surface of the substrate facing the chip, and the passive device is arranged in the first insulating layer and located in the first insulating layer. Between the metal ring and the chip.

In a specific embodiment, when the number of chips is multiple, the method for preparing the chip package further includes: before forming the first insulating layer, mounting a third metal ring on the surface of the substrate facing the chip , The third metal ring is located between at least two of the plurality of chips.

In a specific embodiment, the method for preparing the chip package further includes: implanting solder balls on the side of the substrate facing away from the chip; forming a second insulating layer on the side of the substrate facing away from the chip; The ball is arranged on the surface of the substrate opposite to the chip and facing the substrate in the second insulating layer. The height of the second insulating layer is smaller than the height of the second insulating layer in the direction perpendicular to the substrate. The height of the solder ball, the thermal expansion coefficient of the second insulating layer is greater than the thermal expansion coefficient of the substrate. In the above technical solution, the second insulating layer is formed on the side where the solder balls are planted on the substrate, and the thickness of the second insulating layer is limited to be smaller than the height of the solder balls, and the thermal expansion coefficient of the second insulating layer is defined to be greater than that of the substrate during material selection. The thermal expansion coefficient can reduce the thermal mismatch between the substrate and the printed circuit board during the temperature cycle while packaging the solder balls, buffer the solder ball stress, and enhance the fatigue resistance of the solder balls during the temperature cycle; the above forming process There are fewer procedures, more convenient and quick preparation, and the formed chip package has higher board-level reliability.

For solder balls of different sizes, shapes, and positions, the solder balls can be packaged through different processes. In a specific embodiment, the second substrate is formed on the side facing away from the chip with solder balls. The insulating layer specifically includes: implanting solder balls on the side of the substrate facing away from the chip; forming a second insulating layer on the side of the substrate facing away from the chip. Along a direction perpendicular to the substrate, the second insulating layer The thickness of the layer is less than the height of the solder ball, and the second insulating layer surrounds the solder ball. Through the above process, solder balls with lower size, shape and location requirements can be packaged.

In another specific embodiment, said forming a second insulating layer on the substrate with solder balls planted on the side facing away from the chip specifically includes: implanting first solder balls on the side of the substrate facing away from the chip; A second insulating layer is formed on the side of the substrate facing away from the chip. Along a direction perpendicular to the substrate, the height of the second insulating layer is greater than the height of the first solder balls; A second insulating layer and a first solder ball. The first solder ball exposes the ball-planting surface, and the ball-planting surface is flush with the surface of the second insulating layer facing away from the substrate; Solder balls. The special-shaped solder balls can be packaged on the substrate more conveniently and quickly through the two-layer solder ball preparation process.

In still another specific embodiment, the forming a second insulating layer on the substrate on which the solder balls are planted on the side facing away from the chip specifically includes: fixing a metal block on the side of the substrate facing away from the chip; A second insulating layer is formed on the side of the substrate away from the chip. Along the direction perpendicular to the substrate, the height of the second insulating layer is greater than the height of the metal block; the second insulating layer is thinned by a thinning process And a metal block, wherein the metal block exposes a ball-planting surface, and the ball-planting surface is flush with the side of the second insulating layer away from the substrate; and solder balls are implanted on the ball-planting surface. The height of the solder ball relative to the substrate can be adjusted conveniently and quickly by arranging a metal block between the solder ball and the substrate.

Description of the drawings

Fig. 1 is a schematic cross-sectional view of a chip package in the prior art;

2 is a schematic cross-sectional view of the chip package provided by this application;

3 is a schematic cross-sectional view of another chip package provided by this application;

Figures 4(a)-(d) are cross-sectional views of (A)-(A) in Figure 2;

Figure 5 is a cross-sectional view of (B)-(B) in Figure 3;

6 is a schematic cross-sectional view of another chip package provided by this application;

Figure 7 is a cross-sectional view (C)-(C) in Figure 6;

8 is a schematic cross-sectional view of another chip package provided by this application;

FIG. 9 is a top view of the chip package in FIG. 8;

10 is a schematic cross-sectional view of another chip package provided by this application;

FIG. 11 is a schematic cross-sectional view of still another chip package provided by this application;

FIG. 12 is a flow chart of the manufacturing method of the chip package provided by this application;

Figure 13(a)-(e) is a diagram of the manufacturing process of the chip package provided by this application;

Figure 14(a)-(d) is another process diagram of the solder ball package in the chip package provided by this application;

15(a)-(d) are diagrams of another manufacturing process of the solder ball package in the chip package provided by this application.

detailed description

In order to make the purpose, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings.

In view of the problems of chip package warpage and low board-level reliability in the prior art, the existing chip package changes the structure of the package substrate and the material of the package substrate, but this change causes an adverse effect on the solder balls. The chip package in the prior art is shown in FIG. 1. The chip package 500 is packaged with a plastic molding compound 530, the chip 510 located on the upper surface 521 of the substrate 520 is packaged with the plastic molding compound 531, and the solder balls 540 located on the lower surface 523 of the substrate 520 are packaged with plastic When the solder ball 540 is packaged, the lower surface 522 of the substrate 520 is provided with a solder resist layer 524. The plastic encapsulant 532 covers the solder resist layer 524, and an opening 533 is provided to expose the pad 523. The size of the opening 533 is larger than the solder ball. 540 size, so that the molding compound 532 will not directly contact the solder balls 540, thereby enhancing the resistance of the solder balls 540 to moisture and preventing the solder balls from being impacted and falling off. However, this chip package only directly enhances the protection directly physically. Significantly improve the thermal deformation of the chip package and enhance the board-level reliability. In the embodiments of the present application, the structure of the chip package and the structure and materials of the solder ball package are changed to improve the problems of chip package warpage and low board-level reliability in the prior art. In order to facilitate understanding, the following introduces several words mentioned in this application. Electrical connection refers to a way to achieve electrical connection between two components, such as welding, gold wire bonding, etc. The ring has a certain thickness and runs along the arc. The extended geometric figures can be closed or unclosed.

In the first aspect, this application provides a chip package, as shown in FIGS. 2, 3, 4, and 5. FIG. 3 shows a schematic cross-sectional view of a structure of the chip package, and FIG. 2 shows the chip package. Fig. 4 shows a schematic cross-sectional view of the structure of the first metal ring in the chip package, and Fig. 5 shows a schematic cross-sectional view of another structure of the first metal ring in the chip package. The chip package includes a substrate 100, and a chip 200 and solder balls 300. The chip 200 and solder balls 300 are located on both sides of the substrate 100. The chip 200 includes but is not limited to wire bond chips and flip chips. The number of chips 200 It can be one or more. As shown in FIG. 3, the number of chips 200 is two, and as shown in FIG. 2, the number of chips 200 is one, and when multiple chips are used, the chips can be of different types. chip. In the embodiments provided in the present application, two chips 200 are provided on the substrate 100, and the form of the two chips 200 described above is merely an example. As shown in FIGS. 3 and 2, a chip 200 and a first metal ring 400 are provided on one side of the substrate 100. The first metal ring 400 may be a closed ring or a ring with at least one gap. When the chip 200 is installed, the chip 200 It is electrically connected to the substrate 100, and the first metal ring 400 is fixed on the same side of the substrate 100. During the package reflow process, the first metal ring 400 is arranged on the substrate 100 to suppress the thermal deformation of the substrate 100 at high temperatures In order to reduce the amount of deformation of the substrate 100 during the reflow process of the package, the warpage deformation of the chip package can be effectively reduced, thereby improving the board-level mounting yield. The first metal ring 400 may be a ring structure, as shown in FIG. 4(a), the ring structure may be a ring closed structure, as shown in FIG. 4(b), the ring structure may also have a plurality of non-closed It is composed of an arc-shaped structure, and a gap is formed between two arc-shaped structures. The first metal ring 400 includes, but is not limited to, a ring-shaped closed structure and a separated structure with at least one gap. The first metal ring 400 may also have other structural forms. For example, the first metal ring 400 may be a frame-shaped structure arranged outside the chip 200. As shown in FIG. 4(c), the ring-shaped structure may be a closed frame-shaped structure. As shown in Figure 4(d), the ring structure can also be composed of multiple non-closed strip structures. Of course, the ring structure may also be a broken line structure provided on the substrate 100. In a specific configuration, the first metal ring 400 may be symmetrical about the center of the chip 200, and the first metal ring 400 includes but is not limited to be symmetrical about the center of the chip 200. As shown in Figure 4 (a)-Figure 4 (d), when there is only one chip 200, the ring structure is arranged around the chip 200, as shown in Figure 5, when there are two chips, the ring structure can be arranged Around the chip 200, and when there are multiple chips, the ring structure may be arranged around the chip 200, as shown in FIG. 6 and FIG. 7, the ring structure may also be arranged between two chips 200, FIG. Shows a schematic cross-sectional view of another structure of the chip package. FIG. 7 shows a schematic cross-sectional view of the structure of the middle ring structure of the chip package. The ring structure is composed of a first metal ring 400 and a third metal ring 450. The metal ring 400 includes an arc structure 410, an arc structure 420, an arc structure 430, and an arc structure 440. When specifically arranged, the third metal ring 450 is disposed on the surface of the substrate 100 facing the chip 200, and is located on the two chips 200 In between, the arc structure 410, the arc structure 420, the arc structure 440 and the third metal ring 450 cooperate to surround the chip 200 on the left, the arc structure 420, the arc structure 430, the arc structure 440 and the third metal ring The ring 450 cooperates to surround the chip 200 on the right. Of course, the first metal ring 400 includes but is not limited to the periphery of the chip 200 and the position between the chips 200. For example, the first metal ring 400 can be specifically set according to the warpage deformation of the chip package, and the warpage deformation of the package structure is relatively high. More first metal rings 400 are arranged in large positions, and a small number of first metal rings 400 are arranged in positions where the warpage deformation of the package structure is small, or even no first metal rings 400 are arranged.

Continuing to refer to Figures 3, 8 and 9, Figure 3 shows a schematic cross-sectional view of a structure of the chip package, Figure 8 shows a schematic cross-sectional view of another structure of the chip package, and Figure 9 shows a schematic cross-sectional view of another structure of the chip package. At the position on the substrate, in order to further reduce the thermal deformation of the substrate 100 during the packaging process, the chip package further includes a first insulating layer 500 and a second metal ring 700. The first insulating layer 500 is used to package the chip 200 and the first metal. Ring 400, the first insulating layer 500 is disposed on the surface of the substrate 100 facing the chip 200, the chip 200 and the first metal ring 400 are disposed inside the first insulating layer 500, the first insulating layer 500 just covers the chip 200, and the chip 200 is exposed Away from the upper surface of the substrate 100 to enable subsequent operations with the chip 200. When the first insulating layer 500 is specifically provided, the material of the first insulating layer 500 can be a plastic molding compound, a resin, or other insulating materials that meet the requirements. The specific material of the first insulating layer 500 is selected according to the actual situation of the chip package. In the specific configuration, the first insulating layer 500 completely covers the first metal ring 400 and surrounds the periphery of the chip 200, so as to realize the stable packaging of the chip 200. Continuing to refer to FIG. 3, FIG. 3 shows the positional relationship between the first insulating layer 500 and the first metal ring 400. When the first insulating layer 500 and the first metal ring 400 are specifically arranged, along the direction perpendicular to the substrate 100 The thickness of the first metal ring 400 is less than the thickness of the first insulating layer 500, so that the first metal ring 400 is completely wrapped in the first insulating layer 500, so as to prevent the arrangement of the first metal ring 400 from affecting other components of the chip package. The setting position and size will cause adverse effects. At the same time, the first metal ring 400 has the first insulating layer 500 on the side away from the substrate 100 so that the arrangement of the first metal ring 400 will not adversely affect the functions of other components of the chip package.

Continuing to refer to FIG. 8, FIG. 8 shows the positional relationship between the first insulating layer 500 and the second metal ring 700. The second metal ring 700 is provided on the side of the first insulating layer 500 away from the substrate 100, and the second metal The ring 700 surrounds the periphery of the chip 200. Refer to FIG. 9 together. FIG. 9 shows the positional relationship between the chip 200 and the second metal ring 700. The second metal ring 700 wraps the chip 200. Similar to the first metal ring 400, the second metal ring 700 can be a closed ring or a ring with at least one gap, the second metal ring 700 can be a ring structure, the ring structure can be a ring closed structure, or a non- The second metal ring 700 is composed of a plurality of closed arc-shaped structures, and a gap is formed between the two arc-shaped structures. The second metal ring 700 includes but is not limited to a ring-shaped closed structure and a separated structure with at least one gap. The second metal ring 700 may also have other structural forms. For example, the second metal ring 700 may be a frame-shaped structure arranged on the outside of the chip 200, or may be a broken line-shaped structure arranged on the substrate 100. In specific settings, the second metal ring 700 may be symmetrical about the center of the chip 200, and the second metal ring 700 includes but is not limited to being symmetrical about the center of the chip 200. In order to ensure the uniformity of the deformation of the substrate 100, thereby improving the stability of the chip packaging structure, during the reflow process of the package, the first metal ring 400 is arranged on the substrate 100 to suppress the thermal deformation of the substrate 100 at high temperatures, thereby reducing the The amount of deformation of the substrate 100 during the reflow process, and the second metal ring 700 disposed on the first insulating layer 500 can further suppress the thermal deformation of the substrate 100 at high temperatures, so as to further reduce the amount of deformation of the substrate 100 during the package reflow process, thereby It can better reduce the warpage of the chip package, thereby improving the board-level mounting yield. When the first metal ring 400 and the second metal ring 700 are specifically set, the material of the first metal ring 400 and the second metal ring 700 can be the same metal material, such as copper or stainless steel, and the first metal ring 400 and the second metal ring The material of 700 can also choose different metal materials. For example, the first metal ring 400 can choose copper, and the second metal ring 700 can choose stainless steel. Of course, the materials of the first metal ring 400 and the second metal ring 700 include but are not limited to For these two metals, you can also choose other materials that meet your needs.

Continuing to refer to FIG. 8, FIG. 8 shows a schematic cross-sectional view of the specific structure of the chip package. At least one passive device 800 connected to the pin of the chip 200 is also provided on the side of the substrate 100 facing the chip 200, and each passive device 800 is connected to the pins of at least one chip 200, the passive device 800 is electrically connected to the substrate 100, and the electrical connection may be gold wire bonding. In the specific configuration, the passive device 800 is disposed inside the first insulating layer 500, and Located between the first metal ring 400 and the chip 200, as shown in FIG. 8, the number of the chip 200 is two, and the two passive devices 800 are arranged on the outside of the two adjacent chips 200, and are located in the first Between the metal ring 400 and the chip 200. Of course, the form of the two chips 200 and the passive device 800 in FIG. 8 is only an example. When specifically setting the chip 200 and the passive device 800, the passive device 800 has n, n is an integer, and the chip 200 has m, m is an integer, and m≥1, m≥n. A passive device 800 can only be connected to the pins of one chip 200, and a passive device 800 can also be connected to the pins of multiple chips 200 at the same time. The specific number of passive devices 800 and the corresponding relationship with the chip 200 can be based on The size of the chip 200 and the chip package are determined. Continuing to refer to FIG. 8, the first insulating layer 500 completely wraps the chip 200 and the passive device 800, and the first metal ring 400 is located around the two chips 200. Refer to FIG. 9 together. FIG. 9 shows the second metal ring 700 in The position on the substrate 100, the second metal ring 700 is located around two adjacent chips 200, of course, the same as the first metal ring 400, the second metal ring 700 includes but is not limited to the chip 200 and the chip 200 For example, the second metal ring 700 can be specifically set according to the warpage deformation of the chip package. More second metal rings 700 are arranged at the positions where the warpage deformation of the packaging structure is larger, and the A small amount of the second metal ring 700 is arranged at a position with less deformation, even if the second metal ring 700 is not provided, and the first metal ring 400 and the second metal ring 700 may not be arranged oppositely, and may be arranged in a certain area The first metal ring 400 is provided with a second metal ring 700 in another area. When the first metal ring 400 and the second metal ring 700 are arranged oppositely, the area size of the two can also be determined according to the actual situation of chip packaging.

Continuing to refer to FIGS. 3 and 8, FIGS. 3 and 8 show a packaging form of the solder ball 300. The surface of the substrate 100 away from the chip 200 is provided with the solder ball 300, and the solder ball 300 is packaged by the second insulating layer 600. When the solder balls 300 are arranged, the solder balls 300 include but are not limited to solder balls. The solder ball 300 is fixed on the side of the substrate 100 facing away from the chip 200, and a second insulating layer 600 is provided on the side of the substrate 100 facing away from the chip 200. The second insulating layer 600 surrounds the solder balls 300. Wrapped by two insulating layers 600, the other part of the solder balls 300 exposes the side of the second insulating layer 600 away from the substrate 100 for connection between the substrate 100 and other substrates or printed circuit boards. The solder balls 300 expose the second insulation The specific height of the side of the layer 600 facing away from the substrate 100 is determined according to the actual situation of the chip package. When the second insulating layer 600 is specifically provided, the thermal expansion coefficient of the second insulating layer 600 is greater than the thermal expansion coefficient of the substrate 100, so that the thermal mismatch between the substrate 100 and the printed circuit board can be reduced during the temperature cycling process, and the substrate 100 and the printed circuit board The heat distribution between the printed circuit boards is relatively uniform, thereby improving the service life of the substrate 100 and the printed circuit board, and the existence of the second insulating layer 600 can also buffer the stress of the solder balls 300 and enhance the fatigue resistance of the solder balls 300 during the temperature cycling process Characteristics, and thus the board-level reliability of the chip 200. When specifically selecting the material of the second insulating layer 600, it is only necessary to limit the thermal expansion coefficient of the second insulating layer 600 to be greater than the thermal expansion coefficient of the substrate 100. The second insulating layer 600 can be a molding compound, a resin, or a thermal expansion coefficient greater than Other insulating materials of the substrate 100, and the specific material of the second insulating layer 600 are selected according to the actual situation of the chip package.

As shown in Figure 3 and Figure 8, Figure 3 and Figure 8 show a form of solder ball for chip packaging. The solder balls used for chip packaging are common spherical solder balls, and the diameter of the solder balls ranges from 0.2mm-1mm. , The diameter of the solder ball is 0.2mm, 0.4mm, 0.6mm, 0.8mm, 1mm. Of course, the shape of the solder balls includes but is not limited to spherical solder balls. Refer to FIG. 10 together. FIG. 10 shows another solder ball form of the chip package. The solder ball 300 may be a special-shaped solder that directly contacts the substrate 100. The ball, as shown in FIG. 10, when the solder ball 300 is set, the special-shaped solder ball 300 includes a first solder ball 310 and a second solder ball 320. The cross section of the first solder ball 310 is a curved surface, and the first solder ball The side of 310 away from the substrate 100 is used as a soldering surface for connecting the second solder ball 320. The cross section of the second solder ball 320 is another arc-shaped surface. The second solder ball 320 has a matching surface with the soldering surface of the first solder ball 310. On the end surface, the second solder ball 320 is embedded on the soldering surface of the first solder ball 310. When the solder ball 300 is packaged, the first solder ball 310 is disposed in the second insulating layer 600, and the height of the second insulating layer 600 is along the The direction perpendicular to the substrate 100 is equal to the height of the first solder ball 310, so that the end surface of the first solder ball 310 away from the substrate 100 is flush with the second insulating layer 600, so that the welding surface of the first solder ball 310 exposes the second insulating layer 60 In order to facilitate the fixed connection of the second solder ball 320 on the first solder ball 310, the special-shaped solder ball can be packaged through this two-layer solder ball arrangement, and the solder ball packaging process described above is relatively simple and easy to implement.

Also refer to FIG. 11, which shows another solder ball form of the chip package. The solder ball 300 can also be fixed on the substrate 100 through a connector. As shown in FIG. 11, when the solder ball 330 is set, the solder ball 330 and the substrate 100 are connected by a metal block 900. The side of the substrate 100 away from the chip 200 is provided with a metal block 900. The side of the metal block 900 away from the substrate 100 is used as a soldering surface for connecting the solder balls 330. The cross-section is an arc surface, the solder ball 330 has an end surface that matches the welding surface of the metal block 900, and the solder ball 330 is embedded on the welding surface of the metal block 900. It is selected when the distance between the solder ball 330 and the substrate 100 is large The metal block 900 with a larger size is selected when the distance between the solder ball 330 and the substrate 100 is small. When the solder ball 330 is packaged, the metal block 900 is arranged in the second insulating layer 600. The height of the insulating layer 600 is equal to the height of the metal block 900 in a direction perpendicular to the substrate 100 so that the end surface of the metal block 900 away from the substrate 100 is flush with the second insulating layer 600. The height of the solder ball 330 relative to the substrate 100 can be adjusted conveniently and quickly by disposing the metal block 900 between the solder ball 330 and the substrate 100. When the metal block 900 is specifically provided, the metal block 900 may be a copper pillar. The diameter of the copper column ranges from 0.2mm-1mm, and the diameter of the copper column is 0.2mm, 0.4mm, 0.6mm, 0.8mm, 1mm. The shape of the metal block 900 includes but is not limited to a cylinder and a rectangular parallelepiped. The material of the metal block 900 includes but is not limited to copper, copper alloy, nickel, stainless steel. The shape and material of the metal block 900 are based on the solder balls 330 and The actual situation of chip packaging is determined.

As shown in FIG. 12, in the second aspect, the present application also provides a method for manufacturing a chip package, and the specific process of the method for manufacturing the chip package is as follows:

Step 710: Mount the chip 200 and the first metal ring 400 on the substrate 100. The first metal ring 400 is disposed on the surface of the substrate 100 facing the chip 200 and surrounds the chip 200. The first metal ring 400 is a closed ring or has at least A gaped ring.

As shown in Figure 13(a), Figure 13(a) is a structure formed by performing step 710. After the substrate 100 is cleaned, a plurality of chips 200, a first metal ring 400, and other components are mounted on the substrate 100. For example, the passive device 800 connected to the pins of the chip 200 may also include components capable of implementing other functions. In specific settings, the first metal ring 400 is symmetrical about the center of the chip 200. When the number of chips 200 is multiple, in order to further reduce the deformation of the substrate 100, the substrate 100 is mounted on the surface of the chip 200 with a third metal ring 450, and the third metal ring 450 is located in at least two of the multiple chips 200. Between 200 chips.

After performing step 710, in order to package the chip 200 and the first metal ring 400, the following operations need to be performed: a first insulating layer 500 is formed on the substrate 100, and the first insulating layer 500 completely covers the first metal ring 400 and surrounds the chip 200.

As shown in Figure 13(b), Figure 13(b) is the structure formed by performing step 720. After the chip 200, the first metal ring 400 and other components are mounted, the first insulating layer is prepared on the substrate 100 500. The first insulating layer 500 completely covers the first metal ring 400, is arranged around the chip 200 and wraps the chip 200. The preparation method of the first insulating layer 500 includes but not limited to compression injection molding and transfer injection molding, thermal compression bonding, spraying, etc. the way.

Performing step 710 can package the chip 200 and the first metal ring 400 on the substrate 100. The first metal ring 400 can suppress the thermal deformation of the substrate 100 at high temperatures, and in order to further reduce the thermal deformation of the substrate 100 during the packaging process, It is also necessary to provide a second metal ring 700 on the first insulating layer 500, as shown in FIG. 13(c). FIG. 13(c) shows another package structure of the chip 200. The first insulating layer 500 is formed. After that, continue to mount the second metal ring 700 on the side of the first insulating layer 500 away from the substrate 100. The thermal deformation of the substrate 100 during the packaging process is further reduced through two mounting processes.

Step 720: Implant solder balls 300 on the side of the substrate 100 away from the chip 200, and then form a second insulating layer 600 on the side of the substrate 100 away from the chip 200. The solder balls 300 are disposed on the surface of the substrate 100 facing away from the chip 200 and facing the substrate 100. The part of the second insulating layer 600 is arranged in the second insulating layer 600. The height of the second insulating layer 600 is smaller than the height of the solder balls 300 along the direction perpendicular to the substrate 100. The thermal expansion coefficient of the second insulating layer 600 is greater than that of the substrate 100.

For solder balls of different sizes, shapes, and positions, the solder balls can be packaged through different processes. When step 730 is performed, the following three implementation methods can be used:

Method one, the solder balls used for chip packaging are common spherical solder balls, which are packaged in Figure 13(d)-Figure 13(e), as shown in Figure 13(d), directly on the side of the substrate 100 facing away from the chip 200 The solder balls 300 are implanted. At this time, the solder balls 300 are fixedly connected to the substrate 100; then, as shown in FIG. 13(e), a second insulating layer 600 is prepared on the substrate 100, and the second insulating layer 600 surrounds the solder balls. 300, and along the direction perpendicular to the substrate 100, the thickness of the second insulating layer 600 is less than the height of the solder balls 300, so that the solder balls 300 expose the second insulating layer 600. The preparation methods of the second insulating layer 600 include but are not limited to pressing Injection molding and transfer injection molding, hot pressing, spraying and other methods. Through the above process, solder balls with lower size, shape and location requirements can be packaged.

In the second method, the solder balls used in the chip package are special-shaped solder balls. Through the package shown in Fig. 14(a)-14(d), as shown in Fig. 14(a), the first side of the substrate 100 away from the chip 200 is implanted. Solder balls 310. At this time, the first solder balls 310 have a spherical structure, and the first solder balls 310 are fixedly connected to the substrate 100; then, as shown in FIG. 14(b), a layer of first solder balls is formed on the side of the substrate 100 away from the chip 200. Two insulating layers 600, the second insulating layer 600 covers the first solder balls 310, along the direction perpendicular to the substrate 100, the thickness of the second insulating layer 600 is greater than or equal to the height of the first solder balls 310, the preparation method of the second insulating layer 600 Including but not limited to compression injection molding and transfer injection molding, thermocompression bonding, spraying, etc.; then, as shown in Figure 14 (c), the second insulating layer 600 and the first solder ball 310 are thinned by a thinning process so as to be vertical In the direction of the substrate 100, the thickness of the second insulating layer 600 and the height of the first solder ball 310 are smaller than the original height of the first solder ball 310, the first solder ball 310 exposes the ball-planting surface, and the ball-planting surface and the second insulating layer 600 are away from the substrate One side of 100 is flush, and the thinning process includes but is not limited to grinding, chemical etching, laser etching, etc.; finally, as shown in FIG. 14(d), a second solder ball 320 is implanted on the surface of the ball. Through the two-layer solder ball preparation process, the special-shaped solder ball 300 can be packaged on the substrate 100 more conveniently and quickly.

Method three, the solder balls used in the chip packaging are indirectly connected to the substrate, and through the package shown in Figure 15(a)-15(d), as shown in Figure 15(a), a metal block is fixed on the side of the substrate 100 facing away from the chip 200 900. At this time, the size of the metal block 900 is relatively large, and the metal block 900 is fixedly connected under the pad of the substrate 100. The connection process includes but not limited to electroplating, electroless plating and placing pre-forming; then as shown in Figure 15(b) As shown, a second insulating layer 600 is formed on the side of the substrate 100 away from the chip 200. The second insulating layer 600 covers the metal block 900. Along the direction perpendicular to the substrate 100, the thickness of the second insulating layer 600 is greater than or equal to that of the metal block 900. Height, the preparation methods of the second insulating layer 600 include but are not limited to compression injection molding and transfer injection molding, hot compression bonding, spraying, etc.; then, as shown in FIG. 15(c), a thinning process is used to thin the second insulating layer 600 And the metal block 900 so that in the direction perpendicular to the substrate 100, the thickness of the second insulating layer 600 and the height of the metal block 900 are less than the original height of the metal block 900, and the metal block 900 exposes the ball-planting surface, the ball-planting surface and the second insulating layer 600 The side facing away from the substrate 100 is flush, and the thinning process includes, but is not limited to, grinding, chemical etching, laser etching, etc.; finally, as shown in FIG. 15(d), a second solder ball 320 is implanted on the ball-planting surface. By providing the metal block 900 between the solder ball and the substrate 100, the height of the solder ball relative to the substrate 100 can be adjusted conveniently and quickly.

In the method for manufacturing the chip package described above, the first metal ring 400 is mounted on the substrate 100, and the first metal ring 400 is used to suppress the thermal deformation of the substrate 100 at high temperatures; and the solder balls 300 are planted on the substrate 100. The second insulating layer 600 is formed on one side of the second insulating layer, and the thickness of the second insulating layer 600 is defined to be less than the height of the solder balls 300. When the material is selected, the thermal expansion coefficient of the second insulating layer 600 is defined to be greater than the thermal expansion coefficient of the substrate 100, so as to package the solder balls. 300 at the same time reduces the thermal mismatch between the substrate 100 and the printed circuit board during the temperature cycle, buffers the stress of the solder ball 300, and enhances the fatigue resistance of the solder ball 300 during the temperature cycle; the above-mentioned formation process has fewer steps and preparation It is more convenient and fast, the formed chip package has less warpage and higher board-level reliability.

In the third aspect, this application also provides a terminal device, including a chip package and a printed circuit board P(C)(B), the chip package is electrically connected to the P(C)(B), and the chip package is either Chip packaging of technical solutions. Since the chip packaging structure is provided with the first metal ring 400, the warpage deformation is small, and the board-level mounting yield is high. Moreover, by limiting the thermal expansion coefficient of the second insulating layer 600 to be greater than the thermal expansion coefficient of the substrate 100, the chip packaging structure After being connected to the printed circuit board P(C)(B), the board-level reliability during the temperature cycle is relatively high. Therefore, the product yield rate of the terminal device with the chip package is relatively high.

Claims

A chip package, characterized by comprising a substrate, a chip and a first metal ring, the chip is arranged on the surface of the substrate and electrically connected to the substrate, the first metal ring is arranged on the substrate facing the On the surface of the chip and surrounding the chip, the first metal ring is a closed ring or a ring with at least one gap.
The chip package of claim 1, wherein the first metal ring is symmetrical about the center of the chip.
The chip package of claim 1 or 2, wherein the chip package further comprises a first insulating layer, and the first insulating layer is disposed on the surface of the substrate facing the chip, and the chip and the The first metal ring is arranged in the first insulating layer.
The chip package according to any one of claims 1 to 3, wherein the chip package further comprises a second metal ring, and the second metal ring is disposed on a surface of the first insulating layer facing away from the substrate , And surrounding the chip, the second metal ring is a closed ring or a ring with at least one gap.
5. The chip package of claim 4, wherein the second metal ring is symmetrical about the center of the chip.
The chip package according to any one of claims 1 to 5, further comprising a passive device, the passive device is arranged on the surface of the substrate facing the chip and connected to the chip pins The passive device is electrically connected to the substrate, and the passive device is arranged in the first insulating layer and between the first metal ring and the chip.
The chip package according to any one of claims 1-6, wherein the number of the chips is multiple, the chip package further comprises a third metal ring, and the third metal ring is disposed on the substrate It faces the surface of the chip and is located between at least two of the chips.
7. The chip package of any one of claims 1-7, further comprising a solder ball and a second insulating layer, the second insulating layer being disposed on the surface of the substrate facing away from the chip, the The solder balls are arranged on the surface of the substrate facing the chip and are arranged in the second insulating layer. The height of the second insulating layer is smaller than that of the substrate in the direction perpendicular to the substrate. For the height of the solder ball, the thermal expansion coefficient of the second insulating layer is greater than the thermal expansion coefficient of the substrate.
The chip package according to any one of claims 8, wherein the solder ball comprises a first solder ball connected to the substrate, and a first solder ball embedded on a side of the first solder ball facing away from the substrate. The second solder ball, the first solder ball is arranged in the second insulating layer, and the height of the second insulating layer is equal to the height of the first solder ball in a direction perpendicular to the substrate.
The chip package according to any one of claims 1-9, further comprising a solder ball, a metal block, and a second insulating layer, the second insulating layer being disposed on the surface of the substrate facing away from the chip , The metal block is disposed on the surface of the substrate away from the chip and located in the second insulating layer, the solder ball is fixed on the surface of the metal block away from the substrate, and the second insulating layer The height of is equal to the height of the metal block in the direction perpendicular to the substrate.
10. The chip package according to any one of claims 8-10, wherein the material of the second insulating layer is resin or molding compound.
A terminal equipment, characterized by comprising a chip package and a printed circuit board P(C)(B), the chip package is electrically connected to the P(C)(B), and the chip package is as claimed The chip package described in any one of 1-11.
A method for manufacturing a chip package, characterized in that it comprises:

A chip and a first metal ring are mounted on one side of the substrate. The first metal ring is disposed on the surface of the substrate facing the chip and surrounds the chip. The first metal ring is a closed ring or has at least A gaped ring.
The manufacturing method according to claim 13, wherein the first metal ring is symmetrical about the center of the chip.
The preparation method of claim 13, further comprising:

Forming a first insulating layer on the surface of the substrate facing the chip, and the chip and the first metal ring are arranged in the first insulating layer;

A second metal ring is attached to the side of the first insulating layer facing away from the substrate. The second metal ring is a closed ring or a ring with at least one gap and surrounds the chip.
The manufacturing method of claim 15, wherein the second metal ring is symmetrical about the center of the chip.
The manufacturing method according to claim 15, further comprising: mounting a passive device on the surface of the substrate facing the chip, the passive device being arranged in the first insulating layer and located in the first insulating layer. Between the metal ring and the chip.
The manufacturing method according to claim 15, wherein when the number of chips is multiple, it further comprises: before forming the first insulating layer, mounting a third metal ring on the surface of the substrate facing the chip , The third metal ring is located between at least two of the plurality of chips.
The preparation method according to any one of claims 13-18, further comprising:

Implanting solder balls on the side of the substrate facing away from the chip;

A second insulating layer is formed on the side of the substrate facing away from the chip, and the solder balls are arranged on the surface of the substrate facing away from the chip and are arranged in the second insulating layer. The height of the second insulating layer is smaller than the height of the solder balls in a direction perpendicular to the substrate, and the thermal expansion coefficient of the second insulating layer is greater than the thermal expansion coefficient of the substrate.
The manufacturing method of claim 19, wherein the solder ball comprises a first solder ball connected to the substrate and a second solder ball embedded on a side of the first solder ball facing away from the substrate. When soldering balls, specifically include:

Implanting a first solder ball on the side of the substrate facing away from the chip;

Forming a second insulating layer on the side of the substrate away from the chip, and in a direction perpendicular to the substrate, the height of the second insulating layer is greater than the height of the first solder balls;

Using a thinning process to thin the second insulating layer and the first solder ball, the first solder ball exposes the ball-planting surface, and the ball-planting surface is flush with the side of the second insulating layer away from the substrate;

A second solder ball is implanted on the implanted ball surface.
The preparation method according to any one of claims 13-18, further comprising:

A metal block is fixedly arranged on the side of the substrate facing away from the chip;

Forming a second insulating layer on the side of the substrate away from the chip, and in a direction perpendicular to the substrate, the height of the second insulating layer is greater than the height of the metal block;

Using a thinning process to thin the second insulating layer and the metal block, where the metal block exposes the ball-planting surface, and the ball-planting surface is flush with the surface of the second insulating layer facing away from the substrate;

A solder ball is implanted on the implanted ball surface.