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WO2020189929A1 - Manufacturing method for semiconductor device - Google Patents

Manufacturing method for semiconductor device Download PDF

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Publication number
WO2020189929A1
WO2020189929A1 PCT/KR2020/003072 KR2020003072W WO2020189929A1 WO 2020189929 A1 WO2020189929 A1 WO 2020189929A1 KR 2020003072 W KR2020003072 W KR 2020003072W WO 2020189929 A1 WO2020189929 A1 WO 2020189929A1
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WO
WIPO (PCT)
Prior art keywords
layer
pattern
forming
seed layer
barrier metal
Prior art date
Application number
PCT/KR2020/003072
Other languages
French (fr)
Korean (ko)
Inventor
이석재
민우식
오찬권
Original Assignee
하이엔드테크놀로지(주)
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Publication of WO2020189929A1 publication Critical patent/WO2020189929A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365

Definitions

  • the present invention relates to a method of manufacturing a semiconductor device.
  • Copper has a specific resistance of about 1.7u ⁇ cm, has a low specific resistance compared to aluminum having a specific resistance of 2.65u ⁇ cm, and resistance to EM characteristics and SIM characteristics is approximately twice or more superior to that of aluminum.
  • a suitable etchant for patterning by etching copper has not been developed. Therefore, in general, a Damascene process is used to form copper wiring.
  • the damascene process is performed by forming intaglio and relief patterns on a substrate, forming copper to be buried in the intaglio pattern, and then performing a CMP process to remove copper formed in areas other than the intaglio patterns.
  • the method of embedding copper in the intaglio pattern is generally using an electroplating method and an electroless plating method.
  • the electroplating method there is a problem in that the step coverage is reduced in the highly integrated semiconductor device, and thus voids are formed in the copper wiring.
  • an electroless plating method is sometimes used.
  • the CMP process not only uses a lot of consumable materials such as pads and slurries, but also has a problem of lowering the yield due to the occurrence of scratches and contamination sources due to polishing, and dishing and erosion. have.
  • a number of CMP processes must be performed and a large amount of copper layers must be removed through the CMP process, so manufacturing cost and manufacturing time of the semiconductor device are increased, thereby lowering productivity and yielding production.
  • An object of the present invention is to provide a method of manufacturing a semiconductor device capable of increasing productivity by reducing manufacturing cost and manufacturing time of a metal wiring process.
  • a method of manufacturing a semiconductor device includes forming an intaglio pattern and a relief pattern on an insulating layer; Forming a barrier metal layer on the intaglio pattern and the relief pattern; Forming a seed layer on the barrier metal layer; Removing the seed layer on the barrier metal layer formed on the embossed pattern; And forming a conductive layer on the seed layer formed on the intaglio pattern.
  • a method of manufacturing a semiconductor device includes forming a photoresist pattern on an insulating layer, and forming an intaglio pattern and a relief pattern formed on the insulating layer; Forming a barrier metal layer on the intaglio pattern and the photoresist pattern disposed on the intaglio pattern; Forming a seed layer on the barrier metal layer; Removing the seed layer on the barrier metal layer formed on the embossed pattern; Removing the photoresist pattern disposed on the embossed pattern; And forming a conductive layer on the seed layer formed on the intaglio pattern.
  • the method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention can increase productivity by reducing manufacturing cost and manufacturing time of a metal wiring process.
  • 1 to 7 illustrate a method of manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 8 to 16 illustrate a method of manufacturing a semiconductor device according to another embodiment of the present invention.
  • 1 to 7 illustrate a method of manufacturing a semiconductor device 100 according to an embodiment of the present invention.
  • a method of manufacturing a semiconductor device 100 includes forming an intaglio pattern and a relief pattern on the insulating layer 120; Forming a barrier metal layer 140 on the intaglio pattern and the relief pattern; Forming a seed layer 150 on the barrier metal layer 140; Removing the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern; And forming a conductive layer 170 on the seed layer 150 formed on the intaglio pattern.
  • the step of forming the intaglio pattern and the embossed pattern on the insulating layer 120 is a step of forming a region in which the metal wiring is to be disposed.
  • Metal wiring having a certain shape may be manufactured by forming a conductive material such as copper to be buried inside the intaglio pattern. Referring to FIG. 1, a portion of the lower portion of the intaglio pattern may be formed to be connected to the through electrode 130. As a result, the metal wiring may be electrically connected to an electrical system (gate, etc.) under the semiconductor device 100 through the through electrode 130.
  • the intaglio pattern and the relief pattern may be performed through a lithography process.
  • the method of forming the concave pattern and the concave pattern using a lithography process may be performed by patterning a photoresist on the insulating layer 120 to form and then removing other portions. Thereafter, by removing the insulating layer 120 exposed to the outside through an etching process, an intaglio pattern and a relief pattern may be formed on the insulating layer 120. Next, the photoresist disposed on the embossed pattern of the insulating layer 120 may be removed.
  • the insulating layer 120 may be a substrate 110 used for manufacturing the semiconductor device 100, and may be a layer of an insulating material formed by being coated on the substrate 110.
  • the substrate 110 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate, and may include an impurity element therein and having a certain level of conductivity.
  • the insulating material may be a material generally used when forming an insulating layer in semiconductor device manufacturing, and may include various oxides, nitrides, or oxynitrides.
  • the step of forming the barrier metal layer 140 on the intaglio pattern and the relief pattern may be performed using various deposition methods such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).
  • the barrier metal layer 140 may be a single layer of a Ta layer or a TaN layer, or a stacked layer of a Ta layer and a TaN layer, and is not particularly limited.
  • the thickness of the barrier metal layer 140 may be selected as necessary and may be several nm to several hundreds nm.
  • the barrier metal layer 140 may be formed to have a constant thickness along an intaglio pattern and a relief pattern.
  • Forming the seed layer 150 on the barrier metal layer 140 includes various deposition methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition (ALD). It can be done using.
  • the seed layer 150 may be formed to a thickness of several nm or thousands of nm, and is not particularly limited.
  • the seed layer 150 may serve as a seed for forming the conductive layer 170 in the step of forming the conductive layer 170 using an electroplating method or an electroless plating method.
  • seed Cu can be used as the seed layer when copper (Cu) is formed as the conductive layer
  • seed Co is used as the seed layer when cobalt (Co) is formed as the conductive layer.
  • the seed Cu or seed Co may be deposited by sputtering, CVD, ALD, or the like.
  • a seed layer that functions as an activator may be formed on the barrier metal layer before plating the conductive layer (Cu or Co).
  • the seed layer may be formed by depositing or plating palladium (Pd) in the form of a thin film or particles on the barrier metal layer, and in this case, the surface of the barrier metal layer may be changed to autocatalytic.
  • FIGS. 17 and 18 show the principle of the electroless plating process.
  • Cu ions contained in the electroless solution are reduced from Pd particles included in the seed layer formed on the barrier metal layer to form a copper film, and once the copper film is formed, the copper film is continuously reduced. A reaction may occur to increase the thickness of the copper layer.
  • FIG. 4 illustrates a step of removing the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern
  • FIG. 5 illustrates a state in which the seed layer 150 on the embossed pattern is removed.
  • the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern may be selectively removed.
  • the mass body 160 is sprayed onto the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern.
  • the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern may be selectively removed.
  • the step of removing the seed layer 150 may be performed by spraying the mass body 160 onto the seed layer 150.
  • the method of spraying the mass body 160 may be spraying the mass body 160 to have a predetermined angle from a direction perpendicular to the photolaser layer. Referring to FIG. 4, it can be seen that the mass body 160 is sprayed in a direction inclined at a predetermined angle ⁇ with respect to a direction (dotted line) perpendicular to the seed layer 150. Through this, it is possible to control so that the mass body 160 collides with the seed layer 150 but does not collide with the seed layer 150 disposed on the intaglio pattern.
  • An angle at which the mass body 160 is incident may be 20 to 70° with respect to a direction perpendicular to the seed layer 150.
  • the mass body 160 When the incident angle of the mass body 160 is less than 20°, the mass body 160 may collide with the seed layer 150 on the cathode pattern. When the incident angle of the mass body 160 exceeds 70°, since the mass body 160 does not transmit a sufficient amount of impact to the seed layer 150, the seed layer 150 may not be sufficiently removed.
  • the mass body 160 may have a mass capable of transmitting an amount of impact sufficient to remove the seed layer 150, and it is preferable that the mass body 160 has a size such that it does not flow into the cathode pattern when incident at a predetermined angle. Do. To this end, the average diameter of the mass body 160 incident on the seed layer 150 in this step may be 5 ⁇ m or more, more preferably 10 ⁇ m or more.
  • the mass body 160 may be a sublimation material, and preferably, the sublimation material may be any one of dry ice, naphthalene, and iodine.
  • the sublimation material may be any one of dry ice, naphthalene, and iodine.
  • the seed layer 150 can be removed by a simple process, and an additional cleaning process due to generation of by-products is unnecessary.
  • the method of injecting the mass body 160 may be a method of transporting the powdered mass body 160 through a carrier gas and emitting it to a nozzle.
  • the conductive layer 170 may be formed by performing an electroplating process or an electroless plating process.
  • unnecessary portions have to be removed through etching, but there is a problem in that the feasibility is low due to high technical difficulty and high cost and time.
  • a plating layer can be formed quickly and economically compared to forming a conductive wiring using a conventional sputtering method or the like.
  • the conductive layer 170 may be made of a material having conductivity, and preferably may be copper (Cu), cobalt (Co), a copper alloy, or a cobalt alloy.
  • the conductive layer 170 may be formed on the seed layer 150 formed on the intaglio pattern and on the embossed pattern from which the seed layer 150 has been removed.
  • the seed layer 150 on the embossed pattern is removed in the previous process, but a plating layer may be partially formed in the process of performing the electroplating method and the electroless plating method. In addition, it may be formed by growing from the seed layer 150 that has not been removed in the previous process.
  • the electroless plating method may be performed by supplying a plating solution onto the seed layer 150.
  • the electroless plating method may be performed by a conventional method performed to form a metal layer.
  • the plating solution used for electroless plating may include a metal salt such as copper sulfate, an oxidizing agent such as formalin, a complexing agent such as Rossel salt, and sodium hydroxide.
  • the CMP process is to remove the substrate 110 on which the conductive layer 170 is formed using a physical reaction and a chemical reaction by rubbing the substrate 110 on which the slurry is supplied, and a conventional CMP process method may be applied and is not particularly limited.
  • the conductive layer 170 on the anode pattern can be formed relatively less by selectively removing the seed layer 150 formed on the anode pattern.
  • FIG. 8 to 16 illustrate a method of manufacturing a semiconductor device 100 according to another embodiment of the present invention.
  • a photoresist pattern 180 is formed on the insulating layer 120, and the insulating layer 120 is Forming the formed engraved pattern and the embossed pattern; Forming a barrier metal layer 140 on the photoresist pattern 180 disposed on the intaglio pattern and the relief pattern; Forming a seed layer 150 on the barrier metal layer 140; Removing the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern; Removing the photoresist pattern 180 disposed on the embossed pattern; And forming a conductive layer 170 on the seed layer 150 formed on the intaglio pattern.
  • FIG. 8 illustrates a step of forming a photoresist pattern 180 on the insulating layer 120
  • FIG. 2 illustrates a step of forming an intaglio pattern and an embossed pattern formed on the insulating layer 120.
  • This step is a step of forming a region in which the metal wiring is to be arranged.
  • Metal wiring having a certain shape may be manufactured by forming a conductive material such as copper to be buried inside the intaglio pattern. Referring to FIG. 9, a portion of the lower portion of the intaglio pattern may be formed to be connected to the through electrode 130. As a result, the metal wiring may be electrically connected to an electrical system (gate, etc.) under the semiconductor device 100 through the through electrode 130.
  • the intaglio pattern and the relief pattern may be performed through a lithography process.
  • a method of forming an intaglio pattern and an intaglio pattern using a lithography process may be performed by patterning a photoresist on the insulating layer 120 and then removing other portions. Thereafter, by removing the insulating layer 120 exposed to the outside through an etching process, an intaglio pattern and a relief pattern may be formed on the insulating layer 120.
  • the insulating layer 120 may be a substrate 110 used for manufacturing the semiconductor device 100, and may be a layer of an insulating material formed by being coated on the substrate 110.
  • the substrate 110 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate, and may include an impurity element therein and having a certain level of conductivity.
  • the insulating material may be a material generally used when forming an insulating layer in semiconductor device manufacturing, and may include various oxides, nitrides, or oxynitrides.
  • FIG. 10 shows a step of forming a barrier metal layer 140 on the photoresist pattern 180 disposed on the intaglio pattern and the relief pattern.
  • This step may be performed using various deposition methods such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).
  • the barrier metal layer 140 may be a single layer of a Ta layer or a TaN layer, or a stacked layer of a Ta layer and a TaN layer, and is not particularly limited.
  • the thickness of the barrier metal layer 140 may be selected as necessary and may be several nm to several hundreds nm.
  • the barrier metal layer 140 may be formed to have a constant thickness along an intaglio pattern and a relief pattern.
  • the 11 shows a step of forming the seed layer 150 on the barrier metal layer 140.
  • This step may be performed using various deposition methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition (ALD).
  • the seed layer 150 may be formed to a thickness of several nm or thousands of nm, and is not particularly limited.
  • the seed layer 150 may serve as a seed for forming the conductive layer 170 in the step of forming the conductive layer 170 using an electroplating method or an electroless plating method.
  • the seed layer 150 may preferably include palladium (Pd).
  • Pd palladium
  • seed Cu can be used as the seed layer when copper (Cu) is formed as the conductive layer
  • seed Co is used as the seed layer when cobalt (Co) is formed as the conductive layer.
  • the seed Cu or seed Co may be deposited by sputtering, CVD, ALD, or the like.
  • a seed layer that functions as an activator may be formed on the barrier metal layer before plating the conductive layer (Cu or Co).
  • the seed layer may be formed by depositing or plating palladium (Pd) in the form of a thin film or particles on the barrier metal layer, and in this case, the surface of the barrier metal layer may be changed to autocatalytic.
  • FIGS. 17 and 18 show the principle of the electroless plating process.
  • Cu ions contained in the electroless solution are reduced from Pd particles included in the seed layer formed on the barrier metal layer to form a copper film, and once the copper film is formed, the copper film is continuously reduced. A reaction may occur to increase the thickness of the copper layer.
  • FIG. 12 shows a step of removing the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern
  • FIG. 13 shows a state in which the seed layer 150 on the embossed pattern is removed.
  • the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern may be selectively removed.
  • the mass body 160 is sprayed onto the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern.
  • the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern may be selectively removed.
  • the step of removing the seed layer 150 may be performed by spraying the mass body 160 onto the seed layer 150.
  • the method of spraying the mass body 160 may be spraying the mass body 160 to have a predetermined angle from a direction perpendicular to the photolaser layer. Referring to FIG. 12, it can be seen that the mass body 160 is sprayed in a direction inclined at a predetermined angle ⁇ with respect to the direction (dotted line) perpendicular to the seed layer 150. Through this, it is possible to control so that the mass body 160 collides with the seed layer 150 but does not collide with the seed layer 150 disposed on the intaglio pattern.
  • An angle at which the mass body 160 is incident may be 20 to 70° with respect to a direction perpendicular to the seed layer 150.
  • the mass body 160 When the incident angle of the mass body 160 is less than 20°, the mass body 160 may collide with the seed layer 150 on the cathode pattern. When the incident angle of the mass body 160 exceeds 70°, since the mass body 160 does not transmit a sufficient amount of impact to the seed layer 150, the seed layer 150 may not be sufficiently removed.
  • the mass body 160 may have a mass capable of transmitting an amount of impact sufficient to remove the seed layer 150, and it is preferable that the mass body 160 has a size such that it does not flow into the cathode pattern when incident at a predetermined angle. Do. To this end, the average diameter of the mass body 160 incident on the seed layer 150 in this step may be 5 ⁇ m or more, more preferably 10 ⁇ m or more.
  • the mass body 160 may be a sublimation material, and preferably, the sublimation material may be any one of dry ice, naphthalene, and iodine.
  • the sublimation material may be any one of dry ice, naphthalene, and iodine.
  • the seed layer 150 can be removed by a simple process, and an additional cleaning process due to generation of by-products is unnecessary.
  • the method of injecting the mass body 160 may be a method of transporting the powdered mass body 160 through a carrier gas and emitting it to a nozzle.
  • the conductive layer 170 may be formed only on the seed layer 150 on the intaglio pattern.
  • the process of removing the photoresist may be performed by a method commonly performed in a semiconductor device manufacturing process, and is not particularly limited.
  • the conductive layer 170 may be formed by performing an electroplating process or an electroless plating process.
  • unnecessary portions have to be removed through etching, but there is a problem in that the practicality is low due to high technical difficulty and high cost and time.
  • copper is used as a conductive material, there is a problem in that there is no suitable etching material. Since the embodiment of the present invention uses an electroless plating method, a plating layer can be formed quickly and economically compared to forming a conductive wiring using a conventional sputtering method or the like.
  • the conductive layer 170 may be made of a material having conductivity, and preferably may be copper (Cu), cobalt (Co), a copper alloy, or a cobalt alloy.
  • the conductive layer 170 may be formed on the seed layer 150 formed on the intaglio pattern and on the embossed pattern from which the seed layer 150 has been removed.
  • the seed layer 150 on the embossed pattern is removed in the previous process, but a plating layer may be partially formed in the process of performing the electroplating method and the electroless plating method. In addition, it may be formed by growing from the seed layer 150 that has not been removed in the previous process.
  • the electroless plating method may be performed by supplying a plating solution onto the seed layer 150.
  • the electroless plating method may be performed by a conventional method performed to form a metal layer.
  • the plating solution used for electroless plating may include a metal salt such as copper sulfate, an oxidizing agent such as formalin, a complexing agent such as Rossel salt, and sodium hydroxide.
  • the CMP process is to remove the substrate 110 on which the conductive layer 170 is formed using a physical reaction and a chemical reaction by rubbing the substrate 110 on which the slurry is supplied, and a conventional CMP process method may be applied and is not particularly limited.

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Abstract

The present invention relates to a manufacturing method for a semiconductor device. The manufacturing method for a semiconductor device according to an embodiment of the present invention includes: a step for forming an engraved pattern and an embossed pattern in an insulation layer; a step for forming a barrier metal layer over the engraved pattern and the embossed pattern; a step for forming a seed layer on the barrier metal layer; a step for removing the seed layer from the barrier metal layer formed over the embossed pattern; and a step for forming a conductive layer on the seed layer formed over the engraved pattern.

Description

반도체 소자의 제조 방법Semiconductor device manufacturing method
본 발명은 반도체 소자의 제조 방법에 관한 것이다. The present invention relates to a method of manufacturing a semiconductor device.
전자 제품이 소형화되고 있으며, 높은 기능을 요구하게 되면서 반도체 소자에 대해서도 소형화 및 고성능화에 대한 요구가 커지고 있다. 이러한 이유로 종래의 반도체 소자 제조에 사용되는 재료 및 제조 장치에 대한 개선이 요구되고 있다. 또한, 새로운 반도체 소자의 제조 방법을 도입하여 고집적화, 고성능화 및 고수율을 이루고자 하는 시도가 지속적으로 이루어지고 있다. As electronic products are being miniaturized and high functions are required, there is a growing demand for miniaturization and high performance of semiconductor devices. For this reason, there is a demand for improvement in materials and manufacturing apparatuses used in conventional semiconductor device manufacturing. In addition, attempts to achieve high integration, high performance, and high yield by introducing new semiconductor device manufacturing methods have been continuously made.
일 예로, 반도체 소자의 금속배선 물질로 알루미늄을 적용하는 대신 구리를 적용함으로써 전기저항 감소를 통한 시간 지연(Time Delay) 문제를 해결하고 있다. 구리는 비저항이 1.7uΩ㎝ 정도로서, 2.65uΩ㎝의 비저항을 갖는 알루미늄에 비해 비저항이 낮고, EM 특성 및 SIM 특성에 대한 저항성도 알루미늄 보다 대략 2배 이상 우수하다. 다만, 현재로서는 구리를 식각하여 패터닝할 수 있는 적합한 식각액이 개발되지 않은 상태이다. 따라서, 일반적으로 구리 배선을 형성하기 위해 다마신(Damascene) 공정을 이용한다. 다마신 공정은 기판에 음각 및 양각 패턴을 형성한 후 구리가 상기 음각 패턴에 매립되도록 형성한 후 CMP 공정을 수행하여 음각 패턴 이외의 영역에 형성된 구리를 제거함으로써 이루어진다. For example, by applying copper instead of using aluminum as a metal wiring material of a semiconductor device, the problem of time delay through reduction of electrical resistance is solved. Copper has a specific resistance of about 1.7uΩcm, has a low specific resistance compared to aluminum having a specific resistance of 2.65uΩcm, and resistance to EM characteristics and SIM characteristics is approximately twice or more superior to that of aluminum. However, at present, a suitable etchant for patterning by etching copper has not been developed. Therefore, in general, a Damascene process is used to form copper wiring. The damascene process is performed by forming intaglio and relief patterns on a substrate, forming copper to be buried in the intaglio pattern, and then performing a CMP process to remove copper formed in areas other than the intaglio patterns.
이 때, 음각 패턴에 구리를 매립하는 방법은 일반적으로 전해도금법 및 무전도금법을 이용한다. 전해도금법의 경우 고집적 반도체 소자에서 스텝 커버리지(step coverage)가 감소하여 구리 배선 내부에 공극(void)가 형성되는 문제점이 있다. 이러한 전해도금의 대안으로 무전해도금법을 사용하기도 한다. At this time, the method of embedding copper in the intaglio pattern is generally using an electroplating method and an electroless plating method. In the case of the electroplating method, there is a problem in that the step coverage is reduced in the highly integrated semiconductor device, and thus voids are formed in the copper wiring. As an alternative to such electroplating, an electroless plating method is sometimes used.
한편, 상기 CMP 공정은 패드, 슬러리 등 많은 소모성 재료를 사용할 뿐 아니라, 연마에 따른 스크레치(scratch) 및 오염원이 발생하고, 디싱(Dishing) 및 이로전(Erosion)이 발생하여 수율을 낮추는 문제점을 가지고 있다. 종래의 반도체 소자의 금속 배선 형성 공정에서는 다수의 CMP 공정을 수행하여야 하고 CMP 공정을 통해 많은 량의 구리 층을 제거해야 하기 때문에, 반도체 소자의 제조 비용 및 제조 시간을 증가시켜 생산성을 낮추고, 생산 수율을 낮추고, 성능을 낮추는 문제점이 있다.On the other hand, the CMP process not only uses a lot of consumable materials such as pads and slurries, but also has a problem of lowering the yield due to the occurrence of scratches and contamination sources due to polishing, and dishing and erosion. have. In the conventional metal wiring forming process of a semiconductor device, a number of CMP processes must be performed and a large amount of copper layers must be removed through the CMP process, so manufacturing cost and manufacturing time of the semiconductor device are increased, thereby lowering productivity and yielding production. There is a problem of lowering the value and lowering the performance.
관련선행문헌으로 한국특허공개공보 제2004-0043383호가 있다.As a related prior document, there is Korean Patent Publication No. 2004-0043383.
본 발명은 금속 배선 공정의 제조 비용 및 제조 시간을 감소시켜 생산성을 증가시킬 수 있는 반도체 소자의 제조 방법을 제공하는 것을 목적으로 한다. An object of the present invention is to provide a method of manufacturing a semiconductor device capable of increasing productivity by reducing manufacturing cost and manufacturing time of a metal wiring process.
또한, CMP(Chemical Mechanical Polishing) 공정에 따른 디싱 및 이로전 발생을 최소화함으로써, 반도체 소자의 성능을 개선할 수 있다.In addition, by minimizing the occurrence of dishing and erosion according to the CMP (Chemical Mechanical Polishing) process, it is possible to improve the performance of the semiconductor device.
본 발명의 실시 예를 따르는 반도체 소자의 제조 방법은, 절연층에 음각 패턴 및 양각 패턴을 형성하는 단계; 상기 음각 패턴 및 양각 패턴 상에 베리어메탈층을 형성하는 단계; 상기 베리어메탈층 상에 씨드층을 형성하는 단계; 상기 양각 패턴 상에 형성된 베리어메탈층 상의 씨드층을 제거하는 단계; 및 음각 패턴 상에 형성된 씨드층 상에 도전층을 형성하는 단계; 를 포함한다.A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming an intaglio pattern and a relief pattern on an insulating layer; Forming a barrier metal layer on the intaglio pattern and the relief pattern; Forming a seed layer on the barrier metal layer; Removing the seed layer on the barrier metal layer formed on the embossed pattern; And forming a conductive layer on the seed layer formed on the intaglio pattern. Includes.
본 발명의 다른 실시 예를 따르는 반도체 소자의 제조 방법은, 절연층에 포토레지스트 패턴을 형성하고, 상기 절연층에 형성된 음각 패턴 및 양각 패턴을 형성하는 단계; 상기 음각 패턴 및 양각 패턴 상에 배치된 포토레지스트 패턴 상에 베리어메탈층을 형성하는 단계; 상기 베리어메탈층 상에 씨드층을 형성하는 단계; 상기 양각 패턴 상에 형성된 베리어메탈층 상의 씨드층을 제거하는 단계; 상기 양각 패턴 상에 배치된 포토레지스트 패턴을 제거하는 단계; 및 음각 패턴 상에 형성된 씨드층 상에 도전층을 형성하는 단계;를 포함한다.A method of manufacturing a semiconductor device according to another embodiment of the present invention includes forming a photoresist pattern on an insulating layer, and forming an intaglio pattern and a relief pattern formed on the insulating layer; Forming a barrier metal layer on the intaglio pattern and the photoresist pattern disposed on the intaglio pattern; Forming a seed layer on the barrier metal layer; Removing the seed layer on the barrier metal layer formed on the embossed pattern; Removing the photoresist pattern disposed on the embossed pattern; And forming a conductive layer on the seed layer formed on the intaglio pattern.
본 발명의 실시 예를 따르는 반도체 소자의 제조 방법은, 금속 배선 공정의 제조 비용 및 제조 시간을 감소시켜 생산성을 증가시킬 수 있다. The method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention can increase productivity by reducing manufacturing cost and manufacturing time of a metal wiring process.
또한, CMP(Chemical Mechanical Polishing) 공정에 따른 디싱 및 이로전 발생을 최소화함으로써, 반도체 소자의 성능을 개선할 수 있다.In addition, by minimizing the occurrence of dishing and erosion according to the CMP (Chemical Mechanical Polishing) process, it is possible to improve the performance of the semiconductor device.
도 1 내지 도 7은 본 발명의 실시 예를 따르는 반도체 소자의 제조 방법을 도시한 것이다. 1 to 7 illustrate a method of manufacturing a semiconductor device according to an embodiment of the present invention.
도 8 내지 도 16은 본 발명의 다른 실시 예를 따르는 반도체 소자의 제조 방법을 도시한 것이다.8 to 16 illustrate a method of manufacturing a semiconductor device according to another embodiment of the present invention.
도 17 및 도 18은 무전해도금 공정 원리를 도시한 것이다.17 and 18 show the principle of the electroless plating process.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시 형태들을 다음과 같이 설명한다. 그러나, 본 발명의 실시 형태는 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 이하 설명하는 실시 형태로 한정되는 것은 아니다.　 또한, 본 발명의 실시 형태는 당해 기술분야에서 평균적인 지식을 가진 자에게 본 발명을 더욱 완전하게 설명하기 위해서 제공되는 것이다.　 따라서, 도면에서의 요소들의 형상 및 크기 등은 보다 명확한 설명을 위해 과장될 수 있으며, 도면 상의 동일한 부호로 표시되는 요소는 동일한 요소이다. 또한, 유사한 기능 및 작용을 하는 부분에 대해서는 도면 전체에 걸쳐 동일한 부호를 사용한다. 덧붙여, 명세서 전체에서 어떤 구성요소를 "포함"한다는 것은 특별히 반대되는 기재가 없는 한 다른 구성요소를 제외하는 것이 아니라 다른 구성요소를 더 포함할 수 있다는 것을 의미한다. Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. In addition, embodiments of the present invention are provided in order to more completely explain the present invention to those having average knowledge in the art. Accordingly, shapes and sizes of elements in the drawings may be exaggerated for clearer description, and elements indicated by the same reference numerals in the drawings are the same elements. In addition, the same reference numerals are used throughout the drawings for portions having similar functions and functions. In addition, "including" certain elements throughout the specification means that other elements may be further included rather than excluding other elements unless specifically stated to the contrary.
도 1 내지 도 7은 본 발명의 실시 예를 따르는 반도체 소자(100)의 제조 방법을 도시한 것이다. 1 to 7 illustrate a method of manufacturing a semiconductor device 100 according to an embodiment of the present invention.
도 1 내지 도 7을 참조하면, 본 발명의 실시 예를 따르는 반도체 소자(100)의 제조 방법은, 절연층(120)에 음각 패턴 및 양각 패턴을 형성하는 단계; 상기 음각 패턴 및 양각 패턴 상에 베리어메탈층(140)을 형성하는 단계; 상기 베리어메탈층(140) 상에 씨드층(150)을 형성하는 단계; 상기 양각 패턴 상에 형성된 베리어메탈층(140) 상의 씨드층(150)을 제거하는 단계; 및 음각 패턴 상에 형성된 씨드층(150) 상에 도전층(170)을 형성하는 단계; 를 포함한다.Referring to FIGS. 1 to 7, a method of manufacturing a semiconductor device 100 according to an embodiment of the present invention includes forming an intaglio pattern and a relief pattern on the insulating layer 120; Forming a barrier metal layer 140 on the intaglio pattern and the relief pattern; Forming a seed layer 150 on the barrier metal layer 140; Removing the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern; And forming a conductive layer 170 on the seed layer 150 formed on the intaglio pattern. Includes.
도 1은 절연층(120)에 음각 패턴 및 양각 패턴을 형성하는 단계를 도시한 것이다. 절연층(120)에 음각 패턴 및 양각 패턴을 형성하는 단계는 금속 배선이 배치될 영역을 형성하는 단계이다. 상기 음각 패턴 내부에 구리 등의 전도성 물질이 매립되도록 형성함으로써 일정한 형상을 가진 금속 배선을 제조할 수 있다. 도 1을 참조하면, 음각 패턴의 하부 중 일부는 관통전극(130)과 연결되도록 형성될 수 있다. 이로써 금속 배선이 관통전극(130)을 통해 반도체 소자(100) 하부의 전기 시스템(게이트 등)과 전기적으로 연결될 수 있다. 1 shows a step of forming an intaglio pattern and a relief pattern on the insulating layer 120. The step of forming the intaglio pattern and the embossed pattern on the insulating layer 120 is a step of forming a region in which the metal wiring is to be disposed. Metal wiring having a certain shape may be manufactured by forming a conductive material such as copper to be buried inside the intaglio pattern. Referring to FIG. 1, a portion of the lower portion of the intaglio pattern may be formed to be connected to the through electrode 130. As a result, the metal wiring may be electrically connected to an electrical system (gate, etc.) under the semiconductor device 100 through the through electrode 130.
상기 음각 패턴 및 양각 패턴은 리소그래피(Lithography) 공정을 통해 수행될 수 있다. 리소그래피 공정을 이용하여 음각 패턴 및 양각 패턴을 형성하는 방법은 포토레지스트를 절연층(120) 상에 패터닝하여 형성한 후 그 이외의 부분을 제거함으로써 수행될 수 있다. 이 후 외부로 노출된 절연층(120)을 식각 공정을 통해 제거함으로써 절연층(120)에 음각 패턴 및 양각 패턴을 형성할 수 있다. 다음으로, 절연층(120)의 양각 패턴 상에 배치된 포토레지스트를 제거할 수 있다. The intaglio pattern and the relief pattern may be performed through a lithography process. The method of forming the concave pattern and the concave pattern using a lithography process may be performed by patterning a photoresist on the insulating layer 120 to form and then removing other portions. Thereafter, by removing the insulating layer 120 exposed to the outside through an etching process, an intaglio pattern and a relief pattern may be formed on the insulating layer 120. Next, the photoresist disposed on the embossed pattern of the insulating layer 120 may be removed.
상기 절연층(120)은 일반적으로 반도체 소자(100) 제조에 사용되는 기판(110)일 수 있으며, 기판(110) 상에 도포되어 형성된 절연성을 가진 물질의 층일 수 있다. 상기 기판(110)은 실리콘 기판, 게르마늄 기판 또는 실리콘-게르마늄 기판일 수 있으며, 내부에 불순물 원소를 포함하여 일정한 수준의 전도성을 갖는 것을 포함할 수 있다. 상기 절연성을 가진 물질은 반도체 소자 제조에서 절연층 형성 시 일반적으로 사용하는 물질일 수 있으며, 다양한 산화물, 질화물 또는 산질화물을 포함할 수 있다. In general, the insulating layer 120 may be a substrate 110 used for manufacturing the semiconductor device 100, and may be a layer of an insulating material formed by being coated on the substrate 110. The substrate 110 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate, and may include an impurity element therein and having a certain level of conductivity. The insulating material may be a material generally used when forming an insulating layer in semiconductor device manufacturing, and may include various oxides, nitrides, or oxynitrides.
도 2는 음각 패턴 및 양각 패턴 상에 베리어메탈층(140)을 형성하는 단계를 도시한 것이다. 상기 음각 패턴 및 양각 패턴 상에 베리어메탈층(140)을 형성하는 단계는 CVD(Chemical vapor deposition) 또는 ALD (Atomic Layer Deposition) 등의 다양한 증착방법을 이용하여 수행될 수 있다. 상기 베리어메탈층(140)은 Ta막 또는 TaN막의 단일막이거나, Ta막과 TaN막의 적층막일 수 있으며 특별히 제한되지 않는다. 상기 베리어메탈층(140)의 두께는 필요에 따라 선택될 수 있으며 수 nm에서 수백 nm일 수 있다. 2 shows a step of forming the barrier metal layer 140 on the intaglio pattern and the relief pattern. The step of forming the barrier metal layer 140 on the intaglio pattern and the relief pattern may be performed using various deposition methods such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The barrier metal layer 140 may be a single layer of a Ta layer or a TaN layer, or a stacked layer of a Ta layer and a TaN layer, and is not particularly limited. The thickness of the barrier metal layer 140 may be selected as necessary and may be several nm to several hundreds nm.
도 2를 참조하면, 상기 베리어메탈층(140)은 음각 패턴 및 양각 패턴을 따라 일정한 두께를 갖도록 형성될 수 있다. Referring to FIG. 2, the barrier metal layer 140 may be formed to have a constant thickness along an intaglio pattern and a relief pattern.
도 3은 베리어메탈층(140) 상에 씨드층(150)을 형성하는 단계를 도시한 것이다. 상기 베리어메탈층(140) 상에 씨드층(150)을 형성하는 단계는 CVD(Chemical vapor deposition), PVD(Physical Vapor Deposition), 스퍼터링(sputtering) 또는 ALD (Atomic Layer Deposition) 등의 다양한 증착방법을 이용하여 수행될 수 있다. 상기 씨드층(150)은 수 nm 또는 수 천 nm의 두께로 형성될 수 있으며 특별히 제한되지 않는다.3 shows a step of forming the seed layer 150 on the barrier metal layer 140. Forming the seed layer 150 on the barrier metal layer 140 includes various deposition methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition (ALD). It can be done using. The seed layer 150 may be formed to a thickness of several nm or thousands of nm, and is not particularly limited.
씨드층(150)은 도전층(170)을 전해도금법 또는 무전해도금법을 이용하여 형성하는 단계에서 상기 도전층(170)을 형성하기 위한 씨드 역할을 수행할 수 있다. The seed layer 150 may serve as a seed for forming the conductive layer 170 in the step of forming the conductive layer 170 using an electroplating method or an electroless plating method.
도전층을 전해도금법으로 형성할 경우, 도전층으로 구리(Cu)를 형성하는 경우에는 씨드층으로 seed Cu를 사용할 수 있고, 도전층으로 코발트(Co)를 형성하는 경우에는 씨드층으로 seed Co를 사용할 수 있다. 상기 seed Cu 또는 seed Co는 스퍼터링(sputtering), CVD, ALD 등으로 증착할 수 있다. 도전층을 무전해도금법으로 형성할 경우, 도전층(Cu 또는 Co)을 도금하기 전에 베리어메탈층 상에 액티베이터(Activator)로서 기능을 수행하는 씨드층을 형성할 수 있다. 상기 씨드층은 베리어메탈층 상에 팔라듐(Pd)을 박막 또는 입자 형태로 증착 또는 도금하여 형성할 수 있으며, 이 경우, 상기 베리어메탈층 표면을 자가촉매적(autocatalytic)으로 바꾸어 줄 수 있다. When the conductive layer is formed by electroplating, seed Cu can be used as the seed layer when copper (Cu) is formed as the conductive layer, and seed Co is used as the seed layer when cobalt (Co) is formed as the conductive layer. Can be used. The seed Cu or seed Co may be deposited by sputtering, CVD, ALD, or the like. When the conductive layer is formed by an electroless plating method, a seed layer that functions as an activator may be formed on the barrier metal layer before plating the conductive layer (Cu or Co). The seed layer may be formed by depositing or plating palladium (Pd) in the form of a thin film or particles on the barrier metal layer, and in this case, the surface of the barrier metal layer may be changed to autocatalytic.
도 17 및 도 18은 무전해도금 공정의 원리를 도시한 것이다. 도 17 및 도 18 에서, 베리어메탈층 상에 형성된 씨드층에 포함된 Pd 입자에서 무전해도금액에 포함되어 있는 Cu이온이 환원됨으로써 구리막이 형성되고, 일단 구리막이 형성되면 상기 구리막 상에서 계속적으로 환원반응이 일어나 상기 구리막의 두께가 증가할 수 있다. 17 and 18 show the principle of the electroless plating process. In FIGS. 17 and 18, Cu ions contained in the electroless solution are reduced from Pd particles included in the seed layer formed on the barrier metal layer to form a copper film, and once the copper film is formed, the copper film is continuously reduced. A reaction may occur to increase the thickness of the copper layer.
도 4는 양각 패턴 상에 형성된 베리어메탈층(140) 상의 씨드층(150)을 제거하는 단계를 도시한 것이고, 도 5는 양각 패턴 상의 씨드층(150)이 제거된 모습을 도시한 것이다. 본 단계에서 상기 양각 패턴 상에 형성된 베리어메탈층(140) 상의 씨드층(150)을 선택적으로 제거할 수 있다. 이를 통해 도전층(170)을 형성하는 경우 양각 패턴 상에서 도전층(170)이 형성되는 양을 줄일 수 있고, 양각 패턴 상에 형성된 도전층(170)을 제거하기 위한 CMP 공정을 수행함에 있어서, 공정 시간 및 공정 횟수를 감소시킬 수 있다. FIG. 4 illustrates a step of removing the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern, and FIG. 5 illustrates a state in which the seed layer 150 on the embossed pattern is removed. In this step, the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern may be selectively removed. In the case of forming the conductive layer 170 through this, it is possible to reduce the amount of the conductive layer 170 formed on the embossed pattern, and in performing the CMP process for removing the conductive layer 170 formed on the embossed pattern, the process Time and number of processes can be reduced.
상기 양각 패턴 상에 형성된 베리어메탈층(140) 상의 씨드층(150)을 제거하는 단계는, 상기 양각 패턴 상에 형성된 베리어메탈층(140) 상의 씨드층(150) 상에 질량체(160)를 분사하여 상기 양각 패턴 상에 형성된 베리어메탈층(140) 상의 씨드층(150)을 선택적으로 제거하는 것일 수 있다. In the step of removing the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern, the mass body 160 is sprayed onto the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern. Thus, the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern may be selectively removed.
상기 씨드층(150)을 제거하는 단계는 씨드층(150)에 질량체(160)를 분사하여 수행될 수 있다. 상기 질량체(160)를 분사하는 방법은, 상기 포토레이지스층에 수직인 방향으로부터 소정의 각도를 갖도록 상기 질량체(160)를 분사하는 것일 수 있다. 도 4를 참조하면, 질량체(160)가 씨드층(150)에 수직인 방향(점선)에 대하여 소정의 각도(θ)로 경사진 방향으로 분사됨을 알 수 있다. 이를 통해 상기 질량체(160)가 씨드층(150)에 충돌하되, 음각 패턴 상에 배치된 씨드층(150)에는 충돌하지 않도록 제어할 수 있다. 상기 질량체(160)가 입사되는 각도는 씨드층(150)에 수직인 방향에 대하여 20 내지 70°일 수 있다. 상기 질량체(160)가 입사되는 각도가 20°미만인 경우에는 질량체(160)가 음극 패턴 상의 씨드층(150)에 충돌하는 문제가 발생할 수 있다. 상기 질량체(160)가 입사되는 각도가 70°초과인 경우에는 질량체(160)가 씨드층(150)에 충분한 충격량을 전달하지 못하기 때문에 씨드층(150)의 제거가 충분히 일어나지 않을 수 있다. The step of removing the seed layer 150 may be performed by spraying the mass body 160 onto the seed layer 150. The method of spraying the mass body 160 may be spraying the mass body 160 to have a predetermined angle from a direction perpendicular to the photolaser layer. Referring to FIG. 4, it can be seen that the mass body 160 is sprayed in a direction inclined at a predetermined angle θ with respect to a direction (dotted line) perpendicular to the seed layer 150. Through this, it is possible to control so that the mass body 160 collides with the seed layer 150 but does not collide with the seed layer 150 disposed on the intaglio pattern. An angle at which the mass body 160 is incident may be 20 to 70° with respect to a direction perpendicular to the seed layer 150. When the incident angle of the mass body 160 is less than 20°, the mass body 160 may collide with the seed layer 150 on the cathode pattern. When the incident angle of the mass body 160 exceeds 70°, since the mass body 160 does not transmit a sufficient amount of impact to the seed layer 150, the seed layer 150 may not be sufficiently removed.
상기 질량체(160)는 씨드층(150)이 제거될 수 있을 정도의 충격량을 전달할 수 있는 질량을 가질 수 있고, 소정의 각도로 입사하는 경우 음극 패턴 내부로 유입되지 않을 정도의 크기를 가지는 것이 바람직하다. 이를 위해 본 단계에서 씨드층(150)으로 입사되는 질량체(160)의 평균 지름은 5μm 이상, 보다 바람직하게는 10μm 이상일 수 있다. The mass body 160 may have a mass capable of transmitting an amount of impact sufficient to remove the seed layer 150, and it is preferable that the mass body 160 has a size such that it does not flow into the cathode pattern when incident at a predetermined angle. Do. To this end, the average diameter of the mass body 160 incident on the seed layer 150 in this step may be 5 μm or more, more preferably 10 μm or more.
상기 질량체(160)는 승화(sublimation) 물질일 수 있고, 바람직하게 상기 승화 물질은 드라이아이스, 나프탈렌 및 아이오딘 중 어느 하나일 수 있다. 상기 질량체(160)로 승화 물질을 사용하는 경우, 질량체(160)가 씨드층(150)과 충돌한 후 기화되므로 씨드층(150) 상에 부산물이 존재하지 않을 수 있다. 따라서, 간단한 공정으로 씨드층(150)을 제거할 수 있고, 부산물 발생에 의한 추가 세정 공정이 불필요하다. The mass body 160 may be a sublimation material, and preferably, the sublimation material may be any one of dry ice, naphthalene, and iodine. When a sublimation material is used as the mass body 160, since the mass body 160 is vaporized after colliding with the seed layer 150, by-products may not exist on the seed layer 150. Therefore, the seed layer 150 can be removed by a simple process, and an additional cleaning process due to generation of by-products is unnecessary.
상기 질량체(160)를 입사하는 방법은 분말 상태의 질량체(160)를 캐리어 기체를 통해 운반하여 노즐로 방사하는 방법일 수 있다. The method of injecting the mass body 160 may be a method of transporting the powdered mass body 160 through a carrier gas and emitting it to a nozzle.
도 6은 음각 패턴 상에 형성된 씨드층(150) 상에 도전층(170)을 형성하는 단계를 도시한 것이다. 상기 도전층(170)을 형성하는 단계는 전해도금 공정 또는 무전해도금 공정을 수행하여 상기 도전층(170)을 형성할 수 있다. 종래의 스퍼터링 법에 의해 금속 배선을 형성하는 경우, 식각을 통해 불필요한 부분을 제거해야 했으나, 비용 및 시간이 많이 소요되고 기술적으로 난이도가 높아 실현성이 낮은 문제가 있었다. 또한, 구리를 도전성 물질로 사용하는 경우, 적합한 식각 물질이 없는 문제점이 있다. 본 발명의 실시 예는 종래의 스퍼터링 법 등을 이용하여 도전성 배선을 형성한 것에 비하여 빠르고 경제적으로 도금층을 형성할 수 있다.6 shows a step of forming the conductive layer 170 on the seed layer 150 formed on the intaglio pattern. In the forming of the conductive layer 170, the conductive layer 170 may be formed by performing an electroplating process or an electroless plating process. In the case of forming the metal wiring by the conventional sputtering method, unnecessary portions have to be removed through etching, but there is a problem in that the feasibility is low due to high technical difficulty and high cost and time. In addition, when copper is used as a conductive material, there is a problem that there is no suitable etching material. According to an exemplary embodiment of the present invention, a plating layer can be formed quickly and economically compared to forming a conductive wiring using a conventional sputtering method or the like.
상기 도전층(170)은 도전성을 갖는 물질로 이루어질 수 있고, 바람직하게는 구리(Cu), 코발트(Co), 구리 합금 또는 코발트 합금일 수 있다. 상기 도전층(170)은 상기 음각 패턴 상에 형성된 씨드층(150) 상 및 상기 씨드층(150)이 제거된 양각 패턴 상에 형성될 수 있다. 양각 패턴 상의 씨드층(150)은 앞선 공정에서 제거되지만, 전해도금법 및 무전해도금법을 수행하는 과정에서 도금층이 일부 형성될 수 있다. 또한, 앞선 공정에서 미쳐 제거되지 못한 씨드층(150)으로부터 성장하여 형성될 수 있다. The conductive layer 170 may be made of a material having conductivity, and preferably may be copper (Cu), cobalt (Co), a copper alloy, or a cobalt alloy. The conductive layer 170 may be formed on the seed layer 150 formed on the intaglio pattern and on the embossed pattern from which the seed layer 150 has been removed. The seed layer 150 on the embossed pattern is removed in the previous process, but a plating layer may be partially formed in the process of performing the electroplating method and the electroless plating method. In addition, it may be formed by growing from the seed layer 150 that has not been removed in the previous process.
상기 무전해도금법은 상기 씨드층(150) 상에 도금액을 공급하여 수행될 수 있다. 상기 무전해도금법은 금속층을 형성하기 위해 수행되는 통상적인 방법으로 수행될 수 있다. 형성되는 도금층이 구리막인 경우, 무전해도금을 위해 사용되는 도금액은 황산구리 등의 금속염, 포르말린 등의 산화제, 롯셀염 등의 착화제 및 수산화나트륨을 포함할 수 있다. The electroless plating method may be performed by supplying a plating solution onto the seed layer 150. The electroless plating method may be performed by a conventional method performed to form a metal layer. When the formed plating layer is a copper film, the plating solution used for electroless plating may include a metal salt such as copper sulfate, an oxidizing agent such as formalin, a complexing agent such as Rossel salt, and sodium hydroxide.
도 7은 도전층(170)을 형성하는 단계 이후에, CMP 공정을 수행하여 상기 씨드층(150)이 제거된 양각 패턴 상에 형성된 도금층을 제거한 모습을 도시한 것이다. CMP 공정은 도전층(170)이 형성된 기판(110)을 슬러리가 공급되는 패드에 문질러 물리적 반응 및 화학적 반응을 이용하여 제거하는 것으로, 통상적인 CMP 공정법을 적용할 수 있으며 특별히 제한되지 않는다. 7 shows a state in which the plating layer formed on the embossed pattern from which the seed layer 150 is removed is removed by performing a CMP process after the step of forming the conductive layer 170. The CMP process is to remove the substrate 110 on which the conductive layer 170 is formed using a physical reaction and a chemical reaction by rubbing the substrate 110 on which the slurry is supplied, and a conventional CMP process method may be applied and is not particularly limited.
본 발명의 실시 예를 따른 반도체 소자(100)의 제조 방법은, 양극 패턴 상에 형성된 씨드층(150)을 선택적으로 제거함으로써 양극 패턴 상의 도전층(170)을 상대적으로 적게 형성하도록 할 수 있기 때문에 CMP 공정을 짧은 시간동안 수행할 수 있을 뿐 아니라, 1회만을 수행하는 것만으로 도전층(170) 간의 분리가 가능하고, 과도한 CMP 공정에 따른 디싱 및 이로전 발생을 방지할 수 있다. In the method of manufacturing the semiconductor device 100 according to the embodiment of the present invention, the conductive layer 170 on the anode pattern can be formed relatively less by selectively removing the seed layer 150 formed on the anode pattern. In addition to performing the CMP process for a short time, it is possible to separate the conductive layers 170 by performing only once, and it is possible to prevent the occurrence of dishing and erosion due to an excessive CMP process.
도 8 내지 도 16은 본 발명의 다른 실시 예를 따르는 반도체 소자(100)의 제조 방법을 도시한 것이다.8 to 16 illustrate a method of manufacturing a semiconductor device 100 according to another embodiment of the present invention.
도 8 내지 도 16을 참조하면, 본 발명의 다른 실시 예를 따르는 반도체 소자(100)의 제조 방법은, 절연층(120)에 포토레지스트 패턴(180)을 형성하고, 상기 절연층(120)에 형성된 음각 패턴 및 양각 패턴을 형성하는 단계; 상기 음각 패턴 및 양각 패턴 상에 배치된 포토레지스트 패턴(180) 상에 베리어메탈층(140)을 형성하는 단계; 상기 베리어메탈층(140) 상에 씨드층(150)을 형성하는 단계; 상기 양각 패턴 상에 형성된 베리어메탈층(140) 상의 씨드층(150)을 제거하는 단계; 상기 양각 패턴 상에 배치된 포토레지스트 패턴(180)을 제거하는 단계; 및 음각 패턴 상에 형성된 씨드층(150) 상에 도전층(170)을 형성하는 단계;를 포함한다.8 to 16, in a method of manufacturing a semiconductor device 100 according to another embodiment of the present invention, a photoresist pattern 180 is formed on the insulating layer 120, and the insulating layer 120 is Forming the formed engraved pattern and the embossed pattern; Forming a barrier metal layer 140 on the photoresist pattern 180 disposed on the intaglio pattern and the relief pattern; Forming a seed layer 150 on the barrier metal layer 140; Removing the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern; Removing the photoresist pattern 180 disposed on the embossed pattern; And forming a conductive layer 170 on the seed layer 150 formed on the intaglio pattern.
도 8은 절연층(120)에 포토레지스트 패턴(180)을 형성하는 단계를 도시한 것이고, 도 2는 상기 절연층(120)에 형성된 음각 패턴 및 양각 패턴을 형성하는 단계를 도시한 것이다. 본 단계는 금속 배선이 배치될 영역을 형성하는 단계이다. 상기 음각 패턴 내부에 구리 등의 전도성 물질이 매립되도록 형성함으로써 일정한 형상을 가진 금속 배선을 제조할 수 있다. 도 9를 참조하면, 음각 패턴의 하부 중 일부는 관통전극(130)과 연결되도록 형성될 수 있다. 이로써 금속 배선이 관통전극(130)을 통해 반도체 소자(100) 하부의 전기 시스템(게이트 등)과 전기적으로 연결될 수 있다. 8 illustrates a step of forming a photoresist pattern 180 on the insulating layer 120, and FIG. 2 illustrates a step of forming an intaglio pattern and an embossed pattern formed on the insulating layer 120. This step is a step of forming a region in which the metal wiring is to be arranged. Metal wiring having a certain shape may be manufactured by forming a conductive material such as copper to be buried inside the intaglio pattern. Referring to FIG. 9, a portion of the lower portion of the intaglio pattern may be formed to be connected to the through electrode 130. As a result, the metal wiring may be electrically connected to an electrical system (gate, etc.) under the semiconductor device 100 through the through electrode 130.
상기 음각 패턴 및 양각 패턴은 리소그래피(Lithography) 공정을 통해 수행될 수 있다. 도 8을 참조하면, 리소그래피 공정을 이용하여 음각 패턴 및 양각 패턴을 형성하는 방법은 포토레지스트를 절연층(120) 상에 패터닝하여 형성한 후 그 이외의 부분을 제거함으로써 수행될 수 있다. 이후 외부로 노출된 절연층(120)을 식각 공정을 통해 제거함으로써 절연층(120)에 음각 패턴 및 양각 패턴을 형성할 수 있다. The intaglio pattern and the relief pattern may be performed through a lithography process. Referring to FIG. 8, a method of forming an intaglio pattern and an intaglio pattern using a lithography process may be performed by patterning a photoresist on the insulating layer 120 and then removing other portions. Thereafter, by removing the insulating layer 120 exposed to the outside through an etching process, an intaglio pattern and a relief pattern may be formed on the insulating layer 120.
상기 절연층(120)은 일반적으로 반도체 소자(100) 제조에 사용되는 기판(110)일 수 있으며, 기판(110) 상에 도포되어 형성된 절연성을 가진 물질의 층일 수 있다. 상기 기판(110)은 실리콘 기판, 게르마늄 기판 또는 실리콘-게르마늄 기판일 수 있으며, 내부에 불순물 원소를 포함하여 일정한 수준의 전도성을 갖는 것을 포함할 수 있다. 상기 절연성을 가진 물질은 반도체 소자 제조에서 절연층 형성 시 일반적으로 사용하는 물질일 수 있으며, 다양한 산화물, 질화물 또는 산질화물을 포함할 수 있다. In general, the insulating layer 120 may be a substrate 110 used for manufacturing the semiconductor device 100, and may be a layer of an insulating material formed by being coated on the substrate 110. The substrate 110 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate, and may include an impurity element therein and having a certain level of conductivity. The insulating material may be a material generally used when forming an insulating layer in semiconductor device manufacturing, and may include various oxides, nitrides, or oxynitrides.
도 10은 상기 음각 패턴 및 양각 패턴 상에 배치된 포토레지스트 패턴(180) 상에 베리어메탈층(140)을 형성하는 단계를 도시한 것이다. 본 단계는 CVD(Chemical vapor deposition) 또는 ALD (Atomic Layer Deposition) 등의 다양한 증착방법을 이용하여 수행될 수 있다. 상기 베리어메탈층(140)은 Ta막 또는 TaN막의 단일막이거나, Ta막과 TaN막의 적층막일 수 있으며 특별히 제한되지 않는다. 상기 베리어메탈층(140)의 두께는 필요에 따라 선택될 수 있으며 수 nm에서 수 백 nm일 수 있다. FIG. 10 shows a step of forming a barrier metal layer 140 on the photoresist pattern 180 disposed on the intaglio pattern and the relief pattern. This step may be performed using various deposition methods such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The barrier metal layer 140 may be a single layer of a Ta layer or a TaN layer, or a stacked layer of a Ta layer and a TaN layer, and is not particularly limited. The thickness of the barrier metal layer 140 may be selected as necessary and may be several nm to several hundreds nm.
도 10을 참조하면, 상기 베리어메탈층(140)은 음각 패턴 및 양각 패턴을 따라 일정한 두께를 갖도록 형성될 수 있다. Referring to FIG. 10, the barrier metal layer 140 may be formed to have a constant thickness along an intaglio pattern and a relief pattern.
도 11은 상기 베리어메탈층(140) 상에 씨드층(150)을 형성하는 단계를 도시한 것이다. 본 단계는 CVD(Chemical vapor deposition), PVD(Physical Vapor Deposition), 스퍼터링(sputtering) 또는 ALD (Atomic Layer Deposition) 등의 다양한 증착방법을 이용하여 수행될 수 있다. 상기 씨드층(150)은 수 nm 또는 수 천 nm의 두께로 형성될 수 있으며 특별히 제한되지 않는다.11 shows a step of forming the seed layer 150 on the barrier metal layer 140. This step may be performed using various deposition methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition (ALD). The seed layer 150 may be formed to a thickness of several nm or thousands of nm, and is not particularly limited.
씨드층(150)은 도전층(170)을 전해도금법 또는 무전해도금법을 이용하여 형성하는 단계에서 상기 도전층(170)을 형성하기 위한 씨드 역할을 수행할 수 있다. 이를 위해 상기 씨드층(150)은 바람직하게 팔라듐(Pd)를 포함할 수 있다. 도전층을 전해도금법으로 형성할 경우, 도전층으로 구리(Cu)를 형성하는 경우에는 씨드층으로 seed Cu를 사용할 수 있고, 도전층으로 코발트(Co)를 형성하는 경우에는 씨드층으로 seed Co를 사용할 수 있다. 상기 seed Cu 또는 seed Co는 스퍼터링(sputtering), CVD, ALD 등으로 증착할 수 있다. 도전층을 무전해도금법으로 형성할 경우, 도전층(Cu 또는 Co)을 도금하기 전에 베리어메탈층 상에 액티베이터(Activator)로서 기능을 수행하는 씨드층을 형성할 수 있다. 상기 씨드층은 베리어메탈층 상에 팔라듐(Pd)을 박막 또는 입자 형태로 증착 또는 도금하여 형성할 수 있으며, 이 경우, 상기 베리어메탈층 표면을 자가촉매적(autocatalytic)으로 바꾸어 줄 수 있다. The seed layer 150 may serve as a seed for forming the conductive layer 170 in the step of forming the conductive layer 170 using an electroplating method or an electroless plating method. To this end, the seed layer 150 may preferably include palladium (Pd). When the conductive layer is formed by electroplating, seed Cu can be used as the seed layer when copper (Cu) is formed as the conductive layer, and seed Co is used as the seed layer when cobalt (Co) is formed as the conductive layer. Can be used. The seed Cu or seed Co may be deposited by sputtering, CVD, ALD, or the like. When the conductive layer is formed by an electroless plating method, a seed layer that functions as an activator may be formed on the barrier metal layer before plating the conductive layer (Cu or Co). The seed layer may be formed by depositing or plating palladium (Pd) in the form of a thin film or particles on the barrier metal layer, and in this case, the surface of the barrier metal layer may be changed to autocatalytic.
도 17 및 도 18은 무전해도금 공정의 원리를 도시한 것이다. 도 17 및 도 18 에서, 베리어메탈층 상에 형성된 씨드층에 포함된 Pd 입자에서 무전해도금액에 포함되어 있는 Cu이온이 환원됨으로써 구리막이 형성되고, 일단 구리막이 형성되면 상기 구리막 상에서 계속적으로 환원반응이 일어나 상기 구리막의 두께가 증가할 수 있다.17 and 18 show the principle of the electroless plating process. In FIGS. 17 and 18, Cu ions contained in the electroless solution are reduced from Pd particles included in the seed layer formed on the barrier metal layer to form a copper film, and once the copper film is formed, the copper film is continuously reduced. A reaction may occur to increase the thickness of the copper layer.
도 12는 상기 양각 패턴 상에 형성된 베리어메탈층(140) 상의 씨드층(150)을 제거하는 단계를 도시한 것이고, 도 13은 양각 패턴 상의 씨드층(150)이 제거된 모습을 도시한 것이다. 본 단계에서 상기 양각 패턴 상에 형성된 베리어메탈층(140) 상의 씨드층(150)을 선택적으로 제거할 수 있다. 이를 통해 도전층(170)을 형성하는 경우 양각 패턴 상에서 도전층(170)이 형성되는 양을 줄일 수 있고, 양각 패턴 상에 형성된 도전층(170)을 제거하기 위한 CMP 공정을 수행함에 있어서, 공정 시간 및 공정 횟수를 감소시킬 수 있다. FIG. 12 shows a step of removing the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern, and FIG. 13 shows a state in which the seed layer 150 on the embossed pattern is removed. In this step, the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern may be selectively removed. In the case of forming the conductive layer 170 through this, it is possible to reduce the amount of the conductive layer 170 formed on the embossed pattern, and in performing the CMP process for removing the conductive layer 170 formed on the embossed pattern, the process Time and number of processes can be reduced.
상기 양각 패턴 상에 형성된 베리어메탈층(140) 상의 씨드층(150)을 제거하는 단계는, 상기 양각 패턴 상에 형성된 베리어메탈층(140) 상의 씨드층(150) 상에 질량체(160)를 분사하여 상기 양각 패턴 상에 형성된 베리어메탈층(140) 상의 씨드층(150)을 선택적으로 제거하는 것일 수 있다. In the step of removing the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern, the mass body 160 is sprayed onto the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern. Thus, the seed layer 150 on the barrier metal layer 140 formed on the embossed pattern may be selectively removed.
상기 씨드층(150)을 제거하는 단계는 씨드층(150)에 질량체(160)를 분사하여 수행될 수 있다. 상기 질량체(160)를 분사하는 방법은, 상기 포토레이지스층에 수직인 방향으로부터 소정의 각도를 갖도록 상기 질량체(160)를 분사하는 것일 수 있다. 도 12를 참조하면, 질량체(160)가 씨드층(150)에 수직인 방향(점선)에 대하여 소정의 각도(θ)로 경사진 방향으로 분사됨을 알 수 있다. 이를 통해 상기 질량체(160)가 씨드층(150)에 충돌하되, 음각 패턴 상에 배치된 씨드층(150)에는 충돌하지 않도록 제어할 수 있다. 상기 질량체(160)가 입사되는 각도는 씨드층(150)에 수직인 방향에 대하여 20 내지 70°일 수 있다. 상기 질량체(160)가 입사되는 각도가 20°미만인 경우에는 질량체(160)가 음극 패턴 상의 씨드층(150)에 충돌하는 문제가 발생할 수 있다. 상기 질량체(160)가 입사되는 각도가 70°초과인 경우에는 질량체(160)가 씨드층(150)에 충분한 충격량을 전달하지 못하기 때문에 씨드층(150)의 제거가 충분히 일어나지 않을 수 있다. The step of removing the seed layer 150 may be performed by spraying the mass body 160 onto the seed layer 150. The method of spraying the mass body 160 may be spraying the mass body 160 to have a predetermined angle from a direction perpendicular to the photolaser layer. Referring to FIG. 12, it can be seen that the mass body 160 is sprayed in a direction inclined at a predetermined angle θ with respect to the direction (dotted line) perpendicular to the seed layer 150. Through this, it is possible to control so that the mass body 160 collides with the seed layer 150 but does not collide with the seed layer 150 disposed on the intaglio pattern. An angle at which the mass body 160 is incident may be 20 to 70° with respect to a direction perpendicular to the seed layer 150. When the incident angle of the mass body 160 is less than 20°, the mass body 160 may collide with the seed layer 150 on the cathode pattern. When the incident angle of the mass body 160 exceeds 70°, since the mass body 160 does not transmit a sufficient amount of impact to the seed layer 150, the seed layer 150 may not be sufficiently removed.
상기 질량체(160)는 씨드층(150)이 제거될 수 있을 정도의 충격량을 전달할 수 있는 질량을 가질 수 있고, 소정의 각도로 입사하는 경우 음극 패턴 내부로 유입되지 않을 정도의 크기를 가지는 것이 바람직하다. 이를 위해 본 단계에서 씨드층(150)으로 입사되는 질량체(160)의 평균 지름은 5μm 이상, 보다 바람직하게는 10μm 이상일 수 있다. The mass body 160 may have a mass capable of transmitting an amount of impact sufficient to remove the seed layer 150, and it is preferable that the mass body 160 has a size such that it does not flow into the cathode pattern when incident at a predetermined angle. Do. To this end, the average diameter of the mass body 160 incident on the seed layer 150 in this step may be 5 μm or more, more preferably 10 μm or more.
상기 질량체(160)는 승화(sublimation) 물질일 수 있고, 바람직하게 상기 승화 물질은 드라이아이스, 나프탈렌 및 아이오딘 중 어느 하나일 수 있다. 상기 질량체(160)로 승화 물질을 사용하는 경우, 질량체(160)가 씨드층(150)과 충돌한 후 기화되므로 씨드층(150) 상에 부산물이 존재하지 않을 수 있다. 따라서, 간단한 공정으로 씨드층(150)을 제거할 수 있고, 부산물 발생에 의한 추가 세정 공정이 불필요하다. The mass body 160 may be a sublimation material, and preferably, the sublimation material may be any one of dry ice, naphthalene, and iodine. When a sublimation material is used as the mass body 160, since the mass body 160 is vaporized after colliding with the seed layer 150, by-products may not exist on the seed layer 150. Therefore, the seed layer 150 can be removed by a simple process, and an additional cleaning process due to generation of by-products is unnecessary.
상기 질량체(160)를 입사하는 방법은 분말 상태의 질량체(160)를 캐리어 기체를 통해 운반하여 노즐로 방사하는 방법일 수 있다.The method of injecting the mass body 160 may be a method of transporting the powdered mass body 160 through a carrier gas and emitting it to a nozzle.
도 14는 상기 양각 패턴 상에 배치된 포토레지스트 패턴(180)을 제거하는 단계를 도시한 것이다. 앞선 단계에서 포토레지스트 상의 씨드층(150)을 제거하였기 때문에, 포토레지스트 제거가 용이하게 이루어질 수 있다. 본 단계를 통해 포토레지스트 상의 씨드층(150)이 와전하게 제거되며, 이후 도전층(170)을 형성할 때, 음각 패턴 상의 씨드층(150) 상에서만 도전층(170)이 형성되도록 할 수 있다. 포토레지스트를 제거하는 공정은 반도체 소자 제조 공정에서 통상적으로 수행되는 방법에 의할 수 있으며, 특별히 제한되지 않는다.14 illustrates a step of removing the photoresist pattern 180 disposed on the embossed pattern. Since the seed layer 150 on the photoresist was removed in the previous step, photoresist removal can be easily performed. Through this step, the seed layer 150 on the photoresist is completely removed, and then when the conductive layer 170 is formed, the conductive layer 170 may be formed only on the seed layer 150 on the intaglio pattern. . The process of removing the photoresist may be performed by a method commonly performed in a semiconductor device manufacturing process, and is not particularly limited.
도 15는 음각 패턴 상에 형성된 씨드층(150) 상에 도전층(170)을 형성하는 단계를 도시한 것이다. 상기 도전층(170)을 형성하는 단계는 전해도금 공정 또는 무전해도금 공정을 수행하여 상기 도전층(170)을 형성할 수 있다. 종래의 스퍼터링 법에 의해 도전성 배선을 형성하는 경우, 식각을 통해 불필요한 부분을 제거해야 했으나, 비용 및 시간이 많이 소요되고 기술적으로 난이도가 높아 실현성이 낮은 문제가 있었다. 또한, 구리를 도전성 물질로 사용하는 경우, 적합한 식각 물질이 없는 문제점이 있다. 본 발명의 실시 예는 무전해도금법을 이용하기 때문에, 종래의 스퍼터링 법 등을 이용하여 도전성 배선을 형성한 것에 비하여 빠르고 경제적으로 도금층을 형성할 수 있다.15 shows a step of forming the conductive layer 170 on the seed layer 150 formed on the intaglio pattern. In the forming of the conductive layer 170, the conductive layer 170 may be formed by performing an electroplating process or an electroless plating process. In the case of forming the conductive wiring by the conventional sputtering method, unnecessary portions have to be removed through etching, but there is a problem in that the practicality is low due to high technical difficulty and high cost and time. In addition, when copper is used as a conductive material, there is a problem in that there is no suitable etching material. Since the embodiment of the present invention uses an electroless plating method, a plating layer can be formed quickly and economically compared to forming a conductive wiring using a conventional sputtering method or the like.
상기 도전층(170)은 도전성을 갖는 물질로 이루어질 수 있고, 바람직하게는 구리(Cu), 코발트(Co), 구리 합금 또는 코발트 합금일 수 있다. 상기 도전층(170)은 상기 음각 패턴 상에 형성된 씨드층(150) 상 및 상기 씨드층(150)이 제거된 양각 패턴 상에 형성될 수 있다. 양각 패턴 상의 씨드층(150)은 앞선 공정에서 제거되지만, 전해도금법 및 무전해도금법을 수행하는 과정에서 도금층이 일부 형성될 수 있다. 또한, 앞선 공정에서 미쳐 제거되지 못한 씨드층(150)으로부터 성장하여 형성될 수 있다. The conductive layer 170 may be made of a material having conductivity, and preferably may be copper (Cu), cobalt (Co), a copper alloy, or a cobalt alloy. The conductive layer 170 may be formed on the seed layer 150 formed on the intaglio pattern and on the embossed pattern from which the seed layer 150 has been removed. The seed layer 150 on the embossed pattern is removed in the previous process, but a plating layer may be partially formed in the process of performing the electroplating method and the electroless plating method. In addition, it may be formed by growing from the seed layer 150 that has not been removed in the previous process.
상기 무전해도금법은 상기 씨드층(150) 상에 도금액을 공급하여 수행될 수 있다. 상기 무전해도금법은 금속층을 형성하기 위해 수행되는 통상적인 방법으로 수행될 수 있다. 형성되는 도금층이 구리막인 경우, 무전해도금을 위해 사용되는 도금액은 황산구리 등의 금속염, 포르말린 등의 산화제, 롯셀염 등의 착화제 및 수산화나트륨을 포함할 수 있다.The electroless plating method may be performed by supplying a plating solution onto the seed layer 150. The electroless plating method may be performed by a conventional method performed to form a metal layer. When the formed plating layer is a copper film, the plating solution used for electroless plating may include a metal salt such as copper sulfate, an oxidizing agent such as formalin, a complexing agent such as Rossel salt, and sodium hydroxide.
도 16은 도전층(170)을 형성하는 단계 이후에, CMP 공정을 수행하여 상기 씨드층(150)이 제거된 양각 패턴 상에 형성된 도금층을 제거한 모습을 도시한 것이다. CMP 공정은 도전층(170)이 형성된 기판(110)을 슬러리가 공급되는 패드에 문질러 물리적 반응 및 화학적 반응을 이용하여 제거하는 것으로, 통상적인 CMP 공정법을 적용할 수 있으며 특별히 제한되지 않는다. 16 illustrates a state in which the plating layer formed on the embossed pattern from which the seed layer 150 is removed is removed by performing a CMP process after the step of forming the conductive layer 170. The CMP process is to remove the substrate 110 on which the conductive layer 170 is formed using a physical reaction and a chemical reaction by rubbing the substrate 110 on which the slurry is supplied, and a conventional CMP process method may be applied and is not particularly limited.
본 발명은 상술한 실시 형태 및 첨부된 도면에 의해 한정되는 것이 아니며 첨부된 청구범위에 의해 한정하고자 한다. 따라서, 청구범위에 기재된 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 당 기술분야의 통상의 지식을 가진 자에 의해 다양한 형태의 치환, 변형 및 변경이 가능할 것이며, 이 또한 본 발명의 범위에 속한다고 할 것이다. The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited by the appended claims. Therefore, various types of substitutions, modifications and changes will be possible by those of ordinary skill in the art within the scope not departing from the technical spirit of the present invention described in the claims, and this also belongs to the scope of the present invention. something to do.
[부호의 설명][Explanation of code]
100: 반도체 소자, 110: 기판, 120: 절연층, 130: 관통전극, 140: 베리어메탈층, 150: 씨드층 , 160: 질량체, 170: 도전층, 180: 포토레지스트 패턴, 190: 팔라듐 원소100: semiconductor element, 110: substrate, 120: insulating layer, 130: through electrode, 140: barrier metal layer, 150: seed layer, 160: mass body, 170: conductive layer, 180: photoresist pattern, 190: palladium element

Claims (7)

  1. 절연층에 음각 패턴 및 양각 패턴을 형성하는 단계;Forming an intaglio pattern and a relief pattern on the insulating layer;
    상기 음각 패턴 및 양각 패턴 상에 베리어메탈층을 형성하는 단계;Forming a barrier metal layer on the intaglio pattern and the relief pattern;
    상기 베리어메탈층 상에 씨드층을 형성하는 단계;Forming a seed layer on the barrier metal layer;
    상기 양각 패턴 상에 형성된 베리어메탈층 상의 씨드층을 제거하는 단계; 및Removing the seed layer on the barrier metal layer formed on the embossed pattern; And
    상기 음각 패턴 상에 형성된 씨드층 상에 도전층을 형성하는 단계;를 포함하는,Including, forming a conductive layer on the seed layer formed on the intaglio pattern;
    반도체 소자의 제조 방법. Method of manufacturing a semiconductor device.
  2. 제1항에 있어서,The method of claim 1,
    상기 양각 패턴 상에 형성된 베리어메탈층 상의 씨드층을 제거하는 단계는,The step of removing the seed layer on the barrier metal layer formed on the embossed pattern,
    상기 양각 패턴 상에 형성된 베리어메탈층 상의 씨드층 상에 질량체를 분사하여 상기 양각 패턴 상에 형성된 베리어메탈층 상의 씨드층을 선택적으로 제거하는,Selectively removing the seed layer on the barrier metal layer formed on the embossed pattern by spraying a mass on the seed layer on the barrier metal layer formed on the embossed pattern,
    반도체 소자의 제조 방법.Method of manufacturing a semiconductor device.
  3. 제2항에 있어서,The method of claim 2,
    상기 질량체는 승화(sublimation) 물질인,The mass is a sublimation material,
    반도체 소자의 제조 방법.Method of manufacturing a semiconductor device.
  4. 제1항에 있어서,The method of claim 1,
    상기 씨드층은 팔라듐(Pd)를 포함하는The seed layer includes palladium (Pd)
    반도체 소자의 제조 방법.Method of manufacturing a semiconductor device.
  5. 제1항에 있어서,The method of claim 1,
    상기 도전층을 형성하는 단계에서, 상기 도전층은 상기 음각 패턴 상에 형성된 씨드층 상 및 상기 씨드층이 제거된 양각 패턴 상에 형성되고,In the step of forming the conductive layer, the conductive layer is formed on the seed layer formed on the intaglio pattern and on the embossed pattern from which the seed layer has been removed,
    상기 도전층을 형성하는 단계 이후에, CMP 공정을 수행하여 상기 씨드층이 제거된 양각 패턴 상에 형성된 도금층을 제거하는 After the step of forming the conductive layer, a CMP process is performed to remove the plating layer formed on the embossed pattern from which the seed layer has been removed.
    반도체 소자의 제조 방법.Method of manufacturing a semiconductor device.
  6. 제1항에 있어서,The method of claim 1,
    상기 도전층을 형성하는 단계는 전해도금 공정 또는 무전해도금 공정을 수행하여 상기 도전층을 형성하는The step of forming the conductive layer may include forming the conductive layer by performing an electroplating process or an electroless plating process.
    반도체 소자의 제조 방법.Method of manufacturing a semiconductor device.
  7. 절연층에 포토레지스트 패턴을 형성하고, 상기 절연층에 형성된 음각 패턴 및 양각 패턴을 형성하는 단계;Forming a photoresist pattern on the insulating layer, and forming an intaglio pattern and a relief pattern formed on the insulating layer;
    상기 음각 패턴 및 양각 패턴 상에 배치된 포토레지스트 패턴 상에 베리어메탈층을 형성하는 단계;Forming a barrier metal layer on the intaglio pattern and the photoresist pattern disposed on the intaglio pattern;
    상기 베리어메탈층 상에 씨드층을 형성하는 단계;Forming a seed layer on the barrier metal layer;
    상기 양각 패턴 상에 형성된 베리어메탈층 상의 씨드층을 제거하는 단계;Removing the seed layer on the barrier metal layer formed on the embossed pattern;
    상기 양각 패턴 상에 배치된 포토레지스트 패턴을 제거하는 단계; 및Removing the photoresist pattern disposed on the embossed pattern; And
    상기 음각 패턴 상에 형성된 씨드층 상에 도전층을 형성하는 단계;를 포함하는,Including, forming a conductive layer on the seed layer formed on the intaglio pattern;
    반도체 소자의 제조 방법. Method of manufacturing a semiconductor device.
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