WO2020179026A1 - Display device and method for manufacturing same - Google Patents
Display device and method for manufacturing same Download PDFInfo
- Publication number
- WO2020179026A1 WO2020179026A1 PCT/JP2019/008924 JP2019008924W WO2020179026A1 WO 2020179026 A1 WO2020179026 A1 WO 2020179026A1 JP 2019008924 W JP2019008924 W JP 2019008924W WO 2020179026 A1 WO2020179026 A1 WO 2020179026A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- insulating film
- interlayer insulating
- display device
- gate
- opening
- Prior art date
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Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
Definitions
- the present invention relates to a display device and a manufacturing method thereof.
- a self-luminous organic EL display device using an organic electroluminescence (hereinafter also referred to as EL) element has been attracting attention.
- EL organic electroluminescence
- the active matrix driving type organic EL display device for example, a thin film transistor (hereinafter, also referred to as a TFT) is provided for each sub-pixel which is a minimum unit of an image.
- a top gate type TFT having a channel layer made of low temperature polysilicon is provided in a peripheral region, and a top gate type TFT having a channel layer made of an oxide semiconductor is provided in a display region.
- An organic EL display device is disclosed.
- a top-gate TFT is, for example, provided on a base substrate via a base coat film, a semiconductor layer including an intrinsic region and a pair of conductor regions, and a gate insulating film provided so as to cover the semiconductor layer, A gate electrode provided on the gate insulating film so as to overlap with the intrinsic region of the semiconductor layer, an interlayer insulating film provided so as to cover the gate electrode, and a pair of conductor regions of the semiconductor layer provided on the interlayer insulating film. And a source electrode and a drain electrode that are electrically connected to each other.
- the interlayer insulating film is formed of, for example, an inorganic insulating film formed by a CVD (Chemical Vapor Deposition) method, and if foreign matter is present on the film formation surface, the foreign matter is used as a nucleus to form the CVD film. Due to abnormal growth, a cavity called a void may be formed in the interlayer insulating film. Then, for example, the gate electrode and the source electrode and the drain electrode are likely to be short-circuited, so that a point defect, a line defect, or the like is likely to occur in the display region where an image is displayed.
- CVD Chemical Vapor Deposition
- the present invention has been made in view of the above points, and an object thereof is to suppress the occurrence of short-circuit defects due to voids formed in the interlayer insulating film.
- a display device includes a base substrate, a semiconductor layer, a gate insulating film, a gate metal layer, a first interlayer insulating film, an intermediate metal layer, and A two-layer insulating film, an organic insulating film, and a source metal layer are laminated in this order, a thin film layer in which a thin film and a capacitor are arranged for each sub pixel, and a light emitting element provided on the thin film layer and a light emitting element is arranged for each sub pixel.
- the thin film is a first thin film having a first semiconductor layer provided as the semiconductor layer, a gate insulating film, and a first gate electrode provided as the gate metal layer.
- the capacitor includes the first gate electrode, the first interlayer insulating film, and the capacitor electrode provided as the intermediate metal layer and arranged to overlap the first gate electrode in plan view.
- the capacitive electrode is provided with a first opening so as to overlap the first gate electrode in a plan view and penetrate the capacitive electrode, and the first interlayer insulating film and the second interlayer insulating film are provided.
- the organic insulating film is arranged inside the peripheral edge of the first opening in a plan view, and a second opening is provided so as to penetrate the first interlayer insulating film and the second interlayer insulating film.
- the first contact hole is provided inside the peripheral edge of the second opening in a plan view, and the first contact hole is provided so as to penetrate the organic insulating film, and the first gate electrode is passed through the first contact hole. Is electrically connected to a connection wiring provided as the source metal layer, and the organic insulating film is provided so as to cover a side surface of the second opening.
- the method for manufacturing a display device includes a thin film transistor layer forming step of forming a thin film transistor layer and a thin film transistor layer on each of which a sub pixel is disposed on a base substrate;
- a light emitting element layer forming step of forming a light emitting element layer in which a light emitting element is arranged is provided for each, and the thin film has a first thin film, and the first thin film includes a first semiconductor layer and a first semiconductor layer.
- the gate insulating film provided above and the first gate electrode provided on the gate insulating film are provided, and the capacitor is the first gate electrode and the first gate electrode provided on the first gate electrode.
- An interlayer insulating film and a capacitive electrode provided on the first interlayer insulating film and arranged so as to overlap the first gate electrode in a plan view are provided, and the thin film layer forming step is performed on the base substrate.
- the intermediate metal film is formed.
- the second interlayer insulating film forming step of forming the second interlayer insulating film and the first interlayer insulating film and the second interlayer insulating film were penetrated so as to be arranged inside the peripheral edge of the first opening in a plan view.
- the organic insulating film is patterned and viewed in a plan view.
- the organic insulating film is patterned so as to cover the side surface of the second opening.
- the organic insulating film laminated between the second interlayer insulating film and the source metal layer covers the side surface of the second opening formed in the first interlayer insulating film and the second interlayer insulating film. Therefore, it is possible to suppress the occurrence of short-circuit defects due to voids formed in the interlayer insulating film.
- FIG. 1 is a plan view showing a schematic configuration of an organic EL display device according to a first embodiment of the present invention.
- FIG. 2 is a plan view showing a schematic configuration of a display region of the organic EL display device according to the first embodiment of the present invention.
- FIG. 3 is a plan view of a TFT layer forming the organic EL display device according to the first embodiment of the present invention.
- FIG. 4 is an equivalent circuit diagram of a TFT layer that constitutes the organic EL display device according to the first embodiment of the present invention.
- FIG. 5 is a cross-sectional view of the organic EL display device taken along the line VV in FIG.
- FIG. 6 is a cross-sectional view of the TFT layer constituting the organic EL display device taken along the line VI-VI in FIG.
- FIG. 7 is a cross-sectional view showing an organic EL layer forming the organic EL display device according to the first embodiment of the present invention.
- FIG. 8 is a cross-sectional view schematically showing a laminated form of thin films formed on the base substrate when manufacturing the organic EL display device according to the first embodiment of the present invention.
- FIG. 9 is a cross-sectional view showing a step of forming a resist pattern in the opening forming step of the method for manufacturing an organic EL display device according to the first embodiment of the present invention, and corresponds to FIG. 5.
- FIG. 5 is a cross-sectional view showing an organic EL layer forming the organic EL display device according to the first embodiment of the present invention.
- FIG. 10 is a cross-sectional view showing a step of forming a resist pattern in the opening forming step of the method for manufacturing an organic EL display device according to the first embodiment of the present invention, and is a diagram corresponding to FIG. 6.
- FIG. 11 is a cross-sectional view showing a step of forming a second opening in the opening forming step of the method for manufacturing an organic EL display device according to the first embodiment of the present invention, and is a view corresponding to FIG. ..
- FIG. 12 is a cross-sectional view showing a step of forming a third opening in the opening forming step of the method for manufacturing an organic EL display device according to the first embodiment of the present invention, and is a view corresponding to FIG. 6. .. FIG.
- FIG. 13 is a cross-sectional view showing a step of applying an organic insulating film in the contact hole forming step of the method for manufacturing an organic EL display device according to the first embodiment of the present invention, and is a view corresponding to FIG. 5.
- FIG. 14 is a cross-sectional view showing a step of applying an organic insulating film in the contact hole forming step of the method for manufacturing an organic EL display device according to the first embodiment of the present invention, and is a diagram corresponding to FIG. 6.
- FIG. 15 is a cross-sectional view showing a step of patterning the organic insulating film in the contact hole forming step of the method for manufacturing an organic EL display device according to the first embodiment of the present invention, which corresponds to FIG. 5.
- FIG. 5 is a cross-sectional view showing a step of applying an organic insulating film in the contact hole forming step of the method for manufacturing an organic EL display device according to the first embodiment of the present invention, which corresponds to FIG. 5.
- FIG. 16 is a cross-sectional view showing a step of patterning the organic insulating film in the contact hole forming step of the method for manufacturing an organic EL display device according to the first embodiment of the present invention, and is a diagram corresponding to FIG. 6.
- FIG. 17 is a cross-sectional view showing a source metal layer forming step of the method for manufacturing the organic EL display device according to the first embodiment of the present invention, which is a view corresponding to FIG. 5.
- FIG. 18 is a cross-sectional view showing a source metal layer forming step of the method for manufacturing the organic EL display device according to the first embodiment of the present invention, and is a view corresponding to FIG. 6.
- FIG. 19 is a cross-sectional view of the organic EL display device according to the second embodiment of the present invention and is a view corresponding to FIG. 20 is a cross-sectional view of the organic EL display device according to the second embodiment of the present invention, which is a view corresponding to FIG. 6.
- FIG. 21 is a cross-sectional view showing a step of forming a resist pattern in the opening forming step of the method for manufacturing an organic EL display device according to the second embodiment of the present invention, which corresponds to FIG. 22 is a cross-sectional view showing a step of forming a resist pattern in the opening forming step of the method for manufacturing an organic EL display device according to the second embodiment of the present invention, and is a diagram corresponding to FIG. FIG.
- FIG. 23 is a cross-sectional view showing a step of forming the second opening in the opening forming step of the method for manufacturing an organic EL display device according to the second embodiment of the present invention, and is a view corresponding to FIG. 19. ..
- FIG. 24 is a cross-sectional view showing a step of forming a third opening in the opening forming step of the method for manufacturing an organic EL display device according to the second embodiment of the present invention, and is a view corresponding to FIG. 20. ..
- FIG. 1 is a plan view showing a schematic configuration of the organic EL display device 50a of the present embodiment.
- 2 is a plan view showing a schematic configuration of the display area D of the organic EL display device 50a.
- FIG. 3 is a plan view of the TFT layer 30a that constitutes the organic EL display device 50a.
- FIG. 4 is an equivalent circuit diagram of the TFT layer 30a. 5 and 6 are cross-sectional views of the organic EL display device 50a taken along line VV and line VI-VI in FIG.
- the organic EL display device 50a includes, for example, a rectangular display area D for displaying an image and a frame area F provided around the display area D.
- the rectangular display area D is illustrated, but the rectangular shape may have, for example, a shape in which the sides are arcuate, a shape in which the corners are arcuate, or a part of the sides.
- a substantially rectangular shape such as a shape with a cutout is also included.
- a plurality of sub-pixels P are arranged in a matrix in the display area D. Further, in the display area D, as shown in FIG. 2, for example, a sub-pixel P having a red light-emitting area Er for displaying a red color, a sub-pixel P having a green light-emitting area Eg for performing a green color display, And sub-pixels P having a blue light emitting region Eb for displaying blue are provided adjacent to each other. In the display area D, for example, one pixel is configured by three adjacent sub-pixels P having the red light emitting area Er, the green light emitting area Eg, and the blue light emitting area Eb.
- a terminal portion T is provided at the right end of the frame area F in FIG. Further, in the frame region F, as shown in FIG. 1, between the display region D and the terminal portion T, a bent portion B which can be bent at 180° (in a U shape) with the longitudinal direction in the drawing as a bending axis. Are provided so as to extend in one direction (vertical direction in the figure).
- the organic EL display device 50a includes a resin substrate layer 10 provided as a base substrate, a TFT layer 30a provided on the resin substrate layer 10, and a light emitting element on the TFT layer 30a.
- the organic EL element layer 40 provided as a layer and the sealing film 45 provided on the organic EL element layer 40 are provided.
- the resin substrate layer 10 is made of, for example, a polyimide resin or the like.
- the TFT layer 30a includes a base coat film 11, a semiconductor layer (for example, a first semiconductor layer 12a), a gate insulating film 13, a gate metal layer (for example, a gate line 14g), a first interlayer, which are sequentially provided on the resin substrate layer 10.
- the insulating film 15, the intermediate metal layer (for example, the capacitor electrode 16c), the second interlayer insulating film 17, the organic insulating film 18, the source metal layer (for example, the source line 19f), and the planarization film 20 are provided.
- the TFT layer 30a includes a base coat film 11 provided on the resin substrate layer 10 and a first initialization provided on the base coat film 11 for each sub-pixel P.
- TFT 9a threshold voltage compensation TFT 9b, write control TFT 9c, drive TFT 9d, power supply TFT 9e, light emission control TFT 9f, second initialization TFT 9g and capacitor 9h, and flattening film 20 provided on each TFT 9a to 9g and capacitor 9h. Equipped with.
- the TFT layer 30a is provided with a plurality of gate lines 14g so as to extend parallel to each other in the lateral direction in the drawings.
- the TFT layer 30a is provided with a plurality of light emission control lines 14e as gate metal layers so as to extend in the lateral direction in FIG.
- FIGS. 1 the TFT layer 30a
- the TFT layer 30a is provided with a plurality of initialization power supply lines 16i extending in parallel to each other in the lateral direction in the drawings.
- Each light emission control line 14e is provided adjacent to each gate line 14g and each initialization power supply line 16i, as shown in FIGS.
- the TFT layer 30a is provided with a plurality of source lines 19f so as to extend parallel to each other in the vertical direction in the drawings.
- the TFT layer 30a is provided with a plurality of power supply lines 19g so as to extend in parallel to each other in the vertical direction in the drawings.
- Each power supply line 19g is provided adjacent to each source line 19f, as shown in FIGS. 2 and 3.
- the first initialization TFT 9a to the second initialization TFT 9g include a first terminal (see Na in FIG. 4) and a second terminal (see Nb in FIG. 4) which are arranged so as to be separated from each other. And a control terminal for controlling conduction between the first terminal and the second terminal.
- the first terminal and the second terminal of each of the TFTs 9a to 9g are conductor regions of the first semiconductor layer 12a and the second semiconductor layer 12b that are integrally provided with each other.
- the first initialization TFT 9a has its control terminal electrically connected to the corresponding gate line 14g, and its first terminal is the first gate electrode of the capacitor 9h described later. 14a, and its second terminal is electrically connected to the corresponding initialization power supply line 16i.
- the control terminal of the first initialization TFT 9a is, as shown in FIG. 3, two portions of the gate line 14g that overlap the first semiconductor layer 12a.
- the first terminal of the first initialization TFT 9a has a first gate electrode of the capacitor 9h via a third contact hole Hc, a first connection wiring 19e described later, and a first contact hole Ha, as shown in FIG. It is electrically connected to 14a.
- the second terminal of the first initialization TFT 9a is electrically connected to the initialization power supply line 16i through the fourth contact hole Hd, the second connection wiring 19h and the fifth contact hole He, as shown in FIG. It is connected.
- the first initialization TFT 9a is configured to initialize the voltage applied to the control terminal of the drive TFT 9d by applying the voltage of the initialization power line 16i to the capacitor 9h.
- the first initializing TFT 9a scans before the gate line 14g electrically connected to the control terminals of the threshold voltage compensating TFT 9b, the write control TFT 9c, and the second initializing TFT 9g, which will be described later. It is electrically connected to the gate line 14g.
- the first initialization TFT 9a to the emission control TFT 9f correspond to the pixel circuit in the nth row
- the second initialization TFT 9g corresponds to the pixel circuit in the n-1th row. is there.
- the threshold voltage compensation TFT 9b has its control terminal electrically connected to the corresponding gate line 14g, and its first terminal electrically connected to the second terminal of the drive TFT 9d.
- the second terminal is electrically connected to the control terminal of the driving TFT 9d.
- the control terminal of the threshold voltage compensation TFT 9b is, as shown in FIG. 3, two portions of the gate line 14g that overlap the first semiconductor layer 12a.
- the first terminal of the threshold voltage compensation TFT 9b is integrally formed with the second terminal of the driving TFT 9d as shown in FIG. 3, and is electrically connected to the second terminal of the driving TFT 9d.
- the second terminal of the threshold voltage compensating TFT 9b is, as shown in FIG.
- the threshold voltage compensating TFT 9b is configured to compensate the threshold voltage of the driving TFT 9d by setting the driving TFT 9d in a diode connection state according to the selection of the gate line 14g.
- the write control TFT 9c has its control terminal electrically connected to the corresponding gate line 14g and its first terminal electrically connected to the corresponding source line 19f in each sub-pixel P.
- the second terminal is electrically connected to the first terminal of the driving TFT 9d.
- the control terminal of the write control TFT 9c is a portion that overlaps the first semiconductor layer 12a of the gate line 14g, as shown in FIG.
- the first terminal of the write control TFT 9c is electrically connected to the source line 19f through the sixth contact hole Hf, as shown in FIG.
- the second terminal of the write control TFT 9c is formed integrally with the first terminal of the drive TFT 9d and is electrically connected to the first terminal of the drive TFT 9d.
- the write control TFT 9c is configured to apply the voltage of the source line 19f to the first terminal of the drive TFT 9d according to the selection of the gate line 14g.
- the drive TFT 9d has its control terminal electrically connected to the first terminal of the first initialization TFT 9a and the second terminal of the threshold voltage compensation TFT 9b in each sub-pixel P, and its first terminal. Are electrically connected to the respective second terminals of the write control TFT 9c and the power supply TFT 9e, and the second terminals thereof are electrically connected to the respective first terminals of the threshold voltage compensation TFT 9b and the light emission control TFT 9f.
- the drive TFT 9d is provided as a first TFT, and a drive current according to a voltage applied between its control terminal and its first terminal is applied to the first terminal of the light emission control TFT 9f to apply the organic EL element. It is configured to control the current amount of 35.
- the driving TFT 9d includes a first semiconductor layer 12a, a gate insulating film 13, a first gate electrode (control terminal) 14a, a first semiconductor layer 12a, a first gate electrode 14a, a first gate electrode (control terminal) 14a and a first semiconductor layer 12a, which are sequentially provided on the base coat film 11.
- An interlayer insulating film 15 and a second interlayer insulating film 17 are provided.
- the first semiconductor layer 12a is provided on the base coat film 11 in a bent shape.
- FIG. 1 the driving TFT 9d includes a first semiconductor layer 12a, a gate insulating film 13, a first gate electrode (control terminal) 14a, a first semiconductor layer 12a, a first gate electrode 14a, a first gate electrode (control terminal) 14a and a first semiconductor layer 12a, which are sequentially provided on the base coat film 11.
- An interlayer insulating film 15 and a second interlayer insulating film 17 are provided.
- the first semiconductor layer 12a is provided on the base coat film
- the first semiconductor layer 12a includes an intrinsic region 12ac provided so as to overlap the first gate electrode 14a in a plan view, and a first conductor region provided so as to sandwich the intrinsic region 12ac. (Not shown) and the second conductor region 12ab.
- the intrinsic region 12ac has an intermediate portion provided in a substantially V shape in a plan view.
- one conductor region of the first semiconductor layer 12a is provided as a first terminal, and as shown in FIG. 3, is integrally formed with each second terminal of the write control TFT 9c and the power supply TFT 9e to write data. It is electrically connected to each second terminal of the control TFT 9c and the power supply TFT 9e.
- the other conductor region of the first semiconductor layer 12a is provided as a second terminal, and as shown in FIG. 3, it is integrally formed with each first terminal of the threshold voltage compensating TFT 9b and the emission control TFT 9f to obtain a threshold voltage.
- the compensation TFT 9b and the emission control TFT 9f are electrically connected to the respective first terminals.
- the gate insulating film 13 is provided so as to cover the first semiconductor layer 12a, as shown in FIG.
- the first gate electrode 14a is provided on the gate insulating film 13 as a gate metal layer in a rectangular island shape in plan view so as to overlap with the channel region 12ac of the semiconductor layer 12a. ing.
- the first interlayer insulating film 15 is provided so as to cover the first gate electrode 14a, as shown in FIG. Further, as shown in FIG. 5, the second interlayer insulating film 17 is provided on the first interlayer insulating film 15 via a capacitance electrode 16c described later.
- the power supply TFT 9e has its control terminal electrically connected to the corresponding light emission control line 14e and its first terminal electrically connected to the corresponding power supply line 19g.
- the second terminal is electrically connected to the first terminal of the driving TFT 9d.
- the power supply TFT 9e is provided as a second TFT, and is configured to apply the voltage of the power supply line 19g to the first terminal of the drive TFT 9d according to the selection of the light emission control line 14e.
- the power supply TFT 9e includes a second semiconductor layer 12b, a gate insulating film 13, and a light emission control line (second gate electrode, control terminal) provided in this order on the base coat film 11. ) 14e, a first interlayer insulating film 15 and a second interlayer insulating film 17.
- the second semiconductor layer 12b is provided in a bent shape on the base coat film 11.
- the second semiconductor layer 12b includes an intrinsic region 12bc provided so as to overlap the emission control line 14e in a plan view and a first conductor region 12ba provided so as to sandwich the intrinsic region 12bc. And a second conductor region 12bb.
- the first conductor region 12ba is provided as a second terminal, is formed integrally with the first terminal of the drive TFT 9d, and is electrically connected to the first terminal of the drive TFT 9d, as shown in FIG. ..
- the second conductor region 12bb is provided as a first terminal, and as shown in FIGS. 3 and 6, electricity is supplied to the power supply line 19g via the second contact hole Hb formed in the organic insulating film 18 described later. Is connected.
- the gate insulating film 13 is provided so as to cover the second semiconductor layer 12b, as shown in FIG.
- the second gate electrode (control terminal) is provided as a gate metal layer and is a portion that overlaps the second semiconductor layer 12b of the emission control line 14e.
- the first interlayer insulating film 15 is provided so as to cover the light emission control line 14e, as shown in FIG. Further, the second interlayer insulating film 17 is provided on the first interlayer insulating film 15, as shown in FIG. Further, as shown in FIGS. 3 and 6, the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17 have the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17.
- a third opening Mc is provided so as to penetrate 17 and reach the second conductor region 12bb. Further, as shown in FIGS.
- the organic insulating film 18 is provided with a second contact hole Hb so as to overlap the third opening Mc in a plan view and to penetrate the organic insulating film 18. ..
- the second contact hole Hb is provided so as to be adjacent to the light emission control line 14e, as shown in FIGS. Further, as shown in FIG. 3, the peripheral edge of the third opening Mc is provided outside the peripheral edge of the second contact hole Hb in plan view. Further, the side surface of the second contact hole Hb is inclined in a forward taper shape toward the resin substrate layer 10 side.
- the second semiconductor layer 12b is shown separated from the first semiconductor layer 12a by a two-dot chain line in FIG. 3 for convenience, it is provided integrally with the first semiconductor layer 12a as described above.
- each light emitting control TFT 9f its control terminal is electrically connected to the corresponding light emission control line 14e, and its first terminal is electrically connected to the second terminal of the drive TFT 9d.
- the second terminal is electrically connected to the first electrode 31 of the organic EL element 35 described later.
- the control terminal of the light emission control TFT 9f is a portion that overlaps with the first semiconductor layer 12a of the light emission control line 14e, as shown in FIG.
- the first terminal of the light emission control TFT 9f is formed integrally with the second terminal of the driving TFT 9d and is electrically connected to the second terminal of the driving TFT 9d.
- the second terminal of the emission control TFT 9f is electrically connected to the first electrode 31 of the organic EL element 35 via the seventh contact hole Hg and the third connection wiring 19i, as shown in FIG. ..
- the light emission control TFT 9f is configured to apply the drive current to the organic EL element 35 according to the selection of the light emission control line 14e.
- the control terminal of the second initialization TFT 9g is electrically connected to the corresponding gate line 14g, and the first terminal thereof is connected to the first terminal 31 of the organic EL element 35. It is electrically connected, and its second terminal is electrically connected to the corresponding initialization power supply line 16i.
- the control terminal of the second initialization TFT 9g is a portion that overlaps the first semiconductor layer 12a of the gate line 14g, as shown in FIG.
- the first terminal of the second initialization TFT 9g is integrally formed with the second terminal of the emission control TFT 9f and electrically connected to the first electrode 31 of the organic EL element 35. There is.
- the second terminal of the second initialization TFT 9g is electrically connected to the initialization power supply line 16i via the fourth contact hole Hd, the second connection wiring 19h and the fifth contact hole He, as shown in FIG. It is connected.
- the second initialization TFT 9g is configured to reset the charge accumulated in the first electrode 31 of the organic EL element 35 in accordance with the selection of the gate line 14g.
- the capacitor 9h includes a first gate electrode 14a, a first interlayer insulating film 15 provided on the gate electrode 14a, and a plane on the gate electrode 14a on the first interlayer insulating film 15.
- the capacitor electrode 16c is provided so as to overlap with the eyes.
- the first gate electrode 14a of each sub-pixel P is formed integrally with the first gate electrode 14a of the driving TFT 9d, and the first gate electrode of the driving TFT 9d is formed.
- the electrode 14a is electrically connected to the first terminal of the first initialization TFT 9a and the second terminal of the threshold voltage compensation TFT 9b, and the capacitance electrode 16c is electrically connected to the corresponding power supply line 19g through the eighth contact hole Hh. It is connected.
- the capacitor 9h stores the voltage at the corresponding source line 19f when the corresponding gate line 14g is in the selected state, and holds the stored voltage so that the corresponding gate line 14g is in the non-selected state. It is configured to maintain the voltage applied to the first gate electrode 14a of the drive TFT 9d.
- the capacitance electrode 16c is provided to the outside of the peripheral edge of the gate electrode 14a over the entire peripheral edge of the first gate electrode 14a.
- the capacitance electrode 16c is provided with a first opening Ma that overlaps the first gate electrode 14a in plan view and penetrates the capacitance electrode 16c.
- a second interlayer insulating film 17 is provided on the capacitance electrode 16c so as to cover the capacitance electrode 16c.
- the first interlayer insulating film 15 and the second interlayer insulating film 17 are arranged inside the peripheral edge of the first opening Ma in plan view, and the first interlayer insulating film is formed.
- a second opening Mb is provided so as to penetrate 15 and the second interlayer insulating film 17. Further, on the second interlayer insulating film 17, as shown in FIG.
- an organic insulating film 18 formed of a coating type insulating material is provided. Further, as shown in FIGS. 3 and 5, the organic insulating film 18 is arranged inside the peripheral edge of the second opening Mb in plan view, and the first contact hole Ha is formed so as to penetrate the organic insulating film 18. Is provided. Further, as shown in FIGS. 3 and 5, the first gate electrode 14a is electrically connected to the first connection wiring 19e provided as the source metal layer via the first contact hole Ha. The organic insulating film 18 is provided so as to cover the side surface of the second opening Mb, as shown in FIG. Further, as shown in FIG. 3, the peripheral edge of the second opening Mb is provided outside the peripheral edge of the first contact hole Ha in plan view. Further, the side surface of the first contact hole Ha is inclined in a forward taper shape toward the resin substrate layer 10 as shown in FIG.
- the flattening film 20 is made of, for example, an organic resin material such as polyimide resin.
- the first to fifth contact holes Ha to He provided in the TFT layer 30a will be described below.
- the first contact hole Ha is for electrically connecting the gate metal layer and the source metal layer.
- the second to fourth contact holes Hb to Hd are for electrically connecting the conductor region of the semiconductor layer and the source metal layer.
- the fifth contact hole He is for electrically connecting the intermediate metal layer and the source metal layer.
- the first contact hole Ha and the second contact hole Hb are provided in the organic insulating film 18 filling the corresponding openings of the first interlayer insulating film 15 and the second interlayer insulating film 17, as shown in FIGS. Has been. This is because the capacitance electrode 16c is provided near the first contact hole Ha and the emission control line 14e is provided near the second contact hole Hb, so that the source metal layer, the capacitance electrode 16c and the emission control line 14e are provided. This is because it is easy to short circuit.
- the third contact hole Hc is provided in the interlayer insulating film (first interlayer insulating film 15 and second interlayer insulating film 17) as shown in FIG. This is because there is no metal layer near the third contact hole Hc above the semiconductor layer, as shown in FIG. 5, as compared with the first contact hole Ha and the second contact hole Hc.
- the structure of the first contact hole Ha to the third contact hole Hc described above is an example, and if the distance between the contact hole and the metal layer is long, the contact hole is provided in the interlayer insulating film and the contact hole is separated from the metal layer. If the distance is short, the contact hole may be provided in the organic insulating film inside the interlayer insulating film.
- the organic EL element layer 40 includes a plurality of organic EL elements 35 provided as a plurality of light emitting elements so as to be arranged in a matrix on the flattening film 19, and each organic EL element. 35 and a sealing film 45 provided so as to cover 35.
- the organic EL element 35 has an island-shaped first electrode 31 on the flattening film 20 and an edge provided so as to cover the peripheral end of the first electrode 31.
- a cover 32, an organic EL layer 33 (not shown) provided on the first electrode 31, and a second electrode 34 provided on the organic EL layer 33 so as to be common to the entire display region D are provided.
- the first electrode 31 is electrically connected to the second terminal of the light emission control TFT 9f of each sub-pixel P via a contact hole formed in the flattening film 20.
- the first electrode 31 has a function of injecting holes into the organic EL layer 33.
- the first electrode 31 is more preferably formed of a material having a large work function in order to improve the efficiency of injecting holes into the organic EL layer 33.
- a material forming the first electrode 31 for example, silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au).
- the material forming the first electrode 31 may be an alloy such as astatine (At)/oxidized astatine (AtO 2 ). Further, the material forming the first electrode 31 is, for example, a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO). It may be. Further, the first electrode 31 may be formed by stacking a plurality of layers made of the above materials. Examples of the compound material having a large work function include indium tin oxide (ITO) and indium zinc oxide (IZO).
- the edge cover 32 is provided in a grid shape so as to be common to the entire display area D.
- examples of the material forming the edge cover 32 include a polyimide resin, an acrylic resin, a polysiloxane resin, and a novolac resin.
- the organic EL layer 33 includes a hole injection layer 1, a hole transport layer 2, a light emitting layer 3, an electron transport layer 4, and an electron injection layer 5, which are sequentially provided on the first electrode 31. ing.
- the hole injection layer 1 is also called an anode buffer layer and has a function of bringing the energy levels of the first electrode 31 and the organic EL layer 33 close to each other and improving the hole injection efficiency from the first electrode 31 to the organic EL layer 33.
- a triazole derivative, an oxadiazole derivative, an imidazole derivative, a polyarylalkane derivative, a pyrazoline derivative, a phenylenediamine derivative, an oxazole derivative, a styrylanthracene derivative, a fluorenone derivative examples thereof include hydrazone derivatives and stilbene derivatives.
- the hole transport layer 2 has a function of improving the efficiency of transporting holes from the first electrode 31 to the organic EL layer 33.
- examples of the material forming the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, styrylamine derivatives, polyvinylcarbazole, poly-p-phenylenevinylene, polysilane, triazole derivatives, and oxadiazole.
- Derivatives imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, Examples thereof include hydride amorphous silicon carbide, zinc sulfide, and zinc selenium.
- the light emitting layer 3 when the voltage is applied by the first electrode 31 and the second electrode 34, holes and electrons are injected from the first electrode 31 and the second electrode 34, respectively, and the holes and electrons are recombined. Area.
- the light emitting layer 3 is formed of a material having high luminous efficiency. Examples of the material forming the light emitting layer 3 include metal oxinoid compound [8-hydroxyquinoline metal complex], naphthalene derivative, anthracene derivative, diphenylethylene derivative, vinylacetone derivative, triphenylamine derivative, butadiene derivative, coumarin derivative.
- the electron transport layer 4 has a function of efficiently moving electrons to the light emitting layer 3.
- examples of the material forming the electron transport layer 4 include organic compounds such as oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, diphenoquinone derivatives, and fluorenone derivatives. , Silole derivatives, metal oxinoid compounds and the like.
- the electron injection layer 5 has a function of bringing the energy levels of the second electrode 34 and the organic EL layer 33 close to each other and improving the efficiency of injecting electrons from the second electrode 34 to the organic EL layer 33. With this function, The drive voltage of the organic EL element 35 can be lowered.
- the electron injection layer 5 is also called a cathode buffer layer.
- a material forming the electron injection layer 5 for example, lithium fluoride (LiF), magnesium fluoride (MgF 2 ), calcium fluoride (CaF 2 ), strontium fluoride (SrF 2 ), barium fluoride.
- Inorganic alkali compounds such as (BaF 2 ), aluminum oxide (Al 2 O 3 ), strontium oxide (SrO) and the like can be mentioned.
- the second electrode 34 is provided so as to cover the organic EL layer 33 of each sub-pixel P and the edge cover 32 common to all the sub-pixels P. Further, the second electrode 34 has a function of injecting electrons into the organic EL layer 33. Further, the second electrode 34 is more preferably made of a material having a small work function in order to improve the efficiency of injecting electrons into the organic EL layer 33.
- a material forming the second electrode 34 for example, silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au).
- the second electrode 34 is, for example, magnesium (Mg)/copper (Cu), magnesium (Mg)/silver (Ag), sodium (Na)/potassium (K), astatine (At)/oxidized astatine (AtO 2 ).
- the second electrode 34 may be formed of a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO). ..
- the second electrode 34 may be formed by stacking a plurality of layers made of the above materials.
- Examples of the material having a small work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg)/copper (Cu), magnesium (Mg)/silver (Ag), and sodium.
- (Na)/potassium (K) lithium (Li)/aluminum (Al), lithium (Li)/calcium (Ca)/aluminum (Al), lithium fluoride (LiF)/calcium (Ca)/aluminum (Al) Etc.
- the sealing film 45 is provided on the first sealing inorganic insulating film 41 provided so as to cover the second electrode 34 and the first sealing inorganic insulating film 41.
- the sealing organic film 42 and the second sealing inorganic insulating film 43 provided so as to cover the sealing organic film 42 are provided, and have a function of protecting the organic EL layer 33 from moisture, oxygen and the like.
- the first sealing inorganic insulating film 41 and the second sealing inorganic insulating film 43 are, for example, silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), and trisilicon tetroxide (Si 3 N 4 ).
- the sealing organic film 42 is made of, for example, an organic material such as acrylic resin, polyurea resin, parylene resin, polyimide resin, or polyamide resin.
- the organic EL display device 50a having the above configuration, when the corresponding light emission control line 14e is first selected in each sub-pixel P and put into an inactive state, the organic EL element 35 is put into a non-light emitting state.
- the corresponding gate line 14g (electrically connected to the first initializing TFT 9a and the second initializing TFT 9g) is selected, and the gate signal is transmitted via the gate line 14g to the first initializing TFT 9a. Is input to the first initialization TFT 9a and the second initialization TFT 9g, the corresponding initialization power supply line 16i voltage is applied to the capacitor 9h, and the drive TFT 9d is turned on.
- the charge of the capacitor 9h is discharged, and the voltage applied to the control terminal (first gate electrode) 14a of the drive TFT 9d is initialized.
- the corresponding gate line 14g (electrically connected to the threshold voltage compensation TFT 9b and the write control TFT 9c) is selected and activated to turn on the threshold voltage compensation TFT 9b and the write control TFT 9c.
- a predetermined voltage corresponding to the source signal transmitted via the corresponding source line 19f is written in the capacitor 9h via the driving TFT 9d in the diode connection state, and initialized via the corresponding initialization power supply line 16i.
- the signal is applied to the first electrode 31 of the organic EL element 35, and the charge accumulated in the first electrode 31 is reset.
- the corresponding light emission control line 14e is selected, the power supply TFT 9e and the light emission control TFT 9f are turned on, and the drive current corresponding to the voltage applied to the control terminal (gate electrode) 16a of the drive TFT 9d is supplied from the corresponding power line 19g. It is supplied to the organic EL element 35. In this way, in the organic EL display device 50a, in each sub-pixel P, the organic EL element 35 emits light with the brightness corresponding to the drive current, and image display is performed.
- the method for manufacturing the organic EL display device 50a according to the present embodiment includes a TFT layer forming step including an opening forming step, a contact hole forming step, and a source metal layer forming step, an organic EL element layer forming step, and a sealing film. And a forming step.
- FIG. 8 is a cross-sectional view schematically showing a laminated form of thin films formed on the resin substrate layer 10 when the organic EL display device 50a is manufactured.
- 9 and 10 are cross-sectional views showing a step of forming the resist pattern Ra in the opening forming step of the method for manufacturing the organic EL display device 50a, which corresponds to FIGS. 5 and 6.
- FIGS. 11 and 12 are cross-sectional views showing a step of forming the second opening Mb and the third opening Mc in the opening forming step of the method for manufacturing the organic EL display device 50a
- FIGS. It is a figure equivalent to. 13 and 14 are cross-sectional views showing a step of applying an organic insulating film in the contact hole forming step of the manufacturing method of the organic EL display device 50a, and are views corresponding to FIGS. 5 and 6.
- 15 and 16 are cross-sectional views showing a step of patterning the organic insulating film in the contact hole forming step of the manufacturing method of the organic EL display device 50a, and are views corresponding to FIGS. 5 and 6.
- 17 and 18 are cross-sectional views showing the source metal layer forming step of the method for manufacturing the organic EL display device 50a, which corresponds to FIGS. 5 and 6.
- the base coat film 11 is formed by forming an inorganic insulating film (thickness of about 1000 nm) such as a silicon oxide film on the resin substrate layer 10 formed on the glass substrate by, for example, a plasma CVD method. To do.
- an amorphous silicon film (with a thickness of about 50 nm) is formed on the entire substrate on which the base coat film 11 is formed by a plasma CVD method, and the amorphous silicon film is crystallized by laser annealing or the like to form a polysilicon film.
- the semiconductor film 12 is patterned to form the first semiconductor layer (12a) and the like (semiconductor layer forming step).
- an inorganic insulating film (about 100 nm) such as a silicon oxide film is formed on the entire substrate on which the first semiconductor layer (12a) and the like are formed by, for example, a plasma CVD method to form the first semiconductor layer 12a and the like.
- the gate insulating film 13 is formed so as to cover (gate insulating film forming step).
- an aluminum film having a thickness of about 350 nm
- a molybdenum nitride film having a thickness of about 50 nm
- the gate metal film 14 is patterned to form a gate metal layer such as the first gate electrode 14a (gate metal layer forming step).
- impurity ions are doped using the gate metal layer such as the first gate electrode 14a as a mask to form the first semiconductor layer 12a having the intrinsic region 12ac and the pair of conductor regions (doping step).
- an inorganic insulating film (having a thickness of about 100 nm) such as a silicon oxide film is formed on the entire substrate on which the first semiconductor layer 12a and the like are formed by, for example, a plasma CVD method, and thus the first interlayer insulating film 15 is formed. Are formed (first interlayer insulating film forming step).
- an aluminum film about 350 nm in thickness
- a molybdenum nitride film about 50 nm in thickness
- an intermediate film is formed.
- the intermediate metal film 16 is patterned to form an intermediate metal layer such as the capacitor electrode 16c having the first opening Ma (intermediate metal layer forming step).
- an inorganic insulating film such as a silicon oxide film is formed on the entire substrate on which the intermediate metal layer such as the capacitance electrode 16c is formed, for example, by the plasma CVD method, so that the second interlayer insulating film is formed.
- the film 17 is formed (second interlayer insulating film forming step).
- a positive resist material R (see FIG. 8) is applied on the second interlayer insulating film 17, and the resist material R is exposed, developed, and baked, so that a second resist material R is formed as shown in FIGS.
- a resist pattern Ra having a through hole Hr is formed corresponding to the opening Mb, the third opening Mc, and the third contact hole Hc.
- the first interlayer insulating film 15 and the second interlayer insulating film 17 have a flat surface.
- the penetrating second opening Mb is formed so as to be arranged inside the peripheral edge of the first opening Ma as viewed.
- the gate insulating film 13 and the first interlayer insulating film 13 are formed.
- a third opening Mc is formed through the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17, and reaches the second conductor region 12bb. (Opening formation step).
- the gate insulating film 13 and the first interlayer insulating film 13 are etched.
- the third contact hole Hc is formed in the insulating film 15 and the second interlayer insulating film 17 so as to penetrate the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17 and reach the second conductor region 12ab.
- the lower part is formed.
- the whole substrate on which the second interlayer insulating film 17 having the second opening Mb and the third opening Mc is formed is shown in FIGS. 13 and 15 by, for example, a spin coating method or a slit coating method.
- the organic insulating film 18 formed of a photosensitive insulating material for example, SOG (spin-on-glass) material
- the organic insulating film 18 is patterned.
- the hole Hb and the upper part of the third contact hole Hc penetrating so as to overlap the lower part of the third contact hole Hc in plan view are formed (contact hole forming step).
- the organic insulating film 18 is patterned so as to cover the side surfaces of the second opening Mb and the third opening Mc, and the resin substrate layer 10 is then formed.
- the first contact hole Ha and the second contact hole Hb are formed so that the side surfaces incline toward the side in a forward tapered shape.
- a titanium film (thickness of about 30 nm), an aluminum film (thickness of about 300 nm), a titanium film (thickness of about 50 nm), etc. are formed on the entire substrate in which the first contact holes Ha and the like are formed by, for example, a sputtering method.
- the source metal film 19 is patterned to form a source metal layer such as the first connection wiring 19e and the power supply line 19g (source metal layer forming step).
- the flattening film 20 is formed by performing pre-baking, exposure, development, and post-baking on the coating film.
- the TFT layer 30a can be formed as described above.
- ⁇ Organic EL element layer forming step> The first electrode 31, the edge cover 32, and the organic EL layer 33 (hole injection layer 1, hole transport) are used on the flattening film 20 of the TFT layer 30a formed in the TFT layer forming step by a well-known method.
- the layer 2, the light emitting layer 3, the electron transport layer 4, the electron injection layer 5) and the second electrode 34 are formed to form the organic EL element layer 40.
- a sealing film 45 (first sealing inorganic insulating film 41, sealing organic film 42, second sealing) is formed on the organic EL element layer 40 formed in the organic EL element layer forming step by a known method.
- a protective sheet (not shown) is attached to the surface of the substrate on which the sealing film 45 is formed, and then the glass substrate is irradiated from the glass substrate side of the resin substrate layer 10 to irradiate the glass substrate from the lower surface of the resin substrate layer 10.
- a protective sheet (not shown) is attached to the lower surface of the resin substrate layer 10 from which the glass substrate has been peeled off.
- the organic EL display device 50a of this embodiment can be manufactured as described above.
- the first interlayer insulating film 15 and the second interlayer insulating film 17 are first.
- the second opening Mb is formed so as to penetrate the interlayer insulating film 15 and the second interlayer insulating film 17, and the gate insulating film 13 is formed on the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17.
- the third opening Mc is formed so as to penetrate the first interlayer insulating film 15 and the second interlayer insulating film 17.
- the foreign material X is temporarily present on the surfaces of the gate insulating film 13 and the first interlayer insulating film 15, and the first interlayer insulating film 15 and the second interlayer insulating film are formed in the first interlayer insulating film forming step and the second interlayer insulating film forming step. Even if a void Y is formed in the first interlayer insulating film 15 and the second interlayer insulating film 17 when the film 17 is formed, the second opening Mb and the third opening Mb are formed in the subsequent contact hole forming step.
- the organic insulating film 18 is patterned so as to cover the side surface of Mc, the organic insulating film 18 is filled in the void Y formed in the first interlayer insulating film 15 and the second interlayer insulating film 17. This causes a short circuit between the first connection wiring 19e formed in the source metal layer forming step and the capacitor electrode 16c formed in the intermediate metal layer forming step, and a power supply line 19g and a gate metal formed in the source metal layer forming step. Since a short circuit with the light emission control line 14e formed in the layer forming step can be suppressed, occurrence of a short circuit defect due to the void Y formed in the first interlayer insulating film 15 and the second interlayer insulating film 17 can be suppressed. can do.
- FIG. 19 to 24 show a second embodiment of the display device and the manufacturing method thereof according to the present invention.
- FIG. 19 and FIG. 20 are cross-sectional views of the organic EL display device 50b of the present embodiment, and are views corresponding to FIG. 5 and FIG. 6 described in the first embodiment.
- the same parts as those in FIGS. 1 to 18 are designated by the same reference numerals, and detailed description thereof will be omitted.
- the organic EL display device 50a in which the side surfaces of the openings of the first interlayer insulating film 15 and the second interlayer insulating film 17 are substantially upright is exemplified, but in the present embodiment, the first interlayer insulating film is formed.
- 15 illustrates an organic EL display device 50b in which the side surfaces of the openings of 15 and the second interlayer insulating film 17 are inclined in a reverse taper shape.
- the organic EL display device 50b includes a display area D and a frame area F provided around the display area D, similarly to the organic EL display device 50a of the first embodiment.
- the organic EL display device 50b includes a resin substrate layer 10, a TFT layer 30b provided on the resin substrate layer 10, and an organic EL element layer 40 provided on the TFT layer 30b. , And a sealing film 45 provided on the organic EL element layer 40.
- the TFT layer 30b is provided on the base coat film 11 provided on the resin substrate layer 10 and on the base coat film 11 for each sub-pixel P.
- the first initialization TFT 9a, the threshold voltage compensation TFT 9b, the write control TFT 9c, the drive TFT 9d, the power supply TFT 9e, the light emission control TFT 9f, the second initialization TFT 9g and the capacitor 9h, and the respective TFTs 9a to 9g and the capacitor 9h are provided.
- a flattening film 20 is provided.
- the side surfaces of the second opening Mb and the third opening Mc formed in the first interlayer insulating film 15 and the second interlayer insulating film 17 have the resin substrate layer 10 on the side surfaces.
- a fourth opening Md is formed in the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 so as to incline in a reverse taper shape toward the side and overlap the third contact hole Hc in a plan view.
- the side surface of the fourth opening Md is inclined in the reverse taper shape toward the resin substrate layer 10 side.
- the TFT layer 30b has the same structure as the TFT layer 30a of the organic EL display device 50a according to the first embodiment except for the structures of the second opening Mb, the third opening Mc, and the fourth opening Md described above. It is virtually the same.
- the organic EL display device 50b having the above configuration has flexibility as in the organic EL display device 50a of the first embodiment, and in each sub-pixel P, the first initialization TFT 9a, the threshold voltage compensation TFT 9b, An image is displayed by appropriately causing the light emitting layer 3 of the organic EL layer 33 to emit light via the write control TFT 9c, the drive TFT 9d, the power supply TFT 9e, the light emission control TFT 9f, and the second initialization TFT 9g. ..
- the organic EL display device 50b of the present embodiment can be manufactured by changing the opening forming step in the method of manufacturing the organic EL display device 50a of the first embodiment.
- FIGS. 21 and 22 are cross-sectional views showing a step of forming a resist pattern in the opening forming step of the method for manufacturing the organic EL display device 50b, and are views corresponding to FIGS. 19 and 20.
- 23 and 24 are cross-sectional views showing a step of forming the second opening Mb, the fourth opening Md, and the third opening Mc in the opening forming step of the method for manufacturing the organic EL display device 50b.
- FIG. 21 is a view corresponding to FIGS. 19 and 20.
- the negative resist material R is applied on the second interlayer insulating film 17. Then, by exposing, developing and baking the resist material R, as shown in FIGS. 21 and 22, through holes Hr corresponding to the second opening Mb, the third opening Mc and the fourth opening Md are formed. A resist pattern Rb provided with is formed.
- the side surface of the through hole Hr formed in the resist pattern Rb is inclined in an inverse taper shape toward the resin substrate layer 10 side.
- the first interlayer insulating film 15 and the second interlayer insulating film 17 are planarized as shown in FIG.
- the penetrating second opening Mb is formed so as to be arranged inside the peripheral edge of the first opening Ma as viewed.
- the gate insulating film 13 and the first interlayer insulating film 13 are formed.
- a third opening Mc is formed through the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17, and reaches the second conductor region 12bb. (Opening formation step). Further, at this time, by etching the second interlayer insulating film 17, the first interlayer insulating film 15 and the gate insulating film 13 exposed from the resist pattern Rb, the gate insulating film 13 and the first interlayer insulating film 13 are etched as shown in FIG.
- the fourth opening Md is formed in the insulating film 15 and the second interlayer insulating film 17 so as to penetrate the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17 and reach the second conductor region 12ab. It is formed.
- the second opening formed by etching using the resist pattern Rb as a mask As shown in FIGS. 23 and 24, the side surfaces of Mb, the third opening Mc, and the fourth opening Md are inclined in a reverse taper shape toward the resin substrate layer 10 side.
- the flattening film 20 is formed to form the TFT layer 30b.
- the organic EL display device 50b of the present embodiment is manufactured by performing the organic EL element layer forming step and the sealing film forming step of the manufacturing method of the organic EL display device 50a of the first embodiment. can do.
- the first interlayer insulating film 15 and the second interlayer insulating film 17 have the first interlayer insulating film 15 and the first interlayer insulating film 17 in the opening forming step of the TFT layer forming step.
- the second opening Mb is formed so as to penetrate the interlayer insulating film 15 and the second interlayer insulating film 17, and the gate insulating film 13 is formed on the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17.
- the third opening Mc is formed so as to penetrate the first interlayer insulating film 15 and the second interlayer insulating film 17.
- the foreign material X is temporarily present on the surfaces of the gate insulating film 13 and the first interlayer insulating film 15, and the first interlayer insulating film 15 and the second interlayer insulating film are formed in the first interlayer insulating film forming step and the second interlayer insulating film forming step. Even if a void Y is formed in the first interlayer insulating film 15 and the second interlayer insulating film 17 when the film 17 is formed, the second opening Mb and the third opening Mb are formed in the subsequent contact hole forming step.
- the organic insulating film 18 is patterned so as to cover the side surface of Mc, the organic insulating film 18 is filled in the void Y formed in the first interlayer insulating film 15 and the second interlayer insulating film 17. This causes a short circuit between the first connection wiring 19e formed in the source metal layer forming step and the capacitor electrode 16c formed in the intermediate metal layer forming step, and a power supply line 19g and a gate metal formed in the source metal layer forming step. Since a short circuit with the light emission control line 14e formed in the layer forming step can be suppressed, occurrence of a short circuit defect due to the void Y formed in the first interlayer insulating film 15 and the second interlayer insulating film 17 can be suppressed. can do.
- the side surfaces of the second opening Mb and the third opening Mc are inclined in a reverse taper shape toward the resin substrate layer 10 side.
- the organic insulating film 18 is formed thicker on the side surfaces of the second opening Mb and the third opening Mc than the organic EL display device 50a of the first embodiment. Therefore, in the organic EL display device 50b of the present embodiment, it is possible to further suppress the occurrence of short-circuit defects due to the void Y formed in the first interlayer insulating film 15 and the second interlayer insulating film 17.
- the organic EL layer having a five-layer laminated structure of the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer is exemplified. It may have a three-layer laminated structure of a layer/hole transport layer, a light emitting layer, and an electron transport layer/electron injection layer.
- the organic EL display device in which the first electrode is the anode and the second electrode is the cathode has been illustrated, but the present invention reverses the laminated structure of the organic EL layer and the first electrode is the cathode. And can be applied to an organic EL display device using the second electrode as an anode.
- the organic EL display device in which the electrode of the TFT connected to the first electrode is used as the drain electrode is illustrated, but the present invention uses the electrode of the TFT connected to the first electrode as the source electrode. It can also be applied to a so-called organic EL display device.
- an organic EL display device has been described as an example of a display device, but the present invention can be applied to a display device including a plurality of light emitting elements driven by current.
- a display device including a QLED (Quantum-dot light emitting diode) which is a light emitting element using a quantum dot containing layer.
- the present invention is useful for flexible display devices.
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Abstract
A second opening (Mb) is provided in a first interlayer insulating film (15) and a second interlayer insulating film (17) so as to penetrate the first interlayer insulating film (15) and the second interlayer insulating film (17), and a first contact hole (Ha) is provided in an organic insulating film (18) by being arranged on the inside of circumferential edge of the second opening (Mb) in a plan view and in such a way as to penetrate the organic insulating film (18). A first gate electrode (14a) is electrically connected to a connection wiring (19e) which is provided via the first contact hole (Ha) as a source metal layer, and the organic insulating film (18) is provided so as to cover the side face of the second opening (Mb).
Description
本発明は、表示装置及びその製造方法に関するものである。
The present invention relates to a display device and a manufacturing method thereof.
近年、液晶表示装置に代わる表示装置として、有機エレクトロルミネッセンス（electroluminescence、以下、ＥＬとも称する）素子を用いた自発光型の有機ＥＬ表示装置が注目されている。ここで、アクティブマトリクス駆動方式の有機ＥＬ表示装置では、例えば、画像の最小単位であるサブ画素毎に薄膜トランジスタ（thin film transistor、以下、ＴＦＴとも称する）が設けられている。
Recently, as a display device that replaces the liquid crystal display device, a self-luminous organic EL display device using an organic electroluminescence (hereinafter also referred to as EL) element has been attracting attention. Here, in the active matrix driving type organic EL display device, for example, a thin film transistor (hereinafter, also referred to as a TFT) is provided for each sub-pixel which is a minimum unit of an image.
例えば、特許文献１には、周辺領域に低温ポリシリコンからなるチャネル層を有するトップゲート型のＴＦＴが設けられ、表示領域に酸化物半導体からなるチャネル層を有するトップゲート型のＴＦＴが設けられた有機ＥＬ表示装置が開示されている。
For example, in Patent Document 1, a top gate type TFT having a channel layer made of low temperature polysilicon is provided in a peripheral region, and a top gate type TFT having a channel layer made of an oxide semiconductor is provided in a display region. An organic EL display device is disclosed.
ところで、トップゲート型のＴＦＴは、例えば、ベース基板上にベースコート膜を介して設けられ、真性領域及び一対の導体領域を含む半導体層と、半導体層を覆うように設けられたゲート絶縁膜と、ゲート絶縁膜上に半導体層の真性領域と重なるように設けられたゲート電極と、ゲート電極を覆うように設けられた層間絶縁膜と、層間絶縁膜上に設けられ、半導体層の一対の導体領域にそれぞれ電気的に接続されたソース電極及びドレイン電極とを備えている。ここで、層間絶縁膜は、例えば、ＣＶＤ（Chemical Vapor Deposition）法により成膜された無機絶縁膜により形成され、仮に、被成膜面に異物が存在すると、その異物を核として、ＣＶＤ膜が異常成長することにより、層間絶縁膜内に鬆と呼ばれる空洞が形成されるおそれがある。そうなると、例えば、ゲート電極とソース電極及びドレイン電極とが短絡し易くなるので、画像表示を行う表示領域に点欠陥や線欠陥等が発生し易くなってしまう。
By the way, a top-gate TFT is, for example, provided on a base substrate via a base coat film, a semiconductor layer including an intrinsic region and a pair of conductor regions, and a gate insulating film provided so as to cover the semiconductor layer, A gate electrode provided on the gate insulating film so as to overlap with the intrinsic region of the semiconductor layer, an interlayer insulating film provided so as to cover the gate electrode, and a pair of conductor regions of the semiconductor layer provided on the interlayer insulating film. And a source electrode and a drain electrode that are electrically connected to each other. Here, the interlayer insulating film is formed of, for example, an inorganic insulating film formed by a CVD (Chemical Vapor Deposition) method, and if foreign matter is present on the film formation surface, the foreign matter is used as a nucleus to form the CVD film. Due to abnormal growth, a cavity called a void may be formed in the interlayer insulating film. Then, for example, the gate electrode and the source electrode and the drain electrode are likely to be short-circuited, so that a point defect, a line defect, or the like is likely to occur in the display region where an image is displayed.
本発明は、かかる点に鑑みてなされたものであり、その目的とするところは、層間絶縁膜に形成された鬆に起因する短絡欠陥の発生を抑制することにある。
The present invention has been made in view of the above points, and an object thereof is to suppress the occurrence of short-circuit defects due to voids formed in the interlayer insulating film.
上記目的を達成するために、本発明に係る表示装置は、ベース基板と、上記ベース基板上に設けられ、半導体層、ゲート絶縁膜、ゲート金属層、第１層間絶縁膜、中間金属層、第２層間絶縁膜、有機絶縁膜及びソース金属層が順に積層され、サブ画素毎に薄膜トランジスタ及びキャパシタが配置された薄膜トランジスタ層と、上記薄膜トランジスタ層上に設けられ、上記サブ画素毎に発光素子が配置された発光素子層とを備え、上記薄膜トランジスタは、上記半導体層として設けられた第１半導体層と、上記ゲート絶縁膜と、上記ゲート金属層として設けられた第１ゲート電極とを備えた第１薄膜トランジスタを有し、上記キャパシタは、上記第１ゲート電極と、上記第１層間絶縁膜と、上記中間金属層として設けられ、平面視で該第１ゲート電極に重なるように配置された容量電極とを備え、上記容量電極には、平面視で上記第１ゲート電極と重なると共に該容量電極を貫通するように第１開口部が設けられ、上記第１層間絶縁膜及び上記第２層間絶縁膜には、平面視で上記第１開口部の周縁の内側に配置すると共に、該第１層間絶縁膜及び該第２層間絶縁膜を貫通するように第２開口部が設けられ、上記有機絶縁膜には、平面視で上記第２開口部の周縁の内側に配置すると共に、該有機絶縁膜を貫通するように第１コンタクトホールが設けられ、上記第１ゲート電極は、上記第１コンタクトホールを介して、上記ソース金属層として設けられた接続配線に電気的に接続され、上記有機絶縁膜は、上記第２開口部の側面を覆うように設けられていることを特徴とする。
To achieve the above object, a display device according to the present invention includes a base substrate, a semiconductor layer, a gate insulating film, a gate metal layer, a first interlayer insulating film, an intermediate metal layer, and A two-layer insulating film, an organic insulating film, and a source metal layer are laminated in this order, a thin film layer in which a thin film and a capacitor are arranged for each sub pixel, and a light emitting element provided on the thin film layer and a light emitting element is arranged for each sub pixel. The thin film is a first thin film having a first semiconductor layer provided as the semiconductor layer, a gate insulating film, and a first gate electrode provided as the gate metal layer. And the capacitor includes the first gate electrode, the first interlayer insulating film, and the capacitor electrode provided as the intermediate metal layer and arranged to overlap the first gate electrode in plan view. The capacitive electrode is provided with a first opening so as to overlap the first gate electrode in a plan view and penetrate the capacitive electrode, and the first interlayer insulating film and the second interlayer insulating film are provided. The organic insulating film is arranged inside the peripheral edge of the first opening in a plan view, and a second opening is provided so as to penetrate the first interlayer insulating film and the second interlayer insulating film. The first contact hole is provided inside the peripheral edge of the second opening in a plan view, and the first contact hole is provided so as to penetrate the organic insulating film, and the first gate electrode is passed through the first contact hole. Is electrically connected to a connection wiring provided as the source metal layer, and the organic insulating film is provided so as to cover a side surface of the second opening.
また、本発明に係る表示装置の製造方法は、ベース基板上にサブ画素毎に薄膜トランジスタ及びキャパシタが配置された薄膜トランジスタ層を形成する薄膜トランジスタ層形成工程と、上記薄膜トランジスタ層上に設けられ、上記サブ画素毎に発光素子が配置された発光素子層を形成する発光素子層形成工程とを備え、上記薄膜トランジスタは、第１薄膜トランジスタを有し、該第１薄膜トランジスタは、第１半導体層と、第１半導体層上に設けられたゲート絶縁膜と、上記ゲート絶縁膜上に設けられた第１ゲート電極とを備え、上記キャパシタは、上記第１ゲート電極と、上記第１ゲート電極上に設けられた第１層間絶縁膜と、上記第１層間絶縁膜上に設けられ、平面視で該第１ゲート電極に重なるように配置された容量電極とを備えており、上記薄膜トランジスタ層形成工程は、上記ベース基板上に半導体膜を成膜した後に、該半導体膜をパターニングして上記第１半導体層を含む半導体層を形成する半導体層形成工程と、上記半導体層上に上記ゲート絶縁膜を形成するゲート絶縁膜形成工程と、上記ゲート絶縁膜上にゲート金属膜を成膜した後に、該ゲート金属膜をパターニングして上記第１ゲート電極を含むゲート金属層を形成するゲート金属層形成工程と、上記ゲート金属層上に上記第１層間絶縁膜を形成する第１層間絶縁膜形成工程と、上記ゲート金属層上に形成された上記第１層間絶縁膜上に中間金属膜を成膜した後に、該中間金属膜をパターニングして平面視で上記第１ゲート電極に重なるように貫通した第１開口部が設けられた上記容量電極を含む中間金属層を形成する中間金属層形成工程と、上記中間金属層上に第２層間絶縁膜を形成する第２層間絶縁膜形成工程と、上記第１層間絶縁膜及び上記第２層間絶縁膜に平面視で上記第１開口部の周縁の内側に配置するように貫通した第２開口部を形成する開口部形成工程と、上記第２開口部が形成された上記第２層間絶縁膜上に有機絶縁膜を塗布した後に、該有機絶縁膜をパターニングして、平面視で上記第２開口部の周縁の内側に配置するように貫通した第１コンタクトホールを形成するコンタクトホール形成工程と、上記有機絶縁膜上にソース金属膜を成膜した後に、該ソース金属膜をパターニングして上記第１コンタクトホールを介して上記第１ゲート電極に電気的に接続された接続配線を含むソース金属層を形成するソース金属層形成工程とを備え、上記コンタクトホール形成工程では、上記第２開口部の側面を覆うように上記有機絶縁膜をパターニングすることを特徴とする。
Further, the method for manufacturing a display device according to the present invention includes a thin film transistor layer forming step of forming a thin film transistor layer and a thin film transistor layer on each of which a sub pixel is disposed on a base substrate; A light emitting element layer forming step of forming a light emitting element layer in which a light emitting element is arranged is provided for each, and the thin film has a first thin film, and the first thin film includes a first semiconductor layer and a first semiconductor layer. The gate insulating film provided above and the first gate electrode provided on the gate insulating film are provided, and the capacitor is the first gate electrode and the first gate electrode provided on the first gate electrode. An interlayer insulating film and a capacitive electrode provided on the first interlayer insulating film and arranged so as to overlap the first gate electrode in a plan view are provided, and the thin film layer forming step is performed on the base substrate. A semiconductor layer forming step of forming a semiconductor layer including the first semiconductor layer by patterning the semiconductor film after forming a semiconductor film in the same manner, and forming a gate insulating film for forming the gate insulating film on the semiconductor layer. A gate metal layer forming step of forming a gate metal film on the gate insulating film and then patterning the gate metal film to form a gate metal layer including the first gate electrode, and a gate metal layer. After the first interlayer insulating film forming step of forming the first interlayer insulating film on the intermediate metal film and the intermediate metal film being formed on the first interlayer insulating film formed on the gate metal layer, the intermediate metal film is formed. An intermediate metal layer forming step of forming an intermediate metal layer including the capacitive electrode provided with a first opening penetrating so as to overlap the first gate electrode in a plan view, and an intermediate metal layer forming step on the intermediate metal layer. The second interlayer insulating film forming step of forming the second interlayer insulating film and the first interlayer insulating film and the second interlayer insulating film were penetrated so as to be arranged inside the peripheral edge of the first opening in a plan view. After the opening forming step of forming the second opening and the organic insulating film being applied on the second interlayer insulating film in which the second opening is formed, the organic insulating film is patterned and viewed in a plan view. A contact hole forming step of forming a first contact hole penetrating so as to be arranged inside the peripheral edge of the second opening, and a patterning of the source metal film after forming a source metal film on the organic insulating film. And a source metal layer forming step of forming a source metal layer including a connection wiring electrically connected to the first gate electrode through the first contact hole. In the step of forming the contact hole, the organic insulating film is patterned so as to cover the side surface of the second opening.
本発明によれば、第２層間絶縁膜及びソース金属層の間に積層された有機絶縁膜が、第１層間絶縁膜及び第２層間絶縁膜に形成された第２開口部の側面を覆うように設けられているので、層間絶縁膜に形成された鬆に起因する短絡欠陥の発生を抑制することができる。
According to the present invention, the organic insulating film laminated between the second interlayer insulating film and the source metal layer covers the side surface of the second opening formed in the first interlayer insulating film and the second interlayer insulating film. Therefore, it is possible to suppress the occurrence of short-circuit defects due to voids formed in the interlayer insulating film.
以下、本発明の実施形態を図面に基づいて詳細に説明する。なお、本発明は、以下の各実施形態に限定されるものではない。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments.
《第１の実施形態》
図１～図１８は、本発明に係る表示装置及びその製造方法の第１の実施形態を示している。なお、以下の各実施形態では、発光素子を備えた表示装置として、有機ＥＬ素子を備えた有機ＥＬ表示装置を例示する。ここで、図１は、本実施形態の有機ＥＬ表示装置５０ａの概略構成を示す平面図である。また、図２は、有機ＥＬ表示装置５０ａの表示領域Ｄの概略構成を示す平面図である。また、図３は、有機ＥＬ表示装置５０ａを構成するＴＦＴ層３０ａ平面図である。また、図４は、ＴＦＴ層３０ａの等価回路図である。また、図５及び図６は、図３中のV－V線及びVI－VI線に沿った有機ＥＬ表示装置５０ａの断面図である。 <<First Embodiment>>
1 to 18 show a first embodiment of a display device and a manufacturing method thereof according to the present invention. In each of the following embodiments, an organic EL display device including an organic EL element is illustrated as a display device including a light emitting element. Here, FIG. 1 is a plan view showing a schematic configuration of the organicEL display device 50a of the present embodiment. 2 is a plan view showing a schematic configuration of the display area D of the organic EL display device 50a. Further, FIG. 3 is a plan view of the TFT layer 30a that constitutes the organic EL display device 50a. Further, FIG. 4 is an equivalent circuit diagram of the TFT layer 30a. 5 and 6 are cross-sectional views of the organic EL display device 50a taken along line VV and line VI-VI in FIG.
図１～図１８は、本発明に係る表示装置及びその製造方法の第１の実施形態を示している。なお、以下の各実施形態では、発光素子を備えた表示装置として、有機ＥＬ素子を備えた有機ＥＬ表示装置を例示する。ここで、図１は、本実施形態の有機ＥＬ表示装置５０ａの概略構成を示す平面図である。また、図２は、有機ＥＬ表示装置５０ａの表示領域Ｄの概略構成を示す平面図である。また、図３は、有機ＥＬ表示装置５０ａを構成するＴＦＴ層３０ａ平面図である。また、図４は、ＴＦＴ層３０ａの等価回路図である。また、図５及び図６は、図３中のV－V線及びVI－VI線に沿った有機ＥＬ表示装置５０ａの断面図である。 <<First Embodiment>>
1 to 18 show a first embodiment of a display device and a manufacturing method thereof according to the present invention. In each of the following embodiments, an organic EL display device including an organic EL element is illustrated as a display device including a light emitting element. Here, FIG. 1 is a plan view showing a schematic configuration of the organic
有機ＥＬ表示装置５０ａは、図１に示すように、例えば、矩形状に設けられた画像表示を行う表示領域Ｄと、表示領域Ｄの周囲に設けられた額縁領域Ｆとを備えている。なお、本実施形態では、矩形状の表示領域Ｄを例示したが、この矩形状には、例えば、辺が円弧状になった形状、角部が円弧状になった形状、辺の一部に切り欠きがある形状等の略矩形状も含まれる。
As shown in FIG. 1, the organic EL display device 50a includes, for example, a rectangular display area D for displaying an image and a frame area F provided around the display area D. In the present embodiment, the rectangular display area D is illustrated, but the rectangular shape may have, for example, a shape in which the sides are arcuate, a shape in which the corners are arcuate, or a part of the sides. A substantially rectangular shape such as a shape with a cutout is also included.
表示領域Ｄには、図２に示すように、複数のサブ画素Ｐがマトリクス状に配列されている。また、表示領域Ｄでは、図２に示すように、例えば、赤色の表示を行うための赤色発光領域Ｅｒを有するサブ画素Ｐ、緑色の表示を行うための緑色発光領域Ｅｇを有するサブ画素Ｐ、及び青色の表示を行うための青色発光領域Ｅｂを有するサブ画素Ｐが互いに隣り合うように設けられている。なお、表示領域Ｄでは、例えば、赤色発光領域Ｅｒ、緑色発光領域Ｅｇ及び青色発光領域Ｅｂを有する隣り合う３つのサブ画素Ｐにより、１つの画素が構成されている。
As shown in FIG. 2, a plurality of sub-pixels P are arranged in a matrix in the display area D. Further, in the display area D, as shown in FIG. 2, for example, a sub-pixel P having a red light-emitting area Er for displaying a red color, a sub-pixel P having a green light-emitting area Eg for performing a green color display, And sub-pixels P having a blue light emitting region Eb for displaying blue are provided adjacent to each other. In the display area D, for example, one pixel is configured by three adjacent sub-pixels P having the red light emitting area Er, the green light emitting area Eg, and the blue light emitting area Eb.
額縁領域Ｆの図１中右端部には、端子部Ｔが設けられている。また、額縁領域Ｆにおいて、図１に示すように、表示領域Ｄ及び端子部Ｔの間には、図中縦方向を折り曲げの軸として１８０°に（Ｕ字状に）折り曲げ可能な折り曲げ部Ｂが一方向（図中縦方向）に延びるように設けられている。
A terminal portion T is provided at the right end of the frame area F in FIG. Further, in the frame region F, as shown in FIG. 1, between the display region D and the terminal portion T, a bent portion B which can be bent at 180° (in a U shape) with the longitudinal direction in the drawing as a bending axis. Are provided so as to extend in one direction (vertical direction in the figure).
有機ＥＬ表示装置５０ａは、図５及び図６に示すように、ベース基板として設けられた樹脂基板層１０と、樹脂基板層１０上に設けられたＴＦＴ層３０ａと、ＴＦＴ層３０ａ上に発光素子層として設けられた有機ＥＬ素子層４０、有機ＥＬ素子層４０上に設けられた封止膜４５とを備えている。
As shown in FIGS. 5 and 6, the organic EL display device 50a includes a resin substrate layer 10 provided as a base substrate, a TFT layer 30a provided on the resin substrate layer 10, and a light emitting element on the TFT layer 30a. The organic EL element layer 40 provided as a layer and the sealing film 45 provided on the organic EL element layer 40 are provided.
樹脂基板層１０は、例えば、ポリイミド樹脂等により構成されている。
The resin substrate layer 10 is made of, for example, a polyimide resin or the like.
ＴＦＴ層３０ａは、樹脂基板層１０上に順に設けられたベースコート膜１１、半導体層（例えば、第１半導体層１２ａ）、ゲート絶縁膜１３、ゲート金属層（例えば、ゲート線１４ｇ）、第１層間絶縁膜１５、中間金属層（例えば、容量電極１６ｃ）、第２層間絶縁膜１７、有機絶縁膜１８、ソース金属層（例えば、ソース線１９ｆ）及び平坦化膜２０を備えている。具体的に、ＴＦＴ層３０ａは、図３～図６に示すように、樹脂基板層１０上に設けられたベースコート膜１１と、ベースコート膜１１上にサブ画素Ｐ毎に設けられた第１初期化ＴＦＴ９ａ、閾値電圧補償ＴＦＴ９ｂ、書込制御ＴＦＴ９ｃ、駆動ＴＦＴ９ｄ、電源供給ＴＦＴ９ｅ、発光制御ＴＦＴ９ｆ、第２初期化ＴＦＴ９ｇ及びキャパシタ９ｈと、各ＴＦＴ９ａ～９ｇ及びキャパシタ９ｈ上に設けられた平坦化膜２０とを備えている。ここで、ＴＦＴ層３０ａには、図２及び図３に示すように、図中横方向に互いに平行に延びるように複数のゲート線１４ｇが設けられている。また、ＴＦＴ層３０ａには、図２及び図３に示すように、図中横方向に互いに平行に延びるように複数の発光制御線１４ｅがゲート金属層として設けられている。また、ＴＦＴ層３０ａには、図２及び図３に示すように、図中横方向に互いに平行に延びるように複数の初期化電源線１６ｉが設けられている。なお、各発光制御線１４ｅは、図２及び図３に示すように、各ゲート線１４ｇ及び各初期化電源線１６ｉと隣り合うように設けられている。また、ＴＦＴ層３０ａには、図２及び図３に示すように、図中縦方向に互いに平行に延びるように複数のソース線１９ｆが設けられている。また、ＴＦＴ層３０ａには、図２及び図３に示すように、図中縦方向に互いに平行に延びるように複数の電源線１９ｇが設けられている。なお、各電源線１９ｇは、図２及び図３に示すように、各ソース線１９ｆと隣り合うように設けられている。
The TFT layer 30a includes a base coat film 11, a semiconductor layer (for example, a first semiconductor layer 12a), a gate insulating film 13, a gate metal layer (for example, a gate line 14g), a first interlayer, which are sequentially provided on the resin substrate layer 10. The insulating film 15, the intermediate metal layer (for example, the capacitor electrode 16c), the second interlayer insulating film 17, the organic insulating film 18, the source metal layer (for example, the source line 19f), and the planarization film 20 are provided. Specifically, as shown in FIGS. 3 to 6, the TFT layer 30a includes a base coat film 11 provided on the resin substrate layer 10 and a first initialization provided on the base coat film 11 for each sub-pixel P. TFT 9a, threshold voltage compensation TFT 9b, write control TFT 9c, drive TFT 9d, power supply TFT 9e, light emission control TFT 9f, second initialization TFT 9g and capacitor 9h, and flattening film 20 provided on each TFT 9a to 9g and capacitor 9h. Equipped with. Here, as shown in FIGS. 2 and 3, the TFT layer 30a is provided with a plurality of gate lines 14g so as to extend parallel to each other in the lateral direction in the drawings. Further, as shown in FIGS. 2 and 3, the TFT layer 30a is provided with a plurality of light emission control lines 14e as gate metal layers so as to extend in the lateral direction in FIG. Further, as shown in FIGS. 2 and 3, the TFT layer 30a is provided with a plurality of initialization power supply lines 16i extending in parallel to each other in the lateral direction in the drawings. Each light emission control line 14e is provided adjacent to each gate line 14g and each initialization power supply line 16i, as shown in FIGS. Further, as shown in FIGS. 2 and 3, the TFT layer 30a is provided with a plurality of source lines 19f so as to extend parallel to each other in the vertical direction in the drawings. Further, as shown in FIGS. 2 and 3, the TFT layer 30a is provided with a plurality of power supply lines 19g so as to extend in parallel to each other in the vertical direction in the drawings. Each power supply line 19g is provided adjacent to each source line 19f, as shown in FIGS. 2 and 3.
ここで、第１初期化ＴＦＴ９ａ～第２初期化ＴＦＴ９ｇは、互いに離間するように配置された第１端子（図４中のＮａ参照）及び第２端子（図４中のＮｂ参照）と、第１端子及び第２端子の間の導通を制御するための制御端子とをそれぞれ備えている。なお、各ＴＦＴ９ａ～９ｇの第１端子及び第２端子は、互いに一体に設けられた第１半導体層１２ａ及び第２半導体層１２ｂの導体領域である。
Here, the first initialization TFT 9a to the second initialization TFT 9g include a first terminal (see Na in FIG. 4) and a second terminal (see Nb in FIG. 4) which are arranged so as to be separated from each other. And a control terminal for controlling conduction between the first terminal and the second terminal. The first terminal and the second terminal of each of the TFTs 9a to 9g are conductor regions of the first semiconductor layer 12a and the second semiconductor layer 12b that are integrally provided with each other.
第１初期化ＴＦＴ９ａは、図４に示すように、各サブ画素Ｐにおいて、その制御端子が対応するゲート線１４ｇに電気的に接続され、その第１端子が後述するキャパシタ９ｈの第１ゲート電極１４ａに電気的に接続され、その第２端子が対応する初期化電源線１６ｉに電気的に接続されている。なお、第１初期化ＴＦＴ９ａの制御端子は、図３に示すように、ゲート線１４ｇの第１半導体層１２ａと重なる２つの部分である。また、第１初期化ＴＦＴ９ａの第１端子は、図３に示すように、第３コンタクトホールＨｃ、後述する第１接続配線１９ｅ及び第１コンタクトホールＨａを介して、キャパシタ９ｈの第１ゲート電極１４ａに電気的に接続されている。また、第１初期化ＴＦＴ９ａの第２端子は、図３に示すように、第４コンタクトホールＨｄ、第２接続配線１９ｈ及び第５コンタクトホールＨｅを介して、初期化電源線１６ｉに電気的に接続されている。ここで、第１初期化ＴＦＴ９ａは、初期化電源線１６ｉの電圧をキャパシタ９ｈに印加することにより、駆動ＴＦＴ９ｄの制御端子にかかる電圧を初期化するように構成されている。なお、第１初期化ＴＦＴ９ａは、後述する閾値電圧補償ＴＦＴ９ｂ、書込制御ＴＦＴ９ｃ及び第２初期化ＴＦＴ９ｇの制御端子の各制御端子に電気的に接続されたゲート線１４ｇよりも１つ前に走査されるゲート線１４ｇに電気的に接続されている。また、図３において、第１初期化ＴＦＴ９ａ～発光制御ＴＦＴ９ｆは、ｎ行目の画素回路に対応するものであり、第２初期化ＴＦＴ９ｇは、ｎ－１行目の画素回路に対応するものである。
As shown in FIG. 4, in each sub-pixel P, the first initialization TFT 9a has its control terminal electrically connected to the corresponding gate line 14g, and its first terminal is the first gate electrode of the capacitor 9h described later. 14a, and its second terminal is electrically connected to the corresponding initialization power supply line 16i. The control terminal of the first initialization TFT 9a is, as shown in FIG. 3, two portions of the gate line 14g that overlap the first semiconductor layer 12a. Further, the first terminal of the first initialization TFT 9a has a first gate electrode of the capacitor 9h via a third contact hole Hc, a first connection wiring 19e described later, and a first contact hole Ha, as shown in FIG. It is electrically connected to 14a. Further, the second terminal of the first initialization TFT 9a is electrically connected to the initialization power supply line 16i through the fourth contact hole Hd, the second connection wiring 19h and the fifth contact hole He, as shown in FIG. It is connected. Here, the first initialization TFT 9a is configured to initialize the voltage applied to the control terminal of the drive TFT 9d by applying the voltage of the initialization power line 16i to the capacitor 9h. The first initializing TFT 9a scans before the gate line 14g electrically connected to the control terminals of the threshold voltage compensating TFT 9b, the write control TFT 9c, and the second initializing TFT 9g, which will be described later. It is electrically connected to the gate line 14g. Further, in FIG. 3, the first initialization TFT 9a to the emission control TFT 9f correspond to the pixel circuit in the nth row, and the second initialization TFT 9g corresponds to the pixel circuit in the n-1th row. is there.
閾値電圧補償ＴＦＴ９ｂは、図４に示すように、各サブ画素Ｐにおいて、その制御端子が対応するゲート線１４ｇに電気的に接続され、その第１端子が駆動ＴＦＴ９ｄの第２端子に電気的に接続され、その第２端子が駆動ＴＦＴ９ｄの制御端子に電気的に接続されている。なお、閾値電圧補償ＴＦＴ９ｂの制御端子は、図３に示すように、ゲート線１４ｇの第１半導体層１２ａと重なる２つの部分である。また、閾値電圧補償ＴＦＴ９ｂの第１端子は、図３に示すように、駆動ＴＦＴ９ｄの第２端子と一体に形成されて、駆動ＴＦＴ９ｄの第２端子に電気的に接続されている。また、閾値電圧補償ＴＦＴ９ｂの第２端子は、図３に示すように、第３コンタクトホールＨｃ、後述する第１接続配線１９ｅ及び第１コンタクトホールＨａを介して、駆動ＴＦＴ９ｄの第１ゲート電極１４ａに電気的に接続されている。ここで、閾値電圧補償ＴＦＴ９ｂは、ゲート線１４ｇの選択に応じて駆動ＴＦＴ９ｄをダイオード接続状態にして、駆動ＴＦＴ９ｄの閾値電圧を補償するように構成されている。
As shown in FIG. 4, in each sub-pixel P, the threshold voltage compensation TFT 9b has its control terminal electrically connected to the corresponding gate line 14g, and its first terminal electrically connected to the second terminal of the drive TFT 9d. The second terminal is electrically connected to the control terminal of the driving TFT 9d. The control terminal of the threshold voltage compensation TFT 9b is, as shown in FIG. 3, two portions of the gate line 14g that overlap the first semiconductor layer 12a. The first terminal of the threshold voltage compensation TFT 9b is integrally formed with the second terminal of the driving TFT 9d as shown in FIG. 3, and is electrically connected to the second terminal of the driving TFT 9d. The second terminal of the threshold voltage compensating TFT 9b is, as shown in FIG. 3, connected to the first gate electrode 14a of the driving TFT 9d via the third contact hole Hc, the first connection wiring 19e and the first contact hole Ha described later. Is electrically connected to. Here, the threshold voltage compensating TFT 9b is configured to compensate the threshold voltage of the driving TFT 9d by setting the driving TFT 9d in a diode connection state according to the selection of the gate line 14g.
書込制御ＴＦＴ９ｃは、図４に示すように、各サブ画素Ｐにおいて、その制御端子が対応するゲート線１４ｇに電気的に接続され、その第１端子が対応するソース線１９ｆに電気的に接続され、その第２端子が駆動ＴＦＴ９ｄの第１端子に電気的に接続されている。なお、書込制御ＴＦＴ９ｃの制御端子は、図３に示すように、ゲート線１４ｇの第１半導体層１２ａと重なる部分である。また、書込制御ＴＦＴ９ｃの第１端子は、図３に示すように、第６コンタクトホールＨｆを介して、ソース線１９ｆに電気的に接続されている。また、書込制御ＴＦＴ９ｃの第２端子は、図３に示すように、駆動ＴＦＴ９ｄの第１端子と一体に形成されて、駆動ＴＦＴ９ｄの第１端子に電気的に接続されている。ここで、書込制御ＴＦＴ９ｃは、ゲート線１４ｇの選択に応じてソース線１９ｆの電圧を駆動ＴＦＴ９ｄの第１端子に印加するように構成されている。
As shown in FIG. 4, the write control TFT 9c has its control terminal electrically connected to the corresponding gate line 14g and its first terminal electrically connected to the corresponding source line 19f in each sub-pixel P. The second terminal is electrically connected to the first terminal of the driving TFT 9d. The control terminal of the write control TFT 9c is a portion that overlaps the first semiconductor layer 12a of the gate line 14g, as shown in FIG. The first terminal of the write control TFT 9c is electrically connected to the source line 19f through the sixth contact hole Hf, as shown in FIG. Further, as shown in FIG. 3, the second terminal of the write control TFT 9c is formed integrally with the first terminal of the drive TFT 9d and is electrically connected to the first terminal of the drive TFT 9d. Here, the write control TFT 9c is configured to apply the voltage of the source line 19f to the first terminal of the drive TFT 9d according to the selection of the gate line 14g.
駆動ＴＦＴ９ｄは、図４に示すように、各サブ画素Ｐにおいて、その制御端子が第１初期化ＴＦＴ９ａの第１端子及び閾値電圧補償ＴＦＴ９ｂの第２端子に電気的に接続され、その第１端子が書込制御ＴＦＴ９ｃ及び電源供給ＴＦＴ９ｅの各第２端子に電気的に接続され、その第２端子が閾値電圧補償ＴＦＴ９ｂ及び発光制御ＴＦＴ９ｆの各第１端子に電気的に接続されている。ここで、駆動ＴＦＴ９ｄは、第１ＴＦＴとして設けられ、その制御端子とその第１端子との間に印加される電圧に応じた駆動電流を発光制御ＴＦＴ９ｆの第１端子に印加して、有機ＥＬ素子３５の電流量を制御するように構成されている。
As shown in FIG. 4, the drive TFT 9d has its control terminal electrically connected to the first terminal of the first initialization TFT 9a and the second terminal of the threshold voltage compensation TFT 9b in each sub-pixel P, and its first terminal. Are electrically connected to the respective second terminals of the write control TFT 9c and the power supply TFT 9e, and the second terminals thereof are electrically connected to the respective first terminals of the threshold voltage compensation TFT 9b and the light emission control TFT 9f. Here, the drive TFT 9d is provided as a first TFT, and a drive current according to a voltage applied between its control terminal and its first terminal is applied to the first terminal of the light emission control TFT 9f to apply the organic EL element. It is configured to control the current amount of 35.
具体的に、駆動ＴＦＴ９ｄは、図３及び図５に示すように、ベースコート膜１１上に順に設けられた第１半導体層１２ａ、ゲート絶縁膜１３、第１ゲート電極（制御端子）１４ａ、第１層間絶縁膜１５及び第２層間絶縁膜１７を備えている。ここで、第１半導体層１２ａは、図３及び図５に示すように、ベースコート膜１１上に屈曲した形状に設けられている。また、第１半導体層１２ａは、図５に示すように、第１ゲート電極１４ａに平面視で重なるように設けられた真性領域１２ａｃと、真性領域１２ａｃを挟むように設けられた第１導体領域（不図示）及び第２導体領域１２ａｂとを備えている。なお、真性領域１２ａｃは、図３及び図５に示すように、その中間部分が平面視で略Ｖ字形状に設けられている。また、第１半導体層１２ａの一方の導体領域は、第１端子として設けられ、図３に示すように、書込制御ＴＦＴ９ｃ及び電源供給ＴＦＴ９ｅの各第２端子と一体に形成されて、書込制御ＴＦＴ９ｃ及び電源供給ＴＦＴ９ｅの各第２端子に電気的に接続されている。また、第１半導体層１２ａの他方の導体領域は、第２端子として設けられ、図３に示すように、閾値電圧補償ＴＦＴ９ｂ及び発光制御ＴＦＴ９ｆの各第１端子と一体に形成されて、閾値電圧補償ＴＦＴ９ｂ及び発光制御ＴＦＴ９ｆの各第１端子に電気的に接続されている。また、ゲート絶縁膜１３は、図５に示すように、第１半導体層１２ａを覆うように設けられている。また、第１ゲート電極１４ａは、図３及び図５に示すように、ゲート絶縁膜１３上に半導体層１２ａのチャネル領域１２ａｃと重なるように平面視で矩形の島状にゲート金属層として設けられている。また、第１層間絶縁膜１５は、図５に示すように、第１ゲート電極１４ａを覆うように設けられている。また、第２層間絶縁膜１７は、図５に示すように、後述する容量電極１６ｃを介して、第１層間絶縁膜１５上に設けられている。
Specifically, as shown in FIGS. 3 and 5, the driving TFT 9d includes a first semiconductor layer 12a, a gate insulating film 13, a first gate electrode (control terminal) 14a, a first semiconductor layer 12a, a first gate electrode 14a, a first gate electrode (control terminal) 14a and a first semiconductor layer 12a, which are sequentially provided on the base coat film 11. An interlayer insulating film 15 and a second interlayer insulating film 17 are provided. Here, as shown in FIGS. 3 and 5, the first semiconductor layer 12a is provided on the base coat film 11 in a bent shape. In addition, as shown in FIG. 5, the first semiconductor layer 12a includes an intrinsic region 12ac provided so as to overlap the first gate electrode 14a in a plan view, and a first conductor region provided so as to sandwich the intrinsic region 12ac. (Not shown) and the second conductor region 12ab. In addition, as shown in FIGS. 3 and 5, the intrinsic region 12ac has an intermediate portion provided in a substantially V shape in a plan view. In addition, one conductor region of the first semiconductor layer 12a is provided as a first terminal, and as shown in FIG. 3, is integrally formed with each second terminal of the write control TFT 9c and the power supply TFT 9e to write data. It is electrically connected to each second terminal of the control TFT 9c and the power supply TFT 9e. Further, the other conductor region of the first semiconductor layer 12a is provided as a second terminal, and as shown in FIG. 3, it is integrally formed with each first terminal of the threshold voltage compensating TFT 9b and the emission control TFT 9f to obtain a threshold voltage. The compensation TFT 9b and the emission control TFT 9f are electrically connected to the respective first terminals. Further, the gate insulating film 13 is provided so as to cover the first semiconductor layer 12a, as shown in FIG. As shown in FIGS. 3 and 5, the first gate electrode 14a is provided on the gate insulating film 13 as a gate metal layer in a rectangular island shape in plan view so as to overlap with the channel region 12ac of the semiconductor layer 12a. ing. The first interlayer insulating film 15 is provided so as to cover the first gate electrode 14a, as shown in FIG. Further, as shown in FIG. 5, the second interlayer insulating film 17 is provided on the first interlayer insulating film 15 via a capacitance electrode 16c described later.
電源供給ＴＦＴ９ｅは、図４に示すように、各サブ画素Ｐにおいて、その制御端子が対応する発光制御線１４ｅに電気的に接続され、その第１端子が対応する電源線１９ｇに電気的に接続され、その第２端子が駆動ＴＦＴ９ｄの第１端子に電気的に接続されている。ここで、電源供給ＴＦＴ９ｅは、第２ＴＦＴとして設けられ、発光制御線１４ｅの選択に応じて電源線１９ｇの電圧を駆動ＴＦＴ９ｄの第１端子に印加するように構成されている。
As shown in FIG. 4, in each sub-pixel P, the power supply TFT 9e has its control terminal electrically connected to the corresponding light emission control line 14e and its first terminal electrically connected to the corresponding power supply line 19g. The second terminal is electrically connected to the first terminal of the driving TFT 9d. Here, the power supply TFT 9e is provided as a second TFT, and is configured to apply the voltage of the power supply line 19g to the first terminal of the drive TFT 9d according to the selection of the light emission control line 14e.
具体的に、電源供給ＴＦＴ９ｅは、図３及び図６に示すように、ベースコート膜１１上に順に設けられた第２半導体層１２ｂ、ゲート絶縁膜１３、発光制御線（第２ゲート電極、制御端子）１４ｅ、第１層間絶縁膜１５及び第２層間絶縁膜１７を備えている。ここで、第２半導体層１２ｂは、図３及び図６に示すように、ベースコート膜１１上に屈曲した形状に設けられている。また、第２半導体層１２ｂは、図６に示すように、発光制御線１４ｅに平面視で重なるように設けられた真性領域１２ｂｃと、真性領域１２ｂｃを挟むように設けられた第１導体領域１２ｂａ及び第２導体領域１２ｂｂとを備えている。なお、第１導体領域１２ｂａは、第２端子として設けられ、図３に示すように、駆動ＴＦＴ９ｄの第１端子と一体に形成されて、駆動ＴＦＴ９ｄの第１端子に電気的に接続されている。また、第２導体領域１２ｂｂは、第１端子として設けられ、図３及び図６に示すように、後述する有機絶縁膜１８に形成された第２コンタクトホールＨｂを介して、電源線１９ｇに電気的に接続されている。また、ゲート絶縁膜１３は、図６に示すように、第２半導体層１２ｂを覆うように設けられている。また、第２ゲート電極（制御端子）は、ゲート金属層として設けられ、発光制御線１４ｅの第２半導体層１２ｂと重なる部分である。また、第１層間絶縁膜１５は、図６に示すように、発光制御線１４ｅを覆うように設けられている。また、第２層間絶縁膜１７は、図６に示すように、第１層間絶縁膜１５上に設けられている。また、ゲート絶縁膜１３、第１層間絶縁膜１５及び第２層間絶縁膜１７には、図３及び図６に示すように、ゲート絶縁膜１３、第１層間絶縁膜１５及び第２層間絶縁膜１７を貫通して、第２導体領域１２ｂｂに到達するように第３開口部Ｍｃが設けられている。また、有機絶縁膜１８には、図３及び図６に示すように、平面視で第３開口部Ｍｃと重なると共に、有機絶縁膜１８を貫通するように第２コンタクトホールＨｂが設けられている。また、第２コンタクトホールＨｂは、図３及び図６に示すように、発光制御線１４ｅと隣り合うように設けられている。また、第３開口部Ｍｃの周縁は、図３に示すように、平面視で第２コンタクトホールＨｂの周縁よりも外側に設けられている。また、第２コンタクトホールＨｂの側面は、樹脂基板層１０側に向けて順テーパ状に傾斜している。なお、第２半導体層１２ｂは、図３において、便宜上、２点鎖線により第１半導体層１２ａと区切って示しているが、上述したように、第１半導体層１２ａと一体に設けられている。
Specifically, as shown in FIGS. 3 and 6, the power supply TFT 9e includes a second semiconductor layer 12b, a gate insulating film 13, and a light emission control line (second gate electrode, control terminal) provided in this order on the base coat film 11. ) 14e, a first interlayer insulating film 15 and a second interlayer insulating film 17. Here, as shown in FIGS. 3 and 6, the second semiconductor layer 12b is provided in a bent shape on the base coat film 11. In addition, as shown in FIG. 6, the second semiconductor layer 12b includes an intrinsic region 12bc provided so as to overlap the emission control line 14e in a plan view and a first conductor region 12ba provided so as to sandwich the intrinsic region 12bc. And a second conductor region 12bb. The first conductor region 12ba is provided as a second terminal, is formed integrally with the first terminal of the drive TFT 9d, and is electrically connected to the first terminal of the drive TFT 9d, as shown in FIG. .. Further, the second conductor region 12bb is provided as a first terminal, and as shown in FIGS. 3 and 6, electricity is supplied to the power supply line 19g via the second contact hole Hb formed in the organic insulating film 18 described later. Is connected. Further, the gate insulating film 13 is provided so as to cover the second semiconductor layer 12b, as shown in FIG. The second gate electrode (control terminal) is provided as a gate metal layer and is a portion that overlaps the second semiconductor layer 12b of the emission control line 14e. The first interlayer insulating film 15 is provided so as to cover the light emission control line 14e, as shown in FIG. Further, the second interlayer insulating film 17 is provided on the first interlayer insulating film 15, as shown in FIG. Further, as shown in FIGS. 3 and 6, the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17 have the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17. A third opening Mc is provided so as to penetrate 17 and reach the second conductor region 12bb. Further, as shown in FIGS. 3 and 6, the organic insulating film 18 is provided with a second contact hole Hb so as to overlap the third opening Mc in a plan view and to penetrate the organic insulating film 18. .. The second contact hole Hb is provided so as to be adjacent to the light emission control line 14e, as shown in FIGS. Further, as shown in FIG. 3, the peripheral edge of the third opening Mc is provided outside the peripheral edge of the second contact hole Hb in plan view. Further, the side surface of the second contact hole Hb is inclined in a forward taper shape toward the resin substrate layer 10 side. Although the second semiconductor layer 12b is shown separated from the first semiconductor layer 12a by a two-dot chain line in FIG. 3 for convenience, it is provided integrally with the first semiconductor layer 12a as described above.
発光制御ＴＦＴ９ｆは、図４に示すように、各サブ画素Ｐにおいて、その制御端子が対応する発光制御線１４ｅに電気的に接続され、その第１端子が駆動ＴＦＴ９ｄの第２端子に電気的に接続され、その第２端子が後述する有機ＥＬ素子３５の第１電極３１に電気的に接続されている。なお、発光制御ＴＦＴ９ｆの制御端子は、図３に示すように、発光制御線１４ｅの第１半導体層１２ａと重なる部分である。また、発光制御ＴＦＴ９ｆの第１端子は、図３に示すように、駆動ＴＦＴ９ｄの第２端子と一体に形成されて、駆動ＴＦＴ９ｄの第２端子に電気的に接続されている。また、発光制御ＴＦＴ９ｆの第２端子は、図３に示すように、第７コンタクトホールＨｇ及び第３接続配線１９ｉを介して、有機ＥＬ素子３５の第１電極３１に電気的に接続されている。ここで、発光制御ＴＦＴ９ｆは、発光制御線１４ｅの選択に応じて上記駆動電流を有機ＥＬ素子３５に印加するように構成されている。
As shown in FIG. 4, in each light emitting control TFT 9f, its control terminal is electrically connected to the corresponding light emission control line 14e, and its first terminal is electrically connected to the second terminal of the drive TFT 9d. The second terminal is electrically connected to the first electrode 31 of the organic EL element 35 described later. The control terminal of the light emission control TFT 9f is a portion that overlaps with the first semiconductor layer 12a of the light emission control line 14e, as shown in FIG. Further, as shown in FIG. 3, the first terminal of the light emission control TFT 9f is formed integrally with the second terminal of the driving TFT 9d and is electrically connected to the second terminal of the driving TFT 9d. The second terminal of the emission control TFT 9f is electrically connected to the first electrode 31 of the organic EL element 35 via the seventh contact hole Hg and the third connection wiring 19i, as shown in FIG. .. Here, the light emission control TFT 9f is configured to apply the drive current to the organic EL element 35 according to the selection of the light emission control line 14e.
第２初期化ＴＦＴ９ｇは、図４に示すように、各画素Ｐにおいて、その制御端子が対応するゲート線１４ｇに電気的に接続され、その第１端子が有機ＥＬ素子３５の第１端子３１に電気的に接続され、その第２端子が対応する初期化電源線１６ｉに電気的に接続されている。なお、第２初期化ＴＦＴ９ｇの制御端子は、図３に示すように、ゲート線１４ｇの第１半導体層１２ａと重なる部分である。また、第２初期化ＴＦＴ９ｇの第１端子は、図３に示すように、発光制御ＴＦＴ９ｆの第２端子と一体に形成されて、有機ＥＬ素子３５の第１電極３１に電気的に接続されている。また、第２初期化ＴＦＴ９ｇの第２端子は、図３に示すように、第４コンタクトホールＨｄ、第２接続配線１９ｈ及び第５コンタクトホールＨｅを介して、初期化電源線１６ｉに電気的に接続されている。ここで、第２初期化ＴＦＴ９ｇは、ゲート線１４ｇの選択に応じて有機ＥＬ素子３５の第１電極３１に蓄積した電荷をリセットするように構成されている。
As shown in FIG. 4, in each pixel P, the control terminal of the second initialization TFT 9g is electrically connected to the corresponding gate line 14g, and the first terminal thereof is connected to the first terminal 31 of the organic EL element 35. It is electrically connected, and its second terminal is electrically connected to the corresponding initialization power supply line 16i. The control terminal of the second initialization TFT 9g is a portion that overlaps the first semiconductor layer 12a of the gate line 14g, as shown in FIG. Further, as shown in FIG. 3, the first terminal of the second initialization TFT 9g is integrally formed with the second terminal of the emission control TFT 9f and electrically connected to the first electrode 31 of the organic EL element 35. There is. The second terminal of the second initialization TFT 9g is electrically connected to the initialization power supply line 16i via the fourth contact hole Hd, the second connection wiring 19h and the fifth contact hole He, as shown in FIG. It is connected. Here, the second initialization TFT 9g is configured to reset the charge accumulated in the first electrode 31 of the organic EL element 35 in accordance with the selection of the gate line 14g.
キャパシタ９ｈは、図３及び図５に示すように、第１ゲート電極１４ａと、ゲート電極１４ａ上に設けられた第１層間絶縁膜１５と、第１層間絶縁膜１５上にゲート電極１４ａに平面視で重なるように設けられた容量電極１６ｃとを備えている。また、キャパシタ９ｈは、図３及び図４に示すように、各サブ画素Ｐにおいて、その第１ゲート電極１４ａが駆動ＴＦＴ９ｄの第１ゲート電極１４ａと一体に形成されて、駆動ＴＦＴ９ｄの第１ゲート電極１４ａ、第１初期化ＴＦＴ９ａの第１端子及び閾値電圧補償ＴＦＴ９ｂの第２端子に電気的に接続され、その容量電極１６ｃが第８コンタクトホールＨｈを介して対応する電源線１９ｇに電気的に接続されている。ここで、キャパシタ９ｈは、対応するゲート線１４ｇが選択状態のときに対応するソース線１９ｆの電圧で蓄電し、蓄電した電圧を保持することにより、対応するゲート線１４ｇが非選択状態のときに駆動ＴＦＴ９ｄの第１ゲート電極１４ａにかかる電圧を維持するように構成されている。また、容量電極１６ｃは、図３に示すように、第１ゲート電極１４ａの周端の全周にわたりゲート電極１４ａの周端の外側まで設けられている。また、容量電極１６ｃには、図３及び図５に示すように、平面視で第１ゲート電極１４ａと重なると共に容量電極１６ｃを貫通するように第１開口部Ｍａが設けられている。また、容量電極１６ｃ上には、図５に示すように、容量電極１６ｃを覆うように第２層間絶縁膜１７が設けられている。また、第１層間絶縁膜１５及び第２層間絶縁膜１７には、図３及び図５に示すように、平面視で第１開口部Ｍａの周縁の内側に配置すると共に、第１層間絶縁膜１５及び第２層間絶縁膜１７を貫通するように第２開口部Ｍｂが設けられている。また、第２層間絶縁膜１７上には、図５に示すように、塗布型の絶縁材料により形成された有機絶縁膜１８が設けられている。また、有機絶縁膜１８には、図３及び図５に示すように、平面視で第２開口部Ｍｂの周縁の内側に配置すると共に、有機絶縁膜１８を貫通するように第１コンタクトホールＨａが設けられている。また、第１ゲート電極１４ａは、図３及び図５に示すように、第１コンタクトホールＨａを介して、ソース金属層として設けられた第１接続配線１９ｅに電気的に接続されている。なお、有機絶縁膜１８は、図５に示すように、第２開口部Ｍｂの側面を覆うように設けられている。また、第２開口部Ｍｂの周縁は、図３に示すように、平面視で第１コンタクトホールＨａの周縁よりも外側に設けられている。また、第１コンタクトホールＨａの側面は、図５に示すように、樹脂基板層１０に向けて順テーパ状に傾斜している。
As shown in FIGS. 3 and 5, the capacitor 9h includes a first gate electrode 14a, a first interlayer insulating film 15 provided on the gate electrode 14a, and a plane on the gate electrode 14a on the first interlayer insulating film 15. The capacitor electrode 16c is provided so as to overlap with the eyes. As shown in FIGS. 3 and 4, in the capacitor 9h, the first gate electrode 14a of each sub-pixel P is formed integrally with the first gate electrode 14a of the driving TFT 9d, and the first gate electrode of the driving TFT 9d is formed. The electrode 14a is electrically connected to the first terminal of the first initialization TFT 9a and the second terminal of the threshold voltage compensation TFT 9b, and the capacitance electrode 16c is electrically connected to the corresponding power supply line 19g through the eighth contact hole Hh. It is connected. Here, the capacitor 9h stores the voltage at the corresponding source line 19f when the corresponding gate line 14g is in the selected state, and holds the stored voltage so that the corresponding gate line 14g is in the non-selected state. It is configured to maintain the voltage applied to the first gate electrode 14a of the drive TFT 9d. Further, as shown in FIG. 3, the capacitance electrode 16c is provided to the outside of the peripheral edge of the gate electrode 14a over the entire peripheral edge of the first gate electrode 14a. As shown in FIGS. 3 and 5, the capacitance electrode 16c is provided with a first opening Ma that overlaps the first gate electrode 14a in plan view and penetrates the capacitance electrode 16c. Further, as shown in FIG. 5, a second interlayer insulating film 17 is provided on the capacitance electrode 16c so as to cover the capacitance electrode 16c. In addition, as shown in FIGS. 3 and 5, the first interlayer insulating film 15 and the second interlayer insulating film 17 are arranged inside the peripheral edge of the first opening Ma in plan view, and the first interlayer insulating film is formed. A second opening Mb is provided so as to penetrate 15 and the second interlayer insulating film 17. Further, on the second interlayer insulating film 17, as shown in FIG. 5, an organic insulating film 18 formed of a coating type insulating material is provided. Further, as shown in FIGS. 3 and 5, the organic insulating film 18 is arranged inside the peripheral edge of the second opening Mb in plan view, and the first contact hole Ha is formed so as to penetrate the organic insulating film 18. Is provided. Further, as shown in FIGS. 3 and 5, the first gate electrode 14a is electrically connected to the first connection wiring 19e provided as the source metal layer via the first contact hole Ha. The organic insulating film 18 is provided so as to cover the side surface of the second opening Mb, as shown in FIG. Further, as shown in FIG. 3, the peripheral edge of the second opening Mb is provided outside the peripheral edge of the first contact hole Ha in plan view. Further, the side surface of the first contact hole Ha is inclined in a forward taper shape toward the resin substrate layer 10 as shown in FIG.
平坦化膜２０は、例えば、ポリイミド樹脂等の有機樹脂材料により構成されている。
The flattening film 20 is made of, for example, an organic resin material such as polyimide resin.
以下に、ＴＦＴ層３０ａに設けられた第１コンタクトホールＨａ～第５コンタクトホールＨｅについて説明する。
The first to fifth contact holes Ha to He provided in the TFT layer 30a will be described below.
第１コンタクトホールＨａは、ゲート金属層とソース金属層とを電気的に接続するためのものである。また、第２コンタクトホールＨｂ～第４コンタクトホールＨｄは、半導体層の導体領域とソース金属層とを電気的に接続するためのものである。また、第５コンタクトホールＨｅは、中間金属層とソース金属層とを電気的に接続するためのものである。
The first contact hole Ha is for electrically connecting the gate metal layer and the source metal layer. The second to fourth contact holes Hb to Hd are for electrically connecting the conductor region of the semiconductor layer and the source metal layer. The fifth contact hole He is for electrically connecting the intermediate metal layer and the source metal layer.
第１コンタクトホールＨａ及び第２コンタクトホールＨｂは、図５及び図６に示すように、第１層間絶縁膜１５及び第２層間絶縁膜１７の対応する開口部を充填する有機絶縁膜１８に設けられている。これは、第１コンタクトホールＨａの近くに容量電極１６ｃが設けられ、第２コンタクトホールＨｂの近くに発光制御線１４ｅが設けられているので、ソース金属層と、容量電極１６ｃ及び発光制御線１４ｅと短絡し易いためである。
The first contact hole Ha and the second contact hole Hb are provided in the organic insulating film 18 filling the corresponding openings of the first interlayer insulating film 15 and the second interlayer insulating film 17, as shown in FIGS. Has been. This is because the capacitance electrode 16c is provided near the first contact hole Ha and the emission control line 14e is provided near the second contact hole Hb, so that the source metal layer, the capacitance electrode 16c and the emission control line 14e are provided. This is because it is easy to short circuit.
また、第３コンタクトホールＨｃは、図５に示すように、層間絶縁膜（第１層間絶縁膜１５及び第２層間絶縁膜１７）に設けられている。これは、第３コンタクトホールＨｃの近くには、図５に示すように、第１コンタクトホールＨａ及び第２コンタクトホールＨｃと比べ、半導体層よりも上層に金属層が存在しないためである。
Further, the third contact hole Hc is provided in the interlayer insulating film (first interlayer insulating film 15 and second interlayer insulating film 17) as shown in FIG. This is because there is no metal layer near the third contact hole Hc above the semiconductor layer, as shown in FIG. 5, as compared with the first contact hole Ha and the second contact hole Hc.
また、第４コンタクトホールＨｄ及び第５コンタクトホールＨｅにおいて、第１層間絶縁膜１５及び第２層間絶縁膜１７にコンタクトホールを設けるか、又は有機絶縁膜１８にコンタクトホールを設けるかは、そのコンタクトホールと金属層との距離によって選択する。
In addition, in the fourth contact hole Hd and the fifth contact hole He, whether the contact hole is provided in the first interlayer insulating film 15 and the second interlayer insulating film 17 or the contact hole is provided in the organic insulating film 18 It is selected according to the distance between the hole and the metal layer.
上述した第１コンタクトホールＨａ～第３コンタクトホールＨｃの構造は、一例であって、コンタクトホールと金属層との距離が遠ければ、コンタクトホールを層間絶縁膜に設け、コンタクトホールと金属層との距離が近ければ、コンタクトホールを層間絶縁膜の内部の有機絶縁膜に設けるようにするとよい。
The structure of the first contact hole Ha to the third contact hole Hc described above is an example, and if the distance between the contact hole and the metal layer is long, the contact hole is provided in the interlayer insulating film and the contact hole is separated from the metal layer. If the distance is short, the contact hole may be provided in the organic insulating film inside the interlayer insulating film.
有機ＥＬ素子層４０は、図５及び図６に示すように、平坦化膜１９上にマトリクス状に配列するように複数の発光素子として設けられた複数の有機ＥＬ素子３５と、各有機ＥＬ素子３５を覆うように設けられた封止膜４５とを備えている。
As shown in FIGS. 5 and 6, the organic EL element layer 40 includes a plurality of organic EL elements 35 provided as a plurality of light emitting elements so as to be arranged in a matrix on the flattening film 19, and each organic EL element. 35 and a sealing film 45 provided so as to cover 35.
有機ＥＬ素子３５は、図５及び図６に示すように、平坦化膜２０上に島状に設けられた第１電極３１と、第１電極３１の周端部を覆うように設けられたエッジカバー３２と、第１電極３１上に設けられた有機ＥＬ層３３（不図示）、表示領域Ｄ全体で共通するように有機ＥＬ層３３上に設けられた第２電極３４とを備えている。
As shown in FIGS. 5 and 6, the organic EL element 35 has an island-shaped first electrode 31 on the flattening film 20 and an edge provided so as to cover the peripheral end of the first electrode 31. A cover 32, an organic EL layer 33 (not shown) provided on the first electrode 31, and a second electrode 34 provided on the organic EL layer 33 so as to be common to the entire display region D are provided.
第１電極３１は、図３に示すように、平坦化膜２０に形成されたコンタクトホールを介して、各サブ画素Ｐの発光制御ＴＦＴ９ｆの第２端子に電気的に接続されている。また、第１電極３１は、有機ＥＬ層３３にホール（正孔）を注入する機能を有している。また、第１電極３１は、有機ＥＬ層３３への正孔注入効率を向上させるために、仕事関数の大きな材料で形成するのがより好ましい。ここで、第１電極３１を構成する材料としては、例えば、銀（Ａｇ）、アルミニウム（Ａｌ）、バナジウム（Ｖ）、コバルト（Ｃｏ）、ニッケル（Ｎｉ）、タングステン（Ｗ）、金（Ａｕ）、チタン（Ｔｉ）、ルテニウム（Ｒｕ）、マンガン（Ｍｎ）、インジウム（Ｉｎ）、イッテルビウム（Ｙｂ）、フッ化リチウム（ＬｉＦ）、白金（Ｐｔ）、パラジウム（Ｐｄ）、モリブデン（Ｍｏ）、イリジウム（Ｉｒ）、スズ（Ｓｎ）等の金属材料が挙げられる。また、第１電極３１を構成する材料は、例えば、アスタチン（Ａｔ）／酸化アスタチン（ＡｔＯ２）等の合金であっても構わない。さらに、第１電極３１を構成する材料は、例えば、酸化スズ（ＳｎＯ）、酸化亜鉛（ＺｎＯ）、インジウムスズ酸化物（ＩＴＯ）、インジウム亜鉛酸化物（ＩＺＯ）のような導電性酸化物等であってもよい。また、第１電極３１は、上記材料からなる層を複数積層して形成されていてもよい。なお、仕事関数の大きな化合物材料としては、例えば、インジウムスズ酸化物（ＩＴＯ）やインジウム亜鉛酸化物（ＩＺＯ）等が挙げられる。
As shown in FIG. 3, the first electrode 31 is electrically connected to the second terminal of the light emission control TFT 9f of each sub-pixel P via a contact hole formed in the flattening film 20. In addition, the first electrode 31 has a function of injecting holes into the organic EL layer 33. Further, the first electrode 31 is more preferably formed of a material having a large work function in order to improve the efficiency of injecting holes into the organic EL layer 33. Here, as a material forming the first electrode 31, for example, silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au). , Titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium ( Metal materials such as Ir) and tin (Sn) can be cited. The material forming the first electrode 31 may be an alloy such as astatine (At)/oxidized astatine (AtO 2 ). Further, the material forming the first electrode 31 is, for example, a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO). It may be. Further, the first electrode 31 may be formed by stacking a plurality of layers made of the above materials. Examples of the compound material having a large work function include indium tin oxide (ITO) and indium zinc oxide (IZO).
エッジカバー３２は、表示領域Ｄ全体で共通するように格子状に設けられている。ここで、エッジカバー３２を構成する材料としては、例えば、ポリイミド樹脂、アクリル樹脂、ポリシロキサン樹脂、ノボラック樹脂等が挙げられる。
The edge cover 32 is provided in a grid shape so as to be common to the entire display area D. Here, examples of the material forming the edge cover 32 include a polyimide resin, an acrylic resin, a polysiloxane resin, and a novolac resin.
有機ＥＬ層３３は、図７に示すように、第１電極３１上に順に設けられた正孔注入層１、正孔輸送層２、発光層３、電子輸送層４及び電子注入層５を備えている。
As shown in FIG. 7, the organic EL layer 33 includes a hole injection layer 1, a hole transport layer 2, a light emitting layer 3, an electron transport layer 4, and an electron injection layer 5, which are sequentially provided on the first electrode 31. ing.
正孔注入層１は、陽極バッファ層とも呼ばれ、第１電極３１と有機ＥＬ層３３とのエネルギーレベルを近づけ、第１電極３１から有機ＥＬ層３３への正孔注入効率を改善する機能を有している。ここで、正孔注入層１を構成する材料としては、例えば、トリアゾール誘導体、オキサジアゾール誘導体、イミダゾール誘導体、ポリアリールアルカン誘導体、ピラゾリン誘導体、フェニレンジアミン誘導体、オキサゾール誘導体、スチリルアントラセン誘導体、フルオレノン誘導体、ヒドラゾン誘導体、スチルベン誘導体等が挙げられる。
The hole injection layer 1 is also called an anode buffer layer and has a function of bringing the energy levels of the first electrode 31 and the organic EL layer 33 close to each other and improving the hole injection efficiency from the first electrode 31 to the organic EL layer 33. Have Here, as the material constituting the hole injection layer 1, for example, a triazole derivative, an oxadiazole derivative, an imidazole derivative, a polyarylalkane derivative, a pyrazoline derivative, a phenylenediamine derivative, an oxazole derivative, a styrylanthracene derivative, a fluorenone derivative, Examples thereof include hydrazone derivatives and stilbene derivatives.
正孔輸送層２は、第１電極３１から有機ＥＬ層３３への正孔の輸送効率を向上させる機能を有している。ここで、正孔輸送層２を構成する材料としては、例えば、ポルフィリン誘導体、芳香族第三級アミン化合物、スチリルアミン誘導体、ポリビニルカルバゾール、ポリ－ｐ－フェニレンビニレン、ポリシラン、トリアゾール誘導体、オキサジアゾール誘導体、イミダゾール誘導体、ポリアリールアルカン誘導体、ピラゾリン誘導体、ピラゾロン誘導体、フェニレンジアミン誘導体、アリールアミン誘導体、アミン置換カルコン誘導体、オキサゾール誘導体、スチリルアントラセン誘導体、フルオレノン誘導体、ヒドラゾン誘導体、スチルベン誘導体、水素化アモルファスシリコン、水素化アモルファス炭化シリコン、硫化亜鉛、セレン化亜鉛等が挙げられる。
The hole transport layer 2 has a function of improving the efficiency of transporting holes from the first electrode 31 to the organic EL layer 33. Here, examples of the material forming the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, styrylamine derivatives, polyvinylcarbazole, poly-p-phenylenevinylene, polysilane, triazole derivatives, and oxadiazole. Derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, Examples thereof include hydride amorphous silicon carbide, zinc sulfide, and zinc selenium.
発光層３は、第１電極３１及び第２電極３４による電圧印加の際に、第１電極３１及び第２電極３４から正孔及び電子がそれぞれ注入されると共に、正孔及び電子が再結合する領域である。ここで、発光層３は、発光効率が高い材料により形成されている。そして、発光層３を構成する材料としては、例えば、金属オキシノイド化合物［８－ヒドロキシキノリン金属錯体］、ナフタレン誘導体、アントラセン誘導体、ジフェニルエチレン誘導体、ビニルアセトン誘導体、トリフェニルアミン誘導体、ブタジエン誘導体、クマリン誘導体、ベンズオキサゾール誘導体、オキサジアゾール誘導体、オキサゾール誘導体、ベンズイミダゾール誘導体、チアジアゾール誘導体、ベンズチアゾール誘導体、スチリル誘導体、スチリルアミン誘導体、ビススチリルベンゼン誘導体、トリススチリルベンゼン誘導体、ペリレン誘導体、ペリノン誘導体、アミノピレン誘導体、ピリジン誘導体、ローダミン誘導体、アクイジン誘導体、フェノキサゾン、キナクリドン誘導体、ルブレン、ポリ－ｐ－フェニレンビニレン、ポリシラン等が挙げられる。
In the light emitting layer 3, when the voltage is applied by the first electrode 31 and the second electrode 34, holes and electrons are injected from the first electrode 31 and the second electrode 34, respectively, and the holes and electrons are recombined. Area. Here, the light emitting layer 3 is formed of a material having high luminous efficiency. Examples of the material forming the light emitting layer 3 include metal oxinoid compound [8-hydroxyquinoline metal complex], naphthalene derivative, anthracene derivative, diphenylethylene derivative, vinylacetone derivative, triphenylamine derivative, butadiene derivative, coumarin derivative. , Benzoxazole derivative, oxadiazole derivative, oxazole derivative, benzimidazole derivative, thiadiazole derivative, benzthiazole derivative, styryl derivative, styrylamine derivative, bisstyrylbenzene derivative, trisstyrylbenzene derivative, perylene derivative, perinone derivative, aminopyrene derivative, Pyridine derivatives, rhodamine derivatives, aquidin derivatives, phenoxazone, quinacridone derivatives, rubrene, poly-p-phenylene vinylene, polysilane and the like can be mentioned.
電子輸送層４は、電子を発光層３まで効率良く移動させる機能を有している。ここで、電子輸送層４を構成する材料としては、例えば、有機化合物として、オキサジアゾール誘導体、トリアゾール誘導体、ベンゾキノン誘導体、ナフトキノン誘導体、アントラキノン誘導体、テトラシアノアントラキノジメタン誘導体、ジフェノキノン誘導体、フルオレノン誘導体、シロール誘導体、金属オキシノイド化合物等が挙げられる。
The electron transport layer 4 has a function of efficiently moving electrons to the light emitting layer 3. Here, examples of the material forming the electron transport layer 4 include organic compounds such as oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, diphenoquinone derivatives, and fluorenone derivatives. , Silole derivatives, metal oxinoid compounds and the like.
電子注入層５は、第２電極３４と有機ＥＬ層３３とのエネルギーレベルを近づけ、第２電極３４から有機ＥＬ層３３へ電子が注入される効率を向上させる機能を有し、この機能により、有機ＥＬ素子３５の駆動電圧を下げることができる。なお、電子注入層５は、陰極バッファ層とも呼ばれる。ここで、電子注入層５を構成する材料としては、例えば、フッ化リチウム（ＬｉＦ）、フッ化マグネシウム（ＭｇＦ２）、フッ化カルシウム（ＣａＦ２）、フッ化ストロンチウム（ＳｒＦ２）、フッ化バリウム（ＢａＦ２）のような無機アルカリ化合物、酸化アルミニウム（Ａｌ２Ｏ３）、酸化ストロンチウム（ＳｒＯ）等が挙げられる。
The electron injection layer 5 has a function of bringing the energy levels of the second electrode 34 and the organic EL layer 33 close to each other and improving the efficiency of injecting electrons from the second electrode 34 to the organic EL layer 33. With this function, The drive voltage of the organic EL element 35 can be lowered. The electron injection layer 5 is also called a cathode buffer layer. Here, as a material forming the electron injection layer 5, for example, lithium fluoride (LiF), magnesium fluoride (MgF 2 ), calcium fluoride (CaF 2 ), strontium fluoride (SrF 2 ), barium fluoride. Inorganic alkali compounds such as (BaF 2 ), aluminum oxide (Al 2 O 3 ), strontium oxide (SrO) and the like can be mentioned.
第２電極３４は、図５及び図６に示すように、各サブ画素Ｐの有機ＥＬ層３３、及び全サブ画素Ｐに共通するエッジカバー３２を覆うように設けられている。また、第２電極３４は、有機ＥＬ層３３に電子を注入する機能を有している。また、第２電極３４は、有機ＥＬ層３３への電子注入効率を向上させるために、仕事関数の小さな材料で構成するのがより好ましい。ここで、第２電極３４を構成する材料としては、例えば、銀（Ａｇ）、アルミニウム（Ａｌ）、バナジウム（Ｖ）、コバルト（Ｃｏ）、ニッケル（Ｎｉ）、タングステン（Ｗ）、金（Ａｕ）、カルシウム（Ｃａ）、チタン（Ｔｉ）、イットリウム（Ｙ）、ナトリウム（Ｎａ）、ルテニウム（Ｒｕ）、マンガン（Ｍｎ）、インジウム（Ｉｎ）、マグネシウム（Ｍｇ）、リチウム（Ｌｉ）、イッテルビウム（Ｙｂ）、フッ化リチウム（ＬｉＦ）等が挙げられる。また、第２電極３４は、例えば、マグネシウム（Ｍｇ）／銅（Ｃｕ）、マグネシウム（Ｍｇ）／銀（Ａｇ）、ナトリウム（Ｎａ）／カリウム（Ｋ）、アスタチン（Ａｔ）／酸化アスタチン（ＡｔＯ２）、リチウム（Ｌｉ）／アルミニウム（Ａｌ）、リチウム（Ｌｉ）／カルシウム（Ｃａ）／アルミニウム（Ａｌ）、フッ化リチウム（ＬｉＦ）／カルシウム（Ｃａ）／アルミニウム（Ａｌ）等の合金により形成されていてもよい。また、第２電極３４は、例えば、酸化スズ（ＳｎＯ）、酸化亜鉛（ＺｎＯ）、インジウムスズ酸化物（ＩＴＯ）、インジウム亜鉛酸化物（ＩＺＯ）等の導電性酸化物により形成されていてもよい。また、第２電極３４は、上記材料からなる層を複数積層して形成されていてもよい。なお、仕事関数が小さい材料としては、例えば、マグネシウム（Ｍｇ）、リチウム（Ｌｉ）、フッ化リチウム（ＬｉＦ）、マグネシウム（Ｍｇ）／銅（Ｃｕ）、マグネシウム（Ｍｇ）／銀（Ａｇ）、ナトリウム（Ｎａ）／カリウム（Ｋ）、リチウム（Ｌｉ）／アルミニウム（Ａｌ）、リチウム（Ｌｉ）／カルシウム（Ｃａ）／アルミニウム（Ａｌ）、フッ化リチウム（ＬｉＦ）／カルシウム（Ｃａ）／アルミニウム（Ａｌ）等が挙げられる。
As shown in FIGS. 5 and 6, the second electrode 34 is provided so as to cover the organic EL layer 33 of each sub-pixel P and the edge cover 32 common to all the sub-pixels P. Further, the second electrode 34 has a function of injecting electrons into the organic EL layer 33. Further, the second electrode 34 is more preferably made of a material having a small work function in order to improve the efficiency of injecting electrons into the organic EL layer 33. Here, as a material forming the second electrode 34, for example, silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au). , Calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), ruthenium (Ru), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb). , Lithium fluoride (LiF), and the like. The second electrode 34 is, for example, magnesium (Mg)/copper (Cu), magnesium (Mg)/silver (Ag), sodium (Na)/potassium (K), astatine (At)/oxidized astatine (AtO 2 ). ), lithium (Li)/aluminum (Al), lithium (Li)/calcium (Ca)/aluminum (Al), lithium fluoride (LiF)/calcium (Ca)/aluminum (Al), and the like. May be. The second electrode 34 may be formed of a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO). .. The second electrode 34 may be formed by stacking a plurality of layers made of the above materials. Examples of the material having a small work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg)/copper (Cu), magnesium (Mg)/silver (Ag), and sodium. (Na)/potassium (K), lithium (Li)/aluminum (Al), lithium (Li)/calcium (Ca)/aluminum (Al), lithium fluoride (LiF)/calcium (Ca)/aluminum (Al) Etc.
封止膜４５は、図５及び図６に示すように、第２電極３４を覆うように設けられた第１封止無機絶縁膜４１と、第１封止無機絶縁膜４１上に設けられた封止有機膜４２と、封止有機膜４２を覆うように設けられた第２封止無機絶縁膜４３とを備え、有機ＥＬ層３３を水分や酸素等から保護する機能を有している。ここで、第１封止無機絶縁膜４１及び第２封止無機絶縁膜４３は、例えば、酸化シリコン（ＳｉＯ２）や酸化アルミニウム（Ａｌ２Ｏ３）、四窒化三ケイ素（Ｓｉ３Ｎ４）のような窒化シリコン（ＳｉＮｘ（ｘは正数））、炭窒化ケイ素（ＳｉＣＮ）等の無機材料により構成されている。また、封止有機膜４２は、例えば、アクリル樹脂、ポリ尿素樹脂、パリレン樹脂、ポリイミド樹脂、ポリアミド樹脂等の有機材料により構成されている。
As shown in FIGS. 5 and 6, the sealing film 45 is provided on the first sealing inorganic insulating film 41 provided so as to cover the second electrode 34 and the first sealing inorganic insulating film 41. The sealing organic film 42 and the second sealing inorganic insulating film 43 provided so as to cover the sealing organic film 42 are provided, and have a function of protecting the organic EL layer 33 from moisture, oxygen and the like. Here, the first sealing inorganic insulating film 41 and the second sealing inorganic insulating film 43 are, for example, silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), and trisilicon tetroxide (Si 3 N 4 ). And an inorganic material such as silicon nitride (SiNx (x is a positive number)), silicon carbonitride (SiCN), or the like. The sealing organic film 42 is made of, for example, an organic material such as acrylic resin, polyurea resin, parylene resin, polyimide resin, or polyamide resin.
上記構成の有機ＥＬ表示装置５０ａでは、各サブ画素Ｐにおいて、まず、対応する発光制御線１４ｅが選択されて非活性状態とされると、有機ＥＬ素子３５が非発光状態となる。その非発光状態で、（第１初期化ＴＦＴ９ａ及び第２初期化ＴＦＴ９ｇに電気的に接続された）対応するゲート線１４ｇが選択され、そのゲート線１４ｇを介してゲート信号が第１初期化ＴＦＴ９ａに入力されることにより、第１初期化ＴＦＴ９ａ及び第２初期化ＴＦＴ９ｇがオン状態となり、対応する初期化電源線１６ｉの電圧がキャパシタ９ｈに印加されると共に、駆動ＴＦＴ９ｄがオン状態となる。これにより、キャパシタ９ｈの電荷が放電されて、駆動ＴＦＴ９ｄの制御端子（第１ゲート電極）１４ａにかかる電圧が初期化される。次に、（閾値電圧補償ＴＦＴ９ｂ及び書込制御ＴＦＴ９ｃに電気的に接続された）対応するゲート線１４ｇが選択されて活性状態とされることにより、閾値電圧補償ＴＦＴ９ｂ及び書込制御ＴＦＴ９ｃがオン状態となり、対応するソース線１９ｆを介して伝達されるソース信号に対応する所定の電圧がダイオード接続状態の駆動ＴＦＴ９ｄを介してキャパシタ９ｈに書き込まれると共に、対応する初期化電源線１６ｉを介して初期化信号が有機ＥＬ素子３５の第１電極３１に印加されて第１電極３１に蓄積した電荷がリセットされる。その後、対応する発光制御線１４ｅが選択されて、電源供給ＴＦＴ９ｅ及び発光制御ＴＦＴ９ｆがオン状態となり、駆動ＴＦＴ９ｄの制御端子（ゲート電極）１６ａにかかる電圧に応じた駆動電流が対応する電源線１９ｇから有機ＥＬ素子３５に供給される。このようにして、有機ＥＬ表示装置５０ａでは、各サブ画素Ｐにおいて、有機ＥＬ素子３５が駆動電流に応じた輝度で発光して、画像表示が行われる。
In the organic EL display device 50a having the above configuration, when the corresponding light emission control line 14e is first selected in each sub-pixel P and put into an inactive state, the organic EL element 35 is put into a non-light emitting state. In the non-light emitting state, the corresponding gate line 14g (electrically connected to the first initializing TFT 9a and the second initializing TFT 9g) is selected, and the gate signal is transmitted via the gate line 14g to the first initializing TFT 9a. Is input to the first initialization TFT 9a and the second initialization TFT 9g, the corresponding initialization power supply line 16i voltage is applied to the capacitor 9h, and the drive TFT 9d is turned on. As a result, the charge of the capacitor 9h is discharged, and the voltage applied to the control terminal (first gate electrode) 14a of the drive TFT 9d is initialized. Next, the corresponding gate line 14g (electrically connected to the threshold voltage compensation TFT 9b and the write control TFT 9c) is selected and activated to turn on the threshold voltage compensation TFT 9b and the write control TFT 9c. Then, a predetermined voltage corresponding to the source signal transmitted via the corresponding source line 19f is written in the capacitor 9h via the driving TFT 9d in the diode connection state, and initialized via the corresponding initialization power supply line 16i. The signal is applied to the first electrode 31 of the organic EL element 35, and the charge accumulated in the first electrode 31 is reset. After that, the corresponding light emission control line 14e is selected, the power supply TFT 9e and the light emission control TFT 9f are turned on, and the drive current corresponding to the voltage applied to the control terminal (gate electrode) 16a of the drive TFT 9d is supplied from the corresponding power line 19g. It is supplied to the organic EL element 35. In this way, in the organic EL display device 50a, in each sub-pixel P, the organic EL element 35 emits light with the brightness corresponding to the drive current, and image display is performed.
次に、本実施形態の有機ＥＬ表示装置５０ａの製造方法について説明する。なお、本実施形態の有機ＥＬ表示装置５０ａの製造方法は、開口部形成工程、コンタクトホール形成工程及びソース金属層形成工程を含むＴＦＴ層形成工程と、有機ＥＬ素子層形成工程と、封止膜形成工程とを備える。ここで、図８は、有機ＥＬ表示装置５０ａを製造する際に樹脂基板層１０上に形成する薄膜の積層形態を模式的に示す断面図である。また、図９及び図１０は、有機ＥＬ表示装置５０ａの製造方法の開口部形成工程におけるレジストパターンＲａを形成する工程を示す断面図であり、図５及び図６に相当する図である。また、図１１及び図１２は、有機ＥＬ表示装置５０ａの製造方法の開口部形成工程における第２開口部Ｍｂ及び第３開口部Ｍｃを形成する工程を示す断面図であり、図５及び図６に相当する図である。また、図１３及び図１４は、有機ＥＬ表示装置５０ａの製造方法のコンタクトホール形成工程における有機絶縁膜を塗布する工程を示す断面図であり、図５及び図６に相当する図である。また、図１５及び図１６は、有機ＥＬ表示装置５０ａの製造方法のコンタクトホール形成工程における有機絶縁膜をパターニングする工程を示す断面図であり、図５及び図６に相当する図である。また、図１７及び図１８は、有機ＥＬ表示装置５０ａの製造方法のソース金属層形成工程を示す断面図であり、図５及び図６に相当する図である。
Next, a method of manufacturing the organic EL display device 50a of this embodiment will be described. The method for manufacturing the organic EL display device 50a according to the present embodiment includes a TFT layer forming step including an opening forming step, a contact hole forming step, and a source metal layer forming step, an organic EL element layer forming step, and a sealing film. And a forming step. Here, FIG. 8 is a cross-sectional view schematically showing a laminated form of thin films formed on the resin substrate layer 10 when the organic EL display device 50a is manufactured. 9 and 10 are cross-sectional views showing a step of forming the resist pattern Ra in the opening forming step of the method for manufacturing the organic EL display device 50a, which corresponds to FIGS. 5 and 6. 11 and 12 are cross-sectional views showing a step of forming the second opening Mb and the third opening Mc in the opening forming step of the method for manufacturing the organic EL display device 50a, and FIGS. It is a figure equivalent to. 13 and 14 are cross-sectional views showing a step of applying an organic insulating film in the contact hole forming step of the manufacturing method of the organic EL display device 50a, and are views corresponding to FIGS. 5 and 6. 15 and 16 are cross-sectional views showing a step of patterning the organic insulating film in the contact hole forming step of the manufacturing method of the organic EL display device 50a, and are views corresponding to FIGS. 5 and 6. 17 and 18 are cross-sectional views showing the source metal layer forming step of the method for manufacturing the organic EL display device 50a, which corresponds to FIGS. 5 and 6.
＜ＴＦＴ層形成工程＞
まず、例えば、ガラス基板上に形成した樹脂基板層１０上に、例えば、プラズマＣＶＤ法により、酸化シリコン膜等の無機絶縁膜（厚さ１０００ｎｍ程度）を成膜することにより、ベースコート膜１１を形成する。 <TFT layer forming step>
First, for example, thebase coat film 11 is formed by forming an inorganic insulating film (thickness of about 1000 nm) such as a silicon oxide film on the resin substrate layer 10 formed on the glass substrate by, for example, a plasma CVD method. To do.
まず、例えば、ガラス基板上に形成した樹脂基板層１０上に、例えば、プラズマＣＶＤ法により、酸化シリコン膜等の無機絶縁膜（厚さ１０００ｎｍ程度）を成膜することにより、ベースコート膜１１を形成する。 <TFT layer forming step>
First, for example, the
続いて、ベースコート膜１１が形成された基板全体に、プラズマＣＶＤ法により、例えば、アモルファスシリコン膜（厚さ５０ｎｍ程度）を成膜し、そのアモルファスシリコン膜をレーザーアニール等により結晶化してポリシリコン膜の半導体膜１２（図８参照）を形成した後に、その半導体膜１２をパターニングして、第１半導体層（１２ａ）等を形成する（半導体層形成工程）。
Subsequently, for example, an amorphous silicon film (with a thickness of about 50 nm) is formed on the entire substrate on which the base coat film 11 is formed by a plasma CVD method, and the amorphous silicon film is crystallized by laser annealing or the like to form a polysilicon film. After forming the semiconductor film 12 (see FIG. 8), the semiconductor film 12 is patterned to form the first semiconductor layer (12a) and the like (semiconductor layer forming step).
その後、第１半導体層（１２ａ）等が形成された基板全体に、例えば、プラズマＣＶＤ法により、酸化シリコン膜等の無機絶縁膜（１００ｎｍ程度）を成膜して、第１半導体層１２ａ等を覆うようにゲート絶縁膜１３を形成する（ゲート絶縁膜形成工程）。
After that, an inorganic insulating film (about 100 nm) such as a silicon oxide film is formed on the entire substrate on which the first semiconductor layer (12a) and the like are formed by, for example, a plasma CVD method to form the first semiconductor layer 12a and the like. The gate insulating film 13 is formed so as to cover (gate insulating film forming step).
さらに、ゲート絶縁膜１３が形成された基板全体に、例えば、スパッタリング法により、アルミニウム膜（厚さ３５０ｎｍ程度）及び窒化モリブデン膜（厚さ５０ｎｍ程度）等を順に成膜して、ゲート金属膜１４（図８参照）を成膜した後に、ゲート金属膜１４をパターニングして、第１ゲート電極１４ａ等のゲート金属層を形成する（ゲート金属層形成工程）。
Further, an aluminum film (having a thickness of about 350 nm), a molybdenum nitride film (having a thickness of about 50 nm), and the like are sequentially formed on the entire substrate on which the gate insulating film 13 is formed by, for example, a sputtering method to form the gate metal film 14. (See FIG. 8) After the film is formed, the gate metal film 14 is patterned to form a gate metal layer such as the first gate electrode 14a (gate metal layer forming step).
続いて、第１ゲート電極１４ａ等のゲート金属層をマスクとして、不純物イオンをドーピングすることにより、真性領域１２ａｃ及び一対の導体領域を有する第１半導体層１２ａ等を形成する（ドーピング工程）。
Subsequently, impurity ions are doped using the gate metal layer such as the first gate electrode 14a as a mask to form the first semiconductor layer 12a having the intrinsic region 12ac and the pair of conductor regions (doping step).
その後、第１半導体層１２ａ等が形成された基板全体に、例えば、プラズマＣＶＤ法により、酸化シリコン膜等の無機絶縁膜（厚さ１００ｎｍ程度）を成膜することにより、第１層間絶縁膜１５を形成する（第１層間絶縁膜形成工程）。
After that, an inorganic insulating film (having a thickness of about 100 nm) such as a silicon oxide film is formed on the entire substrate on which the first semiconductor layer 12a and the like are formed by, for example, a plasma CVD method, and thus the first interlayer insulating film 15 is formed. Are formed (first interlayer insulating film forming step).
続いて、第１層間絶縁膜１５が形成された基板全体に、例えば、スパッタリング法により、アルミニウム膜（厚さ３５０ｎｍ程度）及び窒化モリブデン膜（厚さ５０ｎｍ程度）等を順に成膜して、中間金属膜１６（図８参照）を成膜した後に、中間金属膜１６をパターニングして、第１開口部Ｍａを有する容量電極１６ｃ等の中間金属層を形成する（中間金属層形成工程）。
Then, an aluminum film (about 350 nm in thickness), a molybdenum nitride film (about 50 nm in thickness), etc. are sequentially formed on the entire substrate on which the first interlayer insulating film 15 is formed, for example, by a sputtering method, and an intermediate film is formed. After forming the metal film 16 (see FIG. 8), the intermediate metal film 16 is patterned to form an intermediate metal layer such as the capacitor electrode 16c having the first opening Ma (intermediate metal layer forming step).
さらに、容量電極１６ｃ等の中間金属層が形成された基板全体に、例えば、プラズマＣＶＤ法により、酸化シリコン膜等の無機絶縁膜（厚さ５００ｎｍ程度）を成膜することにより、第２層間絶縁膜１７を形成する（第２層間絶縁膜形成工程）。
Further, an inorganic insulating film (thickness of about 500 nm) such as a silicon oxide film is formed on the entire substrate on which the intermediate metal layer such as the capacitance electrode 16c is formed, for example, by the plasma CVD method, so that the second interlayer insulating film is formed. The film 17 is formed (second interlayer insulating film forming step).
その後、第２層間絶縁膜１７上にポジ型のレジスト材料Ｒ（図８参照）を塗布し、レジスト材料Ｒを露光、現像及び焼成することにより、図９及び図１０に示すように、第２開口部Ｍｂ、第３開口部Ｍｃ及び第３コンタクトホールＨｃに対応して、貫通孔Ｈｒが設けられたレジストパターンＲａを形成する。そして、レジストパターンＲａから露出する第２層間絶縁膜１７及び第１層間絶縁膜１５をエッチングすることにより、図１１に示すように、第１層間絶縁膜１５及び第２層間絶縁膜１７に、平面視で第１開口部Ｍａの周縁の内側に配置するように貫通した第２開口部Ｍｂを形成する。このとき、レジストパターンＲａから露出する第２層間絶縁膜１７、第１層間絶縁膜１５及びゲート絶縁膜１３をエッチングすることにより、図１２に示すように、ゲート絶縁膜１３、第１層間絶縁膜１５及び第２層間絶縁膜１７にゲート絶縁膜１３、第１層間絶縁膜１５及び第２層間絶縁膜１７を貫通して、第２導体領域１２ｂｂに到達するように第３開口部Ｍｃを形成する（開口部形成工程）。さらに、このとき、レジストパターンＲａから露出する第２層間絶縁膜１７、第１層間絶縁膜１５及びゲート絶縁膜１３をエッチングすることにより、図１１に示すように、ゲート絶縁膜１３、第１層間絶縁膜１５及び第２層間絶縁膜１７にゲート絶縁膜１３、第１層間絶縁膜１５及び第２層間絶縁膜１７を貫通して、第２導体領域１２ａｂに到達するように第３コンタクトホールＨｃの下部が形成される。
After that, a positive resist material R (see FIG. 8) is applied on the second interlayer insulating film 17, and the resist material R is exposed, developed, and baked, so that a second resist material R is formed as shown in FIGS. A resist pattern Ra having a through hole Hr is formed corresponding to the opening Mb, the third opening Mc, and the third contact hole Hc. Then, by etching the second interlayer insulating film 17 and the first interlayer insulating film 15 exposed from the resist pattern Ra, as shown in FIG. 11, the first interlayer insulating film 15 and the second interlayer insulating film 17 have a flat surface. The penetrating second opening Mb is formed so as to be arranged inside the peripheral edge of the first opening Ma as viewed. At this time, by etching the second interlayer insulating film 17, the first interlayer insulating film 15 and the gate insulating film 13 exposed from the resist pattern Ra, as shown in FIG. 12, the gate insulating film 13 and the first interlayer insulating film 13 are formed. A third opening Mc is formed through the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17, and reaches the second conductor region 12bb. (Opening formation step). Further, at this time, by etching the second interlayer insulating film 17, the first interlayer insulating film 15, and the gate insulating film 13 exposed from the resist pattern Ra, as shown in FIG. 11, the gate insulating film 13 and the first interlayer insulating film 13 are etched. The third contact hole Hc is formed in the insulating film 15 and the second interlayer insulating film 17 so as to penetrate the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17 and reach the second conductor region 12ab. The lower part is formed.
続いて、第２開口部Ｍｂ及び第３開口部Ｍｃが形成された第２層間絶縁膜１７が形成された基板全体に、例えば、スピンコート法やスリットコート法により、図１３及び図１５に示すように、感光性を有する絶縁材料（例えば、ＳＯＧ（spin on glass）材料等）により形成された有機絶縁膜１８を塗布した後に、有機絶縁膜１８をパターニングして、図１５及び図１６に示すように、有機絶縁膜１８に平面視で第２開口部Ｍｂの周縁の内側に配置するように貫通した第１コンタクトホールＨａ、平面視で第３開口部Ｍｃと重なるように貫通した第２コンタクトホールＨｂ、及び平面視で第３コンタクトホールＨｃの下部と重なるように貫通した第３コンタクトホールＨｃの上部を形成する（コンタクトホール形成工程）。ここで、コンタクトホール形成工程では、図１５及び図１６に示すように、第２開口部Ｍｂ及び第３開口部Ｍｃの側面を覆うように、有機絶縁膜１８をパターニングして、樹脂基板層１０側に向けて側面が順テーパ状に傾斜するように第１コンタクトホールＨａ及び第２コンタクトホールＨｂを形成する。
Subsequently, the whole substrate on which the second interlayer insulating film 17 having the second opening Mb and the third opening Mc is formed is shown in FIGS. 13 and 15 by, for example, a spin coating method or a slit coating method. As shown in FIGS. 15 and 16, after applying the organic insulating film 18 formed of a photosensitive insulating material (for example, SOG (spin-on-glass) material), the organic insulating film 18 is patterned. Thus, the first contact hole Ha penetrating the organic insulating film 18 so as to be disposed inside the peripheral edge of the second opening Mb in a plan view, and the second contact penetrating so as to overlap the third opening Mc in a plan view. The hole Hb and the upper part of the third contact hole Hc penetrating so as to overlap the lower part of the third contact hole Hc in plan view are formed (contact hole forming step). Here, in the contact hole forming step, as shown in FIGS. 15 and 16, the organic insulating film 18 is patterned so as to cover the side surfaces of the second opening Mb and the third opening Mc, and the resin substrate layer 10 is then formed. The first contact hole Ha and the second contact hole Hb are formed so that the side surfaces incline toward the side in a forward tapered shape.
その後、第１コンタクトホールＨａ等が形成された基板全体に、例えば、スパッタリング法により、チタン膜（厚さ３０ｎｍ程度）、アルミニウム膜（厚さ３００ｎｍ程度）及びチタン膜（厚さ５０ｎｍ程度）等を順に成膜してソース金属膜１９を形成した後に、ソース金属膜１９をパターニングして、第１接続配線１９ｅ、電源線１９ｇ等のソース金属層を形成する（ソース金属層形成工程）。
After that, a titanium film (thickness of about 30 nm), an aluminum film (thickness of about 300 nm), a titanium film (thickness of about 50 nm), etc. are formed on the entire substrate in which the first contact holes Ha and the like are formed by, for example, a sputtering method. After sequentially forming the source metal film 19 to form the source metal film 19, the source metal film 19 is patterned to form a source metal layer such as the first connection wiring 19e and the power supply line 19g (source metal layer forming step).
最後に、第１接続配線１８ｅ等のソース金属層が形成された基板全体に、例えば、スピンコート法やスリットコート法により、ポリイミド系の感光性樹脂膜（厚さ２μｍ程度）を塗布した後に、その塗布膜に対して、プリベーク、露光、現像及びポストベークを行うことにより、平坦化膜２０を形成する。
Finally, after applying a polyimide-based photosensitive resin film (thickness of about 2 μm) to the entire substrate on which the source metal layer such as the first connection wiring 18e is formed, for example, by a spin coating method or a slit coating method, The flattening film 20 is formed by performing pre-baking, exposure, development, and post-baking on the coating film.
以上のようにして、ＴＦＴ層３０ａを形成することができる。
The TFT layer 30a can be formed as described above.
＜有機ＥＬ素子層形成工程＞
上記ＴＦＴ層形成工程で形成されたＴＦＴ層３０ａの平坦化膜２０上に、周知の方法を用いて、第１電極３１、エッジカバー３２、有機ＥＬ層３３（正孔注入層１、正孔輸送層２、発光層３、電子輸送層４、電子注入層５）及び第２電極３４を形成して、有機ＥＬ素子層４０を形成する。 <Organic EL element layer forming step>
The first electrode 31, theedge cover 32, and the organic EL layer 33 (hole injection layer 1, hole transport) are used on the flattening film 20 of the TFT layer 30a formed in the TFT layer forming step by a well-known method. The layer 2, the light emitting layer 3, the electron transport layer 4, the electron injection layer 5) and the second electrode 34 are formed to form the organic EL element layer 40.
上記ＴＦＴ層形成工程で形成されたＴＦＴ層３０ａの平坦化膜２０上に、周知の方法を用いて、第１電極３１、エッジカバー３２、有機ＥＬ層３３（正孔注入層１、正孔輸送層２、発光層３、電子輸送層４、電子注入層５）及び第２電極３４を形成して、有機ＥＬ素子層４０を形成する。 <Organic EL element layer forming step>
The first electrode 31, the
＜封止膜形成工程＞
上記有機ＥＬ素子層形成工程で形成された有機ＥＬ素子層４０上に、周知の方法を用いて、封止膜４５（第１封止無機絶縁膜４１、封止有機膜４２、第２封止無機絶縁膜４３）を形成する。その後、封止膜４５が形成された基板表面に保護シート（不図示）を貼付した後に、樹脂基板層１０のガラス基板側からレーザー光を照射することにより、樹脂基板層１０の下面からガラス基板を剥離させ、さらに、ガラス基板を剥離させた樹脂基板層１０の下面に保護シート（不図示）を貼付する。 <Sealing film forming step>
A sealing film 45 (first sealing inorganic insulatingfilm 41, sealing organic film 42, second sealing) is formed on the organic EL element layer 40 formed in the organic EL element layer forming step by a known method. An inorganic insulating film 43) is formed. After that, a protective sheet (not shown) is attached to the surface of the substrate on which the sealing film 45 is formed, and then the glass substrate is irradiated from the glass substrate side of the resin substrate layer 10 to irradiate the glass substrate from the lower surface of the resin substrate layer 10. Then, a protective sheet (not shown) is attached to the lower surface of the resin substrate layer 10 from which the glass substrate has been peeled off.
上記有機ＥＬ素子層形成工程で形成された有機ＥＬ素子層４０上に、周知の方法を用いて、封止膜４５（第１封止無機絶縁膜４１、封止有機膜４２、第２封止無機絶縁膜４３）を形成する。その後、封止膜４５が形成された基板表面に保護シート（不図示）を貼付した後に、樹脂基板層１０のガラス基板側からレーザー光を照射することにより、樹脂基板層１０の下面からガラス基板を剥離させ、さらに、ガラス基板を剥離させた樹脂基板層１０の下面に保護シート（不図示）を貼付する。 <Sealing film forming step>
A sealing film 45 (first sealing inorganic insulating
以上のようにして、本実施形態の有機ＥＬ表示装置５０ａを製造することができる。
The organic EL display device 50a of this embodiment can be manufactured as described above.
以上説明したように、本実施形態の有機ＥＬ表示装置５０ａ及びその製造方法によれば、ＴＦＴ層形成工程の開口部形成工程において、第１層間絶縁膜１５及び第２層間絶縁膜１７に第１層間絶縁膜１５及び第２層間絶縁膜１７を貫通するように第２開口部Ｍｂが形成されると共に、ゲート絶縁膜１３、第１層間絶縁膜１５及び第２層間絶縁膜１７にゲート絶縁膜１３、第１層間絶縁膜１５及び第２層間絶縁膜１７を貫通するように第３開口部Ｍｃが形成される。ここで、ゲート絶縁膜１３及び第１層間絶縁膜１５の表面に異物Ｘが仮に存在し、第１層間絶縁膜形成工程及び第２層間絶縁膜形成工程で第１層間絶縁膜１５第２層間絶縁膜１７を形成する際に第１層間絶縁膜１５及び第２層間絶縁膜１７に空洞の鬆Ｙが形成されたとしても、後のコンタクトホール形成工程において、第２開口部Ｍｂ及び第３開口部Ｍｃの側面を覆うように、有機絶縁膜１８をパターニングするので、第１層間絶縁膜１５及び第２層間絶縁膜１７に形成された鬆Ｙの内部に有機絶縁膜１８が充填される。これにより、ソース金属層形成工程で形成される第１接続配線１９ｅと中間金属層形成工程で形成された容量電極１６ｃとの短絡、及びソース金属層形成工程で形成される電源線１９ｇとゲート金属層形成工程で形成された発光制御線１４ｅとの短絡を抑制することができるので、第１層間絶縁膜１５及び第２層間絶縁膜１７に形成された鬆Ｙに起因する短絡欠陥の発生を抑制することができる。
As described above, according to the organic EL display device 50a of the present embodiment and the manufacturing method thereof, in the opening forming step of the TFT layer forming step, the first interlayer insulating film 15 and the second interlayer insulating film 17 are first. The second opening Mb is formed so as to penetrate the interlayer insulating film 15 and the second interlayer insulating film 17, and the gate insulating film 13 is formed on the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17. The third opening Mc is formed so as to penetrate the first interlayer insulating film 15 and the second interlayer insulating film 17. Here, the foreign material X is temporarily present on the surfaces of the gate insulating film 13 and the first interlayer insulating film 15, and the first interlayer insulating film 15 and the second interlayer insulating film are formed in the first interlayer insulating film forming step and the second interlayer insulating film forming step. Even if a void Y is formed in the first interlayer insulating film 15 and the second interlayer insulating film 17 when the film 17 is formed, the second opening Mb and the third opening Mb are formed in the subsequent contact hole forming step. Since the organic insulating film 18 is patterned so as to cover the side surface of Mc, the organic insulating film 18 is filled in the void Y formed in the first interlayer insulating film 15 and the second interlayer insulating film 17. This causes a short circuit between the first connection wiring 19e formed in the source metal layer forming step and the capacitor electrode 16c formed in the intermediate metal layer forming step, and a power supply line 19g and a gate metal formed in the source metal layer forming step. Since a short circuit with the light emission control line 14e formed in the layer forming step can be suppressed, occurrence of a short circuit defect due to the void Y formed in the first interlayer insulating film 15 and the second interlayer insulating film 17 can be suppressed. can do.
《第２の実施形態》
図１９～図２４は、本発明に係る表示装置及びその製造方法の第２の実施形態を示している。ここで、図１９及び図２０は、本実施形態の有機ＥＬ表示装置５０ｂの断面図であり、上記第１の実施形態で説明した図５及び図６に相当する図である。なお、以下の各実施形態において、図１～図１８と同じ部分については同じ符号を付して、その詳細な説明を省略する。 <<Second Embodiment>>
19 to 24 show a second embodiment of the display device and the manufacturing method thereof according to the present invention. Here, FIG. 19 and FIG. 20 are cross-sectional views of the organicEL display device 50b of the present embodiment, and are views corresponding to FIG. 5 and FIG. 6 described in the first embodiment. In each of the following embodiments, the same parts as those in FIGS. 1 to 18 are designated by the same reference numerals, and detailed description thereof will be omitted.
図１９～図２４は、本発明に係る表示装置及びその製造方法の第２の実施形態を示している。ここで、図１９及び図２０は、本実施形態の有機ＥＬ表示装置５０ｂの断面図であり、上記第１の実施形態で説明した図５及び図６に相当する図である。なお、以下の各実施形態において、図１～図１８と同じ部分については同じ符号を付して、その詳細な説明を省略する。 <<Second Embodiment>>
19 to 24 show a second embodiment of the display device and the manufacturing method thereof according to the present invention. Here, FIG. 19 and FIG. 20 are cross-sectional views of the organic
上記第１の実施形態では、第１層間絶縁膜１５及び第２層間絶縁膜１７の開口部の側面が略直立した有機ＥＬ表示装置５０ａを例示したが、本実施形態では、第１層間絶縁膜１５及び第２層間絶縁膜１７の開口部の側面が逆テーパ状に傾斜した有機ＥＬ表示装置５０ｂを例示する。
In the first embodiment described above, the organic EL display device 50a in which the side surfaces of the openings of the first interlayer insulating film 15 and the second interlayer insulating film 17 are substantially upright is exemplified, but in the present embodiment, the first interlayer insulating film is formed. 15 illustrates an organic EL display device 50b in which the side surfaces of the openings of 15 and the second interlayer insulating film 17 are inclined in a reverse taper shape.
有機ＥＬ表示装置５０ｂは、上記第１の実施形態の有機ＥＬ表示装置５０ａと同様に、表示領域Ｄと、表示領域Ｄの周囲に設けられた額縁領域Ｆとを備えている。
The organic EL display device 50b includes a display area D and a frame area F provided around the display area D, similarly to the organic EL display device 50a of the first embodiment.
有機ＥＬ表示装置５０ｂは、図１９及び図２０に示すように、樹脂基板層１０と、樹脂基板層１０上に設けられたＴＦＴ層３０ｂと、ＴＦＴ層３０ｂ上に設けられた有機ＥＬ素子層４０、有機ＥＬ素子層４０上に設けられた封止膜４５とを備えている。
As shown in FIGS. 19 and 20, the organic EL display device 50b includes a resin substrate layer 10, a TFT layer 30b provided on the resin substrate layer 10, and an organic EL element layer 40 provided on the TFT layer 30b. , And a sealing film 45 provided on the organic EL element layer 40.
ＴＦＴ層３０ｂは、上記第１の実施形態の有機ＥＬ表示装置５０ａのＴＦＴ層３０ａと同様に、樹脂基板層１０上に設けられたベースコート膜１１と、ベースコート膜１１上にサブ画素Ｐ毎に設けられた第１初期化ＴＦＴ９ａ、閾値電圧補償ＴＦＴ９ｂ、書込制御ＴＦＴ９ｃ、駆動ＴＦＴ９ｄ、電源供給ＴＦＴ９ｅ、発光制御ＴＦＴ９ｆ、第２初期化ＴＦＴ９ｇ及びキャパシタ９ｈと、各ＴＦＴ９ａ～９ｇ及びキャパシタ９ｈ上に設けられた平坦化膜２０とを備えている。
Similar to the TFT layer 30a of the organic EL display device 50a of the first embodiment, the TFT layer 30b is provided on the base coat film 11 provided on the resin substrate layer 10 and on the base coat film 11 for each sub-pixel P. The first initialization TFT 9a, the threshold voltage compensation TFT 9b, the write control TFT 9c, the drive TFT 9d, the power supply TFT 9e, the light emission control TFT 9f, the second initialization TFT 9g and the capacitor 9h, and the respective TFTs 9a to 9g and the capacitor 9h are provided. And a flattening film 20.
ＴＦＴ層３０ｂでは、図１９及び図２０に示すように、第１層間絶縁膜１５及び第２層間絶縁膜１７に形成された第２開口部Ｍｂ及び第３開口部Ｍｃの側面が樹脂基板層１０側に向けて逆テーパ状に傾斜し、平面視で第３コンタクトホールＨｃに重なるように、ゲート絶縁膜１３、第１層間絶縁膜１５及び第２層間絶縁膜１７に第４開口部Ｍｄが形成され、第４開口部Ｍｄの側面が樹脂基板層１０側に向けて逆テーパ状に傾斜している。なお、ＴＦＴ層３０ｂにおいて、上述した第２開口部Ｍｂ、第３開口部Ｍｃ及び第４開口部Ｍｄの構成以外は、上記第１の実施形態の有機ＥＬ表示装置５０ａのＴＦＴ層３０ａの構成と実質的に同じになっている。
In the TFT layer 30b, as shown in FIGS. 19 and 20, the side surfaces of the second opening Mb and the third opening Mc formed in the first interlayer insulating film 15 and the second interlayer insulating film 17 have the resin substrate layer 10 on the side surfaces. A fourth opening Md is formed in the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 so as to incline in a reverse taper shape toward the side and overlap the third contact hole Hc in a plan view. Thus, the side surface of the fourth opening Md is inclined in the reverse taper shape toward the resin substrate layer 10 side. The TFT layer 30b has the same structure as the TFT layer 30a of the organic EL display device 50a according to the first embodiment except for the structures of the second opening Mb, the third opening Mc, and the fourth opening Md described above. It is virtually the same.
上記構成の有機ＥＬ表示装置５０ｂは、上記第１の実施形態の有機ＥＬ表示装置５０ａと同様に、可撓性を有し、各サブ画素Ｐにおいて、第１初期化ＴＦＴ９ａ、閾値電圧補償ＴＦＴ９ｂ、書込制御ＴＦＴ９ｃ、駆動ＴＦＴ９ｄ、電源供給ＴＦＴ９ｅ、発光制御ＴＦＴ９ｆ及び第２初期化ＴＦＴ９ｇを介して、有機ＥＬ層３３の発光層３を適宜発光させることにより、画像表示を行うように構成されている。
The organic EL display device 50b having the above configuration has flexibility as in the organic EL display device 50a of the first embodiment, and in each sub-pixel P, the first initialization TFT 9a, the threshold voltage compensation TFT 9b, An image is displayed by appropriately causing the light emitting layer 3 of the organic EL layer 33 to emit light via the write control TFT 9c, the drive TFT 9d, the power supply TFT 9e, the light emission control TFT 9f, and the second initialization TFT 9g. ..
本実施形態の有機ＥＬ表示装置５０ｂは、上記第１の実施形態の有機ＥＬ表示装置５０ａの製造方法における開口部形成工程を変更することにより、製造することができる。ここで、図２１及び図２２は、有機ＥＬ表示装置５０ｂの製造方法の開口部形成工程におけるレジストパターンを形成する工程を示す断面図であり、図１９及び図２０に相当する図である。また、図２３及び図２４は、有機ＥＬ表示装置５０ｂの製造方法の開口部形成工程における第２開口部Ｍｂ、第４開口部Ｍｄ及び第３開口部Ｍｃを形成する工程を示す断面図であり、図１９及び図２０に相当する図である。
The organic EL display device 50b of the present embodiment can be manufactured by changing the opening forming step in the method of manufacturing the organic EL display device 50a of the first embodiment. Here, FIGS. 21 and 22 are cross-sectional views showing a step of forming a resist pattern in the opening forming step of the method for manufacturing the organic EL display device 50b, and are views corresponding to FIGS. 19 and 20. 23 and 24 are cross-sectional views showing a step of forming the second opening Mb, the fourth opening Md, and the third opening Mc in the opening forming step of the method for manufacturing the organic EL display device 50b. FIG. 21 is a view corresponding to FIGS. 19 and 20.
具体的には、上記第１の実施形態の有機ＥＬ表示装置５０ａの製造方法の第２層間絶縁膜形成工程までを行った後に、第２層間絶縁膜１７上にネガ型のレジスト材料Ｒを塗布し、レジスト材料Ｒを露光、現像及び焼成することにより、図２１及び図２２に示すように、第２開口部Ｍｂ、第３開口部Ｍｃ及び第４開口部Ｍｄに対応して、貫通孔Ｈｒが設けられたレジストパターンＲｂを形成する。ここで、レジストパターンＲｂに形成された貫通孔Ｈｒの側面は、図２１及び図２２に示すように、樹脂基板層１０側に向けて側面が逆テーパ状に傾斜している。
Specifically, after the steps up to the second interlayer insulating film forming step of the method for manufacturing the organic EL display device 50a of the first embodiment are performed, the negative resist material R is applied on the second interlayer insulating film 17. Then, by exposing, developing and baking the resist material R, as shown in FIGS. 21 and 22, through holes Hr corresponding to the second opening Mb, the third opening Mc and the fourth opening Md are formed. A resist pattern Rb provided with is formed. Here, as shown in FIGS. 21 and 22, the side surface of the through hole Hr formed in the resist pattern Rb is inclined in an inverse taper shape toward the resin substrate layer 10 side.
その後、レジストパターンＲｂから露出する第２層間絶縁膜１７及び第１層間絶縁膜１５をエッチングすることにより、図２３に示すように、第１層間絶縁膜１５及び第２層間絶縁膜１７に、平面視で第１開口部Ｍａの周縁の内側に配置するように貫通した第２開口部Ｍｂを形成する。このとき、レジストパターンＲｂから露出する第２層間絶縁膜１７、第１層間絶縁膜１５及びゲート絶縁膜１３をエッチングすることにより、図２４に示すように、ゲート絶縁膜１３、第１層間絶縁膜１５及び第２層間絶縁膜１７にゲート絶縁膜１３、第１層間絶縁膜１５及び第２層間絶縁膜１７を貫通して、第２導体領域１２ｂｂに到達するように第３開口部Ｍｃを形成する（開口部形成工程）。さらに、このとき、レジストパターンＲｂから露出する第２層間絶縁膜１７、第１層間絶縁膜１５及びゲート絶縁膜１３をエッチングすることにより、図２３に示すように、ゲート絶縁膜１３、第１層間絶縁膜１５及び第２層間絶縁膜１７にゲート絶縁膜１３、第１層間絶縁膜１５及び第２層間絶縁膜１７を貫通して、第２導体領域１２ａｂに到達するように第４開口部Ｍｄが形成される。なお、レジストパターンＲｂに形成された貫通孔Ｈｒの側面が樹脂基板層１０側に向けて側面が逆テーパ状に傾斜されているので、レジストパターンＲｂをマスクとしてエッチングにより形成された第２開口部Ｍｂ、第３開口部Ｍｃ及び第４開口部Ｍｄの側面は、図２３及び図２４に示すように、樹脂基板層１０側に向けて側面が逆テーパ状に傾斜される。
Then, by etching the second interlayer insulating film 17 and the first interlayer insulating film 15 exposed from the resist pattern Rb, the first interlayer insulating film 15 and the second interlayer insulating film 17 are planarized as shown in FIG. The penetrating second opening Mb is formed so as to be arranged inside the peripheral edge of the first opening Ma as viewed. At this time, by etching the second interlayer insulating film 17, the first interlayer insulating film 15 and the gate insulating film 13 exposed from the resist pattern Rb, as shown in FIG. 24, the gate insulating film 13 and the first interlayer insulating film 13 are formed. A third opening Mc is formed through the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17, and reaches the second conductor region 12bb. (Opening formation step). Further, at this time, by etching the second interlayer insulating film 17, the first interlayer insulating film 15 and the gate insulating film 13 exposed from the resist pattern Rb, the gate insulating film 13 and the first interlayer insulating film 13 are etched as shown in FIG. The fourth opening Md is formed in the insulating film 15 and the second interlayer insulating film 17 so as to penetrate the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17 and reach the second conductor region 12ab. It is formed. Since the side surface of the through hole Hr formed in the resist pattern Rb is inclined in the reverse taper shape toward the resin substrate layer 10 side, the second opening formed by etching using the resist pattern Rb as a mask. As shown in FIGS. 23 and 24, the side surfaces of Mb, the third opening Mc, and the fourth opening Md are inclined in a reverse taper shape toward the resin substrate layer 10 side.
引き続いて、上記第１の実施形態の有機ＥＬ表示装置５０ａの製造方法のコンタクトホール形成工程、ソース金属層形成工程を行った後に、平坦化膜２０を形成することにより、ＴＦＴ層３０ｂを形成することができ、さらに、上記第１の実施形態の有機ＥＬ表示装置５０ａの製造方法の有機ＥＬ素子層形成工程及び封止膜形成工程を行うことにより、本実施形態の有機ＥＬ表示装置５０ｂを製造することができる。
Subsequently, after performing the contact hole forming step and the source metal layer forming step of the manufacturing method of the organic EL display device 50a of the first embodiment, the flattening film 20 is formed to form the TFT layer 30b. Further, the organic EL display device 50b of the present embodiment is manufactured by performing the organic EL element layer forming step and the sealing film forming step of the manufacturing method of the organic EL display device 50a of the first embodiment. can do.
以上説明したように、本実施形態の有機ＥＬ表示装置５０ｂ及びその製造方法によれば、ＴＦＴ層形成工程の開口部形成工程において、第１層間絶縁膜１５及び第２層間絶縁膜１７に第１層間絶縁膜１５及び第２層間絶縁膜１７を貫通するように第２開口部Ｍｂが形成されると共に、ゲート絶縁膜１３、第１層間絶縁膜１５及び第２層間絶縁膜１７にゲート絶縁膜１３、第１層間絶縁膜１５及び第２層間絶縁膜１７を貫通するように第３開口部Ｍｃが形成される。ここで、ゲート絶縁膜１３及び第１層間絶縁膜１５の表面に異物Ｘが仮に存在し、第１層間絶縁膜形成工程及び第２層間絶縁膜形成工程で第１層間絶縁膜１５第２層間絶縁膜１７を形成する際に第１層間絶縁膜１５及び第２層間絶縁膜１７に空洞の鬆Ｙが形成されたとしても、後のコンタクトホール形成工程において、第２開口部Ｍｂ及び第３開口部Ｍｃの側面を覆うように、有機絶縁膜１８をパターニングするので、第１層間絶縁膜１５及び第２層間絶縁膜１７に形成された鬆Ｙの内部に有機絶縁膜１８が充填される。これにより、ソース金属層形成工程で形成される第１接続配線１９ｅと中間金属層形成工程で形成された容量電極１６ｃとの短絡、及びソース金属層形成工程で形成される電源線１９ｇとゲート金属層形成工程で形成された発光制御線１４ｅとの短絡を抑制することができるので、第１層間絶縁膜１５及び第２層間絶縁膜１７に形成された鬆Ｙに起因する短絡欠陥の発生を抑制することができる。
As described above, according to the organic EL display device 50b and the manufacturing method thereof of the present embodiment, the first interlayer insulating film 15 and the second interlayer insulating film 17 have the first interlayer insulating film 15 and the first interlayer insulating film 17 in the opening forming step of the TFT layer forming step. The second opening Mb is formed so as to penetrate the interlayer insulating film 15 and the second interlayer insulating film 17, and the gate insulating film 13 is formed on the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17. The third opening Mc is formed so as to penetrate the first interlayer insulating film 15 and the second interlayer insulating film 17. Here, the foreign material X is temporarily present on the surfaces of the gate insulating film 13 and the first interlayer insulating film 15, and the first interlayer insulating film 15 and the second interlayer insulating film are formed in the first interlayer insulating film forming step and the second interlayer insulating film forming step. Even if a void Y is formed in the first interlayer insulating film 15 and the second interlayer insulating film 17 when the film 17 is formed, the second opening Mb and the third opening Mb are formed in the subsequent contact hole forming step. Since the organic insulating film 18 is patterned so as to cover the side surface of Mc, the organic insulating film 18 is filled in the void Y formed in the first interlayer insulating film 15 and the second interlayer insulating film 17. This causes a short circuit between the first connection wiring 19e formed in the source metal layer forming step and the capacitor electrode 16c formed in the intermediate metal layer forming step, and a power supply line 19g and a gate metal formed in the source metal layer forming step. Since a short circuit with the light emission control line 14e formed in the layer forming step can be suppressed, occurrence of a short circuit defect due to the void Y formed in the first interlayer insulating film 15 and the second interlayer insulating film 17 can be suppressed. can do.
また、本実施形態の有機ＥＬ表示装置５０ｂ及びその製造方法によれば、第２開口部Ｍｂ及び第３開口部Ｍｃの側面が樹脂基板層１０側に向けて逆テーパ状に傾斜しているので、第２開口部Ｍｂ及び第３開口部Ｍｃの側面に有機絶縁膜１８が上記第１の実施形態の有機ＥＬ表示装置５０ａよりも厚く形成される。そのため、本実施形態の有機ＥＬ表示装置５０ｂでは、第１層間絶縁膜１５及び第２層間絶縁膜１７に形成された鬆Ｙに起因する短絡欠陥の発生をいっそう抑制することができる。
Further, according to the organic EL display device 50b and the method of manufacturing the same of the present embodiment, the side surfaces of the second opening Mb and the third opening Mc are inclined in a reverse taper shape toward the resin substrate layer 10 side. The organic insulating film 18 is formed thicker on the side surfaces of the second opening Mb and the third opening Mc than the organic EL display device 50a of the first embodiment. Therefore, in the organic EL display device 50b of the present embodiment, it is possible to further suppress the occurrence of short-circuit defects due to the void Y formed in the first interlayer insulating film 15 and the second interlayer insulating film 17.
《その他の実施形態》
上記各実施形態では、正孔注入層、正孔輸送層、発光層、電子輸送層及び電子注入層の５層積層構造の有機ＥＬ層を例示したが、有機ＥＬ層は、例えば、正孔注入層兼正孔輸送層、発光層、及び電子輸送層兼電子注入層の３層積層構造であってもよい。 <<Other Embodiments>>
In each of the above-described embodiments, the organic EL layer having a five-layer laminated structure of the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer is exemplified. It may have a three-layer laminated structure of a layer/hole transport layer, a light emitting layer, and an electron transport layer/electron injection layer.
上記各実施形態では、正孔注入層、正孔輸送層、発光層、電子輸送層及び電子注入層の５層積層構造の有機ＥＬ層を例示したが、有機ＥＬ層は、例えば、正孔注入層兼正孔輸送層、発光層、及び電子輸送層兼電子注入層の３層積層構造であってもよい。 <<Other Embodiments>>
In each of the above-described embodiments, the organic EL layer having a five-layer laminated structure of the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer is exemplified. It may have a three-layer laminated structure of a layer/hole transport layer, a light emitting layer, and an electron transport layer/electron injection layer.
また、上記各実施形態では、第１電極を陽極とし、第２電極を陰極とした有機ＥＬ表示装置を例示したが、本発明は、有機ＥＬ層の積層構造を反転させ、第１電極を陰極とし、第２電極を陽極とした有機ＥＬ表示装置にも適用することができる。
Further, in each of the above-described embodiments, the organic EL display device in which the first electrode is the anode and the second electrode is the cathode has been illustrated, but the present invention reverses the laminated structure of the organic EL layer and the first electrode is the cathode. And can be applied to an organic EL display device using the second electrode as an anode.
また、上記各実施形態では、第１電極に接続されたＴＦＴの電極をドレイン電極とした有機ＥＬ表示装置を例示したが、本発明は、第１電極に接続されたＴＦＴの電極をソース電極と呼ぶ有機ＥＬ表示装置にも適用することができる。
Further, in each of the above-described embodiments, the organic EL display device in which the electrode of the TFT connected to the first electrode is used as the drain electrode is illustrated, but the present invention uses the electrode of the TFT connected to the first electrode as the source electrode. It can also be applied to a so-called organic EL display device.
また、上記各実施形態では、表示装置として有機ＥＬ表示装置を例に挙げて説明したが、本発明は、電流によって駆動される複数の発光素子を備えた表示装置に適用することができる。例えば、量子ドット含有層を用いた発光素子であるＱＬＥＤ（Quantum-dot light emitting diode）を備えた表示装置に適用することができる。
Further, in each of the above-described embodiments, an organic EL display device has been described as an example of a display device, but the present invention can be applied to a display device including a plurality of light emitting elements driven by current. For example, it can be applied to a display device including a QLED (Quantum-dot light emitting diode) which is a light emitting element using a quantum dot containing layer.
以上説明したように、本発明は、フレキシブルな表示装置について有用である。
As described above, the present invention is useful for flexible display devices.
Ｈａ 第１コンタクトホール
Ｈｂ 第２コンタクトホール
Ｈｃ 第３コンタクトホール
Ｈｒ 貫通孔
Ｍａ 第１開口部
Ｍｂ 第２開口部
Ｍｃ 第３開口部
Ｐ サブ画素
Ｒ レジスト材料
Ｒｂ レジストパターン
９ｄ 駆動ＴＦＴ（第１薄膜トランジスタ）
９ｅ 電源供給ＴＦＴ（第２薄膜トランジスタ）
９ｈ キャパシタ
１０ 樹脂基板層（ベース基板）
１２ 半導体膜
１２ａ 第１半導体層
１２ａｂ 第２導体領域
１２ｂ 第２半導体層
１２ｂａ 第１導体領域
１２ｂｂ 第２導体領域
１２ｂｃ 真性領域
１３ ゲート絶縁膜
１４ ゲート金属膜
１４ａ 第１ゲート電極（ゲート金属層）
１４ｅ 発光制御線（第２ゲート電極、ゲート金属層）
１５ 第１層間絶縁膜
１６ 中間金属膜
１６ｃ 容量電極（中間金属層）
１７ 第２層間絶縁膜
１８ 有機絶縁膜
１９ ソース金属膜
１９ｅ 第１接続配線（ソース金属層）
１９ｇ 電源線
３０ａ，３０ｂ ＴＦＴ層（薄膜トランジスタ層）
３５ 有機ＥＬ素子（有機エレクトロルミネッセンス素子、発光素子）
４０ 有機ＥＬ素子層（発光素子層）
５０ａ，５０ｂ 有機ＥＬ表示装置 Ha First contact hole Hb Second contact hole Hc Third contact hole Hr Through hole Ma First opening Mb Second opening Mc Third opening P Sub-pixel R Resist material Rb Resistpattern 9d Driving TFT (first thin film transistor)
9e Power supply TFT (second thin film transistor)
9h Capacitor 10 Resin substrate layer (base substrate)
12semiconductor film 12a first semiconductor layer 12ab second conductor region 12b second semiconductor layer 12ba first conductor region 12bb second conductor region 12bc intrinsic region 13 gate insulating film 14 gate metal film 14a first gate electrode (gate metal layer)
14e Light emission control line (second gate electrode, gate metal layer)
15 FirstInterlayer Insulating Film 16 Intermediate Metal Film 16c Capacitance Electrode (Intermediate Metal Layer)
17 SecondInterlayer Insulation Film 18 Organic Insulation Film 19 Source Metal Film 19e First Connection Wiring (Source Metal Layer)
19g Power line 30a, 30b TFT layer (thin film transistor layer)
35 Organic EL element (organic electroluminescence element, light emitting element)
40 Organic EL element layer (light emitting element layer)
50a, 50b Organic EL display device
Ｈｂ 第２コンタクトホール
Ｈｃ 第３コンタクトホール
Ｈｒ 貫通孔
Ｍａ 第１開口部
Ｍｂ 第２開口部
Ｍｃ 第３開口部
Ｐ サブ画素
Ｒ レジスト材料
Ｒｂ レジストパターン
９ｄ 駆動ＴＦＴ（第１薄膜トランジスタ）
９ｅ 電源供給ＴＦＴ（第２薄膜トランジスタ）
９ｈ キャパシタ
１０ 樹脂基板層（ベース基板）
１２ 半導体膜
１２ａ 第１半導体層
１２ａｂ 第２導体領域
１２ｂ 第２半導体層
１２ｂａ 第１導体領域
１２ｂｂ 第２導体領域
１２ｂｃ 真性領域
１３ ゲート絶縁膜
１４ ゲート金属膜
１４ａ 第１ゲート電極（ゲート金属層）
１４ｅ 発光制御線（第２ゲート電極、ゲート金属層）
１５ 第１層間絶縁膜
１６ 中間金属膜
１６ｃ 容量電極（中間金属層）
１７ 第２層間絶縁膜
１８ 有機絶縁膜
１９ ソース金属膜
１９ｅ 第１接続配線（ソース金属層）
１９ｇ 電源線
３０ａ，３０ｂ ＴＦＴ層（薄膜トランジスタ層）
３５ 有機ＥＬ素子（有機エレクトロルミネッセンス素子、発光素子）
４０ 有機ＥＬ素子層（発光素子層）
５０ａ，５０ｂ 有機ＥＬ表示装置 Ha First contact hole Hb Second contact hole Hc Third contact hole Hr Through hole Ma First opening Mb Second opening Mc Third opening P Sub-pixel R Resist material Rb Resist
9e Power supply TFT (second thin film transistor)
12
14e Light emission control line (second gate electrode, gate metal layer)
15 First
17 Second
35 Organic EL element (organic electroluminescence element, light emitting element)
40 Organic EL element layer (light emitting element layer)
50a, 50b Organic EL display device
Claims (19)
- ベース基板と、
上記ベース基板上に設けられ、半導体層、ゲート絶縁膜、ゲート金属層、第１層間絶縁膜、中間金属層、第２層間絶縁膜、有機絶縁膜及びソース金属層が順に積層され、サブ画素毎に薄膜トランジスタ及びキャパシタが配置された薄膜トランジスタ層と、
上記薄膜トランジスタ層上に設けられ、上記サブ画素毎に発光素子が配置された発光素子層とを備え、
上記薄膜トランジスタは、上記半導体層として設けられた第１半導体層と、上記ゲート絶縁膜と、上記ゲート金属層として設けられた第１ゲート電極とを備えた第１薄膜トランジスタを有し、
上記キャパシタは、上記第１ゲート電極と、上記第１層間絶縁膜と、上記中間金属層として設けられ、平面視で該第１ゲート電極に重なるように配置された容量電極とを備え、
上記容量電極には、平面視で上記第１ゲート電極と重なると共に該容量電極を貫通するように第１開口部が設けられ、
上記第１層間絶縁膜及び上記第２層間絶縁膜には、平面視で上記第１開口部の周縁の内側に配置すると共に、該第１層間絶縁膜及び該第２層間絶縁膜を貫通するように第２開口部が設けられ、
上記有機絶縁膜には、平面視で上記第２開口部の周縁の内側に配置すると共に、該有機絶縁膜を貫通するように第１コンタクトホールが設けられ、
上記第１ゲート電極は、上記第１コンタクトホールを介して、上記ソース金属層として設けられた接続配線に電気的に接続され、
上記有機絶縁膜は、上記第２開口部の側面を覆うように設けられていることを特徴とする表示装置。 A base substrate,
Provided on the base substrate, a semiconductor layer, a gate insulating film, a gate metal layer, a first interlayer insulating film, an intermediate metal layer, a second interlayer insulating film, an organic insulating film and a source metal layer are laminated in this order for each subpixel. A thin film transistor layer in which a thin film transistor and a capacitor are arranged,
The light emitting element layer is provided on the thin film transistor layer, and the light emitting element is arranged for each of the sub-pixels,
The thin film transistor includes a first thin film transistor including a first semiconductor layer provided as the semiconductor layer, the gate insulating film, and a first gate electrode provided as the gate metal layer,
The capacitor includes the first gate electrode, the first interlayer insulating film, and a capacitive electrode provided as the intermediate metal layer and arranged so as to overlap the first gate electrode in a plan view.
The capacitance electrode is provided with a first opening so as to overlap with the first gate electrode in a plan view and penetrate the capacitance electrode.
The first interlayer insulating film and the second interlayer insulating film are arranged inside the peripheral edge of the first opening in a plan view, and penetrate the first interlayer insulating film and the second interlayer insulating film. Is provided with a second opening,
The organic insulating film is provided inside the peripheral edge of the second opening in plan view, and a first contact hole is provided so as to penetrate the organic insulating film.
The first gate electrode is electrically connected to the connection wiring provided as the source metal layer through the first contact hole,
The display device, wherein the organic insulating film is provided so as to cover a side surface of the second opening. - 請求項１に記載された表示装置において、
上記第２開口部の側面は、上記ベース基板側に向けて逆テーパ状に傾斜していることを特徴とする表示装置。 The display device according to claim 1,
The display device is characterized in that a side surface of the second opening is inclined in a reverse taper shape toward the base substrate side. - 請求項２に記載された表示装置において、
上記第１コンタクトホールの側面は、上記ベース基板側に向けて順テーパ状に傾斜していることを特徴とする表示装置。 The display device according to claim 2,
A display device, wherein a side surface of the first contact hole is inclined in a forward taper shape toward the base substrate side. - 請求項１に記載された表示装置において、
上記第１コンタクトホールの側面は、上記ベース基板側に向けて順テーパ状に傾斜していることを特徴とする表示装置。 The display device according to claim 1,
A display device, wherein a side surface of the first contact hole is inclined in a forward taper shape toward the base substrate side. - 請求項１に記載された表示装置において、
上記薄膜トランジスタは、上記半導体層として設けられた第２半導体層と、上記ゲート絶縁膜と、上記ゲート金属層として設けられた第２ゲート電極とを備えた第２薄膜トランジスタを有し、
上記第２半導体層は、平面視で上記第２ゲート電極に重なるように設けられた真性領域と、該真性領域を挟むように設けられた一対の導体領域とを備え、
上記ゲート絶縁膜、上記第１層間絶縁膜及び上記第２層間絶縁膜には、該ゲート絶縁膜、該第１層間絶縁膜及び該第２層間絶縁膜を貫通して、上記一対の導体領域の一方に到達するように第３開口部が設けられ、
上記有機絶縁膜には、平面視で上記第３開口部の内側に配置すると共に、該有機絶縁膜を貫通するように第２コンタクトホールが設けられ、
上記一対の導体領域の一方は、上記第２コンタクトホールを介して、上記ソース金属層として設けられた電源線に電気的に接続され、
上記第２コンタクトホールは、上記ゲート金属層として設けられた発光制御線と隣り合うように設けられていることを特徴とする表示装置。 The display device according to claim 1,
The thin film transistor includes a second thin film transistor including a second semiconductor layer provided as the semiconductor layer, the gate insulating film, and a second gate electrode provided as the gate metal layer,
The second semiconductor layer includes an intrinsic region provided so as to overlap the second gate electrode in a plan view, and a pair of conductor regions provided so as to sandwich the intrinsic region.
The gate insulating film, the first interlayer insulating film, and the second interlayer insulating film penetrate the gate insulating film, the first interlayer insulating film, and the second interlayer insulating film, and form the pair of conductor regions. The third opening is provided to reach one side,
The organic insulating film is provided inside the third opening in a plan view, and a second contact hole is provided so as to penetrate the organic insulating film.
One of the pair of conductor regions is electrically connected to the power supply line provided as the source metal layer through the second contact hole,
The display device, wherein the second contact hole is provided adjacent to the light emission control line provided as the gate metal layer. - 請求項５に記載された表示装置において、
上記第３開口部の側面は、上記ベース基板側に向けて逆テーパ状に傾斜していることを特徴とする表示装置。 The display device according to claim 5,
A display device, wherein a side surface of the third opening is inclined in an inverse taper shape toward the base substrate side. - 請求項６に記載された表示装置において、
上記第２コンタクトホールの側面は、上記ベース基板側に向けて順テーパ状に傾斜していることを特徴とする表示装置。 The display device according to claim 6,
The display device is characterized in that a side surface of the second contact hole is inclined in a forward taper shape toward the base substrate side. - 請求項５に記載された表示装置において、
上記第２コンタクトホールの側面は、上記ベース基板側に向けて順テーパ状に傾斜していることを特徴とする表示装置。 The display device according to claim 5,
A display device, wherein a side surface of the second contact hole is inclined in a forward taper shape toward the base substrate side. - 請求項１～８の何れか１つに記載された表示装置において、
上記ゲート絶縁膜、上記第１層間絶縁膜、上記第２層間絶縁膜及び上記有機絶縁膜には、該ゲート絶縁膜、該第１層間絶縁膜、該第２層間絶縁膜及び該有機絶縁膜を貫通するように第３コンタクトホールが設けられ、
上記接続配線は、上記第３コンタクトホールを介して、上記第１半導体層の導体領域に電気的に接続されていることを特徴とする表示装置。 The display device according to any one of claims 1 to 8,
The gate insulating film, the first interlayer insulating film, the second interlayer insulating film, and the organic insulating film include the gate insulating film, the first interlayer insulating film, the second interlayer insulating film, and the organic insulating film. A third contact hole is provided so as to penetrate therethrough,
The display device, wherein the connection wiring is electrically connected to the conductor region of the first semiconductor layer through the third contact hole. - 請求項１～９の何れか１つに記載された表示装置において、
上記有機絶縁膜は、塗布型の絶縁材料により形成されていることを特徴とする表示装置。 The display device according to any one of claims 1 to 9,
The display device, wherein the organic insulating film is formed of a coating type insulating material. - 請求項１０に記載された表示装置において、
上記有機絶縁膜は、感光性を有していることを特徴とする表示装置。 The display device according to claim 10,
The organic insulating film is a display device characterized by having photosensitivity. - 請求項１～１１の何れか１つに記載された表示装置において、
上記発光素子は、有機エレクトロルミネッセンス素子であることを特徴とする表示装置。 In the display device according to any one of claims 1 to 11.
The display device, wherein the light emitting element is an organic electroluminescence element. - ベース基板上にサブ画素毎に薄膜トランジスタ及びキャパシタが配置された薄膜トランジスタ層を形成する薄膜トランジスタ層形成工程と、
上記薄膜トランジスタ層上に設けられ、上記サブ画素毎に発光素子が配置された発光素子層を形成する発光素子層形成工程とを備え、
上記薄膜トランジスタは、第１薄膜トランジスタを有し、該第１薄膜トランジスタは、第１半導体層と、第１半導体層上に設けられたゲート絶縁膜と、上記ゲート絶縁膜上に設けられた第１ゲート電極とを備え、
上記キャパシタは、上記第１ゲート電極と、上記第１ゲート電極上に設けられた第１層間絶縁膜と、上記第１層間絶縁膜上に設けられ、平面視で該第１ゲート電極に重なるように配置された容量電極とを備えており、
上記薄膜トランジスタ層形成工程は、
上記ベース基板上に半導体膜を成膜した後に、該半導体膜をパターニングして上記第１半導体層を含む半導体層を形成する半導体層形成工程と、
上記半導体層上に上記ゲート絶縁膜を形成するゲート絶縁膜形成工程と、
上記ゲート絶縁膜上にゲート金属膜を成膜した後に、該ゲート金属膜をパターニングして上記第１ゲート電極を含むゲート金属層を形成するゲート金属層形成工程と、
上記ゲート金属層上に上記第１層間絶縁膜を形成する第１層間絶縁膜形成工程と、
上記ゲート金属層上に形成された上記第１層間絶縁膜上に中間金属膜を成膜した後に、該中間金属膜をパターニングして平面視で上記第１ゲート電極に重なるように貫通した第１開口部が設けられた上記容量電極を含む中間金属層を形成する中間金属層形成工程と、
上記中間金属層上に第２層間絶縁膜を形成する第２層間絶縁膜形成工程と、
上記第１層間絶縁膜及び上記第２層間絶縁膜に平面視で上記第１開口部の周縁の内側に配置するように貫通した第２開口部を形成する開口部形成工程と、
上記第２開口部が形成された上記第２層間絶縁膜上に有機絶縁膜を塗布した後に、該有機絶縁膜をパターニングして、平面視で上記第２開口部の周縁の内側に配置するように貫通した第１コンタクトホールを形成するコンタクトホール形成工程と、
上記有機絶縁膜上にソース金属膜を成膜した後に、該ソース金属膜をパターニングして上記第１コンタクトホールを介して上記第１ゲート電極に電気的に接続された接続配線を含むソース金属層を形成するソース金属層形成工程とを備え、
上記コンタクトホール形成工程では、上記第２開口部の側面を覆うように上記有機絶縁膜をパターニングすることを特徴とする表示装置の製造方法。 A thin film transistor layer forming step of forming a thin film transistor layer in which a thin film transistor and a capacitor are arranged for each sub-pixel on a base substrate;
A light emitting element layer forming step of forming a light emitting element layer provided on the thin film transistor layer and having a light emitting element arranged for each of the sub-pixels,
The thin film transistor has a first thin film transistor, and the first thin film transistor includes a first semiconductor layer, a gate insulating film provided on the first semiconductor layer, and a first gate electrode provided on the gate insulating film. With and
The capacitor is provided on the first gate electrode, the first interlayer insulating film provided on the first gate electrode, and the first interlayer insulating film so as to overlap the first gate electrode in a plan view. And a capacitive electrode arranged in
The thin film transistor layer forming step,
A semiconductor layer forming step of forming a semiconductor film on the base substrate and then patterning the semiconductor film to form a semiconductor layer including the first semiconductor layer;
A gate insulating film forming step of forming the gate insulating film on the semiconductor layer,
A gate metal layer forming step of forming a gate metal film on the gate insulating film and then patterning the gate metal film to form a gate metal layer including the first gate electrode;
A first interlayer insulating film forming step of forming the first interlayer insulating film on the gate metal layer;
After forming an intermediate metal film on the first interlayer insulating film formed on the gate metal layer, the intermediate metal film is patterned and penetrated so as to overlap the first gate electrode in a plan view. An intermediate metal layer forming step of forming an intermediate metal layer including the capacitance electrode provided with an opening,
A second interlayer insulating film forming step of forming a second interlayer insulating film on the intermediate metal layer;
An opening forming step of forming a second opening penetrating the first interlayer insulating film and the second interlayer insulating film so as to be arranged inside the peripheral edge of the first opening in a plan view;
After applying the organic insulating film on the second interlayer insulating film on which the second opening is formed, the organic insulating film is patterned and arranged inside the peripheral edge of the second opening in a plan view. A contact hole forming step of forming a first contact hole penetrating to
A source metal layer including a connection wiring electrically connected to the first gate electrode through the first contact hole by forming a source metal film on the organic insulating film and then patterning the source metal film. With a source metal layer forming step to form
In the contact hole forming step, the organic insulating film is patterned so as to cover a side surface of the second opening, a manufacturing method of a display device. - 請求項１３に記載された表示装置の製造方法において、
上記開口部形成工程は、
上記第２層間絶縁膜上にネガ型のレジスト材料を塗布する工程と、
上記レジスト材料を露光、現像及び焼成することにより、上記第２開口部に対応して、上記ベース基板側に向けて側面が逆テーパ状に傾斜した貫通孔が設けられたレジストパターンを形成する工程と、
上記レジストパターンから露出する上記第２層間絶縁膜及び上記第１層間絶縁膜をエッチングして、上記ベース基板側に向けて側面が逆テーパ状に傾斜した上記第２開口部を形成する工程とを備えることを特徴とする表示装置の製造方法。 The method for manufacturing a display device according to claim 13,
The opening forming step,
A step of applying a negative resist material on the second interlayer insulating film,
A step of exposing, developing, and firing the resist material to form a resist pattern having through holes whose side surfaces are inclined in a reverse taper shape toward the base substrate side in response to the second opening. When,
A step of etching the second interlayer insulating film and the first interlayer insulating film exposed from the resist pattern to form the second opening whose side surface is inclined in a reverse taper shape toward the base substrate side. A method for manufacturing a display device, comprising: - 請求項１３又は１４に記載された表示装置の製造方法において、
上記コンタクトホール形成工程では、上記ベース基板側に向けて側面が順テーパ状に傾斜するように上記第１コンタクトホールを形成することを特徴とする表示装置の製造方法。 In the method for manufacturing a display device according to claim 13 or 14.
In the contact hole forming step, the method of manufacturing a display device, wherein the first contact hole is formed so that a side surface thereof is inclined in a forward tapered shape toward the base substrate side. - 請求項１３に記載された表示装置の製造方法において、
上記薄膜トランジスタは、第２薄膜トランジスタを有し、該第２薄膜トランジスタは、上記半導体層として設けられた第２半導体層と、第２半導体層上に設けられた上記ゲート絶縁膜と、上記ゲート絶縁膜上に上記ゲート金属層として設けられた第２ゲート電極とを備え、
上記第２半導体層は、平面視で上記第２ゲート電極に重なるように設けられた真性領域と、該真性領域を挟むように設けられた一対の導体領域とを備えており、
上記開口部形成工程では、上記ゲート絶縁膜、上記第１層間絶縁膜及び上記第２層間絶縁膜に該ゲート絶縁膜、該第１層間絶縁膜及び該第２層間絶縁膜を貫通して、上記一対の導体領域の一方に到達するように第３開口部を形成し、
上記コンタクトホール形成工程では、上記有機絶縁膜に平面視で上記第３開口部と重なると共に、該有機絶縁膜を貫通するように第２コンタクトホールを形成し、
上記ソース金属層形成工程では、上記ソース金属膜をパターニングして上記第２コンタクトホールを介して上記一対の導体領域の一方に電気的に接続された電源線を形成することを特徴とする表示装置の製造方法。 The method for manufacturing a display device according to claim 13,
The thin film transistor has a second thin film transistor, and the second thin film transistor has a second semiconductor layer provided as the semiconductor layer, the gate insulating film provided on the second semiconductor layer, and the gate insulating film. A second gate electrode provided as the gate metal layer,
The second semiconductor layer includes an intrinsic region provided so as to overlap the second gate electrode in a plan view, and a pair of conductor regions provided so as to sandwich the intrinsic region.
In the opening forming step, the gate insulating film, the first interlayer insulating film, and the second interlayer insulating film are penetrated through the gate insulating film, the first interlayer insulating film, and the second interlayer insulating film. Forming a third opening so as to reach one of the pair of conductor regions,
In the contact hole forming step, a second contact hole is formed in the organic insulating film so as to overlap the third opening in plan view and penetrate the organic insulating film.
In the source metal layer forming step, the source metal film is patterned to form a power supply line electrically connected to one of the pair of conductor regions through the second contact hole. Manufacturing method. - 請求項１６に記載された表示装置の製造方法において、
上記コンタクトホール形成工程では、上記ベース基板側に向けて側面が順テーパ状に傾斜するように上記第２コンタクトホールを形成することを特徴とする表示装置の製造方法。 In the method for manufacturing a display device according to claim 16,
In the contact hole forming step, the second contact hole is formed so that a side surface thereof is inclined in a forward taper shape toward the base substrate side. - 請求項１６又は１７に記載された表示装置の製造方法において、
上記開口部形成工程は、
上記第２層間絶縁膜上にネガ型のレジスト材料を塗布する工程と、
上記レジスト材料を露光、現像及び焼成することにより、上記第２開口部に対応して、上記ベース基板側に向けて側面が逆テーパ状に傾斜した貫通孔が設けられたレジストパターンを形成する工程と、
上記レジストパターンから露出する上記第２層間絶縁膜、上記第１層間絶縁膜及び上記ゲート絶縁膜をエッチングして、上記ベース基板側に向けて側面が逆テーパ状に傾斜した上記第３開口部を形成する工程とを備えることを特徴とする表示装置の製造方法。 In the method for manufacturing a display device according to claim 16 or 17.
The opening forming step,
A step of applying a negative resist material on the second interlayer insulating film,
A step of forming a resist pattern in which a through hole whose side surface is inclined in an inverse taper shape toward the base substrate side is provided corresponding to the second opening by exposing, developing, and baking the resist material. When,
The second interlayer insulating film exposed from the resist pattern, the first interlayer insulating film, and the gate insulating film are etched to form the third opening whose side surface is inclined in a reverse taper shape toward the base substrate side. And a step of forming the display device. - 請求項１３～１８の何れか１つに記載された表示装置の製造方法において、
上記発光素子は、有機エレクトロルミネッセンス素子であることを特徴とする表示装置の製造方法。 In the method for manufacturing a display device according to any one of claims 13 to 18.
The method for manufacturing a display device, wherein the light emitting element is an organic electroluminescence element.
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