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WO2020154831A1 - 测序芯片及其制备方法 - Google Patents

测序芯片及其制备方法 Download PDF

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Publication number
WO2020154831A1
WO2020154831A1 PCT/CN2019/073332 CN2019073332W WO2020154831A1 WO 2020154831 A1 WO2020154831 A1 WO 2020154831A1 CN 2019073332 W CN2019073332 W CN 2019073332W WO 2020154831 A1 WO2020154831 A1 WO 2020154831A1
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WO
WIPO (PCT)
Prior art keywords
oxide layer
transition metal
chip
metal oxide
wafer
Prior art date
Application number
PCT/CN2019/073332
Other languages
English (en)
French (fr)
Inventor
李世峰
李腾跃
李元
王照辉
江雪芹
陈家诚
王奥立
黄扶兴
宋晓刚
彭玲玲
李汉东
章文蔚
Original Assignee
深圳华大生命科学研究院
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to CA3125496A priority Critical patent/CA3125496A1/en
Application filed by 深圳华大生命科学研究院 filed Critical 深圳华大生命科学研究院
Priority to AU2019426202A priority patent/AU2019426202B2/en
Priority to CN201980090338.1A priority patent/CN113396229B/zh
Priority to KR1020217024474A priority patent/KR102634755B1/ko
Priority to PCT/CN2019/073332 priority patent/WO2020154831A1/zh
Priority to EP24164794.0A priority patent/EP4407044A1/en
Priority to JP2021541150A priority patent/JP7386874B2/ja
Priority to EP19913626.8A priority patent/EP3919630B1/en
Priority to CN202410336310.4A priority patent/CN118325713A/zh
Priority to SG11202108115XA priority patent/SG11202108115XA/en
Publication of WO2020154831A1 publication Critical patent/WO2020154831A1/zh
Priority to US17/377,114 priority patent/US20210384031A1/en
Priority to JP2023108319A priority patent/JP2023138996A/ja

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    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
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    • B01J2219/00277—Apparatus
    • B01J2219/00497—Features relating to the solid phase supports
    • B01J2219/00527—Sheets
    • B01J2219/00529—DNA chips
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
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    • B01J2219/00—Chemical, physical or physico-chemical processes in general; Their relevant apparatus
    • B01J2219/00274—Sequential or parallel reactions; Apparatus and devices for combinatorial chemistry or for making arrays; Chemical library technology
    • B01J2219/00583—Features relative to the processes being carried out
    • B01J2219/00603—Making arrays on substantially continuous surfaces
    • B01J2219/00605—Making arrays on substantially continuous surfaces the compounds being directly bound or immobilised to solid supports
    • B01J2219/00608—DNA chips
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01J—CHEMICAL OR PHYSICAL PROCESSES, e.g. CATALYSIS OR COLLOID CHEMISTRY; THEIR RELEVANT APPARATUS
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    • B01J2219/00274—Sequential or parallel reactions; Apparatus and devices for combinatorial chemistry or for making arrays; Chemical library technology
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    • B01J2219/00603—Making arrays on substantially continuous surfaces
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    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
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    • B01J2219/00—Chemical, physical or physico-chemical processes in general; Their relevant apparatus
    • B01J2219/00274—Sequential or parallel reactions; Apparatus and devices for combinatorial chemistry or for making arrays; Chemical library technology
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    • B01J2219/00603—Making arrays on substantially continuous surfaces
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    • B01J2219/00614—Delimitation of the attachment areas
    • B01J2219/00621—Delimitation of the attachment areas by physical means, e.g. trenches, raised areas
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    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
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    • B01J2219/00274—Sequential or parallel reactions; Apparatus and devices for combinatorial chemistry or for making arrays; Chemical library technology
    • B01J2219/00583—Features relative to the processes being carried out
    • B01J2219/00603—Making arrays on substantially continuous surfaces
    • B01J2219/00605—Making arrays on substantially continuous surfaces the compounds being directly bound or immobilised to solid supports
    • B01J2219/00623—Immobilisation or binding
    • B01J2219/00626—Covalent
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    • B01J2219/00603—Making arrays on substantially continuous surfaces
    • B01J2219/00659—Two-dimensional arrays
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    • B01L2200/06—Fluid handling related problems
    • B01L2200/0647—Handling flowable solids, e.g. microscopic beads, cells, particles
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    • B01L2300/00—Additional constructional details
    • B01L2300/08—Geometry, shape and general structure
    • B01L2300/0809—Geometry, shape and general structure rectangular shaped
    • B01L2300/0819—Microarrays; Biochips
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
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    • C12Q1/00—Measuring or testing processes involving enzymes, nucleic acids or microorganisms; Compositions therefor; Processes of preparing such compositions
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    • C12Q1/6869—Methods for sequencing

Definitions

  • the present invention relates to the field of biotechnology. Specifically, the present invention relates to a sequencing chip and a preparation method thereof.
  • Microarray sequencing chips are one of the necessary conditions for high-throughput sequencing.
  • the currently used DNA Nano Ball (DNB, DNA Nano Ball) sequencing technology requires fixing the DNB on the sequencing chip for the next step of sequencing biochemical reactions.
  • each chip has nearly 200 million DNB binding sites on its surface.
  • the surface of the sequencing chip needs to be aminated.
  • the areas other than the non-binding sites on the chip surface need to be treated to minimize non-specific adsorption, reduce background, and improve sequencing quality. Therefore, efficient and low-cost preparation of sequencing chips with microarrays is one of the basic tasks to achieve high-quality sequencing.
  • the current manufacturing steps of sequencing chips mainly include: firstly, a patterned photoresist layer containing nano-arrays is prepared on a silicon wafer by a semiconductor process.
  • the patterned layer can contain multiple identical unit structures, and each unit can form one Sequencing chip; then the wafer with the patterned layer is subjected to chemical vapor deposition processing to form an amination layer in the functional area of the wafer; then after the assembly process, the wafer is divided into individual chips and assembled into testable Sequencing chip.
  • the process of forming a patterned photoresist layer on a silicon wafer includes: first, a silicon wafer is provided, and a silicon oxide layer is formed on the surface of the silicon wafer. Then a HMDS (Hexamethyldisiloxane) layer is formed on the silicon oxide layer using chemical vapor deposition (CVD) or spin coating method, and is formed by standard photolithography, development, and oxygen plasma etching process In the patterned photoresist layer, the part of the photoresist layer that has been developed and treated with oxygen plasma will expose the underlying silicon oxide layer.
  • the patterned photoresist layer includes a plurality of units containing the same nano-array structure, and each unit can form a sequencing chip.
  • the process of forming an amination layer in the functional area is: the silicon wafer with the patterned photoresist layer is amination treated by chemical vapor deposition. In the areas where there is no photoresist and exposed silicon oxide, the amino The amination layer is formed on the silicon oxide layer, and in the area covered by other photoresist, the amination layer is formed on the photoresist layer.
  • the assembly process includes: coating a second layer of protective photoresist on the wafer that has undergone amination treatment, and cutting the wafer by a wafer dicing process to form multiple single chips.
  • the surface will form a functionalized array pattern with alternating amination areas and HMDS areas, and then use glue or other adhesives to assemble the frame, cover glass and chip into fluid channels and liquid inlets and outlets.
  • the fluid channel is formed between the cover glass and the silicon chip and is separated by glue or adhesive, and the liquid inlet and outlet can be on the frame or the cover glass.
  • the DNB sample to be tested is injected into the fluid channel through the liquid inlet and outlet, and contacts the surface functionalized array with the amination area and the HMDS area alternately arranged on the silicon chip.
  • the DNB will be selectively aminated
  • the area is adsorbed and repelled by the HMDS area, so an array of DNB arrays are formed on the surface.
  • the signal emitted by the DNB array is collected by an optical method, the arrangement of bases on the DNB can be identified for sequencing applications.
  • the sequencing chip prepared by this method mainly performs sequencing by selectively adsorbing DNB on the amination area and HMDS area on the surface of the silicon chip, but both the amination area and the HMDS area are monolayers on the surface of silicon oxide.
  • the surface monomolecular layer is easily damaged by physical and chemical contact (such as surface scratching, high temperature or contact with other chemical reagents that can react with it), thereby affecting the sequencing chip The performance even makes the chip unusable. This not only affects the efficiency of generating valid data when the sequencing chip is used for sequencing applications, but also reduces the yield of the sequencing chip preparation, reduces the output of the sequencing chip, and indirectly increases the cost of the sequencing chip.
  • the present invention proposes a new type of sequencing chip structure and preparation method that is more stable, reliable, and has better performance.
  • the present invention does not use a monolayer on the surface to form a DNB array, but instead uses a patterned array (a cross-cut or spot-shaped) alternately existing on the surface of the silicon wafer with a metal oxide area and a silicon oxide area on the surface of the silicon wafer. Adsorb DNB and form a DNB array that can be used for sequencing.
  • the sequencing chip of the present invention is also prepared by a semiconductor process.
  • a patterned array with transition metal oxide regions and silicon oxide regions alternately is formed on a wafer, and then the wafer is cut into multiple single chips using a slicing process , And assemble a single chip into a sequencing chip through an assembly process.
  • the difference in surface properties of transition metal oxide and silicon oxide can be used to realize the selectivity between the DNB binding site area (i.e. functional area, transition metal oxide area) and non-binding site area (i.e.
  • non-functional area silicon oxide
  • the inventors also proposed for the first time that an amino group was specifically introduced on the transition metal oxide to further improve The functional area on the chip surface specifically binds to DNB.
  • the inventor also proposed for the first time the use of a copolymer with good biocompatibility (such as polyethylene glycol compounds) on the non-functional area on the chip surface (that is, the non-binding site of DNB).
  • the advantage of the sequencing chip of the present invention is that the surface of the silicon wafer is an array formed by alternating metal oxide regions and silicon oxide regions, which is more stable and reliable than an array formed by a monolayer, and can improve the data output efficiency of the sequencing chip , Improve the output of sequencing chips, thereby reducing costs.
  • the present invention also proposes an optimal structural size of the sequencing chip based on the optical simulation result, and the superior structural size can enhance the signal emitted by the sample to be tested, thereby improving the performance of the sequencing chip.
  • the present invention proposes a chip substrate.
  • the chip substrate includes: a wafer layer with uniformly distributed cutting lines; a first silicon oxide layer, the first silicon oxide layer is composed of silicon oxide, and is formed on the The upper surface of the wafer layer; a transition metal oxide layer, the transition metal oxide layer is composed of a transition metal oxide, and is formed on the upper surface of the first silicon oxide layer.
  • the "chip substrate” in the present invention refers to a sequencing chip unit that can be used to divide into chip particles.
  • the chip substrate according to the embodiment of the present invention can be divided into chip particles, and the chip particles can be divided into chip particles. It is further combined into a sequencing chip main body, and the sequencing chip main body and a support frame with liquid inlet and outlet ports form a sequencing chip.
  • the chip substrate according to the embodiment of the present invention has a transition metal oxide layer composed of a transition metal oxide and a silicon oxide layer composed of silicon oxide, and the transition metal oxide and silicon oxide have different properties, they can be changed
  • the pH and surfactant components of the solution containing the sequence to be sequenced, especially DNB enable the sequence to be sequenced to be selectively adsorbed on the transition metal oxide region of the chip substrate according to the embodiment of the present invention.
  • the chip matrix of the embodiment can be divided into two regions, namely the binding site region (ie functional region) of the sequence to be sequenced, and the non-binding site region (ie non-functional region) of the sequence to be sequenced.
  • the transition metal oxide layer on the substrate constitutes a functional area that specifically binds the sequence to be sequenced, while the silicon oxide layer that cannot bind the sequenced sequence constitutes a non-functional area.
  • the binding site region and non-binding site region of the sequencing sequence can be selectively modified to further enhance the selective adsorption capacity of the sequence to be tested in the transition metal oxide region.
  • the chip substrate according to the embodiment of the present invention has the characteristics of high temperature resistance, high humidity resistance and other harsh environments.
  • the present invention provides a sequencing chip.
  • the sequencing chip includes a chip main body, the chip main body includes a plurality of chip particles, and the chip particles are obtained by cutting the aforementioned chip substrate along the cutting line of the wafer layer. .
  • the inventor found that the selective adsorption of the sequence to be sequenced on the transition metal oxide layer can be achieved only by changing the pH and surfactant composition of the solution containing the sequence to be sequenced, especially DNB.
  • the sequencing chip according to the embodiment of the present invention is more stable and the sequencing result is more reliable, can significantly improve the data output efficiency of the sequencing chip, increase the output of the sequencing chip, and significantly reduce the sequencing cost.
  • the present invention provides a method for preparing the aforementioned chip substrate.
  • the method includes: performing surface modification on a wafer layer, and the surface modification includes treating the surface of the wafer layer with a transition metal oxide to form a transition metal oxide layer, so
  • the upper surface of the wafer layer has a first silicon oxide layer, the silicon oxide layer is composed of silicon oxide, the transition metal layer is formed on the upper surface of the first silicon oxide layer, and the wafer layer has evenly distributed Cutting line.
  • the method according to the embodiment of the present invention is simple to operate and environmentally friendly.
  • the present invention provides a method for preparing a sequencing chip.
  • the method includes: assembling chip particles, the chip particles are obtained by cutting the chip matrix along the cutting line of the wafer layer, and the chip matrix is defined as described above Or according to the method described above.
  • the method according to the embodiment of the present invention is simple to operate, and the yield of the prepared sequencing chip is high.
  • the present invention provides a sequencing method.
  • the method includes: using a sequencing chip to perform sequencing, the sequencing chip is as defined above or prepared according to the method described above. According to the method of the embodiment of the present invention, the sequencing result is more accurate and the cost is lower.
  • Figures 1-5 are cross-sectional views of various processes in the preparation process of the patterned transition metal oxide layer sequencing chip with the arrayed "spot" structure according to one aspect of the present invention, wherein,
  • FIG. 1 is a cross-sectional view of a wafer structure 1-10 in which a transition metal oxide layer film with an array type "spot" structure is formed on a wafer with a silicon oxide layer on the surface according to an embodiment of the present invention
  • FIG. 2 is a cross-sectional view of multiple single chips 1-20 formed after the wafer structure 1-10 in FIG. 1 is subjected to a slicing process according to an embodiment of the present invention
  • FIG. 3 is a cross-sectional view of a sequencing chip 1-30 formed after the chip in FIG. 2 is subjected to an assembly process according to an embodiment of the present invention
  • FIG. 4 is a sequencing chip 1-40 after surface functional modification of the sequencing chip 1-30 in FIG. 3 according to an embodiment of the present invention
  • 5A is a cross-sectional view of a sequencing chip 1-50A containing a DNB array formed after DNB is loaded on the sequencing chip 1-40 with surface modification in FIG. 4 according to an embodiment of the present invention
  • 5B is a cross-sectional view of a more concise sequencing chip 1-50B that can form a DNB array in a sequencing chip without surface modification according to an embodiment of the present invention
  • FIG. 5C shows the relationship between the intensity of the fluorescent signal and the thickness of the silicon oxide layer according to an embodiment of the present invention
  • Fig. 5D shows the relationship between the intensity of the fluorescent signal and the thickness of the transition metal oxide ('spot' structure) according to an embodiment of the present invention
  • 6-11 are cross-sectional views of various processes in the preparation process of the patterned transition metal oxide layer sequencing chip with an array type "well" structure according to another aspect of the present invention, wherein,
  • FIG. 6 is a cross-sectional view of a wafer structure 2-10 in which a thin film of a transition metal oxide layer is formed on a wafer with a silicon oxide layer on the surface according to an embodiment of the present invention
  • FIG. 7 is a wafer 2 formed after forming a silicon oxide layer with an array type "well” structure on the wafer structure 2-10 with a transition metal oxide layer film shown in FIG. 6 according to an embodiment of the present invention -20 section view;
  • FIG. 8 is a cross-sectional view of a plurality of single chips 2-30 formed after slicing the wafer structure 2-20 with the arrayed "well" structure shown in FIG. 7 according to an embodiment of the present invention
  • FIG. 9 is a cross-sectional view of a sequencing chip 2-40 formed after the single chip in FIG. 8 is subjected to an assembly process according to an embodiment of the present invention.
  • FIG. 10 is a cross-sectional view of a sequencing chip 2-50 formed after the sequencing chip shown in FIG. 9 is subjected to surface functional modification treatment according to an embodiment of the present invention
  • 11A is a cross-sectional view of a sequencing chip 2-60A with a DNB array formed after loading the sequencing chip 2-50 with surface functional modification treatment shown in FIG. 10 with DNB according to an embodiment of the present invention
  • 11B is a cross-sectional view of a more concise sequencing chip 2-60B that can form a DNB array in a sequencing chip without surface modification according to an embodiment of the present invention
  • FIG. 11C shows the relationship between the fluorescent signal of different "well” structures based on the silicon substrate and the second oxide layer according to an embodiment of the present invention
  • FIG. 11D shows the relationship between the intensity of the fluorescence signal and the thickness of the transition metal oxide according to an embodiment of the present invention
  • FIG. 12 is a cross-sectional view of a wafer structure 3-10 in which a transition metal oxide layer with an arrayed "spot" structure is formed on a wafer with a silicon oxide layer on the surface according to an embodiment of the present invention
  • FIG. 13 is a wafer 3 formed after forming a silicon oxide layer with an array type "well” structure on the wafer structure 3-10 with a transition metal oxide layer film shown in FIG. 12 according to an embodiment of the present invention -20 section view;
  • FIG. 14 is a cross-sectional view of a plurality of single chips 3-30 formed after slicing the wafer structure 3-20 with the arrayed "well" structure shown in FIG. 13 according to an embodiment of the present invention
  • FIG. 15 is a cross-sectional view of a sequencing chip 3-40 formed after the single chip in FIG. 14 is subjected to an assembly process according to an embodiment of the present invention
  • FIG. 16 is a cross-sectional view of a sequencing chip 3-50 formed after the sequencing chip shown in FIG. 15 is subjected to surface functional modification treatment according to an embodiment of the present invention
  • FIG. 17A is a cross-sectional view of a sequencing chip 3-60A with a DNB array formed after loading the sequencing chip 3-50 with surface functional modification treatment shown in FIG. 16 with DNB according to an embodiment of the present invention
  • 17B is a cross-sectional view of a more concise sequencing chip 3-60B that can form a DNB array in a sequencing chip without surface modification according to an embodiment of the present invention
  • FIG. 17C shows the relationship between the fluorescence signal of another silicon substrate-based different "well” structure and the second oxide layer according to an embodiment of the present invention
  • 18-22 are cross-sectional views of various processes in the preparation process of the back-illuminated, patterned transition metal oxide layer sequencing chip with an array type "spot" structure according to another aspect of the present invention.
  • FIG. 18 is a cross-sectional view of a wafer structure 4-10 in which a transition metal oxide layer film with an array type "spot" structure is formed on a wafer with a silicon oxide layer on the surface according to an embodiment of the present invention
  • FIG. 19 is a cross-sectional view of a plurality of single chips 4-20 formed after slicing the wafer structure 4-10 with the arrayed "well" structure shown in FIG. 18 according to an embodiment of the present invention
  • FIG. 20 is a cross-sectional view of the sequencing chip 4-30 formed after the single chip 4-20 in FIG. 19 is subjected to an assembly process according to an embodiment of the present invention.
  • This assembly process is to assemble the chip patterned layer downwards and the frame , So that the excitation light source and the camera illuminate the DNB through the quartz or glass substrate from the back of the chip and collect signals;
  • 21 is a cross-sectional view of a sequencing chip 4-40 formed after the sequencing chip shown in FIG. 20 is subjected to surface functional modification treatment according to an embodiment of the present invention
  • 22A is a cross-sectional view of a sequencing chip 4-50A with a DNB array formed after DNB loading the sequencing chip 4-40 shown in FIG. 21 that has undergone surface functional modification treatment according to an embodiment of the present invention
  • 22B is a cross-sectional view of a more concise sequencing chip 4-50B that can form a DNB array in a sequencing chip without surface modification according to an embodiment of the present invention
  • FIG. 22C shows the relationship between the fluorescent signal based on the quartz substrate and the second oxide layer (back-illuminated "spot” structure) according to an embodiment of the present invention
  • 23-28 are cross-sectional views of various processes in the preparation process of the back-illuminated, patterned transition metal oxide layer sequencing chip with an array type "well" structure according to another aspect of the present invention.
  • FIG. 23 is a cross-sectional view of a wafer structure 5-10 in which a thin film of a transition metal oxide layer is formed on a wafer with a silicon oxide layer on the surface according to an embodiment of the present invention
  • FIG. 24 is a wafer 5 formed after forming a silicon oxide layer with an arrayed "well” structure on the wafer structure 5-10 with a transition metal oxide layer film shown in FIG. 23 according to an embodiment of the present invention -20 section view;
  • FIG. 25 is a cross-sectional view of a plurality of single chips 5-30 formed after slicing the wafer structure 5-20 with the arrayed "well" structure shown in FIG. 24 according to an embodiment of the present invention
  • FIG. 26 is a cross-sectional view of the sequencing chip 5-40 formed after the single chip 5-30 in FIG. 25 is subjected to an assembly process according to an embodiment of the present invention.
  • the assembly process is to assemble the chip with the patterned layer facing down and the frame , So that the excitation light source and the camera illuminate the DNB through the quartz or glass substrate from the back of the chip and collect signals;
  • FIG. 27 is a cross-sectional view of a sequencing chip 5-50 formed after the sequencing chip shown in FIG. 26 is subjected to surface functional modification treatment according to an embodiment of the present invention
  • 28A is a cross-sectional view of a sequencing chip 5-60A with a DNB array formed after loading the sequencing chip 5-50 with surface functional modification treatment shown in FIG. 27 with DNB according to an embodiment of the present invention
  • 28B is a cross-sectional view of a more concise sequencing chip 5-60B that can form a DNB array in a sequencing chip without surface modification according to an embodiment of the present invention
  • FIG. 28C shows the relationship between the fluorescence signal of different "well” structures based on the quartz substrate and the second oxide layer (back-illuminated "well” structure) according to an embodiment of the present invention
  • 29-34 are cross-sectional views of various processes in the preparation process of the back-illuminated, patterned transition metal oxide layer sequencing chip with another array type "well" structure according to another aspect of the present invention, wherein,
  • 29 is a cross-sectional view of a wafer structure 6-10 in which a transition metal oxide layer 613 with an array type "spot" structure is formed on a wafer 611 with a silicon oxide layer 612 on the surface according to an embodiment of the present invention
  • FIG. 30 is a wafer 6 formed after forming a silicon oxide layer with an array type "well” structure on the wafer structure 6-10 with a transition metal oxide layer film shown in FIG. 29 according to an embodiment of the present invention -20 section view;
  • FIG. 31 is a cross-sectional view of a plurality of single chips 6-30 formed after slicing the wafer structure 6-20 with the array type "well" structure shown in FIG. 30 according to an embodiment of the present invention
  • FIG. 32 is a cross-sectional view of the sequencing chip 6-40 formed after the single chip 6-30 in FIG. 31 is subjected to an assembly process according to an embodiment of the present invention.
  • the assembly process is to assemble the chip patterned layer downwards and the frame , So that the excitation light source and the camera illuminate the DNB through the quartz or glass substrate from the back of the chip and collect signals;
  • FIG. 33 is a cross-sectional view of a sequencing chip 6-50 formed after the sequencing chip shown in FIG. 32 is subjected to surface functional modification treatment according to an embodiment of the present invention
  • 34A is a cross-sectional view of a sequencing chip 6-60A with a DNB array formed after loading the sequencing chip 6-50 with surface functional modification treatment shown in FIG. 33 with DNB according to an embodiment of the present invention
  • 34B is a cross-sectional view of a more concise sequencing chip 6-60B that can form a DNB array in a sequencing chip without surface modification according to an embodiment of the present invention
  • FIG. 34C shows the relationship between the fluorescence signal of another different "well” structure based on a quartz substrate and the second oxide layer (another back-illuminated "well” structure) according to an embodiment of the present invention
  • 35-41 are cross-sections of various process steps in the preparation process of a sequencing chip with an arrayed "spot” structure or a "well” structure patterned transition metal oxide layer on a CMOS image sensor wafer according to another aspect of the present invention Figure;
  • 35 is a cross-sectional view of a CMOS image sensor wafer 7-10 with a surface oxide layer according to an embodiment of the present invention
  • 36A is a cross-sectional view of a wafer structure 7-20A after an arrayed "spot" structure patterned transition metal oxide layer is formed on the CMOS wafer 7-10 shown in FIG. 35 according to an embodiment of the present invention
  • 36B is a cross-sectional view of the wafer structure 7-20B after an arrayed "well" structure patterned transition metal oxide layer is formed on the CMOS wafer 7-10 shown in FIG. 35 according to an embodiment of the present invention
  • 36C is a cross-sectional view of the wafer structure 7-20C after forming another arrayed "well” structure patterned transition metal oxide layer on the CMOS wafer 7-10 shown in FIG. 35 according to an embodiment of the present invention ;
  • FIG. 37 is a cross-sectional view of a plurality of single chips 7-30 formed after performing a slicing process on the CMOS wafer 7-20 with a patterned transition metal oxide layer shown in FIG. 36 according to an embodiment of the present invention
  • FIG. 38 is a cross-sectional view of a chip structure 7-40 formed after chip mounting and wire bonding of the single chip shown in FIG. 37 according to an embodiment of the present invention
  • FIG. 39 is a cross-sectional view of a sequencing chip 7-50 formed by attaching a lid structure to the chip 7-50 after chip mounting and wire bonding shown in FIG. 38 according to an embodiment of the present invention
  • FIG. 40 is a cross-sectional view of the sequencing chip 7-60 formed after the surface functional modification treatment of the sequencing chip shown in FIG. 39 according to an embodiment of the present invention
  • 41A is a cross-sectional view of a sequencing chip 7-70A with a DNB array formed after DNB is loaded on the chip 7-60 shown in FIG. 40 after surface functional modification treatment according to an embodiment of the present invention
  • 41B is a cross-sectional view of a more concise sequencing chip 7-70B that can form a DNB array in the sequencing chip without surface modification according to an embodiment of the present invention
  • FIG. 41C shows the relationship between the fluorescence intensity based on the CMOS structure and the thickness of the top oxide layer according to an embodiment of the present invention
  • FIG. 41D shows the relationship between the fluorescence intensity based on the CMOS structure and the thickness of the "spot" metal oxide layer according to an embodiment of the present invention
  • FIG. 41E shows the relationship between the fluorescence intensity based on the CMOS structure and the thickness of the thin-film metal oxide layer according to an embodiment of the present invention
  • 41F is the relationship between the fluorescence intensity based on the CMOS structure and the thickness of the second oxide layer (thin film metal oxide layer) according to an embodiment of the present invention.
  • FIG. 43 is a cross-sectional view of a wafer structure 8-20 after multiple single chips 81 and 82 are formed after the wafer structure 8-10 shown in FIG. 42 is subjected to a slicing process according to an embodiment of the present invention
  • Fig. 44 is a cross-sectional view of a reusable sequencing chip 8-30 formed by assembling the single chip 81 or 82 formed in Fig. 43 and a handle structure 831 according to an embodiment of the present invention
  • FIG. 45 is a schematic diagram of immersing the assembled sequencing chip shown in FIG. 44 into a container 841 containing a reagent 842 according to an embodiment of the present invention
  • FIG. 46 is a fluorescence image of the surface of the transition metal oxide chip without modification but changing the DNB loading conditions according to an embodiment of the present invention.
  • FIG. 47 is a diagram showing the results of on-machine sequencing on the Zebra platform according to an embodiment of the present invention.
  • FIG. 48 is a fluorescence image after selective amination modification of the surface of a transition metal oxide chip after DNB loading according to an embodiment of the present invention.
  • Fig. 49 is a fluorescence image of the transition metal oxide region after amination of the transition metal oxide region and the copolymer modification of the silica non-functional region after DNB loading, left: control group, right: experimental group; and
  • Figure 50 is a fluorescence image of the detection of the effect of further modification of non-functional regions using a silane coupling agent containing polyethylene glycol according to an embodiment of the present invention. Left: control group, right: experimental group.
  • a single chip is assembled into a sequencing chip
  • the sequencing core of the DNB array is formed in the sequencing chip
  • transition metal oxide layer 2-60A: sequencing chip with DNB array formed after DNB loading on the sequencing chip,
  • 3-60B The sequencing chip that forms the DNB array in the sequencing chip
  • 5-60B The sequencing chip that forms the DNB array in the sequencing chip
  • 61 and 62 a single chip on a wafer
  • 6-60B A sequencing chip that forms a DNB array in a sequencing chip
  • 661 DNB
  • CMOS wafer structure after forming a patterned transition metal oxide layer with a "spot" structure on the CMOS image sensor wafer
  • Chip structure formed after chip mounting and wire bonding Chip structure formed after chip mounting and wire bonding
  • Wafer structure with transition metal oxide layer of array type "spot" structure Wafer structure with transition metal oxide layer of array type "spot" structure
  • Wafer structure The wafer structure after multiple single chips formed after the slicing process
  • a reusable sequencing chip formed by assembling a single chip and a handle structure
  • the reagents and testing instruments in the example can be prepared by yourself or obtained through commercial channels unless otherwise specified.
  • transition metal oxide region in the present invention refers to a region composed of transition metal oxide viewed from the surface of the chip substrate
  • silicon oxide region in the present invention refers to the region from the surface of the chip substrate Look at the area made of silicon oxide.
  • patterned layer refers to a shape in which transition metal oxide regions and silicon oxide regions alternately exist on the surface of the wafer, including “tic-square” and “spot” structures.
  • spot structure means that the transition metal oxide region is higher than the silicon oxide region, that is, the transition metal oxide is in a discrete distribution on the silicon oxide.
  • the transition metal oxide layer is a continuous layer structure, and the second silicon dioxide layer is formed on the upper surface of the transition metal oxide layer by silicon oxide in a number of connected crosses” refers to the second silicon dioxide
  • the layer is a grid structure covering the upper surface of the transition metal oxide layer, that is, the grid body of the grid is silicon oxide, and the recess of the grid is a transition metal oxide. It can also be understood that the second silicon dioxide layer is sunken like a well, forming a grid shape on the upper surface of the transition metal oxide layer.
  • chip matrix can be used to divide into individual chips and assemble them into sequencing chips that can be tested. The wafer structure contains tens to thousands of the same single chip (depending on the wafer size and chip size), and a very narrow non-functional interval is reserved between the chip and the chip, which is also called a cutting line .
  • the preparation of the sequencing chip of the present invention is not particularly limited, and can be adapted to the conventional method for preparing a sequencing chip from the wafer material in the prior art according to the difference of the wafer material used.
  • the difference from the sequencing chip in the prior art is ,
  • the single chip used is different.
  • single chip refers to the "chip matrix" in the present invention obtained by cutting along the cutting line, and can also be called “chip particles”.
  • the present invention proposes a chip substrate.
  • the chip substrate includes: a wafer layer with uniformly distributed cutting lines; a first silicon oxide layer, the first silicon oxide layer is composed of silicon oxide, and is formed on the The upper surface of the wafer layer; a transition metal oxide layer, the transition metal oxide layer is composed of a transition metal oxide, and is formed on the upper surface of the first silicon oxide layer.
  • the surface of the chip substrate according to the embodiment of the present invention includes two regions, namely, the binding site region (transition metal oxide region, or functional region) of the sequence to be sequenced (especially DNB) and the non-binding site region (oxidation) of the sequence to be sequenced. Silicon area, that is, non-functional area).
  • the transition metal oxide region and non-functional region can be selectively modified to further enhance the selective adsorption capacity of DNB in the transition metal oxide region.
  • the transition metal oxide layer is composed of several unconnected transition metal oxide spots.
  • the transition metal oxide can be discretely distributed on the surface of the silicon oxide by conventional methods such as sputtering, electron beam evaporation or thermal evaporation atomic layer deposition to form a patterned transition metal oxide layer in a "spot" shape.
  • sputtering electron beam evaporation or thermal evaporation atomic layer deposition
  • transition metal oxide spots that specifically bind the sequencing sequence and silicon oxide regions that cannot bind the sequencing sequence are formed on the chip substrate.
  • the thickness of the transition metal oxide spots is 10-20 nm, and the thickness of the first silicon oxide layer is 80-100 nm, preferably 90 nm.
  • the thickness of transition metal oxide spots is 10-20nm and the silicon oxide layer, the thickness of the first silicon oxide layer is 80-100nm, preferably 90nm chip matrix can be sequenced to be sequenced, especially DNB emission
  • the light reflectivity of the sequence to be sequenced is higher, so that the sequence to be sequenced, especially the light signal emitted by DNB, is captured by the signal detection device as much as possible, which indirectly enhances the signal intensity of the sequence to be sequenced, especially the signal intensity of DNB, and makes the signal to noise ratio higher , Significantly improve the performance of the final sequencing chip.
  • amino groups are further connected to the transition metal oxide spots.
  • the inventor found that the amination of transition metal oxide molecules can further improve the specificity of DNB adsorption on the surface of the chip matrix. Therefore, by adjusting the pH of DNB and the surfactant composition, the specific adsorption function of DNB on the surface functional area of the chip matrix is stronger.
  • polyethylene glycol is further connected to the first silicon oxide layer between the plurality of unconnected transition metal oxide spots.
  • the chip substrate further includes a second silicon dioxide layer.
  • the transition metal oxide layer has a continuous layer structure
  • the second silicon dioxide layer is formed of silicon oxide on the upper surface of the transition metal oxide layer in a number of connected tic-tacles.
  • the continuous layer structure means that the transition metal oxide is spread all over the first silicon oxide layer.
  • one or more second silicon dioxide layers having a cross-cut shape are covered on the transition metal oxide layer, and a pattern in which patterned transition metal oxide and silicon oxide alternately appear can be obtained.
  • the transition metal oxide layer is composed of a plurality of unconnected transition metal oxide spots
  • the second silicon dioxide layer is formed between the plurality of unconnected transition metal oxide spots
  • the upper surface of the first silicon oxide layer It is understandable that the second silicon dioxide layer and the transition metal oxide spots can form a cross-cut shape, where the transition metal oxide is in the cross-cut recess, and the second silicon dioxide layer forms a cross-cut lattice.
  • the second silicon dioxide layer can be higher than the transition metal oxide layer, and can also be as high as the transition metal oxide layer.
  • the wafer is a silicon wafer
  • the thickness of the second silicon dioxide layer is 40-60 nm, preferably 50 nm
  • the thickness of the transition metal oxide layer is 5-15 nm.
  • the thickness of the first silicon oxide layer is 80-100 nm, preferably 90 nm.
  • the sequence to be sequenced especially the light emitted by DNB
  • the detection device captures the indirect enhancement of the signal strength of the sequence to be sequenced, especially the DNB, so that the signal-to-noise ratio is higher, and the performance of the finally obtained sequencing chip is significantly improved.
  • the wafer is a quartz wafer
  • the thickness of the second silicon dioxide layer is 100-200 nm
  • the thickness of the transition metal oxide layer is 10-20 nm
  • the first silicon oxide layer The thickness of the layer is 80-100 nm, preferably 90 nm.
  • the inventor calculated by simulation that when the wafer is a quartz wafer, the thickness of the second silicon dioxide layer of the chip matrix forming the cross-cut structure is 100-200nm, the thickness of the transition metal oxide layer is 10-20nm, and the first silicon oxide layer
  • the thickness is 80-100nm, preferably 90nm
  • the sequence to be sequenced, especially the light emitted by DNB has a higher reflectivity, so that the sequence to be sequenced, especially the light signal emitted by DNB, is captured by the signal detection device as much as possible , which indirectly enhances the signal strength of the sequence to be sequenced, especially DNB, makes the signal-to-noise ratio higher, and significantly improves the performance of the final sequencing chip.
  • the final formed sequencing chip not only ensures that the well-shaped structure has the appropriate depth to load the sequence to be sequenced, especially DNB, but also enables the camera to collect relatively high intensity Fluorescence signal.
  • an amino group is further connected to the transition metal oxide layer or the transition metal oxide spots at the recess of the second silicon dioxide layer.
  • the inventor found that amination of transition metal oxide molecules can further improve the specificity of the adsorption of the sequence to be sequenced on the surface functional area of the chip substrate. Therefore, by adjusting the pH of the sequence to be sequenced and the surfactant composition, the specific adsorption of the sequence to be sequenced can be achieved by the functional area on the surface of the chip substrate.
  • polyethylene glycol is further connected to the second silicon dioxide layer.
  • the amino group and at least a part of the transition metal oxide molecules in the transition metal oxide layer are connected by a chemical bond.
  • chemical bond refers to a transition metal-O-P bond (such as Zr-O-P bond, Ti-O-P bond, Ta-O-P bond).
  • the amino group and the transition metal oxide can be closely combined.
  • the chemical bond is formed by the transition metal oxide molecule and the phosphoric acid group of the aminophosphonic acid compound.
  • the inventor used the phosphonic acid group to react specifically with the transition metal oxide molecule without reacting with the silicon oxide layer, and the amino phosphonic acid compound can specifically introduce the amino group on the transition metal oxide molecule.
  • the polyethylene glycol is provided by including at least one selected from polyethyleneimine-polyethylene glycol and a silane coupling agent containing polyethylene glycol.
  • the polyethylene glycol is provided by polyethyleneimine-polyethylene glycol, and the polyethyleneimine-polyethylene glycol is electrostatically adsorbed on the surface of the first silicon oxide layer Or the surface of the second silicon dioxide layer.
  • the polyethylene glycol is provided by a silane coupling agent containing polyethylene glycol, and the silane coupling agent containing polyethylene glycol is combined with the -Si-O-Si- chain
  • the first silicon oxide layer or the second silicon oxide layer is connected.
  • the material of the wafer according to the embodiment of the present invention is not limited.
  • the wafer includes at least one selected from a silicon wafer, a quartz wafer, a glass wafer, and a CMOS wafer.
  • the transition metal oxide includes at least one selected from the group consisting of titanium dioxide, zirconium dioxide, tantalum pentoxide, niobium hexaoxide, and hafnium dioxide.
  • the transition metal oxide includes at least one selected from titanium dioxide, zirconium dioxide, and tantalum pentoxide.
  • the present invention provides a sequencing chip.
  • the sequencing chip includes a chip main body, the chip main body includes a plurality of chip particles, and the chip particles are obtained by cutting the aforementioned chip substrate along the cutting line of the wafer layer. .
  • the inventor found that the selective adsorption of the sequence to be sequenced on the transition metal oxide layer can be achieved only by changing the pH and surfactant composition of the solution containing the sequence to be sequenced.
  • the sequencing chip according to the embodiment of the present invention is more stable and the sequencing result is more reliable, can significantly improve the data output efficiency of the sequencing chip, increase the output of the sequencing chip, and significantly reduce the sequencing cost.
  • the sequencing chip structure according to the embodiments of the present invention may not require a surface monolayer, or may be surface modified after the chip preparation process is completed. Therefore, the sequencing chip of the present invention has the characteristics of stable properties, and it can withstand scratches Wipe this kind of physical contact without affecting the performance of the sequencing chip, and it can withstand high temperature and chemical reagent corrosion. Therefore, the chip can withstand more stringent, but more efficient processing and assembly processes, and is less likely to be damaged during packaging, transportation and pre-use preparations. Therefore, the yield of the sequencing chip is improved, and the efficiency of using the sequencing chip to generate data is increased, thereby reducing the cost.
  • the present invention provides a method for preparing the aforementioned chip substrate.
  • the method includes: performing surface modification on a wafer layer, and the surface modification includes treating the surface of the wafer layer with a transition metal oxide to form a transition metal oxide layer, so
  • the upper surface of the wafer layer has a first silicon oxide layer, the silicon oxide layer is composed of silicon oxide, the transition metal layer is formed on the upper surface of the first silicon oxide layer, and the wafer layer has evenly distributed Cutting line.
  • the method according to the embodiment of the present invention is simple to operate and environmentally friendly.
  • the first silicon oxide layer is formed in advance on the upper surface of the wafer layer by low temperature plasma chemical vapor deposition, plasma enhanced chemical vapor deposition, sputtering, or atomic layer deposition.
  • the method of forming the first silicon oxide layer on the surface of the wafer is not limited, and can be carried out by conventional semiconductor technology, such as low temperature plasma chemical vapor deposition, plasma enhanced chemical vapor deposition, sputtering, atomic layer Deposition etc.
  • the surface modification of the wafer layer is achieved by thin film deposition, photolithography or etching, so as to form a continuous transition metal oxide layer or a transition metal oxide layer arranged in spots.
  • a patterned transition metal oxide layer is formed on the silicon oxide layer.
  • the transition metal oxide may be titanium dioxide, zirconium dioxide, tantalum pentoxide, niobium hexaoxide, or niobium dioxide.
  • the transition metal oxide layer is discretely distributed on the silicon oxide layer, and forms a specific array pattern (ie, transition metal oxide lattice and specially designed graphics or lines for later sequencing Optical calibration), and have the same pattern arrangement on each single chip.
  • This patterned layer can be realized by conventional semiconductor process technologies, such as thin film deposition, photolithography, and etching processes, that is, first formed on the silicon oxide layer by sputtering, electron beam evaporation, thermal evaporation atomic layer deposition and other thin film deposition techniques A layer covering the entire wafer transition metal oxide layer, and then on the metal oxide layer through thin film deposition, photolithography, etching processes to form a layer of hard mask material corresponding to the required patterning layer, and finally through etching The process re-etches the pattern of the hard mask layer onto the transition metal oxide layer to form a patterned transition metal oxide layer, that is, the discretely arranged transition metal oxides are arranged on the silicon oxide layer in a "spot" order.
  • the silicon oxide layer will be exposed on the area where there is no “spot” of transition metal oxide.
  • the size of the “spot”-like transition metal oxide area is the same as or slightly smaller than that of DNB, so that a “spot” only adsorbs A DNB.
  • the transition metal oxide layer has a continuous layer structure, and further includes a second silicon dioxide layer formed of silicon oxide on the upper surface of the transition metal oxide layer and arranged in a continuous trough shape.
  • the formation here is mainly achieved by atomic layer deposition.
  • a first silicon oxide layer is first formed on the wafer, and then a transition metal oxide layer is formed on the first silicon oxide layer, and then the photolithography,
  • the etching technique forms discretely arranged array "well” structures on the transition metal oxide layer.
  • the bottom of the "well” structure is the exposed transition metal oxide layer, and the periphery of the "well” structure is the silicon oxide layer higher than the transition metal oxide layer.
  • the size of the "well” is the same as or slightly smaller than the DNB size, so that each The "well” structure combines only one DNB.
  • the transition metal oxide layer is arranged in spots, and further includes depositing silicon oxide between the transition metal oxide layer spots to form a second silicon dioxide layer.
  • the deposition here is mainly achieved by atomic layer deposition.
  • a first silicon oxide layer is formed on the wafer first, and then a discrete array of "well" structures are formed on the silicon oxide layer by photolithography and etching techniques in conventional semiconductor processes. .
  • the bottom of the “well” structure is the exposed transition metal oxide layer, the surroundings of the “well” structure are higher or as high as the silicon oxide layer of the transition metal oxide layer, and the size of the “well” is the same as or slightly smaller than the DNB size , So that each "well” structure only combines one DNB.
  • it further includes an amination treatment on the transition metal oxide.
  • amino groups can be introduced into the functional area of the chip matrix to further improve the specific adsorption capacity of the functional area of the sequence to be sequenced, especially DNB.
  • the amination treatment is obtained by reacting a transition metal oxide with an aminophosphonic acid compound.
  • the aminophosphonic acid compound and the transition metal oxide can form a transition metal-O-P bond (such as a Zr-O-P bond, a Ti-O-P bond, and a Ta-O-P bond).
  • amino groups can be introduced into the functional area of the chip matrix to further improve the specific adsorption capacity of the functional area to sequence sequence, especially DNB.
  • it further includes surface modification of the first silicon oxide layer or the second silicon dioxide layer, so as to introduce polyethylene glycol into the first silicon oxide layer or the second silicon dioxide layer. Therefore, the adsorption capacity of the non-functional regions of the chip matrix to the sequencing sequence, especially DNB, can be further reduced.
  • the polyethylene glycol is provided by including at least one selected from polyethyleneimine-polyethylene glycol and a silane coupling agent containing polyethylene glycol.
  • the polyethylene glycol is provided by polyethyleneimine-polyethylene glycol, and the surface modification is performed by combining polyethyleneimine-polyethylene glycol with the first silica
  • the surface of the layer or the surface of the second silicon dioxide layer is electrostatically adsorbed.
  • polyethylene glycol can be introduced into the non-functional area of the chip substrate.
  • the polyethylene glycol is provided by a silane coupling agent containing polyethylene glycol, and the surface modification is performed by combining the silane coupling agent containing polyethylene glycol with the first
  • the condensation reaction of the hydroxyl groups of the silicon oxide layer or the second silicon dioxide layer is carried out, and the hydroxyl groups are provided by the Si-OH formed after the first or second silicon dioxide layer is ionized and adsorbs hydroxide ions in the water.
  • polyethylene glycol can be introduced into the non-functional area of the chip substrate.
  • the present invention provides a method for preparing a sequencing chip.
  • the method includes: assembling chip particles, the chip particles are obtained by cutting the chip matrix along the cutting line of the wafer layer, and the chip matrix is defined as described above Or according to the method described above.
  • the method according to the embodiment of the present invention is simple to operate, and the yield of the prepared sequencing chip is high.
  • the cutting is realized by a semiconductor wafer cutting method.
  • the assembling includes placing the chip particles in a supporting frame containing liquid inlets and outlets, and bonding the chip particles and the supporting frame with glue or an adhesive to form a structure.
  • a fluid channel is formed between the chip particles.
  • the wafer is a silicon wafer
  • the assembling includes: attaching the upper surface of the chip pellet to the supporting frame, and placing a cover glass on the upper surface of the chip pellet , In order to obtain the sequencing chip.
  • the wafer is a quartz wafer or a glass wafer
  • the assembling includes: attaching the chip particles to the support frame with the lower surface facing upward, so as to obtain the sequencing chip.
  • the wafer is a CMOS wafer
  • the assembly includes: attaching the lower surface of the chip particles to a substrate (ie, photosensitive element), and the chip particles and the substrate pass through The lead wire is used to transmit the electrical signal on the chip particle to the substrate.
  • the substrate form includes but is not limited to LGA, CLCC, PLCC and other forms.
  • the metal wire used for the wire bonding includes, but is not limited to, gold wire and aluminum wire.
  • the present invention provides a sequencing method.
  • the method includes: using a sequencing chip for sequencing, and the sequencing chip is as defined above or prepared according to the method described above. According to the method of the embodiment of the present invention, the sequencing result is more accurate and the cost is lower.
  • the transition metal oxide layer of the sequencing chip is pre-fixed with DNB.
  • the DNB sample can be considered as a point light source.
  • the light emitted by it can be collected by a camera or CMOS image sensor, and then sequenced.
  • Embodiment 1 Method for preparing "spot” structure transition metal oxide sequencing chip on silicon or quartz wafer
  • this embodiment proposes a method for preparing a "spot" structure transition metal oxide sequencing chip on a silicon or quartz wafer, and shows a cross-sectional view of the process of each step of the method .
  • the method can be completed on a bare wafer without any internal circuits or structures.
  • the illustration of the present invention only schematically shows two regions 11 and 12 on the wafer. Those skilled in the art should recognize that multiple regions (depending on the wafer size and chip size) can be formed on the wafer. , The number of chips can range from tens to thousands) A single chip with the same structure, each single chip can form a sequencing chip.
  • Figure 1 shows the patterning of alternating DNB-containing binding site regions (transition metal oxide layer, ie functional region) and DNB non-binding site regions (silicon oxide layer, ie non-functional region) formed on a bare wafer Cross-sectional view of layer 1-10 of wafer.
  • the material can be silicon or quartz. However, those skilled in the art should realize that the present invention does not limit the substrate material to silicon or quartz. Any other suitable Semiconductor wafer materials can also be used in the present invention.
  • a silicon oxide layer 112 is formed on the wafer 111.
  • the silicon oxide layer can be formed by conventional semiconductor technology, such as low temperature plasma chemical vapor deposition, plasma enhanced chemical vapor deposition, sputtering, atomic layer deposition, and the like. Then, a patterned transition metal oxide layer is formed on the silicon oxide layer.
  • the transition metal oxide can be titanium dioxide, zirconium dioxide, tantalum pentoxide, niobium hexaoxide, hafnium dioxide or any combination thereof.
  • the metal oxide layer is discretely distributed on the silicon oxide layer and forms a specific array pattern, and each single chip (single chip 11 and 12 in Figure 1) has the same pattern arrangement .
  • This patterned layer can be realized by conventional semiconductor process technologies, such as thin film deposition, photolithography, and etching processes, that is, first formed on the silicon oxide layer by sputtering, electron beam evaporation, thermal evaporation atomic layer deposition and other thin film deposition techniques One layer covers the entire wafer transition metal oxide layer (not shown), and then a hard mask material layer corresponding to the desired patterned layer is formed on the metal oxide layer through thin film deposition, photolithography, and etching processes (Not shown), finally, the pattern of the hard mask layer is re-etched onto the transition metal oxide layer through an etching process to form the patterned transition metal oxide layer shown in structure 113 in FIG. 1.
  • the discretely arranged transition metal oxides are arranged on the silicon oxide layer in "spots" orderly, and in areas where there is no transition metal oxide "spots", the silicon oxide layer It will be exposed, where the size of the "spot”-like transition metal oxide region is the same as or slightly smaller than the size of the DNB, so that one "spot” only adsorbs one DNB. It should be realized that the process steps required to form the patterned layer are described here, but any process method that can realize the patterned layer should be included in this invention.
  • the wafer structure 1-10 in Figure 1 can contain tens to thousands of identical chips (depending on the wafer size and chip size), and a very narrow non-functional interval is reserved between the chip and the chip. Also called a dicing line, the dicing knife can cut the wafer into multiple single chips without damaging the effective structure area of the chip.
  • FIG. 2 shows a cross-sectional view of multiple single wafer structures 1-20 formed after the wafer 1-10 with the patterned transition metal oxide layer is subjected to a slicing process.
  • the wafer in FIG. 2 has been diced into individual chips divided by the dicing groove 121.
  • FIG. 2 schematically illustrates the individual chips 11 and 12 formed after the slicing process.
  • FIG. 3 shows a cross-sectional view after the single chip is assembled into a sequencing chip 1-30.
  • a single chip with a patterned surface layer 131 is first installed in the frame structure 131 containing the liquid inlet and outlet 133, and then the hydrophobically treated cover glass 132 is attached to the frame structure 131 and placed on the cover glass
  • a fluid channel 134 is formed between the sheet 132 and the chip containing the patterned surface 113, and liquid can pass into or out of the fluid channel 134 from the liquid inlet and outlet 133.
  • assembling the chip into the frame 131 and attaching the cover glass 132 to the frame 131 are all fixed by an adhesive method, and any suitable adhesive can be used in the present invention.
  • This figure schematically depicts the structure of the assembled sequencing chip, that is, it includes a frame that provides liquid inlet and outlet ports, and a cover glass that forms a fluid channel with the frame, but those skilled in the art should recognize that any suitable material
  • the frame and cover glass, and any frame and cover glass structure that can provide liquid inlet and outlet ports and fluid passages, should be included in the present invention.
  • Figure 4 shows the sequencing chip 1-40 formed after functional surface modification of the sequencing chip 1-30.
  • the liquid used for surface modification can enter the fluid channel through the liquid inlet and outlet, and contact the transition metal oxide region and the silicon oxide region, and functionally modify the surface to make it have adsorption DNB (ie DNB binding site). , Transition metal oxide region, functional region) and repelling DNB (ie DNB non-binding site, silicon oxide region, non-functional region) function.
  • the surface modification process includes: 1) forming a polyethylene glycol molecular layer 142 on the surface of the silicon oxide layer.
  • the polyethylene glycol molecule includes at least one selected from polyethyleneimine-polyethylene glycol and a silane coupling agent containing polyethylene glycol, whereby the non-specific adsorption of DNB on the non-functional area on the chip surface is further reduced
  • the polyethylene glycol molecule is polyethyleneimine-polyethylene glycol.
  • One end of the plurality of polyethylene glycol molecules and the silicon oxide layer 112 are connected by electrostatic adsorption.
  • Polyethyleneimine-polyethylene glycol can be self-assembled on the silicon oxide layer 112, and then adsorbed on the silicon oxide layer 112 by electrostatic action; or the polyethylene glycol molecule is a silane coupling containing polyethylene glycol One end of the plurality of polyethylene glycol molecules is connected to the silicon oxide layer 112 through a -Si-O-Si- chain.
  • the silane coupling agent containing polyethylene glycol can interact with the hydroxyl groups on the surface of the silicon oxide layer 112. Condensation reaction to form -Si-O-Si-chain. 2)
  • a plurality of amino groups 141 are formed on the transition metal oxide layer.
  • the plurality of amino groups are connected to at least a part of the plurality of transition metal oxide molecules, and the plurality of amino groups are not connected to the silicon oxide layer.
  • the multiple amino groups are provided by aminophosphonic acid compounds.
  • the phosphonic acid group does not react with the silicon oxide layer but reacts specifically with the transition metal oxide molecule, and amino phosphonic acid compounds can be used to specifically introduce the amino group on the transition metal oxide molecule; or
  • the plurality of amino groups are connected to at least a part of the plurality of transition metal oxide molecules through chemical bonds.
  • the inventor used the phosphonic acid group to react specifically with the transition metal oxide molecule without reacting with the silicon oxide layer, and the amino phosphonic acid compound can specifically introduce the amino group on the transition metal oxide molecule.
  • the phosphonic acid group and the transition metal oxide molecule can form a corresponding chemical bond, and the plurality of amino groups are connected to the transition metal oxide molecule by forming a chemical bond with the transition metal oxide molecule through the phosphonic acid group;
  • the chemical bond is formed by the transition metal and the phosphoric acid group of the aminophosphonic acid compound.
  • the phosphonic acid group in the aminophosphonic acid compound can form the corresponding transition metal-OP bond (such as Zr-OP bond, Ti-OP bond, Ta-OP bond) with the transition metal oxide molecule, so the multiple The amino group is connected to the transition metal oxide molecule through the transition metal-OP bond formed by the phosphonic acid group and the transition metal oxide molecule.
  • FIG. 5A is a cross-sectional view of a sequencing chip 1-50A containing a DNB array formed by loading the sequencing chip 1-40 formed after functionalization in FIG. 4 with DNB. Pass the DNB reagent into the fluid channel through the liquid inlet and outlet 133 on the sequencing chip. DNB will selectively bind to the DNB binding site (transition metal oxide region modified by the amino group, that is, the functional region). Combine with DNB non-binding sites (polyethylene glycol modified silicon oxide layer) to form a DNB nanoarray.
  • Figure 5A also shows a light source and a camera 152.
  • the DNB combined with a fluorescent marker can emit light of a specific wavelength or energy under the excitation of a light source of a specific wavelength or energy, and the light is collected by the camera, and the light collected by the camera is analyzed.
  • the signal can identify the base arrangement on DNB.
  • FIG. 5B shows another more concise DNB loading method.
  • the sequencing chip 1-30 of Figure 3 in Figure 5B can be loaded without any surface modification treatment. This step requires the pH and surface activity of the DNB reagent
  • the composition of the agent is optimized, so that without surface functional modification, DNB can only be selectively adsorbed on the DNB binding site (transition metal oxide layer, that is, the functional region), and the DNB non-binding site (The silicon oxide layer, that is, the non-functional area) repels.
  • DNB binding site transition metal oxide layer, that is, the functional region
  • the silicon oxide layer that is, the non-functional area
  • the results are shown in FIGS. 5A and 5B.
  • the DNB sample 151 is loaded on the transition metal oxide "spot" 113, and the camera 152 is placed above the DNB sample and used to collect the light signal emitted by the DNB sample.
  • the DNB sample can be considered as a point light source, the light emitted upward is directly collected by the camera, part of the light emitted downward can be reflected by the transition metal oxide layer and silicon oxide layer and collected by the camera, and the other part emitted downward The light will pass through the transition metal oxide layer and the silicon oxide layer and enter the silicon substrate.
  • the inventor obtained an optimized thickness of the transition metal oxide layer and the silicon oxide layer through optical simulation calculations.
  • the transition metal oxide layer and the silicon oxide layer have the largest reflection and the smallest transmission of the optical signal emitted by the DNB.
  • the light signal emitted by the DNB is transmitted upward as much as possible and collected by the camera, that is, the intensity of the fluorescence signal captured by the camera is the largest.
  • the fluorescence signal intensity corresponding to different silicon oxide layer thicknesses in the absence of a transition metal oxide layer was calculated.
  • the simulation calculation results are shown in Figure 5C. Show. When the thickness of the silicon oxide layer is about 90 nanometers, the reflectance of light of the four wavelengths is relatively high.
  • the silicon oxide layer When the thickness of the silicon oxide layer is about 90 nanometers, the silicon oxide layer has the best reflection effect on the light signal emitted by the DNB sample, that is, the intensity of the fluorescence signal captured by the camera is the strongest. Then, when the thickness of the silicon oxide layer is 90 nanometers, the relationship between the change in the thickness of the transition metal oxide layer and the fluorescence signal intensity is calculated and simulated. The result is shown in Figure 5D.
  • the thickness of the transition metal oxide layer is less than 40 nanometers, As the thickness of the metal oxide layer increases, the intensity of the fluorescent signal that the camera can capture gradually decreases. Therefore, when the thickness of the transition metal oxide layer is about 10 to 20 nanometers, the transition metal oxide layer has better mechanical reliability, and The reflectance is the highest, and the fluorescence signal intensity captured by the camera is the highest, as shown in Figure 5D.
  • Embodiment 2 Method for preparing "well” structure transition metal oxide sequencing chip on silicon or quartz wafer
  • this embodiment provides a method for preparing a "well" structure transition metal oxide sequencing chip on a silicon or quartz wafer. And shows the cross-sectional view of the process of each step of the method.
  • the method can be completed on a bare wafer without any internal circuits or structures.
  • the illustration of the present invention only schematically shows two regions 21 and 22 on the wafer. Those skilled in the art should recognize that multiple regions (depending on the wafer size and chip size) can be formed on the wafer. , The number of chips can range from tens to thousands) A single chip with the same structure, each single chip can form a sequencing chip.
  • a wafer substrate 211 is provided.
  • the wafer substrate can be silicon or quartz material, but is not limited to this. Any suitable semiconductor wafer can be applied to the present invention.
  • a silicon oxide layer 212 is formed on the wafer 211, and the process of forming the silicon oxide layer is similar to that described in FIG. 1 in the first embodiment.
  • a transition metal oxide layer 213 is formed on the silicon oxide layer.
  • the transition metal oxide can be titanium dioxide, zirconium dioxide, tantalum pentoxide, niobium hexaoxide, hafnium dioxide or any combination thereof, and the formation method is the same as It is similar to that in Figure 1 in Example 1.
  • FIG. 7 shows a cross-sectional view of the wafer 2-20 after forming a patterned "well” structure silicon oxide layer on the wafer 2-10 containing the transition metal oxide layer in FIG.
  • a silicon oxide layer 221 is first formed on the wafer 2-10 of FIG. 6, and then a discrete array is formed on the silicon oxide layer 221 by photolithography and etching techniques in the conventional semiconductor process.
  • "Well" structure 222 The bottom of the “well” structure is the exposed transition metal oxide layer, and the periphery of the “well” structure is the silicon oxide layer 221 higher than the transition metal oxide layer.
  • the size of the “well” is the same as or slightly smaller than that of the DNB. Each "well” structure only combines one DNB.
  • FIG. 8 shows a cross-sectional view of multiple single chips 2-30 formed after the wafer structure 2-20 of FIG. 7 is subjected to a slicing process.
  • a slicing process similar to that in Fig. 2 in Example 1 is used.
  • the 2-20 wafer in FIG. 7 is diced into individual chips 21 and 22 separated by a dicing slot 231.
  • Fig. 9 shows a cross-sectional view of a sequencing chip 2-40 formed after a single chip is assembled.
  • the assembly process is similar to the process of FIG. 3 in Embodiment 1. It includes a frame 241 with a liquid inlet and outlet 243, and a cover glass 242 attached to the frame. A fluid channel is formed between the cover glass and the single chip containing the arrayed "well" structure.
  • FIG. 10 is a cross-sectional view of the sequencing chip 2-50 formed by subjecting the sequencing chip 2-40 of FIG. 9 to surface functional modification treatment.
  • the surface functionalization treatment steps in the figure are similar to those in Fig. 4 in Example 1.
  • the bottom of the "well" structure exposed on the transition metal oxide layer 213 forms an amino group-modified DNB binding site region (ie, functional region). ), and a polyethylene glycol molecular layer is formed on the surface of the silicon oxide layer above the transition metal oxide layer.
  • FIG. 11A is a cross-sectional view of a sequencing chip 2-60A with a DNB array formed after DNB loading on the sequencing chip 2-50 shown in FIG. 10.
  • DNB is loaded in the array type "well" structure of the sequencing chip 2-60A that has undergone surface functional modification treatment. This will enable DNB to withstand the washing of higher flow rates of liquid and improve the sequencing time of the sequencing chip. speed.
  • This figure also shows the excitation light source and camera structure 262, which can provide excitation light of a specific wavelength and capacity and collect the light signals of the specific wavelength and capacity emitted by the DNB marked with a fluorescent marker, which is used to identify DNB.
  • the arrangement of bases are examples of bases.
  • FIG. 11B shows another more concise DNB loading method.
  • the sequencing chip 2-40 in Figure 9 can be loaded with DNB without any surface modification treatment to form the sequencing chip 2-60B.
  • This step requires the pH of the DNB reagent And the surfactant components are optimized, so that without surface functional modification, DNB can only be selectively adsorbed on the DNB binding site (transition metal oxide layer, that is, the functional region), and is not modified by DNB.
  • the binding site (silicon oxide layer, ie non-functional area) repels.
  • the inventor found that the method of performing surface functional modification first and then loading DNB as shown in FIG. 10 and FIG. 11A will make the selective adsorption effect of DNB on the patterned surface better.
  • the inventor also optimized the thickness of the silicon oxide layer and the transition metal oxide layer through optical simulation calculations.
  • the transition metal oxide layer in this embodiment has a thin film structure, and the first layer is below the transition metal oxide layer.
  • the silicon oxide layer, above the transition metal oxide layer is a second silicon oxide layer with an array type "well" structure. According to the simulation results in Example 1, the inventors learned that when the thickness of the transition metal oxide layer varies from 0 to 40 nanometers, as the thickness of the transition metal oxide layer increases, the reflectance of the film gradually decreases, and the camera can The intensity of the collected fluorescent signal gradually decreases.
  • the fluorescence signal intensity is compared with the second layer with an arrayed "well" structure.
  • the relationship between the thickness of the silicon oxide layer. The simulation result is shown in FIG. 11C.
  • the thickness of the second silicon oxide layer increases, the intensity of the fluorescent signal gradually decreases, and the reflectivity of the film to the optical signal decreases. Therefore, in order to make the "well" structure have a certain depth for loading DNB, the inventor chooses the thickness of the second silicon oxide layer to be about 50 nanometers.
  • the thickness of the first silicon oxide layer is 90 nanometers and the thickness of the second silicon oxide layer is 50 nanometers
  • the corresponding relationship between the thickness of different transition metal oxide layers and the intensity of the fluorescent signal is simulated and calculated.
  • the simulation result is shown in Fig. 11D.
  • the trend of rejection is similar to that of the above-mentioned Example 1. That is, when the thickness of the transition metal oxide layer is less than 40 nanometers, as the thickness of the transition metal oxide layer increases, the reflectivity decreases, and the fluorescence signal The intensity gradually weakened. Therefore, the inventor believes that the thickness of the transition metal oxide layer is about 5-15 nanometers. At this time, the intensity of the fluorescent signals of different wavelengths emitted by the four bases is relatively high.
  • the inventor believes that in this embodiment, when the thickness of the first silicon oxide layer is 90 nm, the thickness of the transition metal oxide layer is 5-15 nm, and the thickness of the second silicon oxide layer is 50 nm, the sequencing chip The reflectivity of the film is relatively high, and the fluorescence signal intensity that the camera can capture is relatively high.
  • Embodiment 3 Another method for preparing a "well" structure transition metal oxide sequencing chip on a silicon or quartz wafer
  • this embodiment provides process cross-sectional views of each step of another method for preparing a "well" structure transition metal oxide sequencing chip on a silicon or quartz wafer.
  • the difference between this method and the method in Embodiment 2 is that the method first forms a patterned transition metal oxide layer 313 on the wafer 311 containing the silicon oxide layer 312, while the method in the second method is to form the transition metal oxide layer on the entire wafer.
  • the metal oxide layer is shown in comparison with FIG. 12 and FIG. 6.
  • FIG. 12 is a cross-sectional view of a wafer structure 3-10 containing a patterned transition metal oxide layer 313, and the formation process is similar to that of FIG. 1 in Embodiment 1.
  • FIG. 13 is a cross-section of the wafer structure 3-20 after the silicon oxide layer 321 with the patterned "well” structure 322 is formed on the wafer 3-10 containing the patterned transition metal oxide layer shown in FIG. 12 Figure.
  • the formation process is similar to that shown in Figure 7 in Embodiment 2, in which the “well” structure 322 on the silicon oxide layer corresponds to the patterned “spot”-like transition metal oxide layer 313 one by one, and the final silicon oxide layer will be higher than the transition metal oxide layer 313.
  • a metal oxide layer, and an array of patterned "well” structures are formed on the surface of the wafer, and the bottom of the "well” structure is an exposed transition metal oxide layer 313.
  • FIG. 14 is a cross-sectional view of a plurality of single chips 3-30 separated by dicing grooves 331 formed after the wafer structure 3-20 of FIG. 13 is subjected to a slicing process.
  • the slicing process is similar to that of FIG. 8 in Embodiment 2.
  • FIG. 15 is a cross-sectional view of the sequencing chip 3-40 formed after the single chip 3-30 shown in FIG. 14 is assembled.
  • the assembly process is similar to that of FIG. 9 in Embodiment 2.
  • Fig. 16 is a sequencing chip 3-50 formed after surface functional modification of the sequencing chip 3-40 shown in Fig. 15.
  • the surface functionalization treatment process is similar to that shown in FIG. 10 in Example 2.
  • FIG. 17A is a cross-sectional view of a sequencing chip 3-60A with a DNB array formed after the surface-functionalized sequencing chip 3-50 shown in FIG. 16 is subjected to a DNB loading process.
  • the DNB loading steps are similar to those described in Figure 11A in Example 2.
  • FIG. 17B is another simpler DNB loading method that does not require surface functional modification treatment, which is similar to FIG. 11B in Embodiment 2 above.
  • the transition metal oxide layer is an array-type "spot” structure formed on the first silicon oxide layer, and at the same time a second layer of oxide with an array-type "well” structure is formed on it.
  • the "well” structure of the silicon oxide layer corresponds to the "spots" of the transition metal oxide layer.
  • the simulation results are shown in Figure 17C.
  • the second silicon oxide layer is optimal when the thickness is about 50 nanometers.
  • the thickness of the first silicon oxide layer is 90 nanometers and the thickness of the transition metal oxide layer is 10 to Around 20 nanometers.
  • this embodiment provides cross-sectional views of various steps of a method for preparing a back-illuminated "spot” structure transition metal oxide sequencing chip on a quartz wafer.
  • the method of this embodiment uses a quartz wafer or any other suitable light-transmitting glass wafer as the substrate, and prepares patterned "spots" on the substrate wafer Structure the transition metal oxide patterned layer, and assemble the chip patterned layer downward during the assembly process, and use the excitation light source and camera to excite DNB from the back of the chip (ie through the quartz wafer substrate) and collect fluorescence signal.
  • FIG. 18 is a cross-sectional view of a wafer structure 4-10 in which a patterned transition metal oxide layer is formed on a quartz wafer 411 with a silicon oxide layer 412, where the wafer is a quartz wafer, but any other suitable light-transmitting glass Wafers can be used in the present invention.
  • the process of forming the oxide layer 412 and the patterned transition metal oxide layer 413 is similar to that of FIG. 1 in the first embodiment.
  • FIG. 19 is a cross-sectional view of a plurality of single chips 4-20 separated by dicing grooves formed after the slicing process is performed on the wafer 4-10 of FIG. 18.
  • the slicing process is similar to FIG. 2 in Embodiment 1.
  • FIG. 20 shows a cross-sectional view of the sequencing chip 4-30 formed after the single chip in FIG. 19 is packaged.
  • the patterned layer of the sequencing chip is assembled and attached to a frame 431 containing the liquid inlet and outlet 432 facing downwards, and a fluid channel 433 is formed between the frame and the patterned layer on the chip.
  • the frame 431 can be processed by any suitable material by any suitable processing method, and any suitable adhesive can be used to bond the chip and the frame together. It should be realized that this figure schematically describes the structure that the frame should have, but this figure is not restrictive. Any frame structure that can provide the function of supporting the chip, has liquid inlet and outlet ports, and can form a fluid channel with the patterned layer of the chip All should be regarded as within the scope of the rights of the present invention.
  • FIG. 21 is a cross-sectional view of the sequencing chip 4-40 formed after the surface functional modification treatment of the sequencing chip 4-30 shown in FIG. 20.
  • the steps of functional modification are similar to those shown in Figure 4 in Example 1.
  • FIG. 22A is a cross-sectional view of a sequencing chip 4-50A with a DNB array formed after DNB loading on the functionally modified sequencing chip 4-40 shown in FIG. 21.
  • the DNB loading steps are similar to those shown in Figure 5A in Example 1.
  • This Figure 22A also shows the excitation light source and camera 452, which irradiate DNB from the back of the quartz or glass substrate of the sequencing chip, and collect the fluorescent chip emitted by the DNB labeled with fluorescent markers, so as to perform the analysis on the bases on the DNB. Sequencing.
  • FIG. 22B is another simpler DNB loading method that does not require surface functional modification treatment, which is similar to FIG. 5B in Example 1.
  • the excitation light source and the camera 452 illuminate the DNB from the back of the quartz or glass substrate of the sequencing chip, and collect the fluorescent chip emitted by the DNB labeled with the fluorescent marker, so as to sequence the bases on the DNB.
  • the silicon oxide layer is first formed on the transparent quartz wafer, and then the array of transition metal oxide "spot” structures are formed on the silicon oxide layer, and the DNB sample is loaded on the transition metal oxide "spot” structure on.
  • the camera is placed on the back of the quartz substrate, and the light signal emitted by the DNB needs to pass through the transition metal oxide layer, the silicon oxide layer and the quartz substrate, and then be captured by the camera. Therefore, in this embodiment 4, the fluorescence signal emitted by the DNB is calculated after passing through the transition metal oxide layer, the silicon oxide layer and the quartz substrate of different thickness, and the signal intensity comparison that can be captured by the camera. The simulation result is shown in Figure 22C.
  • the transmittance of the fluorescence emitted by the DNB sample is the largest At this time, the intensity of the fluorescence signal passing through the transition metal oxide layer, the silicon oxide layer and the quartz substrate is the largest, which is close to 100%.
  • Embodiment 5 Method for preparing "well” structure and back-illuminated transition metal oxide sequencing chip on quartz wafer
  • this embodiment proposes cross-sectional views of various steps of a method for preparing a back-illuminated "well" structure transition metal oxide sequencing chip on a quartz wafer.
  • the method of this embodiment uses a quartz wafer or any other suitable light-transmitting glass wafer as a substrate, and prepares a patterned "well" structure transition metal oxide patterned layer on the substrate wafer, and is assembled During the process, the patterned layer of the chip is assembled facing down, and the DNB is excited from the back of the chip (that is, through the quartz wafer substrate) with an excitation light source and a camera, and fluorescent signals are collected.
  • FIG. 23 shows a cross-sectional view of the wafer structure 5-10 after forming a silicon oxide layer and a transition metal oxide layer on a bare wafer.
  • the forming method is similar to that in FIG. 6 in Embodiment 2.
  • FIG. 24 shows a cross-sectional view of the wafer 5-20 after forming a patterned silicon oxide layer with a "well" structure on the wafer 5-10 containing the transition metal oxide layer in FIG. 23.
  • the formation and distribution are similar to those in Fig. 7 in Example 2.
  • FIG. 25 shows a cross-sectional view of a plurality of single chips 5-30 formed after the wafer structure 5-20 of FIG. 24 is subjected to a slicing process.
  • a slicing process similar to that in Fig. 2 in Example 1 is used.
  • FIG. 26 shows a cross-sectional view of the sequencing chip 5-30 formed after the single chip in FIG. 25 is packaged.
  • the patterned layer of the sequencing chip is assembled and attached to a frame 431 containing the liquid inlet and outlet 432 facing downwards, and a fluid channel 433 is formed between the frame and the patterned layer on the chip.
  • the process of FIG. 20 in Embodiment 3 is used.
  • FIG. 27 is a cross-sectional view of the sequencing chip 5-50 formed after performing surface functional modification treatment on the sequencing chip 5-40 shown in FIG. 26.
  • the steps of functional modification are similar to those shown in Figure 4 in Example 1.
  • FIG. 28A is a cross-sectional view of a sequencing chip 5-60A with a DNB array formed after DNB loading on the functionally modified sequencing chip 5-50 shown in FIG. 27.
  • the DNB loading steps are similar to those shown in Figure 5A in Example 1.
  • This figure also shows the excitation light source and camera 562, which irradiate DNB from the back of the quartz or glass substrate of the sequencing chip, and collect the fluorescent chip emitted by the DNB labeled with fluorescent markers, thereby sequencing the bases on the DNB .
  • FIG. 28B is another simpler DNB loading method that does not require surface functional modification treatment, which is similar to FIG. 5B in Embodiment 1.
  • the excitation light source and the camera 562 irradiate the DNB from the back of the quartz or glass substrate of the sequencing chip, and collect the fluorescent signal emitted by the DNB labeled with the fluorescent marker, so as to sequence the bases on the DNB.
  • a first silicon oxide layer is formed on the quartz wafer first, and then a transition metal oxide layer is formed on the first silicon oxide layer, and then a transition metal oxide layer is formed on the transition metal oxide layer.
  • the second silicon oxide layer of the array type "well" structure is also loaded on the transition metal oxide layer in the "well” structure, and the light signal emitted by it passes through the transition metal oxide layer, the first silicon oxide layer and the quartz substrate, and is placed Captured by the camera on the back of the quartz substrate.
  • the thickness of the first silicon oxide layer and the thickness of the transition metal oxide layer are determined, when the thickness of the second silicon oxide layer increases, the intensity of the fluorescent signal passing through the thin film layer does not increase with the thickness of the second silicon oxide layer. But monotonous increase or monotonous decrease, but show different fluorescence signal intensity changing trends under different wavelengths. In this case, when the thickness of the second silicon oxide layer is 100 to 200 nanometers, it is ensured that the "well" structure has a suitable depth to load DNB, and the camera can collect fluorescent signals with relatively high intensity.
  • Example 6 Another method for preparing a "well" structure, back-illuminated transition metal oxide sequencing chip on a quartz wafer
  • this embodiment presents cross-sectional views of various steps of a method for preparing a back-illuminated "well" structure transition metal oxide sequencing chip on a quartz wafer.
  • the difference between this method and the above method 5 is that the method first forms a patterned transition metal oxide layer 613 on the wafer 611 containing the silicon oxide layer 612, while the method of embodiment 5 is formed on the entire wafer.
  • the transition metal oxide layer is shown in comparison with FIG. 29 and FIG. 23.
  • FIG. 29 is a cross-sectional view of a wafer structure 6-10 containing a patterned transition metal oxide layer 613, and the formation process is similar to that of FIG. 1 described above.
  • FIG. 30 is a cross-section of the wafer junction 6-20 after forming a silicon oxide layer 621 with a patterned "well” structure 622 on the wafer 6-10 containing the patterned transition metal oxide layer shown in FIG. 29 Figure.
  • the formation process is similar to that shown in Figure 7 in Embodiment 2, in which the "well" structure 622 on the silicon oxide layer corresponds to the patterned "spot”-like transition metal oxide layer 613 one by one, and the final silicon oxide layer will be higher than the transition metal oxide layer.
  • a metal oxide layer, and an array of patterned "well” structures are formed on the surface of the wafer, and the bottom of the "well” structure is an exposed transition metal oxide layer 613.
  • FIG. 31 is a cross-sectional view of a plurality of single chips 6-30 separated by dicing grooves 631 formed after the wafer structure 6-20 of FIG. 30 is subjected to a slicing process.
  • the slicing process is similar to that of FIG. 8 in Embodiment 2.
  • FIG. 32 shows a cross-sectional view of the sequencing chip 6-40 formed after the single chip in FIG. 31 is packaged. The process of this figure is similar to that of FIG. 26 in Embodiment 5.
  • FIG. 33 is a cross-sectional view of the sequencing chip 6-50 formed after performing surface functional modification treatment on the sequencing chip 6-40 shown in FIG. 32.
  • the steps of functional modification are similar to those shown in Figure 4 in Example 1.
  • FIG. 34A is a cross-sectional view of a sequencing chip 6-60A with a DNB array formed after loading the functionally modified sequencing chip 6-50 shown in FIG. 33 with DNB.
  • the DNB loading steps are similar to those shown in Figure 5A in Example 1.
  • This figure also shows the excitation light source and camera 662, which irradiate DNB from the back of the quartz or glass substrate of the sequencing chip, and collect the fluorescent chip emitted by the DNB labeled with a fluorescent marker, so as to sequence the bases on the DNB .
  • FIG. 34B is another simpler DNB loading method that does not require surface functional modification treatment, which is similar to FIG. 5B in Embodiment 1.
  • the excitation light source and the camera 662 illuminate the DNB from the back of the quartz or glass substrate of the sequencing chip, and collect the fluorescent chip emitted by the DNB labeled with the fluorescent marker, so as to sequence the bases on the DNB.
  • a first silicon oxide layer is formed on the quartz wafer first, and then a transition metal oxide layer with an arrayed "spot” structure is formed on the first silicon oxide layer, and then the transition metal oxide layer Above the metal oxide layer is formed a second silicon oxide layer with an array of "wells” structure, where the "well” structure of the second silicon oxide layer corresponds to the "spot” structure of the transition metal oxide layer, and the transition metal oxide The “spot” structure is at the bottom of the “well” structure of the second silicon oxide layer.
  • the DNB sample is also loaded on the transition metal oxide layer in the "well" structure, and the light signal emitted by it passes through the transition metal oxide layer, the first silicon oxide layer and the quartz substrate, and is placed Captured by the camera on the back of the quartz substrate.
  • the influence of the thickness of the second silicon oxide layer on the intensity of the fluorescent signal is simulated. .
  • the simulation result is shown in Figure 34C.
  • the fluorescence signal intensity of the structure with the transition metal oxide layer of 10 nanometers is also higher than that of 20 nanometers. Structure.
  • the thickness of the first silicon oxide layer and the thickness of the transition metal oxide layer are determined, when the thickness of the second silicon oxide layer increases, the intensity of the fluorescent signal passing through the thin film layer also does not increase with the thickness of the second silicon oxide layer.
  • the thickness of the second silicon oxide layer is 100 to 200 nanometers, it is ensured that the "well" structure has a suitable depth to load DNB, and the camera can collect fluorescent signals with relatively high intensity.
  • this embodiment proposes a method for preparing a transition metal oxide sequencing chip with an array type "spot” structure or a "well” structure on a CMOS wafer.
  • the difference between this method and the above method is that the above methods all use an external excitation light source and camera equipment, and the DNB labeled with a fluorescent marker is irradiated by the specific wavelength and energy excitation light emitted by the external excitation light source, so that the DNB emits a specific The light of wavelength and energy can be sequenced by collecting the light signal from DNB by the camera, but this method does not require external excitation light source and camera equipment.
  • the CMOS wafer used in this method is a CMOS wafer with image sensor function.
  • Each wafer can have hundreds to thousands of image sensor chips, and each image sensor chip can have millions to tens of millions of pixels.
  • the image sensor chip can sense external light signals of different intensities and convert them into corresponding electrical signals.
  • the DNB labeled with fluorescent markers is selectively loaded on the photodiode array on the image sensor chip to form a DNB array corresponding to the photodiode array one-to-one, and biological or chemical methods are used to make the DNB emit light (without external excitation light source) ), the DNB array loaded on the image sensor chip can be sequenced by identifying the light signal values of the image sensor chip at different times and at different pixels.
  • CMOS image sensor wafer has a photosensitive layer 73, an interconnection layer 74, a substrate layer 75, and a dielectric film layer 717 on the photosensitive layer 73.
  • the material of this layer is usually a stack of hafnium dioxide and tantalum pentoxide films.
  • a silicon oxide layer 718 is usually a stack of hafnium dioxide and tantalum pentoxide films.
  • the photosensitive layer 73 includes a photosensitive portion 716 formed in a semiconductor material 715, and the photosensitive portion 716 may be a photodiode.
  • the semiconductor material layer 715 may be made of any suitable material, such as silicon, III-V materials on silicon, graphene on silicon, silicon on insulator, and combinations thereof. Although the present invention is described herein for the photodiode 716, it is worth noting that any suitable photosensitive structure can be applied in the present invention.
  • the photodiode 716 can convert the measured light signal into a current signal.
  • the photodiode 716 may include the source and drain of a MOS (Metal Oxide Semiconductor) transistor, which can transmit current to other components, such as to another MOS transistor.
  • MOS Metal Oxide Semiconductor
  • the CMOS image sensor 10 may also include a dielectric layer. It is worth noting that the dielectric layer may include any suitable electrical insulating material.
  • the interconnection layer 74 includes metal wiring 714 formed in the dielectric layer 713. The metal wiring 714 can be used for internal interconnection of integrated circuit materials and also for electrical connection to the outside.
  • the substrate layer 75 includes a silicon substrate 711 and a CMOS processing circuit layer 712, and the CMOS processing circuit layer may include CMOS circuits required for sequencing operations.
  • the CMOS processing circuit layer 712 may include circuits for image processing, signal processing, control functions for realizing sequencing operations, and external communication.
  • the CMOS processing circuit 712 processes the photosensitive signal sensed by the photosensitive layer 73 into an electrical signal, and transmits the electrical signal to an external device through the interconnected silicon via 720 and the pad 719.
  • CMOS image sensor chip is only schematically described in the present invention, but this description is not restrictive, and image sensor chips of any structure can be used in the present invention.
  • FIG. 36A is a cross-sectional view of the CMOS wafer structure 7-20A after a patterned transition metal oxide layer with a "spot" structure is formed on the CMOS image sensor wafer 7-10 shown in FIG. 35.
  • the process steps in this figure are similar to those in FIG. 1 in Embodiment 1, except that the wafer in this figure is a CMOS wafer, and the transition metal oxide regions 721 of the "spot" structure are distributed above the photodiode array 716 .
  • FIG. 36B is a cross-sectional view of the CMOS wafer structure 7-20B after a patterned transition metal oxide layer with a "well” structure is formed on the CMOS image sensor wafer 7-10 shown in FIG. 35.
  • the process steps in this figure are similar to those in Figure 6 and Figure 7 in Embodiment 2, except that the wafer in this figure is a CMOS wafer, and the transition metal oxide region 724 of the "well" structure is distributed in the photodiode Above the array 716.
  • FIG. 36C is a cross-sectional view of the CMOS wafer structure 7-20C after forming another patterned transition metal oxide layer of the "well" structure on the CMOS image sensor wafer 7-10 shown in FIG. 35.
  • the process steps in FIG. 36C are similar to those in FIG. 12 and FIG. 13 in Embodiment 3. The only difference is that the wafer in this figure is a CMOS wafer, and the transition metal oxide region 727 of the "well" structure is distributed in the photodiode Above the array 716.
  • FIG. 37 is a CMOS wafer 7-20A with a patterned transition metal oxide layer formed in FIG. 36A (because the subsequent processes in FIG. 36A, FIG. 36B, and FIG. 36C are the same, the subsequent content of the invention only uses the pattern shown in FIG. 36A (Description of the wafer structure) is a cross-sectional view of a plurality of single chips 7-30 separated by the dicing groove 731 formed after the slicing process. The slicing process is similar to that in FIG. 2 in Embodiment 1.
  • FIG. 38 is a cross-sectional view of the chip structure 7-40 formed after the chip shown in FIG. 37 is die-mounted and wire-bonded.
  • FIG. 38 shows the first two steps in the sequencing chip assembly process.
  • a single chip is attached to the packaging substrate 741 by glue or adhesive.
  • the packaging substrate 741 may be a substrate in the form of an LGA package.
  • the front of the substrate has a pad 742 for electrical connection with the chip, and the back of the substrate has a contact 743 for electrical connection with an external device.
  • the pad 742 is connected to the contact. 743 has a one-to-one correspondence through the wiring inside the substrate.
  • the pad 719 on the chip and the pad 742 on the substrate are electrically connected by wire bonding, so that the electrical signal from the chip is transmitted out through the wire, but on the substrate, and then through the substrate and the external device The interface is transmitted to the external device.
  • the substrate in this description includes but is not limited to LGA form, any suitable packaging substrate form can be applied to the present invention, and the glue or adhesive used in the chip mounting process should also include but not Limited to the glue or adhesive used in any packaging process, the metal connections in the wire bonding process also include but are not limited to gold wires, aluminum wires, etc.
  • FIG. 39 is a cross-sectional view of the sequencing chip 7-50 formed after the chip structure 7-40 shown in FIG. 38 is attached to the cover structure.
  • a cover structure 751 including a fluid channel 753, a liquid inlet and an outlet 752, and a supporting structure is attached to the CMOS image sensor chip and substrate by glue or adhesive to form a sequencing chip.
  • the fluid channel 753 is formed on the patterned transition metal oxide layer, and the liquid is confined within a certain space range, so that the liquid does not come into contact with other energized areas such as pads and leads outside the fluid channel.
  • cover 751 can be made of any suitable material (including but not limited to PC, PEI, PEEK, PMMA, etc.) of any color and processed by any suitable processing method (including but not limited to CNC, open mold injection, 3D printing, etc.) Become. And those skilled in the art should also realize that the physical structure of the substrate 741 and the cover 751 should include but are not limited to those shown in this figure, and any physical structure that can realize the functions of this figure should be included in the present invention.
  • FIG. 40 is a cross-sectional view of a sequencing chip 7-60 formed after the sequencing chip shown in FIG. 39 is subjected to surface functional modification treatment.
  • the functionalized treatment process in this figure is similar to that in FIG. 4 in Embodiment 1.
  • FIG. 41A is a cross-sectional view of a sequencing chip 7-70A with a DNB array formed after the functionalized sequencing chip 7-60 described in FIG. 40 is loaded with DNB.
  • the DNB loading process shown in this figure is similar to that shown in Figure 5 in Example 1, except that the DNB labeled with a fluorescent marker in this method emits light through biological or chemical methods, without the need for an external excitation light source Therefore, the light emitted by the DNB array through biological or chemical methods is captured by the photodiode array on the image sensor and output as an electrical signal by the processing circuit. According to the light emission of different pixels (photodiodes) in the DNB array at different times, the base arrangement of DNB can be identified.
  • FIG 41B shows another simpler DNB loading method that does not require surface functionalization. This loading method is shown in Figure 5B above, and the luminescence signal of DNB is converted into base arrangement information on DNB in the manner described in Figure 41A above.
  • the transition metal oxide layer and the second silicon oxide layer form three kinds of "spots” or “spots” or “spots” on the CMOS wafer containing the photosensitive structure with the first silicon oxide layer.
  • the well” structure includes: 1. A transition metal oxide layer with an array “spot” structure is formed on the first silicon oxide layer, and DNB is loaded on the "spot” structure of the transition metal oxide layer; 2. In the first A transition metal oxide film is formed on the silicon oxide layer, and a second silicon oxide layer with an array “well” structure is formed on the transition metal oxide film. DNB is loaded on the second silicon oxide layer "well” On the transition metal oxide layer at the bottom of the structure; 3.
  • a transition metal oxide layer with an array type "spot” structure is formed, and then an array type "well” is formed on the transition metal oxide layer
  • DNB is loaded on the transition metal oxide “spot” structure at the bottom of the silicon oxide layer of the “well” structure.
  • the light signal emitted by DNB needs to pass through the transition metal oxide, the first silicon oxide layer and the ARC layer (anti-reflection layer, usually pentoxide) on the CMOS wafer.
  • Two tantalum), PIN layer (usually hafnium dioxide) are finally collected by the photosensitive structure on the CMOS wafer, so the signal intensity that the light emitted by the DNB can be collected by the photosensitive structure after passing through these layers of film is simulated .
  • the thickness of the PIN layer and the ARC layer is determined by the process of the CMOS wafer, and is usually a certain value.
  • the thickness of the PIN layer is 6 nanometers and the thickness of the ARC layer is 50 nanometers. Therefore, in the above-mentioned three kinds of "spot" or "well” structures, the influence of the changes in the thickness of the first silicon oxide layer, the transition metal oxide layer and the second silicon oxide layer on the intensity of the fluorescent signal is simulated.
  • the first case described in this embodiment is simulated.
  • the relationship between the intensity of the fluorescent signal and the thickness of the first oxide layer is simulated.
  • the simulation result is shown in Figure 41C.
  • the intensity of the light signal collected by the photosensitive structure in the CMOS wafer decreases monotonically with the increase of the thickness of the first oxide layer.
  • the thickness of the oxide layer can be selected as 150nm.
  • the thickness of the first silicon oxide layer is 150 nanometers
  • the relationship between the thickness of the transition metal oxide layer of the array type "spot" structure on the first silicon oxide layer and the intensity of the fluorescent signal is simulated.
  • the simulation result is shown in Fig. 41D.
  • the light signal intensity collected by the photosensitive structure in the CMOS wafer fluctuates with the thickness of the transition metal oxide layer. From the process point of view, the optimized thickness can be 40-50nm.
  • Example 7 Then, the second case in Example 7 was simulated.
  • the thickness of the first silicon oxide layer was 150 nanometers, another transition metal oxide film was formed on the first silicon oxide layer.
  • the thickness of the transition metal oxide layer film is simulated by the relationship between the thickness and the intensity of the fluorescent signal. The simulation result is shown in FIG. 41E.
  • the intensity of the fluorescence signal fluctuates as the thickness of the transition metal oxide layer increases. When the thickness is 10-20 nm, the intensity of the fluorescence signal is the highest.
  • the relationship between the thickness of the second layer of silicon oxide and the intensity of the fluorescent signal when the second layer of silicon oxide with a "well" structure is formed on this basis is simulated.
  • the simulation result is shown in FIG. 41F.
  • the thickness of the transition metal oxide layer is determined, the correlation between the intensity of the optical signal collected by this structure and the thickness of the second oxide layer is negligible.
  • the thickness of the second oxide layer is too large, making the surface structure too deep, which can easily lead to fluid dead zones and affect the quality of sequencing.
  • a moderate thickness of the second oxide layer can be more effective to make the DNA groups to be tested fall in the effective area, and the thickness of the second oxide layer can be selected as 50-100nm.
  • a new sequencing chip packaging method is proposed.
  • the sequencing chip in this packaging method can be reused after a special processing process, which greatly reduces the cost of the sequencing chip.
  • This array patterned structure can be shown in Figure 1, Figure 7, and Figure in the above-mentioned Embodiments 1 to 3.
  • the structure in FIG. 1 in Embodiment 1 is used as an example to describe the manufacturing process of this reusable sequencing chip.
  • the present invention includes The other sequencing chip structures of the company can also be prepared into reusable sequencing chips using the same packaging process.
  • FIG. 42 is a cross-sectional view of a wafer structure 8-10 of a transition metal oxide layer with an array-type "spot" structure, which is the same as FIG. 1 in Embodiment 1, in which a silicon oxide layer 812 is formed on the semiconductor crystal. On the round substrate 811, a transition metal oxide layer 813 with a “spot” structure is formed on the silicon oxide layer 812. The process and material requirements of each step are the same as those described in FIG. 1 in Embodiment 1.
  • FIG. 43 is a cross-sectional view of the wafer structure 8-20 after multiple single chips 81 and 82 are formed after the wafer structure 8-10 shown in FIG. 42 is subjected to a slicing process, where the slicing process is the same as that in Embodiment 1. Similar in Figure 2.
  • FIG. 44 is a cross-sectional view of the reusable sequencing chip 8-30 formed by assembling the single chip 81 or 82 formed in FIG. 43 and a handle structure 831.
  • the function of the handle structure 831 is that by fixing the handle structure and a single chip to form a sequencing chip, the handle structure can be used to perform operations such as grabbing and transferring the sequencing chip to perform DNB loading and sequencing.
  • Fig. 44 only schematically shows an "L"-shaped armrest structure.
  • the human body skilled in the art should realize that any armrest structure that can achieve the above functions is included in the present invention, and the present invention does not limit the armrest structure.
  • the quantity can be packaged with multiple armrest structures and a single chip.
  • the material of the armrest structure can be made of plastic or metal compatible with DNB loading and sequencing reagents, low cost, easy to process and not easy to wear and tear, such as including but not limited to polyether ether ketone, polycarbonate, polymethyl methacrylate, etc. Polymer plastics, or metals such as aluminum alloy and stainless steel. A solid or liquid adhesive can be used to bond the single chip and the handrail structure together. Any adhesive compatible with DNB loading and sequencing reagents can be used in this patent.
  • the assembled sequencing chip shown in Figure 44 is immersed in a container 841 containing reagent 842, where reagent 842 can be any reagent during chip surface modification, DNB loading, and sequencing.
  • reagent 842 can be any reagent during chip surface modification, DNB loading, and sequencing.
  • the sequencing chip can be switched between different containers and reagents by grabbing the handle structure of the sequencing chip to perform different operations. Reaction.
  • the DNB binding site area (the "spot" structure transition metal oxide layer) on the sequencing chip is completely loaded with DNB.
  • An excitation light source and camera 843 can be used to collect the different wavelengths and wavelengths emitted by DNB. Energy of the light signal, thereby performing sequencing operations.
  • the sequencing chip with the packaging structure can be processed and reused.
  • the specific treatment method is as follows:
  • the sequencing chip after sequencing is preprocessed, and the handle structure is removed, so that the entire chip is completely exposed. Then immerse the chip in SC1 washing solution (Slide Clean 1, 50mM potassium hydroxide solution containing Triton) for 10 minutes, then take it out, use deionized water to repeatedly clean the surface of the chip more than 3 times, and place the chip in a nitrogen stream to dry completely .
  • SC1 washing solution Slide Clean 1, 50mM potassium hydroxide solution containing Triton
  • the SC1 washing solution mentioned above can also be replaced by SC2 washing solution.
  • the specific operation steps are: remove the handle structure of the sequencing chip after sequencing, and place it in the SC2 washing solution (Slide Clean 2, using ammonia and hydrogen peroxide to a certain amount) Proportional mixing). Warm the washing solution to 80 degrees for 5 minutes, then take out the chip, use deionized water to repeatedly clean the chip 3 times, and place the chip in a nitrogen stream to dry completely.
  • the above-mentioned washing solution cleaning method can also be replaced by plasma drying treatment.
  • the sequencing chip after sequencing is placed in an argon plasma atmosphere for 30 minutes, and then deionized water is used to clean the dust to remove dust, and the chip is placed in a nitrogen gas flow It is completely dry.
  • Example 9 The surface of the chip was not modified, and the microarray was formed by changing the loading conditions
  • the surface of silicon dioxide is used to simulate the non-binding site area, and the surface of titanium dioxide and tantalum pentoxide is used to simulate the binding site area.
  • a plasma cleaner was used to clean the three surfaces, and then ethanol was used for further cleaning.
  • Use optimized DNB solution change pH and surfactant content (160BP, 10ng/uL) to load DNB on the surface of the chip. After DNB is loaded, use cy3 dye to fluorescently label DNB, and then use a fluorescence microscope to mark the chip The surface is analyzed, and the result is shown in Figure 46.
  • the bright spot is the loaded DNB, the black line is the area where the non-functional area is more concentrated, and the density of the functional area is low (do not adsorb DNB).
  • This chip is made into a sequencing chip according to the aforementioned assembly method, and the results of computer sequencing on the Zebra platform are shown in Figure 47.
  • the loading success rate (GRR value) of DNB loading using the new transition metal oxide array chip is higher than the current one. Chips manufactured using existing processes.
  • the silicon crystal chip with a transition metal oxide lattice is placed in a 10mM aminoethylphosphonic acid solution after being cleaned with a plasma cleaning machine and ethanol, soaked for 24 hours and then taken out, and the surface is cleaned with ethanol and water.
  • X-ray photoelectron spectrometer to analyze the elements of the three surfaces, the results showed that the silicon dioxide surface before and after amination did not contain phosphorus, while the phosphorus atom concentration on the surface of titanium dioxide and tantalum pentoxide was different from that of amino The 0 before conversion rose to 2%.
  • DNB solution 160BP, 10ng/uL
  • the silicon crystal chip with the transition metal oxide lattice is prepared by oxidizing the surface of the silicon dioxide element crystal used in the factory, and then using ALD plating the transition metal oxide lattice.
  • Example 11 Effect detection of further modification of non-functional regions using copolymers containing polyethylene glycol
  • This embodiment adopts a specially-made chip.
  • the size of the transition metal oxide area on the chip is 200 microns and the interval is 500 microns.
  • PEI-PEG polyethyleneimine-polyethylene glycol
  • DNB solution 160BP, 10ng/uL
  • DNB is fluorescently labeled with cy3 dye
  • the chip surface is analyzed using a fluorescence microscope. The results are shown in Figure 49. Show. It can be seen in Figure 49 that the non-specific adsorption on the surface is further reduced after the non-binding area of silica is treated with the copolymer.
  • copolymers containing polyethylene glycol can further reduce the adsorption of DNB and impurities on the non-functional areas of the chip surface.
  • Example 12 Use of silane coupling agent containing polyethylene glycol to detect the effect of further modification of non-functional regions
  • the silicon crystal chip with transition metal oxide lattice is placed in a silane coupling agent solution modified by alendronic acid and polyethylene glycol after being cleaned by a plasma cleaner and ethanol, and taken out after a period of reaction. Wash with ethanol and water. Then use the DNB solution (160BP, 10ng/uL) consistent with sequencing to load DNB on the chip surface. After DNB loading is completed, DNB is fluorescently labeled with cy3 dye, and then the chip surface is analyzed using a fluorescence microscope, as shown in Figure 50 .
  • silane coupling agent containing polyethylene glycol can further reduce the adsorption of DNB and impurities on the non-functional area of the silica surface.

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Abstract

一种芯片基质、测序芯片及其制备方法，该芯片基质包括：晶圆层(111)，所述晶圆层(111)上具有均匀分布的切割线；第一氧化硅层(112)，所述第一氧化硅层(112)由氧化硅构成，形成在所述晶圆层(111)的上表面；过渡金属氧化物层(113)，所述过渡金属氧化物层(113)由过渡金属氧化物构成，形成在所述第一氧化硅层(112)的上表面。该芯片基质具有耐高温、耐高湿度等苛刻环境的特点，同时，通过改变含有待测序序列溶液的pH及表面活性剂等成分，可以使得芯片基质表面功能区特异性吸附待测序序列。

Description

测序芯片及其制备方法
优先权信息
无
技术领域
本发明涉及生物技术领域，具体地，本发明涉及测序芯片及其制备方法。
背景技术
微阵列测序芯片是实现高通量测序的必备条件之一，目前使用的DNA纳米球(DNB，DNA Nano Ball)测序技术需要将DNB固定在测序芯片上进行下一步的测序生化反应。以目前使用的测序芯片为例，每张芯片表面带有近2亿个DNB结合位点。为了将DNB稳定地固定在结合位点上，测序芯片表面需进行氨基化处理。除此之外芯片表面非结合位点以外的区域需进行其他处理尽可能减少非特异性吸附，降低背景，提高测序质量。因此高效、低成本地制备带有微阵列的测序芯片是实现高质量测序的基础工作之一。
目前测序芯片的制作步骤主要包括：首先借助半导体工艺在硅晶圆上制备包含纳米阵列的图案化光刻胶层，该图案化层可包含多个相同的单元结构，每个单元可形成一张测序芯片；然后将带有图案化层的晶圆进行化学气相沉积处理，在晶圆功能区域形成氨基化层；然后在经过组装工艺，将晶圆分割成单颗芯片并组装成可进行测试的测序芯片。
其中在硅晶圆上形成图案化光刻胶层的工艺包括：首先，提供一张硅晶圆，并在硅晶圆表面形成一层氧化硅层。然后在使用化学气相淀积(CVD)或旋凃方法在氧化硅层上形成一层HMDS(Hexamethyldisiloxane，六甲基二硅胺)层，并通过标准光刻、显影、氧等离子体刻蚀工艺形成图案化的光刻胶层，其中光刻胶层中被显影掉并经过氧等离子体处理的部分将暴露出底层的氧化硅层。该图案化光刻胶层包括多个含相同纳米阵列结构的单元，每个单元可形成一个测序芯片。
其中在功能区形成氨基化层的工艺为：将形成了图案化光刻胶层的硅晶圆通过化学气相沉积的方法进行氨基化处理，在无光刻胶并暴露出氧化硅的区域，氨基化层形成在氧化硅层上，而在其他光刻胶覆盖的区域，氨基化层形成在光刻胶层上。
其中组装工艺包括：将进行过氨基化处理的晶圆涂覆第二层起保护作用的光刻胶，并采用晶圆切割工艺切割晶圆形成多个单颗芯片，这种单颗芯片在经过光刻胶去除工艺后，表面将形成具有氨基化区域和HMDS区域交替存在的功能化阵列图案，再通过胶水或其他粘合剂将框架、盖玻片及芯片组装成含流体通道及进出液口的测序芯片，流体通道形成在盖玻片及硅芯片之间并被胶水或粘合剂分隔开，进出液口可在框架或盖玻片上。
在形成测序芯片之后，将待测DNB样品通过进出液口注入流体通道内，并接触到硅芯片上的氨基化区域和HMDS区域交替排布的表面功能化阵列，DNB将选择性的被氨基化区域吸附，而被HMDS区域排斥，因此在表面形成阵列排布的DNB阵列。在采用光学方法采集DNB阵列发出的信号，则可识别出DNB上碱基的排布，从而进行测序应用。
此种方法制备的测序芯片主要通过硅芯片表面的氨基化区域和HMDS区域选择性的吸附DNB来进行测序，但氨基化区域和HMDS区域都为氧化硅表面上的单分子层，在将硅芯片组装成测序芯片的过程中或测序芯片使用过程中，表面单分子层很容易被物理、化学接触损坏(如表面刮擦、高温或其与他可与其反应的化学试剂接触)，从而影响测序芯片的性能，甚至使芯片无法使用。这不仅影响了使用测序芯片进行测序应用时产出有效数据的效率，还使测序芯片制备的成品率低，降低了测序芯片的产出，间接提高了测序芯片的成本。
因而，开发高效、低成本、环境友好型的测序芯片迫在眉睫。
发明内容
基于上述现有测序芯片存在的问题，本发明提出了更稳定可靠、性能更好的新型测序芯片结构及制 备方法。本发明不采用表面的单分子层来形成DNB阵列，而是采用在硅晶圆表面宏观存在一种金属氧化物区域和氧化硅区域交替存在图案化阵列(井字形或斑点形)来选择性的吸附DNB，并形成可用于测序的DNB阵列。本发明所述的测序芯片同样用半导体工艺制备，首先在一张晶圆上形成具有过渡金属氧化物区域和氧化硅区域交替存在的图案化阵列，然后利用切片工艺将晶圆切割成多张单颗芯片，并通过组装工艺将单颗芯片组装成一张测序芯片。利用过渡金属氧化物和氧化硅表面性质的不同可实现芯片表面DNB结合位点区域(即功能区，过渡金属氧化物区域)与非结合位点区域(即非功能区，氧化硅)的选择性修饰，同时，为了进一步提高芯片表面功能区(即DNB的结合位点区域)对DNB的特异性结合，发明人还首次提出了在过渡金属氧化物上特异性地引入氨基基团，以进一步提高芯片表面功能区对DNB的特异性结合，同时发明人还首次提出了利用具有较好生物兼容性的共聚物(如聚乙二醇类化合物)对芯片表面非功能区(即DNB非结合位点区域)进行修饰，来降低芯片表面非功能区对DNB的结合，更进一步提高芯片表面功能区对DNB的特异性结合，进而提高测序质量。本发明的测序芯片的优点为硅晶圆表面为金属氧化物区域、氧化硅区域交替存在形成的阵列，相比于由单分子层形成的阵列更稳定、可靠，可提高测序芯片数据产出效率，提高测序芯片的产出，从而降低成本。并且本发明还根据光学仿真结果提出了该种测序芯片的较优结构尺寸，该较优的结构尺寸可以使待测样品发出的信号得到增强，从而提升测序芯片的性能。
在本发明的第一方面，本发明提出了一种芯片基质。根据本发明的实施例，所述芯片基质包括：晶圆层，所述晶圆层上具有均匀分布的切割线；第一氧化硅层，所述第一氧化硅层由氧化硅构成，形成在所述晶圆层的上表面；过渡金属氧化物层，所述过渡金属氧化物层由过渡金属氧化物构成，形成在所述第一氧化硅层的上表面。
如无特别说明，本发明所述的“芯片基质”是指可用于分割成芯片颗粒的测序芯片单元，例如，利用根据本发明实施例的芯片基质可分割成芯片颗粒，进而所述芯片颗粒可进一步组合成测序芯片主体，所述测序芯片主体与具有进出液口的支撑框架形成测序芯片。
根据本发明实施例的芯片基质由于具有由过渡金属氧化物构成的过渡金属氧化物层和由氧化硅构成的氧化硅层，而过渡金属氧化物与氧化硅具有不同的性质，因此，可以通过改变含有待测序序列，尤其是DNB的溶液的pH及表面活性剂成分等，实现待测序序列选择性的吸附在根据本发明实施例的芯片基质的过渡金属氧化物区域上，此时，根据本发明实施例的芯片基质可划分为包括两个区域，即待测序序列结合位点区域(即功能区)，和测序序列非结合位点区域(即非功能区)，可以理解的是，此时测序基质上的过渡金属氧化物层就构成了特异性结合待测序序列的功能区，而不能结合测序序列的氧化硅层就构成了非功能区。此外，还可以对测序序列结合位点区域和非结合位点区域进行选择性修饰，进一步增强待测序列在过渡金属氧化物区域的选择性吸附能力。根据本发明实施例的芯片基质具有耐高温、耐高湿度等苛刻环境的特点。
在本发明的第二方面，本发明提出了一种测序芯片。根据本发明的实施例，所述测序芯片包括芯片主体，所述芯片主体包括数个芯片颗粒，所述芯片颗粒是将前面所述的芯片基质沿着晶圆层的切割线进行切割后获得的。发明人发现，仅通过改变含有待测序序列，尤其是DNB的溶液的pH及表面活性剂成分等，就可实现待测序序列的选择性的吸附在过渡金属氧化物层上。根据本发明实施例的测序芯片更稳定，测序结果更可靠，能显著提高测序芯片数据产出效率，提高测序芯片的产出，显著降低测序成本。
在本发明的第三方面，本发明提出了一种制备前面所述的芯片基质的方法。根据本发明的实施例，所述方法包括：对晶圆层进行表面修饰，所述表面修饰包括利用过渡金属氧化物对所述晶圆层的表面进行处理，以便形成过渡金属氧化物层，所述晶圆层的上表面具有第一氧化硅层，氧化硅层由氧化硅构成，所述过渡金属层形成在所述第一氧化硅层的上表面，所述晶圆层上具有均匀分布的切割线。根据本发明实施例的方法操作简单，环境友好。
在本发明的第四方面，本发明提出了一种制备测序芯片的方法。根据本发明的实施例，所述方法包括：将芯片颗粒进行组装，所述芯片颗粒是将芯片基质沿着晶圆层的切割线进行切割后获得的，所述芯片基质如前面所述限定的或依据前面所述的方法获得。根据本发明实施例的方法操作简单，制备的测序芯片的成品率高。
在本发明的第五方面，本发明提出了一种测序方法。根据本发明的实施例，所述方法包括：利用测 序芯片进行测序，所述测序芯片如前面所限定的或依据前面所述的方法制备的。根据本发明实施例的方法，测序的结果更加准确，成本更加低廉。
附图说明
图1-5为本发明的一方面所述的具有阵列式“斑点”结构的图案化过渡金属氧化物层测序芯片制备过程的各工艺过程截面图，其中，
图1为根据本发明实施例的在表面具有氧化硅层的晶圆上形成一层具有阵列式“斑点”结构的过渡金属氧化物层薄膜的晶圆结构1-10的截面图；
图2为根据本发明实施例的将图1中的晶圆结构1-10进行切片工艺之后形成的多个单颗芯片1-20的截面图；
图3为根据本发明实施例的将图2中的芯片进行组装工艺之后形成的测序芯片1-30的截面图；
图4为根据本发明实施例的将图3中的测序芯片1-30进行表面功能化修饰之后的测序芯片1-40；
图5A为根据本发明实施例的对图4中进行过表面修饰的测序芯片1-40进行DNB装载之后形成的包含DNB阵列的测序芯片1-50A的截面图；
图5B为根据本发明实施例的一种更简洁的、不需要进行表面修饰即可在测序芯片中形成DNB阵列的测序芯片1-50B的截面图；
图5C为根据本发明实施例的荧光信号强度与氧化硅层厚度的关系；
图5D为根据本发明实施例的荧光信号强度与过渡金属氧化物厚度的关系(‘斑点’结构)；
图6-11为本发明的另一方面所述的具有阵列式“井”结构的图案化过渡金属氧化物层测序芯片制备过程的各工艺过程截面图，其中，
图6为根据本发明实施例的在表面具有氧化硅层的晶圆上形成一层过渡金属氧化物层薄膜的晶圆结构2-10的截面图；
图7为在根据本发明实施例的图6所示的具有过渡金属氧化物层薄膜的晶圆结构2-10上形成一层具有阵列式“井”结构的氧化硅层之后形成的晶圆2-20的截面图；
图8为根据本发明实施例的将图7所示的具有阵列式“井”结构的晶圆结构2-20进行切片工艺之后形成的多个单颗芯片2-30的截面图；
图9为根据本发明实施例的将图8中的单颗芯片进行组装工艺之后形成的测序芯片2-40的截面图；
图10为根据本发明实施例的将图9所示的测序芯片进行表面功能化修饰处理之后形成的测序芯片2-50的截面图；
图11A为根据本发明实施例的对图10中所示的进行过表面功能化修饰处理的测序芯片2-50进行DNB装载之后形成的具有DNB阵列的测序芯片2-60A的截面图；
图11B为根据本发明实施例的一种更简洁的、不需要进行表面修饰即可在测序芯片中形成DNB阵列的测序芯片2-60B的截面图；
图11C为根据本发明实施例的基于硅衬底的不同“井”结构的荧光信号与第二层氧化层的关系；
图11D为根据本发明实施例的荧光信号强度与过渡金属氧化物厚度的关系；
图12-17为本发明的另一方面所述的具有另一种阵列式“井”结构的图案化过渡金属氧化物层测序芯片制备过程的各工艺过程截面图，其中，
图12为根据本发明实施例的在表面具有氧化硅层的晶圆上形成一层具有阵列式“斑点”结构的过渡金属氧化物层的晶圆结构3-10的截面图；
图13为根据本发明实施例的在图12所示的具有过渡金属氧化物层薄膜的晶圆结构3-10上形成一层具有阵列式“井”结构的氧化硅层之后形成的晶圆3-20的截面图；
图14为根据本发明实施例的将图13所示的具有阵列式“井”结构的晶圆结构3-20进行切片工艺之后形成的多个单颗芯片3-30的截面图；
图15为根据本发明实施例的将图14中的单颗芯片进行组装工艺之后形成的测序芯片3-40的截面图；
图16为根据本发明实施例的将图15所示的测序芯片进行表面功能化修饰处理之后形成的测序芯片3-50的截面图；
图17A为根据本发明实施例的对图16中所示的进行过表面功能化修饰处理的测序芯片3-50进行DNB装载之后形成的具有DNB阵列的测序芯片3-60A的截面图；
图17B为根据本发明实施例的一种更简洁的、不需要进行表面修饰即可在测序芯片中形成DNB阵列的测序芯片3-60B的截面图；
图17C为根据本发明实施例的另一种基于硅衬底的不同“井”结构的荧光信号与第二层氧化层的关系；
图18-22为本发明的另一方面所述的背照式、具有阵列式“斑点”结构的图案化过渡金属氧化物层测序芯片制备过程的各工艺过程截面图；
图18为根据本发明实施例的在表面具有氧化硅层的晶圆上形成一层具有阵列式“斑点”结构的过渡金属氧化物层薄膜的晶圆结构4-10的截面图；
图19为根据本发明实施例的将图18所示的具有阵列式“井”结构的晶圆结构4-10进行切片工艺之后形成的多个单颗芯片4-20的截面图；
图20为根据本发明实施例的将图19中的单颗芯片4-20进行组装工艺之后形成的测序芯片4-30的截面图，此组装工艺为将芯片图案化层朝下与框架进行组装，从而激发光源和照相机从芯片背部透过石英或玻璃衬底照射DNB并收集信号；
图21为根据本发明实施例的将图20所示的测序芯片进行表面功能化修饰处理之后形成的测序芯片4-40的截面图；
图22A为根据本发明实施例的对图21中所示的进行过表面功能化修饰处理的测序芯片4-40进行DNB装载之后形成的具有DNB阵列的测序芯片4-50A的截面图；
图22B为根据本发明实施例的一种更简洁的、不需要进行表面修饰即可在测序芯片中形成DNB阵列的测序芯片4-50B的截面图；
图22C为根据本发明实施例的基于石英衬底的荧光信号与第二层氧化层的关系(背照式“斑点”结构)；
图23-28为本发明的另一方面所述的背照式、具有阵列式“井”结构的图案化过渡金属氧化物层测序芯片制备过程的各工艺过程截面图；
图23为根据本发明实施例的在表面具有氧化硅层的晶圆上形成一层过渡金属氧化物层薄膜的晶圆结构5-10的截面图；
图24为根据本发明实施例的在图23所示的具有过渡金属氧化物层薄膜的晶圆结构5-10上形成一层具有阵列式“井”结构的氧化硅层之后形成的晶圆5-20的截面图；
图25为根据本发明实施例的将图24所示的具有阵列式“井”结构的晶圆结构5-20进行切片工艺之后形成的多个单颗芯片5-30的截面图；
图26为根据本发明实施例的将图25中的单颗芯片5-30进行组装工艺之后形成的测序芯片5-40的截面图，此组装工艺为将芯片图案化层朝下与框架进行组装，从而激发光源和照相机从芯片背部透过石英或玻璃衬底照射DNB并收集信号；
图27为根据本发明实施例的将图26所示的测序芯片进行表面功能化修饰处理之后形成的测序芯片5-50的截面图；
图28A为根据本发明实施例的对图27中所示的进行过表面功能化修饰处理的测序芯片5-50进行DNB装载之后形成的具有DNB阵列的测序芯片5-60A的截面图；
图28B为根据本发明实施例的一种更简洁的、不需要进行表面修饰即可在测序芯片中形成DNB阵列的测序芯片5-60B的截面图；
图28C为根据本发明实施例的基于石英衬底的不同“井”结构的荧光信号与第二层氧化层的关系(背照式“井”结构)；
图29-34为本发明的另一方面所述的背照式、具有另一种阵列式“井”结构的图案化过渡金属氧化物层测序芯片制备过程的各工艺过程截面图，其中，
图29为根据本发明实施例的在表面具有氧化硅层612的晶圆611上形成一层具有阵列式“斑点”结构的过渡金属氧化物层613的晶圆结构6-10的截面图；
图30为根据本发明实施例的在图29所示的具有过渡金属氧化物层薄膜的晶圆结构6-10上形成一层具有阵列式“井”结构的氧化硅层之后形成的晶圆6-20的截面图；
图31为根据本发明实施例的将图30所示的具有阵列式“井”结构的晶圆结构6-20进行切片工艺之后形成的多个单颗芯片6-30的截面图；
图32为根据本发明实施例的将图31中的单颗芯片6-30进行组装工艺之后形成的测序芯片6-40的截面图，此组装工艺为将芯片图案化层朝下与框架进行组装，从而激发光源和照相机从芯片背部透过石英或玻璃衬底照射DNB并收集信号；
图33为根据本发明实施例的将图32所示的测序芯片进行表面功能化修饰处理之后形成的测序芯片6-50的截面图；
图34A为根据本发明实施例的对图33中所示的进行过表面功能化修饰处理的测序芯片6-50进行DNB装载之后形成的具有DNB阵列的测序芯片6-60A的截面图；
图34B为根据本发明实施例的一种更简洁的、不需要进行表面修饰即可在测序芯片中形成DNB阵列的测序芯片6-60B的截面图；
图34C为根据本发明实施例的另一种基于石英衬底的不同“井”结构的荧光信号与第二层氧化层的关系(另一种背照式“井”结构)；
图35-41为本发明的另一方面所述的在CMOS图像传感器晶圆上制备具有阵列式“斑点”结构或“井”结构图案化过渡金属氧化物层测序芯片制备过程的各工艺步骤截面图；
图35为根据本发明实施例的带有表面氧化层的CMOS图像传感器晶圆7-10的截面图；
图36A为根据本发明实施例的在图35所示的CMOS晶圆7-10上形成阵列式“斑点”结构图案化过渡金属氧化物层之后的晶圆结构7-20A的截面图；
图36B为根据本发明实施例的在图35所示的CMOS晶圆7-10上形成阵列式“井”结构图案化过渡金属氧化物层之后的晶圆结构7-20B的截面图；
图36C为根据本发明实施例的在图35所示的CMOS晶圆7-10上形成另一种阵列式“井”结构图案化过渡金属氧化物层之后的晶圆结构7-20C的截面图；
图37为根据本发明实施例的对图36所示的具有图案化过渡金属氧化物层的CMOS晶圆7-20进行切片工艺后形成的多个单颗芯片7-30的截面图；
图38为根据本发明实施例的图37所示的单颗芯片进行芯片贴装及引线键合之后形成的芯片结构7-40的截面图；
图39为根据本发明实施例的对图38所示的进行过芯片贴装及引线键合工艺之后的芯片7-50进行盖子结构贴合而形成的测序芯片7-50的截面图；
图40为根据本发明实施例的对图39所示的测序芯片进行表面功能化修饰处理之后形成的测序芯片7-60的截面图；
图41A为根据本发明实施例的对图40所示的经过表面功能化修饰处理的芯片7-60进行DNB装载之后形成的具有DNB阵列的测序芯片7-70A的截面图；
图41B为根据本发明实施例的一种更简洁的、不需要进行表面修饰即可在测序芯片中形成DNB阵列的测序芯片7-70B的截面图；
图41C为根据本发明实施例的基于CMOS结构的荧光强度与顶层氧化层厚度关系；
图41D为根据本发明实施例的基于CMOS结构的荧光强度与“斑点”金属氧化层厚度关系；
图41E为根据本发明实施例的基于CMOS结构的荧光强度与薄膜金属氧化层厚度关系；
图41F为根据本发明实施例的基于CMOS结构的荧光强度与第二层氧化物厚度的关系(薄膜金属氧化层)；
图42为根据本发明实施例的具有阵列式“斑点”结构的过渡金属氧化物层的晶圆结构8-10的截面图；
图43为根据本发明实施例的将图42所示的晶圆结构8-10进行切片工艺后形成的多个单颗芯片81和82后的晶圆结构8-20的截面图；
图44为根据本发明实施例的将图43中形成的单颗芯片81或82与一个把手结构831组装后形成的 可重复利用的测序芯片8-30的截面图；
图45为根据本发明实施例的将图44中所示的组装好的测序芯片浸入到一个装了试剂842的容器841中的示意图；
图46为根据本发明实施例的对过渡金属氧化物芯片表面未进行修饰，但改变DNB装载条件的荧光图像；
图47为根据本发明实施例的Zebra平台上进行上机测序结果图；
图48为根据本发明实施例的对过渡金属氧化物芯片表面进行选择性氨基化修饰之后进行DNB加载后的荧光图像；
图49为根据本发明实施例的对过渡金属氧化物区域进行氨基化并对二氧化硅非功能区域进行共聚物修饰后进行DNB加载后的荧光图像，左：对照组，右：实验组；以及
图50为根据本发明实施例的使用含有聚乙二醇的硅烷偶联剂对非功能区域的进一步修饰的效果检测的荧光图像，左：对照组，右：实验组。
附图标记：
1-10：晶圆结构，
11和12：晶圆上的单颗芯片，
111：晶圆衬底结构，
112：氧化硅层，
113：图案化过渡金属氧化物层(即过渡金属氧化物“斑点”)，
1-20：多个单颗晶圆结构，
121：切割槽，
1-30：单颗芯片组装成测序芯片，
131：框架结构，
132：盖玻片，
133：进出液口，
134：流体通道，
1-40：功能化表面修饰后形成的测序芯片，
141：氨基基团，
142：聚乙二醇分子层，
1-50A：DNB装载后形成的含DNB阵列的测序芯片，
1-50B：在测序芯片中形成DNB阵列的测序芯，
151：DNB样品，
152：光源和相机，
2-10：在裸晶圆上形成一层氧化硅层及过渡金属氧化物层之后的晶圆结构，
21和22：单颗芯片，
211：晶圆衬底，
212：氧化硅层，
213：过渡金属氧化物层，
2-20：在含过渡金属氧化物层的晶圆上形成图案化的“井”结构氧化硅层之后的晶圆，
221：氧化硅层，
222：离散排布的阵列式“井”结构，
2-30：晶圆结构进行切片工艺后形成的多个单颗芯片，
231：切割槽，
2-40：将单颗芯片进行组装之后形成的测序芯片，
241：框架，
242：盖玻片，
243：进出液口，
244：流体通道，
2-50：进行表面功能化修饰处理之后形成的测序芯片，
251：氧化硅层，
252：过渡金属氧化物层，2-60A：测序芯片上进行DNB装载之后形成的具有DNB阵列的测序芯片，
2-60B：在测序芯片中形成DNB阵列的测序芯片；
261：DNB，
262：激发光源及照相机结构，
3-10：含图案化过渡金属氧化物层的晶圆结构，
31和32：单颗芯片，
311：晶圆，
312：氧化硅层，
313：过渡金属氧化物层，
3-20：含图案化过渡金属氧化物层的晶圆上，再形成具有图案化“井”结构的氧化硅层之后的晶圆结构，
321：氧化硅层，
322：氧化硅层上的“井”结构，
3-30：晶圆结构进行切片工艺之后形成的被切割槽分隔开的多个单颗芯片，
331：切割槽，
3-40：单颗芯片进行组装工艺之后形成的测序芯片，
341：框架，
342：盖玻片，
343：进出液口，
344：流体通道，
3-50：测序芯片进行表面功能化修饰处理之后形成的测序芯片，
351：氧化硅层，
352：过渡金属氧化物层，
3-60A：进行过表面功能化处理的测序芯片进行DNB装载工艺之后形成的具有DNB阵列的测序芯片，
361：DNB，
362：激发光源及照相机结构，
3-60B：在测序芯片中形成DNB阵列的测序芯片，
4-10：具有氧化硅层的石英晶圆上形成图案化过渡金属氧化物层的晶圆结构，
41和42：晶圆上的单颗芯片，
411：石英晶圆，
412：氧化硅层，
413：图案化过渡金属氧化物层，
4-20：晶圆上进行切片工艺后，形成的被切割槽分隔开的多个单颗芯片，
421：切割槽，
4-30：单颗芯片进行封装工艺之后形成的测序芯片，
431：框架，
432：进出液口，
433：流体通道，
4-40：测序芯片进行表面功能化修饰处理之后形成的测序芯片，
441：氧化硅层，
442：过渡金属氧化物层，
4-50A：经过功能化修饰处理的测序芯片进行DNB装载之后形成的具有DNB阵列的测序芯片，
4-50B：在测序芯片中形成DNB阵列的测序芯片，
451：DNB，
452：激发光源与照相机，
5-10：在裸晶圆上形成一层氧化硅层及过渡金属氧化物层之后的晶圆结构，
51和52：晶圆上的单颗芯片，
511：晶圆衬底结构，
512：氧化硅层，
513：图案化过渡金属氧化物层，5-20：含过渡金属氧化物层的晶圆上形成图案化的“井”结构氧化硅层之后的晶圆，
521：氧化硅层，
522：过渡金属氧化物层，
5-30：晶圆结构进行切片工艺后形成的多个单颗芯片，
531：切割槽，
5-40：单颗芯片进行组装工艺之后形成的测序芯片，
541：框架，
542：进出液口，
5-50：测序芯片进行表面功能化修饰处理之后形成的测序芯片，
551：氧化硅层，
552：过渡金属氧化物层，
5-60A：经过功能化修饰处理的测序芯片进行DNB装载之后形成的具有DNB阵列的测序芯片，
5-60B：在测序芯片中形成DNB阵列的测序芯片，
561：DNB，
562：激发光源与照相机；
6-10：含图案化过渡金属氧化物层的晶圆结构，
61和62：晶圆上的单颗芯片，
611：晶圆，
612：氧化硅层，
613：过渡金属氧化物层，
6-20：含图案化过渡金属氧化物层的晶圆上，再形成具有图案化“井”结构的氧化硅层之后的晶圆结，
621：氧化硅层，
622：氧化硅层上的“井”结构，
6-30：晶圆结构进行切片工艺之后形成的被切割槽分隔开的多个单颗芯片，
631：切割槽，
6-40：单颗芯片进行封装工艺之后形成的测序芯片，
641：框架，
642：进出液口，
6-50：测序芯片进行表面功能化修饰处理之后形成的测序芯片，
651：氧化硅层，
652：过渡金属氧化物层，
6-60A：经过功能化修饰处理的测序芯片进行DNB装载之后形成的具有DNB阵列的测序芯片，
6-60B：在测序芯片中形成DNB阵列的测序芯片，661：DNB，
662：激发光源与照相机，
7-10：CMOS图像传感器晶圆，
71和72：两个芯片，
73：光敏层，
74：互联层，
75：衬底层，
711：硅衬底，
712：CMOS处理电路层，
713：介电层，
714：金属布线，
715：半导体材料，
716：光敏部分，
717：介电薄膜层，
718：氧化硅层，
719：芯片上的焊盘，
720：互联硅通孔，
7-20A：CMOS图像传感器晶圆上形成“斑点”结构的图案化过渡金属氧化物层之后的CMOS晶圆结构，
721：过渡金属氧化物区域，
7-20B：CMOS图像传感器晶圆上形成一种“井”结构的图案化过渡金属氧化物层之后的CMOS晶圆结构，
722：过渡金属氧化物区域，
723：氧化硅区域，
724：“井”结构的过渡金属氧化物区域，
7-20C：CMOS图像传感器晶圆上形成另一种“井”结构的图案化过渡金属氧化物层之后的CMOS晶圆结构，
725：过渡金属氧化物区域，
726：氧化硅区域，
727：过渡金属氧化物区域，
7-30：图案化晶圆结构进行切片工艺之后形成的被切割槽分开的多个单颗芯片，
731：切割槽，
7-40：芯片进行芯片贴装及引线键合之后形成的芯片结构，
741：封装衬底，
742：衬底上的焊盘，
743：触点，
744：金属连线，
7-50：芯片结构进行盖子结构贴合之后形成的测序芯片，
751：支撑结构的盖子结构，
752：进出液口，
753：流体通道，
7-60：测序芯片进行表面功能化修饰处理之后形成的测序芯片，
761：过渡金属氧化物区域，
762：氧化硅区域，
7-70A：经过功能化处理的测序芯片进行DNB装载之后形成的具有DNB阵列的测序芯片，
7-70B：在测序芯片中形成DNB阵列的测序芯片，
771：DNB，
8-10：具有阵列式“斑点”结构的过渡金属氧化物层的晶圆结构，
81和82：晶圆上的单颗芯片，
811：晶圆衬底，
812：氧化硅层，
813：“斑点”结构的过渡金属氧化物层，
81和82：多个单颗芯片，
8-20：晶圆结构进行切片工艺后形成的多个单颗芯片后的晶圆结构，
821：切割线，
8-30：单颗芯片与一个把手结构组装后形成的可重复利用的测序芯片，
831：把手结构，
8-40：组装好的测序芯片浸入到一个装了试剂的容器中的测序芯片，
841：容器，
842：试剂，
843：激发光源及照相机。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出。下面通过参考附图描述的实施例是示例性的，旨在用于解释本发明，而不能理解为对本发明的限制。
示例中的试剂、检测仪器等，如无特殊说明，可自配或者通过市售途径获取。
需要说明的是，本发明所述的“过渡金属氧化物区域”是指从芯片基质表面看，由过渡金属氧化物构成的区域，本发明所述的“氧化硅区域”是指从芯片基质表面看，由氧化硅构成的区域。
术语“图案化层”是指在晶圆表面上的过渡金属氧化物区域和氧化硅区域交替存在的形状，包括“井字形”和“斑点”结构。
术语“斑点”结构是指过渡金属氧化物区域高出于氧化硅区域，即过渡金属氧化物在氧化硅上呈离散型的分布形式。
术语“所述过渡金属氧化物层为连续层结构，所述第二氧化硅层由氧化硅呈数个相连的井字形成在所述过渡金属氧化物层上表面”，是指第二氧化硅层为井字格结构覆盖位于所述过渡金属氧化物层上表面，即井字格格体为氧化硅，井字格凹陷处为过渡金属氧化物。也可理解为第二氧化硅层像水井一样凹陷下去，在过渡金属氧化物层上表面形成了井字格形状。术语“芯片基质”可用于分割成单颗芯片并组装成可以进行测试的测序芯片。晶圆结构中包含数十至数千个相同的单颗芯片(由晶圆尺寸及晶片尺寸而定)，且在芯片和芯片中间保留了非常窄的无功能间隔，此间隔也称为切割线。
本发明的测序芯片的制备不受特别限制，可以根据所采用的晶圆材料的不同适用于现有技术中常规的该晶圆材料制备测序芯片的方法，与现有技术中测序芯片的差别在于，其中所用到的单颗芯片不同。
术语“单颗芯片”是指将本发明中的“芯片基质”沿着切割线切割而获得的，又可称为“芯片颗粒”。
芯片基质
在本发明的第一方面，本发明提出了一种芯片基质。根据本发明的实施例，所述芯片基质包括：晶圆层，所述晶圆层上具有均匀分布的切割线；第一氧化硅层，所述第一氧化硅层由氧化硅构成，形成在所述晶圆层的上表面；过渡金属氧化物层，所述过渡金属氧化物层由过渡金属氧化物构成，形成在所述第一氧化硅层的上表面。根据本发明实施例的芯片基质的表面包括两个区域，即待测序序列(尤其是DNB)结合位点区域(过渡金属氧化物区域，即功能区)和待测序序列非结合位点区域(氧化硅区域，即非功能区)。发明人发现，利用所述芯片基质上过渡金属氧化物区域和氧化硅区域表面性质不同，仅通过改变含有待测序序列溶液的pH及表面活性剂成分等，就可实现待测序序列选择性的吸附在过渡金属氧化物区域上。此外，还可以对过渡金属氧化物区域和非功能区进行选择性修饰，进一步增强DNB在过渡金属氧化物区域的选择性吸附能力。
根据本发明的实施例，所述过渡金属氧化物层由数个不相连的过渡金属氧化物斑点构成。过渡金属氧化物可以通过溅射、电子束蒸发或热蒸发原子层沉积法等常规的方法将过渡金属氧化物离散分布在氧化硅的表面，形成“斑点”形的图案化过渡金属氧化物层。由此，从表面上看，在芯片基质上形成了特异性结合测序序列的过渡金属氧化物斑点以及位于斑点之间的不能结合测序序列的氧化硅区域。
根据本发明的实施例，所述过渡金属氧化物斑点的厚度为10-20nm，所述第一氧化硅层的厚度为 80-100nm，优选为90nm。发明人通过仿真计算，发现过渡金属氧化物斑点的厚度为10-20nm和氧化硅层，第一氧化硅层的厚度为80-100nm，优选为90nm的芯片基质能对待测序序列，尤其是DNB发出的光的反射率更高，使得待测序序列，尤其是DNB发出的光信号尽可能多倍信号检测装置捕捉到，间接增强了待测序序列，尤其是DNB的信号强度，使信噪比更高，显著提高了最终获得的测序芯片的性能。
根据本发明的实施例，所述过渡金属氧化物斑点上进一步连接有氨基。发明人发现，将过渡金属氧化物分子进行氨基化，能进一步提高芯片基质表面功能区对DNB吸附的特异性。由此，通过调整DNB的pH以及表面活性剂成分，芯片基质表面功能区对DNB的特异性吸附功能更强。
根据本发明的实施例，所述数个不相连的过渡金属氧化物斑点之间的第一氧化硅层上进一步连接有聚乙二醇。由此，芯片基质表面非功能区对DNB的非特异性吸附进一步降低。
根据本发明的实施例，所述芯片基质进一步包括第二氧化硅层。
根据本发明的实施例，所述过渡金属氧化物层为连续层结构，所述第二氧化硅层由氧化硅呈数个相连的井字形成在所述过渡金属氧化物层上表面。需要说明的是，连续层结构是指过渡金属氧化物铺满在第一氧化硅层上面。由此，在过渡金属氧化物层上面覆盖一个或多个具有井字形的第二氧化硅层，能得到图案化的过渡金属氧化物与氧化硅交替出现的图案。
根据本发明的实施例，所述过渡金属氧化物层由数个不相连的过渡金属氧化物斑点构成，所述第二氧化硅层形成在所述数个不相连的过渡金属氧化物斑点之间的第一氧化硅层的上表面。可以理解的是，这里的第二氧化硅层可以和过渡金属氧化物斑点形成井字形，其中，过渡金属氧化物在井字形的凹陷内，第二氧化硅层构成井字形的格体，这样的话，第二氧化硅层可高于过渡金属氧化物层，也可与过渡金属氧化层一样高。
根据本发明的实施例，所述晶圆为硅晶圆，所述第二氧化硅层的厚度为40-60nm，优选为50nm，所述过渡金属氧化物层的厚度为5-15nm，所述第一氧化硅层的厚度为80-100nm，优选为90nm。发明人通过仿真计算，当晶圆为硅晶圆，形成井字形结构的芯片基质第二氧化硅层的厚度为40-60nm，优选为50nm，过渡金属氧化物层的厚度为5-15nm，第一氧化硅层的厚度为80-100nm，优选为90nm时，其对待测序序列，尤其是DNB发出的光的反射率更高，使得待测序序列，尤其是DNB发出的光信号尽可能多倍信号检测装置捕捉到，间接增强了待测序序列，尤其是DNB的信号强度，使信噪比更高，显著提高了最终获得的测序芯片的性能。
根据本发明的实施例，所述晶圆为石英晶圆，所述第二氧化硅层的厚度为100-200nm，所述过渡金属氧化物层的厚度为10-20nm，所述第一氧化硅层的厚度为80-100nm，优选为90nm。发明人通过仿真计算，当晶圆为石英晶圆，形成井字形结构的芯片基质第二氧化硅层的厚度为100-200nm，过渡金属氧化物层的厚度为10-20nm，第一氧化硅层的厚度为80-100nm，优选为90nm时，其对待测序序列，尤其是DNB发出的光的反射率更高，使得待测序序列，尤其是DNB发出的光信号尽可能多被信号检测装置捕捉到，间接增强了待测序序列，尤其是DNB的信号强度，使信噪比更高，显著提高了最终获得的测序芯片的性能。并且，当第二氧化硅层厚度为100-200nm时，最终形成的测序芯片中既保证了井字形结构具有合适的深度装载待测序序列，尤其是DNB，又能使相机能采集到强度比较高的荧光信号。
根据本发明的实施例，所述第二氧化硅层井字格凹陷处的所述过渡金属氧化物层或所述过渡金属氧化物斑点上进一步连接有氨基。发明人发现，将过渡金属氧化物分子进行氨基化，能进一步提高芯片基质表面功能区对待测序序列吸附的特异性。由此，通过调整待测序序列的pH以及表面活性剂成分，能实现芯片基质表面功能区对待测序序列的特异性吸附。
根据本发明的实施例，所述第二氧化硅层上进一步连接有聚乙二醇。由此，芯片表面非功能区对DNB的非特异性吸附进一步降低。
根据本发明的实施例，所述氨基与所述过渡金属氧化物层中的过渡金属氧化物分子至少一部分通过化学键相连。其中，“化学键”是指过渡金属-O-P键(如Zr-O-P键、Ti-O-P键、Ta-O-P键)。由此，氨基与过渡金属氧化物能紧密地结合在一起。
根据本发明的实施例，所述化学键是由过渡金属氧化物分子与氨基膦酸类化合物的磷酸基团连接形成的。发明人利用膦酸基团与氧化硅层不反应而与过渡金属氧化物分子的特异性反应，利用氨基膦酸类化合物可特异性地在过渡金属氧化物分子上引入氨基基团。
根据本发明的实施例，所述聚乙二醇是由包括选自选自聚乙烯亚胺-聚乙二醇和含有聚乙二醇的硅烷偶联剂的至少之一提供的。由此，芯片基质表面非功能区对DNB的非特异性吸附进一步降低。
根据本发明的实施例，所述聚乙二醇是由聚乙烯亚胺-聚乙二醇提供的，所述聚乙烯亚胺-聚乙二醇通过静电吸附在所述第一氧化硅层表面或第二氧化硅层表面。
根据本发明的实施例，所述聚乙二醇是由含有聚乙二醇的硅烷偶联剂提供的，所述含有聚乙二醇的硅烷偶联剂通过-Si-O-Si-链与所述第一氧化硅层或第二氧化硅层相连。
需要说明的是，根据本发明实施例的晶圆的材料不受限制。根据本发明的具体实施例，所述晶圆包括选自硅晶圆、石英晶圆、玻璃晶圆以及CMOS晶圆的至少之一。
根据本发明的实施例，所述过渡金属氧化物包括选自二氧化钛、二氧化锆、五氧化二钽、六氧化二铌以及二氧化铪的至少之一。
根据本发明的实施例，所述过渡金属氧化物包括选自二氧化钛、二氧化锆、五氧化二钽的至少之一。
测序芯片
在本发明的第二方面，本发明提出了一种测序芯片。根据本发明的实施例，所述测序芯片包括芯片主体，所述芯片主体包括数个芯片颗粒，所述芯片颗粒是将前面所述的芯片基质沿着晶圆层的切割线进行切割后获得的。发明人发现，仅通过改变含有待测序序列的溶液的pH及表面活性剂成分等，就可实现待测序序列的选择性的吸附在过渡金属氧化物层上。根据本发明实施例的测序芯片更稳定，测序结果更可靠，能显著提高测序芯片数据产出效率，提高测序芯片的产出，显著降低测序成本。
根据本发明的实施例的测序芯片结构可不需要表面单分子层，或可在进行完芯片制备工艺后再进行表面修饰，因此本发明所述的测序芯片具有性质稳定的特点，其可承受如刮擦这类的物理接触而不影响测序芯片性能，且能耐高温、耐化学试剂腐蚀。因此该芯片可承受条件更严苛、但效率更高的加工、组装工艺，在包装运输及进行使用前的准备工作时也更不易损坏。因此提高测序芯片的成品率，增加了使用测序芯片产出数据的效率，从而降低成本。
制备前面所述的芯片基质的方法
在本发明的第三方面，本发明提出了一种制备前面所述的芯片基质的方法。根据本发明的实施例，所述方法包括：对晶圆层进行表面修饰，所述表面修饰包括利用过渡金属氧化物对所述晶圆层的表面进行处理，以便形成过渡金属氧化物层，所述晶圆层的上表面具有第一氧化硅层，氧化硅层由氧化硅构成，所述过渡金属层形成在所述第一氧化硅层的上表面，所述晶圆层上具有均匀分布的切割线。根据本发明实施例的方法操作简单，环境友好。
根据本发明的实施例，第一氧化硅层是通过低温等离子体化学气相沉积、等离子体增强化学气相沉积、溅射或原子层沉积法的方法预先在所述晶圆层的上表面形成的。需要说明的是，在晶圆表面形成第一氧化硅层的方法不受限制，可以通过常规的半导体工艺技术进行，如低温等离子体化学气相沉积、等离子体增强化学气相沉积、溅射、原子层沉积等。
根据本发明的实施例，对晶圆层进行表面修饰是通过薄膜沉积、光刻或刻蚀的方法实现的，以便形成连续过渡金属氧化物层或呈斑点排列的过渡金属氧化物层。根据本发明的一个具体实施例，在氧化硅层上面形成一层图案化的过渡金属氧化物层，过渡金属氧化物可为二氧化钛、二氧化锆、五氧化二钽、六氧化二铌、二氧化铪或其任意组合，该过渡金属氧化物层离散式的分布在氧化硅层之上，并形成特定的阵列式图案(即过渡金属氧化物点阵和特殊设计的图形或线条，以便在后期测序光学进行校准)，且在每张单颗芯片上具有相同的图案排布。此图案化层可利用常规的半导体工艺技术，如薄膜沉积、光刻、刻蚀工艺实现，即首先在氧化硅层之上通过溅射、电子束蒸发、热蒸发原子层沉积等薄膜沉积技术形成一层覆盖整个晶圆过渡金属氧化物层，再在金属氧化物层上通过薄膜沉积、光刻、刻蚀工艺形成一层与所需图案化层对应的硬掩膜材料层，最后通过刻蚀工艺将硬掩膜层的图案复刻到过渡金属氧化物层上，形成图案化过渡金属氧化物层，即离散排布的过渡金属氧化物以“斑点”状有序的排布在氧化硅层之上，且无过渡金属氧化物“斑点”的区域，氧化硅层将暴露出来，其中“斑点”状过渡金属氧化物区域尺寸为与DNB尺寸相同或略小，从而使一个“斑点”仅吸附一个DNB。
根据本发明的实施例，所述过渡金属氧化物层为连续层结构，进一步包括在所述过渡金属氧化物层的上表面由氧化硅形成呈连续井字形排列的第二氧化硅层。其中，这里的形成主要是通过原子层沉积法 实现的。根据本发明的一个具体实施例，首先在晶圆上形成第一氧化硅层，之后再第一氧化硅层上再形成一层过渡金属氧化物层，之后再通过常规半导体工艺中的光刻、刻蚀技术在过渡金属氧化物层上形成离散排布的阵列式“井”结构。“井”结构底部为暴露出来的过渡金属氧化物层，“井”结构四周为高出过渡金属氧化物层的氧化硅层，“井”的尺寸为与DNB尺寸一致或略小，使每个“井”结构仅结合一个DNB。
根据本发明的实施例，所述过渡金属氧化物层呈斑点排列，进一步包括在所述过渡金属氧化物层斑点之间沉积氧化硅形成第二氧化硅层。其中，这里的沉积主要是通过原子层沉积法实现的。根据本发明的一个具体实施例，首先在晶圆上形成第一氧化硅层，再通过常规半导体工艺中的光刻、刻蚀技术在氧化硅层上形成离散排布的阵列式“井”结构。“井”结构底部为暴露出来的过渡金属氧化物层，“井”结构四周为高出或者与过渡金属氧化物层的氧化硅层一样高，“井”的尺寸为与DNB尺寸一致或略小，使每个“井”结构仅结合一个DNB。
根据本发明的实施例，进一步包括对所述过渡金属氧化物进行氨基化处理。由此，能在芯片基质的功能区引入氨基，进一步提高功能区对待测序序列，尤其是DNB的特异性吸附能力。
根据本发明的实施例，所述氨基化处理是通过将过渡金属氧化物与氨基膦酸类化合物进行反应获得的。由此，能使得氨基膦酸类化合物与过渡金属氧化物形成过渡金属-O-P键(如Zr-O-P键、Ti-O-P键、Ta-O-P键)。进而，能在芯片基质的功能区引入氨基，进一步提高功能区对待测序序列，尤其是DNB的特异性吸附能力。
根据本发明的实施例，进一步包括对所述第一氧化硅层或第二氧化硅层进行表面修饰，以便在所述第一氧化硅层或第二氧化硅层引入聚乙二醇。由此，能进一步降低芯片基质非功能区对测序序列，尤其是DNB的吸附能力。
根据本发明的实施例，所述聚乙二醇是由包括选自选自聚乙烯亚胺-聚乙二醇和含有聚乙二醇的硅烷偶联剂的至少之一提供的。
根据本发明的实施例，所述聚乙二醇是由聚乙烯亚胺-聚乙二醇提供的，所述表面修饰是通过将聚乙烯亚胺-聚乙二醇与所述第一氧化硅层表面或第二氧化硅层表面进行静电吸附进行的。由此，能在芯片基质的非功能区引入聚乙二醇。
根据本发明的实施例，所述聚乙二醇是由含有聚乙二醇的硅烷偶联剂提供的，所述表面修饰是通过将含有聚乙二醇的硅烷偶联剂与所述第一氧化硅层或第二氧化硅层的羟基进行缩合反应进行的，所述羟基是由第一或第二氧化硅层电离后吸附水中的氢氧根离子后形成的Si-OH提供的。由此，能在芯片基质的非功能区引入聚乙二醇。
制备测序芯片的方法
在本发明的第四方面，本发明提出了一种制备测序芯片的方法。根据本发明的实施例，所述方法包括：将芯片颗粒进行组装，所述芯片颗粒是将芯片基质沿着晶圆层的切割线进行切割后获得的，所述芯片基质如前面所述限定的或依据前面所述的方法获得。根据本发明实施例的方法操作简单，制备的测序芯片的成品率高。
根据本发明的实施例，所述切割是通过半导体晶圆切割方法实现的。
根据本发明的实施例，所述组装包括将所述芯片颗粒放置于一个含进出液口的支撑框架中，并用胶水或粘合剂将芯片颗粒与支撑框架贴合形成的，所述框架与所述芯片颗粒之间形成流体通道。
根据本发明的实施例，所述晶圆为硅晶圆，所述组装包括：所述芯片颗粒的上表面朝上与所述支撑框架贴合，将一个盖玻片设置在芯片颗粒的上表面，以便获得所述测序芯片。
根据本发明的实施例，所述晶圆为石英晶圆或玻璃晶圆，所述组装包括：所述芯片颗粒的下表面朝上与所述支撑框架贴合，以便获得所述测序芯片。
根据本发明的实施例，所述晶圆为CMOS晶圆，所述组装包括：将所述芯片颗粒的下表面与衬底(即感光元件)贴合，所述芯片颗粒与所述衬底通过引线连接，所述引线用于将芯片颗粒上的电信号传输到衬底上。
根据本发明的实施例，所述衬底形式包括但不限于LGA，CLCC，PLCC等形式。
根据本发明的实施例，所述引线键合所用的金属线包括但不限于金线和铝线等。
测序方法
在本发明的第五方面，本发明提出了一种测序方法。根据本发明的实施例，所述方法包括：利用测序芯片进行测序，所述测序芯片如前面所限定的或依据前面所述的方法制备的。根据本发明实施例的方法，测序的结果更加准确，成本更加低廉。
根据本发明的实施例，所述测序芯片的过渡金属氧化物层预先固定有DNB。DNB样品可认为是一个点光源，其发出的光能被相机或CMOS图像传感器收集采集到，之后进行测序。
以下详细介绍本发明的实施例。
实施例1在硅或石英晶圆上制备“斑点”结构的过渡金属氧化物测序芯片的方法
参见附图1-5，本实施例提出了一种在硅或石英晶圆上制备“斑点”结构的过渡金属氧化物测序芯片的方法，并示出了该方法的各步骤工艺过程的截面图。该方法可在不含任何内在电路或结构的裸晶圆上完成。本发明的图示中仅示意性的示出了晶圆上的两个区域11和12，本领域的专业技术人员应认识到，在晶圆上可形成多个(根据晶圆尺寸及芯片大小，芯片数量可为几十至数千不等)具有相同结构的单颗芯片，每张单颗芯片可形成一张测序芯片。
图1示出了在裸晶圆上形成含DNB结合位点区域(过渡金属氧化物层，即功能区)和DNB非结合位点区域(氧化硅层，即非功能区)交替存在的图案化层的晶圆1-10的截面图。首先提供图1中的晶圆衬底结构111，材料可为硅或石英，但本领域技术人员应认识到的是，本发明并不将衬底材料局限于硅或石英材料，其他任何合适的半导体晶圆材料也可用于本发明中。然后在晶圆111上形成一层氧化硅层112，可通过常规的半导体工艺技术形成该层氧化硅，如低温等离子体化学气相沉积、等离子体增强化学气相沉积、溅射、原子层沉积等。然后在氧化硅层上面形成一层图案化的过渡金属氧化物层，过渡金属氧化物可为二氧化钛、二氧化锆、五氧化二钽、六氧化二铌、二氧化铪或其任意组合，该过渡金属氧化物层离散式的分布在氧化硅层之上，并形成特定的阵列式图案，且在每张单颗芯片(如图1中的单颗芯片11和12)上具有相同的图案排布。此图案化层可利用常规的半导体工艺技术，如薄膜沉积、光刻、刻蚀工艺实现，即首先在氧化硅层之上通过溅射、电子束蒸发、热蒸发原子层沉积等薄膜沉积技术形成一层覆盖整个晶圆过渡金属氧化物层(未示出)，再在金属氧化物层上通过薄膜沉积、光刻、刻蚀工艺形成一层与所需图案化层对应的硬掩膜材料层(未示出)，最后通过刻蚀工艺将硬掩膜层的图案复刻到过渡金属氧化物层上，形成图1中结构113所示的图案化过渡金属氧化物层。结构113所示的图案化层中，离散排布的过渡金属氧化物以“斑点”状有序的排布在氧化硅层之上，且无过渡金属氧化物“斑点”的区域，氧化硅层将暴露出来，其中“斑点”状过渡金属氧化物区域尺寸为与DNB尺寸相同或略小，从而使一个“斑点”仅吸附一个DNB。应认识到，此处描述了形成此图案化层所需的工艺步骤，但任何可实现此图案化层的工艺方法应包含在此发明之内。图1中的晶圆结构1-10可包含数十至数千个相同的芯片(由晶圆尺寸及芯片尺寸而定)，且在芯片与芯片中间保留了非常窄的无功能间隔，此间隔也称为切割线，切割刀可在不损伤芯片有效结构区域的情况下将晶圆切割成多个单颗芯片。
图2示出了将具有图案化过渡金属氧化物层的晶圆1-10进行切片工艺后形成的多个单颗晶圆结构1-20的截面图。图2中晶圆已被切割成由切割槽121分割开的单颗芯片，此图2中示意性的描述了切片工艺之后的形成的单颗芯片11和12。
图3示出了将单颗芯片组装成测序芯片1-30之后的截面图。其中具有图案化表面层131的单颗芯片首先被装进含有进出液口133的框架结构131中，然后将进行过疏水处理的盖玻片132贴合到框架结构131之上，并在盖玻片132和含图案化表面113的芯片的之间形成流体通道134，液体可从进出液口133通入或排出流体通道134。本图中将芯片组装进框架131，及将盖玻片132贴合到框架131都采用粘合剂的方法将各个部件固定，任何合适的粘合剂都可使用在本发明中。此图为示意性的描述了被组装好的测序芯片的结构，即包括提供进出液口的框架、及与框架形成流体通道的盖玻片，但本领域技术人员应认识到，任何合适材料的框架及盖玻片，和任何可实现提供进出液口及流体通道的框架及盖玻片结构，都应包含在本发明内。
图4为将测序芯片1-30进行功能化表面修饰后形成的测序芯片1-40。其中用于表面修饰的液体可通过进出液口进入流体通道内，并与过渡金属氧化物区域和氧化硅区域接触，对其表面进行功能化修饰，使其分别具有吸附DNB(即DNB结合位点，过渡金属氧化物区域，功能区)和排斥DNB(即DNB非 结合位点，氧化硅区域，非功能区)的功能。其中表面修饰的过程包括：1)在氧化硅层表面形成聚乙二醇分子层142。所述聚乙二醇分子包括选自聚乙烯亚胺-聚乙二醇和含有聚乙二醇的硅烷偶联剂的至少之一，由此，芯片表面非功能区对DNB的非特异性吸附进一步降低；或所述聚乙二醇分子为聚乙烯亚胺-聚乙二醇所述多个聚乙二醇分子的一端与氧化硅层112是通过静电吸附相连。聚乙烯亚胺-聚乙二醇能在氧化硅层112上进行自组装，之后通过静电作用吸附在氧化硅层112上；或所述聚乙二醇分子为含有聚乙二醇的硅烷偶联剂，所述多个聚乙二醇分子的一端与氧化硅层112是通过-Si-O-Si-链相连，含有聚乙二醇的硅烷偶联剂能与氧化硅层112表面的羟基发生缩合反应，形成-Si-O-Si-链。2)在过渡金属氧化物层上形成多个氨基基团141。所述多个氨基基团与所述多个过渡金属氧化物分子的至少一部分相连，所述多个氨基基团与氧化硅层不相连。发明人发现，将过渡金属氧化物分子进行氨基化，能进一步提高芯片表面功能区对DNB吸附的特异性。由此，通过调整DNB的pH以及表面活性剂成分，能实现芯片表面功能区对DNB的特异性吸附。所述多个氨基基团是由氨基膦酸类化合物提供氨基基团的。发明人发现，膦酸基团与氧化硅层不反应而与过渡金属氧化物分子的特异性反应，利用氨基膦酸类化合物可特异性地在过渡金属氧化物分子上引入氨基基团；或所述多个氨基基团与所述多个过渡金属氧化物分子的至少一部分相连是通过化学键相连。如前所述，发明人利用膦酸基团与氧化硅层不反应而与过渡金属氧化物分子的特异性反应，利用氨基膦酸类化合物可特异性地在过渡金属氧化物分子上引入氨基基团，其中，膦酸基团与过渡金属氧化物分子能形成相应的化学键，所述多个氨基基团通过膦酸基团与过渡金属氧化物分子形成化学键与过渡金属氧化物分子连接；所述化学键由过渡金属与氨基膦酸类化合物的磷酸基团连接形成的。氨基膦酸类化合物中的膦酸基团可与过渡金属氧化物分子能形成相应的过渡金属-O-P键(如Zr-O-P键、Ti-O-P键、Ta-O-P键)，因此所述多个氨基基团通过膦酸基团与过渡金属氧化物分子形成的过渡金属-O-P键与过渡金属氧化物分子连接。
图5A为将图4中进行了功能化处理后形成的测序芯片1-40进行DNB装载后形成的含DNB阵列的测序芯片1-50A的截面图。通过测序芯片上的进出液口133将DNB试剂通入流体通道中，DNB将选择性的与DNB结合位点(氨基基团修饰后的过渡金属氧化物区域，即功能区)进行结合，而不与DNB非结合位点结合(聚乙二醇修饰后的氧化硅层)，从而形成DNB纳米阵列。图5A中还示出光源和相机152，结合了荧光标记物的DNB可在特定波长或能量的光源的激发下发射出特定波长或能量的光，并被相机采集，通过分析相机采集到的光信号可识别出DNB上碱基排布。
图5B示出了另一种更简洁的DNB装载方法，图5B中图3的测序芯片1-30未经过任何表面修饰处理，即可进行DNB装载，此步骤需使DNB试剂的ph及表面活性剂成分达到最优，从而使不进行表面功能化修饰的情况下，DNB可只选择性的吸附在DNB结合位点(过渡金属氧化物层，即功能区)上，而被DNB非结合位点(氧化硅层，即非功能区)排斥。应认识到图4及图5A所示的先进行表面功能化修饰再进行DNB装载的方法将使DNB对图案化表面的选择性吸附效果更好。
结果如图5A和5B所示，DNB样品151装载在过渡金属氧化物“斑点”113上，相机152放置于DNB样品上方，并用来采集DNB样品发出的光信号。DNB样品可认为是一个点光源，其向上方向发出的光直接被相机收集到，向下发出的光一部分可被过渡金属氧化物层和氧化硅层反射并被相机收集到，另一部分向下发出的光则会穿过过渡金属氧化物层和氧化硅层进入硅衬底。发明人通过光学仿真计算得到了一个最优化的过渡金属氧化物层和氧化硅层厚度，在此厚度时过渡金属氧化物层和氧化硅层对DNB发出的光信号的反射最大、透射最小，使DNB发出的光信号尽可能多的向上传输并被相机收集到，即被相机捕捉到的荧光信号强度最大。在进行仿真计算时，首先为了先确定一个最优的氧化硅层厚度，计算了在没有过渡金属氧化物层的情况下，不同氧化硅层厚度对应的荧光信号强度，仿真计算结果如图5C所示。在氧化硅层厚度为90纳米左右时，4种波长的光的反射率都相对较高。
当氧化硅层厚度为90纳米左右时，氧化硅层对DNB样品发出的光信号的反射效果最好，即相机捕捉到的荧光信号强度最强。然后又计算仿真了当氧化硅层厚度为90纳米时，过渡金属氧化层厚度的变化与荧光信号强度的关系，结果如图5D所示，当过渡金属氧化物层厚度小于40纳米时，当过渡金属氧化物层的厚度升高，相机可以捕捉的荧光信号强度逐渐降低，因此当过渡金属氧化物层的厚度为10至20纳米左右时，过渡金属氧化物层具有较好的机械可靠性，并且反射率最大，相机捕捉到的荧光信号强度最高，如图5D所示。
实施例2在硅或石英晶圆上制备“井”结构的过渡金属氧化物测序芯片的方法
见附图6-11，本实施例提供了一种在硅或石英晶圆上制备“井”结构的过渡金属氧化物测序芯片的方法。并示出了该方法的各步骤工艺过程的截面图。该方法可在不含任何内在电路或结构的裸晶圆上完成。本发明的图示中仅示意性的示出了晶圆上的两个区域21和22，本领域的专业技术人员应认识到，在晶圆上可形成多个(根据晶圆尺寸及芯片大小，芯片数量可为几十至数千不等)具有相同结构的单颗芯片，每张单颗芯片可形成一张测序芯片。
图6示出了在裸晶圆上形成一层氧化硅层及过渡金属氧化物层之后的晶圆结构2-10的截面图。首先提供一张晶圆衬底211，此晶圆衬底可为硅或石英材料，但不局限于此，任何合适的半导体晶圆都可应用于本发明。然后在晶圆211上形成一层氧化硅层212，形成氧化硅层的工艺与实施例1中图1所述相似。再在氧化硅层上形成一层过渡金属氧化物层213，过渡金属氧化物可为二氧化钛、二氧化锆、五氧化二钽、六氧化二铌、二氧化铪或其任意组合，且形成方法与实施例1中图1中类似。
图7示出了在图6中含过渡金属氧化物层的晶圆2-10上形成图案化的“井”结构氧化硅层之后的晶圆2-20的截面图。在图7中，首先在图6的晶圆2-10上形成一层氧化硅层221，再通过常规半导体工艺中的光刻、刻蚀技术在氧化硅层221上形成离散排布的阵列式“井”结构222。“井”结构底部为暴露出来的过渡金属氧化物层，“井”结构四周为高出过渡金属氧化物层的氧化硅层221，“井”的尺寸为与DNB尺寸一致或略小，使每个“井”结构仅结合一个DNB。
图8示出了将图7的晶圆结构2-20进行切片工艺后形成的多个单颗芯片2-30的截面图。本图中采用与实施例1中图2中的相似的切片工艺。图7的2-20晶圆被切割为由切割槽231分隔开的单颗芯片21及22。
图9示出了将单颗芯片进行组装之后形成的测序芯片2-40的截面图。所述组装工艺与实施例1中图3的工艺类似。包括具有进出液口243的框架241，及贴合在框架上的盖玻片242。在盖玻片与含阵列式“井”结构的单颗芯片中间形成流体通道。
图10为将图9的测序芯片2-40进行表面功能化修饰处理后形成的测序芯片2-50的截面图。图中的表面功能化处理步骤与实施例1中图4中类似，最终在过渡金属氧化物层213上暴露出的“井”结构底部形成氨基基团修饰的DNB结合位点区域(即功能区)，而在高出于过渡金属氧化物层之上的氧化硅层表面形成聚乙二醇分子层。
图11A为在图10所示的测序芯片2-50上进行DNB装载之后形成的具有DNB阵列的测序芯片2-60A的截面图。如本图所示DNB被装载在经过表面功能化修饰处理的测序芯片2-60A的阵列式“井”结构内，这将使DNB能承受更高流速的液体的冲刷，提高测序芯片进行测序时的速度。本图中同样示出了激发光源及照相机结构262，其能提供特定波长和能力的激发光并收集被荧光标记物标记了的DNB发射出的特定波长及能力的光信号，应用于识别DNB上碱基的排布。
图11B示出了另一种更简洁的DNB装载方法，图9的测序芯片2-40未经过任何表面修饰处理，即可进行DNB装载形成测序芯片2-60B，此步骤需使DNB试剂的pH及表面活性剂成分达到最优，从而使不进行表面功能化修饰的情况下，DNB可只选择性的吸附在DNB结合位点(过渡金属氧化物层，即功能区)上，而被DNB非结合位点(氧化硅层，即非功能区)排斥。发明人发现，图10及图11A所示的先进行表面功能化修饰再进行DNB装载的方法将使DNB对图案化表面的选择性吸附效果更好。
发明人同样通过光学仿真计算，对氧化硅层和过渡金属氧化物层的厚度进行了优化，本实施例中的过渡金属氧化物层为一层薄膜结构，过渡金属氧化物层下方为第一层氧化硅层，过渡金属氧化物层上方为具有阵列式“井”结构的第二层氧化硅层。根据上述实施例1中的仿真结果，发明人了解到当过渡金属氧化物层厚度在0到40纳米内变化时，随着过渡金属氧化物层厚度的增加，薄膜的反射率逐渐降低，相机能收集到的荧光信号强度逐渐减小。因此，首先仿真了当第一层氧化硅层厚度为90纳米，过渡金属氧化物层厚度分别为0纳米、10纳米、20纳米时，荧光信号强度与具有阵列式“井”结构的第二层氧化硅层厚度的关系。仿真结果如图11C所示，随着第二层氧化硅层厚度的增加，荧光信号强度逐渐减弱，薄膜对光信号的反射率降低。因此为了使“井”结构具有一定的深度用来装载DNB，发明人选择第二层氧化硅层厚度为50纳米左右。
当第一层氧化硅层厚度为90纳米时，第二层氧化硅层厚度为50纳米时，又仿真计算了不同过渡金 属氧化物层厚度与荧光信号强度的对应关系。仿真结果如图11D所示，弃变化趋势与上述实施例1类似，即当过渡金属氧化物层的厚度小于40纳米时，随着过渡金属氧化物层厚度的增加，反射率减小，荧光信号强度逐渐减弱。因此发明人认为过渡金属氧化物层厚度为5～15纳米左右时最优，此时四种碱基发出的不同波长的荧光信号强度都相对较高。所示，发明人认为在本实施例中，当第一层氧化硅层厚度为90纳米，过渡金属氧化物层厚度为5～15纳米，第二层氧化硅厚度为50纳米时，测序芯片上的薄膜的反射率较大，相机可以捕捉到的荧光信号强度相对较高。
实施例3另一种在硅或石英晶圆上制备“井”结构的过渡金属氧化物测序芯片的方法
如附图12-17所示，本实施例提供了另一种在硅或石英晶圆上制备“井”结构的过渡金属氧化物测序芯片的方法的各步骤工艺截面图。此方法与实施例2方法的不同之处在于，本方法首先在含氧化硅层312的晶圆311上形成图案化的过渡金属氧化物层313，而实施2方法的则为整张晶圆上形成过渡金属氧化物层，如图12及图6对比所示。
图12为含图案化过渡金属氧化物层313的晶圆结构3-10的截面图，其形成工艺与实施例1中图1类似。
图13为在图12所示的含图案化过渡金属氧化物层的晶圆3-10上，再形成具有图案化“井”结构322的氧化硅层321之后的晶圆结构3-20的截面图。其形成工艺与实施2中的图7种类似，其中氧化硅层上的“井”结构322与图案化的“斑点”状过渡金属氧化物层313一一对应，最终氧化硅层将高于过渡金属氧化物层，并在晶圆表面形成阵列式的图案化“井”结构，“井”结构底部为暴露出的过渡金属氧化物层313。
图14为将图13的晶圆结构3-20进行切片工艺之后形成的被切割槽331分隔开的多个单颗芯片3-30的截面图。切片工艺与实施例2中图8类似。
图15为将图14所示的单颗芯片3-30进行组装工艺之后形成的测序芯片3-40的截面图。组装工艺与实施例2中图9类似。
图16为将图15所示的测序芯片3-40进行表面功能化修饰处理之后形成的测序芯片3-50。其表面功能化处理工艺与实施例2中图10类似。
图17A为将图16所示的进行过表面功能化处理的测序芯片3-50进行DNB装载工艺之后形成的具有DNB阵列的测序芯片3-60A的截面图。其DNB装载步骤与实施例2中图11A所述类似。
图17B为另一种更简洁、不需进行表面功能化修饰处理的DNB装载方法，其与上述实施例2中图11B类似。
在本实施例中，过渡金属氧化物层为形成在第一层氧化硅层之上的阵列式的“斑点”结构，同时在其上方又形成了第二层具有阵列式“井”结构的氧化硅层，氧化硅层的“井”结构和过渡金属氧化物层的“斑点”对应。在上述实施例1中，通过仿真计算得到，当第一层氧化硅层厚度为90纳米，过渡金属氧化物层厚度为10到20纳米左右时，具有最优化的反射率，荧光信号强度做大。在此基础上，继续仿真了当具有第二层阵列式“井”结构的氧化硅层时，荧光信号强度随着第二层氧化硅层厚度的变化，仿真计算结果如图17C所示，在第二层氧化硅层厚度为0时，即没有第二层氧化硅层时，荧光信号强度最大，而随着第二层氧化硅层厚度的增加，反射率降低，荧光信号强度逐渐减弱。因此为了保证具有“井”结构装载DNB样品，第二层氧化硅层厚度为50纳米左右时为最优，此时第一次氧化硅层厚度为90纳米，过渡金属氧化物层厚度为10至20纳米左右。
实施例4在石英晶圆上制备“斑点”结构、背照式的过渡金属氧化物测序芯片的方法
如附图18-22所示，本实施例提供了一种在石英晶圆上制备背照式“斑点”结构过渡金属氧化物测序芯片的方法的各步工艺的截面图。本实施例与实施例1-3的不用在于，本实施例的方法采用石英晶圆或其他任何合适的透光玻璃晶圆作为衬底，并在衬底晶圆上制备图案化的“斑点”结构过渡金属氧化物图案化层，且在进行组装工艺时将芯片图案化层朝下进行组装，并用激发光源及照相机从芯片背面(即透过石英晶圆衬底)对DNB进行激发并采集荧光信号。
图18为在具有氧化硅层412的石英晶圆411上形成图案化过渡金属氧化物层的晶圆结构4-10的截面图，其中晶圆为石英晶圆，但其他任何合适的透光玻璃晶圆在可在本发明中使用。氧化层412及图案化过渡金属氧化物层413形成的工艺与实施例1中图1类似。
图19为在图18的晶圆4-10上进行切片工艺后，形成的被切割槽分隔开的多个单颗芯片4-20的截面图。切片工艺与实施例1中图2类似。
图20示出了将图19中的单颗芯片进行封装工艺之后形成的测序芯片4-30的截面图。本工艺步骤中，测序芯片的图案化层朝下与一个含进出液口432的框架431组装并贴合在一起，在框架与芯片上的图案化层之间形成流体通道433。其中框架431可由任何合适的材料以任何合适的加工方法加工而成，且可通过任何合适的粘合剂将芯片与框架贴合起来。应认识到，本图示意性的描述了框架应具有的结构，但本图并非限制性的，任何能提供支撑芯片的作用、具备进出液口、可与芯片图案化层形成流体通道的框架结构都应视为本发明的权利范围内。
图21为对图20所示的测序芯片4-30进行表面功能化修饰处理之后形成的测序芯片4-40的截面图。其中功能化修饰的步骤与实施例1中图4所示的类似。
图22A为对图21所示的经过功能化修饰处理的测序芯片4-40进行DNB装载之后形成的具有DNB阵列的测序芯片4-50A的截面图。其中DNB装载步骤与实施例1中图5A中类似。本图22A中同样示出了激发光源与照相机452，其从测序芯片的石英或玻璃衬底背面照射DNB，并收集被荧光标记物标记的DNB发出的荧光芯片，从而对DNB上的碱基进行测序。
图22B为另一种更简洁、不需进行表面功能化修饰处理的的DNB装载方法，其与实施例1中图5B类似。且激发光源与照相机452从测序芯片的石英或玻璃衬底背面照射DNB，并收集被荧光标记物标记的DNB发出的荧光芯片，从而对DNB上的碱基进行测序。
在本实施例4中，氧化硅层首先形成在透明石英晶圆上，然后阵列式的过渡金属氧化物“斑点”结构形成在氧化硅层上，DNB样品装载在过渡金属氧化物“斑点”结构上。但在此实施例中，照相机放置在石英衬底背面，DNB发出的光信号需要透过过渡金属氧化物层、氧化硅层和石英衬底，然后被照相机捕捉到。因此，本实施例4中计算了DNB发出的荧光信号在透过不同厚度的过渡金属氧化物层、氧化硅层及石英衬底后，能被相机捕捉到的信号强度对比。仿真结果如图22C所示，当氧化硅层厚度为90纳米，过渡金属氧化物层厚度为10～20纳米(第二层氧化硅层厚度为0)时，DNB样品发出的荧光的透射率最大，此时透过过渡金属氧化物层，氧化硅层及石英衬底的荧光信号强度最大，接近100％。
实施例5在石英晶圆上制备“井”结构、背照式的过渡金属氧化物测序芯片的方法
如附图23-28所示，本实施例提出了一种石英晶圆上制备背照式“井”结构过渡金属氧化物测序芯片的方法的各步工艺的截面图。本实施例的方法采用石英晶圆或其他任何合适的透光玻璃晶圆作为衬底，并在衬底晶圆上制备图案化的“井”结构过渡金属氧化物图案化层，且在进行组装工艺时将芯片图案化层朝下进行组装，并用激发光源及照相机从芯片背面(即透过石英晶圆衬底)对DNB进行激发并采集荧光信号。
图23示出了在裸晶圆上形成一层氧化硅层及过渡金属氧化物层之后的晶圆结构5-10的截面图。其形成方法与实施例2中图6中类似。
图24示出了在图23中含过渡金属氧化物层的晶圆5-10上形成图案化的“井”结构氧化硅层之后的晶圆5-20的截面图。其形成发放与实施例2中图7中类似。
图25示出了将图24的晶圆结构5-20进行切片工艺后形成的多个单颗芯片5-30的截面图。本图中采用与实施例1中图2中的相似的切片工艺。
图26示出了将图25中的单颗芯片进行封装工艺之后形成的测序芯片5-30的截面图。本工艺步骤中，测序芯片的图案化层朝下与一个含进出液口432的框架431组装并贴合在一起，在框架与芯片上的图案化层之间形成流体通道433。本图中采用与实施例3中图20的工艺。
图27为对图26所示的测序芯片5-40进行表面功能化修饰处理之后形成的测序芯片5-50的截面图。其中功能化修饰的步骤与实施例1中图4所示的类似。
图28A为对图27所示的经过功能化修饰处理的测序芯片5-50进行DNB装载之后形成的具有DNB阵列的测序芯片5-60A的截面图。其中DNB装载步骤与实施例1中图5A中类似。本图中同样示出了激发光源与照相机562，其从测序芯片的石英或玻璃衬底背面照射DNB，并收集被荧光标记物标记的DNB发出的荧光芯片，从而对DNB上的碱基进行测序。
图28B为另一种更简洁、不需进行表面功能化修饰处理的的DNB装载方法，其与实施例1中图5B 类似。且激发光源与照相机562从测序芯片的石英或玻璃衬底背面照射DNB，并收集被荧光标记物标记的DNB发出的荧光信号，从而对DNB上的碱基进行测序。
在本实施例5中，首先在石英晶圆上形成第一层氧化硅层，然后在第一层氧化硅层上方形成一层过渡金属氧化物层，然后在过渡金属氧化物层上方在形成具有阵列式“井”结构的第二层氧化硅层。在这种情况下DNB样品同样装载在“井”结构中的过渡金属氧化物层上，其发出的光信号透过过渡金属氧化物层、第一层氧化硅层及石英衬底，并被放置在石英衬底背面的照相机捕捉到。在这种情况下，仿真了当第一层氧化硅层厚度为90纳米，过渡金属氧化物层厚度为10纳米或20纳米时，不同的第二层氧化硅层厚度对透过薄膜层的荧光信号强度的影响。仿真结果如图28C所示，在第一层氧化硅层和第二层氧化硅层厚度相同的情况下，具有10纳米厚过渡金属氧化物层的结构的荧光信号强度要高于20纳米厚的结构。而在当第一层氧化硅层厚度和过渡金属氧化层厚度确定时，当第二层氧化硅层厚度增加时，透过薄膜层的荧光信号强度并不随着第二层氧化硅层厚度的增加而单调增加或单调减小，而是在不同的波长情况下表现出不同的荧光信号强度变化趋势。在这种情况下，当第二层氧化硅层厚度为100至200纳米时，即保证了“井”结构具有合适的深度装载DNB，又使相机能采集到强度比较高的荧光信号。
实施例6另一种在石英晶圆上制备“井”结构、背照式的过渡金属氧化物测序芯片的方法
如附图29-34所示，本实施例提出了一种石英晶圆上制备背照式“井”结构过渡金属氧化物测序芯片的方法的各步工艺的截面图。此方法与上述5方法的不同之处在于，本方法首先在含氧化硅层612的晶圆611上形成图案化的过渡金属氧化物层613，而实施例5的方法的则为整张晶圆上形成过渡金属氧化物层，如图29及图23对比所示。
图29为含图案化过渡金属氧化物层613的晶圆结构6-10的截面图，其形成工艺与上述图1类似。
图30为在图29所示的含图案化过渡金属氧化物层的晶圆6-10上，再形成具有图案化“井”结构622的氧化硅层621之后的晶圆结6-20的截面图。其形成工艺与实施例2中图7种类似，其中氧化硅层上的“井”结构622与图案化的“斑点”状过渡金属氧化物层613一一对应，最终氧化硅层将高于过渡金属氧化物层，并在晶圆表面形成阵列式的图案化“井”结构，“井”结构底部为暴露出的过渡金属氧化物层613。
图31为将图30的晶圆结构6-20进行切片工艺之后形成的被切割槽631分隔开的多个单颗芯片6-30的截面图。切片工艺与实施例2中图8类似。
图32示出了将图31中的单颗芯片进行封装工艺之后形成的测序芯片6-40的截面图。本图工艺与实施例5中图26类似。
图33为对图32所示的测序芯片6-40进行表面功能化修饰处理之后形成的测序芯片6-50的截面图。其中功能化修饰的步骤与实施例1中图4所示的类似。
图34A为对图33所示的经过功能化修饰处理的测序芯片6-50进行DNB装载之后形成的具有DNB阵列的测序芯片6-60A的截面图。其中DNB装载步骤与实施例1中图5A中类似。本图中同样示出了激发光源与照相机662，其从测序芯片的石英或玻璃衬底背面照射DNB，并收集被荧光标记物标记的DNB发出的荧光芯片，从而对DNB上的碱基进行测序。
图34B为另一种更简洁、不需进行表面功能化修饰处理的DNB装载方法，其与实施例1中图5B类似。且激发光源与照相机662从测序芯片的石英或玻璃衬底背面照射DNB，并收集被荧光标记物标记的DNB发出的荧光芯片，从而对DNB上的碱基进行测序。
在本实施例6中，首先在石英晶圆上形成第一层氧化硅层，然后在第一层氧化硅层上方形成一层具有阵列式“斑点”结构的过渡金属氧化物层，然后在过渡金属氧化物层上方在形成具有阵列式“井”结构的第二层氧化硅层，其中第二层氧化硅层的“井”结构和过渡金属氧化物层的“斑点”结构对应，过渡金属氧化物“斑点”结构在第二层氧化硅层“井”结构的底部。在这种情况下DNB样品同样装载在“井”结构中的过渡金属氧化物层上，其发出的光信号透过过渡金属氧化物层、第一层氧化硅层及石英衬底，并被放置在石英衬底背面的照相机捕捉到。
在这种情况下，首先仿真了当第一层氧化硅层厚度为90纳米，过渡金属氧化物层厚度为10纳米或20纳米时，不同的第二层氧化硅层厚度对荧光信号强度的影响。仿真结果如图34C所示，在第一层氧化硅层和第二层氧化硅层厚度相同的情况下，具有10纳米厚过渡金属氧化物层的结构的荧光信号强度同样 要高于20纳米厚的结构。而在当第一层氧化硅层厚度和过渡金属氧化层厚度确定时，当第二层氧化硅层厚度增加时，透过薄膜层的荧光信号强度同样也并不随着第二层氧化硅层厚度的增加而单调增加或单调减小，而是在不同的波长情况下表现出不同的荧光信号强度变化趋势。在这种情况下，当第二层氧化硅层厚度为100至200纳米时，即保证了“井”结构具有合适的深度装载DNB，又使相机可以采集到强度比较高的荧光信号。
实施例7在CMOS晶圆上制备“斑点”结构或“井”结构过渡金属氧化物测序芯片的方法
如附图35-41所示，本实施例提出了一种在CMOS晶圆上制备具有阵列式“斑点”结构或“井”结构的过渡金属氧化物测序芯片的方法。此方法与上述方法的不同之处在于，上述方法都采用外部的激发光源及照相机设备，通过外部激发光源发出的特定波长和能量激发光照射被荧光标记物标记了的DNB，使DNB发射出特定波长和能量的光，通过照相机采集DNB发出的光信号可进行测序，而本方法则不需要外部的激发光源及照相机设备。本方法所采用的CMOS晶圆为具有图像传感器功能的CMOS晶圆，每张晶圆上可具有数百至数千颗图像传感器芯片，每颗图像传感器芯片可具有数百万至数千万个像素点(及光电二极管阵列)，图像传感器芯片可感知外部的不同强度的光信号并转换为相应的电信号。将标记了荧光标记物的DNB选择性的装载到图像传感器芯片上的光电二极管阵列上，形成与光电二极管阵列一一对应的DNB阵列，并使用生物或化学方法使DNB发光(不加外部激发光源)，通过识别图像传感器芯片在不同时间、不同像素点上的光信号值，可对装载到图像传感器芯片上的DNB阵列进行测序。
图35为一张CMOS图像传感器晶圆7-10截面的示意图，本领域技术人员应认识到一张CMOS晶圆上可具有多个芯片，本图中只示意性的画出其中两个芯片71和72。如图35所示该CMOS图像传感器晶圆具有光敏层73、互联层74、衬底层75、光敏层73上的介电薄膜层717，该层材料通常为二氧化铪和五氧化二钽薄膜堆叠而成，在介电薄膜层717之上为一层氧化硅层718。其中光敏层73包括形成在半导体材料715中的光敏部分716，此光敏部分716可以为一种光电二极管。半导体材料层715可以由任何合适的材料制成，例如硅、硅上的III-V族材料、硅上的石墨烯、绝缘体上的硅及它们的组合等。尽管本发明在此对光电二极管716进行了描述，但是值得注意的是任何合适的光敏结构都可以应用在本发明中。光敏二极管716可将测量到的光信号转变为电流信号。光敏二极管716可以包含一个MOS(Metal Oxide Semiconductor,金属氧化物半导体)晶体管的源极和漏极，其可将电流传输到其他部件上，如传输到另一个MOS晶体管上。其他组件可包括复位晶体管、电流源跟随器或用于将电流值转换为数字信号的行选择器等。CMOS图形传感器10中也可以包含电介质层，值得注意的是此电介质层可以包含任何合适的电绝缘材料。互联层74包含了形成与介电层713中的金属布线714，金属布线714可以被用于集成电路材料内部互联，也可用于对外部的电连接。衬底层75包括硅衬底711和CMOS处理电路层712，CMOS处理电路层可包含用于测序操作需要的CMOS电路。例如，CMOS处理电路层712可包含用于图像处理、信号处理、用于实现测序操作的控制功能和外部通讯的电路。CMOS处理电路712将光敏层73传感到的光敏信号处理成电信号，并通过互联硅通孔720及焊盘719将电信号传输到外部设备。
本领域技术人员应认识到的是，在本发明中只示意性的描述的CMOS图像传感器芯片的结构，但此描述并非限制性的，任何结构的图像传感器芯片都可用于本发明中。
然后在图35所示的CMOS图像传感器晶圆7-10上形成阵列式的具有“斑点”结构或“井”结构的过渡金属氧化物层，即如下所述的图36A，图36B和图36C。
其中图36A为在图35所示的CMOS图像传感器晶圆7-10上形成“斑点”结构的图案化过渡金属氧化物层之后的CMOS晶圆结构7-20A的截面图。本图中的工艺步骤与实施例1中图1中类似，不同之处只在于本图中晶圆为CMOS晶圆，且“斑点”结构的过渡金属氧化物区域721分布在光电二极管阵列716上方。
其中图36B为在图35所示的CMOS图像传感器晶圆7-10上形成一种“井”结构的图案化过渡金属氧化物层之后的CMOS晶圆结构7-20B的截面图。本图中的工艺步骤与实施例2中图6及图7中类似，不同之处只在于本图中晶圆为CMOS晶圆，且“井”结构的过渡金属氧化物区域724分布在光电二极管阵列716上方。
其中图36C为在图35所示的CMOS图像传感器晶圆7-10上形成另一种“井”结构的图案化过渡金属氧化物层之后的CMOS晶圆结构7-20C的截面图。图36C中的工艺步骤与实施例3中图12及图13 中类似，不同之处只在于本图中晶圆为CMOS晶圆，且“井”结构的过渡金属氧化物区域727分布在光电二极管阵列716上方。
图37为将图36A中形成了图案化过渡金属氧化物层的CMOS晶圆7-20A(因上述图36A，图36B，图36C后续工艺一致，因此后续发明内容只采用图36A所示的图案化晶圆结构进行描述)进行切片工艺之后形成的被切割槽731分开的多个单颗芯片7-30的截面图。切片工艺与实施例1中图2中类似。
图38为将图37中所示的芯片进行芯片贴装及引线键合之后形成的芯片结构7-40的截面图。图38为测序芯片组装工艺中的前2步，首先将单颗芯片通过胶水或粘合剂贴合到封装衬底741上。封装衬底741可为一种LGA封装形式的衬底，衬底正面具有与芯片进行电连接的焊盘742，衬底背面具有与外部设备进行电连接的触点743，焊盘742与触点743通过衬底内部的布线一一对应。然后通过引线键合的方法将芯片上的焊盘719与衬底上的焊盘742进行电连接，从而将芯片上传出的电信号通过引线传出但衬底上，再通过衬底与外部设备的接口传出到外部设备上。应认识到本说明中的衬底包括但不局限与LGA形式，任何合适封装衬底形式都可应用于本发明中，且芯片贴片工艺中用到的胶水或粘合剂也应包含但不限于任何封装工艺中使用的胶水或粘合剂，引线键合工艺中的金属连线也包括但不限于金线、铝线等。
图39为将图38所示的芯片结构7-40进行盖子结构贴合之后形成的测序芯片7-50的截面图。本图中，一个包含流体通道753、进出液口752及支撑结构的盖子结构751通过胶水或粘合剂被贴合在CMOS图像传感器芯片及衬底上，形成一个测序芯片。其中流体通道753形成在图案化过渡金属氧化物层之上，且将液体限制在一定空间范围内，而不会使液体接触到流体通道之外的焊盘、引线等其他通电区域。应认识到盖子751可为任何合适材质(如包括但不限于任何颜色的PC，PEI，PEEK，PMMA等)经由任何合适的加工方法(包括但不限于CNC，开模注塑，3D打印等)加工而成。且本领域技术人员还应认识到衬底741及盖子751的物理结构应包括但不限于本图所示，任何可实现本图示功能的物理结构都应包含在本发明内。
图40为将图39所示的测序芯片进行表面功能化修饰处理之后形成的测序芯片7-60的截面图。此图中的功能化处理工艺与实施例1中图4类似。
图41A为将图40所述的经过功能化处理的测序芯片7-60进行DNB装载之后形成的具有DNB阵列的测序芯片7-70A的截面图。此图中示出的DNB装载工艺与实施例1中图5中类似，不同之处在于，此方法中被荧光标记物标记了的DNB通过生物或化学方法发光，而不需要借助外部的激发光源，因此DNB阵列通过生物或化学方法发出的光被图像传感器上的光电二极管阵列捕捉，并被处理电路输出为电信号。根据DNB阵列在不同时间、不同像素点(光电二极管)发光的情况，可识别出DNB的碱基排布。
图41B为另一种更简洁、不需要表面功能化处理的DNB装载方法。此装载方法如上述图5B所示，并通过上述图41A中所述的方式将DNB发光信号转变为DNB上碱基排布信息。
在本实施例7中，过渡金属氧化物层和第二层氧化硅层在具有第一层氧化硅层的含有光敏结构的CMOS晶圆上形成与上述实施例类似的三种“斑点”或者“井”结构，即包括：1.在第一层氧化硅层上形成阵列式“斑点”结构的过渡金属氧化物层，DNB装载在过渡金属氧化物层“斑点”结构上；2.在第一层氧化硅层上形成一层过渡金属氧化物薄膜，并在过渡金属氧化物薄膜上形成具有阵列式“井”结构的第二层氧化硅层，DNB装载在第二层氧化硅层“井”结构底部的过渡金属氧化物层上；3.在第一层氧化硅层上形成具有阵列式“斑点”结构的过渡金属氧化物层，然后在过渡金属氧化物层之上形成具有阵列式“井”结构的第二层氧化硅层，DNB装载在“井”结构氧化硅层底部的过渡金属氧化物“斑点”结构上。在这三种“斑点”或者“井”结构中，DNB发出的光信号需穿过过渡金属氧化物、第一层氧化硅层及CMOS晶圆上的ARC层(抗反射层，通常为五氧化二钽)、PIN层(通常为二氧化铪)，最终被CMOS晶圆上的光敏结构采集到，因此仿真了DNB发出的光在透过这几层薄膜后能被光敏结构采集到的信号强度。而PIN层和ARC层的厚度是由CMOS晶圆的工艺决定的，通常为确定值，其中PIN层厚度为6纳米，ARC层厚度为50纳米。因此仿真了上述三种“斑点”或者“井”结构中，第一层氧化硅层、过渡金属氧化物层及第二层氧化硅层厚度的变化对荧光信号强度的影响。
首先仿真了本实施例所述的第一种情况，当只具有第一层氧化硅层时，荧光信号强度与第一层氧化层厚度的关系。仿真结果如图41C所示，CMOS晶圆中的光敏结构收集到的光信号强度随第一层氧化层 厚度的增加单调减小。为了与现有标准CMOS工艺兼容以及相应的产品的可靠性考虑，氧化层的厚度可选为150nm。
然后又仿真了当第一层氧化硅层厚度为150纳米时，第一层氧化硅层上的阵列式“斑点”结构过渡金属氧化物层的厚度与荧光信号强度的关系。仿真结果如图41D所示，CMOS晶圆中的光敏结构收集到的光信号强度随过渡金属氧化层的厚度呈现波动变化。从工艺角度，优化的厚度可选为40-50nm。
然后仿真了本实施例7中的第二种情况，当第一层氧化硅层厚度为150纳米时，在第一层氧化硅层上再形成一层过渡金属氧化物层薄膜，首先为了确定该层过渡金属氧化物层薄膜的厚度，仿真了该厚度与荧光信号强度的关系。仿真结果如图41E所示，荧光信号强度随着过渡金属氧化物层薄膜厚度增加而波动变化，当厚度为10～20纳米时，荧光信号强度最大。
然后又仿真了在此基础上再形成“井”结构的第二层氧化硅层时，第二层氧化硅厚度与荧光信号强度的关系。仿真结果如图41F所示，当过渡金属氧化物层的厚度确定后，此结构收集到的光信号强度与第二层氧化层厚度相关性可忽略不计。考虑到做DNA测序的流体需求，第二层氧化层厚度太大，使得表面的结构太深容易导致流体死区，影响测序质量。第二层氧化层厚度适中可以更加有效使得待测DNA基团落在有效区域，第二层氧化层厚度可以选为50-100nm。
实施例8另一种可重复利用的测序芯片封装方式
在本实施例中，提出了一种新的测序芯片封装方式，该种封装方式的测序芯片可在经过特殊的处理工艺后再重复利用，使测序芯片的成本大幅降低。
首先需在一张半导体晶圆上形成具有过渡金属氧化物“斑点”或“井”结构的图案化阵列，这个阵列式图案化结构可为上述实施例1～3中图1、图7和图13中的晶圆上的结构的其中之一，在本实施例中以实施例1中图1中的结构为示例来描述这种可重复利用的测序芯片的制造工艺过程，本发明中所包括的其他测序芯片结构也可用相同的封装工艺来制备成可重复利用的测序芯片。
如图42所示为与实施例1中图1一样的一种具有阵列式“斑点”结构的过渡金属氧化物层的晶圆结构8-10的截面图，其中氧化硅层812形成在半导体晶圆衬底811上，“斑点”结构的过渡金属氧化物层813形成在氧化硅层812之上，各步工艺过程及材料要求与实施例1中图1中的描述一致。
如图43为将图42所示的晶圆结构8-10进行切片工艺后形成的多个单颗芯片81和82后的晶圆结构8-20的截面图，其中切片工艺与实施例1中图2中类似。
如图44为将图43中形成的单颗芯片81或82与一个把手结构831组装后形成的可重复利用的测序芯片8-30的截面图。其中把手结构831的作用为，通过将把手结构与单颗芯片进行固定形成测序芯片，可以利用把手结构对测序芯片进行抓取、转移等操作，从而进行DNB的装载及测序。图44中只示意性的画出了一个“L”型的扶手结构，本领域技术人体应认识到任何能实现上述功能的扶手结构都包含在本发明中，本发明中也不限制扶手结构的数量，可用多个扶手结构与单颗芯片进行封装。扶手结构的材料可选用与DNB装载及测序试剂兼容的、成本低、易加工且不易老化磨损的塑料或金属，如包括但不限于聚醚醚酮，聚碳酸酯，聚甲基丙烯酸甲酯等高分子塑料类，或铝合金、不锈钢等金属类。可选用固体或液体类的粘合剂来将单颗芯片和扶手结构粘合在一起，任何与DNB装载及测序试剂兼容的粘合剂都可用于本专利中。
如图45所示为将图44中所示的组装好的测序芯片浸入到一个装了试剂842的容器841中，其中试剂842可为芯片表面修饰、DNB装载及测序过程中任何试剂，在一次表面修饰、DNB装载及测序过程中，可具有多个容器841，并分别装着不同的试剂842，可通过抓取测序芯片的把手结构来使测序芯片在不同的容器及试剂中切换，从而进行不同的反应。在本图45示中，测序芯片上的DNB结合位点区域(“斑点”结构过渡金属氧化物层)上进行完装载着DNB，可通过一个激发光源及照相机843来采集DNB发出的不同波长及能量的光信号，从而进行测序操作。
在进行完一次完整的测序操作后，可对该种封装结构的测序芯片进行处理并重复利用。具体处理方法如下：
将测序结束的测序芯片进行预处理，拆除把手结构，使得整张芯片完全裸露在外。随后将芯片浸入SC1洗液(Slide Clean 1，含有Triton的50mM氢氧化钾溶液)中10分钟，随后取出，使用去离子水反复清洗芯片表面3次以上，并将芯片置于氮气气流中完全干燥。
以上所述的SC1洗液也可以使用SC2洗液进行替代，具体操作步骤为：将测序结束的测序芯片拆除把手结构，置于SC2洗液中(Slide Clean 2，使用氨水与过氧化氢以一定比例混合)。将洗液加温至80度放置5分钟，随后将芯片取出，使用去离子水反复清洗芯片3此以上，并将芯片置于氮气气流中完全干燥。
以上所述的洗液清洗法也可以使用等离子干燥处理法代替，将测序结束的测序芯片置于氩气等离子气氛中30分钟，取出后使用去离子水清洗除去灰尘，并将芯片置于氮气气流中完全干燥。
实施例9芯片表面不进行修饰，通过改变装载条件来形成微阵列
采用二氧化硅表面模拟非结合位点区域，二氧化钛、五氧化二钽表面过渡金属氧化物模拟结合位点区域。使用等离子体清洗机对三种表面进行清洗，随后使用乙醇进行进一步清洗。使用条件优化过的DNB溶液(改变溶液pH及表面活性剂含量)(160BP,10ng/uL)在芯片表面进行DNB加载，DNB加载完成后使用cy3染料对DNB进行荧光标记，随后使用荧光显微镜对芯片表面进行分析，结果如图46所示，其中亮点是加载后的DNB，黑色线条为非功能区较为集中的区域，功能区密度较低(不吸附DNB)。将这种芯片按照前述组装方法制成测序芯片，在Zebra平台上进行上机测序结果如图47所示，使用新型过渡金属氧化物阵列芯片进行DNB加载的加载成功率(GRR值)高于目前使用现有工艺制造的芯片。
结论：由于金属氧化物和二氧化硅表面性质不同，通过改变DNB溶液的pH及表面活性剂等成分，芯片表面功能区可以选择性吸附DNB。
实施例10带有过渡金属氧化物点阵的硅晶体进行选择性功能化后吸附DNB的效果检测
带有过渡金属氧化物点阵的硅晶体芯片在使用等离子体清洗机、乙醇清洗之后被置于10mM氨基乙基膦酸溶液中，浸泡24小时后取出，使用乙醇、水对表面进行清洗。使用X-射线光电子能谱仪对三种表面进行元素分析，结果显示，氨基化前后二氧化硅表面均不含有磷元素的组分，而二氧化钛、五氧化二钽表面的磷元素原子浓度从氨基化之前的0上升到2％。使用与测序一致的DNB溶液(160BP,10ng/uL)在芯片表面进行DNB加载，DNB加载完成后使用cy3染料对DNB进行荧光标记，随后使用荧光显微镜对芯片表面进行分析，结果如图48所示。图48中可见过渡金属氧化物经氨基膦酸修饰后对DNB有良好的吸附效果，同时二氧化硅非结合区域(图中黑色线条)对DNB的吸附相当有限。
其中，带有过渡金属氧化物点阵的硅晶体芯片是将工厂使用的二氧化硅元晶的表面氧化之后，使用ALD镀过渡金属氧化物点阵的方式制备的。
结论：二氧化硅表面无任何氨基膦酸成分，二氧化钛、五氧化二钽表面均可检测到氨基磷酸成分，可以证明膦酸反应的选择性。修饰后的表面可以选择性的对过渡金属氧化物区域进行选择性氨基化并实现芯片表面功能区特异性吸附DNB的效果。
实施例11使用含有聚乙二醇的共聚物对非功能区域的进一步修饰的效果检测
本实施例采用特殊订制的芯片进行，芯片上过渡金属氧化物区域尺寸为200微米，间隔为500微米。芯片使用与实施例9中相同的清洗、氨基膦酸修饰处理后，在10mg/mL聚乙烯亚胺-聚乙二醇(PEI-PEG)共聚物水溶液中浸泡10分钟，随后使用纯水清洗。随后使用与测序一致的DNB溶液(160BP,10ng/uL)在芯片表面进行DNB加载，DNB加载完成后使用cy3染料对DNB进行荧光标记，随后使用荧光显微镜对芯片表面进行分析，结果如图49所示。图49中可见使用共聚物对二氧化硅非结合区域进行处理后，表面的非特异性吸附得到进一步的降低。
结论：使用含有聚乙二醇的共聚物可以进一步降低芯片表面非功能区对DNB及杂质的吸附。
实施例12使用含有聚乙二醇的硅烷偶联剂对非功能区域的进一步修饰的效果检测
带有过渡金属氧化物点阵的硅晶体芯片在使用等离子体清洗机、乙醇清洗之后被置于阿仑膦酸和聚乙二醇改性的硅烷偶联剂溶液中，反应一段时间后取出，用乙醇和水清洗。随后使用与测序一致的DNB溶液(160BP,10ng/uL)在芯片表面进行DNB加载，DNB加载完成后使用cy3染料对DNB进行荧光标记，随后使用荧光显微镜对芯片表面进行分析，如图50所示。
结论：使用含有聚乙二醇的硅烷偶联剂可以进一步降低二氧化硅表面非功能区对DNB及杂质的吸附。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些 示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本发明的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本发明的限制，本领域的普通技术人员在本发明的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (31)

  1. 一种芯片基质，其特征在于，包括：
    晶圆层，所述晶圆层上具有均匀分布的切割线；
    第一氧化硅层，所述第一氧化硅层由氧化硅构成，形成在所述晶圆层的上表面；
    过渡金属氧化物层，所述过渡金属氧化物层由过渡金属氧化物构成，形成在所述第一氧化硅层的上表面。
  2. 根据权利要求1所述的芯片基质，其特征在于，所述过渡金属氧化物层由数个不相连的过渡金属氧化物斑点构成。
  3. 根据权利要求2所述的芯片基质，其特征在于，所述过渡金属氧化物斑点的厚度为10-20nm，所述第一氧化硅层的厚度为80-100nm，优选为90nm。
  4. 根据权利要求2所述的芯片基质，其特征在于，所述过渡金属氧化物斑点上进一步连接有氨基；
    任选地，所述数个不相连的过渡金属氧化物斑点之间的第一氧化硅层上进一步连接有聚乙二醇。
  5. 根据权利要求1或2所述的芯片基质，其特征在于，进一步包括第二氧化硅层；
    任选地，所述过渡金属氧化物层为连续层结构，所述第二氧化硅层由氧化硅呈数个相连的井字形成在所述过渡金属氧化物层上表面；
    任选地，所述过渡金属氧化物层由数个不相连的过渡金属氧化物斑点构成，所述第二氧化硅层形成在所述数个不相连的过渡金属氧化物斑点之间的第一氧化硅层的上表面。
  6. 根据权利要求5所述的芯片基质，其特征在于，所述晶圆为硅晶圆，所述第二氧化硅层的厚度为40-60nm，优选为50nm，所述过渡金属氧化物层的厚度为5-15nm，所述第一氧化硅层的厚度为80-100nm，优选为90nm；
    任选地，所述晶圆为石英晶圆，所述第二氧化硅层的厚度为100-200nm，所述过渡金属氧化物层的厚度为10-20nm，所述第一氧化硅层的厚度为80-100nm，优选为90nm。
  7. 根据权利要求5所述芯片基质，其特征在于，所述第二氧化硅层井字格凹陷处的所述过渡金属氧化物层或所述过渡金属氧化物斑点上进一步连接有氨基；
    任选地，所述第二氧化硅层上进一步连接有聚乙二醇。
  8. 根据权利要求4或7所述的芯片基质，其特征在于，所述氨基与所述过渡金属氧化物层中的过渡金属氧化物分子至少一部分通过化学键相连；
    任选地，所述化学键是由过渡金属氧化物分子与氨基膦酸类化合物的磷酸基团连接形成的。
  9. 根据权利要求4或7所述的芯片基质，其特征在于，所述聚乙二醇是由包括选自选自聚乙烯亚胺-聚乙二醇和含有聚乙二醇的硅烷偶联剂的至少之一提供的。
  10. 根据权利要求9所述的芯片基质，其特征在于，所述聚乙二醇是由聚乙烯亚胺-聚乙二醇提供的，所述聚乙烯亚胺-聚乙二醇通过静电吸附在所述第一氧化硅层表面或第二氧化硅层表面。
  11. 根据权利要求9所述的芯片基质，其特征在于，所述聚乙二醇是由含有聚乙二醇的硅烷偶联剂提供的，所述含有聚乙二醇的硅烷偶联剂通过-Si-O-Si-链与所述第一氧化硅层或第二氧化硅层相连。
  12. 根据权利要求1-11任一项所述的芯片基质，其特征在于，所述晶圆包括选自硅晶圆、石英晶圆、玻璃晶圆以及CMOS晶圆的至少之一。
  13. 根据权利要求1-11任一项所述的芯片基质，其特征在于，所述过渡金属氧化物包括选自二氧化钛、二氧化锆、五氧化二钽、六氧化二铌以及二氧化铪的至少之一。
  14. 根据权利要求13所述的芯片基质，其特征在于，所述过渡金属氧化物包括选自二氧化钛、二氧化锆、五氧化二钽的至少之一。
  15. 一种测序芯片，包括芯片主体，其特征在于，所述芯片主体包括数个芯片颗粒，所述芯片颗粒是将权利要求1～14任一项所述的芯片基质沿着晶圆层的切割线进行切割后获得的。
  16. 一种制备权利要求1～14任一项所述的芯片基质的方法，其特征在于，对晶圆层进行表面修饰，所述表面修饰包括利用过渡金属氧化物对所述晶圆层的表面进行处理，以便形成过渡金属氧化物层，所述晶圆层的上表面具有第一氧化硅层，氧化硅层由氧化硅构成，所述过渡金属层形成在所述第一氧化硅层的上表面，所述晶圆层上具有均匀分布的切割线。
  17. 根据权利要求16所述的方法，其特征在于，第一氧化硅层是通过低温等离子体化学气相沉积、等离子体增强化学气相沉积、溅射或原子层沉积法的方法预先在所述晶圆层的上表面形成的。
  18. 根据权利要求16所述的方法，其特征在于，对晶圆层进行表面修饰是通过薄膜沉积、光刻或刻蚀的方法实现的，以便形成连续过渡金属氧化物层或呈斑点排列的过渡金属氧化物层。
  19. 根据权利要求18所述的方法，其特征在于，所述过渡金属氧化物层为连续层结构，进一步包括在所述过渡金属氧化物层的上表面由氧化硅形成呈连续井字形排列的第二氧化硅层；
    任选地，所述过渡金属氧化物层呈斑点排列，进一步包括在所述过渡金属氧化物层斑点之间沉积氧化硅形成第二氧化硅层。
  20. 根据权利要求16-19任一项所述的方法，其特征在于，进一步包括对所述过渡金属氧化物进行氨基化处理。
  21. 根据权利要求20所述的方法，其特征在于，所述氨基化处理是通过将过渡金属氧化物与氨基膦酸类化合物进行反应获得的。
  22. 根据权利要求16-21任一项所述的方法，其特征在于，进一步包括对所述第一氧化硅层或第二氧化硅层进行表面修饰，以便在所述第一氧化硅层或第二氧化硅层引入聚乙二醇。
  23. 根据权利要求22所述的方法，其特征在于，所述聚乙二醇是由包括选自选自聚乙烯亚胺-聚乙二醇和含有聚乙二醇的硅烷偶联剂的至少之一提供的；
    任选地，所述聚乙二醇是由聚乙烯亚胺-聚乙二醇提供的，所述表面修饰是通过将聚乙烯亚胺-聚乙二醇与所述第一氧化硅层表面或第二氧化硅层表面进行静电吸附进行的；
    任选地，所述聚乙二醇是由含有聚乙二醇的硅烷偶联剂提供的，所述表面修饰是通过将含有聚乙二醇的硅烷偶联剂与所述第一氧化硅层或第二氧化硅层的羟基进行缩合反应进行的，所述羟基是由第一或第二氧化硅层电离后吸附水中的氢氧根离子后形成的Si-OH提供的。
  24. 一种制备测序芯片的方法，其特征在于，将芯片颗粒进行组装，所述芯片颗粒是将芯片基质沿着晶圆层的切割线进行切割后获得的，所述芯片基质如权利要求1～14任一项所述限定的或依据权利要求16～23任一项所述的方法获得。
  25. 根据权利要求24所述的方法，其特征在于，所述切割是通过半导体晶圆切割方法实现的。
  26. 根据权利要求24所述的方法，其特征在于，所述组装包括将所述芯片颗粒放置于一个含进出液口的支撑框架中，并用胶水或粘合剂将芯片颗粒与支撑框架贴合形成的，所述框架与所述芯片颗粒之间形成流体通道。
  27. 根据权利要求26所述的方法，其特征在于，所述晶圆为硅晶圆，所述组装包括：所述芯片颗粒的上表面朝上与所述支撑框架贴合，将一个盖玻片设置在芯片颗粒的上表面，以便获得所述测序芯片。
  28. 根据权利要求26所述的方法，其特征在于，所述晶圆为石英晶圆或玻璃晶圆，所述组装包括：所述芯片颗粒的下表面朝上与所述支撑框架贴合，以便获得所述测序芯片。
  29. 根据权利要求24所述的方法，其特征在于，所述晶圆为CMOS晶圆，所述组装包括：将所述芯片颗粒的下表面与衬底贴合，所述芯片颗粒与所述衬底通过引线连接，所述引线用于将芯片颗粒上的电信号传输到衬底上。
  30. 一种测序方法，其特征在于，利用测序芯片进行测序，所述测序芯片如权利要求15所限定的或依据权利要求24-29任一项所述的方法制备的。
  31. 根据权利要求30所述的方法，其特征在于，所述测序芯片的过渡金属氧化物层预先固定有DNB。
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