WO2020095596A1

WO2020095596A1 - Imaging device

Info

Publication number: WO2020095596A1
Application number: PCT/JP2019/039468
Authority: WO
Inventors: 俊介磯野; 竜典百瀬; 良太境田
Original assignee: パナソニックＩｐマネジメント株式会社
Priority date: 2018-11-07
Filing date: 2019-10-07
Publication date: 2020-05-14

Abstract

The imaging device according to an embodiment of the present disclosure is provided with a photoelectric conversion layer, a first pixel electrode, a second pixel electrode, a shield electrode, and a first shield via. The photoelectric conversion layer converts incident light into electrical charge. The first pixel electrode collects the electrical charge generated in the photoelectric conversion layer. The second pixel electrode collects the electrical charge generated in the photoelectric conversion layer. The second pixel electrode is adjacent to the first pixel electrode in a first direction. The shield electrode is electrically isolated from the first pixel electrode and the second pixel electrode. The first shield via extends from the shield electrode. In plan view, the first shield via is positioned between the first pixel electrode and the second pixel electrode.

Description

Imaging device

The present disclosure relates to an imaging device.

Laminated imaging device is known. The laminated image pickup device has a laminated structure including a semiconductor substrate and a photoelectric conversion layer.

An example of a laminated image pickup device is described in Patent Documents 1 and 2. In the imaging devices of Patent Documents 1 and 2, the photoelectric conversion layer is arranged between the counter electrode and the pixel electrode.

International Publication No. 2013/001809 JP, 2016-127264, A

Demand for technology to obtain higher resolution images.

An imaging device according to an aspect of the present disclosure,
A photoelectric conversion layer for converting incident light into an electric charge,
A first pixel electrode for collecting charges generated in the photoelectric conversion layer;
A second pixel electrode adjacent to the first pixel electrode in the first direction, collecting the charges generated in the photoelectric conversion layer;
A shield electrode electrically separated from the first pixel electrode and the second pixel electrode;
A first shield via extending from the shield electrode and located between the first pixel electrode and the second pixel electrode in plan view;
Equipped with.

The present disclosure provides a technique for obtaining a high-resolution image.

FIG. 1 is a diagram showing a cross-sectional structure of the image pickup apparatus according to the embodiment. FIG. 2 is a diagram showing a cross-sectional structure of the image pickup apparatus according to the embodiment. FIG. 3 is a diagram showing a planar structure of the image pickup apparatus according to the embodiment. FIG. 4A is a diagram showing a cross-sectional structure of the imaging device according to the embodiment. FIG. 4B is a partially enlarged view of FIG. 4A. FIG. 4C is a diagram showing an insulating portion according to an example different from the example in FIG. 4B. FIG. 4D is a schematic diagram showing a method for manufacturing an insulating layer and a photoelectric conversion layer. FIG. 4E is a schematic diagram showing a method for manufacturing an insulating layer and a photoelectric conversion layer. FIG. 5A is a diagram showing a cross-sectional structure of the imaging device according to the embodiment. FIG. 5B is a partially enlarged view of FIG. 5A. FIG. 6 is a diagram showing the protruding portion of the photoelectric conversion layer. FIG. 7 is a diagram showing a cross-sectional structure of the image pickup apparatus according to the embodiment. FIG. 8 is a diagram showing a planar structure of the image pickup apparatus according to the embodiment. FIG. 9A is a diagram showing a planar structure of the image pickup apparatus according to the embodiment. FIG. 9B is a partially enlarged view of FIG. 9A. FIG. 9C is a partially enlarged view according to an example different from the example in FIG. 9B. FIG. 9D is a partially enlarged view of FIG. 9A. FIG. 9E is a partially enlarged view of FIG. 9A. FIG. 10 is a block diagram of the camera system.

(Outline of One Aspect According to the Present Disclosure)
The imaging device according to the first aspect of the present disclosure is
A photoelectric conversion layer for converting incident light into an electric charge,
A first pixel electrode for collecting charges generated in the photoelectric conversion layer;
A second pixel electrode adjacent to the first pixel electrode in the first direction, collecting the charges generated in the photoelectric conversion layer;
A shield electrode electrically separated from the first pixel electrode and the second pixel electrode;
A first shield via extending from the shield electrode and located between the first pixel electrode and the second pixel electrode in plan view;
Equipped with.

The first mode is suitable for obtaining a high-resolution image.

In the second aspect of the present disclosure, for example, the imaging device according to the first aspect is
A third pixel electrode adjacent to the first pixel electrode in a second direction different from the first direction, the charge being generated in the photoelectric conversion layer;
A second shield via extending from the shield electrode and located between the first pixel electrode and the third pixel electrode in the plan view;
May be further provided.

The second mode is suitable for obtaining a high-resolution image.

In the third aspect of the present disclosure, for example, the imaging device according to the first aspect is
A third pixel electrode adjacent to the first pixel electrode in a second direction different from the first direction, the charge being generated in the photoelectric conversion layer;
A fourth pixel electrode that collects charges generated in the photoelectric conversion layer, is adjacent to the second pixel electrode in the second direction, and is adjacent to the third pixel electrode in the first direction;
A third shield via extending from the shield electrode and located between the first pixel electrode and the fourth pixel electrode in the plan view;
May be further provided.

The third mode is suitable for obtaining a high-resolution image.

In the fourth aspect of the present disclosure, for example, the imaging device according to the second aspect is
A fourth pixel electrode that collects charges generated in the photoelectric conversion layer, is adjacent to the second pixel electrode in the second direction, and is adjacent to the third pixel electrode in the first direction;
A third shield via extending from the shield electrode and located between the first pixel electrode and the fourth pixel electrode in the plan view;
May be further provided.

The fourth mode is suitable for obtaining a high-resolution image.

In the fifth aspect of the present disclosure, for example, the imaging device according to any one of the first to fourth aspects,
A first pixel via extending from the first pixel electrode;
A second pixel via extending from the second pixel electrode;
May be further provided.

The first pixel via of the fifth aspect can electrically connect the first pixel electrode to another element. The second pixel via can electrically connect the second pixel electrode to another element.

In the sixth aspect of the present disclosure, for example, in the imaging device according to the fifth aspect,
In the plan view, the first shield via may be located between the first pixel via and the second pixel via.

The sixth mode is suitable for obtaining a high-resolution image.

In the seventh aspect of the present disclosure, for example, an imaging device according to any one of the first to sixth aspects,
A first wiring layer may be further provided,
The first shield via may extend from the shield electrode to the first wiring layer.

⑦ The 7th mode is suitable for obtaining high-resolution images.

In the eighth aspect of the present disclosure, for example, the imaging device according to any one of the first to seventh aspects,
An insulating portion located between the shield electrode and the photoelectric conversion layer may be further provided.

The eighth mode is suitable for obtaining a high-resolution image by the shield electrode while suppressing the decrease in sensitivity of the image pickup device due to the shield electrode.

In the ninth aspect of the present disclosure, for example, in the imaging device according to the eighth aspect,
In the plan view, the insulating portion may include a portion that does not overlap with the shield electrode.

The ninth mode is suitable for obtaining a high-resolution image.

An imaging device according to a tenth aspect of the present disclosure is
A photoelectric conversion layer for converting incident light into an electric charge,
A first pixel electrode for collecting charges generated in the photoelectric conversion layer;
A shield electrode electrically separated from the first pixel electrode,
An insulating portion located between the shield electrode and the photoelectric conversion layer,
Equipped with
In plan view, the insulating portion includes a portion that does not overlap with the shield electrode.

The tenth aspect is suitable for obtaining a high-resolution image by the shield electrode while suppressing a decrease in the sensitivity of the imaging device due to the shield electrode.

In the eleventh aspect of the present disclosure, for example, in the imaging device according to the ninth aspect or the tenth aspect,
In the plan view, the insulating portion may be separated from the first pixel electrode.

The eleventh aspect is suitable for capturing a signal charge by the first pixel electrode and obtaining an image with high resolution.

In the twelfth aspect of the present disclosure, for example, in the imaging device according to any one of the eighth to eleventh aspects,
The insulating portion may have a film shape,
The thickness of the film shape may be 10 nm or more.

The twelfth aspect is suitable for suppressing a decrease in sensitivity of the image pickup device due to the shield electrode.

In the thirteenth aspect of the present disclosure, for example, in the imaging device according to any one of the first to twelfth aspects,
The surface of the first pixel electrode and the surface of the shield electrode may be on the same plane.

The imaging device of the thirteenth aspect is easy to manufacture.

In the fourteenth aspect of the present disclosure, for example, the imaging device according to any one of the first to thirteenth aspects may be a color image sensor.

In the color image sensor, the technique of the first aspect can contribute to suppression of color mixture.

An imaging device according to a fifteenth aspect of the present disclosure is
A photoelectric conversion layer for converting incident light into an electric charge,
A first pixel electrode for collecting charges generated in the photoelectric conversion layer;
A shield electrode electrically separated from the first pixel electrode,
An insulating portion located between the shield electrode and the photoelectric conversion layer,
Equipped with.

In this specification, the term "via" may be used. In this specification, the via hole and the conductor inside thereof are collectively referred to as a "via".

In this specification, the terms “shield via” and “pixel via” may be used. In the exemplary embodiment shown below, the shield via extends from the shield electrode. The pixel via extends from the pixel electrode. The terms “shield via” and “pixel via” are used properly for the convenience of description, and are not intended to limit the features of the via.

In this specification, the ordinal numbers first, second, third ... May be used. When an element has an ordinal number, it is not mandatory that there be a younger element of the same type. You can change the ordinal number if necessary.

Each of the embodiments described below shows a comprehensive or specific example. Numerical values, shapes, materials, components, arrangements and connection forms of components, steps, order of steps, and the like shown in the following embodiments are examples and are not intended to limit the present disclosure. The various aspects described in this specification can be combined with each other as long as there is no conflict. Further, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims showing the highest concept are described as arbitrary constituent elements. In the following description, components having substantially the same function are designated by common reference numerals, and redundant description may be omitted or simplified.

The comprehensive or specific aspects may be realized by an element, device, apparatus, system, integrated circuit, method, or computer program. In addition, the comprehensive or specific aspects may be realized by any combination of elements, devices, apparatuses, systems, integrated circuits, methods, and computer programs. Additional advantages and advantages of the disclosed embodiments will be apparent from the specification and drawings. The benefits and / or advantages are provided individually by the various embodiments or features disclosed in the specification and drawings, and not all are required to obtain one or more of these.

The various elements shown in the drawings are merely schematic for understanding of the present disclosure, and the dimensional ratio and the appearance may be different from the actual ones.

An imaging device according to one embodiment of the present disclosure is a silicon-based device that has a photoelectric conversion layer that converts light into an electric signal, that is, performs photoelectric conversion, in an upper layer and takes out an electric signal obtained in a photoelectric conversion portion to the outside. A signal processing circuit including a CMOS (Complementary Metal Oxide Semiconductor) circuit is provided in a lower layer. As described above, in the imaging device according to the aspect of the present disclosure, the photoelectric conversion unit and the signal processing circuit are stacked, so that they can be designed independently.

[Embodiment]
1 and 2 are cross-sectional views of the image pickup apparatus 100 according to the embodiment.

The imaging device 100 includes the semiconductor substrate 1 and the pixel unit 30. The pixel portion 30 is provided on the semiconductor substrate 1.

The pixel section 30 includes a plurality of pixel electrodes 3, a counter electrode 5, and a photoelectric conversion layer 4. The photoelectric conversion layer 4 is arranged between the pixel electrode 3 and the counter electrode 5. The photoelectric conversion layer 4 has a film shape.

The pixel unit 30 includes the detection circuit 12. A part of the detection circuit 12 is provided in the semiconductor substrate 1. The detection circuit 12 detects the potential of the pixel electrode 3.

The pixel unit 30 includes the insulating layer 2. The insulating layer 2 is arranged between the photoelectric conversion layer 4 and the semiconductor substrate 1.

In the pixel section 30, the detection circuit 12 is configured so as to cross the interface between the semiconductor substrate 1 and the insulating layer 2. Specifically, the detection circuit 12 corresponding to each of the plurality of pixels 20 is configured.

For convenience of description, the terms X axis, Y axis, and Z axis may be used below. These axes are orthogonal to each other. Further, for convenience of description, the positive side in the Z-axis direction may be referred to as the top. The main surface on the plus side in the Z-axis direction may be called the upper surface. In this example, the upper surface is the surface near the light incident side. The lower surface is the surface far from the light incident side. In this example, the vertical direction is a direction perpendicular to the surface of the semiconductor substrate 1.

The pixel electrode 3 is formed on the upper surface of the insulating layer 2. A pixel via 13 is connected to the pixel electrode 3. The pixel via 13 extends from the pixel electrode 3 to the first wiring layer 14. The first wiring layer 14 is a layer closest to the pixel electrode 3 among the plurality of wiring layers. The pixel via 13 electrically connects the pixel electrode 3, the wiring layer, and the detection circuit 12 corresponding to the pixel electrode 3.

Each of the plurality of pixels 20 includes a photoelectric conversion unit 11. The photoelectric conversion section 11 includes a pixel electrode 3, a counter electrode 5, and a photoelectric conversion layer 4. As described above, the photoelectric conversion layer 4 is arranged between the pixel electrode 3 and the counter electrode 5.

The photoelectric conversion layer 4 converts incident light into electric charges.

The pixel electrode 3 collects the electric charge generated in the photoelectric conversion layer 4.

An example of the material of the pixel electrode 3 is a metal compound such as titanium nitride (TiN). Other examples of the material of the pixel electrode 3 are metals such as copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), and aluminum (Al). The material of the pixel electrode 3 may be a compound or alloy formed by selecting at least two kinds from these metals. The pixel electrode 3 may include a laminated structure formed by selecting at least two kinds from these metals. The laminated structure is, for example, a TiN / Ti structure. The TiN / Ti structure is a laminated structure in which a titanium nitride layer and a titanium layer are joined.

In one specific example, the film thickness of each of the plurality of pixel electrodes 3 is uniform. The upper surface of each of the plurality of pixel electrodes 3 is flat.

As shown in the cross-sectional view of FIG. 1, the plurality of pixel electrodes 3 are located between the photoelectric conversion layer 4 and the semiconductor substrate 1.

As shown in the plan view of FIG. 3, the plurality of pixel electrodes 3 are arranged in a two-dimensional direction extending in the X-axis direction and the Y-axis direction. The plurality of pixel electrodes 3 are arranged on the upper surface of the insulating layer 2.

In one specific example, the plurality of pixel electrodes 3 are arranged in a matrix. Here, the expression that a plurality of elements are arranged in a matrix means that the center of each element is located on the intersection of the lattice. The plurality of pixel electrodes 3 have a constant distance from each other.

The pixel electrodes 3 are arranged corresponding to the arrangement of the pixels 20. In one example, the plurality of pixels 20 are arranged in a matrix. The plurality of pixel electrodes 3 are arranged in a matrix according to the arrangement of the plurality of pixels 20.

Refer to FIG. 1 again. As described above, in the imaging device 100, the detection circuit 12 corresponding to each of the plurality of pixels 20 is configured. The detection circuit 12 detects the signal charge collected by the corresponding pixel electrode 3 and outputs a signal voltage according to the charge.

The detection circuit 12 includes, for example, a MOS (Metal Oxide Semiconductor) circuit, a TFT (Thin Film Transistor) circuit, and the like. The detection circuit 12 includes, for example, an amplification transistor whose gate is electrically connected to the pixel electrode 3, and the amplification transistor outputs a signal voltage according to the amount of signal charge. The detection circuit 12 may be shielded from light by a light shielding layer provided inside the insulating layer 2. Illustration of the light shielding layer is omitted.

The pixel via 13 electrically connects the pixel electrode 3 of each pixel 20, the wiring layer, and the detection circuit 12 corresponding to the pixel electrode 3.

An example of the material of the pixel via 13 is a conductive material such as copper (Cu), tungsten (W), cobalt (Co). The pixel via 13 is embedded in the insulating layer 2.

The insulating layer 2 is formed on the semiconductor substrate 1. The insulating layer 2 includes a plurality of

constituent layers

2a, 2b, 2c, 2d and 2e.

The semiconductor substrate 1 is made of, for example, silicon (Si). The plurality of

constituent layers

2a, 2b, 2c, 2d and 2e are composed of, for example, silicon dioxide (SiO ₂ ), a silicon carbide oxide film (SiOC) or the like.

A wiring layer is embedded in each of the

constituent layers

2a, 2b, 2c, 2d and 2e. The wiring layer has wiring. The wiring layer and the wiring layer are connected by a via. Therefore, although the insulator of the insulating layer 2 is provided between the wiring layers, the wiring layers are electrically connected by the vias. The number of constituent layers in the insulating layer 2 can be set arbitrarily and is not limited to the example of the five

constituent layers

2a, 2b, 2c, 2d and 2e shown in FIG. The same applies to the number of wiring layers.

The pixel electrode 3 is arranged on the constituent layer 2e. The photoelectric conversion layer 4 is stacked on the upper surfaces of the constituent layer 2e and the pixel electrode 3. On the upper surface of the photoelectric conversion layer 4, the counter electrode 5, the buffer layer 6, and the sealing layer 7 are laminated in this order. On the upper surface of the sealing layer 7, a color filter 8 in the transmission wavelength range corresponding to each pixel 20 is arranged. A flattening layer 9 is arranged on the upper surface of the color filter 8. The microlens 10 is arranged on the upper surface of the flattening layer 9. The constituent layers of the insulating layer 2 are inserted in the gaps between the adjacent pixel electrodes 3.

In this example, the imaging device 100 is a color image sensor. However, it is also possible to omit the color filter 8. That is, the imaging device 100 may be a monochrome image sensor.

The photoelectric conversion layer 4 is composed of a photoelectric conversion material that generates an electric charge according to the intensity of received light. The photoelectric conversion material is, for example, an organic semiconductor material and includes at least one of a p-type organic semiconductor and an n-type organic semiconductor. In one specific example, the photoelectric conversion layer 4 has a uniform film thickness in the pixel region 30. In another specific example, the photoelectric conversion layer 4 has two or more portions having different film thicknesses in the pixel region 30.

The counter electrode 5 faces the pixel electrode 3. Specifically, the counter electrode 5 faces the plurality of pixel electrodes 3 and a shield electrode 61, which will be described later, with the photoelectric conversion layer 4 sandwiched in the pixel section 30. The counter electrode 5 is arranged on the light incident side of the imaging device 100 when viewed from the photoelectric conversion layer 4. The counter electrode 5 may have a light-transmitting property in order to allow light to enter the photoelectric conversion layer 4. Examples of the material of the counter electrode 5 include transparent oxide conductive materials such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

The expression "the first element faces the second element with the third element sandwiched therebetween" is limitedly interpreted to refer to only the aspect in which the first element and the second element are in contact with the third element. Should not be. For example, the expression “the counter electrode 5 is opposed to the pixel electrode 3 and the shield electrode 61 with the photoelectric conversion layer 4 in between” means that an insulating portion 62 described later is provided between the shield electrode 61 and the photoelectric conversion layer 4. Is included, and the contact between the shield electrode 61 and the photoelectric conversion layer 4 is blocked by this intervention.

Next, I will explain the imaging mechanism.

Light incident on the imaging device 100 from above passes through the sealing layer 7, the buffer layer 6, and the counter electrode 5 and is incident on the photoelectric conversion layer 4. The photoelectric conversion layer 4 photoelectrically converts incident light in a state in which an appropriate bias voltage is applied by the pixel electrode 3 and the counter electrode 5 to generate electric charges. The bias voltage is a potential difference between the counter electrode 5 and the pixel electrode 3.

The electric charge generated in the photoelectric conversion layer 4 as described above is transferred from the pixel electrode 3 to the storage region in the detection circuit 12 via the pixel via 13 and is temporarily stored. Then, the electric charge is output to the outside of the detection circuit 12 as a signal at appropriate time by the opening / closing operation of the transistor element in the detection circuit 12.

(Shield electrode)
In the stacked image pickup device 100 according to the above description, the photoelectric conversion layer 4 is arranged between the pixel electrode 3 and the counter electrode 5. As shown in FIG. 3, a shield electrode 61 is arranged in a region 60 between the

pixel electrodes

3 and 3. Specifically, the insulating layer 2 and the shield electrode 61 are arranged in the region 60. Note that the illustration of the insulating layer 2 is omitted in FIG. 3. In the example of FIG. 3, the region 60 has a lattice shape in plan view. The plan view means, for example, observation in a direction perpendicular to the surface of the semiconductor substrate 1.

Assuming that the shield electrode 61 does not exist. In this case, the electric field strength applied to the portion of the photoelectric conversion layer 4 overlapping the region 60 is smaller than that of the portion overlapping the pixel electrode 3 in plan view. Therefore, in the portion of the photoelectric conversion layer 4 that overlaps the region 60, the electric field strength that the signal charge receives from the pixel electrode 3 is relatively small.

-Signal charges may exist even in the above-mentioned overlapping portions. The signal charge may reach the pixel electrode 3 adjacent to the pixel electrode 3 instead of the pixel electrode 3 which should originally reach. When the signal charges that have reached the adjacent pixel electrodes 3 are detected as the pixel signals of the adjacent pixels, the resolution is reduced. A shield electrode can be used from the viewpoint of suppressing a decrease in resolution. When the imaging device 100 is a color image sensor, color mixture can be suppressed by using a shield electrode.

The shield electrode will be described below with reference to the drawings.

As shown in the sectional view of FIG. 1, the shield electrode 61 is arranged between the photoelectric conversion layer 4 and the semiconductor substrate 1. As shown in FIG. 3, the shield electrode 61 is electrically separated from the plurality of pixel electrodes 3.

In this example, the shield electrode 61 is arranged in the region 60 between the

pixel electrodes

3 and 3. By disposing the shield electrode 61, it becomes possible to apply a voltage to a region between two pixel electrodes 3 adjacent to each other. As a result, the signal charge 65 generated in the portion of the photoelectric conversion layer 4 that overlaps the region 60 in plan view is collected by the shield electrode 61. As a result, it is possible to prevent the signal charge 65, which should originally reach a certain pixel electrode 3, from reaching the adjacent pixel electrode 3. That is, it is possible to suppress mixing of signal charges between adjacent pixels. As a result, an image with high resolution can be obtained. When the image pickup apparatus 100 is a color image sensor, color mixing between adjacent pixels can be suppressed.

Examples of the material of the shield electrode 61 include metals such as copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), and aluminum (Al). The material of the shield electrode 61 may be a compound or alloy formed by selecting at least two kinds from these metals. The shield electrode 61 may include a laminated structure formed by selecting at least two kinds from these metals. The laminated structure is, for example, a TiN / Ti structure.

In one specific example, the film thickness of each shield electrode 61 is uniform. The surface of each shield electrode 61 on the photoelectric conversion layer 4 side is flat.

In the examples shown in FIGS. 1 and 2, the surface of the shield electrode 61 and the surface of the pixel electrode 3 are on the same plane. Specifically, the surface of the shield electrode 61 facing the semiconductor substrate 1 and the surface of the pixel electrode 3 facing the semiconductor substrate 1 are on the same plane. The imaging device having such a configuration is easy to manufacture. However, the surface of the shield electrode 61 and the surface of the pixel electrode 3 do not have to be on the same plane. Specifically, the surface of the shield electrode 61 facing the semiconductor substrate 1 and the surface of the pixel electrode 3 facing the semiconductor substrate 1 do not have to be on the same plane.

The material of the shield electrode 61 and the material of the pixel electrode 3 may be the same. In this case, the shield electrode 61 and the pixel electrode 3 can be formed without requiring separate manufacturing steps. By doing so, the shield electrode 61 and the pixel electrode 3 can be formed in the same manufacturing process and with the same mask. Therefore, it is not necessary to consider misalignment. Here, misalignment means that the relative positional relationship between the shield electrode 61 and the pixel electrode 3 deviates from an appropriate range.

The separation width 71 between the pixel electrode 3 and the shield electrode 61 is, for example, 0.1 μm or more and 1 μm or less.

(Insulating portion between shield electrode 61 and photoelectric conversion layer 4)
When the shield electrode 61 is arranged as shown in FIGS. 1 and 2, a part of the signal charge 65 generated in the photoelectric conversion layer 4 is collected in the shield electrode 61. If the amount of signal charges that can be captured by the pixel electrode 3 decreases due to this collection, the sensitivity of the image pickup device may decrease. An insulating part may be provided between the shield electrode 61 and the photoelectric conversion layer 4 from the viewpoint of suppressing a decrease in sensitivity of the imaging device. Hereinafter, a configuration example in which such an insulating portion is provided will be described with reference to FIGS. 4A, 4B, 4C, 4D, 4E, 5A, 5B and 6.

In the example of FIGS. 4A and 4B, the insulating portion 62 is provided between the shield electrode 61 and the photoelectric conversion layer 4. The insulating portion 62 is an insulator. By providing such an insulating portion 62, the inflow of signal charges into the shield electrode 61 can be maintained while maintaining a state in which an electric field is applied between the counter electrode 5 and a region between two pixel electrodes 3 adjacent to each other. By suppressing the deterioration of the sensitivity of the imaging device. Therefore, this example is suitable for obtaining a high-resolution image by the shield electrode 61 while suppressing a decrease in the sensitivity of the imaging device due to the shield electrode 61.

In the example of FIGS. 4A and 4B, the insulating portion 62 covers the shield electrode 61. The insulating portion 62 specifically covers the entire surface of the shield electrode 61 on the photoelectric conversion layer 4 side.

In the example of FIGS. 4A and 4B, the insulating portion 62 is in contact with the shield electrode 61. Specifically, the insulating portion 62 is in contact with the entire surface of the shield electrode 61 on the photoelectric conversion layer 4 side. The insulating portion 62 blocks contact between the shield electrode 61 and the photoelectric conversion layer 4.

As shown in FIG. 4C, in a plan view, the insulating portion 62 may protrude from the shield electrode 61 and may include a portion that does not overlap with the shield electrode 61. With this configuration, part or all of the contour of the insulating portion 62 can be outside the contour of the shield electrode 61 in plan view. By doing so, an electric field in an obliquely upward direction from the end of the shield electrode 61 toward the photoelectric conversion layer 4 can be suppressed. This is advantageous from the viewpoint of ensuring the insulation between the shield electrode 61 and the pixel electrode 3, for example. In addition, the insulating portion 62 protruding from the shield electrode 61 in a plan view is advantageous from the viewpoint of suppressing the signal charges from wrapping around the insulating portion 62 from the side and flowing into the shield electrode 61. Therefore, the form of FIG. 4C is suitable for obtaining a high-resolution image.

Note that the insulating portion 62 protruding from the shield electrode 61 in a plan view means that the insulating portion 62 includes a portion outside the contour of the shield electrode 61 in a plan view. It can be said that the shield electrode 61 includes a portion located inside the contour of the insulating portion 62 in a plan view. More specifically, the insulating portion 62 protruding from the shield electrode 61 in plan view means not only the case where all the contours of the insulating portion 62 are outside the contour of the shield electrode 61 in plan view, This is a concept including a case where only a part of the outline of the insulating portion 62 exists outside the outline of the shield electrode 61 in a plan view. When seen in a plan view, the entire outline of the insulating portion 62 may be outside the outline of the shield electrode 61, or only a part of the outline of the insulating portion 62 may be outside the outline of the shield electrode 61. Good.

In one specific example, the insulating portion 62 is separated from each pixel electrode 3 in a plan view. With this configuration, the capture of the signal charge by the pixel electrode 3 is unlikely to be hindered by the insulating portion 62. This is suitable for obtaining a high resolution image.

The insulating portion 62 may cover a part of the pixel electrode 3.

In the example of FIGS. 4A and 4B, the pixel electrode 3 and the photoelectric conversion layer 4 are electrically connected. Specifically, the pixel electrode 3 and the photoelectric conversion layer 4 are in contact with each other. However, a blocking layer may be provided between the pixel electrode 3 and the photoelectric conversion layer 4. The blocking layer allows the signal charges of the charge pairs generated by the photoelectric conversion in the photoelectric conversion layer 4 to pass through but blocks the charges other than the signal charges from being injected from the pixel electrode 3. As a result, the signal charge can be efficiently transported to the pixel electrode 3. The blocking layer exhibits a selective charge transport property, and is therefore not an insulator.

Examples of the material of the insulating portion 62 are silicon dioxide (SiO ₂ ), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon carbonitride (SiCN), and the like. Other examples of the material of the insulating portion 62 are a compound of copper (Cu), a compound of titanium (Ti), a compound of tantalum (Ta), a compound of aluminum (Al), and the like. The insulating portion 62 may include a laminated structure formed by selecting at least two kinds from these materials.

The material of the insulating portion 62 may be the same as the material of the insulating layer 2, or may be different from the material of the insulating layer 2.

The insulating portion 62 typically has a film shape. In this example, the thickness direction of the film shape coincides with the direction perpendicular to the surface of the semiconductor substrate 1.

The thickness of the film shape is, for example, 10 nm or more. By increasing the thickness of the film shape to this extent, it is possible to suppress the signal charges from passing through the insulating portion 62 due to the tunnel effect. Therefore, it is possible to suppress the signal charges from being collected by the shield electrode 61. Therefore, setting the thickness of the film shape to 10 nm or more is suitable for suppressing the decrease in the sensitivity of the imaging device due to the shield electrode 61. The thickness of the film shape may be 20 nm or more.

The thickness of the film shape is, for example, 500 nm or less. By reducing the thickness of the film shape to this extent, it is easy to collect signal charges around the shield electrode 61 when a voltage is applied to the shield electrode 61. When the signal charges generated between the pixel electrodes 3 are collected in the vicinity of the shield electrode 61, it is possible to suppress the signal charges from being collected by other than the desired pixel electrode 3. Therefore, setting the thickness of the film shape to 500 nm or less is suitable for obtaining an image with high resolution by the shield electrode 61. The thickness of the film shape may be 300 nm or less.

When the thickness of the film shape is adjusted to an appropriate range, the signal charge collected between the shield electrodes 61 is reduced to a level that can be substantially ignored, and the signal charges generated between the pixel electrodes are generated in the vicinity of the shield electrode 61. Therefore, it is easy to prevent the signal charges from being collected by other than the desired pixel electrode 3. For this reason, it is easy to obtain a high-resolution image while suppressing the decrease in the sensitivity of the imaging device due to the shield electrode 61.

The thickness of the film shape can be specified by a well-known method. The thickness of the film shape can be specified as follows, for example. First, an electron microscope image of the cross section of the film shape is acquired. Next, using the image, the thickness is measured at arbitrary plural measurement points (for example, 5 points) of the film shape. The average value of the thicknesses of the plurality of measurement points is adopted as the thickness of the film shape.

Note that when the above-described specific method is applied to the examples of FIGS. 5A and 5B described later, the side surface 62c is excluded from the measurement point, and the upper surface 62a is set to the measurement point.

The method of forming the insulating portion 62 is not particularly limited.

In one example, the insulating portion 62 is formed as follows. A layer of the material of the insulating portion 62 is formed on the shield electrode 61 (typically, on the entire upper surface of the shield electrode 61). Next, a part of this layer is removed. In this way, the insulating portion 62 is obtained. By doing so, it is possible to obtain the film-shaped insulating portion 62.

The material layer of the insulating portion 62 can be formed by, for example, chemical vapor deposition (CVD). A part of the material layer of the insulating portion 62 can be removed by, for example, lithography, etching or the like.

In plan view, the insulating portion 62 may cover the entire upper surface of the shield electrode 61, the entire upper surface of the insulating layer 2 between the pixel electrode 3 and the shield electrode 61, and a part of the pixel electrode 3. .. By doing so, the position of the step formed at the end of the insulating portion 62 can be on the pixel electrode 3. The advantages obtained by providing the pixel electrode 3 at the step position will be described with reference to FIGS. 4D and 4E. 4D and 4E are schematic views showing a method for manufacturing the insulating layer 2 and the photoelectric conversion layer 4.

In the portion (a) of FIG. 4D and the portion (a) of FIG. 4E, the pixel electrode 3 and the shield electrode 61 are covered with the layer 62x of the material of the insulating portion 62. A part of the layer 62x is covered with the mask 81. A portion of the layer 62x not covered with the mask 81 is removed by etching.

The insulating layer 2 is not shown in the portion (a) of FIG. 4D and the portion (a) of FIG. 4E. In the description relating to FIGS. 4D and 4E, it is assumed that the insulating layer 2 is located between the pixel electrode 3 and the shield electrode 61. 4D and 4E, the upper surface of the insulating layer 2 at the above position is flush with the upper surface of the pixel electrode 3 and the upper surface of the shield electrode 61 before the etching.

In part (a) of FIG. 4D, the mask 81 covers the entire upper surface of the shield electrode 61. However, the mask 81 does not cover the upper surface of the insulating layer 2 between the pixel electrode 3 and the shield electrode 61. Further, the mask 81 does not cover the upper surface of the pixel electrode 3. On the other hand, in the portion (a) of FIG. 4E, the mask 81 covers the entire upper surface of the shield electrode 61 and the entire upper surface of the insulating layer 2 between the pixel electrode 3 and the shield electrode 61. In the portion (a) of FIG. 4E, the mask 81 further partially covers the upper surface of the pixel electrode 3.

By performing etching using the mask 81 in the portion (a) of FIG. 4D, the insulating portion 62 that covers only the entire upper surface of the shield electrode 61 is obtained. On the other hand, by performing etching using the mask 81 of the portion (a) of FIG. 4E, the entire upper surface of the shield electrode 61, the entire upper surface of the insulating layer 2 between the pixel electrode 3 and the shield electrode 61, and the pixel electrode An insulating portion 62 that covers a part of the upper surface of 3 is obtained.

The portion (b) of FIG. 4D and the portion (b) of FIG. 4E show a state in which the portion of the layer 62x not covered with the mask 81 is removed by etching. By this removal, the layer 62x is processed into the insulating portion 62.

Actually, it is difficult to remove only the layer 62x by etching. When the mask 81 is arranged as in the portion (a) of FIG. 4D, the pixel electrode 3 and the insulating layer 2 which are not covered by the mask 81 are also cut to some extent. The pixel electrode 3 and the insulating layer 2 have different etching rates and different degrees of abrasion. Therefore, as shown in the area surrounded by the dotted line 84 in the portion (b) of FIG. 4D, the height of the upper surface is different between the pixel electrode 3 and the insulating layer 2. Further, as shown in the area surrounded by the dotted line 85, there is a difference in the height of the upper surface between the insulating portion 62 and the insulating layer 2. This difference in height of the upper surface occurs at the boundary between the portion covered by the mask 81 and the portion not covered by the mask 81. An alternate long and short dash line 82 in the portion (b) of FIG. 4D represents the positions of the upper surfaces of the pixel electrode 3 and the insulating layer 2.

The same applies when the mask 81 covers the entire upper surface of the shield electrode 61 and partially covers the upper surface of the insulating layer 2 between the pixel electrode 3 and the shield electrode 61. In that case, a difference in the height of the upper surface occurs between the pixel electrode 3 and the insulating layer 2 due to the difference in the etching rate. Further, on the insulating layer 2, there is a difference in height of the upper surface between the portion where the insulating portion 62 is located and the portion where the insulating portion 62 is not located. This difference in height of the upper surface occurs at the boundary between the portion where the insulating layer 62x on the insulating layer 2 is covered with the mask 81 and the portion where the insulating layer 62x is not covered.

On the other hand, when the mask 81 is arranged as in the portion (a) of FIG. 4E, as shown in the dotted line 86 of the portion (b) of FIG. Occurs. This difference occurs at the boundary between the portion covered with the mask 81 and the portion not covered with the mask 81. However, since the insulating layer 2 is completely covered by the insulating portion 62, there is no difference in the height of the upper surface of the insulating layer 2. Therefore, compared to the case of FIG. 4D, the number of steps on the upper surface formed by etching using the mask 81 can be reduced.

The portion (c) of FIG. 4D and the portion (c) of FIG. 4E show a state in which the photoelectric conversion layer 4 is formed on the upper surface formed by etching. When the photoelectric conversion layer 4 is formed on the upper surface formed by etching, the shape of the upper surface is reflected on the shape of the upper surface of the photoelectric conversion layer 4. The two-dot chain line 83 in the portion (c) of FIGS. 4D and 4E represents the position of the upper surface of the photoelectric conversion layer 4.

As can be understood from the above description, the configuration of FIG. 4E is more advantageous than the configuration of FIG. 4D from the viewpoint of flattening the shape of the photoelectric conversion layer 4. From this, the structure in which the insulating portion 62 covers the entire upper surface of the shield electrode 61, the entire upper surface of the insulating layer 2 between the pixel electrode 3 and the shield electrode 61, and a part of the upper surface of the pixel electrode 3 is It can be said that it is advantageous from the viewpoint of flattening the photoelectric conversion layer 4.

In the specific examples shown in FIGS. 4A, 4B, and 4C, the insulating portion 62 has a film shape. As shown in FIGS. 4B and 4C, the film shape has an upper surface 62a, a lower surface 62b, and a side surface 62c. The side surface 62c extends from the lower surface 62b to the upper surface 62a. A corner 62d is formed by the upper surface 62a and the side surface 62c. An angle θ is formed between the lower surface 62b and the side surface 62c. The angle θ is relatively large. Specifically, the angle θ is about 90 °. Therefore, the corner 62d is sharp.

Also in another specific example shown in FIGS. 5A and 5B, the insulating portion 62 has a film shape. In the specific examples of FIGS. 5A and 5B, the angle θ is smaller than in the specific examples of FIGS. 4A, 4B and 4C. In this way, the sharpness of the corner 62d is alleviated, and cracks are less likely to occur at the corner 62d when the photoelectric conversion layer 4 is formed. Thereby, the photoelectric conversion layer 4 is less likely to deteriorate at the contact portion with the insulating portion 62.

Reducing the angle θ or reducing the sharpness of the corner 62d is, for example, a reverse sputtering effect in which the corners of the insulating portion are scraped off by ions in plasma, and the insulating portion is flattened by CMP (Chemical Mechanical Polishing). This can be achieved by removing the corners.

Actually, as shown in FIG. 6, the protrusion 4 p may be formed at a position in the photoelectric conversion layer 4 that overlaps with the insulating portion 62 in a plan view. In the photoelectric conversion layer 4, the protruding portion 4p protrudes in the thickness direction of the film shape of the insulating portion 62 as compared with the peripheral portion of the protruding portion 4p.

The protrusion width PW of the protrusion 4p may be the same as the film thickness TH of the insulating portion 62. However, as shown in FIG. 6, it is possible to make the protrusion width PW smaller than the thickness TH. In other words, the thickness of the portion of the photoelectric conversion layer 4 that overlaps the insulating portion 62 in plan view can be made thinner than the thickness of the periphery of that portion. For example, the protrusion width PW can be reduced by performing heat treatment on the photoelectric conversion layer 4. Note that the protrusion width PW being smaller than the thickness TH is a concept including a case where the protrusion width PW is zero.

As can be understood from the above description, it is possible to realize the photoelectric conversion layer 4 in which the insulating portion 62 is provided and the protruding width PW of the protruding portion 4p is small or the protruding portion 4p does not exist. When the upper surface of the photoelectric conversion layer 4 has high flatness, the layer above the photoelectric conversion layer 4 can be easily manufactured.

In the example of FIG. 6, the thickness of the portion of the photoelectric conversion layer 4 overlapping with the pixel electrode 3 in plan view is larger than the thickness of the portion of the photoelectric conversion layer 4 overlapping with the shield electrode 61 in plan view. This is suitable for promoting photoelectric conversion in the former part and capturing more signal charges in the pixel electrode 3, and suppressing photoelectric conversion in the latter part and suppressing capture of signal charges by the shield electrode 61. ing.

The protruding portion 4p in the photoelectric conversion layer 4 can be formed regardless of whether the insulating portion 62 has the form shown in FIG. 4B or the form shown in FIG. 4C. Also in these cases, PW = TH or PW <TH can be satisfied. Also in these cases, the photoelectric conversion layer 4 without the protruding portion 4p can be realized. Also in these cases, the thickness of the portion of the photoelectric conversion layer 4 that overlaps with the pixel electrode 3 in plan view can be made larger than the thickness of the portion of the photoelectric conversion layer 4 that overlaps with the shield electrode 61 in plan view.

The specific example shown in FIG. 7 can also be adopted. Also in the specific example of FIG. 7, the insulating portion 62 has a film shape. In this specific example, the pixel via 13, the pixel electrode 3, the via 68, and the pixel electrode 69 are sequentially connected from the semiconductor substrate 1 toward the photoelectric conversion layer 4. Therefore, they are electrically connected. The signal charge reaching the pixel electrode 69 flows through the via 68, the pixel electrode 3, and the pixel via 13 in this order.

In the specific example shown in FIG. 7, the insulating portion 62 surrounds the pixel electrode 69 in plan view. The upper surface of the insulating portion 62 and the upper surface of the pixel electrode 69 are flush with each other. The insulating portion 62 also exists between the pixel electrode 3 and the pixel electrode 69.

In the specific example shown in FIG. 7, the upper surface of the shield electrode 61 is covered with the insulating portion 62. The upper surface of the pixel electrode 3 is also covered with the insulating portion 62.

Providing the via 68 and the pixel electrode 69 as in the specific example of FIG. 7 is advantageous from the viewpoint of providing the insulating portion 62 between the shield electrode 61 and the photoelectric conversion layer 4 while flattening the lower surface of the photoelectric conversion layer 4. Is. Therefore, this configuration is advantageous from the viewpoint of suppressing the generation of cracks in the photoelectric conversion layer 4. In particular, when the insulating portion 62 is thick, a large step due to the insulating portion 62 can be formed on the insulating portion 62 or the pixel electrode 69. In that case, since the photoelectric conversion layer 4 is formed on the uneven surface, cracks are likely to occur in the photoelectric conversion layer 4. Therefore, in such a case, the crack suppression effect can be exhibited by using the configuration of FIG. 7. In the specific example of FIG. 7, the film thickness of the insulating portion 62 refers to the thickness of the portion of the insulating portion 62 that overlaps the shield electrode 61 in plan view. The measurement point is set in the portion.

In the example of FIG. 7, an insulator 67 is provided between the pixel electrode 3 and the shield electrode 61. The material of the insulator 67 and the material of the insulating portion 62 may be the same or different. The insulator 67 may be the insulator of the insulating layer 2. Although not shown in FIGS. 4B, 4C, and 5B, the insulating layer 2 serving as an insulator is located between the pixel electrode 3 and the shield electrode 61.

(Shield structure by a via connected to the shield electrode 61)
In the stacked-type imaging device 100, a charge storage region is provided separately from the photoelectric conversion layer 4. The storage region is provided in a portion of the detection circuit 12 inside the semiconductor substrate 1. The charges generated in the photoelectric conversion layer 4 are transported from the pixel electrode 3 to the storage region via the pixel via 13.

In the stacked imaging device 100, when a parasitic capacitance occurs between the pixel via 13 connected to a certain pixel electrode 3 and the pixel via 13 connected to the pixel electrode 3 adjacent to the pixel electrode 3 There is. This parasitic capacitance can cause crosstalk between pixels.

In order to suppress crosstalk due to parasitic capacitance, it is conceivable to connect vias to the shield electrode 61 and shield the pixel vias 13 with the vias. In this way, since the parasitic capacitance between the pixel vias 13 can be reduced, crosstalk due to the parasitic capacitance can be suppressed.

As described above, the imaging device 100 includes a plurality of wiring layers. The plurality of wiring layers are arranged between the shield electrode and the semiconductor substrate 1. The plurality of wiring layers are located at different positions in the direction perpendicular to the surface of the semiconductor substrate 1. The first wiring layer 14 is a layer closest to the pixel electrode 3 among the plurality of wiring layers. In a region located closer to the semiconductor substrate 1 than the first wiring layer 14 than in a region located closer to the pixel electrode 3 than the first wiring layer 14, wiring that can function as a shield for suppressing crosstalk is arranged. Often Therefore, the shield effect due to the vias connected to the shield electrode 61 is more likely to appear in the region closer to the pixel electrode 3 than the first wiring layer 14. Further, the shield effect due to the via connected to the shield electrode 61 is likely to appear when the distance between the pixel electrode 3 and the first wiring layer 14 is large.

In one example, the imaging device 100 is a color image sensor. In an example of a color image sensor, pixels corresponding to RGB are arranged adjacent to each other. That is, pixels corresponding to different colors are arranged adjacent to each other. Therefore, when crosstalk occurs between pixels, color mixing occurs. By applying the shield structure to the color image sensor, crosstalk is suppressed and deterioration of image quality due to color mixture is suppressed.

The following will describe the technique of using the via connected to the shield electrode 61. Hereinafter, the via extending from the shield electrode 61 may be referred to as a shield via.

In this embodiment, as understood from FIGS. 1 to 7, shield vias 63 and 63C are connected to the shield electrode 61. The shield vias 63 and 63C extend from the shield electrode 61 toward the semiconductor substrate 1. Specifically, the

shield vias

63 and 63C extend from the shield electrode 61 to the first wiring layer 14.

A via electrically connected to the shield electrode 61 may be provided closer to the semiconductor substrate 1 than the first wiring layer 14.

In the example of FIG. 3, each pixel electrode 3 is surrounded by the frame-shaped portion included in the shield electrode 61 in plan view. The shield vias 63C connected to the shield electrode 61 are arranged at the four corners of the frame-shaped portion. Further, the shield via 63 is also arranged between the four corners. In FIG. 3, the shield vias 63C located at the four corners of the frame-shaped portion surrounding the pixel electrode 3 at the center of the drawing are denoted by reference numeral 63C.

The number of

shield vias

63, 63C may be increased more than in the example of FIG. The greater the number of

shield vias

63, 63C surrounding one pixel electrode 3 in a plan view, the greater the effect of reducing crosstalk. A large number of

shield vias

63, 63C may be provided so that adjacent shield vias 63, 63C are in contact with each other. A set of the plurality of

shield vias

63, 63C provided in this way can be called a line via.

As described above, by connecting the

shield vias

63 and 63C to the shield electrode 61 and extending the

shield vias

63 and 63C toward the semiconductor substrate 1, crosstalk between the pixels 20 can be suppressed.

When the imaging device 100 is a color image sensor, color mixture can be suppressed by suppressing crosstalk as described above.

Examples of the material of the

shield vias

63, 63C include conductive materials such as copper (Cu), tungsten (W), and cobalt (Co).

The shield vias 63, 63C can be formed by embedding in the insulating layer 2.

A plurality of

shield vias

63, 63C may be formed in the same manufacturing process as the pixel via 13.

A shield structure with shield vias connected to the shield electrode 61 may be provided without providing the insulating portion 62 between the shield electrode 61 and the photoelectric conversion layer 4.

Below, referring to FIG. 8, the shield by the shield via will be further described.

In the following, we may explain the shield via with ordinal numbers. In FIG. 8, the position of the first shield via, which is the shield via 63, is represented by a point P1. The position of the second shield via that is the shield via 63 is represented by a point P2. The position of the third shield via, which is the shield via 63, is represented by a point P3. The position of the fourth shield via that is the shield via 63 is represented by a point P4. The position of the fifth shield via, which is the shield via 63C, is represented by a point P5. The position of the sixth shield via that is the shield via 63C is represented by a point P6. The position of the seventh shield via, which is the shield via 63C, is represented by a point P7. The position of the eighth shield via, which is the shield via 63C, is represented by a point P8. The position of the ninth shield via that is the shield via 63 is represented by a point P9. The position of the tenth shield via, which is the shield via 63, is represented by a point P10. The position of the eleventh shield via, which is the shield via 63, is represented by a point P11. The position of the 12th shield via, which is the shield via 63, is represented by a point P12. The position of the thirteenth shield via which is the shield via 63 is represented by a point P13. The position of the 14th shield via, which is the shield via 63, is represented by a point P14.

In the following, the terms first part X1, second part X2, third part X3, fourth part X4, fifth part X5, sixth part X6, seventh part X7 and eighth part X8 may be used. In FIG. 8, each of these portions is hatched. Note that the illustration of the insulating layer 2 is omitted in FIG.

Hereafter, the term planar view may be used. The plan view means, for example, observation in a direction perpendicular to the surface of the semiconductor substrate 1.

In the example of FIG. 8, the plurality of pixel electrodes 3 are the first pixel electrode 3A, the first adjacent pixel electrode 3B1, the second adjacent pixel electrode 3B2, the third adjacent pixel electrode 3B3, and the fourth adjacent pixel electrode 3B4. And, including. The first adjacent pixel electrode 3B1, the second adjacent pixel electrode 3B2, the third adjacent pixel electrode 3B3, and the fourth adjacent pixel electrode 3B4 are adjacent to the first pixel electrode 3A.

Further, in the example of FIG. 8, the plurality of pixel electrodes 3 include the first specific pixel electrode 3C1, the second specific pixel electrode 3C2, the third specific pixel electrode 3C3, and the fourth specific pixel electrode 3C4. The first specific pixel electrode 3C1 is adjacent to the first adjacent pixel electrode 3B1 and the second adjacent pixel electrode 3B2. The second specific pixel electrode 3C2 is adjacent to the second adjacent pixel electrode 3B2 and the third adjacent pixel electrode 3B3. The third specific pixel electrode 3C3 is adjacent to the third adjacent pixel electrode 3B3 and the fourth adjacent pixel electrode 3B4. The fourth specific pixel electrode 3C4 is adjacent to the fourth adjacent pixel electrode 3B4 and the first adjacent pixel electrode 3B1.

The shield electrode 61 includes a first portion X1, a second portion X2, a third portion X3, and a fourth portion X4. The at least one shield via includes a first shield via, a second shield via, a third shield via, and a fourth shield via. The first shield via extends from the first portion X1 toward the semiconductor substrate 1. The second shield via extends from the second portion X2 toward the semiconductor substrate 1. The third shield via extends from the third portion X3 toward the semiconductor substrate 1. The fourth shield via extends from the fourth portion X4 toward the semiconductor substrate 1.

In a plan view, the first pixel electrode 3A is a quadrangle Q in which a first side S1, a second side S2, a third side S3, and a fourth side S4 are connected in this order. In a plan view, the first portion X1 is located between the first side S1 and the first adjacent pixel electrode 3B1. In plan view, the second portion X2 is located between the second side S2 and the second adjacent pixel electrode 3B2. In plan view, the third portion X3 is located between the third side S3 and the third adjacent pixel electrode 3B3. In a plan view, the fourth portion X4 is located between the fourth side S4 and the fourth adjacent pixel electrode 3B4.

In the example of FIG. 8, specifically, in plan view, the first side S1 faces the first adjacent pixel electrode 3B1 with the first portion X1 interposed therebetween. In plan view, the second side S2 faces the second adjacent pixel electrode 3B2 with the second portion X2 interposed therebetween. In plan view, the third side S3 faces the third adjacent pixel electrode 3B3 with the third portion X3 interposed therebetween. In a plan view, the fourth side S4 faces the fourth adjacent pixel electrode 3B4 with the fourth portion X4 interposed therebetween.

In the example of FIG. 8, the shield electrode 61 includes a fifth portion X5, a sixth portion X6, a seventh portion X7, and an eighth portion X8. The at least one shield via includes a fifth shield via, a sixth shield via, a seventh shield via, and an eighth shield via. The fifth shield via extends from the fifth portion X5 toward the semiconductor substrate 1. The sixth shield via extends from the sixth portion X6 toward the semiconductor substrate 1. The seventh shield via extends from the seventh portion X7 toward the semiconductor substrate 1. The eighth shield via extends from the eighth portion X8 toward the semiconductor substrate 1.

In plan view, the plurality of pixel electrodes 3 are separated from each other via the grid-like region 60 including a plurality of intersecting portions. The shield electrode 61 is located in the grid-shaped region 60 in a plan view.

In plan view, the quadrangle Q includes a first vertex V1, a second vertex V2, a third vertex V3, and a fourth vertex V4. The first vertex V1 is a vertex where the first side S1 and the second side S2 are in contact with each other. The second vertex V2 is a vertex where the second side S2 and the third side S3 are in contact with each other. The third vertex V3 is a vertex where the third side S3 and the fourth side S4 are in contact with each other. The fourth vertex V4 is a vertex where the fourth side S4 and the first side S1 are in contact with each other.

In a plan view, the plurality of intersections include a first intersection Y1, a second intersection Y2, a third intersection Y3, and a fourth intersection Y4. In a plan view, the first intersection Y1 is closest to the first vertex V1 at the plurality of intersections. In plan view, the second intersection Y2 is closest to the second vertex V2 at the plurality of intersections. The third intersection Y3 is closest to the third vertex V3 at the plurality of intersections. The fourth intersection Y4 is closest to the fourth vertex V4 at the plurality of intersections.

The fifth portion X5 is located at the first intersection Y1 in a plan view. The sixth portion X6 is located at the second intersection Y2 in a plan view. The seventh portion X7 is located at the third intersection Y3 in a plan view. The eighth portion X8 is located at the fourth intersection Y4 in a plan view.

Further, in the example of FIG. 8, the at least one shield via is a ninth shield via, a tenth shield via, an eleventh shield via, a twelfth shield via, a thirteenth shield via, and a fourteenth shield via. And, including. The ninth shield via and the tenth shield via extend from the first portion X1 toward the semiconductor substrate 1. The eleventh shield via extends from the second portion X2 toward the semiconductor substrate 1. The twelfth shield via and the thirteenth shield via extend from the third portion X3 toward the semiconductor substrate 1. The fourteenth shield via extends from the fourth portion X4 toward the semiconductor substrate 1.

The vias connected to the shield electrode 61 contribute to obtaining an image with high resolution. Specifically, when the first to fourteenth shield vias are provided in this manner, the number of

shield vias

63 and 63C surrounding one pixel electrode 3 in plan view increases, and the effect of reducing crosstalk increases. .. Further, crosstalk between pixels arranged in an oblique direction can be reduced. Therefore, it is easy to obtain an image with higher resolution. The diagonal direction is the direction in which the diagonal line of the quadrangle Q extends in plan view in the example of FIG.

A part of the

shield vias

63 and 63C connected to the shield electrode 61 according to the above description may be omitted.

Shield vias

63 and 63C extending from the shield electrode 61 toward the semiconductor substrate 1 may be added.

In the example of FIG. 8, the imaging device 100 includes the pixel via 13. The pixel via 13 is connected to the first pixel electrode 3A. The pixel via 13 extends from the first pixel electrode 3A toward the semiconductor substrate 1. In FIG. 8, the position of the pixel via 13 is represented by a point PA. Although illustration is omitted, in the example of FIG. 8, the pixel via 13 is formed on the semiconductor substrate 1 not only from the pixel electrode 3A at the center of the drawing but also from the other eight pixel electrodes 3B1 to 3B4 and 3C1 to 3C4. Extending towards.

In such an imaging device 100, noise caused by parasitic capacitance between the pixel via 13 connected to the first pixel electrode 3A and the signal charge flowing in the pixel via 13 and the pixel via connected to the adjacent pixel electrode is generated. Can be suppressed by the

shield vias

63 and 63C connected to the shield electrode 61. Therefore, such an imaging device 100 is suitable for obtaining an image with high resolution.

In one specific example, in plan view, the pixel vias 13 connected to the first pixel electrodes 3A are the first shield vias, the second shield vias, the third shield vias, the fourth shield vias, and the fifth shields. Surrounded by vias and.

Specifically, in plan view, the pixel vias 13 connected to the first pixel electrode 3A include the first shield via, the second shield via, the third shield via, the fourth shield via, and the fifth shield. It is surrounded by a via, a sixth shield via, a seventh shield via, and an eighth shield via.

More specifically, in plan view, the pixel vias 13 connected to the first pixel electrode 3A are the first shield via, the second shield via, the third shield via, the fourth shield via, and the fifth shield via. Shield via, sixth shield via, seventh shield via, eighth shield via, ninth shield via, tenth shield via, eleventh shield via, twelfth shield via, and thirteenth shield via And the fourteenth shield via.

In the example of FIG. 8, the at least one shield via extends from the shield electrode 61 to the first wiring layer 14. This is suitable for obtaining a high-resolution image.

In the example of FIG. 8, the quadrangle Q is a rectangle. The quadrangle Q may be a square.

In the example of FIG. 8, the first adjacent pixel electrode 3B1, the second adjacent pixel electrode 3B2, the third adjacent pixel electrode 3B3, and the fourth adjacent pixel electrode 3B4 are quadrangular in a plan view. Typically, in plan view, the first adjacent pixel electrode 3B1, the second adjacent pixel electrode 3B2, the third adjacent pixel electrode 3B3, and the fourth adjacent pixel electrode 3B4 have the same shape and size as the quadrangle Q.

In the example of FIG. 8, in plan view, the first adjacent pixel electrode 3B1 and the third adjacent pixel electrode 3B3 are adjacent to the first pixel electrode 3A in the direction in which the second side S2 and the fourth side S4 extend. The second adjacent pixel electrode 3B2 and the fourth adjacent pixel electrode 3B4 are adjacent to the first pixel electrode 3A in the direction in which the first side S1 and the third side S3 extend.

In the example of FIG. 8, the shield electrode 61, which is a single conductor, shields the plurality of pixel electrodes 3. Specifically, the single conductor has a lattice shape in a plan view. However, another form can also be adopted. For example, the shield electrode 61 may be electrically separated into a plurality of portions, and each of the plurality of portions may individually shield the corresponding pixel electrode 3.

The features of the imaging device will be described below with reference to FIGS. 9A to 9E. The following description may overlap with the above description. The following description may be combined with the above description. The terms used in the following description and the terms used in the above description can be interchanged. The insulating layer 2 is not shown in FIGS. 9A to 9E.

The first shield via SV1 in FIG. 9A corresponds to the first shield via at point P1 in FIG. The second shield via SV2 in FIG. 9A corresponds to the second shield via at the point P2 in FIG. The third shield via SV3 in FIG. 9A corresponds to the fifth shield via at point P5 in FIG. The fourth shield via SV4 in FIG. 9A corresponds to the third shield via at point P3 in FIG. The fifth shield via SV5 in FIG. 9A corresponds to the sixth shield via at point P6 in FIG. The sixth shield via SV6 in FIG. 9A corresponds to the fourth shield via at point P4 in FIG. The seventh shield via SV7 in FIG. 9A corresponds to the seventh shield via at point P7 in FIG. The eighth shield via SV8 in FIG. 9A corresponds to the eighth shield via at point P8 in FIG. The ninth shield via SV9 in FIG. 9A corresponds to the ninth shield via at point P9 in FIG. The tenth shield via SV10 in FIG. 9A corresponds to the tenth shield via at point P10 in FIG. The eleventh shield via SV11 in FIG. 9A corresponds to the eleventh shield via at point P11 in FIG. The twelfth shield via SV12 in FIG. 9A corresponds to the twelfth shield via at point P12 in FIG. The thirteenth shield via SV13 in FIG. 9A corresponds to the thirteenth shield via at point P13 in FIG. The fourteenth shield via SV14 in FIG. 9A corresponds to the fourteenth shield via at point P14 in FIG.

The shield vias SV1 to SV14 extend from the shield electrode 61. Specifically, the shield vias SV1 to SV14 extend from the shield electrode 61 in a direction away from the light incident surface. It can be said that the shield vias SV1 to SV14 extend downward from the shield electrode 61. In this example, the shield vias SV1 to SV14 extend to the first wiring layer 14.

The first pixel electrode PE1 in FIG. 9A corresponds to the first pixel electrode 3A in FIG. The second pixel electrode PE2 of FIG. 9A corresponds to the first adjacent pixel electrode 3B1 of FIG. The third pixel electrode PE3 of FIG. 9A corresponds to the second adjacent pixel electrode 3B2 of FIG. The fourth pixel electrode PE4 of FIG. 9A corresponds to the first specific pixel electrode 3C1 of FIG. The fifth pixel electrode PE5 of FIG. 9A corresponds to the third adjacent pixel electrode 3B3 of FIG. The sixth pixel electrode PE6 of FIG. 9A corresponds to the second specific pixel electrode 3C2 of FIG. The seventh pixel electrode PE7 of FIG. 9A corresponds to the fourth adjacent pixel electrode 3B4 of FIG. The eighth pixel electrode PE8 of FIG. 9A corresponds to the third specific pixel electrode 3C3 of FIG. The ninth pixel electrode PE9 of FIG. 9A corresponds to the fourth specific pixel electrode 3C4 of FIG. The first pixel electrode PE1 to the ninth pixel electrode PE9 collect charges. The first pixel electrode PE1 to the ninth pixel electrode PE9 are electrically separated from the shield electrode 61.

The first pixel electrode PE1 is adjacent to the second pixel electrode PE2, the third pixel electrode PE3, the fifth pixel electrode PE5, and the seventh pixel electrode PE7. The fourth pixel electrode PE4 is adjacent to the second pixel electrode PE2 and the third pixel electrode PE3. The sixth pixel electrode PE6 is adjacent to the third pixel electrode PE3 and the fifth pixel electrode PE5. The eighth pixel electrode PE8 is adjacent to the fifth pixel electrode PE5 and the seventh pixel electrode PE7. The ninth pixel electrode PE9 is adjacent to the seventh pixel electrode PE7 and the second pixel electrode PE2.

Specifically, the first pixel electrode PE1 and the second pixel electrode PE2 are adjacent to each other in the first direction. The first pixel electrode PE1 and the third pixel electrode PE3 are adjacent to each other in the second direction. The first pixel electrode PE1 and the fifth pixel electrode PE5 are adjacent to each other in the first direction. The first pixel electrode PE1 and the seventh pixel electrode PE7 are adjacent to each other in the second direction. The fourth pixel electrode PE4 and the second pixel electrode PE2 are adjacent to each other in the second direction. The fourth pixel electrode PE4 and the third pixel electrode PE3 are adjacent to each other in the first direction. The sixth pixel electrode PE6 and the third pixel electrode PE3 are adjacent to each other in the first direction. The sixth pixel electrode PE6 and the fifth pixel electrode PE5 are adjacent to each other in the second direction. The eighth pixel electrode PE8 and the fifth pixel electrode PE5 are adjacent to each other in the second direction. The eighth pixel electrode PE8 and the seventh pixel electrode PE7 are adjacent to each other in the first direction. The ninth pixel electrode PE9 and the seventh pixel electrode PE7 are adjacent to each other in the first direction. The ninth pixel electrode PE9 and the second pixel electrode PE2 are adjacent to each other in the second direction.

Here, the first direction and the second direction are directions different from each other. In the illustrated example, the first direction and the second direction are directions orthogonal to each other. In the illustrated example, the first direction is the row direction. The second direction is the column direction. Further, in the illustrated example, the first direction corresponds to the X-axis direction. The second direction corresponds to the Y-axis direction.

The expression that the first pixel electrode PE1 and the second pixel electrode PE2 are adjacent to each other will be described with reference to FIGS. 9B and 9C. This expression means that, in a plan view, the side Sj of the smallest rectangle RT1 containing the first pixel electrode PE1 and the side Sk of the smallest rectangle RT2 containing the second pixel electrode PE2 face each other. means. A rectangle is a concept that includes a square. Specifically, that the first pixel electrode PE1 and the second pixel electrode PE2 are adjacent to each other means that the normal line of the side Sj passes through the side Sk and the normal line of the side Sk is the side Sj in a plan view. Means to pass through. The normal to the side Sj may be a line that passes through any point on the side Sj. The normal line of the side Sk may be a line passing through any point on the side Sk. In one specific example, the vertical bisector of the side Sj passes through the midpoint of the side Sk and the vertical bisector of the side Sk passes through the midpoint of the side Sj in a plan view. The same applies to expressions relating to adjacency between other pixel electrodes, such as the adjoining of the first pixel electrode PE1 and the third pixel electrode PE3, and specific examples thereof.

In the examples shown in FIGS. 3, 8, 9A, and 9B, the smallest rectangle RT1 that accommodates the first pixel electrode PE1 is the same as the contour of the first pixel electrode PE1 in plan view. The same applies to other pixel electrodes such as the second pixel electrode PE2.

However, as shown in FIG. 9C, the contour of the first pixel electrode PE1 may be rounded in a plan view. In the example of FIG. 9C, the smallest rectangle RT1 that houses the first pixel electrode PE1 is different from the contour of the first pixel electrode PE1. Other pixel electrodes such as the second pixel electrode PE2 may also have the shape shown in FIG. 9C. In reality, when the size of the pixel electrode is small, the pixel electrode tends to be rounded in plan view.

In the examples shown in FIGS. 3, 8 and 9A, a plurality of pixels are arranged in a matrix to form a pixel array. In the case where the pixel array is configured as described above, that a certain pixel electrode and another pixel electrode are adjacent to each other means that these pixel electrodes are adjacent to each other in the row direction or the column direction. Does not mean that the pixels are arranged in an oblique direction that is inclined with respect to the row direction and the column direction. In the examples shown in FIGS. 3, 8 and 9A, the row direction corresponds to the left-right direction and the column direction corresponds to the up-down direction.

Returning to FIG. 9A, the first pixel via PV1 extends from the first pixel electrode PE1. The first pixel via PV1 in FIG. 9A corresponds to the pixel via 13 at the point PA in FIG. The second pixel via PV2 extends from the second pixel electrode PE2. The third pixel via PV3 extends from the third pixel electrode PE3. The fourth pixel via PV4 extends from the fourth pixel electrode PE4. The fifth pixel via PV5 extends from the fifth pixel electrode PE5. The sixth pixel via PV6 extends from the sixth pixel electrode PE6. The seventh pixel via PV7 extends from the seventh pixel electrode PE7. An eighth pixel via PV8 extends from the eighth pixel electrode PE8. The ninth pixel via PV9 extends from the ninth pixel electrode PE9. The first pixel via PV1 to the ninth pixel via PV9 can electrically connect the first pixel electrode PE1 to the ninth pixel electrode PE9 to other elements. Specific examples of other elements are a wiring layer, the detection circuit 12, and the like.

The first shield via SV1 is located between the first pixel electrode PE1 and the second pixel electrode PE2 in a plan view. In plan view, the second shield via SV2 is located between the first pixel electrode PE1 and the third pixel electrode PE3. In a plan view, the fourth shield via SV4 is located between the first pixel electrode PE1 and the fifth pixel electrode PE5. In plan view, the sixth shield via SV6 is located between the first pixel electrode PE1 and the seventh pixel electrode PE7. In plan view, the ninth shield via SV9 is located between the first pixel electrode PE1 and the second pixel electrode PE2. The tenth shield via SV10 is located between the first pixel electrode PE1 and the second pixel electrode PE2 in a plan view. In plan view, the eleventh shield via SV11 is located between the first pixel electrode PE1 and the third pixel electrode PE3. In plan view, the twelfth shield via SV12 is located between the first pixel electrode PE1 and the fifth pixel electrode PE5. In plan view, the thirteenth shield via SV13 is located between the first pixel electrode PE1 and the fifth pixel electrode PE5. In plan view, the fourteenth shield via SV14 is located between the first pixel electrode PE1 and the seventh pixel electrode PE7. The presence of the shield via between the two pixel electrodes in a plan view is suitable for obtaining an image with high resolution.

The fact that the first shield via SV1 is located between the first pixel electrode PE1 and the second pixel electrode PE2 in plan view means that, in plan view, one of the points on the side Sj is one end and one of the sides Sk is one of the ends. This means that the first shield via SV1 is present on the line segment having the point at the other end. In one specific example, the connection portion between the shield electrode 61 and the first shield via SV1 is present on the line segment in plan view. Regarding expressions and specific examples regarding the arrangement of shield vias between other two adjacent pixel electrodes such that the second shield via SV2 is located between the first pixel electrode PE1 and the third pixel electrode PE3 in a plan view Is also the same. When the shield via is located between two adjacent pixel electrodes in a plan view, the shield via can shield at least a part of the lines of electric force between the pixel electrodes.

In the illustrated example, the number of shield vias located between the first pixel electrode PE1 and the second pixel electrode PE2 in a plan view and the position between the first pixel electrode PE1 and the third pixel electrode PE3 in a plan view The number is different from the number of shield vias. The number of shield vias located between the first pixel electrode PE1 and the third pixel electrode PE3 in a plan view, and the number of shield vias located between the first pixel electrode PE1 and the fifth pixel electrode PE5 in a plan view Is different from. The number of shield vias located between the first pixel electrode PE1 and the fifth pixel electrode PE5 in a plan view, and the number of shield vias located between the first pixel electrode PE1 and the seventh pixel electrode PE7 in a plan view Is different from. The number of shield vias located between the first pixel electrode PE1 and the seventh pixel electrode PE7 in a plan view, and the number of shield vias located between the first pixel electrode PE1 and the second pixel electrode PE2 in a plan view Is different from.

In the illustrated example, the number of shield vias located between the first pixel electrode PE1 and the second pixel electrode PE2 in a plan view and the position between the first pixel electrode PE1 and the fifth pixel electrode PE5 in a plan view The number of shield vias is the same. The number of shield vias located between the first pixel electrode PE1 and the third pixel electrode PE3 in a plan view, and the number of shield vias located between the first pixel electrode PE1 and the seventh pixel electrode PE7 in a plan view And are the same.

Specifically, the three shield vias located between the first pixel electrode PE1 and the second pixel electrode PE2 in plan view are the first shield via SV1, the ninth shield via SV9, and the tenth shield via SV10. is there. The two shield vias, the second shield via SV2 and the eleventh shield via SV11, are located between the first pixel electrode PE1 and the third pixel electrode PE3 in a plan view. The three shield vias located between the first pixel electrode PE1 and the fifth pixel electrode PE5 in a plan view are the fourth shield via SV4, the twelfth shield via SV12, and the thirteenth shield via SV13. The two shield vias that are located between the first pixel electrode PE1 and the seventh pixel electrode PE7 in plan view are the sixth shield via SV6 and the fourteenth shield via SV14.

In the illustrated example, the third shield via SV3 is located between the first pixel electrode PE1 and the fourth pixel electrode PE4 in a plan view. In plan view, the fifth shield via SV5 is located between the first pixel electrode PE1 and the sixth pixel electrode PE6. In plan view, the seventh shield via SV7 is located between the first pixel electrode PE1 and the eighth pixel electrode PE8. In a plan view, the eighth shield via SV8 is located between the first pixel electrode PE1 and the ninth pixel electrode PE9. By doing so, crosstalk between pixels arranged in an oblique direction can be reduced. Therefore, it is easy to obtain an image with higher resolution. In the example of FIG. 9A, the outline of the first pixel electrode PE1 is a quadrangle in plan view, and the diagonal direction is the direction in which the diagonal line of the quadrangle extends.

The expression that the third shield via SV3 is located between the first pixel electrode PE1 and the fourth pixel electrode PE4 in plan view will be described with reference to FIG. 9D. This expression is a line segment that connects two opposite apexes of the smallest rectangle RT1 containing the first pixel electrode PE1 and the smallest rectangle RT4 containing the fourth pixel electrode PE4 in plan view. It means that the third shield via SV3 is located in a square Sx2 having a diagonal line of. The two opposite vertices are chosen such that the square Sx2 is the smallest. In one specific example, the connection portion between the shield electrode 61 and the third shield via SV3 exists in the square Sx2 in a plan view. The same applies to expressions and specific examples regarding the arrangement of shield vias between two other pixel electrodes such that the fifth shield via SV5 is located between the first pixel electrode PE1 and the sixth pixel electrode PE6 in a plan view. is there. Since the shield via is located between the two pixel electrodes in plan view, the shield via can shield at least a part of the lines of electric force between the two pixel electrodes.

In the illustrated example, the third shield via SV3 is located between the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, and the fourth pixel electrode PE4 in a plan view. In plan view, the fifth shield via SV5 is located between the first pixel electrode PE1, the third pixel electrode PE3, the fifth pixel electrode PE5, and the sixth pixel electrode PE6. In plan view, the seventh shield via SV7 is located between the first pixel electrode PE1, the fifth pixel electrode PE5, the seventh pixel electrode PE7, and the eighth pixel electrode PE8. In plan view, the eighth shield via SV8 is located between the first pixel electrode PE1, the seventh pixel electrode PE7, the second pixel electrode PE2, and the ninth pixel electrode PE9. The presence of the vias between the four pixel electrodes in a plan view is suitable for obtaining an image with high resolution.

The expression that the third shield via SV3 is located between the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, and the fourth pixel electrode PE4 in a plan view will be described with reference to FIG. 9E. This expression means, in plan view, the minimum rectangle RT1 that accommodates the first pixel electrode PE1, the minimum rectangle RT2 that accommodates the second pixel electrode PE2, and the minimum rectangle that accommodates the third pixel electrode PE3. This means that the third shield via SV3 is located within a quadrangle Sx4 defined by four opposite vertices of the vertex of RT3 and the smallest rectangle RT4 containing the fourth pixel electrode PE4. The four opposing vertices are chosen so that the quadrangle Sx4 is the smallest. In one specific example, the connection portion between the shield electrode 61 and the third shield via SV3 is present inside the quadrangle Sx4 in a plan view. The shield via between the other four pixel electrodes such that the fifth shield via SV5 is located between the first pixel electrode PE1, the third pixel electrode PE3, the fourth pixel electrode PE5 and the sixth pixel electrode PE6 in a plan view. The same applies to the expressions relating to the arrangement and specific examples thereof. When the shield via is located between the four pixel electrodes in a plan view, the shield via can shield at least a part of the lines of electric force between the four pixel electrodes.

The square Sx4 in FIG. 9E may correspond to the square Sx2 in FIG. 9D. The square Sx2 of FIG. 9D and the quadrangle Sx4 of FIG. 9E may correspond to the first intersection Y1 of FIG. The above description using FIG. 9D and the above description using FIG. 9E can be established even when the pixel electrode is rounded in plan view as in FIG. 9C.

Returning to FIG. 9A, the first shield via SV1 is located between the first pixel via PV1 and the second pixel via PV2 in a plan view. In plan view, the third shield via SV3 is located between the first pixel via PV1 and the fourth pixel via PV4. In a plan view, the fourth shield via SV4 is located between the first pixel via PV1 and the fifth pixel via PV5. In plan view, the fifth shield via SV5 is located between the first pixel via PV1 and the sixth pixel via PV6. In plan view, the seventh shield via SV7 is located between the first pixel via PV1 and the eighth pixel via PV8. In a plan view, the eighth shield via SV8 is located between the first pixel via PV1 and the ninth pixel via PV9.

That the first shield via SV1 is located between the first pixel via PV1 and the second pixel via PV2 in plan view means that the first pixel via PV1 is one end and the second pixel via PV2 is the other end in plan view. This means that the first shield via SV1 exists on the line segment. In a specific example, in a plan view, on a line segment having the connection portion of the first pixel electrode PE1 and the first pixel via PV1 as one end and the connection portion of the second pixel electrode PE2 and the second pixel via PV2 as the other end, There is a connection between the shield electrode 61 and the first shield via SV1. The same applies to expressions and specific examples regarding the arrangement of vias between other pixel vias such that the third shield via SV3 is located between the first pixel via PV1 and the fourth pixel via PV4 in a plan view. By disposing the shield vias between the pixel vias in a plan view, the shield vias can shield at least a part of lines of electric force between the pixel vias.

Although not shown in FIG. 9A, the insulating portion 62 includes the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, the fourth pixel electrode PE4, and the fifth pixel electrode PE5 in plan view. It is separated from the sixth pixel electrode PE6, the seventh pixel electrode PE7, the eighth pixel electrode PE8, and the ninth pixel electrode PE9.

In a plan view, the shield electrode 61 extends between the first pixel electrode PE1 and the second pixel electrode PE2. In plan view, the shield electrode 61 extends between the first pixel electrode PE1 and the third pixel electrode PE3. In plan view, the shield electrode 61 extends between the first pixel electrode PE1 and the fifth pixel electrode PE5. In plan view, the shield electrode 61 extends between the first pixel electrode PE1 and the seventh pixel electrode PE7. In plan view, the shield electrode 61 extends between the fourth pixel electrode PE4 and the second pixel electrode PE2. In plan view, the shield electrode 61 extends between the fourth pixel electrode PE4 and the third pixel electrode PE3. In plan view, the shield electrode 61 extends between the sixth pixel electrode PE6 and the third pixel electrode PE3. In plan view, the shield electrode 61 extends between the sixth pixel electrode PE6 and the fifth pixel electrode PE5. In plan view, the shield electrode 61 extends between the eighth pixel electrode PE8 and the fifth pixel electrode PE5. In plan view, the shield electrode 61 extends between the eighth pixel electrode PE8 and the seventh pixel electrode PE7. In plan view, the shield electrode 61 extends between the ninth pixel electrode PE9 and the seventh pixel electrode PE7. In plan view, the shield electrode 61 extends between the ninth pixel electrode PE9 and the second pixel electrode PE2.

(Camera system)
Hereinafter, a camera system to which the above-described image pickup apparatus 100 is applied will be described with reference to FIG.

In the example of FIG. 10, the camera system 604 includes the imaging device 100, an optical system 601, a camera signal processing unit 602, and a system controller 603.

The optical system 601 collects light. The optical system 601 includes, for example, a lens.

The camera signal processing unit 602 performs signal processing on the data captured by the imaging device 100 and outputs it as an image or data.

The system controller 603 controls the imaging device 100 and the camera signal processing unit 602.

The imaging device according to the present disclosure can be used for various camera systems and sensor systems such as digital still cameras, medical cameras, surveillance cameras, vehicle-mounted cameras, digital single-lens reflex cameras, and digital mirrorless single-lens cameras. ..

Although the imaging device of the present disclosure has been described above based on the embodiment, the imaging device and the manufacturing method thereof according to the present disclosure are not limited to the above embodiments. Another embodiment realized by combining arbitrary constituent elements in the above-described embodiment, a modified example obtained by applying various modifications to those skilled in the art to the above-described embodiment without departing from the gist of the present disclosure, and the present embodiment. Various devices incorporating the disclosed solid-state imaging device are also included in the present disclosure.

1 Semiconductor Substrate 2 Insulating Layers 2a, 2b, 2c, 2d, 2e Constituent Layers 3, 3A, 3B1, 3B2, 3B3, 3B4, 3C1, 3C2, 3C3, 3C4, PE1, PE2, PE3, PE4, PE5, PE6, PE7 , PE8, PE9, 69 Pixel electrode 4 Photoelectric conversion layer 4p Protruding part 5 Counter electrode 6 Buffer layer 7 Sealing layer 8 Color filter 9 Flattening layer 10 Microlens 11 Photoelectric conversion part 12 Detection circuit 13, PV1, PV2, PV3 PV4, PV5, PV6, PV7, PV8, PV9 Pixel vias 63, 63C, SV1, SV2, SV3, SV4, SV5, SV6, SV7, SV8, SV9, SV10, SV11, SV12, SV13, SV14 Shield via 14 First wiring Layer 20 Pixel 30 Pixel portion 60 Region 61 Shield electrode 62 Insulating portion 62a Upper surface 62b Lower surface 62 Side surface 62d Corner 62x Layer 65 Signal charge 67 Insulator 68 Via 71 Separation width 81 Mask 100 Imaging device 601 Optical system 602 Camera signal processing unit 603 System controller 604 Camera system S1, S2, S3, S4 Side P1, P2, P3, P4 , P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, PA point Q, Sx4 quadrangle Sx2 square RT1, RT2, RT3, RT4 rectangle Sk, Sj side V1, V2, V3, V4 vertex X1 , X2, X3, X4, X5, X6, X7, X8 Part Y1, Y2, Y3, Y4 Intersection

Claims

A photoelectric conversion layer for converting incident light into an electric charge,
A first pixel electrode for collecting charges generated in the photoelectric conversion layer;
A second pixel electrode adjacent to the first pixel electrode in the first direction, collecting the charges generated in the photoelectric conversion layer;
A shield electrode electrically separated from the first pixel electrode and the second pixel electrode;
A first shield via extending from the shield electrode and located between the first pixel electrode and the second pixel electrode in plan view;
With
Imaging device.
A third pixel electrode adjacent to the first pixel electrode in a second direction different from the first direction, the charge being generated in the photoelectric conversion layer;
A second shield via extending from the shield electrode and located between the first pixel electrode and the third pixel electrode in the plan view;
Further comprising,
The image pickup apparatus according to claim 1.
A third pixel electrode adjacent to the first pixel electrode in a second direction different from the first direction, the charge being generated in the photoelectric conversion layer;
A fourth pixel electrode that collects charges generated in the photoelectric conversion layer, is adjacent to the second pixel electrode in the second direction, and is adjacent to the third pixel electrode in the first direction;
A third shield via extending from the shield electrode and located between the first pixel electrode and the fourth pixel electrode in the plan view;
Further comprising,
The image pickup apparatus according to claim 1.
A fourth pixel electrode that collects charges generated in the photoelectric conversion layer, is adjacent to the second pixel electrode in the second direction, and is adjacent to the third pixel electrode in the first direction;
A third shield via extending from the shield electrode and located between the first pixel electrode and the fourth pixel electrode in the plan view;
Further comprising,
The image pickup apparatus according to claim 2.
A first pixel via extending from the first pixel electrode;
A second pixel via extending from the second pixel electrode;
Further comprising,
The image pickup apparatus according to claim 1.
In the plan view, the first shield via is located between the first pixel via and the second pixel via.
The image pickup apparatus according to claim 5.
Further comprising a first wiring layer,
The first shield via extends from the shield electrode to the first wiring layer,
The image pickup apparatus according to claim 1.
Further comprising an insulating portion located between the shield electrode and the photoelectric conversion layer,
The image pickup apparatus according to claim 1.
In the plan view, the insulating portion includes a portion that does not overlap with the shield electrode,
The imaging device according to claim 8.
In the plan view, the insulating portion is separated from the first pixel electrode,
The image pickup apparatus according to claim 9.
The insulating portion has a film shape,
The thickness of the film shape is 10 nm or more,
The imaging device according to claim 8.
A photoelectric conversion layer for converting incident light into an electric charge,
A first pixel electrode for collecting charges generated in the photoelectric conversion layer;
A shield electrode electrically separated from the first pixel electrode,
An insulating portion located between the shield electrode and the photoelectric conversion layer,
Equipped with
In a plan view, the insulating portion includes a portion that does not overlap with the shield electrode,
Imaging device.
In the plan view, the insulating portion is separated from the first pixel electrode,
The image pickup apparatus according to claim 12.
The insulating portion has a film shape,
The thickness of the film shape is 10 nm or more,
The image pickup apparatus according to claim 12.
A surface of the first pixel electrode and a surface of the shield electrode are on the same plane.
The image pickup apparatus according to claim 1.
The image pickup device is a color image sensor,
The image pickup apparatus according to claim 1.