WO2020070233A1

WO2020070233A1 - Semiconductor powerdevice

Info

Publication number: WO2020070233A1
Application number: PCT/EP2019/076787
Authority: WO
Inventors: Matt ELWIN; Petar Igic; Faramehr SOROUSH
Original assignee: Swansea University
Priority date: 2018-10-02
Filing date: 2019-10-02
Publication date: 2020-04-09

Abstract

The present invention provided a vertical GaN power FET having a source terminal in contact with the gate-side n+GaN region and the pGaN region. The present invention also provides a method of manufacture of such a device.

Description

SEMICONDUCTOR POWERDEVICE

The present invention is concerned with a GaN (gallium nitride) power device. More specifically, the present invention is concerned with a vertical GaN MOSFET for power electronics applications.

Silicon has been the backbone of semiconductor industry since the 1970s and has served the power electronics industry well for over four decades. Silicon MOSFETs have steadily improved over that time, but the limitations of silicon as a semiconductor material have slowed progress. For example, modern silicon MOSFETs have a resistivity which is near the theoretical limit for a silicon device.

To support the rising diversity of industrial and domestic applications and their power requirements, solutions beyond silicon are required. The need to drive circuits at higher powers and higher temperatures stimulate the need for wide bandgap materials.

Gallium nitride (GaN) high electron mobility transistor (FIEMT) devices appeared in the mid-2000s. These early devices were lateral and took advantage of the high electron mobility afforded by a two- dimensional electron "gas" ("2DEG") which existed at the heterojunction between aluminium gallium nitride (AIGaN) and GaN.

An example of a lateral FIEMT is shown in Figure 1. The AIGaN / GaN high electron mobility transistor (FIEMT) 10 is a lateral device consisting of an AIGaN epitaxial layer 12 grown on GaN bulk layer 14 to take an advantage of 2DEG formed at the interface of AIGaN / GaN. The source S, gate G and drain D are fabricated on the same plane. The electrons in-channel are modulated via the gate G. The distance between the gate and drain DGD sustains the voltage at OFF states. Field plates 16, 18 are added over the passivation layer to provide a uniform electric field at the drain side of the gate and to improve the blocking capabilities.

Kmown GaN lateral power devices are provided on silicon, silicon carbide and sapphire substrates where devices need to withstand the high electric fields along the surface. The breakdown voltage increases with increase with gate to drain distance DGD. Power lateral devices are therefore relatively large making silicon the most feasible substrate among the three, since silicon substrates are cheap and available up to 30cm.

The breakdown voltage is determined by the resistivity and the thickness of epitaxial layers. The resistivity of the epitaxial layers depends on the intentional doping, impurity residuals, native defects and threading dislocations. The reduction in threading dislocation density with increasing current blocking layer thickness contributes to the enhancement of breakdown voltage. At higher power levels, exceeding 0.6 to 1.2kV, and 3kW, lateral devices reach a practical limit due to the sizes required. It is therefore desirable to break the link between the breakdown voltage and surface area exhibited by lateral GaN power devices.

Vertical GaN (VeGaN) devices start to become an attractive alternative at this point. The contacts of vertical devices are placed at two different planes. The source and gate are in one plane and drain is in another. The current is controlled via gate and flows through the bulk into the drain.

In vertical devices, the electric field is held in the thick bulk layer rather than the device surface making operation possible at high electric fields while chip area can be reduced compared to the lateral power devices. High breakdown voltages can be achieved by vertical GaN devices on native (nitrides) or foreign substrates (for instance silicon).

A known VeGaN device is shown in Figure 2. The device of Figure 2 is very similar to the well-known vertical silicon trench power MOSFET. The p-body (pGaN region in Fig. 2) region has not been short- circuited to device's source region S, it is left floating.

In prior art n-type VeGaN devices, an electron channel is formed at the pGaN region surface adjacent the gate the dielectric layer. When a bias is applied between source and drain the electrons will flow between these terminals, i.e. the device is "on". During certain device operating conditions, charge can be injected into the p-body region, thus changing its potential. As a result, the device's operation can become unstable because the device's current cannot be controlled by terminal voltages (voltages on gate source and drain). Figure 3 shows the differenced in the device's output characteristic under the same bias condition caused by injection of negative or positive charge into the floating p-body region.

The paper "High-Performance GaN Vertical Fin Power Transistors on Bulk GaN Substrates" published in IEEE Electron Device Letters, Vol. 38, No. 4, April 2017 proposes a VeGaN power field effect transistor structure with submicron fin-shaped channels on bulk GaN substrates. The device requires only n-doped GaN layers. A problem with this type of device is that device is normally "on" (gate bias is needed to switch device off) and potentially high leakage current (high off state losses).

Gallium (III) oxide (Ga C> ) is also seen as a desirable material from which to construct power devices. It has a lower cost and wider band gap than gallium nitride.

It is an aim of the present invention to provide an improved GaN power device.

For the avoidance of doubt, in the following description and claims the term "over" and in e.g. "deposited over" refers to the situation where the elements are not necessarily in direct contact (there may be an intervening element). Where the term "on", "adjacent to" or "in contact with" is used, there is direct physical contact / integration.

According to a first aspect of the invention there is provided a vertical GaN power FET comprising: an n doped drift region; a drain terminal over a first side of the n doped drift region; a p doped region on a second side of the n doped drift region; at least one n+ doped region on the opposite side of the p doped region to the n doped drift region; a gate dielectric layer extending from the n+ doped region, through the p doped region to the n doped drift region; a gate terminal in contact with the gate dielectric layer; at least one source terminal in contact with the n+ doped region, wherein the source terminal is also in contact with the p doped region.

For the avoidance of doubt, the FET of the present invention is constructed with the drift region, p doped region, n+ doped region constructed from GaN.

Advantageously, by forming a contact between the source electrode and the p doped layer, the p doped layer becomes "pinned".

It should be noted that in order to form junctions between conductive terminals and p-doped bodies in silicon, a small p+ doped region is provided to avoid the creation of a Shottky contact. It is not possible to create a p+ doped region in GaN (p+ GaN), and as such this type of contact has been avoided in the prior art.

The inventors have realised that although a Schottky contact is formed between the source contact and the p-doped region, this is not as problematic as might be expected. The application of a voltage to the drain the Schottky barrier is reduced, and as such the creation of the barrier is actually less of a problem for high voltage applications. The Schottky barrier becomes thinner as potential across the device increases.

Preferably the source terminal is in contact with the n+ doped region and the gate dielectric layer.

Preferably the vertical GaN power FET is a layered device, in which each region is provided as a distinct layer. The layer thicknesses are determined by the designed breakdown voltage, channel length and threshold voltage. Preferably these have thicknesses in the following ranges:

• N doped region - preferably between 2 and 20 pm;

• P doped layer - preferably between 0.3pm and 0.1pm;

· n+ doped layer - preferably between 0.1pm and 0.5pm;

• Gate dielectric layer - preferably between 20nm and 200nm.

Preferably the gate dielectric layer is formed in a recess or well.

Preferably the FET is a trench device.

Preferable features are provided in the dependent claims. According to a second aspect of the invention there is provided a method of manufacturing a vertical GaN field effect transistor comprising the steps of: providing a substrate; growing a drain-side n+ doped layer over the substrate growing a n doped layer on the n+ doped layer; growing a p doped layer on the n doped layer; growing a gate-side n+ doped layer on the p doped layer; forming a gate well through the gate-side n+ doped layer, p doped layer to the n doped layer; depositing a gate dielectric onto the surface of the gate well, the gate dielectric contacting the gate-side n+ doped , p doped layer and the n doped layer; depositing a conductive gate terminal into the gate well; depositing a conductive source terminal in contact with the gate dielectric, the gate-side n+ doped layer and the p doped layer; etching the substrate to expose the drain-side n+ doped layer; and, depositing a conductive drain terminal in contact with the drain-side n+ doped layer. Preferable features are provided in the dependent claims. In an alternative version of the invention, the FET of the present invention may be constructed with the drift region, p doped region, n+ doped region constructed from Ga C (instead of GaN). The following embodiments all refer to GaN, but it will be understood that Ga C could be used instead.

An example power device in accordance with the present invention will now be described with reference to the following figures in which:

FIGURE 1 is a schematic view of a known lateral GaN FIEMT device;

FIGURE 2 is a schematic view of a known VeGaN device;

FIGURE 3 is a simulated output characteristic of the known VeGaN device of Figure 2;

FIGURE 4 is a schematic view of a VeGaN in accordance with the present invention;

FIGURE 5 is a detail view of region V of Figure 4;

FIGURE 6 is a flow diagram of the process of manufacture of the VeGaN device of Figure 4;

FIGURES 7a to 7h are diagrams of the stages of the manufacturing method of the VeGaN device of Figure 4; and,

FIGURES 8a and 8b are performance graphs for a simulated device according to the invention. Structure

Referring to Figure 1, a VeGaN power device 100 comprises (from the bottom of Figure 2 up):

• A drain contact D;

• A first, drain-side heavily doped n+ GaN layer 102;

• A doped nGaN layer 104;

• A doped pGaN layer 106;

• A second, gate-side heavily doped n+ GaN layer 108;

• A gate dielectric layer 110;

• A gate electrode G; and,

• Source electrodes Sa, Sb(molybdenum in this embodiment).

In this embodiment, the nGaN layer is doped less than 10¹⁷ cm ³, and preferably between 10¹⁴ to 10¹⁷ cm ³, and the n+GaN layer is doped between 10¹⁸ to 10²⁰ cm ³. The pGaN layer is doped less than 10¹⁷ cm ³, and preferably between 10¹⁴ to 10¹⁷ cm ³.

The drain contact D is deposited on a first (under) side of the heavily doped n+ GaN layer 102. On the opposite side of the heavily doped n+ GaN layer 102 there is provided the epitaxially grown doped nGaN layer 104. On the opposite side of the doped nGaN layer 104 there is provided the doped pGaN layer 106. On the opposite side of the doped pGaN layer 106 there is provided the heavily doped n+ GaN layer 108.

The gate dielectric layer 110 coats part of the heavily doped n+ GaN layer 108. The dielectric layer 110 extends into a gate well 116. The dielectric layer 110 may be constructed from an oxide (e.g. AI2O3) and / or a nitride. The gate well (and hence the dielectric layer 110) extends through the thickness of the heavily doped n+ GaN layer 108, through the thickness of the doped pGaN layer 106 and partly into the doped nGaN layer 104. Therefore the unitary dielectric layer 110 contacts the nGaN 104, pGaN 106 and n+ GaN 108.

The gate electrode G fills the gate well 116 and extends partially over the upper surface of the dielectric layer 110.

The source electrodes Si, S2 extend from the dielectric layer 110 (contacting an edge thereof, but not the gate G) through the thickness of the heavily doped n+ GaN layer 108 and into contact with a surface of the doped pGaN layer 106. Therefore the source electrodes Si, S2 contact the heavily doped n+ GaN layer 108 (as is conventional) but also the doped pGaN layer 106.

The source, drain and gate contacts Si, S2, G, D are constructed from a conductive material such as metal (e.g. molybdenum) or polysilicon.

At the junction between the n+ GaN layer 108 and the conductive metal electrodes Si, S2, an ohmic contact 120 is formed. At the junction between the pGaN layer 106 and the conductive metal electrodes Si, S2, a Schottky contact 122 is formed (see Figure 5). The Schottky contact 122 is formed in particular due to the pGaN doping level being less than 10¹⁷ cm ³

The resistor symbols R_Ch and R_epi represent channel resistance and drift region resistance respectively. Manufacture

Referring to Figures 4 and 5a to 5h, the method of manufacture of the VeGaN device of Figure 2 is shown. Figure 4 shows a flow diagram of the steps in production which are shown in detail in Figures 5a to 5h.

At step 200 (Figure 5a) a silicon substrate 112 is provided. The following epitaxial layers are grown onto the substrate 112:

• A step-graded AIGaN layer 114;

• The heavily doped n+ GaN layer 102 of thickness 0.2pm; • The doped nGaN layer 104 of thickness 9pm;

• The doped pGaN layer 106 of thickness 0.3pm;

• The heavily doped n+ GaN layer 108 of thickness 0.2pm;

The layers are grown in the order listed (starting at the silicon substrate). The width w of the device 100 at this stage is 6pm. The step-graded AIGaN layer 114 (which is eventually etched away) is provided to reduce threading dislocations during the growth process.

The drift region (doped nGaN layer 104) is required to be sufficiently thick (of thickness 9pm in this embodiment). Controlled doping concentration with low compensation to maximize the electron concentration is important for GaN crystal growth. Free electron concentration in GaN is the difference between residuals donors (Oxygen) and acceptors (Carbon) in the crystal. For reproducibility, intentional doping is added to the GaN crystal structure.

The p-n junction between the layers 104 and 106 needs to be made through epitaxial growth to maintain the good quality for crystal.

At step 202 (Figure 5b), the gate well 116 is formed from the top of the heavily doped n+ GaN layer 108, through the thickness of the heavily doped n+ GaN layer 108, doped pGaN layer 106 and partially into the doped nGaN layer 104.

At step 204 (Figure 5c), the gate dielectric layer 110 is deposited across the surface of the heavily doped n+ GaN layer 108 and into the gate well 116, coating the inner surface of the gate well 116. Preferably two such layers are provided (although one is generally sufficient).

At step 206 (Figure 5d), metal is deposited onto the dielectric layer to form the gate electrode G.

At step 208 (Figure 5e), source contact regions 118a, 118b are formed in the dielectric layer. The dielectric layer 110 and heavily doped n+ GaN layer 108 are etched away to expose the upper surface of the doped pGaN layer 106. The width ws of the exposed source contact regions is lpm.

At step 210 (Figure 5f), metal is deposited onto the heavily doped n+ GaN layer 108 to form the source contacts Si and S2.

At step 212 (Figure 5g), the device 100 is back-etched to remove the silicon substrate 112 and the step-graded AIGaN layers 114. This leaves the heavily doped n+ GaN layer 102 exposed.

At step 214 (Figure 5h), metal is deposited on the heavily doped n+ GaN layer 102 to form the drain electrode D. The device 100 is now formed.

Use The VeGaN device 100 lacks 2DEG (as it is a vertical, as opposed to a lateral device). To enable low-on resistance, the drift region is n-doped above intrinsic levels. The drift region is formed in the doped nGaN layer 104.

Performance The VeGaN device according to Figure 4 was simulated with cell simulations using TCAD Silvaco tools. The parameters for the GaN bulk mobility model are based on the experimental values and are taken from the literature for the c-plane GaN bulk layer. Self-heating effects have been neglected. Shockley- Read-Hall recombination, Auger recombination, and Fermi-Dirac statistics were enabled.

Fig. 8a is the transfer characteristics of the simulated VeGaN device for VDS=5V. Fig. 8b is the output characteristics of the VeGaN for different gate biases.

Fligh-voltage switching applications require minimization of off-state leakage current to increase the blocking capabilities. The latter suggests using of insulated-gate structures to minimize the leakage current originating from the gate contact.

Applications The device according to the invention has a wide range of applications, including electrical drive and inverter circuits for automotive and industrial electronics, domestic appliances and power transmission.

Variations

As discussed above, GaN may be substituted for Ga C> , which advantageously has a wider band gap and lower cost.

Aside from silicon, the claimed FET can be grown on Ga C> , GaN, silicon carbide or sapphire substrates. Ga C and GaN are preferable to avoid the lattice mismatch which occurs with growing Ga C or GaN epitaxial layers on silicon but are more expensive. Therefore silicon may be preferred for cost reasons (note that the above example uses a step-graded AIGaN layer to mitigate this problem). SiC is a solution which is less expensive than GaN but has a lower mismatch to pure Si.

Claims

1. A vertical GaN power FET comprising: an n doped drift region; a drain terminal on a first side of the n doped drift region; a p doped region on a second side of the n doped drift region; a gate-side n+ doped region on the opposite side of the p doped region to the n doped drift region; a gate dielectric layer extending from the n+ doped region, through the p doped region to the n doped drift region; a gate terminal in contact with the gate dielectric layer; at least one source terminal in contact with the gate-side n+ doped region, wherein the source terminal is also in contact with the p doped region.

2. A vertical GaN power FET according to claim 1, comprising a drain-side n+ doped region on the opposite side of the n doped draft region to the p doped region, in which the drain terminal is in contact with the drain-side n+ doped region.

3. A vertical GaN power FET according to claim 1 or 2, in which the regions are provided as stacked layers.

4. A vertical GaN power FET according to any preceding claim, wherein the at least one source terminal is formed through the thickness of the gate-side n+ doped region such that it contacts the p doped region.

5. A vertical GaN power FET according to claim 4, wherein the contact between the source terminal and the gate-side n+ doped region is defined on a plane normal to the contact between the source terminal and the p doped region.

6. A vertical GaN power FET according to claim 5, in which the contact between the source terminal and the gate-side n+ doped region is adjacent to the contact between the source terminal and the p doped region

7. A vertical GaN power FET according to any preceding claim, wherein the thickness of the n doped region is between 2 and 20 pm.

8. A vertical GaN power FET according to any preceding claim, wherein the thickness of the p doped layer is between 0.3pm and O.lpm.

9. A vertical GaN power FET according to any preceding claim, wherein the thickness of the n+ doped layer is between O.lpm and 0.5pm.

10. A vertical GaN power FET according to any preceding claim, wherein the thickness of the gate dielectric layer is between 20nm and 200nm.

11. A method of manufacturing a vertical GaN field effect transistor comprising the steps of: providing a substrate; growing a drain-side n+ doped layer over the substrate; growing a n doped layer on the n+ doped layer; growing a p doped layer on the n doped layer; growing a gate-side n+ doped layer on the p doped layer; forming a gate well through the gate-side n+ doped layer, p doped layer to the n doped layer; depositing a gate dielectric onto the surface of the gate well, the gate dielectric contacting the gate-side n+ doped layer, p doped layer and the n doped layer; depositing a conductive gate terminal into the gate well; depositing a conductive source terminal in contact with the gate dielectric, the gate-side n+ doped layer and the p doped layer; etching the substrate to expose the drain-side n+ doped layer; and, depositing a conductive drain terminal in contact with the drain-side n+ doped layer.

12. A method of manufacturing a vertical GaN field effect transistor according to claim 11, comprising the step of: etching part of the gate-side n+ doped layer to the p doped layer; depositing the conductive source terminal into the etched part to contact the n+ doped layer and the p doped layer.

13. A method of manufacturing a vertical GaN field effect transistor according to claim 12, wherein the contact between the source terminal and the gate-side n+ doped layer is defined on a plane normal to the contact between the source terminal and the p doped layer.

14. A method of manufacturing a vertical GaN field effect transistor according to claim 13, in which the contact between the source terminal and the gate-side n+ doped layer is adjacent to the contact between the source terminal and the p doped layer.

15. A method of manufacturing a vertical GaN field effect transistor according to any of claims 11 to 14, wherein the thickness of the n doped layer is between 2 and 20 pm.

16. A method of manufacturing a vertical GaN field effect transistor according to any of claims 11 to 15, wherein the thickness of the p doped layer is between 0.3pm and 0.1pm.

17. A method of manufacturing a vertical GaN field effect transistor according to any of claims 11 to 16, wherein the thickness of the n+ doped layer is between 0.1pm and 0.5pm.

18. A method of manufacturing a vertical GaN field effect transistor according to any of claims 11 to 17, wherein the thickness of the gate dielectric layer is between 20nm and 200nm.