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WO2020049787A1 - Transient voltage protection device - Google Patents

Transient voltage protection device Download PDF

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Publication number
WO2020049787A1
WO2020049787A1 PCT/JP2019/014600 JP2019014600W WO2020049787A1 WO 2020049787 A1 WO2020049787 A1 WO 2020049787A1 JP 2019014600 W JP2019014600 W JP 2019014600W WO 2020049787 A1 WO2020049787 A1 WO 2020049787A1
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WO
WIPO (PCT)
Prior art keywords
transient voltage
input
protection device
zener diode
backflow prevention
Prior art date
Application number
PCT/JP2019/014600
Other languages
French (fr)
Japanese (ja)
Inventor
宣夫 坂井
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to JP2019541812A priority Critical patent/JP6604464B1/en
Priority to CN201990000161.7U priority patent/CN211743125U/en
Publication of WO2020049787A1 publication Critical patent/WO2020049787A1/en

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/20Breakdown diodes, e.g. avalanche diodes
    • H10D8/25Zener diodes 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/50PIN diodes 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • the present invention relates to a transient voltage protection device for protecting an electronic circuit from a transient voltage due to electrostatic discharge or the like.
  • Patent Document 1 discloses a semiconductor integrated circuit including an electrostatic discharge protection circuit for protecting an electronic circuit from electrostatic discharge (ESD: Electrostatic Discharge).
  • the semiconductor integrated circuit disclosed in Patent Literature 1 includes a connection path connecting an external pad for inputting / outputting a signal and an internal circuit, and two protection circuits connected to the connection path.
  • the first protection circuit includes a diode connected between the connection path and the ground line, and the second protection circuit is connected between the connection path and the power supply line or between the connection path and the ground line. It consists of a diode.
  • Patent Document 1 The semiconductor integrated circuit described in Patent Document 1 is a circuit that protects an internal circuit against electrostatic discharge from the outside with respect to a single input / output terminal, but protects a plurality of input terminals from transient voltages such as electrostatic discharge.
  • a circuit for protection is constructed, the following problems occur.
  • FIG. 11 is a circuit diagram of a transient voltage protection device having two input / output terminals P1 and P2 and a common terminal Pc configured to explain the problem of the present invention.
  • This transient voltage protection device includes zener diodes ZD0, ZD1, ZD2 between input / output terminals P1, P2 and common terminal Pc.
  • the input / output terminals P1 and P2 are external terminals
  • the common terminal Pc is a ground terminal.
  • Zener diode ZD1 is connected to input / output terminal P1
  • the anode of Zener diode ZD2 is connected to input / output terminal P2
  • the anode of Zener diode ZD0 is connected to common terminal Pc
  • the cathodes of Zener diodes ZD1, ZD2, ZD3. Are commonly connected.
  • a transient-voltage-suppressor such as a Zener diode
  • TVS transient-voltage-suppressor
  • Zener diode ZD0 breaks down
  • Zener diode ZD2 also breaks down.
  • the transient current i0 flows to the common terminal Pc, and the transient current i2 leaks to the input / output terminal P2. Therefore, the transient voltage protection for the circuit connected to the input / output terminal P2 is not effectively performed.
  • an object of the present invention is to provide a circuit in which a transient voltage suppressing element is connected between a plurality of input / output terminals and a common terminal, so that a plurality of terminals can be appropriately protected against a transient voltage. It is to provide a device.
  • a transient voltage protection device as an example of the present disclosure includes: A single common terminal, a plurality of input / output terminals, and a transient voltage suppressing element having a first end connected directly or indirectly to the common terminal; A direction in which a breakdown voltage is higher than a breakdown voltage of the transient voltage suppression element and a breakdown current of the transient voltage suppression element flows between a second end of the transient voltage suppression element and the plurality of input / output terminals. Is a forward direction, and a backflow prevention circuit is connected.
  • the transient voltage suppressing element breaks down, the transient voltage is not applied from the transient voltage protection device side to the input / output terminal to which the transient voltage is not externally applied by the action of the backflow prevention circuit. Absent. Therefore, the circuits connected to the respective input / output terminals are protected.
  • a transient voltage protection device capable of appropriately protecting a plurality of terminals against a transient voltage. can get.
  • FIG. 1A is a circuit diagram of a transient voltage protection device 101A according to the first embodiment.
  • FIG. 1B is a circuit diagram of the transient voltage protection device 101B according to the first embodiment.
  • FIG. 2 is a circuit diagram showing a main part of an electronic circuit to which the transient voltage protection device 101B is connected.
  • FIG. 3 is a cross-sectional view of a main part of the semiconductor integrated circuit when the transient voltage protection device 101B is configured by a single semiconductor integrated circuit.
  • FIG. 4 is a circuit diagram of a transient voltage protection device 101C having three input / output terminals P1, P2, and P3.
  • FIG. 5 is a circuit diagram of the transient voltage protection device 102 according to the second embodiment.
  • FIG. 1A is a circuit diagram of a transient voltage protection device 101A according to the first embodiment.
  • FIG. 1B is a circuit diagram of the transient voltage protection device 101B according to the first embodiment.
  • FIG. 2 is a circuit diagram showing a main part of
  • FIG. 6 is a circuit diagram of the transient voltage protection device 103 according to the third embodiment.
  • FIG. 7 is a circuit diagram of the transient voltage protection device 104 according to the fourth embodiment.
  • FIG. 8 is a circuit diagram of the transient voltage protection device 105 according to the fifth embodiment.
  • FIG. 9 is a circuit diagram of a transient voltage protection device 106A according to the sixth embodiment.
  • FIG. 10 is a circuit diagram of another transient voltage protection device 106B according to the sixth embodiment.
  • FIG. 11 is a circuit diagram of a transient voltage protection device having two input / output terminals P1 and P2 and a common terminal Pc configured to explain the problem of the present invention.
  • one common terminal, a plurality of input / output terminals, and a transient voltage suppression element whose first end is directly or indirectly connected to the common terminal. Is provided. Then, between the second end of the transient voltage suppressing element and the plurality of input / output terminals, the breakdown voltage is higher than the breakdown voltage of the transient voltage suppressing element, and the breakdown current of the transient voltage suppressing element flows in the forward direction.
  • a backflow prevention circuit is connected to the direction.
  • the transient voltage protection device does not apply the transient voltage to the input / output terminal to which the transient voltage is not externally applied due to the operation of the backflow prevention circuit. Therefore, the circuits connected to the respective input / output terminals are protected.
  • the transient voltage suppression element is a Zener diode that breaks down a circuit connected to the input / output terminal with a voltage to be protected. According to this configuration, the transient voltage suppressing element that breaks down at a relatively low voltage can be provided, and the transient voltage protection can be performed in an electronic device with a low power supply voltage.
  • the backflow prevention circuit is a MOS-FET having a gate and a drain connected to each other. According to this configuration, since the voltage drop in the forward bias state is small and the on-resistance is low, the voltage of the input / output terminal during the transient voltage protection operation can be further suppressed.
  • the backflow prevention circuit is a PN junction diode formed at a junction between the P layer and the N layer. According to this configuration, the backflow prevention circuit can be configured with a simple circuit and a simple element structure, and a small-sized and low-cost transient voltage protection device can be obtained.
  • the backflow prevention circuit is a Zener diode. According to this configuration, a backflow prevention circuit whose breakdown voltage is higher than the breakdown voltage of the transient voltage suppression element can be configured with a simple circuit and a simple element structure, and a small-sized and low-cost transient voltage protection device can be obtained.
  • the backflow prevention circuit further includes an inductor connected in series to a path through which the breakdown current flows. According to this configuration, the high-frequency component of the breakdown current is suppressed, and the high-frequency component of the voltage applied to the input / output terminal is suppressed. In addition, the upper limit of the current flowing through each element in the path of the breakdown current is limited, and destruction of those elements can be prevented.
  • FIG. 1A is a circuit diagram of a transient voltage protection device 101A according to the first embodiment.
  • FIG. 1B is a circuit diagram of a transient voltage protection device 101B according to the first embodiment.
  • one common terminal Pc, two input / output terminals P1 and P2, and a first end T1 are directly or indirectly connected to the common terminal Pc.
  • a transient voltage suppressing element 10 Between the second end T2 of the transient voltage suppressing element 10 and the input / output terminals P1 and P2, the breakdown voltage is higher than the breakdown voltage of the transient voltage suppressing element 10, and the breakdown current of the transient voltage suppressing element 10 is Backflow prevention circuits 11 and 12, each having a flowing direction as a forward direction, are connected.
  • the second end T2 of the transient voltage suppressor 10 is connected to a common connection point CN between the transient voltage suppressor 10 and the backflow prevention circuits 11, 12. .
  • the transient voltage suppressing element 10 protects a circuit connected to the input / output terminal P1 from a transient voltage caused by electrostatic discharge (hereinafter, referred to as ESD) externally applied to the input / output terminal P1. Similarly, the transient voltage suppressing element 10 protects a circuit connected to the input / output terminal P2 from a transient voltage due to ESD or the like externally applied to the input / output terminal P2.
  • ESD electrostatic discharge
  • FIG. 1B is a circuit diagram of an example in which the transient voltage suppression element 10 and the backflow prevention circuits 11 and 12 are configured by specific elements.
  • the transient voltage suppression element 10 is configured by a Zener diode ZD0.
  • the backflow prevention circuit 11 includes a Zener diode ZD1 and a MOS-FET # Q1.
  • the backflow prevention circuit 12 includes a Zener diode ZD2 and a MOS-FET Q2.
  • the breakdown voltage of the zener diode ZD1 is higher than the voltage applied to the input / output terminals P1 and P2 in a steady state and lower than the upper limit voltage required to protect the circuit connected to the input / output terminals P1 and P2.
  • the breakdown voltage of the Zener diode ZD0 is, for example, a voltage in the range of 7V to 13V
  • the breakdown voltage of the Zener diodes ZD1, ZD2 is a voltage in the range of 7V to 13V.
  • the Zener diodes ZD1 and ZD2 are elements formed in one chip together with the Zener diode ZD0, as described later.
  • a MOS-FET Q1 is an N-channel MOS-FET, and a gate G and a drain D are connected.
  • the MOS-FET Q2 is an N-channel MOS-FET, and the gate G and the drain D are connected.
  • the voltage between the gate and the source is equal to the gate threshold voltage (Vth) while the positive voltage is applied to the drain D with respect to the source S.
  • the MOS-FET $ Q1 turns on.
  • the MOSFET Q1 in which the gate G and the drain D are connected functions as a diode having the drain D as an anode and the source S as a cathode.
  • the MOSFET Q2 in which the gate G and the drain D are connected also functions as a diode having the drain D as an anode and the source S as a cathode.
  • FIG. 2 is a circuit diagram showing a main part of an electronic circuit to which the transient voltage protection device 101B is connected.
  • the transient voltage protection device 101B is connected between the signal input / output line of the first electronic circuit 51 and the signal input / output line of the second electronic circuit 52 and the ground.
  • a forward bias voltage is applied to the Zener diode ZD1.
  • a forward bias voltage is applied to a diode constituted by the MOS-FET # Q1 in which the gate G and the drain D are connected. Therefore, the potential of the cathode of the Zener diode ZD0 with respect to the anode exceeds the breakdown voltage, and the Zener diode ZD0 breaks down.
  • a current id flows through the path of the input / output terminal P1, the backflow prevention circuit 11, the transient voltage suppressing element 10, and the common terminal Pc. This current id is a breakdown current of the Zener diode ZD0.
  • the breakdown of the Zener diode ZD0 protects the first electronic circuit 51 connected to the input / output terminal P1 from a transient voltage due to ESD. Further, in a state where the positive ESD is applied to the input / output terminal P1, a reverse bias voltage is applied to the diode constituted by the MOS-FET # Q2 in which the gate G and the drain D are connected. Therefore, the Zener diode ZD2 does not break down, and no ESD is applied to the input / output terminal P2. Therefore, the second electronic circuit 52 connected to the input / output terminal P2 is not affected by the ESD.
  • the above-described example is a case where ESD is applied to the input / output terminal P1, but when an ESD is applied to the input / output terminal P2, similarly, the input / output terminal P2 ⁇ the backflow prevention circuit 12 ⁇ the transient voltage suppression element 10 ⁇ A breakdown current flows through the path of the common terminal Pc. That is, the breakdown of the Zener diode ZD0 protects the second electronic circuit 52 connected to the input / output terminal P2 from a transient voltage due to ESD. Further, the Zener diode ZD1 does not break down, and the ESD is not applied to the input / output terminal P1. Therefore, the first electronic circuit 51 connected to the input / output terminal P1 is not affected by the ESD.
  • a diode formed by connecting the gate G and the drain D of the MOS-FET has a lower forward bias voltage drop than a PN junction diode, and thus is suitable for protecting against a lower transient voltage. Also suitable. Further, since the on-resistance is lower than that of the PN junction diode, the voltage of the input / output terminal during the transient voltage protection operation can be suppressed lower.
  • FIG. 3 is a cross-sectional view of a main part of the semiconductor integrated circuit when the transient voltage protection device 101B is constituted by a single semiconductor integrated circuit.
  • P-SUB is a P-type semiconductor substrate
  • NWELL is an N-type well.
  • P + is a P-type region and N + is an N-type region.
  • OF is an oxide insulating layer.
  • Zener diode is constituted by the N-type well NWELL and the P-type region P + and the N-type region N + formed therein. Further, an N-channel MOS-FET is constituted by the P-type substrate P-SUB, the two N-type regions N +, and the oxide insulating layer OF. Metal films corresponding to the drain D and the source S are formed on the surface of the N-type region N +. On the surface of the oxide insulating layer OF, a metal film corresponding to the gate G is formed.
  • the transient voltage protection device 101B can be constituted by a single semiconductor integrated circuit.
  • FIG. 4 is a circuit diagram of a transient voltage protection device 101C having three input / output terminals P1, P2, and P3.
  • the transient voltage protection device 101C shown in FIG. 4 includes one common terminal Pc, three input / output terminals P1, P2, P3, Zener diodes ZD1, ZD2, ZD3, and MOS-FETs Q1, Q2, Q3.
  • the Zener diode ZD1 and the MOS-FET Q1 constitute a first backflow prevention circuit
  • the Zener diode ZD2 and the MOS-FET Q2 constitute a second backflow prevention circuit
  • a third backflow prevention circuit is configured.
  • one common terminal Pc, a plurality of input / output terminals P1, P2, and P3, and a transient voltage suppressing element (Zener diode ZD0) having a first end connected to the common terminal Pc are provided.
  • the breakdown voltage is higher than the breakdown voltage of the transient voltage suppression element (Zener diode ZD0) and the transient voltage
  • a transient voltage protection device having three or more input / output terminals can be configured by connecting a backflow prevention circuit in which the direction in which the breakdown current of the suppression element (Zener diode ZD0) flows is the forward direction.
  • FIG. 5 is a circuit diagram of the transient voltage protection device 102 according to the second embodiment.
  • the transient voltage protection device 102 shown in FIG. 5 includes one common terminal Pc, two input / output terminals P1 and P2, and a Zener diode ZD0 having an anode connected to the common terminal Pc.
  • Backflow prevention circuits 11 and 12 are connected between the cathode of the Zener diode ZD0 and the input / output terminals P1 and P2, respectively.
  • the diodes are respectively constituted by the MOS-FETs Q1 and Q2, but in the present embodiment, the PN junction diodes D1 and D2 are provided in the backflow prevention circuits 11 and 12, respectively. Each is provided. Other configurations are as described in the first embodiment.
  • the configuration of the diodes D1 and D2 is simplified, and the size of the transient voltage protection device can be further reduced.
  • FIG. 6 is a circuit diagram of the transient voltage protection device 103 according to the third embodiment.
  • the transient voltage protection device 103 illustrated in FIG. 6 includes one common terminal Pc, two input / output terminals P1 and P2, and the transient voltage suppression element 10 having a first end connected to the common terminal Pc.
  • Backflow prevention circuits 11 and 12 are connected between the second end of the transient voltage suppression element 10 and the input / output terminals P1 and P2, respectively.
  • the transient voltage suppressing element 10 is constituted by the Zener diode ZD0.
  • the backflow prevention circuit 11 includes zener diodes ZD1 and ZD21.
  • the backflow prevention circuit 12 includes zener diodes ZD2 and ZD22. Other configurations are as described in the first embodiment.
  • the breakdown voltage of the Zener diodes ZD0, ZD1, ZD2, ZD21, ZD22 is the same.
  • each of the backflow prevention circuits 11 and 12 is configured by a multi-stage connected zener diode as in the present embodiment, the substantial breakdown voltage of the backflow prevention circuit is increased, so that the zener diode ZD0 is first broken down. I do.
  • a breakdown current id flows through the path of the input / output terminal P1, the zener diode ZD1, the zener diode ZD21, the zener diode ZD0, and the common terminal Pc. That is, the breakdown of the Zener diode ZD0 protects the electronic circuit connected to the input / output terminal P1 from a transient voltage due to ESD.
  • the Zener diodes ZD22 and ZD2 do not break down.
  • the ESD is not applied to the input / output terminal P2. Therefore, the electronic circuit connected to the input / output terminal P2 is also protected from ESD.
  • the Zener diode ZD0 constituting the transient voltage suppression element 10 and the Zener diodes ZD1, ZD2, ZD21, ZD22 constituting the backflow prevention circuit can be constituted by Zener diodes having the same breakdown voltage. It can be easily manufactured in the same process without special adjustment of the breakdown voltage.
  • ⁇ 4th Embodiment an example of a transient voltage protection device in which the configuration of the backflow prevention circuit is different from that shown in the first embodiment will be described.
  • FIG. 7 is a circuit diagram of the transient voltage protection device 104 according to the fourth embodiment.
  • the transient voltage protection device 104 illustrated in FIG. 7 includes one common terminal Pc, two input / output terminals P1 and P2, and the transient voltage suppression element 10 having a first end connected to the common terminal Pc.
  • Backflow prevention circuits 11 and 12 are connected between the second end of the transient voltage suppression element 10 and the input / output terminals P1 and P2, respectively.
  • the transient voltage suppressing element 10 is constituted by the Zener diode ZD0.
  • the backflow prevention circuit 11 is configured by a Zener diode ZD31.
  • the backflow prevention circuit 12 includes a Zener diode ZD32. Other configurations are as described in the first embodiment.
  • the breakdown voltage of the Zener diode ZD0 is represented by VB0
  • the breakdown voltage of the Zener diode ZD31 is represented by VB31
  • the breakdown voltage of the Zener diode ZD32 is represented by VB32
  • the relations are VB0 ⁇ VB31 and VB0 ⁇ VB32.
  • the breakdown voltage VB0 of the Zener diode ZD0 is, for example, a voltage in the range of 7V to 8V
  • the breakdown voltages VB31, VB32 of the Zener diodes ZD31, ZD32 are all in the range of, for example, 10V to 13V.
  • the Zener diodes ZD31 and ZD32 connected between the cathode of the Zener diode ZD0 (the second end of the transient voltage suppression element 10) and the input / output terminals P1 and P2 have a breakdown voltage of the Zener diode ZD0.
  • the electronic circuit connected to the input / output terminal P1 is protected from a transient voltage due to the ESD by breaking down the zener diode ZD0.
  • the breakdown voltage of the Zener diode ZD32 forming the backflow prevention circuit 12 is higher than the Zener diode ZD0 forming the transient voltage suppression element 10, even when the Zener diode ZD0 breaks down, the Zener diode ZD32 does not break down and the ESD is reduced. It is not applied to the input / output terminal P2. Therefore, the electronic circuit connected to the input / output terminal P2 is also protected from ESD.
  • the electronic circuit connected to the input / output terminal P2 is similarly protected from the transient voltage due to the ESD by breaking down the zener diode ZD0, and the Zener diode ZD31 is broken down. Therefore, the ESD is not applied to the input / output terminal P1. Therefore, the electronic circuit connected to the input / output terminal P1 is also protected from ESD.
  • ⁇ 5th Embodiment an example of a transient voltage protection device in which the configuration of the backflow prevention circuit is different from that shown in the first embodiment will be described.
  • FIG. 8 is a circuit diagram of the transient voltage protection device 105 according to the fifth embodiment.
  • the transient voltage protection device 105 illustrated in FIG. 8 includes one common terminal Pc, two input / output terminals P1 and P2, and the transient voltage suppression element 10 having a first end connected to the common terminal Pc.
  • Backflow prevention circuits 11 and 12 are connected between the second end of the transient voltage suppression element 10 and the input / output terminals P1 and P2, respectively.
  • the transient voltage suppressing element 10 is constituted by the Zener diode ZD0.
  • the backflow prevention circuit 11 includes a Zener diode ZD1, a MOS-FET Q1, and an inductor L1.
  • the backflow prevention circuit 12 includes a Zener diode ZD2, a MOS-FET Q2, and an inductor L2. Other configurations are as described in the first embodiment.
  • the transient voltage protection device 105 of the present embodiment is obtained by adding inductors L1 and L2 to the transient voltage protection device 101B shown in FIG.
  • the inductor L1 is connected in series to a path of a breakdown current flowing from the input / output terminal P1 to the common terminal Pc.
  • the inductor L2 is connected in series to the path of the breakdown current flowing from the input / output terminal P2 to the common terminal Pc.
  • the MOS-FET Q1 acts as a forward-biased diode, and the input / output terminal P1 ⁇ Zener diode ZD1 ⁇ Inductor L1 ⁇ MOS-FET Q1 ⁇ Zener diode ZD0 ⁇ common.
  • the breakdown current id flows through the path of the terminal Pc.
  • the reverse bias voltage is applied to the diode constituted by the MOS-FET # Q2 in the backflow prevention circuit 12, the diode remains off.
  • the inductor L1 Since the inductor L1 is inserted in the current path of the breakdown current, the inductor L1 suppresses the high-frequency component of the breakdown current and suppresses the high-frequency component of the voltage applied to the input / output terminal P1. That is, the transient voltage fluctuation of the input / output terminal P1 when the ESD is applied to the input / output terminal P1 and the Zener diode ZD0 breaks down is suppressed. Further, the upper limit of the current flowing through each element in the path of the breakdown current is limited, and destruction of those elements is prevented.
  • an inductor may be inserted between the second end T2 (the cathode of the Zener diode ZD0) of the transient voltage suppression element 10 and the common connection point CN. According to the configuration, the inductors L1 and L2 are unnecessary.
  • FIG. 9 is a circuit diagram of a transient voltage protection device 106A according to the sixth embodiment.
  • the transient voltage protection device 106A illustrated in FIG. 9 includes a common terminal Pc, input / output terminals P1 and P2, and transient voltage suppression elements 10p and 10n whose first terminals T1 are connected to the common terminal Pc.
  • Backflow prevention circuits 11p and 12p are connected between the second end of the transient voltage suppression element 10p and the input / output terminals P1 and P2, respectively.
  • backflow prevention circuits 11n and 12n are connected between the second end of the transient voltage suppression element 10n and the input / output terminals P1 and P2, respectively.
  • the transient voltage suppression element 10p and the backflow prevention circuits 11p and 12p constitute a transient voltage protection circuit for a positive transient voltage.
  • the transient voltage suppression element 10n and the backflow prevention circuits 11n and 12n provide a negative voltage.
  • a transient voltage protection circuit for the transient voltage is configured.
  • the transient voltage protection circuit including the transient voltage suppression element 10p and the backflow prevention circuits 11p and 12p has the same configuration as that of the transient voltage protection device shown in FIG.
  • the transient voltage suppressing element 10p is constituted by a Zener diode ZD0p.
  • the transient voltage suppression element 10n is configured by a Zener diode ZD0n.
  • the backflow prevention circuit 11p includes a zener diode ZD1p and a MOS-FET $ Q1p
  • the backflow prevention circuit 12p includes a zener diode ZD2p and a MOS-FET $ Q2p.
  • the backflow prevention circuit 11n includes a zener diode ZD1n and a MOS-FET $ Q1n
  • the backflow prevention circuit 12n includes a zener diode ZD2n and a MOS-FET $ Q2n.
  • the positive transient voltage protection circuit and the negative transient voltage protection circuit have the same circuit configuration except that the direction of each Zener diode and the direction of the MOS-FET are reversed.
  • a forward bias voltage is applied to the Zener diode ZD1p.
  • a forward bias voltage is applied to a diode composed of a MOS-FET # Q1p in which the gate G and the drain D are connected. Therefore, the potential of the cathode of the Zener diode ZD0p with respect to the anode exceeds the breakdown voltage, and the Zener diode ZD0p breaks down. As a result, the current idp flows through the path of the input / output terminal P1, the backflow prevention circuit 11p, the transient voltage suppressing element 10p, and the common terminal Pc. As a result, the input / output terminal P1 is protected from positive ESD.
  • a forward bias voltage is applied to the Zener diode ZD1n.
  • a forward bias voltage is applied to a diode composed of a MOS-FET # Q1n in which the gate G and the drain D are connected. Therefore, the potential of the cathode of the Zener diode ZD0n with respect to the anode exceeds the breakdown voltage, and the Zener diode ZD0n breaks down. As a result, the current idn flows through the path of the common terminal Pc ⁇ transient voltage suppressing element 10n ⁇ backflow prevention circuit 11n ⁇ input / output terminal P1. Thus, the input / output terminal P1 is protected from negative ESD.
  • the above example is a case where ESD is applied to the input / output terminal P1, but the same applies to a case where positive or negative ESD is applied to the input / output terminal P2.
  • ESD positive or negative ESD
  • a breakdown current flows through the path of the input / output terminal P2 ⁇ the backflow prevention circuit 12p ⁇ the transient voltage suppressing element 10p ⁇ the common terminal Pc.
  • the input / output terminal P2 is protected from positive ESD.
  • FIG. 10 is a circuit diagram of another transient voltage protection device 106B according to the present embodiment.
  • This transient voltage protection device 106B is a device that performs transient voltage protection for three input / output terminals P1, P2, and P3.
  • the transient voltage protection device 106B illustrated in FIG. 10 includes one common terminal Pc, three input / output terminals P1, P2, and P3, and zener diodes ZD0p, ZD0n, ZD31p, ZD31n, ZD32p, ZD32n, ZD33p, and ZD33n. Prepare.
  • the Zener diode ZD0p is a transient voltage suppression element for positive transient voltage protection
  • the Zener diode ZD0n is a transient voltage suppression element for negative transient voltage protection
  • the Zener diodes ZD31p, ZD32p, and ZD33p are elements that form a backflow prevention circuit for positive transient voltage protection
  • the Zener diodes ZD31n, ZD32n, and ZD33n are elements that form a backflow prevention circuit for negative transient voltage protection. is there.
  • the breakdown voltage of the Zener diode ZD0p is represented by VB0p
  • the breakdown voltage of the Zener diode ZD31p is represented by VB31p
  • the breakdown voltage of the Zener diode ZD32p is represented by VB32p
  • the breakdown voltage of the Zener diode ZD33p is represented by VB33p, respectively.
  • the breakdown voltage of the Zener diode ZD0n is represented by VB0n
  • the breakdown voltage of the Zener diode ZD31n is represented by VB31n
  • the breakdown voltage of the Zener diode ZD32n is represented by VB32n
  • the breakdown voltage of the Zener diode ZD33n is represented by VB33n, respectively.
  • the electronic circuit connected to the input / output terminal P1 breaks down due to the breakdown of the Zener diode ZD0p. Protected. Further, for example, when a negative ESD is applied to the input / output terminal P1, the Zener diode ZD0n breaks down, and the electronic circuit connected to the input / output terminal P1 is protected from a transient voltage due to the negative ESD. Similarly, the input / output terminals P2 and P3 are protected from positive and negative transient voltages.
  • the first ends of the transient voltage suppression elements 10, 10p, and 10n are directly connected to the common terminal Pc.
  • the first ends of the transient voltage suppression elements 10, 10p, and 10n are common. It may be indirectly connected to the terminal Pc.
  • an inductor may be inserted between the first terminals of the transient voltage suppression elements 10, 10p, and 10n and the common terminal Pc.
  • the common terminal Pc may not be directly connected to the ground but may be connected indirectly.
  • an inductor may be inserted between the common terminal Pc and the ground.
  • CN common connection point D: drain D1, D2: diode G: gate id, idp, idn: breakdown current L1, L2: inductor P1, P2, P3: input / output terminal Pc: common terminal Q1, Q2: MOS-FET S Source T1 First end T2 Second end ZD0, ZD1, ZD2, ZD3 Zener diodes ZD0n, ZD1n, ZD2n Zener diodes ZD0p, ZD1p, ZD2p Zener diodes ZD21, ZD22 Zener diodes ZD31, ZD32 Zener Diodes ZD31n, ZD32n, ZD33n Zener diodes ZD31p, ZD32p, ZD33p Zener diodes 10, 10p, 10n Transient voltage suppressing elements 11, 12 Backflow prevention circuits 11n, 12n Backflow prevention circuits 11p, 12p Backflow prevention circuits 51 1st electronic circuit 52 ... 2nd electronic circuit 101A, 101

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Abstract

A transient voltage protection device (101A, 101B) is provided with: one common terminal (Pc); a plurality of input/output terminals (P1, P2); and a transient voltage limiting element (10) of which a first end (T1) is connected to the common terminal (Pc) directly or indirectly. Between a second end (T2) of the transient voltage limiting element (10) and the plurality of input/output terminals (P1, P2), reverse-flow prevention circuits (11, 12) are connected which have a breakdown voltage higher than a breakdown voltage of the transient voltage limiting element (10) and of which a forward direction corresponds to a direction in which a breakdown current of the transient voltage limiting element (10) flows. This configuration affords appropriate protection against transient voltage with respect to a plurality of terminals of the transient voltage protection device.

Description

過渡電圧保護装置Transient voltage protection device

 本発明は、静電気放電等による過渡電圧から電子回路を保護する過渡電圧保護装置に関する。 (4) The present invention relates to a transient voltage protection device for protecting an electronic circuit from a transient voltage due to electrostatic discharge or the like.

 特許文献1には、静電気放電(ESD:Electrostatic Discharge )から電子回路を保護する静電気放電保護回路を備えた半導体集積回路が示されている。特許文献1に示されている半導体集積回路は、信号を入出力する外部パッドと内部回路とを接続する接続経路と、この接続経路に接続された二つの保護回路とを備える。第1の保護回路は接続経路と接地ラインとの間に接続されたダイオードで構成され、第2の保護回路は接続経路と電源ラインとの間、又は接続経路と接地ラインとの間に接続されたダイオードで構成される。 Patent Document 1 discloses a semiconductor integrated circuit including an electrostatic discharge protection circuit for protecting an electronic circuit from electrostatic discharge (ESD: Electrostatic Discharge). The semiconductor integrated circuit disclosed in Patent Literature 1 includes a connection path connecting an external pad for inputting / outputting a signal and an internal circuit, and two protection circuits connected to the connection path. The first protection circuit includes a diode connected between the connection path and the ground line, and the second protection circuit is connected between the connection path and the power supply line or between the connection path and the ground line. It consists of a diode.

特開2009-54851号公報JP 2009-54851 A

 特許文献1に記載の半導体集積回路は、単一の入出力端子について、外部からの静電気放電に対して内部回路を保護する回路であるが、複数の入力端子について静電気放電などの過渡電圧に対して保護する回路を構成すると以降に述べるような問題が生じる。 The semiconductor integrated circuit described in Patent Document 1 is a circuit that protects an internal circuit against electrostatic discharge from the outside with respect to a single input / output terminal, but protects a plurality of input terminals from transient voltages such as electrostatic discharge. When a circuit for protection is constructed, the following problems occur.

 図11は、本発明の課題を説明するために構成した、二つの入出力端子P1,P2及び共通端子Pcを備える過渡電圧保護装置の回路図である。この過渡電圧保護装置は、入出力端子P1,P2と共通端子Pcとの間にツェナーダイオードZD0,ZD1,ZD2を備える。通常、入出力端子P1,P2は外部端子であり、共通端子Pcはグランド端子である。ツェナーダイオードZD1のアノードは入出力端子P1に接続され、ツェナーダイオードZD2のアノードは入出力端子P2に接続され、ツェナーダイオードZD0のアノードは共通端子Pcに接続され、ツェナーダイオードZD1,ZD2,ZD3のカソードは共通接続される。 FIG. 11 is a circuit diagram of a transient voltage protection device having two input / output terminals P1 and P2 and a common terminal Pc configured to explain the problem of the present invention. This transient voltage protection device includes zener diodes ZD0, ZD1, ZD2 between input / output terminals P1, P2 and common terminal Pc. Usually, the input / output terminals P1 and P2 are external terminals, and the common terminal Pc is a ground terminal. The anode of Zener diode ZD1 is connected to input / output terminal P1, the anode of Zener diode ZD2 is connected to input / output terminal P2, the anode of Zener diode ZD0 is connected to common terminal Pc, and the cathodes of Zener diodes ZD1, ZD2, ZD3. Are commonly connected.

 ところが、このように複数の入出力端子と共通端子との間にツェナーダイオード等の過渡電圧抑制素子(TVS:transient-voltage-suppressor )を接続した回路では、例えば入出力端子P1に過渡電圧が印加されてツェナーダイオードZD0がブレークダウンするとき、ツェナーダイオードZD2もブレークダウンしてしまう。そのことで、過渡電流i0が共通端子Pcに流れると共に、入出力端子P2に過渡電流i2が漏洩しまう。そのため、入出力端子P2に接続されている回路に対する過渡電圧保護が有効に成されない。同様に、入出力端子P2に過渡電圧が印加されてツェナーダイオードZD0がブレークダウンするときも、ツェナーダイオードZD1がブレークダウンしてしまう。そのことで、過渡電流が共通端子Pcに流れると共に、入出力端子P1に漏洩しまう。そのため、入出力端子P1に接続されている回路に対する過渡電圧保護が有効に成されない。 However, in such a circuit in which a transient-voltage-suppressor (TVS) such as a Zener diode is connected between a plurality of input / output terminals and a common terminal, for example, a transient voltage is applied to the input / output terminal P1. Then, when the Zener diode ZD0 breaks down, the Zener diode ZD2 also breaks down. As a result, the transient current i0 flows to the common terminal Pc, and the transient current i2 leaks to the input / output terminal P2. Therefore, the transient voltage protection for the circuit connected to the input / output terminal P2 is not effectively performed. Similarly, when a transient voltage is applied to the input / output terminal P2 and the Zener diode ZD0 breaks down, the Zener diode ZD1 also breaks down. As a result, a transient current flows to the common terminal Pc and leaks to the input / output terminal P1. Therefore, the transient voltage protection for the circuit connected to the input / output terminal P1 is not effectively performed.

 そこで、本発明の目的は、複数の入出力端子と共通端子との間に過渡電圧抑制素子が接続された回路において、複数の端子について過渡電圧に対して適正に保護できるようにした過渡電圧保護装置を提供することにある。 Therefore, an object of the present invention is to provide a circuit in which a transient voltage suppressing element is connected between a plurality of input / output terminals and a common terminal, so that a plurality of terminals can be appropriately protected against a transient voltage. It is to provide a device.

 本開示の一例としての過渡電圧保護装置は、
 1つの共通端子と、複数の入出力端子と、第1端が前記共通端子に直接的に又は間接的に接続された過渡電圧抑制素子と、を備え、
 前記過渡電圧抑制素子の第2端と前記複数の入出力端子との間に、ブレークダウン電圧が前記過渡電圧抑制素子のブレークダウン電圧より高く、かつ前記過渡電圧抑制素子のブレークダウン電流が流れる方向を順方向とする、逆流防止回路が接続されている。
A transient voltage protection device as an example of the present disclosure includes:
A single common terminal, a plurality of input / output terminals, and a transient voltage suppressing element having a first end connected directly or indirectly to the common terminal;
A direction in which a breakdown voltage is higher than a breakdown voltage of the transient voltage suppression element and a breakdown current of the transient voltage suppression element flows between a second end of the transient voltage suppression element and the plurality of input / output terminals. Is a forward direction, and a backflow prevention circuit is connected.

 上記構成によれば、過渡電圧抑制素子がブレークダウンする状態でも、逆流防止回路の作用により、外部から過渡電圧が印加されない入出力端子に、過渡電圧保護装置側から過渡電圧が印加されることはない。そのため、各入出力端子に接続されている回路が保護される。 According to the above configuration, even when the transient voltage suppressing element breaks down, the transient voltage is not applied from the transient voltage protection device side to the input / output terminal to which the transient voltage is not externally applied by the action of the backflow prevention circuit. Absent. Therefore, the circuits connected to the respective input / output terminals are protected.

 本発明によれば、複数の入出力端子と共通端子との間に過渡電圧抑制素子が接続された回路において、複数の端子について過渡電圧に対して適正に保護できるようにした過渡電圧保護装置が得られる。 According to the present invention, in a circuit in which a transient voltage suppressing element is connected between a plurality of input / output terminals and a common terminal, there is provided a transient voltage protection device capable of appropriately protecting a plurality of terminals against a transient voltage. can get.

図1(A)は第1の実施形態に係る過渡電圧保護装置101Aの回路図である。図1(B)は第1の実施形態に係る過渡電圧保護装置101Bの回路図である。FIG. 1A is a circuit diagram of a transient voltage protection device 101A according to the first embodiment. FIG. 1B is a circuit diagram of the transient voltage protection device 101B according to the first embodiment. 図2は、過渡電圧保護装置101Bが接続された電子回路の主要部を示す回路図である。FIG. 2 is a circuit diagram showing a main part of an electronic circuit to which the transient voltage protection device 101B is connected. 図3は、過渡電圧保護装置101Bを単一の半導体集積回路で構成した場合の半導体集積回路の主要部の断面図である。FIG. 3 is a cross-sectional view of a main part of the semiconductor integrated circuit when the transient voltage protection device 101B is configured by a single semiconductor integrated circuit. 図4は三つの入出力端子P1,P2,P3を有する過渡電圧保護装置101Cの回路図である。FIG. 4 is a circuit diagram of a transient voltage protection device 101C having three input / output terminals P1, P2, and P3. 図5は第2の実施形態に係る過渡電圧保護装置102の回路図である。FIG. 5 is a circuit diagram of the transient voltage protection device 102 according to the second embodiment. 図6は第3の実施形態に係る過渡電圧保護装置103の回路図である。FIG. 6 is a circuit diagram of the transient voltage protection device 103 according to the third embodiment. 図7は第4の実施形態に係る過渡電圧保護装置104の回路図である。FIG. 7 is a circuit diagram of the transient voltage protection device 104 according to the fourth embodiment. 図8は第5の実施形態に係る過渡電圧保護装置105の回路図である。FIG. 8 is a circuit diagram of the transient voltage protection device 105 according to the fifth embodiment. 図9は第6の実施形態に係る過渡電圧保護装置106Aの回路図である。FIG. 9 is a circuit diagram of a transient voltage protection device 106A according to the sixth embodiment. 図10は第6の実施形態に係る別の過渡電圧保護装置106Bの回路図である。FIG. 10 is a circuit diagram of another transient voltage protection device 106B according to the sixth embodiment. 図11は、本発明の課題を説明するために構成した、二つの入出力端子P1,P2及び共通端子Pcを備える過渡電圧保護装置の回路図である。FIG. 11 is a circuit diagram of a transient voltage protection device having two input / output terminals P1 and P2 and a common terminal Pc configured to explain the problem of the present invention.

 まず、本発明に係る過渡電圧保護装置における幾つかの態様について記載する。 First, some aspects of the transient voltage protection device according to the present invention will be described.

 本発明に係る第1の態様の過渡電圧保護装置では、1つの共通端子と、複数の入出力端子と、第1端が共通端子に直接的に又は間接的に接続された過渡電圧抑制素子と、を備える。そして、過渡電圧抑制素子の第2端と複数の入出力端子との間に、ブレークダウン電圧が過渡電圧抑制素子のブレークダウン電圧より高く、かつ過渡電圧抑制素子のブレークダウン電流が流れる方向を順方向とする、逆流防止回路が接続されている。この構成によれば、過渡電圧抑制素子がブレークダウンする状態でも、逆流防止回路の作用により、外部から過渡電圧が印加されない入出力端子には、過渡電圧保護装置側から過渡電圧が印加されない。そのため、各入出力端子に接続されている回路が保護される。 In the transient voltage protection device according to the first aspect of the present invention, one common terminal, a plurality of input / output terminals, and a transient voltage suppression element whose first end is directly or indirectly connected to the common terminal. , Is provided. Then, between the second end of the transient voltage suppressing element and the plurality of input / output terminals, the breakdown voltage is higher than the breakdown voltage of the transient voltage suppressing element, and the breakdown current of the transient voltage suppressing element flows in the forward direction. A backflow prevention circuit is connected to the direction. According to this configuration, even when the transient voltage suppressing element breaks down, the transient voltage protection device does not apply the transient voltage to the input / output terminal to which the transient voltage is not externally applied due to the operation of the backflow prevention circuit. Therefore, the circuits connected to the respective input / output terminals are protected.

 本発明に係る第2の態様の過渡電圧保護装置では、前記過渡電圧抑制素子は、前記入出力端子に接続される回路を保護すべき電圧でブレークダウンするツェナーダイオードである。この構成によれば、比較的低い電圧でブレークダウンする過渡電圧抑制素子を設けることができ、電源電圧の低い電子機器において過渡電圧保護を行える。 In the transient voltage protection device according to a second aspect of the present invention, the transient voltage suppression element is a Zener diode that breaks down a circuit connected to the input / output terminal with a voltage to be protected. According to this configuration, the transient voltage suppressing element that breaks down at a relatively low voltage can be provided, and the transient voltage protection can be performed in an electronic device with a low power supply voltage.

 本発明に係る第3の態様の過渡電圧保護装置では、前記逆流防止回路は、ゲートとドレインとが接続されたMOS-FETである。この構成によれば、順方向バイアス状態での電圧降下が小さく、オン抵抗が低いので、過渡電圧保護動作時の入出力端子の電圧をより低く抑えられる。 In the transient voltage protection device according to a third aspect of the present invention, the backflow prevention circuit is a MOS-FET having a gate and a drain connected to each other. According to this configuration, since the voltage drop in the forward bias state is small and the on-resistance is low, the voltage of the input / output terminal during the transient voltage protection operation can be further suppressed.

 本発明に係る第4の態様の過渡電圧保護装置では、前記逆流防止回路は、P層とN層との接合部に形成されるPN接合ダイオードである。この構成によれば、簡素な回路、簡素な素子構造で逆流防止回路を構成でき、小型・低コストの過渡電圧保護装置が得られる。 In the transient voltage protection device according to a fourth aspect of the present invention, the backflow prevention circuit is a PN junction diode formed at a junction between the P layer and the N layer. According to this configuration, the backflow prevention circuit can be configured with a simple circuit and a simple element structure, and a small-sized and low-cost transient voltage protection device can be obtained.

 本発明に係る第5の態様の過渡電圧保護装置では、前記逆流防止回路はツェナーダイオードである。この構成によれば、簡素な回路、簡素な素子構造で、ブレークダウン電圧が過渡電圧抑制素子のブレークダウン電圧より高い逆流防止回路を構成でき、小型・低コストの過渡電圧保護装置が得られる。 In the transient voltage protection device according to a fifth aspect of the present invention, the backflow prevention circuit is a Zener diode. According to this configuration, a backflow prevention circuit whose breakdown voltage is higher than the breakdown voltage of the transient voltage suppression element can be configured with a simple circuit and a simple element structure, and a small-sized and low-cost transient voltage protection device can be obtained.

 本発明に係る第6の態様の過渡電圧保護装置では、前記逆流防止回路は、前記ブレークダウン電流が流れる経路に直列接続されたインダクタをさらに備える。この構成によれば、ブレークダウン電流の高周波成分が抑制され、入出力端子の印加電圧の高周波成分が抑制される。また、ブレークダウン電流の経路中の各素子に流れる電流の上限が制限されて、それら素子の破壊が予防できる。 In the transient voltage protection device according to a sixth aspect of the present invention, the backflow prevention circuit further includes an inductor connected in series to a path through which the breakdown current flows. According to this configuration, the high-frequency component of the breakdown current is suppressed, and the high-frequency component of the voltage applied to the input / output terminal is suppressed. In addition, the upper limit of the current flowing through each element in the path of the breakdown current is limited, and destruction of those elements can be prevented.

 以降、図を参照して幾つかの具体的な例を挙げて、本発明を実施するための複数の形態を示す。各図中には同一箇所に同一符号を付している。要点の説明又は理解の容易性を考慮して、実施形態を説明の便宜上分けて示すが、異なる実施形態で示した構成の部分的な置換又は組み合わせは可能である。第2の実施形態以降では第1の実施形態と共通の事柄についての記述を省略し、異なる点についてのみ説明する。特に、同様の構成による同様の作用効果については実施形態毎には逐次言及しない。 Hereinafter, a plurality of embodiments for implementing the present invention will be described with reference to the drawings and some specific examples. In the drawings, the same parts are denoted by the same reference numerals. Although the embodiments are shown separately for the convenience of explanation in consideration of the explanation of the main points or the ease of understanding, partial replacement or combination of the configurations shown in different embodiments is possible. From the second embodiment onward, description of matters common to the first embodiment will be omitted, and only different points will be described. In particular, the same operation and effect of the same configuration will not be sequentially described for each embodiment.

《第1の実施形態》
 図1(A)は第1の実施形態に係る過渡電圧保護装置101Aの回路図である。また、図1(B)は第1の実施形態に係る過渡電圧保護装置101Bの回路図である。
<< 1st Embodiment >>
FIG. 1A is a circuit diagram of a transient voltage protection device 101A according to the first embodiment. FIG. 1B is a circuit diagram of a transient voltage protection device 101B according to the first embodiment.

 図1(A)に示す過渡電圧保護装置101Aは、1つの共通端子Pcと、二つの入出力端子P1,P2と、第1端T1が共通端子Pcに直接的に又は間接的に接続された過渡電圧抑制素子10と、を備える。過渡電圧抑制素子10の第2端T2と入出力端子P1,P2との間には、ブレークダウン電圧が過渡電圧抑制素子10のブレークダウン電圧より高く、かつ過渡電圧抑制素子10のブレークダウン電流が流れる方向を順方向とする、逆流防止回路11,12がそれぞれ接続されている。図1(A)、図1(B)に示す例では、過渡電圧抑制素子10と逆流防止回路11,12との共通接続点CNに過渡電圧抑制素子10の第2端T2が接続されている。 In the transient voltage protection device 101A shown in FIG. 1A, one common terminal Pc, two input / output terminals P1 and P2, and a first end T1 are directly or indirectly connected to the common terminal Pc. And a transient voltage suppressing element 10. Between the second end T2 of the transient voltage suppressing element 10 and the input / output terminals P1 and P2, the breakdown voltage is higher than the breakdown voltage of the transient voltage suppressing element 10, and the breakdown current of the transient voltage suppressing element 10 is Backflow prevention circuits 11 and 12, each having a flowing direction as a forward direction, are connected. In the example shown in FIGS. 1A and 1B, the second end T2 of the transient voltage suppressor 10 is connected to a common connection point CN between the transient voltage suppressor 10 and the backflow prevention circuits 11, 12. .

 上記過渡電圧抑制素子10は、入出力端子P1に繋がっている回路を、外部から入出力端子P1に印加される静電気放電(以下、ESD)等による過渡電圧から保護する。同様に、上記過渡電圧抑制素子10は、入出力端子P2に繋がっている回路を、外部から入出力端子P2に印加されるESD等による過渡電圧から保護する。 (4) The transient voltage suppressing element 10 protects a circuit connected to the input / output terminal P1 from a transient voltage caused by electrostatic discharge (hereinafter, referred to as ESD) externally applied to the input / output terminal P1. Similarly, the transient voltage suppressing element 10 protects a circuit connected to the input / output terminal P2 from a transient voltage due to ESD or the like externally applied to the input / output terminal P2.

 図1(B)は上記過渡電圧抑制素子10及び上記逆流防止回路11,12を具体的な素子で構成した例の回路図である。図1(B)に示す過渡電圧保護装置101Bにおいて、過渡電圧抑制素子10はツェナーダイオードZD0で構成されている。逆流防止回路11はツェナーダイオードZD1及びMOS-FET Q1で構成されている。逆流防止回路12はツェナーダイオードZD2及びMOS-FET Q2で構成されている。 FIG. 1B is a circuit diagram of an example in which the transient voltage suppression element 10 and the backflow prevention circuits 11 and 12 are configured by specific elements. In the transient voltage protection device 101B shown in FIG. 1B, the transient voltage suppression element 10 is configured by a Zener diode ZD0. The backflow prevention circuit 11 includes a Zener diode ZD1 and a MOS-FET # Q1. The backflow prevention circuit 12 includes a Zener diode ZD2 and a MOS-FET Q2.

 ツェナーダイオードZD1のブレークダウン電圧は、定常時に入出力端子P1,P2に印加される電圧より高く、かつ入出力端子P1,P2に繋がっている回路を保護するに要する上限電圧より低い電圧である。ツェナーダイオードZD0のブレークダウン電圧は例えば7Vから13Vの範囲内の電圧であり、ツェナーダイオードZD1,ZD2のブレークダウン電圧は7Vから13Vの範囲内の電圧である。ツェナーダイオードZD1,ZD2は、後に示すように、ツェナーダイオードZD0と共に一つのチップ内に構成される素子である。 The breakdown voltage of the zener diode ZD1 is higher than the voltage applied to the input / output terminals P1 and P2 in a steady state and lower than the upper limit voltage required to protect the circuit connected to the input / output terminals P1 and P2. The breakdown voltage of the Zener diode ZD0 is, for example, a voltage in the range of 7V to 13V, and the breakdown voltage of the Zener diodes ZD1, ZD2 is a voltage in the range of 7V to 13V. The Zener diodes ZD1 and ZD2 are elements formed in one chip together with the Zener diode ZD0, as described later.

 図1(B)において、MOS-FET Q1はNチャンネルMOS-FETであり、ゲートGとドレインDとが接続されている。同様に、MOS-FET Q2はNチャンネルMOS-FETであり、ゲートGとドレインDとが接続されている。ゲートGとドレインDとが接続されたNチャンネルMOS-FET Q1は、ソースSに対して正の電圧がドレインDに印加される状態で、ゲート・ソース間電圧がゲートしきい値電圧 (Vth)を超えて、MOS-FET Q1はオンする。逆に、MOS-FET Q1のソースSに対して低い電圧がドレインDに印加される状態、又はドレイン・ソース間電圧が0である状態で、ゲート・ソース間電圧はゲートしきい値電圧 (Vth)を超えないので、MOS-FET Q1はオフする。つまり、ゲートGとドレインDとが接続されたMOS-FET Q1は、ドレインDをアノード、ソースSをカソードとするダイオードとして作用する。同様に、ゲートGとドレインDとが接続されたMOS-FET Q2も、ドレインDをアノード、ソースSをカソードとするダイオードとして作用する。 In FIG. 1B, a MOS-FET Q1 is an N-channel MOS-FET, and a gate G and a drain D are connected. Similarly, the MOS-FET Q2 is an N-channel MOS-FET, and the gate G and the drain D are connected. In the N-channel MOS-FET $ Q1 in which the gate G and the drain D are connected, the voltage between the gate and the source is equal to the gate threshold voltage (Vth) while the positive voltage is applied to the drain D with respect to the source S. , The MOS-FET $ Q1 turns on. Conversely, when a low voltage is applied to the drain D with respect to the source S of the MOS-FET $ Q1, or when the drain-source voltage is 0, the gate-source voltage becomes the gate threshold voltage (Vth ), The MOS-FET $ Q1 is turned off. In other words, the MOSFET Q1 in which the gate G and the drain D are connected functions as a diode having the drain D as an anode and the source S as a cathode. Similarly, the MOSFET Q2 in which the gate G and the drain D are connected also functions as a diode having the drain D as an anode and the source S as a cathode.

 図2は、過渡電圧保護装置101Bが接続された電子回路の主要部を示す回路図である。この例では、第1電子回路51の信号入出力ライン及び第2電子回路52の信号入出力ラインとグランドとの間に過渡電圧保護装置101Bが接続されている。 FIG. 2 is a circuit diagram showing a main part of an electronic circuit to which the transient voltage protection device 101B is connected. In this example, the transient voltage protection device 101B is connected between the signal input / output line of the first electronic circuit 51 and the signal input / output line of the second electronic circuit 52 and the ground.

 図1(B)、図2において、例えば入出力端子P1に正のESDが印加されると、ツェナーダイオードZD1に順方向バイアス電圧が印加される。また、ゲートGとドレインDとが接続されたMOS-FET Q1で構成されるダイオードに順方向バイアス電圧が印加される。したがって、ツェナーダイオードZD0のアノードに対するカソードの電位がブレークダウン電圧を超えて、ツェナーダイオードZD0はブレークダウンする。これにより、入出力端子P1→逆流防止回路11→過渡電圧抑制素子10→共通端子Pcの経路で電流idが流れる。この電流idはツェナーダイオードZD0のブレークダウン電流である。 In FIGS. 1B and 2, for example, when a positive ESD is applied to the input / output terminal P1, a forward bias voltage is applied to the Zener diode ZD1. Further, a forward bias voltage is applied to a diode constituted by the MOS-FET # Q1 in which the gate G and the drain D are connected. Therefore, the potential of the cathode of the Zener diode ZD0 with respect to the anode exceeds the breakdown voltage, and the Zener diode ZD0 breaks down. As a result, a current id flows through the path of the input / output terminal P1, the backflow prevention circuit 11, the transient voltage suppressing element 10, and the common terminal Pc. This current id is a breakdown current of the Zener diode ZD0.

 上述のとおり、ツェナーダイオードZD0がブレークダウンすることで入出力端子P1に繋がっている第1電子回路51はESDによる過渡電圧から保護される。また、入出力端子P1に正のESDが印加される状態で、ゲートGとドレインDとが接続されたMOS-FET Q2で構成されるダイオードに逆方向バイアス電圧が印加される。したがって、ツェナーダイオードZD2はブレークダウンせず、ESDが入出力端子P2に印加されることはない。そのため、入出力端子P2に繋がっている第2電子回路52はESDの影響を受けない。 As described above, the breakdown of the Zener diode ZD0 protects the first electronic circuit 51 connected to the input / output terminal P1 from a transient voltage due to ESD. Further, in a state where the positive ESD is applied to the input / output terminal P1, a reverse bias voltage is applied to the diode constituted by the MOS-FET # Q2 in which the gate G and the drain D are connected. Therefore, the Zener diode ZD2 does not break down, and no ESD is applied to the input / output terminal P2. Therefore, the second electronic circuit 52 connected to the input / output terminal P2 is not affected by the ESD.

 上述の例は、入出力端子P1にESDが印加される場合であるが、入出力端子P2にESDが印加される場合、同様にして入出力端子P2→逆流防止回路12→過渡電圧抑制素子10→共通端子Pcの経路で、ブレークダウン電流が流れる。つまり、ツェナーダイオードZD0がブレークダウンすることで入出力端子P2に繋がっている第2電子回路52はESDによる過渡電圧から保護される。また、ツェナーダイオードZD1はブレークダウンせず、ESDが入出力端子P1に印加されることはない。そのため、入出力端子P1に繋がっている第1電子回路51はESDの影響を受けない。 The above-described example is a case where ESD is applied to the input / output terminal P1, but when an ESD is applied to the input / output terminal P2, similarly, the input / output terminal P2 → the backflow prevention circuit 12 → the transient voltage suppression element 10 → A breakdown current flows through the path of the common terminal Pc. That is, the breakdown of the Zener diode ZD0 protects the second electronic circuit 52 connected to the input / output terminal P2 from a transient voltage due to ESD. Further, the Zener diode ZD1 does not break down, and the ESD is not applied to the input / output terminal P1. Therefore, the first electronic circuit 51 connected to the input / output terminal P1 is not affected by the ESD.

 なお、MOS-FETのゲートGとドレインDとが接続されることで構成されるダイオードは、PN接合ダイオードに比べて順方向バイアスの降下電圧が低いので、より低い過渡電圧に対しての保護にも適する。また、PN接合ダイオードに比べてオン抵抗が低いので、過渡電圧保護動作時の入出力端子の電圧をより低く抑えられる。 Note that a diode formed by connecting the gate G and the drain D of the MOS-FET has a lower forward bias voltage drop than a PN junction diode, and thus is suitable for protecting against a lower transient voltage. Also suitable. Further, since the on-resistance is lower than that of the PN junction diode, the voltage of the input / output terminal during the transient voltage protection operation can be suppressed lower.

 図3は過渡電圧保護装置101Bを単一の半導体集積回路で構成した場合の半導体集積回路の主要部の断面図である。図3において、P-SUBはP型半導体基板、NWELLはN型ウェルである。P+はP型領域、N+はN型領域である。OFは酸化絶縁層である。 FIG. 3 is a cross-sectional view of a main part of the semiconductor integrated circuit when the transient voltage protection device 101B is constituted by a single semiconductor integrated circuit. In FIG. 3, P-SUB is a P-type semiconductor substrate, and NWELL is an N-type well. P + is a P-type region and N + is an N-type region. OF is an oxide insulating layer.

 N型ウェルNWELLと、そこに形成されたP型領域P+及びN型領域N+とでツェナーダイオードが構成されている。また、P型基板P-SUBと二つのN型領域N+と酸化絶縁層OFとでNチャンネルMOS-FETが構成されている。N型領域N+の表面には、ドレインD及びソースSに対応する金属膜がそれぞれ形成されている。酸化絶縁層OFの表面にはゲートGに対応する金属膜が形成されている。 ツ ェ A Zener diode is constituted by the N-type well NWELL and the P-type region P + and the N-type region N + formed therein. Further, an N-channel MOS-FET is constituted by the P-type substrate P-SUB, the two N-type regions N +, and the oxide insulating layer OF. Metal films corresponding to the drain D and the source S are formed on the surface of the N-type region N +. On the surface of the oxide insulating layer OF, a metal film corresponding to the gate G is formed.

 このようにして、過渡電圧保護装置101Bは単一の半導体集積回路で構成できる。 よ う Thus, the transient voltage protection device 101B can be constituted by a single semiconductor integrated circuit.

 以上に示した例では二つの入出力端子P1,P2を有する過渡電圧保護装置の例であったが、同様にして三つ以上の入出力端子を有する過渡電圧保護装置を構成することができる。例えば、図4は三つの入出力端子P1,P2,P3を有する過渡電圧保護装置101Cの回路図である。図4に示す過渡電圧保護装置101Cは、1つの共通端子Pcと、三つの入出力端子P1,P2,P3と、ツェナーダイオードZD1,ZD2,ZD3と、MOS-FET Q1,Q2,Q3を備える。ツェナーダイオードZD1とMOS-FET Q1とで第1の逆流防止回路が構成され、ツェナーダイオードZD2とMOS-FET Q2とで第2の逆流防止回路が構成され、ツェナーダイオードZD3とMOS-FET Q3とで第3の逆流防止回路が構成される。 In the example described above, the transient voltage protection device having two input / output terminals P1 and P2 has been described. However, a transient voltage protection device having three or more input / output terminals can be similarly configured. For example, FIG. 4 is a circuit diagram of a transient voltage protection device 101C having three input / output terminals P1, P2, and P3. The transient voltage protection device 101C shown in FIG. 4 includes one common terminal Pc, three input / output terminals P1, P2, P3, Zener diodes ZD1, ZD2, ZD3, and MOS-FETs Q1, Q2, Q3. The Zener diode ZD1 and the MOS-FET Q1 constitute a first backflow prevention circuit, the Zener diode ZD2 and the MOS-FET Q2 constitute a second backflow prevention circuit, and the Zener diode ZD3 and the MOS-FET Q3. A third backflow prevention circuit is configured.

 このように、1つの共通端子Pcと、複数の入出力端子P1,P2,P3と、第1端が共通端子Pcに接続された過渡電圧抑制素子(ツェナーダイオードZD0)と、を備え、過渡電圧抑制素子(ツェナーダイオードZD0)の第2端と複数の入出力端子P1,P2,P3との間に、ブレークダウン電圧が過渡電圧抑制素子(ツェナーダイオードZD0)のブレークダウン電圧より高く、かつ過渡電圧抑制素子(ツェナーダイオードZD0)のブレークダウン電流が流れる方向を順方向とする、逆流防止回路が接続されることで、三つ以上の入出力端子を有する過渡電圧保護装置を構成することができる。 As described above, one common terminal Pc, a plurality of input / output terminals P1, P2, and P3, and a transient voltage suppressing element (Zener diode ZD0) having a first end connected to the common terminal Pc are provided. Between the second end of the suppression element (Zener diode ZD0) and the plurality of input / output terminals P1, P2, P3, the breakdown voltage is higher than the breakdown voltage of the transient voltage suppression element (Zener diode ZD0) and the transient voltage A transient voltage protection device having three or more input / output terminals can be configured by connecting a backflow prevention circuit in which the direction in which the breakdown current of the suppression element (Zener diode ZD0) flows is the forward direction.

《第2の実施形態》
 第2の実施形態では、逆流防止回路の構成が第1の実施形態で示したものとは異なる過渡電圧保護装置の例を示す。
<< 2nd Embodiment >>
In the second embodiment, an example of a transient voltage protection device in which the configuration of the backflow prevention circuit is different from that shown in the first embodiment will be described.

 図5は第2の実施形態に係る過渡電圧保護装置102の回路図である。図5に示す過渡電圧保護装置102は、1つの共通端子Pcと、二つの入出力端子P1,P2と、アノードが共通端子Pcに接続されたツェナーダイオードZD0と、を備える。ツェナーダイオードZD0のカソードと入出力端子P1,P2との間には、逆流防止回路11,12がそれぞれ接続されている。 FIG. 5 is a circuit diagram of the transient voltage protection device 102 according to the second embodiment. The transient voltage protection device 102 shown in FIG. 5 includes one common terminal Pc, two input / output terminals P1 and P2, and a Zener diode ZD0 having an anode connected to the common terminal Pc. Backflow prevention circuits 11 and 12 are connected between the cathode of the Zener diode ZD0 and the input / output terminals P1 and P2, respectively.

 図1(B)に示した過渡電圧保護装置101BではMOS-FET Q1,Q2でそれぞれダイオードを構成していたが、本実施形態では、逆流防止回路11,12に、PN接合ダイオードD1,D2をそれぞれ設けている。その他の構成は第1の実施形態で示したとおりである。 In the transient voltage protection device 101B shown in FIG. 1B, the diodes are respectively constituted by the MOS-FETs Q1 and Q2, but in the present embodiment, the PN junction diodes D1 and D2 are provided in the backflow prevention circuits 11 and 12, respectively. Each is provided. Other configurations are as described in the first embodiment.

 本実施形態によれば、ダイオードD1,D2の構成が簡素化され、過渡電圧保護装置をより小型化できる。 According to the present embodiment, the configuration of the diodes D1 and D2 is simplified, and the size of the transient voltage protection device can be further reduced.

《第3の実施形態》
 第3の実施形態では、逆流防止回路の構成が第1の実施形態で示したものとは異なる過渡電圧保護装置の例を示す。
<< 3rd Embodiment >>
In the third embodiment, an example of a transient voltage protection device in which the configuration of the backflow prevention circuit is different from that shown in the first embodiment will be described.

 図6は第3の実施形態に係る過渡電圧保護装置103の回路図である。図6に示す過渡電圧保護装置103は、1つの共通端子Pcと、二つの入出力端子P1,P2と、第1端が共通端子Pcに接続された過渡電圧抑制素子10と、を備える。過渡電圧抑制素子10の第2端と入出力端子P1,P2との間には、逆流防止回路11,12がそれぞれ接続されている。 FIG. 6 is a circuit diagram of the transient voltage protection device 103 according to the third embodiment. The transient voltage protection device 103 illustrated in FIG. 6 includes one common terminal Pc, two input / output terminals P1 and P2, and the transient voltage suppression element 10 having a first end connected to the common terminal Pc. Backflow prevention circuits 11 and 12 are connected between the second end of the transient voltage suppression element 10 and the input / output terminals P1 and P2, respectively.

 本実施形態では、過渡電圧抑制素子10はツェナーダイオードZD0で構成されている。また、逆流防止回路11はツェナーダイオードZD1,ZD21で構成されている。同様に、逆流防止回路12はツェナーダイオードZD2,ZD22で構成されている。その他の構成は第1の実施形態で示したとおりである。 で は In the present embodiment, the transient voltage suppressing element 10 is constituted by the Zener diode ZD0. The backflow prevention circuit 11 includes zener diodes ZD1 and ZD21. Similarly, the backflow prevention circuit 12 includes zener diodes ZD2 and ZD22. Other configurations are as described in the first embodiment.

 ツェナーダイオードZD0,ZD1,ZD2,ZD21,ZD22のブレークダウン電圧は同じである。 The breakdown voltage of the Zener diodes ZD0, ZD1, ZD2, ZD21, ZD22 is the same.

 本実施形態のように、逆流防止回路11,12それぞれを、多段接続したツェナーダイオードで構成することで、逆流防止回路の実質的なブレークダウン電圧が高くなるため、ツェナーダイオードZD0が先にブレークダウンする。例えば、入出力端子P1にESDが印加されると、入出力端子P1→ツェナーダイオードZD1→ツェナーダイオードZD21→ツェナーダイオードZD0→共通端子Pcの経路でブレークダウン電流idが流れる。つまり、ツェナーダイオードZD0がブレークダウンすることで、入出力端子P1に繋がっている電子回路はESDによる過渡電圧から保護される。このとき、ツェナーダイオードZD22,ZD2はブレークダウンしない。このことで、ESDが入出力端子P2に印加されることはない。そのため、入出力端子P2に繋がっている電子回路もESDから保護される。 Since each of the backflow prevention circuits 11 and 12 is configured by a multi-stage connected zener diode as in the present embodiment, the substantial breakdown voltage of the backflow prevention circuit is increased, so that the zener diode ZD0 is first broken down. I do. For example, when ESD is applied to the input / output terminal P1, a breakdown current id flows through the path of the input / output terminal P1, the zener diode ZD1, the zener diode ZD21, the zener diode ZD0, and the common terminal Pc. That is, the breakdown of the Zener diode ZD0 protects the electronic circuit connected to the input / output terminal P1 from a transient voltage due to ESD. At this time, the Zener diodes ZD22 and ZD2 do not break down. Thus, the ESD is not applied to the input / output terminal P2. Therefore, the electronic circuit connected to the input / output terminal P2 is also protected from ESD.

 本実施形態によれば、過渡電圧抑制素子10を構成するツェナーダイオードZD0と、逆流防止回路を構成するツェナーダイオードZD1,ZD2,ZD21,ZD22とは、同じブレークダウン電圧のツェナーダイオードで構成できるので、ブレークダウン電圧を特別に調整することなく、同一のプロセスで容易に製造できる。 According to the present embodiment, the Zener diode ZD0 constituting the transient voltage suppression element 10 and the Zener diodes ZD1, ZD2, ZD21, ZD22 constituting the backflow prevention circuit can be constituted by Zener diodes having the same breakdown voltage. It can be easily manufactured in the same process without special adjustment of the breakdown voltage.

《第4の実施形態》
 第4の実施形態では、逆流防止回路の構成が第1の実施形態で示したものとは異なる過渡電圧保護装置の例を示す。
<< 4th Embodiment >>
In the fourth embodiment, an example of a transient voltage protection device in which the configuration of the backflow prevention circuit is different from that shown in the first embodiment will be described.

 図7は第4の実施形態に係る過渡電圧保護装置104の回路図である。図7に示す過渡電圧保護装置104は、1つの共通端子Pcと、二つの入出力端子P1,P2と、第1端が共通端子Pcに接続された過渡電圧抑制素子10と、を備える。過渡電圧抑制素子10の第2端と入出力端子P1,P2との間には、逆流防止回路11,12がそれぞれ接続されている。 FIG. 7 is a circuit diagram of the transient voltage protection device 104 according to the fourth embodiment. The transient voltage protection device 104 illustrated in FIG. 7 includes one common terminal Pc, two input / output terminals P1 and P2, and the transient voltage suppression element 10 having a first end connected to the common terminal Pc. Backflow prevention circuits 11 and 12 are connected between the second end of the transient voltage suppression element 10 and the input / output terminals P1 and P2, respectively.

 本実施形態では、過渡電圧抑制素子10はツェナーダイオードZD0で構成されている。また、逆流防止回路11はツェナーダイオードZD31で構成されている。同様に、逆流防止回路12はツェナーダイオードZD32で構成されている。その他の構成は第1の実施形態で示したとおりである。 で は In the present embodiment, the transient voltage suppressing element 10 is constituted by the Zener diode ZD0. The backflow prevention circuit 11 is configured by a Zener diode ZD31. Similarly, the backflow prevention circuit 12 includes a Zener diode ZD32. Other configurations are as described in the first embodiment.

 ここで、ツェナーダイオードZD0のブレークダウン電圧をVB0、ツェナーダイオードZD31のブレークダウン電圧をVB31、ツェナーダイオードZD32のブレークダウン電圧をVB32、でそれぞれ表すと、VB0<VB31,VB0<VB32、の関係にある。ツェナーダイオードZD0のブレークダウン電圧VB0は例えば7Vから8Vの範囲内の電圧であり、ツェナーダイオードZD31,ZD32のブレークダウン電圧VB31,VB32はいずれも例えば10Vから13Vの範囲内の電圧である。 Here, if the breakdown voltage of the Zener diode ZD0 is represented by VB0, the breakdown voltage of the Zener diode ZD31 is represented by VB31, and the breakdown voltage of the Zener diode ZD32 is represented by VB32, the relations are VB0 <VB31 and VB0 <VB32. . The breakdown voltage VB0 of the Zener diode ZD0 is, for example, a voltage in the range of 7V to 8V, and the breakdown voltages VB31, VB32 of the Zener diodes ZD31, ZD32 are all in the range of, for example, 10V to 13V.

 つまり、ツェナーダイオードZD0のカソード(過渡電圧抑制素子10の第2端)と入出力端子P1,P2との間に接続されたツェナーダイオードZD31,ZD32は、ブレークダウン電圧がツェナーダイオードZD0のブレークダウン電圧VB0より高く、かつツェナーダイオードZD0のブレークダウン電流が流れる方向を順方向とする素子である。 That is, the Zener diodes ZD31 and ZD32 connected between the cathode of the Zener diode ZD0 (the second end of the transient voltage suppression element 10) and the input / output terminals P1 and P2 have a breakdown voltage of the Zener diode ZD0. An element whose forward direction is higher than VB0 and in which the breakdown current of the Zener diode ZD0 flows.

 本実施形態によれば、例えば入出力端子P1に正のESDが印加されると、ツェナーダイオードZD0がブレークダウンすることで、入出力端子P1に繋がっている電子回路はESDによる過渡電圧から保護される。逆流防止回路12を構成するツェナーダイオードZD32のブレークダウン電圧は過渡電圧抑制素子10を構成するツェナーダイオードZD0より高いため、ツェナーダイオードZD0のブレークダウン時にも、ツェナーダイオードZD32はブレークダウンせず、ESDが入出力端子P2に印加されることはない。そのため、入出力端子P2に繋がっている電子回路もESDから保護される。入出力端子P2にESDが印加される場合、同様にしてツェナーダイオードZD0がブレークダウンすることで入出力端子P2に繋がっている電子回路はESDによる過渡電圧から保護され、ツェナーダイオードZD31はブレークダウンせず、ESDが入出力端子P1に印加されることはない。そのため、入出力端子P1に繋がっている電子回路もESDから保護される。 According to the present embodiment, for example, when a positive ESD is applied to the input / output terminal P1, the electronic circuit connected to the input / output terminal P1 is protected from a transient voltage due to the ESD by breaking down the zener diode ZD0. You. Since the breakdown voltage of the Zener diode ZD32 forming the backflow prevention circuit 12 is higher than the Zener diode ZD0 forming the transient voltage suppression element 10, even when the Zener diode ZD0 breaks down, the Zener diode ZD32 does not break down and the ESD is reduced. It is not applied to the input / output terminal P2. Therefore, the electronic circuit connected to the input / output terminal P2 is also protected from ESD. When the ESD is applied to the input / output terminal P2, the electronic circuit connected to the input / output terminal P2 is similarly protected from the transient voltage due to the ESD by breaking down the zener diode ZD0, and the Zener diode ZD31 is broken down. Therefore, the ESD is not applied to the input / output terminal P1. Therefore, the electronic circuit connected to the input / output terminal P1 is also protected from ESD.

《第5の実施形態》
 第5の実施形態では、逆流防止回路の構成が第1の実施形態で示したものとは異なる過渡電圧保護装置の例を示す。
<< 5th Embodiment >>
In the fifth embodiment, an example of a transient voltage protection device in which the configuration of the backflow prevention circuit is different from that shown in the first embodiment will be described.

 図8は第5の実施形態に係る過渡電圧保護装置105の回路図である。図8に示す過渡電圧保護装置105は、1つの共通端子Pcと、二つの入出力端子P1,P2と、第1端が共通端子Pcに接続された過渡電圧抑制素子10と、を備える。過渡電圧抑制素子10の第2端と入出力端子P1,P2との間には、逆流防止回路11,12がそれぞれ接続されている。 FIG. 8 is a circuit diagram of the transient voltage protection device 105 according to the fifth embodiment. The transient voltage protection device 105 illustrated in FIG. 8 includes one common terminal Pc, two input / output terminals P1 and P2, and the transient voltage suppression element 10 having a first end connected to the common terminal Pc. Backflow prevention circuits 11 and 12 are connected between the second end of the transient voltage suppression element 10 and the input / output terminals P1 and P2, respectively.

 本実施形態では、過渡電圧抑制素子10はツェナーダイオードZD0で構成されている。また、逆流防止回路11はツェナーダイオードZD1、MOS-FET Q1及びインダクタL1で構成されている。同様に、逆流防止回路12はツェナーダイオードZD2、MOS-FET Q2及びインダクタL2で構成されている。その他の構成は第1の実施形態で示したとおりである。 で は In the present embodiment, the transient voltage suppressing element 10 is constituted by the Zener diode ZD0. The backflow prevention circuit 11 includes a Zener diode ZD1, a MOS-FET Q1, and an inductor L1. Similarly, the backflow prevention circuit 12 includes a Zener diode ZD2, a MOS-FET Q2, and an inductor L2. Other configurations are as described in the first embodiment.

 本実施形態の過渡電圧保護装置105は、図1(B)に示した過渡電圧保護装置101BにインダクタL1,L2を付加したものである。インダクタL1は、入出力端子P1から共通端子Pcへ流れるブレークダウン電流の経路に直列接続されている。同様に、インダクタL2は、入出力端子P2から共通端子Pcへ流れるブレークダウン電流の経路に直列接続されている。 The transient voltage protection device 105 of the present embodiment is obtained by adding inductors L1 and L2 to the transient voltage protection device 101B shown in FIG. The inductor L1 is connected in series to a path of a breakdown current flowing from the input / output terminal P1 to the common terminal Pc. Similarly, the inductor L2 is connected in series to the path of the breakdown current flowing from the input / output terminal P2 to the common terminal Pc.

 例えば、入出力端子P1にESDが印加されると、MOS-FET Q1は順方向バイアスのダイオードとして作用し、入出力端子P1→ツェナーダイオードZD1→インダクタL1→MOS-FET Q1→ツェナーダイオードZD0→共通端子Pcの経路でブレークダウン電流idが流れる。このとき、逆流防止回路12内のMOS-FET Q2で構成されるダイオードには逆方向バイアス電圧が印加されるのでオフしたままである。 For example, when ESD is applied to the input / output terminal P1, the MOS-FET Q1 acts as a forward-biased diode, and the input / output terminal P1 → Zener diode ZD1 → Inductor L1 → MOS-FET Q1 → Zener diode ZD0 → common. The breakdown current id flows through the path of the terminal Pc. At this time, since the reverse bias voltage is applied to the diode constituted by the MOS-FET # Q2 in the backflow prevention circuit 12, the diode remains off.

 上記ブレークダウン電流の電流経路にインダクタL1が挿入されているため、このインダクタL1でブレークダウン電流の高周波成分が抑制され、入出力端子P1の印加電圧の高周波成分が抑制される。つまり、入出力端子P1にESDが印加されて、ツェナーダイオードZD0がブレークダウンするときの、入出力端子P1の過渡的な電圧変動が抑制される。また、ブレークダウン電流の経路中の各素子に流れる電流の上限が制限されて、それら素子の破壊が予防される。 (4) Since the inductor L1 is inserted in the current path of the breakdown current, the inductor L1 suppresses the high-frequency component of the breakdown current and suppresses the high-frequency component of the voltage applied to the input / output terminal P1. That is, the transient voltage fluctuation of the input / output terminal P1 when the ESD is applied to the input / output terminal P1 and the Zener diode ZD0 breaks down is suppressed. Further, the upper limit of the current flowing through each element in the path of the breakdown current is limited, and destruction of those elements is prevented.

 逆流防止回路12内のインダクタL2についても同様である。つまり、入出力端子P2にESDが印加されて、ツェナーダイオードZD0がブレークダウンするときの、入出力端子P2の過渡的な電圧変動が抑制される。また、ブレークダウン電流の経路中の各素子に流れる電流の上限が制限されて、それら素子の破壊が予防される。 同 様 The same applies to the inductor L2 in the backflow prevention circuit 12. That is, the transient voltage fluctuation of the input / output terminal P2 when the ESD is applied to the input / output terminal P2 and the Zener diode ZD0 breaks down is suppressed. Further, the upper limit of the current flowing through each element in the path of the breakdown current is limited, and destruction of those elements is prevented.

 なお、過渡電圧抑制素子10の第2端T2(ツェナーダイオードZD0のカソード)と共通接続点CNとの間にインダクタを挿入してもよい。その構成によれば、上記インダクタL1,L2は不要である。 Note that an inductor may be inserted between the second end T2 (the cathode of the Zener diode ZD0) of the transient voltage suppression element 10 and the common connection point CN. According to the configuration, the inductors L1 and L2 are unnecessary.

《第6の実施形態》
 第6の実施形態では、両極性の過渡電圧に対して保護する過渡電圧保護装置の例を示す。
<< Sixth Embodiment >>
In the sixth embodiment, an example of a transient voltage protection device that protects against a bipolar transient voltage will be described.

 図9は第6の実施形態に係る過渡電圧保護装置106Aの回路図である。図9に示す過渡電圧保護装置106Aは、共通端子Pcと、入出力端子P1,P2と、第1端T1が共通端子Pcに接続された過渡電圧抑制素子10p,10nと、を備える。過渡電圧抑制素子10pの第2端と入出力端子P1,P2との間には、逆流防止回路11p,12pがそれぞれ接続されている。同様に、過渡電圧抑制素子10nの第2端と入出力端子P1,P2との間には、逆流防止回路11n,12nがそれぞれ接続されている。 FIG. 9 is a circuit diagram of a transient voltage protection device 106A according to the sixth embodiment. The transient voltage protection device 106A illustrated in FIG. 9 includes a common terminal Pc, input / output terminals P1 and P2, and transient voltage suppression elements 10p and 10n whose first terminals T1 are connected to the common terminal Pc. Backflow prevention circuits 11p and 12p are connected between the second end of the transient voltage suppression element 10p and the input / output terminals P1 and P2, respectively. Similarly, backflow prevention circuits 11n and 12n are connected between the second end of the transient voltage suppression element 10n and the input / output terminals P1 and P2, respectively.

 図9において、過渡電圧抑制素子10p及び逆流防止回路11p,12pによって、正の過渡電圧に対する過渡電圧保護用回路が構成されていて、過渡電圧抑制素子10n及び逆流防止回路11n,12nによって、負の過渡電圧に対する過渡電圧保護用回路が構成されている。過渡電圧抑制素子10p及び逆流防止回路11p,12pによる過渡電圧保護用回路は図1(B)に示した過渡電圧保護装置の構成と同じである。 In FIG. 9, the transient voltage suppression element 10p and the backflow prevention circuits 11p and 12p constitute a transient voltage protection circuit for a positive transient voltage. The transient voltage suppression element 10n and the backflow prevention circuits 11n and 12n provide a negative voltage. A transient voltage protection circuit for the transient voltage is configured. The transient voltage protection circuit including the transient voltage suppression element 10p and the backflow prevention circuits 11p and 12p has the same configuration as that of the transient voltage protection device shown in FIG.

 過渡電圧抑制素子10pはツェナーダイオードZD0pで構成されている。同様に、過渡電圧抑制素子10nはツェナーダイオードZD0nで構成されている。逆流防止回路11pはツェナーダイオードZD1p及びMOS-FET Q1pで構成されていて、逆流防止回路12pはツェナーダイオードZD2p及びMOS-FET Q2pで構成されている。同様に、逆流防止回路11nはツェナーダイオードZD1n及びMOS-FET Q1nで構成されていて、逆流防止回路12nはツェナーダイオードZD2n及びMOS-FET Q2nで構成されている。 The transient voltage suppressing element 10p is constituted by a Zener diode ZD0p. Similarly, the transient voltage suppression element 10n is configured by a Zener diode ZD0n. The backflow prevention circuit 11p includes a zener diode ZD1p and a MOS-FET $ Q1p, and the backflow prevention circuit 12p includes a zener diode ZD2p and a MOS-FET $ Q2p. Similarly, the backflow prevention circuit 11n includes a zener diode ZD1n and a MOS-FET $ Q1n, and the backflow prevention circuit 12n includes a zener diode ZD2n and a MOS-FET $ Q2n.

 上記正の過渡電圧保護用回路と負の過渡電圧保護用回路とは、各ツェナーダイオードの方向、MOS-FETの方向が逆になっているだけであり、その他の回路構成は同じである。 The positive transient voltage protection circuit and the negative transient voltage protection circuit have the same circuit configuration except that the direction of each Zener diode and the direction of the MOS-FET are reversed.

 例えば、入出力端子P1に正のESDが印加されると、ツェナーダイオードZD1pに順方向バイアス電圧が印加される。また、ゲートGとドレインDとが接続されたMOS-FET Q1pで構成されるダイオードに順方向バイアス電圧が印加される。したがって、ツェナーダイオードZD0pのアノードに対するカソードの電位がブレークダウン電圧を超えて、ツェナーダイオードZD0pはブレークダウンする。これにより、入出力端子P1→逆流防止回路11p→過渡電圧抑制素子10p→共通端子Pcの経路で電流idpが流れる。これにより、入出力端子P1は正のESDから保護される。 {For example, when a positive ESD is applied to the input / output terminal P1, a forward bias voltage is applied to the Zener diode ZD1p. In addition, a forward bias voltage is applied to a diode composed of a MOS-FET # Q1p in which the gate G and the drain D are connected. Therefore, the potential of the cathode of the Zener diode ZD0p with respect to the anode exceeds the breakdown voltage, and the Zener diode ZD0p breaks down. As a result, the current idp flows through the path of the input / output terminal P1, the backflow prevention circuit 11p, the transient voltage suppressing element 10p, and the common terminal Pc. As a result, the input / output terminal P1 is protected from positive ESD.

 また、例えば、入出力端子P1に負のESDが印加されると、ツェナーダイオードZD1nに順方向バイアス電圧が印加される。また、ゲートGとドレインDとが接続されたMOS-FET Q1nで構成されるダイオードに順方向バイアス電圧が印加される。したがって、ツェナーダイオードZD0nのアノードに対するカソードの電位がブレークダウン電圧を超えて、ツェナーダイオードZD0nはブレークダウンする。これにより、共通端子Pc→過渡電圧抑制素子10n→逆流防止回路11n→入出力端子P1の経路で電流idnが流れる。これにより、入出力端子P1は負のESDから保護される。 (4) For example, when a negative ESD is applied to the input / output terminal P1, a forward bias voltage is applied to the Zener diode ZD1n. Further, a forward bias voltage is applied to a diode composed of a MOS-FET # Q1n in which the gate G and the drain D are connected. Therefore, the potential of the cathode of the Zener diode ZD0n with respect to the anode exceeds the breakdown voltage, and the Zener diode ZD0n breaks down. As a result, the current idn flows through the path of the common terminal Pc → transient voltage suppressing element 10n → backflow prevention circuit 11n → input / output terminal P1. Thus, the input / output terminal P1 is protected from negative ESD.

 上述の例は、入出力端子P1にESDが印加される場合であるが、入出力端子P2に正又は負のESDが印加される場合も同様である。例えば、入出力端子P2に正のESDが印加されると、入出力端子P2→逆流防止回路12p→過渡電圧抑制素子10p→共通端子Pcの経路でブレークダウン電流が流れる。これにより、入出力端子P2は正のESDから保護される。また、例えば、入出力端子P2に負のESDが印加されると、共通端子Pc→過渡電圧抑制素子10n→逆流防止回路12n→入出力端子P2の経路でブレークダウン電流が流れる。これにより、入出力端子P2は負のESDから保護される。 The above example is a case where ESD is applied to the input / output terminal P1, but the same applies to a case where positive or negative ESD is applied to the input / output terminal P2. For example, when a positive ESD is applied to the input / output terminal P2, a breakdown current flows through the path of the input / output terminal P2 → the backflow prevention circuit 12p → the transient voltage suppressing element 10p → the common terminal Pc. As a result, the input / output terminal P2 is protected from positive ESD. Further, for example, when a negative ESD is applied to the input / output terminal P2, a breakdown current flows through the path of the common terminal Pc → the transient voltage suppressing element 10n → the backflow prevention circuit 12n → the input / output terminal P2. Thereby, the input / output terminal P2 is protected from negative ESD.

 図10は本実施形態に係る別の過渡電圧保護装置106Bの回路図である。この過渡電圧保護装置106Bは三つの入出力端子P1,P2,P3について過渡電圧保護を行う装置である。図10に示す過渡電圧保護装置106Bは、1つの共通端子Pcと、三つの入出力端子P1,P2,P3と、ツェナーダイオードZD0p,ZD0n,ZD31p,ZD31n,ZD32p,ZD32n,ZD33p,ZD33nと、を備える。ツェナーダイオードZD0pは正の過渡電圧保護用の過渡電圧抑制素子であり、ツェナーダイオードZD0nは負の過渡電圧保護用の過渡電圧抑制素子である。また、ツェナーダイオードZD31p,ZD32p,ZD33pは正の過渡電圧保護用の逆流防止回路を構成する素子であり、ツェナーダイオードZD31n,ZD32n,ZD33nは負の過渡電圧保護用の逆流防止回路を構成する素子である。 FIG. 10 is a circuit diagram of another transient voltage protection device 106B according to the present embodiment. This transient voltage protection device 106B is a device that performs transient voltage protection for three input / output terminals P1, P2, and P3. The transient voltage protection device 106B illustrated in FIG. 10 includes one common terminal Pc, three input / output terminals P1, P2, and P3, and zener diodes ZD0p, ZD0n, ZD31p, ZD31n, ZD32p, ZD32n, ZD33p, and ZD33n. Prepare. The Zener diode ZD0p is a transient voltage suppression element for positive transient voltage protection, and the Zener diode ZD0n is a transient voltage suppression element for negative transient voltage protection. The Zener diodes ZD31p, ZD32p, and ZD33p are elements that form a backflow prevention circuit for positive transient voltage protection, and the Zener diodes ZD31n, ZD32n, and ZD33n are elements that form a backflow prevention circuit for negative transient voltage protection. is there.

 ここで、ツェナーダイオードZD0pのブレークダウン電圧をVB0p、ツェナーダイオードZD31pのブレークダウン電圧をVB31p、ツェナーダイオードZD32pのブレークダウン電圧をVB32p、ツェナーダイオードZD33pのブレークダウン電圧をVB33p、でそれぞれ表すと、
 VB0p<VB31p
 VB0p<VB32p
 VB0p<VB33p
 である。また、ツェナーダイオードZD0nのブレークダウン電圧をVB0n、ツェナーダイオードZD31nのブレークダウン電圧をVB31n、ツェナーダイオードZD32nのブレークダウン電圧をVB32n、ツェナーダイオードZD33nのブレークダウン電圧をVB33n、でそれぞれ表すと、
 |VB0n|<|VB31n|
 |VB0n|<|VB32n|
 |VB0n|<|VB33n|
 である。
Here, the breakdown voltage of the Zener diode ZD0p is represented by VB0p, the breakdown voltage of the Zener diode ZD31p is represented by VB31p, the breakdown voltage of the Zener diode ZD32p is represented by VB32p, and the breakdown voltage of the Zener diode ZD33p is represented by VB33p, respectively.
VB0p <VB31p
VB0p <VB32p
VB0p <VB33p
It is. Also, when the breakdown voltage of the Zener diode ZD0n is represented by VB0n, the breakdown voltage of the Zener diode ZD31n is represented by VB31n, the breakdown voltage of the Zener diode ZD32n is represented by VB32n, and the breakdown voltage of the Zener diode ZD33n is represented by VB33n, respectively.
| VB0n | <| VB31n |
| VB0n | <| VB32n |
| VB0n | <| VB33n |
It is.

 本実施形態によれば、例えば入出力端子P1に正のESDが印加されると、ツェナーダイオードZD0pがブレークダウンすることで、入出力端子P1に繋がっている電子回路は正のESDによる過渡電圧から保護される。また、例えば入出力端子P1に負のESDが印加されると、ツェナーダイオードZD0nがブレークダウンすることで、入出力端子P1に繋がっている電子回路は負のESDによる過渡電圧から保護される。入出力端子P2,P3についても同様に、正負の過渡電圧から保護される。 According to the present embodiment, for example, when a positive ESD is applied to the input / output terminal P1, the electronic circuit connected to the input / output terminal P1 breaks down due to the breakdown of the Zener diode ZD0p. Protected. Further, for example, when a negative ESD is applied to the input / output terminal P1, the Zener diode ZD0n breaks down, and the electronic circuit connected to the input / output terminal P1 is protected from a transient voltage due to the negative ESD. Similarly, the input / output terminals P2 and P3 are protected from positive and negative transient voltages.

 以上に示した実施形態では、過渡電圧抑制素子10,10p,10nの第1端を共通端子Pcに直接接続した例を示したが、過渡電圧抑制素子10,10p,10nの第1端は共通端子Pcに間接的に接続されていてもよい。例えば、過渡電圧抑制素子10,10p,10nの第1端と共通端子Pcとの間にインダクタが挿入されていてもよい。 In the embodiment described above, an example is shown in which the first ends of the transient voltage suppression elements 10, 10p, and 10n are directly connected to the common terminal Pc. However, the first ends of the transient voltage suppression elements 10, 10p, and 10n are common. It may be indirectly connected to the terminal Pc. For example, an inductor may be inserted between the first terminals of the transient voltage suppression elements 10, 10p, and 10n and the common terminal Pc.

 さらに、共通端子Pcをグランドに直接接続せず、間接的に接続してもよい。例えば、共通端子Pcとグランドとの間に、インダクタを挿入してもよい。その構成によれば、過渡電圧抑制素子のブレークダウン電流の高周波成分が抑制され、ブレークダウン電流の高周波成分が抑制される。これにより、入出力端子(P1,P2等)の過渡的な電圧変動が抑制される。また、ブレークダウン電流の経路中の各素子に流れる電流の上限が制限されて、それら素子が破壊から保護される。 (4) The common terminal Pc may not be directly connected to the ground but may be connected indirectly. For example, an inductor may be inserted between the common terminal Pc and the ground. According to this configuration, the high-frequency component of the breakdown current of the transient voltage suppression element is suppressed, and the high-frequency component of the breakdown current is suppressed. Thereby, transient voltage fluctuations of the input / output terminals (P1, P2, etc.) are suppressed. Further, the upper limit of the current flowing through each element in the path of the breakdown current is limited, and the elements are protected from destruction.

 最後に、上述の実施形態の説明は、すべての点で例示であって、制限的なものではない。当業者にとって変形及び変更が適宜可能である。本発明の範囲は、上述の実施形態ではなく、特許請求の範囲によって示される。さらに、本発明の範囲には、特許請求の範囲内と均等の範囲内での実施形態からの変更が含まれる。 Lastly, the description of the above-described embodiment is illustrative in all aspects and is not restrictive. Modifications and changes can be made by those skilled in the art as appropriate. The scope of the present invention is defined by the terms of the claims, rather than the embodiments described above. Further, the scope of the present invention includes modifications from the embodiments within the scope equivalent to the scope of the claims.

CN…共通接続点
D…ドレイン
D1,D2…ダイオード
G…ゲート
id,idp,idn…ブレークダウン電流
L1,L2…インダクタ
P1,P2,P3…入出力端子
Pc…共通端子
Q1,Q2…MOS-FET
S…ソース
T1…第1端
T2…第2端
ZD0,ZD1,ZD2,ZD3…ツェナーダイオード
ZD0n,ZD1n,ZD2n…ツェナーダイオード
ZD0p,ZD1p,ZD2p…ツェナーダイオード
ZD21,ZD22…ツェナーダイオード
ZD31,ZD32…ツェナーダイオード
ZD31n,ZD32n,ZD33n…ツェナーダイオード
ZD31p,ZD32p,ZD33p…ツェナーダイオード
10,10p,10n…過渡電圧抑制素子
11,12…逆流防止回路
11n,12n…逆流防止回路
11p,12p…逆流防止回路
51…第1電子回路
52…第2電子回路
101A,101B,101C…過渡電圧保護装置
102,103,104,105…過渡電圧保護装置
106A,106B…過渡電圧保護装置
CN: common connection point D: drain D1, D2: diode G: gate id, idp, idn: breakdown current L1, L2: inductor P1, P2, P3: input / output terminal Pc: common terminal Q1, Q2: MOS-FET
S Source T1 First end T2 Second end ZD0, ZD1, ZD2, ZD3 Zener diodes ZD0n, ZD1n, ZD2n Zener diodes ZD0p, ZD1p, ZD2p Zener diodes ZD21, ZD22 Zener diodes ZD31, ZD32 Zener Diodes ZD31n, ZD32n, ZD33n Zener diodes ZD31p, ZD32p, ZD33p Zener diodes 10, 10p, 10n Transient voltage suppressing elements 11, 12 Backflow prevention circuits 11n, 12n Backflow prevention circuits 11p, 12p Backflow prevention circuits 51 1st electronic circuit 52 ... 2nd electronic circuit 101A, 101B, 101C ... transient voltage protection device 102,103,104,105 ... transient voltage protection device 106A, 106B ... transient voltage protection device

Claims (6)

 1つの共通端子と、複数の入出力端子と、第1端が前記共通端子に直接的に又は間接的に接続された過渡電圧抑制素子と、を備え、
 前記過渡電圧抑制素子の第2端と前記複数の入出力端子との間に、ブレークダウン電圧が前記過渡電圧抑制素子のブレークダウン電圧より高く、かつ前記過渡電圧抑制素子のブレークダウン電流が流れる方向を順方向とする、逆流防止回路が接続された、
 過渡電圧保護装置。
A single common terminal, a plurality of input / output terminals, and a transient voltage suppressing element having a first end connected directly or indirectly to the common terminal;
A direction in which a breakdown voltage is higher than a breakdown voltage of the transient voltage suppression element and a breakdown current of the transient voltage suppression element flows between a second end of the transient voltage suppression element and the plurality of input / output terminals. The forward direction, the backflow prevention circuit is connected,
Transient voltage protection device.
 前記過渡電圧抑制素子は、前記入出力端子に接続される回路を保護すべき電圧でブレークダウンするツェナーダイオードである、請求項1に記載の過渡電圧保護装置。 The transient voltage protection device according to claim 1, wherein the transient voltage suppression element is a Zener diode that breaks down at a voltage to protect a circuit connected to the input / output terminal.  前記逆流防止回路は、ゲートとドレインとが接続されたMOS-FETを含む、請求項1又は2に記載の過渡電圧保護装置。 The transient voltage protection device according to claim 1, wherein the backflow prevention circuit includes a MOS-FET having a gate and a drain connected to each other.  前記逆流防止回路は、P層とN層との接合部に形成されるPN接合ダイオードを含む、請求項1又は2に記載の過渡電圧保護装置。 3. The transient voltage protection device according to claim 1, wherein the backflow prevention circuit includes a PN junction diode formed at a junction between the P layer and the N layer.  前記逆流防止回路はツェナーダイオードを含む、請求項1から4のいずれかに記載の過渡電圧保護装置。 The transient voltage protection device according to any one of claims 1 to 4, wherein the backflow prevention circuit includes a Zener diode.  前記逆流防止回路は、前記ブレークダウン電流が流れる経路に直列接続されたインダクタをさらに備える、請求項1から5のいずれかに記載の過渡電圧保護装置。 6. The transient voltage protection device according to claim 1, wherein the backflow prevention circuit further includes an inductor connected in series to a path through which the breakdown current flows. 7.
PCT/JP2019/014600 2018-09-05 2019-04-02 Transient voltage protection device WO2020049787A1 (en)

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JP2012182381A (en) * 2011-03-02 2012-09-20 Panasonic Corp Semiconductor device
US20150084162A1 (en) * 2013-09-24 2015-03-26 Semiconductor Components Industries, Llc Electronic device including a diode and a process of forming the same
US20160141429A1 (en) * 2014-11-18 2016-05-19 Magnachip Semiconductor, Ltd. Electrostatic discharge device and method of fabricating the same
US20170084601A1 (en) * 2015-09-22 2017-03-23 Silergy Semiconductor Technology (Hangzhou) Ltd Transient voltage suppressor and manufacture method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012182381A (en) * 2011-03-02 2012-09-20 Panasonic Corp Semiconductor device
US20150084162A1 (en) * 2013-09-24 2015-03-26 Semiconductor Components Industries, Llc Electronic device including a diode and a process of forming the same
US20160141429A1 (en) * 2014-11-18 2016-05-19 Magnachip Semiconductor, Ltd. Electrostatic discharge device and method of fabricating the same
US20170084601A1 (en) * 2015-09-22 2017-03-23 Silergy Semiconductor Technology (Hangzhou) Ltd Transient voltage suppressor and manufacture method thereof

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